[deliverable/linux.git] / drivers / gpu / drm / gma500 / intel_gmbus.c

/*
 * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
 * Copyright © 2006-2008,2010 Intel Corporation
 *   Jesse Barnes <jesse.barnes@intel.com>
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice (including the next
 * paragraph) shall be included in all copies or substantial portions of the
 * Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
 * DEALINGS IN THE SOFTWARE.
 *
 * Authors:
 *	Eric Anholt <eric@anholt.net>
 *	Chris Wilson <chris@chris-wilson.co.uk>
 */
#include <linux/module.h>
#include <linux/i2c.h>
#include <linux/i2c-algo-bit.h>
#include "drmP.h"
#include "drm.h"
#include "psb_intel_drv.h"
#include "gma_drm.h"
#include "psb_drv.h"
#include "psb_intel_reg.h"

#define _wait_for(COND, MS, W) ({ \
	unsigned long timeout__ = jiffies + msecs_to_jiffies(MS);	\
	int ret__ = 0;							\
	while (! (COND)) {						\
		if (time_after(jiffies, timeout__)) {			\
			ret__ = -ETIMEDOUT;				\
			break;						\
		}							\
		if (W && !(in_atomic() || in_dbg_master())) msleep(W);	\
	}								\
	ret__;								\
})

#define wait_for(COND, MS) _wait_for(COND, MS, 1)
#define wait_for_atomic(COND, MS) _wait_for(COND, MS, 0)

/* Intel GPIO access functions */

#define I2C_RISEFALL_TIME 20

static inline struct intel_gmbus *
to_intel_gmbus(struct i2c_adapter *i2c)
{
	return container_of(i2c, struct intel_gmbus, adapter);
}

struct intel_gpio {
	struct i2c_adapter adapter;
	struct i2c_algo_bit_data algo;
	struct drm_psb_private *dev_priv;
	u32 reg;
};

void
gma_intel_i2c_reset(struct drm_device *dev)
{
	REG_WRITE(GMBUS0, 0);
}

static void intel_i2c_quirk_set(struct drm_psb_private *dev_priv, bool enable)
{
	/* When using bit bashing for I2C, this bit needs to be set to 1 */
	/* FIXME: We are never Pineview, right?

	u32 val;

	if (!IS_PINEVIEW(dev_priv->dev))
		return;

	val = REG_READ(DSPCLK_GATE_D);
	if (enable)
		val |= DPCUNIT_CLOCK_GATE_DISABLE;
	else
		val &= ~DPCUNIT_CLOCK_GATE_DISABLE;
	REG_WRITE(DSPCLK_GATE_D, val);

	return;
	*/
}

static u32 get_reserved(struct intel_gpio *gpio)
{
	struct drm_psb_private *dev_priv = gpio->dev_priv;
	struct drm_device *dev = dev_priv->dev;
	u32 reserved = 0;

	/* On most chips, these bits must be preserved in software. */
	reserved = REG_READ(gpio->reg) &
				     (GPIO_DATA_PULLUP_DISABLE |
				      GPIO_CLOCK_PULLUP_DISABLE);

	return reserved;
}

static int get_clock(void *data)
{
	struct intel_gpio *gpio = data;
	struct drm_psb_private *dev_priv = gpio->dev_priv;
	struct drm_device *dev = dev_priv->dev;
	u32 reserved = get_reserved(gpio);
	REG_WRITE(gpio->reg, reserved | GPIO_CLOCK_DIR_MASK);
	REG_WRITE(gpio->reg, reserved);
	return (REG_READ(gpio->reg) & GPIO_CLOCK_VAL_IN) != 0;
}

static int get_data(void *data)
{
	struct intel_gpio *gpio = data;
	struct drm_psb_private *dev_priv = gpio->dev_priv;
	struct drm_device *dev = dev_priv->dev;
	u32 reserved = get_reserved(gpio);
	REG_WRITE(gpio->reg, reserved | GPIO_DATA_DIR_MASK);
	REG_WRITE(gpio->reg, reserved);
	return (REG_READ(gpio->reg) & GPIO_DATA_VAL_IN) != 0;
}

static void set_clock(void *data, int state_high)
{
	struct intel_gpio *gpio = data;
	struct drm_psb_private *dev_priv = gpio->dev_priv;
	struct drm_device *dev = dev_priv->dev;
	u32 reserved = get_reserved(gpio);
	u32 clock_bits;

	if (state_high)
		clock_bits = GPIO_CLOCK_DIR_IN | GPIO_CLOCK_DIR_MASK;
	else
		clock_bits = GPIO_CLOCK_DIR_OUT | GPIO_CLOCK_DIR_MASK |
			GPIO_CLOCK_VAL_MASK;

	REG_WRITE(gpio->reg, reserved | clock_bits);
	REG_READ(gpio->reg); /* Posting */
}

static void set_data(void *data, int state_high)
{
	struct intel_gpio *gpio = data;
	struct drm_psb_private *dev_priv = gpio->dev_priv;
	struct drm_device *dev = dev_priv->dev;
	u32 reserved = get_reserved(gpio);
	u32 data_bits;

	if (state_high)
		data_bits = GPIO_DATA_DIR_IN | GPIO_DATA_DIR_MASK;
	else
		data_bits = GPIO_DATA_DIR_OUT | GPIO_DATA_DIR_MASK |
			GPIO_DATA_VAL_MASK;

	REG_WRITE(gpio->reg, reserved | data_bits);
	REG_READ(gpio->reg);
}

static struct i2c_adapter *
intel_gpio_create(struct drm_psb_private *dev_priv, u32 pin)
{
	static const int map_pin_to_reg[] = {
		0,
		GPIOB,
		GPIOA,
		GPIOC,
		GPIOD,
		GPIOE,
		0,
		GPIOF,
	};
	struct intel_gpio *gpio;

	if (pin >= ARRAY_SIZE(map_pin_to_reg) || !map_pin_to_reg[pin])
		return NULL;

	gpio = kzalloc(sizeof(struct intel_gpio), GFP_KERNEL);
	if (gpio == NULL)
		return NULL;

	gpio->reg = map_pin_to_reg[pin];
	gpio->dev_priv = dev_priv;

	snprintf(gpio->adapter.name, sizeof(gpio->adapter.name),
		 "gma500 GPIO%c", "?BACDE?F"[pin]);
	gpio->adapter.owner = THIS_MODULE;
	gpio->adapter.algo_data	= &gpio->algo;
	gpio->adapter.dev.parent = &dev_priv->dev->pdev->dev;
	gpio->algo.setsda = set_data;
	gpio->algo.setscl = set_clock;
	gpio->algo.getsda = get_data;
	gpio->algo.getscl = get_clock;
	gpio->algo.udelay = I2C_RISEFALL_TIME;
	gpio->algo.timeout = usecs_to_jiffies(2200);
	gpio->algo.data = gpio;

	if (i2c_bit_add_bus(&gpio->adapter))
		goto out_free;

	return &gpio->adapter;

out_free:
	kfree(gpio);
	return NULL;
}

static int
intel_i2c_quirk_xfer(struct drm_psb_private *dev_priv,
		     struct i2c_adapter *adapter,
		     struct i2c_msg *msgs,
		     int num)
{
	struct intel_gpio *gpio = container_of(adapter,
					       struct intel_gpio,
					       adapter);
	int ret;

	gma_intel_i2c_reset(dev_priv->dev);

	intel_i2c_quirk_set(dev_priv, true);
	set_data(gpio, 1);
	set_clock(gpio, 1);
	udelay(I2C_RISEFALL_TIME);

	ret = adapter->algo->master_xfer(adapter, msgs, num);

	set_data(gpio, 1);
	set_clock(gpio, 1);
	intel_i2c_quirk_set(dev_priv, false);

	return ret;
}

static int
gmbus_xfer(struct i2c_adapter *adapter,
	   struct i2c_msg *msgs,
	   int num)
{
	struct intel_gmbus *bus = container_of(adapter,
					       struct intel_gmbus,
					       adapter);
	struct drm_psb_private *dev_priv = adapter->algo_data;
	struct drm_device *dev = dev_priv->dev;
	int i, reg_offset;

	if (bus->force_bit)
		return intel_i2c_quirk_xfer(dev_priv,
					    bus->force_bit, msgs, num);

	reg_offset = 0;

	REG_WRITE(GMBUS0 + reg_offset, bus->reg0);

	for (i = 0; i < num; i++) {
		u16 len = msgs[i].len;
		u8 *buf = msgs[i].buf;

		if (msgs[i].flags & I2C_M_RD) {
			REG_WRITE(GMBUS1 + reg_offset,
				   GMBUS_CYCLE_WAIT | (i + 1 == num ? GMBUS_CYCLE_STOP : 0) |
				   (len << GMBUS_BYTE_COUNT_SHIFT) |
				   (msgs[i].addr << GMBUS_SLAVE_ADDR_SHIFT) |
				   GMBUS_SLAVE_READ | GMBUS_SW_RDY);
			REG_READ(GMBUS2+reg_offset);
			do {
				u32 val, loop = 0;

				if (wait_for(REG_READ(GMBUS2 + reg_offset) & (GMBUS_SATOER | GMBUS_HW_RDY), 50))
					goto timeout;
				if (REG_READ(GMBUS2 + reg_offset) & GMBUS_SATOER)
					goto clear_err;

				val = REG_READ(GMBUS3 + reg_offset);
				do {
					*buf++ = val & 0xff;
					val >>= 8;
				} while (--len && ++loop < 4);
			} while (len);
		} else {
			u32 val, loop;

			val = loop = 0;
			do {
				val |= *buf++ << (8 * loop);
			} while (--len && ++loop < 4);

			REG_WRITE(GMBUS3 + reg_offset, val);
			REG_WRITE(GMBUS1 + reg_offset,
				   (i + 1 == num ? GMBUS_CYCLE_STOP : GMBUS_CYCLE_WAIT) |
				   (msgs[i].len << GMBUS_BYTE_COUNT_SHIFT) |
				   (msgs[i].addr << GMBUS_SLAVE_ADDR_SHIFT) |
				   GMBUS_SLAVE_WRITE | GMBUS_SW_RDY);
			REG_READ(GMBUS2+reg_offset);

			while (len) {
				if (wait_for(REG_READ(GMBUS2 + reg_offset) & (GMBUS_SATOER | GMBUS_HW_RDY), 50))
					goto timeout;
				if (REG_READ(GMBUS2 + reg_offset) & GMBUS_SATOER)
					goto clear_err;

				val = loop = 0;
				do {
					val |= *buf++ << (8 * loop);
				} while (--len && ++loop < 4);

				REG_WRITE(GMBUS3 + reg_offset, val);
				REG_READ(GMBUS2+reg_offset);
			}
		}

		if (i + 1 < num && wait_for(REG_READ(GMBUS2 + reg_offset) & (GMBUS_SATOER | GMBUS_HW_WAIT_PHASE), 50))
			goto timeout;
		if (REG_READ(GMBUS2 + reg_offset) & GMBUS_SATOER)
			goto clear_err;
	}

	goto done;

clear_err:
	/* Toggle the Software Clear Interrupt bit. This has the effect
	 * of resetting the GMBUS controller and so clearing the
	 * BUS_ERROR raised by the slave's NAK.
	 */
	REG_WRITE(GMBUS1 + reg_offset, GMBUS_SW_CLR_INT);
	REG_WRITE(GMBUS1 + reg_offset, 0);

done:
	/* Mark the GMBUS interface as disabled. We will re-enable it at the
	 * start of the next xfer, till then let it sleep.
	 */
	REG_WRITE(GMBUS0 + reg_offset, 0);
	return i;

timeout:
	DRM_INFO("GMBUS timed out, falling back to bit banging on pin %d [%s]\n",
		 bus->reg0 & 0xff, bus->adapter.name);
	REG_WRITE(GMBUS0 + reg_offset, 0);

	/* Hardware may not support GMBUS over these pins? Try GPIO bitbanging instead. */
	bus->force_bit = intel_gpio_create(dev_priv, bus->reg0 & 0xff);
	if (!bus->force_bit)
		return -ENOMEM;

	return intel_i2c_quirk_xfer(dev_priv, bus->force_bit, msgs, num);
}

static u32 gmbus_func(struct i2c_adapter *adapter)
{
	struct intel_gmbus *bus = container_of(adapter,
					       struct intel_gmbus,
					       adapter);

	if (bus->force_bit)
		bus->force_bit->algo->functionality(bus->force_bit);

	return (I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL |
		/* I2C_FUNC_10BIT_ADDR | */
		I2C_FUNC_SMBUS_READ_BLOCK_DATA |
		I2C_FUNC_SMBUS_BLOCK_PROC_CALL);
}

static const struct i2c_algorithm gmbus_algorithm = {
	.master_xfer	= gmbus_xfer,
	.functionality	= gmbus_func
};

/**
 * intel_gmbus_setup - instantiate all Intel i2c GMBuses
 * @dev: DRM device
 */
int gma_intel_setup_gmbus(struct drm_device *dev)
{
	static const char *names[GMBUS_NUM_PORTS] = {
		"disabled",
		"ssc",
		"vga",
		"panel",
		"dpc",
		"dpb",
		"reserved",
		"dpd",
	};
	struct drm_psb_private *dev_priv = dev->dev_private;
	int ret, i;

	dev_priv->gmbus = kcalloc(sizeof(struct intel_gmbus), GMBUS_NUM_PORTS,
				  GFP_KERNEL);
	if (dev_priv->gmbus == NULL)
		return -ENOMEM;

	for (i = 0; i < GMBUS_NUM_PORTS; i++) {
		struct intel_gmbus *bus = &dev_priv->gmbus[i];

		bus->adapter.owner = THIS_MODULE;
		bus->adapter.class = I2C_CLASS_DDC;
		snprintf(bus->adapter.name,
			 sizeof(bus->adapter.name),
			 "gma500 gmbus %s",
			 names[i]);

		bus->adapter.dev.parent = &dev->pdev->dev;
		bus->adapter.algo_data	= dev_priv;

		bus->adapter.algo = &gmbus_algorithm;
		ret = i2c_add_adapter(&bus->adapter);
		if (ret)
			goto err;

		/* By default use a conservative clock rate */
		bus->reg0 = i | GMBUS_RATE_100KHZ;

		/* XXX force bit banging until GMBUS is fully debugged */
		bus->force_bit = intel_gpio_create(dev_priv, i);
	}

	gma_intel_i2c_reset(dev_priv->dev);

	return 0;

err:
	while (--i) {
		struct intel_gmbus *bus = &dev_priv->gmbus[i];
		i2c_del_adapter(&bus->adapter);
	}
	kfree(dev_priv->gmbus);
	dev_priv->gmbus = NULL;
	return ret;
}

void gma_intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed)
{
	struct intel_gmbus *bus = to_intel_gmbus(adapter);

	/* speed:
	 * 0x0 = 100 KHz
	 * 0x1 = 50 KHz
	 * 0x2 = 400 KHz
	 * 0x3 = 1000 Khz
	 */
	bus->reg0 = (bus->reg0 & ~(0x3 << 8)) | (speed << 8);
}

void gma_intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit)
{
	struct intel_gmbus *bus = to_intel_gmbus(adapter);

	if (force_bit) {
		if (bus->force_bit == NULL) {
			struct drm_psb_private *dev_priv = adapter->algo_data;
			bus->force_bit = intel_gpio_create(dev_priv,
							   bus->reg0 & 0xff);
		}
	} else {
		if (bus->force_bit) {
			i2c_del_adapter(bus->force_bit);
			kfree(bus->force_bit);
			bus->force_bit = NULL;
		}
	}
}

void gma_intel_teardown_gmbus(struct drm_device *dev)
{
	struct drm_psb_private *dev_priv = dev->dev_private;
	int i;

	if (dev_priv->gmbus == NULL)
		return;

	for (i = 0; i < GMBUS_NUM_PORTS; i++) {
		struct intel_gmbus *bus = &dev_priv->gmbus[i];
		if (bus->force_bit) {
			i2c_del_adapter(bus->force_bit);
			kfree(bus->force_bit);
		}
		i2c_del_adapter(&bus->adapter);
	}

	kfree(dev_priv->gmbus);
	dev_priv->gmbus = NULL;
}
Commit	Line	Data
5c0c1d50 PJ	1	/*
	2	* Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
	3	* Copyright © 2006-2008,2010 Intel Corporation
	4	* Jesse Barnes <jesse.barnes@intel.com>
	5	*
	6	* Permission is hereby granted, free of charge, to any person obtaining a
	7	* copy of this software and associated documentation files (the "Software"),
	8	* to deal in the Software without restriction, including without limitation
	9	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	10	* and/or sell copies of the Software, and to permit persons to whom the
	11	* Software is furnished to do so, subject to the following conditions:
	12	*
	13	* The above copyright notice and this permission notice (including the next
	14	* paragraph) shall be included in all copies or substantial portions of the
	15	* Software.
	16	*
	17	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	18	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	19	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	20	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	21	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
	22	* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
	23	* DEALINGS IN THE SOFTWARE.
	24	*
	25	* Authors:
	26	* Eric Anholt <eric@anholt.net>
	27	* Chris Wilson <chris@chris-wilson.co.uk>
	28	*/
	29	#include <linux/module.h>
	30	#include <linux/i2c.h>
	31	#include <linux/i2c-algo-bit.h>
	32	#include "drmP.h"
	33	#include "drm.h"
	34	#include "psb_intel_drv.h"
	35	#include "gma_drm.h"
	36	#include "psb_drv.h"
	37	#include "psb_intel_reg.h"
	38
	39	#define _wait_for(COND, MS, W) ({ \
	40	unsigned long timeout__ = jiffies + msecs_to_jiffies(MS); \
	41	int ret__ = 0; \
	42	while (! (COND)) { \
	43	if (time_after(jiffies, timeout__)) { \
	44	ret__ = -ETIMEDOUT; \
	45	break; \
	46	} \
	47	if (W && !(in_atomic() \|\| in_dbg_master())) msleep(W); \
	48	} \
	49	ret__; \
	50	})
	51
	52	#define wait_for(COND, MS) _wait_for(COND, MS, 1)
	53	#define wait_for_atomic(COND, MS) _wait_for(COND, MS, 0)
	54
	55	/* Intel GPIO access functions */
	56
	57	#define I2C_RISEFALL_TIME 20
	58
	59	static inline struct intel_gmbus *
	60	to_intel_gmbus(struct i2c_adapter *i2c)
	61	{
	62	return container_of(i2c, struct intel_gmbus, adapter);
	63	}
	64
65	struct intel_gpio {
66	struct i2c_adapter adapter;
67	struct i2c_algo_bit_data algo;
68	struct drm_psb_private *dev_priv;
69	u32 reg;
70	};
71
72	void
73	gma_intel_i2c_reset(struct drm_device *dev)
74	{
75	REG_WRITE(GMBUS0, 0);
76	}
77
78	static void intel_i2c_quirk_set(struct drm_psb_private *dev_priv, bool enable)
79	{
80	/* When using bit bashing for I2C, this bit needs to be set to 1 */
81	/* FIXME: We are never Pineview, right?
82
83	u32 val;
84
85	if (!IS_PINEVIEW(dev_priv->dev))
86	return;
87
88	val = REG_READ(DSPCLK_GATE_D);
89	if (enable)
90	val \|= DPCUNIT_CLOCK_GATE_DISABLE;
91	else
92	val &= ~DPCUNIT_CLOCK_GATE_DISABLE;
93	REG_WRITE(DSPCLK_GATE_D, val);
94
95	return;
96	*/
97	}
98
99	static u32 get_reserved(struct intel_gpio *gpio)
100	{
101	struct drm_psb_private *dev_priv = gpio->dev_priv;
102	struct drm_device *dev = dev_priv->dev;
103	u32 reserved = 0;
104
105	/* On most chips, these bits must be preserved in software. */
106	reserved = REG_READ(gpio->reg) &
107	(GPIO_DATA_PULLUP_DISABLE \|
108	GPIO_CLOCK_PULLUP_DISABLE);
109
110	return reserved;
111	}
112
113	static int get_clock(void *data)
114	{
115	struct intel_gpio *gpio = data;
116	struct drm_psb_private *dev_priv = gpio->dev_priv;
117	struct drm_device *dev = dev_priv->dev;
118	u32 reserved = get_reserved(gpio);
119	REG_WRITE(gpio->reg, reserved \| GPIO_CLOCK_DIR_MASK);
120	REG_WRITE(gpio->reg, reserved);
121	return (REG_READ(gpio->reg) & GPIO_CLOCK_VAL_IN) != 0;
122	}
123
124	static int get_data(void *data)
125	{
126	struct intel_gpio *gpio = data;
127	struct drm_psb_private *dev_priv = gpio->dev_priv;
128	struct drm_device *dev = dev_priv->dev;
129	u32 reserved = get_reserved(gpio);
130	REG_WRITE(gpio->reg, reserved \| GPIO_DATA_DIR_MASK);
131	REG_WRITE(gpio->reg, reserved);
132	return (REG_READ(gpio->reg) & GPIO_DATA_VAL_IN) != 0;
133	}
134
135	static void set_clock(void *data, int state_high)
136	{
137	struct intel_gpio *gpio = data;
138	struct drm_psb_private *dev_priv = gpio->dev_priv;
139	struct drm_device *dev = dev_priv->dev;
140	u32 reserved = get_reserved(gpio);
141	u32 clock_bits;
142
143	if (state_high)
144	clock_bits = GPIO_CLOCK_DIR_IN \| GPIO_CLOCK_DIR_MASK;
145	else
146	clock_bits = GPIO_CLOCK_DIR_OUT \| GPIO_CLOCK_DIR_MASK \|
147	GPIO_CLOCK_VAL_MASK;
148
149	REG_WRITE(gpio->reg, reserved \| clock_bits);
150	REG_READ(gpio->reg); /* Posting */
151	}
152
153	static void set_data(void *data, int state_high)
154	{
155	struct intel_gpio *gpio = data;
156	struct drm_psb_private *dev_priv = gpio->dev_priv;
157	struct drm_device *dev = dev_priv->dev;
158	u32 reserved = get_reserved(gpio);
159	u32 data_bits;
160
161	if (state_high)
162	data_bits = GPIO_DATA_DIR_IN \| GPIO_DATA_DIR_MASK;
163	else
164	data_bits = GPIO_DATA_DIR_OUT \| GPIO_DATA_DIR_MASK \|
165	GPIO_DATA_VAL_MASK;
166
167	REG_WRITE(gpio->reg, reserved \| data_bits);
168	REG_READ(gpio->reg);
169	}
170
171	static struct i2c_adapter *
172	intel_gpio_create(struct drm_psb_private *dev_priv, u32 pin)
173	{
174	static const int map_pin_to_reg[] = {
175	0,
176	GPIOB,
177	GPIOA,
178	GPIOC,
179	GPIOD,
180	GPIOE,
181	0,
182	GPIOF,
183	};
184	struct intel_gpio *gpio;
185
186	if (pin >= ARRAY_SIZE(map_pin_to_reg) \|\| !map_pin_to_reg[pin])
187	return NULL;
188
189	gpio = kzalloc(sizeof(struct intel_gpio), GFP_KERNEL);
190	if (gpio == NULL)
191	return NULL;
192
193	gpio->reg = map_pin_to_reg[pin];
194	gpio->dev_priv = dev_priv;
195
196	snprintf(gpio->adapter.name, sizeof(gpio->adapter.name),
197	"gma500 GPIO%c", "?BACDE?F"[pin]);
198	gpio->adapter.owner = THIS_MODULE;
199	gpio->adapter.algo_data = &gpio->algo;
200	gpio->adapter.dev.parent = &dev_priv->dev->pdev->dev;
201	gpio->algo.setsda = set_data;
202	gpio->algo.setscl = set_clock;
203	gpio->algo.getsda = get_data;
204	gpio->algo.getscl = get_clock;
205	gpio->algo.udelay = I2C_RISEFALL_TIME;
206	gpio->algo.timeout = usecs_to_jiffies(2200);
207	gpio->algo.data = gpio;
208
209	if (i2c_bit_add_bus(&gpio->adapter))
210	goto out_free;
211
212	return &gpio->adapter;
213
214	out_free:
215	kfree(gpio);
216	return NULL;
217	}
218
219	static int
220	intel_i2c_quirk_xfer(struct drm_psb_private *dev_priv,
221	struct i2c_adapter *adapter,
222	struct i2c_msg *msgs,
223	int num)
224	{
225	struct intel_gpio *gpio = container_of(adapter,
226	struct intel_gpio,
227	adapter);
228	int ret;
229
230	gma_intel_i2c_reset(dev_priv->dev);
231
232	intel_i2c_quirk_set(dev_priv, true);
233	set_data(gpio, 1);
234	set_clock(gpio, 1);
235	udelay(I2C_RISEFALL_TIME);
236
237	ret = adapter->algo->master_xfer(adapter, msgs, num);
238
239	set_data(gpio, 1);
240	set_clock(gpio, 1);
241	intel_i2c_quirk_set(dev_priv, false);
242
243	return ret;
244	}
245
246	static int
247	gmbus_xfer(struct i2c_adapter *adapter,
248	struct i2c_msg *msgs,
249	int num)
250	{
251	struct intel_gmbus *bus = container_of(adapter,
252	struct intel_gmbus,
253	adapter);
254	struct drm_psb_private *dev_priv = adapter->algo_data;
255	struct drm_device *dev = dev_priv->dev;
256	int i, reg_offset;
257
258	if (bus->force_bit)
259	return intel_i2c_quirk_xfer(dev_priv,
260	bus->force_bit, msgs, num);
261
262	reg_offset = 0;
263
264	REG_WRITE(GMBUS0 + reg_offset, bus->reg0);
265
266	for (i = 0; i < num; i++) {
267	u16 len = msgs[i].len;
268	u8 *buf = msgs[i].buf;
269
270	if (msgs[i].flags & I2C_M_RD) {
271	REG_WRITE(GMBUS1 + reg_offset,
272	GMBUS_CYCLE_WAIT \| (i + 1 == num ? GMBUS_CYCLE_STOP : 0) \|
273	(len << GMBUS_BYTE_COUNT_SHIFT) \|
274	(msgs[i].addr << GMBUS_SLAVE_ADDR_SHIFT) \|
275	GMBUS_SLAVE_READ \| GMBUS_SW_RDY);
276	REG_READ(GMBUS2+reg_offset);
277	do {
278	u32 val, loop = 0;
279
280	if (wait_for(REG_READ(GMBUS2 + reg_offset) & (GMBUS_SATOER \| GMBUS_HW_RDY), 50))
281	goto timeout;
282	if (REG_READ(GMBUS2 + reg_offset) & GMBUS_SATOER)
283	goto clear_err;
284
285	val = REG_READ(GMBUS3 + reg_offset);
286	do {
287	*buf++ = val & 0xff;
288	val >>= 8;
289	} while (--len && ++loop < 4);
290	} while (len);
291	} else {
292	u32 val, loop;
293
294	val = loop = 0;
295	do {
296	val \|= buf++ << (8 loop);
297	} while (--len && ++loop < 4);
298
299	REG_WRITE(GMBUS3 + reg_offset, val);
300	REG_WRITE(GMBUS1 + reg_offset,
301	(i + 1 == num ? GMBUS_CYCLE_STOP : GMBUS_CYCLE_WAIT) \|
302	(msgs[i].len << GMBUS_BYTE_COUNT_SHIFT) \|
303	(msgs[i].addr << GMBUS_SLAVE_ADDR_SHIFT) \|
304	GMBUS_SLAVE_WRITE \| GMBUS_SW_RDY);
305	REG_READ(GMBUS2+reg_offset);
306
307	while (len) {
308	if (wait_for(REG_READ(GMBUS2 + reg_offset) & (GMBUS_SATOER \| GMBUS_HW_RDY), 50))
309	goto timeout;
310	if (REG_READ(GMBUS2 + reg_offset) & GMBUS_SATOER)
311	goto clear_err;
312
313	val = loop = 0;
314	do {
315	val \|= buf++ << (8 loop);
316	} while (--len && ++loop < 4);
317
318	REG_WRITE(GMBUS3 + reg_offset, val);
319	REG_READ(GMBUS2+reg_offset);
320	}
321	}
322
323	if (i + 1 < num && wait_for(REG_READ(GMBUS2 + reg_offset) & (GMBUS_SATOER \| GMBUS_HW_WAIT_PHASE), 50))
324	goto timeout;
325	if (REG_READ(GMBUS2 + reg_offset) & GMBUS_SATOER)
326	goto clear_err;
327	}
328
329	goto done;
330
331	clear_err:
332	/* Toggle the Software Clear Interrupt bit. This has the effect
333	* of resetting the GMBUS controller and so clearing the
334	* BUS_ERROR raised by the slave's NAK.
335	*/
336	REG_WRITE(GMBUS1 + reg_offset, GMBUS_SW_CLR_INT);
337	REG_WRITE(GMBUS1 + reg_offset, 0);
338
339	done:
340	/* Mark the GMBUS interface as disabled. We will re-enable it at the
341	* start of the next xfer, till then let it sleep.
342	*/
343	REG_WRITE(GMBUS0 + reg_offset, 0);
344	return i;
345
346	timeout:
347	DRM_INFO("GMBUS timed out, falling back to bit banging on pin %d [%s]\n",
348	bus->reg0 & 0xff, bus->adapter.name);
349	REG_WRITE(GMBUS0 + reg_offset, 0);
350
351	/* Hardware may not support GMBUS over these pins? Try GPIO bitbanging instead. */
352	bus->force_bit = intel_gpio_create(dev_priv, bus->reg0 & 0xff);
353	if (!bus->force_bit)
354	return -ENOMEM;
355
356	return intel_i2c_quirk_xfer(dev_priv, bus->force_bit, msgs, num);
357	}
358
359	static u32 gmbus_func(struct i2c_adapter *adapter)
360	{
361	struct intel_gmbus *bus = container_of(adapter,
362	struct intel_gmbus,
363	adapter);
364
365	if (bus->force_bit)
366	bus->force_bit->algo->functionality(bus->force_bit);
367
368	return (I2C_FUNC_I2C \| I2C_FUNC_SMBUS_EMUL \|
369	/* I2C_FUNC_10BIT_ADDR \| */
370	I2C_FUNC_SMBUS_READ_BLOCK_DATA \|
371	I2C_FUNC_SMBUS_BLOCK_PROC_CALL);
372	}
373
374	static const struct i2c_algorithm gmbus_algorithm = {
375	.master_xfer = gmbus_xfer,
376	.functionality = gmbus_func
377	};
378
379	/**
380	* intel_gmbus_setup - instantiate all Intel i2c GMBuses
381	* @dev: DRM device
382	*/
383	int gma_intel_setup_gmbus(struct drm_device *dev)
384	{
385	static const char *names[GMBUS_NUM_PORTS] = {
386	"disabled",
387	"ssc",
388	"vga",
389	"panel",
390	"dpc",
391	"dpb",
392	"reserved",
393	"dpd",
394	};
395	struct drm_psb_private *dev_priv = dev->dev_private;
396	int ret, i;
397
398	dev_priv->gmbus = kcalloc(sizeof(struct intel_gmbus), GMBUS_NUM_PORTS,
399	GFP_KERNEL);
400	if (dev_priv->gmbus == NULL)
401	return -ENOMEM;
402
403	for (i = 0; i < GMBUS_NUM_PORTS; i++) {
404	struct intel_gmbus *bus = &dev_priv->gmbus[i];
405
406	bus->adapter.owner = THIS_MODULE;
407	bus->adapter.class = I2C_CLASS_DDC;
408	snprintf(bus->adapter.name,
409	sizeof(bus->adapter.name),
410	"gma500 gmbus %s",
411	names[i]);
412
413	bus->adapter.dev.parent = &dev->pdev->dev;
414	bus->adapter.algo_data = dev_priv;
415
416	bus->adapter.algo = &gmbus_algorithm;
417	ret = i2c_add_adapter(&bus->adapter);
418	if (ret)
419	goto err;
420
421	/* By default use a conservative clock rate */
422	bus->reg0 = i \| GMBUS_RATE_100KHZ;
423
424	/* XXX force bit banging until GMBUS is fully debugged */
425	bus->force_bit = intel_gpio_create(dev_priv, i);
426	}
427
428	gma_intel_i2c_reset(dev_priv->dev);
429
430	return 0;
431
432	err:
433	while (--i) {
434	struct intel_gmbus *bus = &dev_priv->gmbus[i];
435	i2c_del_adapter(&bus->adapter);
436	}
437	kfree(dev_priv->gmbus);
438	dev_priv->gmbus = NULL;
439	return ret;
440	}
441
442	void gma_intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed)
443	{
444	struct intel_gmbus *bus = to_intel_gmbus(adapter);
445
446	/* speed:
447	* 0x0 = 100 KHz
448	* 0x1 = 50 KHz
449	* 0x2 = 400 KHz
450	* 0x3 = 1000 Khz
451	*/
452	bus->reg0 = (bus->reg0 & ~(0x3 << 8)) \| (speed << 8);
453	}
454
455	void gma_intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit)
456	{
457	struct intel_gmbus *bus = to_intel_gmbus(adapter);
458
459	if (force_bit) {
460	if (bus->force_bit == NULL) {
461	struct drm_psb_private *dev_priv = adapter->algo_data;
462	bus->force_bit = intel_gpio_create(dev_priv,
463	bus->reg0 & 0xff);
464	}
465	} else {
466	if (bus->force_bit) {
467	i2c_del_adapter(bus->force_bit);
468	kfree(bus->force_bit);
469	bus->force_bit = NULL;
470	}
471	}
472	}
473
474	void gma_intel_teardown_gmbus(struct drm_device *dev)
475	{
476	struct drm_psb_private *dev_priv = dev->dev_private;
477	int i;
478
479	if (dev_priv->gmbus == NULL)
480	return;
481
482	for (i = 0; i < GMBUS_NUM_PORTS; i++) {
483	struct intel_gmbus *bus = &dev_priv->gmbus[i];
484	if (bus->force_bit) {
485	i2c_del_adapter(bus->force_bit);
486	kfree(bus->force_bit);
487	}
488	i2c_del_adapter(&bus->adapter);
489	}
490
491	kfree(dev_priv->gmbus);
492	dev_priv->gmbus = NULL;
493	}