[deliverable/linux.git] / drivers / gpu / drm / gma500 / psb_reg.h

/**************************************************************************
 *
 * Copyright (c) (2005-2007) Imagination Technologies Limited.
 * Copyright (c) 2007, Intel Corporation.
 * All Rights Reserved.
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms and conditions of the GNU General Public License,
 * version 2, as published by the Free Software Foundation.
 *
 * This program is distributed in the hope it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 * more details.
 *
 * You should have received a copy of the GNU General Public License along with
 * this program; if not, write to the Free Software Foundation, Inc.,
 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA..
 *
 **************************************************************************/

#ifndef _PSB_REG_H_
#define _PSB_REG_H_

#define PSB_CR_CLKGATECTL		0x0000
#define _PSB_C_CLKGATECTL_AUTO_MAN_REG		(1 << 24)
#define _PSB_C_CLKGATECTL_USE_CLKG_SHIFT	(20)
#define _PSB_C_CLKGATECTL_USE_CLKG_MASK		(0x3 << 20)
#define _PSB_C_CLKGATECTL_DPM_CLKG_SHIFT	(16)
#define _PSB_C_CLKGATECTL_DPM_CLKG_MASK		(0x3 << 16)
#define _PSB_C_CLKGATECTL_TA_CLKG_SHIFT		(12)
#define _PSB_C_CLKGATECTL_TA_CLKG_MASK		(0x3 << 12)
#define _PSB_C_CLKGATECTL_TSP_CLKG_SHIFT	(8)
#define _PSB_C_CLKGATECTL_TSP_CLKG_MASK		(0x3 << 8)
#define _PSB_C_CLKGATECTL_ISP_CLKG_SHIFT	(4)
#define _PSB_C_CLKGATECTL_ISP_CLKG_MASK		(0x3 << 4)
#define _PSB_C_CLKGATECTL_2D_CLKG_SHIFT		(0)
#define _PSB_C_CLKGATECTL_2D_CLKG_MASK		(0x3 << 0)
#define _PSB_C_CLKGATECTL_CLKG_ENABLED		(0)
#define _PSB_C_CLKGATECTL_CLKG_DISABLED		(1)
#define _PSB_C_CLKGATECTL_CLKG_AUTO		(2)

#define PSB_CR_CORE_ID			0x0010
#define _PSB_CC_ID_ID_SHIFT			(16)
#define _PSB_CC_ID_ID_MASK			(0xFFFF << 16)
#define _PSB_CC_ID_CONFIG_SHIFT			(0)
#define _PSB_CC_ID_CONFIG_MASK			(0xFFFF << 0)

#define PSB_CR_CORE_REVISION		0x0014
#define _PSB_CC_REVISION_DESIGNER_SHIFT		(24)
#define _PSB_CC_REVISION_DESIGNER_MASK		(0xFF << 24)
#define _PSB_CC_REVISION_MAJOR_SHIFT		(16)
#define _PSB_CC_REVISION_MAJOR_MASK		(0xFF << 16)
#define _PSB_CC_REVISION_MINOR_SHIFT		(8)
#define _PSB_CC_REVISION_MINOR_MASK		(0xFF << 8)
#define _PSB_CC_REVISION_MAINTENANCE_SHIFT	(0)
#define _PSB_CC_REVISION_MAINTENANCE_MASK	(0xFF << 0)

#define PSB_CR_DESIGNER_REV_FIELD1	0x0018

#define PSB_CR_SOFT_RESET		0x0080
#define _PSB_CS_RESET_TSP_RESET		(1 << 6)
#define _PSB_CS_RESET_ISP_RESET		(1 << 5)
#define _PSB_CS_RESET_USE_RESET		(1 << 4)
#define _PSB_CS_RESET_TA_RESET		(1 << 3)
#define _PSB_CS_RESET_DPM_RESET		(1 << 2)
#define _PSB_CS_RESET_TWOD_RESET	(1 << 1)
#define _PSB_CS_RESET_BIF_RESET			(1 << 0)

#define PSB_CR_DESIGNER_REV_FIELD2	0x001C

#define PSB_CR_EVENT_HOST_ENABLE2	0x0110

#define PSB_CR_EVENT_STATUS2		0x0118

#define PSB_CR_EVENT_HOST_CLEAR2	0x0114
#define _PSB_CE2_BIF_REQUESTER_FAULT		(1 << 4)

#define PSB_CR_EVENT_STATUS		0x012C

#define PSB_CR_EVENT_HOST_ENABLE	0x0130

#define PSB_CR_EVENT_HOST_CLEAR		0x0134
#define _PSB_CE_MASTER_INTERRUPT		(1 << 31)
#define _PSB_CE_TA_DPM_FAULT			(1 << 28)
#define _PSB_CE_TWOD_COMPLETE			(1 << 27)
#define _PSB_CE_DPM_OUT_OF_MEMORY_ZLS		(1 << 25)
#define _PSB_CE_DPM_TA_MEM_FREE			(1 << 24)
#define _PSB_CE_PIXELBE_END_RENDER		(1 << 18)
#define _PSB_CE_SW_EVENT			(1 << 14)
#define _PSB_CE_TA_FINISHED			(1 << 13)
#define _PSB_CE_TA_TERMINATE			(1 << 12)
#define _PSB_CE_DPM_REACHED_MEM_THRESH		(1 << 3)
#define _PSB_CE_DPM_OUT_OF_MEMORY_GBL		(1 << 2)
#define _PSB_CE_DPM_OUT_OF_MEMORY_MT		(1 << 1)
#define _PSB_CE_DPM_3D_MEM_FREE			(1 << 0)


#define PSB_USE_OFFSET_MASK		0x0007FFFF
#define PSB_USE_OFFSET_SIZE		(PSB_USE_OFFSET_MASK + 1)
#define PSB_CR_USE_CODE_BASE0		0x0A0C
#define PSB_CR_USE_CODE_BASE1		0x0A10
#define PSB_CR_USE_CODE_BASE2		0x0A14
#define PSB_CR_USE_CODE_BASE3		0x0A18
#define PSB_CR_USE_CODE_BASE4		0x0A1C
#define PSB_CR_USE_CODE_BASE5		0x0A20
#define PSB_CR_USE_CODE_BASE6		0x0A24
#define PSB_CR_USE_CODE_BASE7		0x0A28
#define PSB_CR_USE_CODE_BASE8		0x0A2C
#define PSB_CR_USE_CODE_BASE9		0x0A30
#define PSB_CR_USE_CODE_BASE10		0x0A34
#define PSB_CR_USE_CODE_BASE11		0x0A38
#define PSB_CR_USE_CODE_BASE12		0x0A3C
#define PSB_CR_USE_CODE_BASE13		0x0A40
#define PSB_CR_USE_CODE_BASE14		0x0A44
#define PSB_CR_USE_CODE_BASE15		0x0A48
#define PSB_CR_USE_CODE_BASE(_i)	(0x0A0C + ((_i) << 2))
#define _PSB_CUC_BASE_DM_SHIFT			(25)
#define _PSB_CUC_BASE_DM_MASK			(0x3 << 25)
#define _PSB_CUC_BASE_ADDR_SHIFT		(0)	/* 1024-bit aligned address? */
#define _PSB_CUC_BASE_ADDR_ALIGNSHIFT		(7)
#define _PSB_CUC_BASE_ADDR_MASK			(0x1FFFFFF << 0)
#define _PSB_CUC_DM_VERTEX			(0)
#define _PSB_CUC_DM_PIXEL			(1)
#define _PSB_CUC_DM_RESERVED			(2)
#define _PSB_CUC_DM_EDM				(3)

#define PSB_CR_PDS_EXEC_BASE		0x0AB8
#define _PSB_CR_PDS_EXEC_BASE_ADDR_SHIFT	(20)	/* 1MB aligned address */
#define _PSB_CR_PDS_EXEC_BASE_ADDR_ALIGNSHIFT	(20)

#define PSB_CR_EVENT_KICKER		0x0AC4
#define _PSB_CE_KICKER_ADDRESS_SHIFT		(4)	/* 128-bit aligned address */

#define PSB_CR_EVENT_KICK		0x0AC8
#define _PSB_CE_KICK_NOW			(1 << 0)

#define PSB_CR_BIF_DIR_LIST_BASE1	0x0C38

#define PSB_CR_BIF_CTRL			0x0C00
#define _PSB_CB_CTRL_CLEAR_FAULT		(1 << 4)
#define _PSB_CB_CTRL_INVALDC			(1 << 3)
#define _PSB_CB_CTRL_FLUSH			(1 << 2)

#define PSB_CR_BIF_INT_STAT		0x0C04

#define PSB_CR_BIF_FAULT		0x0C08
#define _PSB_CBI_STAT_PF_N_RW			(1 << 14)
#define _PSB_CBI_STAT_FAULT_SHIFT		(0)
#define _PSB_CBI_STAT_FAULT_MASK		(0x3FFF << 0)
#define _PSB_CBI_STAT_FAULT_CACHE		(1 << 1)
#define _PSB_CBI_STAT_FAULT_TA			(1 << 2)
#define _PSB_CBI_STAT_FAULT_VDM			(1 << 3)
#define _PSB_CBI_STAT_FAULT_2D			(1 << 4)
#define _PSB_CBI_STAT_FAULT_PBE			(1 << 5)
#define _PSB_CBI_STAT_FAULT_TSP			(1 << 6)
#define _PSB_CBI_STAT_FAULT_ISP			(1 << 7)
#define _PSB_CBI_STAT_FAULT_USSEPDS		(1 << 8)
#define _PSB_CBI_STAT_FAULT_HOST		(1 << 9)

#define PSB_CR_BIF_BANK0		0x0C78
#define PSB_CR_BIF_BANK1		0x0C7C
#define PSB_CR_BIF_DIR_LIST_BASE0	0x0C84
#define PSB_CR_BIF_TWOD_REQ_BASE	0x0C88
#define PSB_CR_BIF_3D_REQ_BASE		0x0CAC

#define PSB_CR_2D_SOCIF			0x0E18
#define _PSB_C2_SOCIF_FREESPACE_SHIFT		(0)
#define _PSB_C2_SOCIF_FREESPACE_MASK		(0xFF << 0)
#define _PSB_C2_SOCIF_EMPTY			(0x80 << 0)

#define PSB_CR_2D_BLIT_STATUS		0x0E04
#define _PSB_C2B_STATUS_BUSY			(1 << 24)
#define _PSB_C2B_STATUS_COMPLETE_SHIFT		(0)
#define _PSB_C2B_STATUS_COMPLETE_MASK		(0xFFFFFF << 0)

/*
 * 2D defs.
 */

/*
 * 2D Slave Port Data : Block Header's Object Type
 */

#define	PSB_2D_CLIP_BH			(0x00000000)
#define	PSB_2D_PAT_BH			(0x10000000)
#define	PSB_2D_CTRL_BH			(0x20000000)
#define	PSB_2D_SRC_OFF_BH		(0x30000000)
#define	PSB_2D_MASK_OFF_BH		(0x40000000)
#define	PSB_2D_RESERVED1_BH		(0x50000000)
#define	PSB_2D_RESERVED2_BH		(0x60000000)
#define	PSB_2D_FENCE_BH			(0x70000000)
#define	PSB_2D_BLIT_BH			(0x80000000)
#define	PSB_2D_SRC_SURF_BH		(0x90000000)
#define	PSB_2D_DST_SURF_BH		(0xA0000000)
#define	PSB_2D_PAT_SURF_BH		(0xB0000000)
#define	PSB_2D_SRC_PAL_BH		(0xC0000000)
#define	PSB_2D_PAT_PAL_BH		(0xD0000000)
#define	PSB_2D_MASK_SURF_BH		(0xE0000000)
#define	PSB_2D_FLUSH_BH			(0xF0000000)

/*
 * Clip Definition block (PSB_2D_CLIP_BH)
 */
#define PSB_2D_CLIPCOUNT_MAX		(1)
#define PSB_2D_CLIPCOUNT_MASK		(0x00000000)
#define PSB_2D_CLIPCOUNT_CLRMASK	(0xFFFFFFFF)
#define PSB_2D_CLIPCOUNT_SHIFT		(0)
/* clip rectangle min & max */
#define PSB_2D_CLIP_XMAX_MASK		(0x00FFF000)
#define PSB_2D_CLIP_XMAX_CLRMASK	(0xFF000FFF)
#define PSB_2D_CLIP_XMAX_SHIFT		(12)
#define PSB_2D_CLIP_XMIN_MASK		(0x00000FFF)
#define PSB_2D_CLIP_XMIN_CLRMASK	(0x00FFF000)
#define PSB_2D_CLIP_XMIN_SHIFT		(0)
/* clip rectangle offset */
#define PSB_2D_CLIP_YMAX_MASK		(0x00FFF000)
#define PSB_2D_CLIP_YMAX_CLRMASK	(0xFF000FFF)
#define PSB_2D_CLIP_YMAX_SHIFT		(12)
#define PSB_2D_CLIP_YMIN_MASK		(0x00000FFF)
#define PSB_2D_CLIP_YMIN_CLRMASK	(0x00FFF000)
#define PSB_2D_CLIP_YMIN_SHIFT		(0)

/*
 * Pattern Control (PSB_2D_PAT_BH)
 */
#define PSB_2D_PAT_HEIGHT_MASK		(0x0000001F)
#define PSB_2D_PAT_HEIGHT_SHIFT		(0)
#define PSB_2D_PAT_WIDTH_MASK		(0x000003E0)
#define PSB_2D_PAT_WIDTH_SHIFT		(5)
#define PSB_2D_PAT_YSTART_MASK		(0x00007C00)
#define PSB_2D_PAT_YSTART_SHIFT		(10)
#define PSB_2D_PAT_XSTART_MASK		(0x000F8000)
#define PSB_2D_PAT_XSTART_SHIFT		(15)

/*
 * 2D Control block (PSB_2D_CTRL_BH)
 */
/* Present Flags */
#define PSB_2D_SRCCK_CTRL		(0x00000001)
#define PSB_2D_DSTCK_CTRL		(0x00000002)
#define PSB_2D_ALPHA_CTRL		(0x00000004)
/* Colour Key Colour (SRC/DST)*/
#define PSB_2D_CK_COL_MASK		(0xFFFFFFFF)
#define PSB_2D_CK_COL_CLRMASK		(0x00000000)
#define PSB_2D_CK_COL_SHIFT		(0)
/* Colour Key Mask (SRC/DST)*/
#define PSB_2D_CK_MASK_MASK		(0xFFFFFFFF)
#define PSB_2D_CK_MASK_CLRMASK		(0x00000000)
#define PSB_2D_CK_MASK_SHIFT		(0)
/* Alpha Control (Alpha/RGB)*/
#define PSB_2D_GBLALPHA_MASK		(0x000FF000)
#define PSB_2D_GBLALPHA_CLRMASK		(0xFFF00FFF)
#define PSB_2D_GBLALPHA_SHIFT		(12)
#define PSB_2D_SRCALPHA_OP_MASK		(0x00700000)
#define PSB_2D_SRCALPHA_OP_CLRMASK	(0xFF8FFFFF)
#define PSB_2D_SRCALPHA_OP_SHIFT	(20)
#define PSB_2D_SRCALPHA_OP_ONE		(0x00000000)
#define PSB_2D_SRCALPHA_OP_SRC		(0x00100000)
#define PSB_2D_SRCALPHA_OP_DST		(0x00200000)
#define PSB_2D_SRCALPHA_OP_SG		(0x00300000)
#define PSB_2D_SRCALPHA_OP_DG		(0x00400000)
#define PSB_2D_SRCALPHA_OP_GBL		(0x00500000)
#define PSB_2D_SRCALPHA_OP_ZERO		(0x00600000)
#define PSB_2D_SRCALPHA_INVERT		(0x00800000)
#define PSB_2D_SRCALPHA_INVERT_CLR	(0xFF7FFFFF)
#define PSB_2D_DSTALPHA_OP_MASK		(0x07000000)
#define PSB_2D_DSTALPHA_OP_CLRMASK	(0xF8FFFFFF)
#define PSB_2D_DSTALPHA_OP_SHIFT	(24)
#define PSB_2D_DSTALPHA_OP_ONE		(0x00000000)
#define PSB_2D_DSTALPHA_OP_SRC		(0x01000000)
#define PSB_2D_DSTALPHA_OP_DST		(0x02000000)
#define PSB_2D_DSTALPHA_OP_SG		(0x03000000)
#define PSB_2D_DSTALPHA_OP_DG		(0x04000000)
#define PSB_2D_DSTALPHA_OP_GBL		(0x05000000)
#define PSB_2D_DSTALPHA_OP_ZERO		(0x06000000)
#define PSB_2D_DSTALPHA_INVERT		(0x08000000)
#define PSB_2D_DSTALPHA_INVERT_CLR	(0xF7FFFFFF)

#define PSB_2D_PRE_MULTIPLICATION_ENABLE	(0x10000000)
#define PSB_2D_PRE_MULTIPLICATION_CLRMASK	(0xEFFFFFFF)
#define PSB_2D_ZERO_SOURCE_ALPHA_ENABLE		(0x20000000)
#define PSB_2D_ZERO_SOURCE_ALPHA_CLRMASK	(0xDFFFFFFF)

/*
 *Source Offset (PSB_2D_SRC_OFF_BH)
 */
#define PSB_2D_SRCOFF_XSTART_MASK	((0x00000FFF) << 12)
#define PSB_2D_SRCOFF_XSTART_SHIFT	(12)
#define PSB_2D_SRCOFF_YSTART_MASK	(0x00000FFF)
#define PSB_2D_SRCOFF_YSTART_SHIFT	(0)

/*
 * Mask Offset (PSB_2D_MASK_OFF_BH)
 */
#define PSB_2D_MASKOFF_XSTART_MASK	((0x00000FFF) << 12)
#define PSB_2D_MASKOFF_XSTART_SHIFT	(12)
#define PSB_2D_MASKOFF_YSTART_MASK	(0x00000FFF)
#define PSB_2D_MASKOFF_YSTART_SHIFT	(0)

/*
 * 2D Fence (see PSB_2D_FENCE_BH): bits 0:27 are ignored
 */

/*
 *Blit Rectangle (PSB_2D_BLIT_BH)
 */

#define PSB_2D_ROT_MASK			(3 << 25)
#define PSB_2D_ROT_CLRMASK		(~PSB_2D_ROT_MASK)
#define PSB_2D_ROT_NONE			(0 << 25)
#define PSB_2D_ROT_90DEGS		(1 << 25)
#define PSB_2D_ROT_180DEGS		(2 << 25)
#define PSB_2D_ROT_270DEGS		(3 << 25)

#define PSB_2D_COPYORDER_MASK		(3 << 23)
#define PSB_2D_COPYORDER_CLRMASK	(~PSB_2D_COPYORDER_MASK)
#define PSB_2D_COPYORDER_TL2BR		(0 << 23)
#define PSB_2D_COPYORDER_BR2TL		(1 << 23)
#define PSB_2D_COPYORDER_TR2BL		(2 << 23)
#define PSB_2D_COPYORDER_BL2TR		(3 << 23)

#define PSB_2D_DSTCK_CLRMASK		(0xFF9FFFFF)
#define PSB_2D_DSTCK_DISABLE		(0x00000000)
#define PSB_2D_DSTCK_PASS		(0x00200000)
#define PSB_2D_DSTCK_REJECT		(0x00400000)

#define PSB_2D_SRCCK_CLRMASK		(0xFFE7FFFF)
#define PSB_2D_SRCCK_DISABLE		(0x00000000)
#define PSB_2D_SRCCK_PASS		(0x00080000)
#define PSB_2D_SRCCK_REJECT		(0x00100000)

#define PSB_2D_CLIP_ENABLE		(0x00040000)

#define PSB_2D_ALPHA_ENABLE		(0x00020000)

#define PSB_2D_PAT_CLRMASK		(0xFFFEFFFF)
#define PSB_2D_PAT_MASK			(0x00010000)
#define PSB_2D_USE_PAT			(0x00010000)
#define PSB_2D_USE_FILL			(0x00000000)
/*
 * Tungsten Graphics note on rop codes: If rop A and rop B are
 * identical, the mask surface will not be read and need not be
 * set up.
 */

#define PSB_2D_ROP3B_MASK		(0x0000FF00)
#define PSB_2D_ROP3B_CLRMASK		(0xFFFF00FF)
#define PSB_2D_ROP3B_SHIFT		(8)
/* rop code A */
#define PSB_2D_ROP3A_MASK		(0x000000FF)
#define PSB_2D_ROP3A_CLRMASK		(0xFFFFFF00)
#define PSB_2D_ROP3A_SHIFT		(0)

#define PSB_2D_ROP4_MASK		(0x0000FFFF)
/*
 *	DWORD0:	(Only pass if Pattern control == Use Fill Colour)
 *	Fill Colour RGBA8888
 */
#define PSB_2D_FILLCOLOUR_MASK		(0xFFFFFFFF)
#define PSB_2D_FILLCOLOUR_SHIFT		(0)
/*
 *	DWORD1: (Always Present)
 *	X Start (Dest)
 *	Y Start (Dest)
 */
#define PSB_2D_DST_XSTART_MASK		(0x00FFF000)
#define PSB_2D_DST_XSTART_CLRMASK	(0xFF000FFF)
#define PSB_2D_DST_XSTART_SHIFT		(12)
#define PSB_2D_DST_YSTART_MASK		(0x00000FFF)
#define PSB_2D_DST_YSTART_CLRMASK	(0xFFFFF000)
#define PSB_2D_DST_YSTART_SHIFT		(0)
/*
 *	DWORD2: (Always Present)
 *	X Size (Dest)
 *	Y Size (Dest)
 */
#define PSB_2D_DST_XSIZE_MASK		(0x00FFF000)
#define PSB_2D_DST_XSIZE_CLRMASK	(0xFF000FFF)
#define PSB_2D_DST_XSIZE_SHIFT		(12)
#define PSB_2D_DST_YSIZE_MASK		(0x00000FFF)
#define PSB_2D_DST_YSIZE_CLRMASK	(0xFFFFF000)
#define PSB_2D_DST_YSIZE_SHIFT		(0)

/*
 * Source Surface (PSB_2D_SRC_SURF_BH)
 */
/*
 * WORD 0
 */

#define PSB_2D_SRC_FORMAT_MASK		(0x00078000)
#define PSB_2D_SRC_1_PAL		(0x00000000)
#define PSB_2D_SRC_2_PAL		(0x00008000)
#define PSB_2D_SRC_4_PAL		(0x00010000)
#define PSB_2D_SRC_8_PAL		(0x00018000)
#define PSB_2D_SRC_8_ALPHA		(0x00020000)
#define PSB_2D_SRC_4_ALPHA		(0x00028000)
#define PSB_2D_SRC_332RGB		(0x00030000)
#define PSB_2D_SRC_4444ARGB		(0x00038000)
#define PSB_2D_SRC_555RGB		(0x00040000)
#define PSB_2D_SRC_1555ARGB		(0x00048000)
#define PSB_2D_SRC_565RGB		(0x00050000)
#define PSB_2D_SRC_0888ARGB		(0x00058000)
#define PSB_2D_SRC_8888ARGB		(0x00060000)
#define PSB_2D_SRC_8888UYVY		(0x00068000)
#define PSB_2D_SRC_RESERVED		(0x00070000)
#define PSB_2D_SRC_1555ARGB_LOOKUP	(0x00078000)


#define PSB_2D_SRC_STRIDE_MASK		(0x00007FFF)
#define PSB_2D_SRC_STRIDE_CLRMASK	(0xFFFF8000)
#define PSB_2D_SRC_STRIDE_SHIFT		(0)
/*
 *  WORD 1 - Base Address
 */
#define PSB_2D_SRC_ADDR_MASK		(0x0FFFFFFC)
#define PSB_2D_SRC_ADDR_CLRMASK		(0x00000003)
#define PSB_2D_SRC_ADDR_SHIFT		(2)
#define PSB_2D_SRC_ADDR_ALIGNSHIFT	(2)

/*
 * Pattern Surface (PSB_2D_PAT_SURF_BH)
 */
/*
 *  WORD 0
 */

#define PSB_2D_PAT_FORMAT_MASK		(0x00078000)
#define PSB_2D_PAT_1_PAL		(0x00000000)
#define PSB_2D_PAT_2_PAL		(0x00008000)
#define PSB_2D_PAT_4_PAL		(0x00010000)
#define PSB_2D_PAT_8_PAL		(0x00018000)
#define PSB_2D_PAT_8_ALPHA		(0x00020000)
#define PSB_2D_PAT_4_ALPHA		(0x00028000)
#define PSB_2D_PAT_332RGB		(0x00030000)
#define PSB_2D_PAT_4444ARGB		(0x00038000)
#define PSB_2D_PAT_555RGB		(0x00040000)
#define PSB_2D_PAT_1555ARGB		(0x00048000)
#define PSB_2D_PAT_565RGB		(0x00050000)
#define PSB_2D_PAT_0888ARGB		(0x00058000)
#define PSB_2D_PAT_8888ARGB		(0x00060000)

#define PSB_2D_PAT_STRIDE_MASK		(0x00007FFF)
#define PSB_2D_PAT_STRIDE_CLRMASK	(0xFFFF8000)
#define PSB_2D_PAT_STRIDE_SHIFT		(0)
/*
 *  WORD 1 - Base Address
 */
#define PSB_2D_PAT_ADDR_MASK		(0x0FFFFFFC)
#define PSB_2D_PAT_ADDR_CLRMASK		(0x00000003)
#define PSB_2D_PAT_ADDR_SHIFT		(2)
#define PSB_2D_PAT_ADDR_ALIGNSHIFT	(2)

/*
 * Destination Surface (PSB_2D_DST_SURF_BH)
 */
/*
 * WORD 0
 */

#define PSB_2D_DST_FORMAT_MASK		(0x00078000)
#define PSB_2D_DST_332RGB		(0x00030000)
#define PSB_2D_DST_4444ARGB		(0x00038000)
#define PSB_2D_DST_555RGB		(0x00040000)
#define PSB_2D_DST_1555ARGB		(0x00048000)
#define PSB_2D_DST_565RGB		(0x00050000)
#define PSB_2D_DST_0888ARGB		(0x00058000)
#define PSB_2D_DST_8888ARGB		(0x00060000)
#define PSB_2D_DST_8888AYUV		(0x00070000)

#define PSB_2D_DST_STRIDE_MASK		(0x00007FFF)
#define PSB_2D_DST_STRIDE_CLRMASK	(0xFFFF8000)
#define PSB_2D_DST_STRIDE_SHIFT		(0)
/*
 * WORD 1 - Base Address
 */
#define PSB_2D_DST_ADDR_MASK		(0x0FFFFFFC)
#define PSB_2D_DST_ADDR_CLRMASK		(0x00000003)
#define PSB_2D_DST_ADDR_SHIFT		(2)
#define PSB_2D_DST_ADDR_ALIGNSHIFT	(2)

/*
 * Mask Surface (PSB_2D_MASK_SURF_BH)
 */
/*
 * WORD 0
 */
#define PSB_2D_MASK_STRIDE_MASK		(0x00007FFF)
#define PSB_2D_MASK_STRIDE_CLRMASK	(0xFFFF8000)
#define PSB_2D_MASK_STRIDE_SHIFT	(0)
/*
 *  WORD 1 - Base Address
 */
#define PSB_2D_MASK_ADDR_MASK		(0x0FFFFFFC)
#define PSB_2D_MASK_ADDR_CLRMASK	(0x00000003)
#define PSB_2D_MASK_ADDR_SHIFT		(2)
#define PSB_2D_MASK_ADDR_ALIGNSHIFT	(2)

/*
 * Source Palette (PSB_2D_SRC_PAL_BH)
 */

#define PSB_2D_SRCPAL_ADDR_SHIFT	(0)
#define PSB_2D_SRCPAL_ADDR_CLRMASK	(0xF0000007)
#define PSB_2D_SRCPAL_ADDR_MASK		(0x0FFFFFF8)
#define PSB_2D_SRCPAL_BYTEALIGN		(1024)

/*
 * Pattern Palette (PSB_2D_PAT_PAL_BH)
 */

#define PSB_2D_PATPAL_ADDR_SHIFT	(0)
#define PSB_2D_PATPAL_ADDR_CLRMASK	(0xF0000007)
#define PSB_2D_PATPAL_ADDR_MASK		(0x0FFFFFF8)
#define PSB_2D_PATPAL_BYTEALIGN		(1024)

/*
 * Rop3 Codes (2 LS bytes)
 */

#define PSB_2D_ROP3_SRCCOPY		(0xCCCC)
#define PSB_2D_ROP3_PATCOPY		(0xF0F0)
#define PSB_2D_ROP3_WHITENESS		(0xFFFF)
#define PSB_2D_ROP3_BLACKNESS		(0x0000)
#define PSB_2D_ROP3_SRC			(0xCC)
#define PSB_2D_ROP3_PAT			(0xF0)
#define PSB_2D_ROP3_DST			(0xAA)

/*
 * Sizes.
 */

#define PSB_SCENE_HW_COOKIE_SIZE	16
#define PSB_TA_MEM_HW_COOKIE_SIZE	16

/*
 * Scene stuff.
 */

#define PSB_NUM_HW_SCENES		2

/*
 * Scheduler completion actions.
 */

#define PSB_RASTER_BLOCK		0
#define PSB_RASTER			1
#define PSB_RETURN			2
#define PSB_TA				3

/* Power management */
#define PSB_PUNIT_PORT			0x04
#define PSB_OSPMBA			0x78
#define PSB_APMBA			0x7a
#define PSB_APM_CMD			0x0
#define PSB_APM_STS			0x04
#define PSB_PWRGT_VID_ENC_MASK		0x30
#define PSB_PWRGT_VID_DEC_MASK		0xc
#define PSB_PWRGT_GL3_MASK		0xc0

#define PSB_PM_SSC			0x20
#define PSB_PM_SSS			0x30
#define PSB_PWRGT_DISPLAY_MASK		0xc /*on a different BA than video/gfx*/
#define MDFLD_PWRGT_DISPLAY_A_CNTR	0x0000000c
#define MDFLD_PWRGT_DISPLAY_B_CNTR	0x0000c000
#define MDFLD_PWRGT_DISPLAY_C_CNTR	0x00030000
#define MDFLD_PWRGT_DISP_MIPI_CNTR	0x000c0000
#define MDFLD_PWRGT_DISPLAY_CNTR    (MDFLD_PWRGT_DISPLAY_A_CNTR | MDFLD_PWRGT_DISPLAY_B_CNTR | MDFLD_PWRGT_DISPLAY_C_CNTR | MDFLD_PWRGT_DISP_MIPI_CNTR) /* 0x000fc00c */
/* Display SSS register bits are different in A0 vs. B0 */
#define PSB_PWRGT_GFX_MASK		0x3
#define MDFLD_PWRGT_DISPLAY_A_STS	0x000000c0
#define MDFLD_PWRGT_DISPLAY_B_STS	0x00000300
#define MDFLD_PWRGT_DISPLAY_C_STS	0x00000c00
#define PSB_PWRGT_GFX_MASK_B0		0xc3
#define MDFLD_PWRGT_DISPLAY_A_STS_B0	0x0000000c
#define MDFLD_PWRGT_DISPLAY_B_STS_B0	0x0000c000
#define MDFLD_PWRGT_DISPLAY_C_STS_B0	0x00030000
#define MDFLD_PWRGT_DISP_MIPI_STS	0x000c0000
#define MDFLD_PWRGT_DISPLAY_STS_A0    (MDFLD_PWRGT_DISPLAY_A_STS | MDFLD_PWRGT_DISPLAY_B_STS | MDFLD_PWRGT_DISPLAY_C_STS | MDFLD_PWRGT_DISP_MIPI_STS) /* 0x000fc00c */
#define MDFLD_PWRGT_DISPLAY_STS_B0    (MDFLD_PWRGT_DISPLAY_A_STS_B0 | MDFLD_PWRGT_DISPLAY_B_STS_B0 | MDFLD_PWRGT_DISPLAY_C_STS_B0 | MDFLD_PWRGT_DISP_MIPI_STS) /* 0x000fc00c */
#endif
Commit	Line	Data
5c49fd3a AC	1	/**************************************************************************
	2	*
	3	* Copyright (c) (2005-2007) Imagination Technologies Limited.
	4	* Copyright (c) 2007, Intel Corporation.
	5	* All Rights Reserved.
	6	*
	7	* This program is free software; you can redistribute it and/or modify it
	8	* under the terms and conditions of the GNU General Public License,
	9	* version 2, as published by the Free Software Foundation.
	10	*
	11	* This program is distributed in the hope it will be useful, but WITHOUT
	12	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	13	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	14	* more details.
	15	*
	16	* You should have received a copy of the GNU General Public License along with
	17	* this program; if not, write to the Free Software Foundation, Inc.,
	18	* 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA..
	19	*
	20	**************************************************************************/
	21
	22	#ifndef _PSB_REG_H_
	23	#define _PSB_REG_H_
	24
	25	#define PSB_CR_CLKGATECTL 0x0000
	26	#define _PSB_C_CLKGATECTL_AUTO_MAN_REG (1 << 24)
	27	#define _PSB_C_CLKGATECTL_USE_CLKG_SHIFT (20)
	28	#define _PSB_C_CLKGATECTL_USE_CLKG_MASK (0x3 << 20)
	29	#define _PSB_C_CLKGATECTL_DPM_CLKG_SHIFT (16)
	30	#define _PSB_C_CLKGATECTL_DPM_CLKG_MASK (0x3 << 16)
	31	#define _PSB_C_CLKGATECTL_TA_CLKG_SHIFT (12)
	32	#define _PSB_C_CLKGATECTL_TA_CLKG_MASK (0x3 << 12)
	33	#define _PSB_C_CLKGATECTL_TSP_CLKG_SHIFT (8)
	34	#define _PSB_C_CLKGATECTL_TSP_CLKG_MASK (0x3 << 8)
	35	#define _PSB_C_CLKGATECTL_ISP_CLKG_SHIFT (4)
	36	#define _PSB_C_CLKGATECTL_ISP_CLKG_MASK (0x3 << 4)
	37	#define _PSB_C_CLKGATECTL_2D_CLKG_SHIFT (0)
	38	#define _PSB_C_CLKGATECTL_2D_CLKG_MASK (0x3 << 0)
	39	#define _PSB_C_CLKGATECTL_CLKG_ENABLED (0)
	40	#define _PSB_C_CLKGATECTL_CLKG_DISABLED (1)
	41	#define _PSB_C_CLKGATECTL_CLKG_AUTO (2)
	42
	43	#define PSB_CR_CORE_ID 0x0010
	44	#define _PSB_CC_ID_ID_SHIFT (16)
	45	#define _PSB_CC_ID_ID_MASK (0xFFFF << 16)
	46	#define _PSB_CC_ID_CONFIG_SHIFT (0)
	47	#define _PSB_CC_ID_CONFIG_MASK (0xFFFF << 0)
	48
	49	#define PSB_CR_CORE_REVISION 0x0014
	50	#define _PSB_CC_REVISION_DESIGNER_SHIFT (24)
	51	#define _PSB_CC_REVISION_DESIGNER_MASK (0xFF << 24)
	52	#define _PSB_CC_REVISION_MAJOR_SHIFT (16)
	53	#define _PSB_CC_REVISION_MAJOR_MASK (0xFF << 16)
	54	#define _PSB_CC_REVISION_MINOR_SHIFT (8)
	55	#define _PSB_CC_REVISION_MINOR_MASK (0xFF << 8)
	56	#define _PSB_CC_REVISION_MAINTENANCE_SHIFT (0)
	57	#define _PSB_CC_REVISION_MAINTENANCE_MASK (0xFF << 0)
	58
	59	#define PSB_CR_DESIGNER_REV_FIELD1 0x0018
	60
	61	#define PSB_CR_SOFT_RESET 0x0080
	62	#define _PSB_CS_RESET_TSP_RESET (1 << 6)
	63	#define _PSB_CS_RESET_ISP_RESET (1 << 5)
	64	#define _PSB_CS_RESET_USE_RESET (1 << 4)
65	#define _PSB_CS_RESET_TA_RESET (1 << 3)
66	#define _PSB_CS_RESET_DPM_RESET (1 << 2)
67	#define _PSB_CS_RESET_TWOD_RESET (1 << 1)
68	#define _PSB_CS_RESET_BIF_RESET (1 << 0)
69
70	#define PSB_CR_DESIGNER_REV_FIELD2 0x001C
71
72	#define PSB_CR_EVENT_HOST_ENABLE2 0x0110
73
74	#define PSB_CR_EVENT_STATUS2 0x0118
75
76	#define PSB_CR_EVENT_HOST_CLEAR2 0x0114
77	#define _PSB_CE2_BIF_REQUESTER_FAULT (1 << 4)
78
79	#define PSB_CR_EVENT_STATUS 0x012C
80
81	#define PSB_CR_EVENT_HOST_ENABLE 0x0130
82
83	#define PSB_CR_EVENT_HOST_CLEAR 0x0134
84	#define _PSB_CE_MASTER_INTERRUPT (1 << 31)
85	#define _PSB_CE_TA_DPM_FAULT (1 << 28)
86	#define _PSB_CE_TWOD_COMPLETE (1 << 27)
87	#define _PSB_CE_DPM_OUT_OF_MEMORY_ZLS (1 << 25)
88	#define _PSB_CE_DPM_TA_MEM_FREE (1 << 24)
89	#define _PSB_CE_PIXELBE_END_RENDER (1 << 18)
90	#define _PSB_CE_SW_EVENT (1 << 14)
91	#define _PSB_CE_TA_FINISHED (1 << 13)
92	#define _PSB_CE_TA_TERMINATE (1 << 12)
93	#define _PSB_CE_DPM_REACHED_MEM_THRESH (1 << 3)
94	#define _PSB_CE_DPM_OUT_OF_MEMORY_GBL (1 << 2)
95	#define _PSB_CE_DPM_OUT_OF_MEMORY_MT (1 << 1)
96	#define _PSB_CE_DPM_3D_MEM_FREE (1 << 0)
97
98
99	#define PSB_USE_OFFSET_MASK 0x0007FFFF
100	#define PSB_USE_OFFSET_SIZE (PSB_USE_OFFSET_MASK + 1)
101	#define PSB_CR_USE_CODE_BASE0 0x0A0C
102	#define PSB_CR_USE_CODE_BASE1 0x0A10
103	#define PSB_CR_USE_CODE_BASE2 0x0A14
104	#define PSB_CR_USE_CODE_BASE3 0x0A18
105	#define PSB_CR_USE_CODE_BASE4 0x0A1C
106	#define PSB_CR_USE_CODE_BASE5 0x0A20
107	#define PSB_CR_USE_CODE_BASE6 0x0A24
108	#define PSB_CR_USE_CODE_BASE7 0x0A28
109	#define PSB_CR_USE_CODE_BASE8 0x0A2C
110	#define PSB_CR_USE_CODE_BASE9 0x0A30
111	#define PSB_CR_USE_CODE_BASE10 0x0A34
112	#define PSB_CR_USE_CODE_BASE11 0x0A38
113	#define PSB_CR_USE_CODE_BASE12 0x0A3C
114	#define PSB_CR_USE_CODE_BASE13 0x0A40
115	#define PSB_CR_USE_CODE_BASE14 0x0A44
116	#define PSB_CR_USE_CODE_BASE15 0x0A48
117	#define PSB_CR_USE_CODE_BASE(_i) (0x0A0C + ((_i) << 2))
118	#define _PSB_CUC_BASE_DM_SHIFT (25)
119	#define _PSB_CUC_BASE_DM_MASK (0x3 << 25)
120	#define _PSB_CUC_BASE_ADDR_SHIFT (0) /* 1024-bit aligned address? */
121	#define _PSB_CUC_BASE_ADDR_ALIGNSHIFT (7)
122	#define _PSB_CUC_BASE_ADDR_MASK (0x1FFFFFF << 0)
123	#define _PSB_CUC_DM_VERTEX (0)
124	#define _PSB_CUC_DM_PIXEL (1)
125	#define _PSB_CUC_DM_RESERVED (2)
126	#define _PSB_CUC_DM_EDM (3)
127
128	#define PSB_CR_PDS_EXEC_BASE 0x0AB8
129	#define _PSB_CR_PDS_EXEC_BASE_ADDR_SHIFT (20) /* 1MB aligned address */
130	#define _PSB_CR_PDS_EXEC_BASE_ADDR_ALIGNSHIFT (20)
131
132	#define PSB_CR_EVENT_KICKER 0x0AC4
133	#define _PSB_CE_KICKER_ADDRESS_SHIFT (4) /* 128-bit aligned address */
134
135	#define PSB_CR_EVENT_KICK 0x0AC8
136	#define _PSB_CE_KICK_NOW (1 << 0)
137
138	#define PSB_CR_BIF_DIR_LIST_BASE1 0x0C38
139
140	#define PSB_CR_BIF_CTRL 0x0C00
141	#define _PSB_CB_CTRL_CLEAR_FAULT (1 << 4)
142	#define _PSB_CB_CTRL_INVALDC (1 << 3)
143	#define _PSB_CB_CTRL_FLUSH (1 << 2)
144
145	#define PSB_CR_BIF_INT_STAT 0x0C04
146
147	#define PSB_CR_BIF_FAULT 0x0C08
148	#define _PSB_CBI_STAT_PF_N_RW (1 << 14)
149	#define _PSB_CBI_STAT_FAULT_SHIFT (0)
150	#define _PSB_CBI_STAT_FAULT_MASK (0x3FFF << 0)
151	#define _PSB_CBI_STAT_FAULT_CACHE (1 << 1)
152	#define _PSB_CBI_STAT_FAULT_TA (1 << 2)
153	#define _PSB_CBI_STAT_FAULT_VDM (1 << 3)
154	#define _PSB_CBI_STAT_FAULT_2D (1 << 4)
155	#define _PSB_CBI_STAT_FAULT_PBE (1 << 5)
156	#define _PSB_CBI_STAT_FAULT_TSP (1 << 6)
157	#define _PSB_CBI_STAT_FAULT_ISP (1 << 7)
158	#define _PSB_CBI_STAT_FAULT_USSEPDS (1 << 8)
159	#define _PSB_CBI_STAT_FAULT_HOST (1 << 9)
160
161	#define PSB_CR_BIF_BANK0 0x0C78
162	#define PSB_CR_BIF_BANK1 0x0C7C
163	#define PSB_CR_BIF_DIR_LIST_BASE0 0x0C84
164	#define PSB_CR_BIF_TWOD_REQ_BASE 0x0C88
165	#define PSB_CR_BIF_3D_REQ_BASE 0x0CAC
166
167	#define PSB_CR_2D_SOCIF 0x0E18
168	#define _PSB_C2_SOCIF_FREESPACE_SHIFT (0)
169	#define _PSB_C2_SOCIF_FREESPACE_MASK (0xFF << 0)
170	#define _PSB_C2_SOCIF_EMPTY (0x80 << 0)
171
172	#define PSB_CR_2D_BLIT_STATUS 0x0E04
173	#define _PSB_C2B_STATUS_BUSY (1 << 24)
174	#define _PSB_C2B_STATUS_COMPLETE_SHIFT (0)
175	#define _PSB_C2B_STATUS_COMPLETE_MASK (0xFFFFFF << 0)
176
177	/*
178	* 2D defs.
179	*/
180
181	/*
182	* 2D Slave Port Data : Block Header's Object Type
183	*/
184
185	#define PSB_2D_CLIP_BH (0x00000000)
186	#define PSB_2D_PAT_BH (0x10000000)
187	#define PSB_2D_CTRL_BH (0x20000000)
188	#define PSB_2D_SRC_OFF_BH (0x30000000)
189	#define PSB_2D_MASK_OFF_BH (0x40000000)
190	#define PSB_2D_RESERVED1_BH (0x50000000)
191	#define PSB_2D_RESERVED2_BH (0x60000000)
192	#define PSB_2D_FENCE_BH (0x70000000)
193	#define PSB_2D_BLIT_BH (0x80000000)
194	#define PSB_2D_SRC_SURF_BH (0x90000000)
195	#define PSB_2D_DST_SURF_BH (0xA0000000)
196	#define PSB_2D_PAT_SURF_BH (0xB0000000)
197	#define PSB_2D_SRC_PAL_BH (0xC0000000)
198	#define PSB_2D_PAT_PAL_BH (0xD0000000)
199	#define PSB_2D_MASK_SURF_BH (0xE0000000)
200	#define PSB_2D_FLUSH_BH (0xF0000000)
201
202	/*
203	* Clip Definition block (PSB_2D_CLIP_BH)
204	*/
205	#define PSB_2D_CLIPCOUNT_MAX (1)
206	#define PSB_2D_CLIPCOUNT_MASK (0x00000000)
207	#define PSB_2D_CLIPCOUNT_CLRMASK (0xFFFFFFFF)
208	#define PSB_2D_CLIPCOUNT_SHIFT (0)
209	/* clip rectangle min & max */
210	#define PSB_2D_CLIP_XMAX_MASK (0x00FFF000)
211	#define PSB_2D_CLIP_XMAX_CLRMASK (0xFF000FFF)
212	#define PSB_2D_CLIP_XMAX_SHIFT (12)
213	#define PSB_2D_CLIP_XMIN_MASK (0x00000FFF)
214	#define PSB_2D_CLIP_XMIN_CLRMASK (0x00FFF000)
215	#define PSB_2D_CLIP_XMIN_SHIFT (0)
216	/* clip rectangle offset */
217	#define PSB_2D_CLIP_YMAX_MASK (0x00FFF000)
218	#define PSB_2D_CLIP_YMAX_CLRMASK (0xFF000FFF)
219	#define PSB_2D_CLIP_YMAX_SHIFT (12)
220	#define PSB_2D_CLIP_YMIN_MASK (0x00000FFF)
221	#define PSB_2D_CLIP_YMIN_CLRMASK (0x00FFF000)
222	#define PSB_2D_CLIP_YMIN_SHIFT (0)
223
224	/*
225	* Pattern Control (PSB_2D_PAT_BH)
226	*/
227	#define PSB_2D_PAT_HEIGHT_MASK (0x0000001F)
228	#define PSB_2D_PAT_HEIGHT_SHIFT (0)
229	#define PSB_2D_PAT_WIDTH_MASK (0x000003E0)
230	#define PSB_2D_PAT_WIDTH_SHIFT (5)
231	#define PSB_2D_PAT_YSTART_MASK (0x00007C00)
232	#define PSB_2D_PAT_YSTART_SHIFT (10)
233	#define PSB_2D_PAT_XSTART_MASK (0x000F8000)
234	#define PSB_2D_PAT_XSTART_SHIFT (15)
235
236	/*
237	* 2D Control block (PSB_2D_CTRL_BH)
238	*/
239	/* Present Flags */
240	#define PSB_2D_SRCCK_CTRL (0x00000001)
241	#define PSB_2D_DSTCK_CTRL (0x00000002)
242	#define PSB_2D_ALPHA_CTRL (0x00000004)
243	/* Colour Key Colour (SRC/DST)*/
244	#define PSB_2D_CK_COL_MASK (0xFFFFFFFF)
245	#define PSB_2D_CK_COL_CLRMASK (0x00000000)
246	#define PSB_2D_CK_COL_SHIFT (0)
247	/* Colour Key Mask (SRC/DST)*/
248	#define PSB_2D_CK_MASK_MASK (0xFFFFFFFF)
249	#define PSB_2D_CK_MASK_CLRMASK (0x00000000)
250	#define PSB_2D_CK_MASK_SHIFT (0)
251	/* Alpha Control (Alpha/RGB)*/
252	#define PSB_2D_GBLALPHA_MASK (0x000FF000)
253	#define PSB_2D_GBLALPHA_CLRMASK (0xFFF00FFF)
254	#define PSB_2D_GBLALPHA_SHIFT (12)
255	#define PSB_2D_SRCALPHA_OP_MASK (0x00700000)
256	#define PSB_2D_SRCALPHA_OP_CLRMASK (0xFF8FFFFF)
257	#define PSB_2D_SRCALPHA_OP_SHIFT (20)
258	#define PSB_2D_SRCALPHA_OP_ONE (0x00000000)
259	#define PSB_2D_SRCALPHA_OP_SRC (0x00100000)
260	#define PSB_2D_SRCALPHA_OP_DST (0x00200000)
261	#define PSB_2D_SRCALPHA_OP_SG (0x00300000)
262	#define PSB_2D_SRCALPHA_OP_DG (0x00400000)
263	#define PSB_2D_SRCALPHA_OP_GBL (0x00500000)
264	#define PSB_2D_SRCALPHA_OP_ZERO (0x00600000)
265	#define PSB_2D_SRCALPHA_INVERT (0x00800000)
266	#define PSB_2D_SRCALPHA_INVERT_CLR (0xFF7FFFFF)
267	#define PSB_2D_DSTALPHA_OP_MASK (0x07000000)
268	#define PSB_2D_DSTALPHA_OP_CLRMASK (0xF8FFFFFF)
269	#define PSB_2D_DSTALPHA_OP_SHIFT (24)
270	#define PSB_2D_DSTALPHA_OP_ONE (0x00000000)
271	#define PSB_2D_DSTALPHA_OP_SRC (0x01000000)
272	#define PSB_2D_DSTALPHA_OP_DST (0x02000000)
273	#define PSB_2D_DSTALPHA_OP_SG (0x03000000)
274	#define PSB_2D_DSTALPHA_OP_DG (0x04000000)
275	#define PSB_2D_DSTALPHA_OP_GBL (0x05000000)
276	#define PSB_2D_DSTALPHA_OP_ZERO (0x06000000)
277	#define PSB_2D_DSTALPHA_INVERT (0x08000000)
278	#define PSB_2D_DSTALPHA_INVERT_CLR (0xF7FFFFFF)
279
280	#define PSB_2D_PRE_MULTIPLICATION_ENABLE (0x10000000)
281	#define PSB_2D_PRE_MULTIPLICATION_CLRMASK (0xEFFFFFFF)
282	#define PSB_2D_ZERO_SOURCE_ALPHA_ENABLE (0x20000000)
283	#define PSB_2D_ZERO_SOURCE_ALPHA_CLRMASK (0xDFFFFFFF)
284
285	/*
286	*Source Offset (PSB_2D_SRC_OFF_BH)
287	*/
288	#define PSB_2D_SRCOFF_XSTART_MASK ((0x00000FFF) << 12)
289	#define PSB_2D_SRCOFF_XSTART_SHIFT (12)
290	#define PSB_2D_SRCOFF_YSTART_MASK (0x00000FFF)
291	#define PSB_2D_SRCOFF_YSTART_SHIFT (0)
292
293	/*
294	* Mask Offset (PSB_2D_MASK_OFF_BH)
295	*/
296	#define PSB_2D_MASKOFF_XSTART_MASK ((0x00000FFF) << 12)
297	#define PSB_2D_MASKOFF_XSTART_SHIFT (12)
298	#define PSB_2D_MASKOFF_YSTART_MASK (0x00000FFF)
299	#define PSB_2D_MASKOFF_YSTART_SHIFT (0)
300
301	/*
302	* 2D Fence (see PSB_2D_FENCE_BH): bits 0:27 are ignored
303	*/
304
305	/*
306	*Blit Rectangle (PSB_2D_BLIT_BH)
307	*/
308
309	#define PSB_2D_ROT_MASK (3 << 25)
310	#define PSB_2D_ROT_CLRMASK (~PSB_2D_ROT_MASK)
311	#define PSB_2D_ROT_NONE (0 << 25)
312	#define PSB_2D_ROT_90DEGS (1 << 25)
313	#define PSB_2D_ROT_180DEGS (2 << 25)
314	#define PSB_2D_ROT_270DEGS (3 << 25)
315
316	#define PSB_2D_COPYORDER_MASK (3 << 23)
317	#define PSB_2D_COPYORDER_CLRMASK (~PSB_2D_COPYORDER_MASK)
318	#define PSB_2D_COPYORDER_TL2BR (0 << 23)
319	#define PSB_2D_COPYORDER_BR2TL (1 << 23)
320	#define PSB_2D_COPYORDER_TR2BL (2 << 23)
321	#define PSB_2D_COPYORDER_BL2TR (3 << 23)
322
323	#define PSB_2D_DSTCK_CLRMASK (0xFF9FFFFF)
324	#define PSB_2D_DSTCK_DISABLE (0x00000000)
325	#define PSB_2D_DSTCK_PASS (0x00200000)
326	#define PSB_2D_DSTCK_REJECT (0x00400000)
327
328	#define PSB_2D_SRCCK_CLRMASK (0xFFE7FFFF)
329	#define PSB_2D_SRCCK_DISABLE (0x00000000)
330	#define PSB_2D_SRCCK_PASS (0x00080000)
331	#define PSB_2D_SRCCK_REJECT (0x00100000)
332
333	#define PSB_2D_CLIP_ENABLE (0x00040000)
334
335	#define PSB_2D_ALPHA_ENABLE (0x00020000)
336
337	#define PSB_2D_PAT_CLRMASK (0xFFFEFFFF)
338	#define PSB_2D_PAT_MASK (0x00010000)
339	#define PSB_2D_USE_PAT (0x00010000)
340	#define PSB_2D_USE_FILL (0x00000000)
341	/*
342	* Tungsten Graphics note on rop codes: If rop A and rop B are
343	* identical, the mask surface will not be read and need not be
344	* set up.
345	*/
346
347	#define PSB_2D_ROP3B_MASK (0x0000FF00)
348	#define PSB_2D_ROP3B_CLRMASK (0xFFFF00FF)
349	#define PSB_2D_ROP3B_SHIFT (8)
350	/* rop code A */
351	#define PSB_2D_ROP3A_MASK (0x000000FF)
352	#define PSB_2D_ROP3A_CLRMASK (0xFFFFFF00)
353	#define PSB_2D_ROP3A_SHIFT (0)
354
355	#define PSB_2D_ROP4_MASK (0x0000FFFF)
356	/*
357	* DWORD0: (Only pass if Pattern control == Use Fill Colour)
358	* Fill Colour RGBA8888
359	*/
360	#define PSB_2D_FILLCOLOUR_MASK (0xFFFFFFFF)
361	#define PSB_2D_FILLCOLOUR_SHIFT (0)
362	/*
363	* DWORD1: (Always Present)
364	* X Start (Dest)
365	* Y Start (Dest)
366	*/
367	#define PSB_2D_DST_XSTART_MASK (0x00FFF000)
368	#define PSB_2D_DST_XSTART_CLRMASK (0xFF000FFF)
369	#define PSB_2D_DST_XSTART_SHIFT (12)
370	#define PSB_2D_DST_YSTART_MASK (0x00000FFF)
371	#define PSB_2D_DST_YSTART_CLRMASK (0xFFFFF000)
372	#define PSB_2D_DST_YSTART_SHIFT (0)
373	/*
374	* DWORD2: (Always Present)
375	* X Size (Dest)
376	* Y Size (Dest)
377	*/
378	#define PSB_2D_DST_XSIZE_MASK (0x00FFF000)
379	#define PSB_2D_DST_XSIZE_CLRMASK (0xFF000FFF)
380	#define PSB_2D_DST_XSIZE_SHIFT (12)
381	#define PSB_2D_DST_YSIZE_MASK (0x00000FFF)
382	#define PSB_2D_DST_YSIZE_CLRMASK (0xFFFFF000)
383	#define PSB_2D_DST_YSIZE_SHIFT (0)
384
385	/*
386	* Source Surface (PSB_2D_SRC_SURF_BH)
387	*/
388	/*
389	* WORD 0
390	*/
391
392	#define PSB_2D_SRC_FORMAT_MASK (0x00078000)
393	#define PSB_2D_SRC_1_PAL (0x00000000)
394	#define PSB_2D_SRC_2_PAL (0x00008000)
395	#define PSB_2D_SRC_4_PAL (0x00010000)
396	#define PSB_2D_SRC_8_PAL (0x00018000)
397	#define PSB_2D_SRC_8_ALPHA (0x00020000)
398	#define PSB_2D_SRC_4_ALPHA (0x00028000)
399	#define PSB_2D_SRC_332RGB (0x00030000)
400	#define PSB_2D_SRC_4444ARGB (0x00038000)
401	#define PSB_2D_SRC_555RGB (0x00040000)
402	#define PSB_2D_SRC_1555ARGB (0x00048000)
403	#define PSB_2D_SRC_565RGB (0x00050000)
404	#define PSB_2D_SRC_0888ARGB (0x00058000)
405	#define PSB_2D_SRC_8888ARGB (0x00060000)
406	#define PSB_2D_SRC_8888UYVY (0x00068000)
407	#define PSB_2D_SRC_RESERVED (0x00070000)
408	#define PSB_2D_SRC_1555ARGB_LOOKUP (0x00078000)
409
410
411	#define PSB_2D_SRC_STRIDE_MASK (0x00007FFF)
412	#define PSB_2D_SRC_STRIDE_CLRMASK (0xFFFF8000)
413	#define PSB_2D_SRC_STRIDE_SHIFT (0)
414	/*
415	* WORD 1 - Base Address
416	*/
417	#define PSB_2D_SRC_ADDR_MASK (0x0FFFFFFC)
418	#define PSB_2D_SRC_ADDR_CLRMASK (0x00000003)
419	#define PSB_2D_SRC_ADDR_SHIFT (2)
420	#define PSB_2D_SRC_ADDR_ALIGNSHIFT (2)
421
422	/*
423	* Pattern Surface (PSB_2D_PAT_SURF_BH)
424	*/
425	/*
426	* WORD 0
427	*/
428
429	#define PSB_2D_PAT_FORMAT_MASK (0x00078000)
430	#define PSB_2D_PAT_1_PAL (0x00000000)
431	#define PSB_2D_PAT_2_PAL (0x00008000)
432	#define PSB_2D_PAT_4_PAL (0x00010000)
433	#define PSB_2D_PAT_8_PAL (0x00018000)
434	#define PSB_2D_PAT_8_ALPHA (0x00020000)
435	#define PSB_2D_PAT_4_ALPHA (0x00028000)
436	#define PSB_2D_PAT_332RGB (0x00030000)
437	#define PSB_2D_PAT_4444ARGB (0x00038000)
438	#define PSB_2D_PAT_555RGB (0x00040000)
439	#define PSB_2D_PAT_1555ARGB (0x00048000)
440	#define PSB_2D_PAT_565RGB (0x00050000)
441	#define PSB_2D_PAT_0888ARGB (0x00058000)
442	#define PSB_2D_PAT_8888ARGB (0x00060000)
443
444	#define PSB_2D_PAT_STRIDE_MASK (0x00007FFF)
445	#define PSB_2D_PAT_STRIDE_CLRMASK (0xFFFF8000)
446	#define PSB_2D_PAT_STRIDE_SHIFT (0)
447	/*
448	* WORD 1 - Base Address
449	*/
450	#define PSB_2D_PAT_ADDR_MASK (0x0FFFFFFC)
451	#define PSB_2D_PAT_ADDR_CLRMASK (0x00000003)
452	#define PSB_2D_PAT_ADDR_SHIFT (2)
453	#define PSB_2D_PAT_ADDR_ALIGNSHIFT (2)
454
455	/*
456	* Destination Surface (PSB_2D_DST_SURF_BH)
457	*/
458	/*
459	* WORD 0
460	*/
461
462	#define PSB_2D_DST_FORMAT_MASK (0x00078000)
463	#define PSB_2D_DST_332RGB (0x00030000)
464	#define PSB_2D_DST_4444ARGB (0x00038000)
465	#define PSB_2D_DST_555RGB (0x00040000)
466	#define PSB_2D_DST_1555ARGB (0x00048000)
467	#define PSB_2D_DST_565RGB (0x00050000)
468	#define PSB_2D_DST_0888ARGB (0x00058000)
469	#define PSB_2D_DST_8888ARGB (0x00060000)
470	#define PSB_2D_DST_8888AYUV (0x00070000)
471
472	#define PSB_2D_DST_STRIDE_MASK (0x00007FFF)
473	#define PSB_2D_DST_STRIDE_CLRMASK (0xFFFF8000)
474	#define PSB_2D_DST_STRIDE_SHIFT (0)
475	/*
476	* WORD 1 - Base Address
477	*/
478	#define PSB_2D_DST_ADDR_MASK (0x0FFFFFFC)
479	#define PSB_2D_DST_ADDR_CLRMASK (0x00000003)
480	#define PSB_2D_DST_ADDR_SHIFT (2)
481	#define PSB_2D_DST_ADDR_ALIGNSHIFT (2)
482
483	/*
484	* Mask Surface (PSB_2D_MASK_SURF_BH)
485	*/
486	/*
487	* WORD 0
488	*/
489	#define PSB_2D_MASK_STRIDE_MASK (0x00007FFF)
490	#define PSB_2D_MASK_STRIDE_CLRMASK (0xFFFF8000)
491	#define PSB_2D_MASK_STRIDE_SHIFT (0)
492	/*
493	* WORD 1 - Base Address
494	*/
495	#define PSB_2D_MASK_ADDR_MASK (0x0FFFFFFC)
496	#define PSB_2D_MASK_ADDR_CLRMASK (0x00000003)
497	#define PSB_2D_MASK_ADDR_SHIFT (2)
498	#define PSB_2D_MASK_ADDR_ALIGNSHIFT (2)
499
500	/*
501	* Source Palette (PSB_2D_SRC_PAL_BH)
502	*/
503
504	#define PSB_2D_SRCPAL_ADDR_SHIFT (0)
505	#define PSB_2D_SRCPAL_ADDR_CLRMASK (0xF0000007)
506	#define PSB_2D_SRCPAL_ADDR_MASK (0x0FFFFFF8)
507	#define PSB_2D_SRCPAL_BYTEALIGN (1024)
508
509	/*
510	* Pattern Palette (PSB_2D_PAT_PAL_BH)
511	*/
512
513	#define PSB_2D_PATPAL_ADDR_SHIFT (0)
514	#define PSB_2D_PATPAL_ADDR_CLRMASK (0xF0000007)
515	#define PSB_2D_PATPAL_ADDR_MASK (0x0FFFFFF8)
516	#define PSB_2D_PATPAL_BYTEALIGN (1024)
517
518	/*
519	* Rop3 Codes (2 LS bytes)
520	*/
521
522	#define PSB_2D_ROP3_SRCCOPY (0xCCCC)
523	#define PSB_2D_ROP3_PATCOPY (0xF0F0)
524	#define PSB_2D_ROP3_WHITENESS (0xFFFF)
525	#define PSB_2D_ROP3_BLACKNESS (0x0000)
526	#define PSB_2D_ROP3_SRC (0xCC)
527	#define PSB_2D_ROP3_PAT (0xF0)
528	#define PSB_2D_ROP3_DST (0xAA)
529
530	/*
531	* Sizes.
532	*/
533
534	#define PSB_SCENE_HW_COOKIE_SIZE 16
535	#define PSB_TA_MEM_HW_COOKIE_SIZE 16
536
537	/*
538	* Scene stuff.
539	*/
540
541	#define PSB_NUM_HW_SCENES 2
542
543	/*
544	* Scheduler completion actions.
545	*/
546
547	#define PSB_RASTER_BLOCK 0
548	#define PSB_RASTER 1
549	#define PSB_RETURN 2
550	#define PSB_TA 3
551
552	/* Power management */
553	#define PSB_PUNIT_PORT 0x04
554	#define PSB_OSPMBA 0x78
555	#define PSB_APMBA 0x7a
556	#define PSB_APM_CMD 0x0
557	#define PSB_APM_STS 0x04
558	#define PSB_PWRGT_VID_ENC_MASK 0x30
559	#define PSB_PWRGT_VID_DEC_MASK 0xc
560	#define PSB_PWRGT_GL3_MASK 0xc0
561
562	#define PSB_PM_SSC 0x20
563	#define PSB_PM_SSS 0x30
564	#define PSB_PWRGT_DISPLAY_MASK 0xc /on a different BA than video/gfx/
565	#define MDFLD_PWRGT_DISPLAY_A_CNTR 0x0000000c
566	#define MDFLD_PWRGT_DISPLAY_B_CNTR 0x0000c000
567	#define MDFLD_PWRGT_DISPLAY_C_CNTR 0x00030000
568	#define MDFLD_PWRGT_DISP_MIPI_CNTR 0x000c0000
569	#define MDFLD_PWRGT_DISPLAY_CNTR (MDFLD_PWRGT_DISPLAY_A_CNTR \| MDFLD_PWRGT_DISPLAY_B_CNTR \| MDFLD_PWRGT_DISPLAY_C_CNTR \| MDFLD_PWRGT_DISP_MIPI_CNTR) /* 0x000fc00c */
570	/* Display SSS register bits are different in A0 vs. B0 */
571	#define PSB_PWRGT_GFX_MASK 0x3
572	#define MDFLD_PWRGT_DISPLAY_A_STS 0x000000c0
573	#define MDFLD_PWRGT_DISPLAY_B_STS 0x00000300
574	#define MDFLD_PWRGT_DISPLAY_C_STS 0x00000c00
575	#define PSB_PWRGT_GFX_MASK_B0 0xc3
576	#define MDFLD_PWRGT_DISPLAY_A_STS_B0 0x0000000c
577	#define MDFLD_PWRGT_DISPLAY_B_STS_B0 0x0000c000
578	#define MDFLD_PWRGT_DISPLAY_C_STS_B0 0x00030000
579	#define MDFLD_PWRGT_DISP_MIPI_STS 0x000c0000
580	#define MDFLD_PWRGT_DISPLAY_STS_A0 (MDFLD_PWRGT_DISPLAY_A_STS \| MDFLD_PWRGT_DISPLAY_B_STS \| MDFLD_PWRGT_DISPLAY_C_STS \| MDFLD_PWRGT_DISP_MIPI_STS) /* 0x000fc00c */
581	#define MDFLD_PWRGT_DISPLAY_STS_B0 (MDFLD_PWRGT_DISPLAY_A_STS_B0 \| MDFLD_PWRGT_DISPLAY_B_STS_B0 \| MDFLD_PWRGT_DISPLAY_C_STS_B0 \| MDFLD_PWRGT_DISP_MIPI_STS) /* 0x000fc00c */
582	#endif