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drm/i2c: tda998x: clean up error chip version checking
[deliverable/linux.git] / drivers / gpu / drm / i2c / tda998x_drv.c
CommitLineData
e7792ce2
RC		 1/*
2 * Copyright (C) 2012 Texas Instruments
3 * Author: Rob Clark <robdclark@gmail.com>
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 as published by
7 * the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program. If not, see <http://www.gnu.org/licenses/>.
16 */
17
18
19
893c3e53 20#include <linux/hdmi.h>
e7792ce2 21#include <linux/module.h>
f0b33b28 22#include <sound/asoundef.h>
e7792ce2
RC		 23
24#include <drm/drmP.h>
25#include <drm/drm_crtc_helper.h>
26#include <drm/drm_encoder_slave.h>
27#include <drm/drm_edid.h>
c4c11dd1 28#include <drm/i2c/tda998x.h>
e7792ce2
RC		 29
30#define DBG(fmt, ...) DRM_DEBUG(fmt"\n", ##__VA_ARGS__)
31
32struct tda998x_priv {
33 struct i2c_client *cec;
2f7f730a 34 struct i2c_client *hdmi;
e7792ce2
RC		 35 uint16_t rev;
36 uint8_t current_page;
37 int dpms;
c4c11dd1 38 bool is_hdmi_sink;
5e74c22c
RK		 39 u8 vip_cntrl_0;
40 u8 vip_cntrl_1;
41 u8 vip_cntrl_2;
c4c11dd1 42 struct tda998x_encoder_params params;
e7792ce2
RC		 43};
44
45#define to_tda998x_priv(x) ((struct tda998x_priv *)to_encoder_slave(x)->slave_priv)
46
47/* The TDA9988 series of devices use a paged register scheme.. to simplify
48 * things we encode the page # in upper bits of the register #. To read/
49 * write a given register, we need to make sure CURPAGE register is set
50 * appropriately. Which implies reads/writes are not atomic. Fun!
51 */
52
53#define REG(page, addr) (((page) << 8) | (addr))
54#define REG2ADDR(reg) ((reg) & 0xff)
55#define REG2PAGE(reg) (((reg) >> 8) & 0xff)
56
57#define REG_CURPAGE 0xff /* write */
58
59
60/* Page 00h: General Control */
61#define REG_VERSION_LSB REG(0x00, 0x00) /* read */
62#define REG_MAIN_CNTRL0 REG(0x00, 0x01) /* read/write */
63# define MAIN_CNTRL0_SR (1 << 0)
64# define MAIN_CNTRL0_DECS (1 << 1)
65# define MAIN_CNTRL0_DEHS (1 << 2)
66# define MAIN_CNTRL0_CECS (1 << 3)
67# define MAIN_CNTRL0_CEHS (1 << 4)
68# define MAIN_CNTRL0_SCALER (1 << 7)
69#define REG_VERSION_MSB REG(0x00, 0x02) /* read */
70#define REG_SOFTRESET REG(0x00, 0x0a) /* write */
71# define SOFTRESET_AUDIO (1 << 0)
72# define SOFTRESET_I2C_MASTER (1 << 1)
73#define REG_DDC_DISABLE REG(0x00, 0x0b) /* read/write */
74#define REG_CCLK_ON REG(0x00, 0x0c) /* read/write */
75#define REG_I2C_MASTER REG(0x00, 0x0d) /* read/write */
76# define I2C_MASTER_DIS_MM (1 << 0)
77# define I2C_MASTER_DIS_FILT (1 << 1)
78# define I2C_MASTER_APP_STRT_LAT (1 << 2)
c4c11dd1
RK		 79#define REG_FEAT_POWERDOWN REG(0x00, 0x0e) /* read/write */
80# define FEAT_POWERDOWN_SPDIF (1 << 3)
e7792ce2
RC		 81#define REG_INT_FLAGS_0 REG(0x00, 0x0f) /* read/write */
82#define REG_INT_FLAGS_1 REG(0x00, 0x10) /* read/write */
83#define REG_INT_FLAGS_2 REG(0x00, 0x11) /* read/write */
84# define INT_FLAGS_2_EDID_BLK_RD (1 << 1)
c4c11dd1 85#define REG_ENA_ACLK REG(0x00, 0x16) /* read/write */
e7792ce2
RC		 86#define REG_ENA_VP_0 REG(0x00, 0x18) /* read/write */
87#define REG_ENA_VP_1 REG(0x00, 0x19) /* read/write */
88#define REG_ENA_VP_2 REG(0x00, 0x1a) /* read/write */
89#define REG_ENA_AP REG(0x00, 0x1e) /* read/write */
90#define REG_VIP_CNTRL_0 REG(0x00, 0x20) /* write */
91# define VIP_CNTRL_0_MIRR_A (1 << 7)
92# define VIP_CNTRL_0_SWAP_A(x) (((x) & 7) << 4)
93# define VIP_CNTRL_0_MIRR_B (1 << 3)
94# define VIP_CNTRL_0_SWAP_B(x) (((x) & 7) << 0)
95#define REG_VIP_CNTRL_1 REG(0x00, 0x21) /* write */
96# define VIP_CNTRL_1_MIRR_C (1 << 7)
97# define VIP_CNTRL_1_SWAP_C(x) (((x) & 7) << 4)
98# define VIP_CNTRL_1_MIRR_D (1 << 3)
99# define VIP_CNTRL_1_SWAP_D(x) (((x) & 7) << 0)
100#define REG_VIP_CNTRL_2 REG(0x00, 0x22) /* write */
101# define VIP_CNTRL_2_MIRR_E (1 << 7)
102# define VIP_CNTRL_2_SWAP_E(x) (((x) & 7) << 4)
103# define VIP_CNTRL_2_MIRR_F (1 << 3)
104# define VIP_CNTRL_2_SWAP_F(x) (((x) & 7) << 0)
105#define REG_VIP_CNTRL_3 REG(0x00, 0x23) /* write */
106# define VIP_CNTRL_3_X_TGL (1 << 0)
107# define VIP_CNTRL_3_H_TGL (1 << 1)
108# define VIP_CNTRL_3_V_TGL (1 << 2)
109# define VIP_CNTRL_3_EMB (1 << 3)
110# define VIP_CNTRL_3_SYNC_DE (1 << 4)
111# define VIP_CNTRL_3_SYNC_HS (1 << 5)
112# define VIP_CNTRL_3_DE_INT (1 << 6)
113# define VIP_CNTRL_3_EDGE (1 << 7)
114#define REG_VIP_CNTRL_4 REG(0x00, 0x24) /* write */
115# define VIP_CNTRL_4_BLC(x) (((x) & 3) << 0)
116# define VIP_CNTRL_4_BLANKIT(x) (((x) & 3) << 2)
117# define VIP_CNTRL_4_CCIR656 (1 << 4)
118# define VIP_CNTRL_4_656_ALT (1 << 5)
119# define VIP_CNTRL_4_TST_656 (1 << 6)
120# define VIP_CNTRL_4_TST_PAT (1 << 7)
121#define REG_VIP_CNTRL_5 REG(0x00, 0x25) /* write */
122# define VIP_CNTRL_5_CKCASE (1 << 0)
123# define VIP_CNTRL_5_SP_CNT(x) (((x) & 3) << 1)
c4c11dd1 124#define REG_MUX_AP REG(0x00, 0x26) /* read/write */
bcb2481d 125#define REG_MUX_VP_VIP_OUT REG(0x00, 0x27) /* read/write */
e7792ce2
RC		 126#define REG_MAT_CONTRL REG(0x00, 0x80) /* write */
127# define MAT_CONTRL_MAT_SC(x) (((x) & 3) << 0)
128# define MAT_CONTRL_MAT_BP (1 << 2)
129#define REG_VIDFORMAT REG(0x00, 0xa0) /* write */
130#define REG_REFPIX_MSB REG(0x00, 0xa1) /* write */
131#define REG_REFPIX_LSB REG(0x00, 0xa2) /* write */
132#define REG_REFLINE_MSB REG(0x00, 0xa3) /* write */
133#define REG_REFLINE_LSB REG(0x00, 0xa4) /* write */
134#define REG_NPIX_MSB REG(0x00, 0xa5) /* write */
135#define REG_NPIX_LSB REG(0x00, 0xa6) /* write */
136#define REG_NLINE_MSB REG(0x00, 0xa7) /* write */
137#define REG_NLINE_LSB REG(0x00, 0xa8) /* write */
138#define REG_VS_LINE_STRT_1_MSB REG(0x00, 0xa9) /* write */
139#define REG_VS_LINE_STRT_1_LSB REG(0x00, 0xaa) /* write */
140#define REG_VS_PIX_STRT_1_MSB REG(0x00, 0xab) /* write */
141#define REG_VS_PIX_STRT_1_LSB REG(0x00, 0xac) /* write */
142#define REG_VS_LINE_END_1_MSB REG(0x00, 0xad) /* write */
143#define REG_VS_LINE_END_1_LSB REG(0x00, 0xae) /* write */
144#define REG_VS_PIX_END_1_MSB REG(0x00, 0xaf) /* write */
145#define REG_VS_PIX_END_1_LSB REG(0x00, 0xb0) /* write */
088d61d1
SH		 146#define REG_VS_LINE_STRT_2_MSB REG(0x00, 0xb1) /* write */
147#define REG_VS_LINE_STRT_2_LSB REG(0x00, 0xb2) /* write */
e7792ce2
RC		 148#define REG_VS_PIX_STRT_2_MSB REG(0x00, 0xb3) /* write */
149#define REG_VS_PIX_STRT_2_LSB REG(0x00, 0xb4) /* write */
088d61d1
SH		 150#define REG_VS_LINE_END_2_MSB REG(0x00, 0xb5) /* write */
151#define REG_VS_LINE_END_2_LSB REG(0x00, 0xb6) /* write */
e7792ce2
RC		 152#define REG_VS_PIX_END_2_MSB REG(0x00, 0xb7) /* write */
153#define REG_VS_PIX_END_2_LSB REG(0x00, 0xb8) /* write */
154#define REG_HS_PIX_START_MSB REG(0x00, 0xb9) /* write */
155#define REG_HS_PIX_START_LSB REG(0x00, 0xba) /* write */
156#define REG_HS_PIX_STOP_MSB REG(0x00, 0xbb) /* write */
157#define REG_HS_PIX_STOP_LSB REG(0x00, 0xbc) /* write */
158#define REG_VWIN_START_1_MSB REG(0x00, 0xbd) /* write */
159#define REG_VWIN_START_1_LSB REG(0x00, 0xbe) /* write */
160#define REG_VWIN_END_1_MSB REG(0x00, 0xbf) /* write */
161#define REG_VWIN_END_1_LSB REG(0x00, 0xc0) /* write */
088d61d1
SH		 162#define REG_VWIN_START_2_MSB REG(0x00, 0xc1) /* write */
163#define REG_VWIN_START_2_LSB REG(0x00, 0xc2) /* write */
164#define REG_VWIN_END_2_MSB REG(0x00, 0xc3) /* write */
165#define REG_VWIN_END_2_LSB REG(0x00, 0xc4) /* write */
e7792ce2
RC		 166#define REG_DE_START_MSB REG(0x00, 0xc5) /* write */
167#define REG_DE_START_LSB REG(0x00, 0xc6) /* write */
168#define REG_DE_STOP_MSB REG(0x00, 0xc7) /* write */
169#define REG_DE_STOP_LSB REG(0x00, 0xc8) /* write */
170#define REG_TBG_CNTRL_0 REG(0x00, 0xca) /* write */
088d61d1
SH		 171# define TBG_CNTRL_0_TOP_TGL (1 << 0)
172# define TBG_CNTRL_0_TOP_SEL (1 << 1)
173# define TBG_CNTRL_0_DE_EXT (1 << 2)
174# define TBG_CNTRL_0_TOP_EXT (1 << 3)
e7792ce2
RC		 175# define TBG_CNTRL_0_FRAME_DIS (1 << 5)
176# define TBG_CNTRL_0_SYNC_MTHD (1 << 6)
177# define TBG_CNTRL_0_SYNC_ONCE (1 << 7)
178#define REG_TBG_CNTRL_1 REG(0x00, 0xcb) /* write */
088d61d1
SH		 179# define TBG_CNTRL_1_H_TGL (1 << 0)
180# define TBG_CNTRL_1_V_TGL (1 << 1)
181# define TBG_CNTRL_1_TGL_EN (1 << 2)
182# define TBG_CNTRL_1_X_EXT (1 << 3)
183# define TBG_CNTRL_1_H_EXT (1 << 4)
184# define TBG_CNTRL_1_V_EXT (1 << 5)
e7792ce2
RC		 185# define TBG_CNTRL_1_DWIN_DIS (1 << 6)
186#define REG_ENABLE_SPACE REG(0x00, 0xd6) /* write */
187#define REG_HVF_CNTRL_0 REG(0x00, 0xe4) /* write */
188# define HVF_CNTRL_0_SM (1 << 7)
189# define HVF_CNTRL_0_RWB (1 << 6)
190# define HVF_CNTRL_0_PREFIL(x) (((x) & 3) << 2)
191# define HVF_CNTRL_0_INTPOL(x) (((x) & 3) << 0)
192#define REG_HVF_CNTRL_1 REG(0x00, 0xe5) /* write */
193# define HVF_CNTRL_1_FOR (1 << 0)
194# define HVF_CNTRL_1_YUVBLK (1 << 1)
195# define HVF_CNTRL_1_VQR(x) (((x) & 3) << 2)
196# define HVF_CNTRL_1_PAD(x) (((x) & 3) << 4)
197# define HVF_CNTRL_1_SEMI_PLANAR (1 << 6)
198#define REG_RPT_CNTRL REG(0x00, 0xf0) /* write */
c4c11dd1
RK		 199#define REG_I2S_FORMAT REG(0x00, 0xfc) /* read/write */
200# define I2S_FORMAT(x) (((x) & 3) << 0)
201#define REG_AIP_CLKSEL REG(0x00, 0xfd) /* write */
202# define AIP_CLKSEL_FS(x) (((x) & 3) << 0)
203# define AIP_CLKSEL_CLK_POL(x) (((x) & 1) << 2)
204# define AIP_CLKSEL_AIP(x) (((x) & 7) << 3)
e7792ce2
RC		 205
206
207/* Page 02h: PLL settings */
208#define REG_PLL_SERIAL_1 REG(0x02, 0x00) /* read/write */
209# define PLL_SERIAL_1_SRL_FDN (1 << 0)
210# define PLL_SERIAL_1_SRL_IZ(x) (((x) & 3) << 1)
211# define PLL_SERIAL_1_SRL_MAN_IZ (1 << 6)
212#define REG_PLL_SERIAL_2 REG(0x02, 0x01) /* read/write */
3ae471f7 213# define PLL_SERIAL_2_SRL_NOSC(x) ((x) << 0)
e7792ce2
RC		 214# define PLL_SERIAL_2_SRL_PR(x) (((x) & 0xf) << 4)
215#define REG_PLL_SERIAL_3 REG(0x02, 0x02) /* read/write */
216# define PLL_SERIAL_3_SRL_CCIR (1 << 0)
217# define PLL_SERIAL_3_SRL_DE (1 << 2)
218# define PLL_SERIAL_3_SRL_PXIN_SEL (1 << 4)
219#define REG_SERIALIZER REG(0x02, 0x03) /* read/write */
220#define REG_BUFFER_OUT REG(0x02, 0x04) /* read/write */
221#define REG_PLL_SCG1 REG(0x02, 0x05) /* read/write */
222#define REG_PLL_SCG2 REG(0x02, 0x06) /* read/write */
223#define REG_PLL_SCGN1 REG(0x02, 0x07) /* read/write */
224#define REG_PLL_SCGN2 REG(0x02, 0x08) /* read/write */
225#define REG_PLL_SCGR1 REG(0x02, 0x09) /* read/write */
226#define REG_PLL_SCGR2 REG(0x02, 0x0a) /* read/write */
227#define REG_AUDIO_DIV REG(0x02, 0x0e) /* read/write */
c4c11dd1
RK		 228# define AUDIO_DIV_SERCLK_1 0
229# define AUDIO_DIV_SERCLK_2 1
230# define AUDIO_DIV_SERCLK_4 2
231# define AUDIO_DIV_SERCLK_8 3
232# define AUDIO_DIV_SERCLK_16 4
233# define AUDIO_DIV_SERCLK_32 5
e7792ce2
RC		 234#define REG_SEL_CLK REG(0x02, 0x11) /* read/write */
235# define SEL_CLK_SEL_CLK1 (1 << 0)
236# define SEL_CLK_SEL_VRF_CLK(x) (((x) & 3) << 1)
237# define SEL_CLK_ENA_SC_CLK (1 << 3)
238#define REG_ANA_GENERAL REG(0x02, 0x12) /* read/write */
239
240
241/* Page 09h: EDID Control */
242#define REG_EDID_DATA_0 REG(0x09, 0x00) /* read */
243/* next 127 successive registers are the EDID block */
244#define REG_EDID_CTRL REG(0x09, 0xfa) /* read/write */
245#define REG_DDC_ADDR REG(0x09, 0xfb) /* read/write */
246#define REG_DDC_OFFS REG(0x09, 0xfc) /* read/write */
247#define REG_DDC_SEGM_ADDR REG(0x09, 0xfd) /* read/write */
248#define REG_DDC_SEGM REG(0x09, 0xfe) /* read/write */
249
250
251/* Page 10h: information frames and packets */
c4c11dd1
RK		 252#define REG_IF1_HB0 REG(0x10, 0x20) /* read/write */
253#define REG_IF2_HB0 REG(0x10, 0x40) /* read/write */
254#define REG_IF3_HB0 REG(0x10, 0x60) /* read/write */
255#define REG_IF4_HB0 REG(0x10, 0x80) /* read/write */
256#define REG_IF5_HB0 REG(0x10, 0xa0) /* read/write */
e7792ce2
RC		 257
258
259/* Page 11h: audio settings and content info packets */
260#define REG_AIP_CNTRL_0 REG(0x11, 0x00) /* read/write */
261# define AIP_CNTRL_0_RST_FIFO (1 << 0)
262# define AIP_CNTRL_0_SWAP (1 << 1)
263# define AIP_CNTRL_0_LAYOUT (1 << 2)
264# define AIP_CNTRL_0_ACR_MAN (1 << 5)
265# define AIP_CNTRL_0_RST_CTS (1 << 6)
c4c11dd1
RK		 266#define REG_CA_I2S REG(0x11, 0x01) /* read/write */
267# define CA_I2S_CA_I2S(x) (((x) & 31) << 0)
268# define CA_I2S_HBR_CHSTAT (1 << 6)
269#define REG_LATENCY_RD REG(0x11, 0x04) /* read/write */
270#define REG_ACR_CTS_0 REG(0x11, 0x05) /* read/write */
271#define REG_ACR_CTS_1 REG(0x11, 0x06) /* read/write */
272#define REG_ACR_CTS_2 REG(0x11, 0x07) /* read/write */
273#define REG_ACR_N_0 REG(0x11, 0x08) /* read/write */
274#define REG_ACR_N_1 REG(0x11, 0x09) /* read/write */
275#define REG_ACR_N_2 REG(0x11, 0x0a) /* read/write */
276#define REG_CTS_N REG(0x11, 0x0c) /* read/write */
277# define CTS_N_K(x) (((x) & 7) << 0)
278# define CTS_N_M(x) (((x) & 3) << 4)
e7792ce2
RC		 279#define REG_ENC_CNTRL REG(0x11, 0x0d) /* read/write */
280# define ENC_CNTRL_RST_ENC (1 << 0)
281# define ENC_CNTRL_RST_SEL (1 << 1)
282# define ENC_CNTRL_CTL_CODE(x) (((x) & 3) << 2)
c4c11dd1
RK		 283#define REG_DIP_FLAGS REG(0x11, 0x0e) /* read/write */
284# define DIP_FLAGS_ACR (1 << 0)
285# define DIP_FLAGS_GC (1 << 1)
286#define REG_DIP_IF_FLAGS REG(0x11, 0x0f) /* read/write */
287# define DIP_IF_FLAGS_IF1 (1 << 1)
288# define DIP_IF_FLAGS_IF2 (1 << 2)
289# define DIP_IF_FLAGS_IF3 (1 << 3)
290# define DIP_IF_FLAGS_IF4 (1 << 4)
291# define DIP_IF_FLAGS_IF5 (1 << 5)
292#define REG_CH_STAT_B(x) REG(0x11, 0x14 + (x)) /* read/write */
e7792ce2
RC		 293
294
295/* Page 12h: HDCP and OTP */
296#define REG_TX3 REG(0x12, 0x9a) /* read/write */
063b472f
RK		 297#define REG_TX4 REG(0x12, 0x9b) /* read/write */
298# define TX4_PD_RAM (1 << 1)
e7792ce2
RC		 299#define REG_TX33 REG(0x12, 0xb8) /* read/write */
300# define TX33_HDMI (1 << 1)
301
302
303/* Page 13h: Gamut related metadata packets */
304
305
306
307/* CEC registers: (not paged)
308 */
309#define REG_CEC_FRO_IM_CLK_CTRL 0xfb /* read/write */
310# define CEC_FRO_IM_CLK_CTRL_GHOST_DIS (1 << 7)
311# define CEC_FRO_IM_CLK_CTRL_ENA_OTP (1 << 6)
312# define CEC_FRO_IM_CLK_CTRL_IMCLK_SEL (1 << 1)
313# define CEC_FRO_IM_CLK_CTRL_FRO_DIV (1 << 0)
314#define REG_CEC_RXSHPDLEV 0xfe /* read */
315# define CEC_RXSHPDLEV_RXSENS (1 << 0)
316# define CEC_RXSHPDLEV_HPD (1 << 1)
317
318#define REG_CEC_ENAMODS 0xff /* read/write */
319# define CEC_ENAMODS_DIS_FRO (1 << 6)
320# define CEC_ENAMODS_DIS_CCLK (1 << 5)
321# define CEC_ENAMODS_EN_RXSENS (1 << 2)
322# define CEC_ENAMODS_EN_HDMI (1 << 1)
323# define CEC_ENAMODS_EN_CEC (1 << 0)
324
325
326/* Device versions: */
327#define TDA9989N2 0x0101
328#define TDA19989 0x0201
329#define TDA19989N2 0x0202
330#define TDA19988 0x0301
331
332static void
2f7f730a 333cec_write(struct tda998x_priv *priv, uint16_t addr, uint8_t val)
e7792ce2 334{
2f7f730a 335 struct i2c_client *client = priv->cec;
e7792ce2
RC		 336 uint8_t buf[] = {addr, val};
337 int ret;
338
339 ret = i2c_master_send(client, buf, ARRAY_SIZE(buf));
340 if (ret < 0)
341 dev_err(&client->dev, "Error %d writing to cec:0x%x\n", ret, addr);
342}
343
344static uint8_t
2f7f730a 345cec_read(struct tda998x_priv *priv, uint8_t addr)
e7792ce2 346{
2f7f730a 347 struct i2c_client *client = priv->cec;
e7792ce2
RC		 348 uint8_t val;
349 int ret;
350
351 ret = i2c_master_send(client, &addr, sizeof(addr));
352 if (ret < 0)
353 goto fail;
354
355 ret = i2c_master_recv(client, &val, sizeof(val));
356 if (ret < 0)
357 goto fail;
358
359 return val;
360
361fail:
362 dev_err(&client->dev, "Error %d reading from cec:0x%x\n", ret, addr);
363 return 0;
364}
365
7d2eadc9 366static int
2f7f730a 367set_page(struct tda998x_priv *priv, uint16_t reg)
e7792ce2 368{
e7792ce2 369 if (REG2PAGE(reg) != priv->current_page) {
2f7f730a 370 struct i2c_client *client = priv->hdmi;
e7792ce2
RC		 371 uint8_t buf[] = {
372 REG_CURPAGE, REG2PAGE(reg)
373 };
374 int ret = i2c_master_send(client, buf, sizeof(buf));
7d2eadc9 375 if (ret < 0) {
e7792ce2 376 dev_err(&client->dev, "Error %d writing to REG_CURPAGE\n", ret);
7d2eadc9
JFM		 377 return ret;
378 }
e7792ce2
RC		 379
380 priv->current_page = REG2PAGE(reg);
381 }
7d2eadc9 382 return 0;
e7792ce2
RC		 383}
384
385static int
2f7f730a 386reg_read_range(struct tda998x_priv *priv, uint16_t reg, char *buf, int cnt)
e7792ce2 387{
2f7f730a 388 struct i2c_client *client = priv->hdmi;
e7792ce2
RC		 389 uint8_t addr = REG2ADDR(reg);
390 int ret;
391
7d2eadc9
JFM		 392 ret = set_page(priv, reg);
393 if (ret < 0)
394 return ret;
e7792ce2
RC		 395
396 ret = i2c_master_send(client, &addr, sizeof(addr));
397 if (ret < 0)
398 goto fail;
399
400 ret = i2c_master_recv(client, buf, cnt);
401 if (ret < 0)
402 goto fail;
403
404 return ret;
405
406fail:
407 dev_err(&client->dev, "Error %d reading from 0x%x\n", ret, reg);
408 return ret;
409}
410
c4c11dd1 411static void
2f7f730a 412reg_write_range(struct tda998x_priv *priv, uint16_t reg, uint8_t *p, int cnt)
c4c11dd1 413{
2f7f730a 414 struct i2c_client *client = priv->hdmi;
c4c11dd1
RK		 415 uint8_t buf[cnt+1];
416 int ret;
417
418 buf[0] = REG2ADDR(reg);
419 memcpy(&buf[1], p, cnt);
420
7d2eadc9
JFM		 421 ret = set_page(priv, reg);
422 if (ret < 0)
423 return;
c4c11dd1
RK		 424
425 ret = i2c_master_send(client, buf, cnt + 1);
426 if (ret < 0)
427 dev_err(&client->dev, "Error %d writing to 0x%x\n", ret, reg);
428}
429
7d2eadc9 430static int
2f7f730a 431reg_read(struct tda998x_priv *priv, uint16_t reg)
e7792ce2
RC		 432{
433 uint8_t val = 0;
7d2eadc9
JFM		 434 int ret;
435
436 ret = reg_read_range(priv, reg, &val, sizeof(val));
437 if (ret < 0)
438 return ret;
e7792ce2
RC		 439 return val;
440}
441
442static void
2f7f730a 443reg_write(struct tda998x_priv *priv, uint16_t reg, uint8_t val)
e7792ce2 444{
2f7f730a 445 struct i2c_client *client = priv->hdmi;
e7792ce2
RC		 446 uint8_t buf[] = {REG2ADDR(reg), val};
447 int ret;
448
7d2eadc9
JFM		 449 ret = set_page(priv, reg);
450 if (ret < 0)
451 return;
e7792ce2
RC		 452
453 ret = i2c_master_send(client, buf, ARRAY_SIZE(buf));
454 if (ret < 0)
455 dev_err(&client->dev, "Error %d writing to 0x%x\n", ret, reg);
456}
457
458static void
2f7f730a 459reg_write16(struct tda998x_priv *priv, uint16_t reg, uint16_t val)
e7792ce2 460{
2f7f730a 461 struct i2c_client *client = priv->hdmi;
e7792ce2
RC		 462 uint8_t buf[] = {REG2ADDR(reg), val >> 8, val};
463 int ret;
464
7d2eadc9
JFM		 465 ret = set_page(priv, reg);
466 if (ret < 0)
467 return;
e7792ce2
RC		 468
469 ret = i2c_master_send(client, buf, ARRAY_SIZE(buf));
470 if (ret < 0)
471 dev_err(&client->dev, "Error %d writing to 0x%x\n", ret, reg);
472}
473
474static void
2f7f730a 475reg_set(struct tda998x_priv *priv, uint16_t reg, uint8_t val)
e7792ce2 476{
7d2eadc9
JFM		 477 int old_val;
478
479 old_val = reg_read(priv, reg);
480 if (old_val >= 0)
481 reg_write(priv, reg, old_val | val);
e7792ce2
RC		 482}
483
484static void
2f7f730a 485reg_clear(struct tda998x_priv *priv, uint16_t reg, uint8_t val)
e7792ce2 486{
7d2eadc9
JFM		 487 int old_val;
488
489 old_val = reg_read(priv, reg);
490 if (old_val >= 0)
491 reg_write(priv, reg, old_val & ~val);
e7792ce2
RC		 492}
493
494static void
2f7f730a 495tda998x_reset(struct tda998x_priv *priv)
e7792ce2
RC		 496{
497 /* reset audio and i2c master: */
2f7f730a 498 reg_set(priv, REG_SOFTRESET, SOFTRESET_AUDIO | SOFTRESET_I2C_MASTER);
e7792ce2 499 msleep(50);
2f7f730a 500 reg_clear(priv, REG_SOFTRESET, SOFTRESET_AUDIO | SOFTRESET_I2C_MASTER);
e7792ce2
RC		 501 msleep(50);
502
503 /* reset transmitter: */
2f7f730a
JFM		 504 reg_set(priv, REG_MAIN_CNTRL0, MAIN_CNTRL0_SR);
505 reg_clear(priv, REG_MAIN_CNTRL0, MAIN_CNTRL0_SR);
e7792ce2
RC		 506
507 /* PLL registers common configuration */
2f7f730a
JFM		 508 reg_write(priv, REG_PLL_SERIAL_1, 0x00);
509 reg_write(priv, REG_PLL_SERIAL_2, PLL_SERIAL_2_SRL_NOSC(1));
510 reg_write(priv, REG_PLL_SERIAL_3, 0x00);
511 reg_write(priv, REG_SERIALIZER, 0x00);
512 reg_write(priv, REG_BUFFER_OUT, 0x00);
513 reg_write(priv, REG_PLL_SCG1, 0x00);
514 reg_write(priv, REG_AUDIO_DIV, AUDIO_DIV_SERCLK_8);
515 reg_write(priv, REG_SEL_CLK, SEL_CLK_SEL_CLK1 | SEL_CLK_ENA_SC_CLK);
516 reg_write(priv, REG_PLL_SCGN1, 0xfa);
517 reg_write(priv, REG_PLL_SCGN2, 0x00);
518 reg_write(priv, REG_PLL_SCGR1, 0x5b);
519 reg_write(priv, REG_PLL_SCGR2, 0x00);
520 reg_write(priv, REG_PLL_SCG2, 0x10);
bcb2481d
RK		 521
522 /* Write the default value MUX register */
2f7f730a 523 reg_write(priv, REG_MUX_VP_VIP_OUT, 0x24);
e7792ce2
RC		 524}
525
c4c11dd1
RK		 526static uint8_t tda998x_cksum(uint8_t *buf, size_t bytes)
527{
528 uint8_t sum = 0;
529
530 while (bytes--)
531 sum += *buf++;
532 return (255 - sum) + 1;
533}
534
535#define HB(x) (x)
536#define PB(x) (HB(2) + 1 + (x))
537
538static void
2f7f730a 539tda998x_write_if(struct tda998x_priv *priv, uint8_t bit, uint16_t addr,
c4c11dd1
RK		 540 uint8_t *buf, size_t size)
541{
542 buf[PB(0)] = tda998x_cksum(buf, size);
543
2f7f730a
JFM		 544 reg_clear(priv, REG_DIP_IF_FLAGS, bit);
545 reg_write_range(priv, addr, buf, size);
546 reg_set(priv, REG_DIP_IF_FLAGS, bit);
c4c11dd1
RK		 547}
548
549static void
2f7f730a 550tda998x_write_aif(struct tda998x_priv *priv, struct tda998x_encoder_params *p)
c4c11dd1 551{
9e541466 552 u8 buf[PB(HDMI_AUDIO_INFOFRAME_SIZE) + 1];
c4c11dd1 553
7288ca07 554 memset(buf, 0, sizeof(buf));
9e541466 555 buf[HB(0)] = HDMI_INFOFRAME_TYPE_AUDIO;
c4c11dd1 556 buf[HB(1)] = 0x01;
9e541466 557 buf[HB(2)] = HDMI_AUDIO_INFOFRAME_SIZE;
c4c11dd1
RK		 558 buf[PB(1)] = p->audio_frame[1] & 0x07; /* CC */
559 buf[PB(2)] = p->audio_frame[2] & 0x1c; /* SF */
560 buf[PB(4)] = p->audio_frame[4];
561 buf[PB(5)] = p->audio_frame[5] & 0xf8; /* DM_INH + LSV */
562
2f7f730a 563 tda998x_write_if(priv, DIP_IF_FLAGS_IF4, REG_IF4_HB0, buf,
c4c11dd1
RK		 564 sizeof(buf));
565}
566
567static void
2f7f730a 568tda998x_write_avi(struct tda998x_priv *priv, struct drm_display_mode *mode)
c4c11dd1 569{
9e541466 570 u8 buf[PB(HDMI_AVI_INFOFRAME_SIZE) + 1];
c4c11dd1
RK		 571
572 memset(buf, 0, sizeof(buf));
9e541466 573 buf[HB(0)] = HDMI_INFOFRAME_TYPE_AVI;
c4c11dd1 574 buf[HB(1)] = 0x02;
9e541466 575 buf[HB(2)] = HDMI_AVI_INFOFRAME_SIZE;
893c3e53 576 buf[PB(1)] = HDMI_SCAN_MODE_UNDERSCAN;
bdf6345b 577 buf[PB(2)] = HDMI_ACTIVE_ASPECT_PICTURE;
893c3e53 578 buf[PB(3)] = HDMI_QUANTIZATION_RANGE_FULL << 2;
c4c11dd1
RK		 579 buf[PB(4)] = drm_match_cea_mode(mode);
580
2f7f730a 581 tda998x_write_if(priv, DIP_IF_FLAGS_IF2, REG_IF2_HB0, buf,
c4c11dd1
RK		 582 sizeof(buf));
583}
584
2f7f730a 585static void tda998x_audio_mute(struct tda998x_priv *priv, bool on)
c4c11dd1
RK		 586{
587 if (on) {
2f7f730a
JFM		 588 reg_set(priv, REG_SOFTRESET, SOFTRESET_AUDIO);
589 reg_clear(priv, REG_SOFTRESET, SOFTRESET_AUDIO);
590 reg_set(priv, REG_AIP_CNTRL_0, AIP_CNTRL_0_RST_FIFO);
c4c11dd1 591 } else {
2f7f730a 592 reg_clear(priv, REG_AIP_CNTRL_0, AIP_CNTRL_0_RST_FIFO);
c4c11dd1
RK		 593 }
594}
595
596static void
2f7f730a 597tda998x_configure_audio(struct tda998x_priv *priv,
c4c11dd1
RK		 598 struct drm_display_mode *mode, struct tda998x_encoder_params *p)
599{
600 uint8_t buf[6], clksel_aip, clksel_fs, ca_i2s, cts_n, adiv;
601 uint32_t n;
602
603 /* Enable audio ports */
2f7f730a
JFM		 604 reg_write(priv, REG_ENA_AP, p->audio_cfg);
605 reg_write(priv, REG_ENA_ACLK, p->audio_clk_cfg);
c4c11dd1
RK		 606
607 /* Set audio input source */
608 switch (p->audio_format) {
609 case AFMT_SPDIF:
2f7f730a 610 reg_write(priv, REG_MUX_AP, 0x40);
c4c11dd1
RK		 611 clksel_aip = AIP_CLKSEL_AIP(0);
612 /* FS64SPDIF */
613 clksel_fs = AIP_CLKSEL_FS(2);
614 cts_n = CTS_N_M(3) | CTS_N_K(3);
615 ca_i2s = 0;
616 break;
617
618 case AFMT_I2S:
2f7f730a 619 reg_write(priv, REG_MUX_AP, 0x64);
c4c11dd1
RK		 620 clksel_aip = AIP_CLKSEL_AIP(1);
621 /* ACLK */
622 clksel_fs = AIP_CLKSEL_FS(0);
623 cts_n = CTS_N_M(3) | CTS_N_K(3);
624 ca_i2s = CA_I2S_CA_I2S(0);
625 break;
3b28802e
DH		 626
627 default:
628 BUG();
629 return;
c4c11dd1
RK		 630 }
631
2f7f730a
JFM		 632 reg_write(priv, REG_AIP_CLKSEL, clksel_aip);
633 reg_clear(priv, REG_AIP_CNTRL_0, AIP_CNTRL_0_LAYOUT);
c4c11dd1
RK		 634
635 /* Enable automatic CTS generation */
2f7f730a
JFM		 636 reg_clear(priv, REG_AIP_CNTRL_0, AIP_CNTRL_0_ACR_MAN);
637 reg_write(priv, REG_CTS_N, cts_n);
c4c11dd1
RK		 638
639 /*
640 * Audio input somehow depends on HDMI line rate which is
641 * related to pixclk. Testing showed that modes with pixclk
642 * >100MHz need a larger divider while <40MHz need the default.
643 * There is no detailed info in the datasheet, so we just
644 * assume 100MHz requires larger divider.
645 */
646 if (mode->clock > 100000)
647 adiv = AUDIO_DIV_SERCLK_16;
648 else
649 adiv = AUDIO_DIV_SERCLK_8;
2f7f730a 650 reg_write(priv, REG_AUDIO_DIV, adiv);
c4c11dd1
RK		 651
652 /*
653 * This is the approximate value of N, which happens to be
654 * the recommended values for non-coherent clocks.
655 */
656 n = 128 * p->audio_sample_rate / 1000;
657
658 /* Write the CTS and N values */
659 buf[0] = 0x44;
660 buf[1] = 0x42;
661 buf[2] = 0x01;
662 buf[3] = n;
663 buf[4] = n >> 8;
664 buf[5] = n >> 16;
2f7f730a 665 reg_write_range(priv, REG_ACR_CTS_0, buf, 6);
c4c11dd1
RK		 666
667 /* Set CTS clock reference */
2f7f730a 668 reg_write(priv, REG_AIP_CLKSEL, clksel_aip | clksel_fs);
c4c11dd1
RK		 669
670 /* Reset CTS generator */
2f7f730a
JFM		 671 reg_set(priv, REG_AIP_CNTRL_0, AIP_CNTRL_0_RST_CTS);
672 reg_clear(priv, REG_AIP_CNTRL_0, AIP_CNTRL_0_RST_CTS);
c4c11dd1
RK		 673
674 /* Write the channel status */
f0b33b28 675 buf[0] = IEC958_AES0_CON_NOT_COPYRIGHT;
c4c11dd1 676 buf[1] = 0x00;
f0b33b28
JFM		 677 buf[2] = IEC958_AES3_CON_FS_NOTID;
678 buf[3] = IEC958_AES4_CON_ORIGFS_NOTID |
679 IEC958_AES4_CON_MAX_WORDLEN_24;
2f7f730a 680 reg_write_range(priv, REG_CH_STAT_B(0), buf, 4);
c4c11dd1 681
2f7f730a 682 tda998x_audio_mute(priv, true);
c4c11dd1 683 mdelay(20);
2f7f730a 684 tda998x_audio_mute(priv, false);
c4c11dd1
RK		 685
686 /* Write the audio information packet */
2f7f730a 687 tda998x_write_aif(priv, p);
c4c11dd1
RK		 688}
689
e7792ce2
RC		 690/* DRM encoder functions */
691
692static void
693tda998x_encoder_set_config(struct drm_encoder *encoder, void *params)
694{
c4c11dd1
RK		 695 struct tda998x_priv *priv = to_tda998x_priv(encoder);
696 struct tda998x_encoder_params *p = params;
697
698 priv->vip_cntrl_0 = VIP_CNTRL_0_SWAP_A(p->swap_a) |
699 (p->mirr_a ? VIP_CNTRL_0_MIRR_A : 0) |
700 VIP_CNTRL_0_SWAP_B(p->swap_b) |
701 (p->mirr_b ? VIP_CNTRL_0_MIRR_B : 0);
702 priv->vip_cntrl_1 = VIP_CNTRL_1_SWAP_C(p->swap_c) |
703 (p->mirr_c ? VIP_CNTRL_1_MIRR_C : 0) |
704 VIP_CNTRL_1_SWAP_D(p->swap_d) |
705 (p->mirr_d ? VIP_CNTRL_1_MIRR_D : 0);
706 priv->vip_cntrl_2 = VIP_CNTRL_2_SWAP_E(p->swap_e) |
707 (p->mirr_e ? VIP_CNTRL_2_MIRR_E : 0) |
708 VIP_CNTRL_2_SWAP_F(p->swap_f) |
709 (p->mirr_f ? VIP_CNTRL_2_MIRR_F : 0);
710
711 priv->params = *p;
e7792ce2
RC		 712}
713
714static void
715tda998x_encoder_dpms(struct drm_encoder *encoder, int mode)
716{
717 struct tda998x_priv *priv = to_tda998x_priv(encoder);
718
719 /* we only care about on or off: */
720 if (mode != DRM_MODE_DPMS_ON)
721 mode = DRM_MODE_DPMS_OFF;
722
723 if (mode == priv->dpms)
724 return;
725
726 switch (mode) {
727 case DRM_MODE_DPMS_ON:
c4c11dd1 728 /* enable video ports, audio will be enabled later */
2f7f730a
JFM		 729 reg_write(priv, REG_ENA_VP_0, 0xff);
730 reg_write(priv, REG_ENA_VP_1, 0xff);
731 reg_write(priv, REG_ENA_VP_2, 0xff);
e7792ce2 732 /* set muxing after enabling ports: */
2f7f730a
JFM		 733 reg_write(priv, REG_VIP_CNTRL_0, priv->vip_cntrl_0);
734 reg_write(priv, REG_VIP_CNTRL_1, priv->vip_cntrl_1);
735 reg_write(priv, REG_VIP_CNTRL_2, priv->vip_cntrl_2);
e7792ce2
RC		 736 break;
737 case DRM_MODE_DPMS_OFF:
db6aaf4d 738 /* disable video ports */
2f7f730a
JFM		 739 reg_write(priv, REG_ENA_VP_0, 0x00);
740 reg_write(priv, REG_ENA_VP_1, 0x00);
741 reg_write(priv, REG_ENA_VP_2, 0x00);
e7792ce2
RC		 742 break;
743 }
744
745 priv->dpms = mode;
746}
747
748static void
749tda998x_encoder_save(struct drm_encoder *encoder)
750{
751 DBG("");
752}
753
754static void
755tda998x_encoder_restore(struct drm_encoder *encoder)
756{
757 DBG("");
758}
759
760static bool
761tda998x_encoder_mode_fixup(struct drm_encoder *encoder,
762 const struct drm_display_mode *mode,
763 struct drm_display_mode *adjusted_mode)
764{
765 return true;
766}
767
768static int
769tda998x_encoder_mode_valid(struct drm_encoder *encoder,
770 struct drm_display_mode *mode)
771{
772 return MODE_OK;
773}
774
775static void
776tda998x_encoder_mode_set(struct drm_encoder *encoder,
777 struct drm_display_mode *mode,
778 struct drm_display_mode *adjusted_mode)
779{
780 struct tda998x_priv *priv = to_tda998x_priv(encoder);
088d61d1
SH		 781 uint16_t ref_pix, ref_line, n_pix, n_line;
782 uint16_t hs_pix_s, hs_pix_e;
783 uint16_t vs1_pix_s, vs1_pix_e, vs1_line_s, vs1_line_e;
784 uint16_t vs2_pix_s, vs2_pix_e, vs2_line_s, vs2_line_e;
785 uint16_t vwin1_line_s, vwin1_line_e;
786 uint16_t vwin2_line_s, vwin2_line_e;
787 uint16_t de_pix_s, de_pix_e;
e7792ce2
RC		 788 uint8_t reg, div, rep;
789
088d61d1
SH		 790 /*
791 * Internally TDA998x is using ITU-R BT.656 style sync but
792 * we get VESA style sync. TDA998x is using a reference pixel
793 * relative to ITU to sync to the input frame and for output
794 * sync generation. Currently, we are using reference detection
795 * from HS/VS, i.e. REFPIX/REFLINE denote frame start sync point
796 * which is position of rising VS with coincident rising HS.
797 *
798 * Now there is some issues to take care of:
799 * - HDMI data islands require sync-before-active
800 * - TDA998x register values must be > 0 to be enabled
801 * - REFLINE needs an additional offset of +1
802 * - REFPIX needs an addtional offset of +1 for UYUV and +3 for RGB
803 *
804 * So we add +1 to all horizontal and vertical register values,
805 * plus an additional +3 for REFPIX as we are using RGB input only.
e7792ce2 806 */
088d61d1
SH		 807 n_pix = mode->htotal;
808 n_line = mode->vtotal;
809
810 hs_pix_e = mode->hsync_end - mode->hdisplay;
811 hs_pix_s = mode->hsync_start - mode->hdisplay;
812 de_pix_e = mode->htotal;
813 de_pix_s = mode->htotal - mode->hdisplay;
814 ref_pix = 3 + hs_pix_s;
815
179f1aa4
SH		 816 /*
817 * Attached LCD controllers may generate broken sync. Allow
818 * those to adjust the position of the rising VS edge by adding
819 * HSKEW to ref_pix.
820 */
821 if (adjusted_mode->flags & DRM_MODE_FLAG_HSKEW)
822 ref_pix += adjusted_mode->hskew;
823
088d61d1
SH		 824 if ((mode->flags & DRM_MODE_FLAG_INTERLACE) == 0) {
825 ref_line = 1 + mode->vsync_start - mode->vdisplay;
826 vwin1_line_s = mode->vtotal - mode->vdisplay - 1;
827 vwin1_line_e = vwin1_line_s + mode->vdisplay;
828 vs1_pix_s = vs1_pix_e = hs_pix_s;
829 vs1_line_s = mode->vsync_start - mode->vdisplay;
830 vs1_line_e = vs1_line_s +
831 mode->vsync_end - mode->vsync_start;
832 vwin2_line_s = vwin2_line_e = 0;
833 vs2_pix_s = vs2_pix_e = 0;
834 vs2_line_s = vs2_line_e = 0;
835 } else {
836 ref_line = 1 + (mode->vsync_start - mode->vdisplay)/2;
837 vwin1_line_s = (mode->vtotal - mode->vdisplay)/2;
838 vwin1_line_e = vwin1_line_s + mode->vdisplay/2;
839 vs1_pix_s = vs1_pix_e = hs_pix_s;
840 vs1_line_s = (mode->vsync_start - mode->vdisplay)/2;
841 vs1_line_e = vs1_line_s +
842 (mode->vsync_end - mode->vsync_start)/2;
843 vwin2_line_s = vwin1_line_s + mode->vtotal/2;
844 vwin2_line_e = vwin2_line_s + mode->vdisplay/2;
845 vs2_pix_s = vs2_pix_e = hs_pix_s + mode->htotal/2;
846 vs2_line_s = vs1_line_s + mode->vtotal/2 ;
847 vs2_line_e = vs2_line_s +
848 (mode->vsync_end - mode->vsync_start)/2;
849 }
e7792ce2
RC		 850
851 div = 148500 / mode->clock;
3ae471f7
JFM		 852 if (div != 0) {
853 div--;
854 if (div > 3)
855 div = 3;
856 }
e7792ce2 857
e7792ce2 858 /* mute the audio FIFO: */
2f7f730a 859 reg_set(priv, REG_AIP_CNTRL_0, AIP_CNTRL_0_RST_FIFO);
e7792ce2
RC		 860
861 /* set HDMI HDCP mode off: */
2f7f730a
JFM		 862 reg_set(priv, REG_TBG_CNTRL_1, TBG_CNTRL_1_DWIN_DIS);
863 reg_clear(priv, REG_TX33, TX33_HDMI);
864 reg_write(priv, REG_ENC_CNTRL, ENC_CNTRL_CTL_CODE(0));
e7792ce2 865
e7792ce2 866 /* no pre-filter or interpolator: */
2f7f730a 867 reg_write(priv, REG_HVF_CNTRL_0, HVF_CNTRL_0_PREFIL(0) |
e7792ce2 868 HVF_CNTRL_0_INTPOL(0));
2f7f730a
JFM		 869 reg_write(priv, REG_VIP_CNTRL_5, VIP_CNTRL_5_SP_CNT(0));
870 reg_write(priv, REG_VIP_CNTRL_4, VIP_CNTRL_4_BLANKIT(0) |
e7792ce2 871 VIP_CNTRL_4_BLC(0));
2f7f730a 872 reg_clear(priv, REG_PLL_SERIAL_3, PLL_SERIAL_3_SRL_CCIR);
e7792ce2 873
2f7f730a
JFM		 874 reg_clear(priv, REG_PLL_SERIAL_1, PLL_SERIAL_1_SRL_MAN_IZ);
875 reg_clear(priv, REG_PLL_SERIAL_3, PLL_SERIAL_3_SRL_DE);
876 reg_write(priv, REG_SERIALIZER, 0);
877 reg_write(priv, REG_HVF_CNTRL_1, HVF_CNTRL_1_VQR(0));
e7792ce2
RC		 878
879 /* TODO enable pixel repeat for pixel rates less than 25Msamp/s */
880 rep = 0;
2f7f730a
JFM		 881 reg_write(priv, REG_RPT_CNTRL, 0);
882 reg_write(priv, REG_SEL_CLK, SEL_CLK_SEL_VRF_CLK(0) |
e7792ce2
RC		 883 SEL_CLK_SEL_CLK1 | SEL_CLK_ENA_SC_CLK);
884
2f7f730a 885 reg_write(priv, REG_PLL_SERIAL_2, PLL_SERIAL_2_SRL_NOSC(div) |
e7792ce2
RC		 886 PLL_SERIAL_2_SRL_PR(rep));
887
e7792ce2 888 /* set color matrix bypass flag: */
2f7f730a 889 reg_set(priv, REG_MAT_CONTRL, MAT_CONTRL_MAT_BP);
e7792ce2
RC		 890
891 /* set BIAS tmds value: */
2f7f730a 892 reg_write(priv, REG_ANA_GENERAL, 0x09);
e7792ce2 893
2f7f730a 894 reg_clear(priv, REG_TBG_CNTRL_0, TBG_CNTRL_0_SYNC_MTHD);
e7792ce2 895
088d61d1
SH		 896 /*
897 * Sync on rising HSYNC/VSYNC
898 */
2f7f730a
JFM		 899 reg_write(priv, REG_VIP_CNTRL_3, 0);
900 reg_set(priv, REG_VIP_CNTRL_3, VIP_CNTRL_3_SYNC_HS);
088d61d1
SH		 901
902 /*
903 * TDA19988 requires high-active sync at input stage,
904 * so invert low-active sync provided by master encoder here
905 */
906 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
2f7f730a 907 reg_set(priv, REG_VIP_CNTRL_3, VIP_CNTRL_3_H_TGL);
e7792ce2 908 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
2f7f730a 909 reg_set(priv, REG_VIP_CNTRL_3, VIP_CNTRL_3_V_TGL);
e7792ce2 910
088d61d1
SH		 911 /*
912 * Always generate sync polarity relative to input sync and
913 * revert input stage toggled sync at output stage
914 */
915 reg = TBG_CNTRL_1_TGL_EN;
e7792ce2 916 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
088d61d1
SH		 917 reg |= TBG_CNTRL_1_H_TGL;
918 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
919 reg |= TBG_CNTRL_1_V_TGL;
2f7f730a
JFM		 920 reg_write(priv, REG_TBG_CNTRL_1, reg);
921
922 reg_write(priv, REG_VIDFORMAT, 0x00);
923 reg_write16(priv, REG_REFPIX_MSB, ref_pix);
924 reg_write16(priv, REG_REFLINE_MSB, ref_line);
925 reg_write16(priv, REG_NPIX_MSB, n_pix);
926 reg_write16(priv, REG_NLINE_MSB, n_line);
927 reg_write16(priv, REG_VS_LINE_STRT_1_MSB, vs1_line_s);
928 reg_write16(priv, REG_VS_PIX_STRT_1_MSB, vs1_pix_s);
929 reg_write16(priv, REG_VS_LINE_END_1_MSB, vs1_line_e);
930 reg_write16(priv, REG_VS_PIX_END_1_MSB, vs1_pix_e);
931 reg_write16(priv, REG_VS_LINE_STRT_2_MSB, vs2_line_s);
932 reg_write16(priv, REG_VS_PIX_STRT_2_MSB, vs2_pix_s);
933 reg_write16(priv, REG_VS_LINE_END_2_MSB, vs2_line_e);
934 reg_write16(priv, REG_VS_PIX_END_2_MSB, vs2_pix_e);
935 reg_write16(priv, REG_HS_PIX_START_MSB, hs_pix_s);
936 reg_write16(priv, REG_HS_PIX_STOP_MSB, hs_pix_e);
937 reg_write16(priv, REG_VWIN_START_1_MSB, vwin1_line_s);
938 reg_write16(priv, REG_VWIN_END_1_MSB, vwin1_line_e);
939 reg_write16(priv, REG_VWIN_START_2_MSB, vwin2_line_s);
940 reg_write16(priv, REG_VWIN_END_2_MSB, vwin2_line_e);
941 reg_write16(priv, REG_DE_START_MSB, de_pix_s);
942 reg_write16(priv, REG_DE_STOP_MSB, de_pix_e);
e7792ce2
RC		 943
944 if (priv->rev == TDA19988) {
945 /* let incoming pixels fill the active space (if any) */
2f7f730a 946 reg_write(priv, REG_ENABLE_SPACE, 0x00);
e7792ce2
RC		 947 }
948
e7792ce2 949 /* must be last register set: */
2f7f730a 950 reg_clear(priv, REG_TBG_CNTRL_0, TBG_CNTRL_0_SYNC_ONCE);
c4c11dd1
RK		 951
952 /* Only setup the info frames if the sink is HDMI */
953 if (priv->is_hdmi_sink) {
954 /* We need to turn HDMI HDCP stuff on to get audio through */
2f7f730a
JFM		 955 reg_clear(priv, REG_TBG_CNTRL_1, TBG_CNTRL_1_DWIN_DIS);
956 reg_write(priv, REG_ENC_CNTRL, ENC_CNTRL_CTL_CODE(1));
957 reg_set(priv, REG_TX33, TX33_HDMI);
c4c11dd1 958
2f7f730a 959 tda998x_write_avi(priv, adjusted_mode);
c4c11dd1
RK		 960
961 if (priv->params.audio_cfg)
2f7f730a 962 tda998x_configure_audio(priv, adjusted_mode,
c4c11dd1
RK		 963 &priv->params);
964 }
e7792ce2
RC		 965}
966
967static enum drm_connector_status
968tda998x_encoder_detect(struct drm_encoder *encoder,
969 struct drm_connector *connector)
970{
2f7f730a
JFM		 971 struct tda998x_priv *priv = to_tda998x_priv(encoder);
972 uint8_t val = cec_read(priv, REG_CEC_RXSHPDLEV);
973
e7792ce2
RC		 974 return (val & CEC_RXSHPDLEV_HPD) ? connector_status_connected :
975 connector_status_disconnected;
976}
977
978static int
979read_edid_block(struct drm_encoder *encoder, uint8_t *buf, int blk)
980{
2f7f730a 981 struct tda998x_priv *priv = to_tda998x_priv(encoder);
e7792ce2
RC		 982 uint8_t offset, segptr;
983 int ret, i;
984
985 /* enable EDID read irq: */
2f7f730a 986 reg_set(priv, REG_INT_FLAGS_2, INT_FLAGS_2_EDID_BLK_RD);
e7792ce2
RC		 987
988 offset = (blk & 1) ? 128 : 0;
989 segptr = blk / 2;
990
2f7f730a
JFM		 991 reg_write(priv, REG_DDC_ADDR, 0xa0);
992 reg_write(priv, REG_DDC_OFFS, offset);
993 reg_write(priv, REG_DDC_SEGM_ADDR, 0x60);
994 reg_write(priv, REG_DDC_SEGM, segptr);
e7792ce2
RC		 995
996 /* enable reading EDID: */
2f7f730a 997 reg_write(priv, REG_EDID_CTRL, 0x1);
e7792ce2
RC		 998
999 /* flag must be cleared by sw: */
2f7f730a 1000 reg_write(priv, REG_EDID_CTRL, 0x0);
e7792ce2
RC		 1001
1002 /* wait for block read to complete: */
1003 for (i = 100; i > 0; i--) {
7d2eadc9
JFM		 1004 ret = reg_read(priv, REG_INT_FLAGS_2);
1005 if (ret < 0)
1006 return ret;
1007 if (ret & INT_FLAGS_2_EDID_BLK_RD)
e7792ce2
RC		 1008 break;
1009 msleep(1);
1010 }
1011
1012 if (i == 0)
1013 return -ETIMEDOUT;
1014
2f7f730a 1015 ret = reg_read_range(priv, REG_EDID_DATA_0, buf, EDID_LENGTH);
e7792ce2
RC		 1016 if (ret != EDID_LENGTH) {
1017 dev_err(encoder->dev->dev, "failed to read edid block %d: %d",
1018 blk, ret);
1019 return ret;
1020 }
1021
2f7f730a 1022 reg_clear(priv, REG_INT_FLAGS_2, INT_FLAGS_2_EDID_BLK_RD);
e7792ce2
RC		 1023
1024 return 0;
1025}
1026
1027static uint8_t *
1028do_get_edid(struct drm_encoder *encoder)
1029{
063b472f 1030 struct tda998x_priv *priv = to_tda998x_priv(encoder);
e7792ce2
RC		 1031 int j = 0, valid_extensions = 0;
1032 uint8_t *block, *new;
1033 bool print_bad_edid = drm_debug & DRM_UT_KMS;
1034
1035 if ((block = kmalloc(EDID_LENGTH, GFP_KERNEL)) == NULL)
1036 return NULL;
1037
063b472f 1038 if (priv->rev == TDA19988)
2f7f730a 1039 reg_clear(priv, REG_TX4, TX4_PD_RAM);
063b472f 1040
e7792ce2
RC		 1041 /* base block fetch */
1042 if (read_edid_block(encoder, block, 0))
1043 goto fail;
1044
1045 if (!drm_edid_block_valid(block, 0, print_bad_edid))
1046 goto fail;
1047
1048 /* if there's no extensions, we're done */
1049 if (block[0x7e] == 0)
063b472f 1050 goto done;
e7792ce2
RC		 1051
1052 new = krealloc(block, (block[0x7e] + 1) * EDID_LENGTH, GFP_KERNEL);
1053 if (!new)
1054 goto fail;
1055 block = new;
1056
1057 for (j = 1; j <= block[0x7e]; j++) {
1058 uint8_t *ext_block = block + (valid_extensions + 1) * EDID_LENGTH;
1059 if (read_edid_block(encoder, ext_block, j))
1060 goto fail;
1061
1062 if (!drm_edid_block_valid(ext_block, j, print_bad_edid))
1063 goto fail;
1064
1065 valid_extensions++;
1066 }
1067
1068 if (valid_extensions != block[0x7e]) {
1069 block[EDID_LENGTH-1] += block[0x7e] - valid_extensions;
1070 block[0x7e] = valid_extensions;
1071 new = krealloc(block, (valid_extensions + 1) * EDID_LENGTH, GFP_KERNEL);
1072 if (!new)
1073 goto fail;
1074 block = new;
1075 }
1076
063b472f
RK		 1077done:
1078 if (priv->rev == TDA19988)
2f7f730a 1079 reg_set(priv, REG_TX4, TX4_PD_RAM);
063b472f 1080
e7792ce2
RC		 1081 return block;
1082
1083fail:
063b472f 1084 if (priv->rev == TDA19988)
2f7f730a 1085 reg_set(priv, REG_TX4, TX4_PD_RAM);
e7792ce2
RC		 1086 dev_warn(encoder->dev->dev, "failed to read EDID\n");
1087 kfree(block);
1088 return NULL;
1089}
1090
1091static int
1092tda998x_encoder_get_modes(struct drm_encoder *encoder,
1093 struct drm_connector *connector)
1094{
c4c11dd1 1095 struct tda998x_priv *priv = to_tda998x_priv(encoder);
e7792ce2
RC		 1096 struct edid *edid = (struct edid *)do_get_edid(encoder);
1097 int n = 0;
1098
1099 if (edid) {
1100 drm_mode_connector_update_edid_property(connector, edid);
1101 n = drm_add_edid_modes(connector, edid);
c4c11dd1 1102 priv->is_hdmi_sink = drm_detect_hdmi_monitor(edid);
e7792ce2
RC		 1103 kfree(edid);
1104 }
1105
1106 return n;
1107}
1108
1109static int
1110tda998x_encoder_create_resources(struct drm_encoder *encoder,
1111 struct drm_connector *connector)
1112{
1113 DBG("");
1114 return 0;
1115}
1116
1117static int
1118tda998x_encoder_set_property(struct drm_encoder *encoder,
1119 struct drm_connector *connector,
1120 struct drm_property *property,
1121 uint64_t val)
1122{
1123 DBG("");
1124 return 0;
1125}
1126
1127static void
1128tda998x_encoder_destroy(struct drm_encoder *encoder)
1129{
1130 struct tda998x_priv *priv = to_tda998x_priv(encoder);
1131 drm_i2c_encoder_destroy(encoder);
fc275a74
JFM		 1132 if (priv->cec)
1133 i2c_unregister_device(priv->cec);
e7792ce2
RC		 1134 kfree(priv);
1135}
1136
1137static struct drm_encoder_slave_funcs tda998x_encoder_funcs = {
1138 .set_config = tda998x_encoder_set_config,
1139 .destroy = tda998x_encoder_destroy,
1140 .dpms = tda998x_encoder_dpms,
1141 .save = tda998x_encoder_save,
1142 .restore = tda998x_encoder_restore,
1143 .mode_fixup = tda998x_encoder_mode_fixup,
1144 .mode_valid = tda998x_encoder_mode_valid,
1145 .mode_set = tda998x_encoder_mode_set,
1146 .detect = tda998x_encoder_detect,
1147 .get_modes = tda998x_encoder_get_modes,
1148 .create_resources = tda998x_encoder_create_resources,
1149 .set_property = tda998x_encoder_set_property,
1150};
1151
1152/* I2C driver functions */
1153
1154static int
1155tda998x_probe(struct i2c_client *client, const struct i2c_device_id *id)
1156{
1157 return 0;
1158}
1159
1160static int
1161tda998x_remove(struct i2c_client *client)
1162{
1163 return 0;
1164}
1165
1166static int
1167tda998x_encoder_init(struct i2c_client *client,
1168 struct drm_device *dev,
1169 struct drm_encoder_slave *encoder_slave)
1170{
e7792ce2 1171 struct tda998x_priv *priv;
fb7544d7 1172 int rev_lo, rev_hi, ret;
e7792ce2
RC		 1173
1174 priv = kzalloc(sizeof(*priv), GFP_KERNEL);
1175 if (!priv)
1176 return -ENOMEM;
1177
5e74c22c
RK		 1178 priv->vip_cntrl_0 = VIP_CNTRL_0_SWAP_A(2) | VIP_CNTRL_0_SWAP_B(3);
1179 priv->vip_cntrl_1 = VIP_CNTRL_1_SWAP_C(0) | VIP_CNTRL_1_SWAP_D(1);
1180 priv->vip_cntrl_2 = VIP_CNTRL_2_SWAP_E(4) | VIP_CNTRL_2_SWAP_F(5);
1181
2eb4c7b1 1182 priv->current_page = 0xff;
2f7f730a 1183 priv->hdmi = client;
e7792ce2 1184 priv->cec = i2c_new_dummy(client->adapter, 0x34);
71c68c4f
DJ		 1185 if (!priv->cec) {
1186 kfree(priv);
6ae668cc 1187 return -ENODEV;
71c68c4f 1188 }
e7792ce2
RC		 1189 priv->dpms = DRM_MODE_DPMS_OFF;
1190
1191 encoder_slave->slave_priv = priv;
1192 encoder_slave->slave_funcs = &tda998x_encoder_funcs;
1193
1194 /* wake up the device: */
2f7f730a 1195 cec_write(priv, REG_CEC_ENAMODS,
e7792ce2
RC		 1196 CEC_ENAMODS_EN_RXSENS | CEC_ENAMODS_EN_HDMI);
1197
2f7f730a 1198 tda998x_reset(priv);
e7792ce2
RC		 1199
1200 /* read version: */
fb7544d7
RK		 1201 rev_lo = reg_read(priv, REG_VERSION_LSB);
1202 rev_hi = reg_read(priv, REG_VERSION_MSB);
1203 if (rev_lo < 0 || rev_hi < 0) {
1204 ret = rev_lo < 0 ? rev_lo : rev_hi;
7d2eadc9 1205 goto fail;
fb7544d7
RK		 1206 }
1207
1208 priv->rev = rev_lo | rev_hi << 8;
e7792ce2
RC		 1209
1210 /* mask off feature bits: */
1211 priv->rev &= ~0x30; /* not-hdcp and not-scalar bit */
1212
1213 switch (priv->rev) {
1214 case TDA9989N2: dev_info(dev->dev, "found TDA9989 n2"); break;
1215 case TDA19989: dev_info(dev->dev, "found TDA19989"); break;
1216 case TDA19989N2: dev_info(dev->dev, "found TDA19989 n2"); break;
1217 case TDA19988: dev_info(dev->dev, "found TDA19988"); break;
1218 default:
1219 DBG("found unsupported device: %04x", priv->rev);
1220 goto fail;
1221 }
1222
1223 /* after reset, enable DDC: */
2f7f730a 1224 reg_write(priv, REG_DDC_DISABLE, 0x00);
e7792ce2
RC		 1225
1226 /* set clock on DDC channel: */
2f7f730a 1227 reg_write(priv, REG_TX3, 39);
e7792ce2
RC		 1228
1229 /* if necessary, disable multi-master: */
1230 if (priv->rev == TDA19989)
2f7f730a 1231 reg_set(priv, REG_I2C_MASTER, I2C_MASTER_DIS_MM);
e7792ce2 1232
2f7f730a 1233 cec_write(priv, REG_CEC_FRO_IM_CLK_CTRL,
e7792ce2
RC		 1234 CEC_FRO_IM_CLK_CTRL_GHOST_DIS | CEC_FRO_IM_CLK_CTRL_IMCLK_SEL);
1235
1236 return 0;
1237
1238fail:
1239 /* if encoder_init fails, the encoder slave is never registered,
1240 * so cleanup here:
1241 */
1242 if (priv->cec)
1243 i2c_unregister_device(priv->cec);
1244 kfree(priv);
1245 encoder_slave->slave_priv = NULL;
1246 encoder_slave->slave_funcs = NULL;
1247 return -ENXIO;
1248}
1249
1250static struct i2c_device_id tda998x_ids[] = {
1251 { "tda998x", 0 },
1252 { }
1253};
1254MODULE_DEVICE_TABLE(i2c, tda998x_ids);
1255
1256static struct drm_i2c_encoder_driver tda998x_driver = {
1257 .i2c_driver = {
1258 .probe = tda998x_probe,
1259 .remove = tda998x_remove,
1260 .driver = {
1261 .name = "tda998x",
1262 },
1263 .id_table = tda998x_ids,
1264 },
1265 .encoder_init = tda998x_encoder_init,
1266};
1267
1268/* Module initialization */
1269
1270static int __init
1271tda998x_init(void)
1272{
1273 DBG("");
1274 return drm_i2c_encoder_register(THIS_MODULE, &tda998x_driver);
1275}
1276
1277static void __exit
1278tda998x_exit(void)
1279{
1280 DBG("");
1281 drm_i2c_encoder_unregister(&tda998x_driver);
1282}
1283
1284MODULE_AUTHOR("Rob Clark <robdclark@gmail.com");
1285MODULE_DESCRIPTION("NXP Semiconductors TDA998X HDMI Encoder");
1286MODULE_LICENSE("GPL");
1287
1288module_init(tda998x_init);
1289module_exit(tda998x_exit);
Linux kernel - Deliverables
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