[deliverable/linux.git] / drivers / gpu / drm / i915 / dvo_ivch.c

/*
 * Copyright © 2006 Intel Corporation
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice (including the next
 * paragraph) shall be included in all copies or substantial portions of the
 * Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
 * DEALINGS IN THE SOFTWARE.
 *
 * Authors:
 *    Eric Anholt <eric@anholt.net>
 *
 */

#include "dvo.h"

/*
 * register definitions for the i82807aa.
 *
 * Documentation on this chipset can be found in datasheet #29069001 at
 * intel.com.
 */

/*
 * VCH Revision & GMBus Base Addr
 */
#define VR00		0x00
# define VR00_BASE_ADDRESS_MASK		0x007f

/*
 * Functionality Enable
 */
#define VR01		0x01

/*
 * Enable the panel fitter
 */
# define VR01_PANEL_FIT_ENABLE		(1 << 3)
/*
 * Enables the LCD display.
 *
 * This must not be set while VR01_DVO_BYPASS_ENABLE is set.
 */
# define VR01_LCD_ENABLE		(1 << 2)
/** Enables the DVO repeater. */
# define VR01_DVO_BYPASS_ENABLE		(1 << 1)
/** Enables the DVO clock */
# define VR01_DVO_ENABLE		(1 << 0)

/*
 * LCD Interface Format
 */
#define VR10		0x10
/** Enables LVDS output instead of CMOS */
# define VR10_LVDS_ENABLE		(1 << 4)
/** Enables 18-bit LVDS output. */
# define VR10_INTERFACE_1X18		(0 << 2)
/** Enables 24-bit LVDS or CMOS output */
# define VR10_INTERFACE_1X24		(1 << 2)
/** Enables 2x18-bit LVDS or CMOS output. */
# define VR10_INTERFACE_2X18		(2 << 2)
/** Enables 2x24-bit LVDS output */
# define VR10_INTERFACE_2X24		(3 << 2)

/*
 * VR20 LCD Horizontal Display Size
 */
#define VR20	0x20

/*
 * LCD Vertical Display Size
 */
#define VR21	0x20

/*
 * Panel power down status
 */
#define VR30		0x30
/** Read only bit indicating that the panel is not in a safe poweroff state. */
# define VR30_PANEL_ON			(1 << 15)

#define VR40		0x40
# define VR40_STALL_ENABLE		(1 << 13)
# define VR40_VERTICAL_INTERP_ENABLE	(1 << 12)
# define VR40_ENHANCED_PANEL_FITTING	(1 << 11)
# define VR40_HORIZONTAL_INTERP_ENABLE	(1 << 10)
# define VR40_AUTO_RATIO_ENABLE		(1 << 9)
# define VR40_CLOCK_GATING_ENABLE	(1 << 8)

/*
 * Panel Fitting Vertical Ratio
 * (((image_height - 1) << 16) / ((panel_height - 1))) >> 2
 */
#define VR41		0x41

/*
 * Panel Fitting Horizontal Ratio
 * (((image_width - 1) << 16) / ((panel_width - 1))) >> 2
 */
#define VR42		0x42

/*
 * Horizontal Image Size
 */
#define VR43		0x43

/* VR80 GPIO 0
 */
#define VR80	    0x80
#define VR81	    0x81
#define VR82	    0x82
#define VR83	    0x83
#define VR84	    0x84
#define VR85	    0x85
#define VR86	    0x86
#define VR87	    0x87

/* VR88 GPIO 8
 */
#define VR88	    0x88

/* Graphics BIOS scratch 0
 */
#define VR8E	    0x8E
# define VR8E_PANEL_TYPE_MASK		(0xf << 0)
# define VR8E_PANEL_INTERFACE_CMOS	(0 << 4)
# define VR8E_PANEL_INTERFACE_LVDS	(1 << 4)
# define VR8E_FORCE_DEFAULT_PANEL	(1 << 5)

/* Graphics BIOS scratch 1
 */
#define VR8F	    0x8F
# define VR8F_VCH_PRESENT		(1 << 0)
# define VR8F_DISPLAY_CONN		(1 << 1)
# define VR8F_POWER_MASK		(0x3c)
# define VR8F_POWER_POS			(2)


struct ivch_priv {
	bool quiet;

	uint16_t width, height;

	uint16_t save_VR01;
	uint16_t save_VR40;
};


static void ivch_dump_regs(struct intel_dvo_device *dvo);

/**
 * Reads a register on the ivch.
 *
 * Each of the 256 registers are 16 bits long.
 */
static bool ivch_read(struct intel_dvo_device *dvo, int addr, uint16_t *data)
{
	struct ivch_priv *priv = dvo->dev_priv;
	struct i2c_adapter *adapter = dvo->i2c_bus;
	struct intel_i2c_chan *i2cbus = container_of(adapter, struct intel_i2c_chan, adapter);
	u8 out_buf[1];
	u8 in_buf[2];

	struct i2c_msg msgs[] = {
		{
			.addr = dvo->slave_addr,
			.flags = I2C_M_RD,
			.len = 0,
		},
		{
			.addr = 0,
			.flags = I2C_M_NOSTART,
			.len = 1,
			.buf = out_buf,
		},
		{
			.addr = dvo->slave_addr,
			.flags = I2C_M_RD | I2C_M_NOSTART,
			.len = 2,
			.buf = in_buf,
		}
	};

	out_buf[0] = addr;

	if (i2c_transfer(&i2cbus->adapter, msgs, 3) == 3) {
		*data = (in_buf[1] << 8) | in_buf[0];
		return true;
	};

	if (!priv->quiet) {
		DRM_DEBUG("Unable to read register 0x%02x from %s:%02x.\n",
			  addr, i2cbus->adapter.name, dvo->slave_addr);
	}
	return false;
}

/** Writes a 16-bit register on the ivch */
static bool ivch_write(struct intel_dvo_device *dvo, int addr, uint16_t data)
{
	struct ivch_priv *priv = dvo->dev_priv;
	struct i2c_adapter *adapter = dvo->i2c_bus;
	struct intel_i2c_chan *i2cbus = container_of(adapter, struct intel_i2c_chan, adapter);
	u8 out_buf[3];
	struct i2c_msg msg = {
		.addr = dvo->slave_addr,
		.flags = 0,
		.len = 3,
		.buf = out_buf,
	};

	out_buf[0] = addr;
	out_buf[1] = data & 0xff;
	out_buf[2] = data >> 8;

	if (i2c_transfer(&i2cbus->adapter, &msg, 1) == 1)
		return true;

	if (!priv->quiet) {
		DRM_DEBUG("Unable to write register 0x%02x to %s:%d.\n",
			  addr, i2cbus->adapter.name, dvo->slave_addr);
	}

	return false;
}

/** Probes the given bus and slave address for an ivch */
static bool ivch_init(struct intel_dvo_device *dvo,
		      struct i2c_adapter *adapter)
{
	struct ivch_priv *priv;
	uint16_t temp;

	priv = kzalloc(sizeof(struct ivch_priv), GFP_KERNEL);
	if (priv == NULL)
		return false;

	dvo->i2c_bus = adapter;
	dvo->dev_priv = priv;
	priv->quiet = true;

	if (!ivch_read(dvo, VR00, &temp))
		goto out;
	priv->quiet = false;

	/* Since the identification bits are probably zeroes, which doesn't seem
	 * very unique, check that the value in the base address field matches
	 * the address it's responding on.
	 */
	if ((temp & VR00_BASE_ADDRESS_MASK) != dvo->slave_addr) {
		DRM_DEBUG("ivch detect failed due to address mismatch "
			  "(%d vs %d)\n",
			  (temp & VR00_BASE_ADDRESS_MASK), dvo->slave_addr);
		goto out;
	}

	ivch_read(dvo, VR20, &priv->width);
	ivch_read(dvo, VR21, &priv->height);

	return true;

out:
	kfree(priv);
	return false;
}

static enum drm_connector_status ivch_detect(struct intel_dvo_device *dvo)
{
	return connector_status_connected;
}

static enum drm_mode_status ivch_mode_valid(struct intel_dvo_device *dvo,
					    struct drm_display_mode *mode)
{
	if (mode->clock > 112000)
		return MODE_CLOCK_HIGH;

	return MODE_OK;
}

/** Sets the power state of the panel connected to the ivch */
static void ivch_dpms(struct intel_dvo_device *dvo, int mode)
{
	int i;
	uint16_t vr01, vr30, backlight;

	/* Set the new power state of the panel. */
	if (!ivch_read(dvo, VR01, &vr01))
		return;

	if (mode == DRM_MODE_DPMS_ON)
		backlight = 1;
	else
		backlight = 0;
	ivch_write(dvo, VR80, backlight);

	if (mode == DRM_MODE_DPMS_ON)
		vr01 |= VR01_LCD_ENABLE | VR01_DVO_ENABLE;
	else
		vr01 &= ~(VR01_LCD_ENABLE | VR01_DVO_ENABLE);

	ivch_write(dvo, VR01, vr01);

	/* Wait for the panel to make its state transition */
	for (i = 0; i < 100; i++) {
		if (!ivch_read(dvo, VR30, &vr30))
			break;

		if (((vr30 & VR30_PANEL_ON) != 0) == (mode == DRM_MODE_DPMS_ON))
			break;
		udelay(1000);
	}
	/* wait some more; vch may fail to resync sometimes without this */
	udelay(16 * 1000);
}

static void ivch_mode_set(struct intel_dvo_device *dvo,
			  struct drm_display_mode *mode,
			  struct drm_display_mode *adjusted_mode)
{
	uint16_t vr40 = 0;
	uint16_t vr01;

	vr01 = 0;
	vr40 = (VR40_STALL_ENABLE | VR40_VERTICAL_INTERP_ENABLE |
		VR40_HORIZONTAL_INTERP_ENABLE);

	if (mode->hdisplay != adjusted_mode->hdisplay ||
	    mode->vdisplay != adjusted_mode->vdisplay) {
		uint16_t x_ratio, y_ratio;

		vr01 |= VR01_PANEL_FIT_ENABLE;
		vr40 |= VR40_CLOCK_GATING_ENABLE;
		x_ratio = (((mode->hdisplay - 1) << 16) /
			   (adjusted_mode->hdisplay - 1)) >> 2;
		y_ratio = (((mode->vdisplay - 1) << 16) /
			   (adjusted_mode->vdisplay - 1)) >> 2;
		ivch_write (dvo, VR42, x_ratio);
		ivch_write (dvo, VR41, y_ratio);
	} else {
		vr01 &= ~VR01_PANEL_FIT_ENABLE;
		vr40 &= ~VR40_CLOCK_GATING_ENABLE;
	}
	vr40 &= ~VR40_AUTO_RATIO_ENABLE;

	ivch_write(dvo, VR01, vr01);
	ivch_write(dvo, VR40, vr40);

	ivch_dump_regs(dvo);
}

static void ivch_dump_regs(struct intel_dvo_device *dvo)
{
	uint16_t val;

	ivch_read(dvo, VR00, &val);
	DRM_DEBUG("VR00: 0x%04x\n", val);
	ivch_read(dvo, VR01, &val);
	DRM_DEBUG("VR01: 0x%04x\n", val);
	ivch_read(dvo, VR30, &val);
	DRM_DEBUG("VR30: 0x%04x\n", val);
	ivch_read(dvo, VR40, &val);
	DRM_DEBUG("VR40: 0x%04x\n", val);

	/* GPIO registers */
	ivch_read(dvo, VR80, &val);
	DRM_DEBUG("VR80: 0x%04x\n", val);
	ivch_read(dvo, VR81, &val);
	DRM_DEBUG("VR81: 0x%04x\n", val);
	ivch_read(dvo, VR82, &val);
	DRM_DEBUG("VR82: 0x%04x\n", val);
	ivch_read(dvo, VR83, &val);
	DRM_DEBUG("VR83: 0x%04x\n", val);
	ivch_read(dvo, VR84, &val);
	DRM_DEBUG("VR84: 0x%04x\n", val);
	ivch_read(dvo, VR85, &val);
	DRM_DEBUG("VR85: 0x%04x\n", val);
	ivch_read(dvo, VR86, &val);
	DRM_DEBUG("VR86: 0x%04x\n", val);
	ivch_read(dvo, VR87, &val);
	DRM_DEBUG("VR87: 0x%04x\n", val);
	ivch_read(dvo, VR88, &val);
	DRM_DEBUG("VR88: 0x%04x\n", val);

	/* Scratch register 0 - AIM Panel type */
	ivch_read(dvo, VR8E, &val);
	DRM_DEBUG("VR8E: 0x%04x\n", val);

	/* Scratch register 1 - Status register */
	ivch_read(dvo, VR8F, &val);
	DRM_DEBUG("VR8F: 0x%04x\n", val);
}

static void ivch_save(struct intel_dvo_device *dvo)
{
	struct ivch_priv *priv = dvo->dev_priv;

	ivch_read(dvo, VR01, &priv->save_VR01);
	ivch_read(dvo, VR40, &priv->save_VR40);
}

static void ivch_restore(struct intel_dvo_device *dvo)
{
	struct ivch_priv *priv = dvo->dev_priv;

	ivch_write(dvo, VR01, priv->save_VR01);
	ivch_write(dvo, VR40, priv->save_VR40);
}

static void ivch_destroy(struct intel_dvo_device *dvo)
{
	struct ivch_priv *priv = dvo->dev_priv;

	if (priv) {
		kfree(priv);
		dvo->dev_priv = NULL;
	}
}

struct intel_dvo_dev_ops ivch_ops= {
	.init = ivch_init,
	.dpms = ivch_dpms,
	.save = ivch_save,
	.restore = ivch_restore,
	.mode_valid = ivch_mode_valid,
	.mode_set = ivch_mode_set,
	.detect = ivch_detect,
	.dump_regs = ivch_dump_regs,
	.destroy = ivch_destroy,
};
Commit	Line	Data
79e53945 JB	1	/*
	2	* Copyright © 2006 Intel Corporation
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice (including the next
	12	* paragraph) shall be included in all copies or substantial portions of the
	13	* Software.
	14	*
	15	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	16	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	17	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	18	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	19	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
	20	* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
	21	* DEALINGS IN THE SOFTWARE.
	22	*
	23	* Authors:
	24	* Eric Anholt <eric@anholt.net>
	25	*
	26	*/
	27
	28	#include "dvo.h"
	29
	30	/*
	31	* register definitions for the i82807aa.
	32	*
	33	* Documentation on this chipset can be found in datasheet #29069001 at
	34	* intel.com.
	35	*/
	36
	37	/*
	38	* VCH Revision & GMBus Base Addr
	39	*/
	40	#define VR00 0x00
	41	# define VR00_BASE_ADDRESS_MASK 0x007f
	42
	43	/*
	44	* Functionality Enable
	45	*/
	46	#define VR01 0x01
	47
	48	/*
	49	* Enable the panel fitter
	50	*/
	51	# define VR01_PANEL_FIT_ENABLE (1 << 3)
	52	/*
	53	* Enables the LCD display.
	54	*
	55	* This must not be set while VR01_DVO_BYPASS_ENABLE is set.
	56	*/
	57	# define VR01_LCD_ENABLE (1 << 2)
	58	/** Enables the DVO repeater. */
	59	# define VR01_DVO_BYPASS_ENABLE (1 << 1)
	60	/** Enables the DVO clock */
	61	# define VR01_DVO_ENABLE (1 << 0)
	62
	63	/*
	64	* LCD Interface Format
65	*/
66	#define VR10 0x10
67	/** Enables LVDS output instead of CMOS */
68	# define VR10_LVDS_ENABLE (1 << 4)
69	/** Enables 18-bit LVDS output. */
70	# define VR10_INTERFACE_1X18 (0 << 2)
71	/** Enables 24-bit LVDS or CMOS output */
72	# define VR10_INTERFACE_1X24 (1 << 2)
73	/** Enables 2x18-bit LVDS or CMOS output. */
74	# define VR10_INTERFACE_2X18 (2 << 2)
75	/** Enables 2x24-bit LVDS output */
76	# define VR10_INTERFACE_2X24 (3 << 2)
77
78	/*
79	* VR20 LCD Horizontal Display Size
80	*/
81	#define VR20 0x20
82
83	/*
84	* LCD Vertical Display Size
85	*/
86	#define VR21 0x20
87
88	/*
89	* Panel power down status
90	*/
91	#define VR30 0x30
92	/** Read only bit indicating that the panel is not in a safe poweroff state. */
93	# define VR30_PANEL_ON (1 << 15)
94
95	#define VR40 0x40
96	# define VR40_STALL_ENABLE (1 << 13)
97	# define VR40_VERTICAL_INTERP_ENABLE (1 << 12)
98	# define VR40_ENHANCED_PANEL_FITTING (1 << 11)
99	# define VR40_HORIZONTAL_INTERP_ENABLE (1 << 10)
100	# define VR40_AUTO_RATIO_ENABLE (1 << 9)
101	# define VR40_CLOCK_GATING_ENABLE (1 << 8)
102
103	/*
104	* Panel Fitting Vertical Ratio
105	* (((image_height - 1) << 16) / ((panel_height - 1))) >> 2
106	*/
107	#define VR41 0x41
108
109	/*
110	* Panel Fitting Horizontal Ratio
111	* (((image_width - 1) << 16) / ((panel_width - 1))) >> 2
112	*/
113	#define VR42 0x42
114
115	/*
116	* Horizontal Image Size
117	*/
118	#define VR43 0x43
119
120	/* VR80 GPIO 0
121	*/
122	#define VR80 0x80
123	#define VR81 0x81
124	#define VR82 0x82
125	#define VR83 0x83
126	#define VR84 0x84
127	#define VR85 0x85
128	#define VR86 0x86
129	#define VR87 0x87
130
131	/* VR88 GPIO 8
132	*/
133	#define VR88 0x88
134
135	/* Graphics BIOS scratch 0
136	*/
137	#define VR8E 0x8E
138	# define VR8E_PANEL_TYPE_MASK (0xf << 0)
139	# define VR8E_PANEL_INTERFACE_CMOS (0 << 4)
140	# define VR8E_PANEL_INTERFACE_LVDS (1 << 4)
141	# define VR8E_FORCE_DEFAULT_PANEL (1 << 5)
142
143	/* Graphics BIOS scratch 1
144	*/
145	#define VR8F 0x8F
146	# define VR8F_VCH_PRESENT (1 << 0)
147	# define VR8F_DISPLAY_CONN (1 << 1)
148	# define VR8F_POWER_MASK (0x3c)
149	# define VR8F_POWER_POS (2)
150
151
152	struct ivch_priv {
153	bool quiet;
154
155	uint16_t width, height;
156
157	uint16_t save_VR01;
158	uint16_t save_VR40;
159	};
160
161
162	static void ivch_dump_regs(struct intel_dvo_device *dvo);
163
164	/**
165	* Reads a register on the ivch.
166	*
167	* Each of the 256 registers are 16 bits long.
168	*/
169	static bool ivch_read(struct intel_dvo_device dvo, int addr, uint16_t data)
170	{
171	struct ivch_priv *priv = dvo->dev_priv;
f9c10a9b KP	172	struct i2c_adapter *adapter = dvo->i2c_bus;
f9c10a9b KP	173	struct intel_i2c_chan *i2cbus = container_of(adapter, struct intel_i2c_chan, adapter);
79e53945 JB	174	u8 out_buf[1];
	175	u8 in_buf[2];
	176
	177	struct i2c_msg msgs[] = {
	178	{
f9c10a9b	179	.addr = dvo->slave_addr,
79e53945 JB	180	.flags = I2C_M_RD,
	181	.len = 0,
	182	},
	183	{
	184	.addr = 0,
	185	.flags = I2C_M_NOSTART,
	186	.len = 1,
	187	.buf = out_buf,
	188	},
	189	{
f9c10a9b	190	.addr = dvo->slave_addr,
79e53945 JB	191	.flags = I2C_M_RD \| I2C_M_NOSTART,
	192	.len = 2,
	193	.buf = in_buf,
	194	}
	195	};
	196
	197	out_buf[0] = addr;
	198
	199	if (i2c_transfer(&i2cbus->adapter, msgs, 3) == 3) {
	200	*data = (in_buf[1] << 8) \| in_buf[0];
	201	return true;
	202	};
	203
	204	if (!priv->quiet) {
	205	DRM_DEBUG("Unable to read register 0x%02x from %s:%02x.\n",
f9c10a9b	206	addr, i2cbus->adapter.name, dvo->slave_addr);
79e53945 JB	207	}
	208	return false;
	209	}
	210
	211	/** Writes a 16-bit register on the ivch */
	212	static bool ivch_write(struct intel_dvo_device *dvo, int addr, uint16_t data)
	213	{
	214	struct ivch_priv *priv = dvo->dev_priv;
f9c10a9b KP	215	struct i2c_adapter *adapter = dvo->i2c_bus;
f9c10a9b KP	216	struct intel_i2c_chan *i2cbus = container_of(adapter, struct intel_i2c_chan, adapter);
79e53945 JB	217	u8 out_buf[3];
79e53945 JB	218	struct i2c_msg msg = {
f9c10a9b	219	.addr = dvo->slave_addr,
79e53945 JB	220	.flags = 0,
	221	.len = 3,
	222	.buf = out_buf,
	223	};
	224
	225	out_buf[0] = addr;
	226	out_buf[1] = data & 0xff;
	227	out_buf[2] = data >> 8;
	228
	229	if (i2c_transfer(&i2cbus->adapter, &msg, 1) == 1)
	230	return true;
	231
	232	if (!priv->quiet) {
	233	DRM_DEBUG("Unable to write register 0x%02x to %s:%d.\n",
f9c10a9b	234	addr, i2cbus->adapter.name, dvo->slave_addr);
79e53945 JB	235	}
	236
	237	return false;
	238	}
	239
	240	/** Probes the given bus and slave address for an ivch */
	241	static bool ivch_init(struct intel_dvo_device *dvo,
f9c10a9b	242	struct i2c_adapter *adapter)
79e53945 JB	243	{
	244	struct ivch_priv *priv;
	245	uint16_t temp;
	246
	247	priv = kzalloc(sizeof(struct ivch_priv), GFP_KERNEL);
	248	if (priv == NULL)
	249	return false;
	250
f9c10a9b	251	dvo->i2c_bus = adapter;
79e53945 JB	252	dvo->dev_priv = priv;
	253	priv->quiet = true;
	254
	255	if (!ivch_read(dvo, VR00, &temp))
	256	goto out;
	257	priv->quiet = false;
	258
	259	/* Since the identification bits are probably zeroes, which doesn't seem
	260	* very unique, check that the value in the base address field matches
	261	* the address it's responding on.
	262	*/
	263	if ((temp & VR00_BASE_ADDRESS_MASK) != dvo->slave_addr) {
	264	DRM_DEBUG("ivch detect failed due to address mismatch "
	265	"(%d vs %d)\n",
	266	(temp & VR00_BASE_ADDRESS_MASK), dvo->slave_addr);
	267	goto out;
	268	}
	269
	270	ivch_read(dvo, VR20, &priv->width);
	271	ivch_read(dvo, VR21, &priv->height);
	272
	273	return true;
	274
	275	out:
	276	kfree(priv);
	277	return false;
	278	}
	279
	280	static enum drm_connector_status ivch_detect(struct intel_dvo_device *dvo)
	281	{
	282	return connector_status_connected;
	283	}
	284
	285	static enum drm_mode_status ivch_mode_valid(struct intel_dvo_device *dvo,
	286	struct drm_display_mode *mode)
	287	{
	288	if (mode->clock > 112000)
	289	return MODE_CLOCK_HIGH;
	290
	291	return MODE_OK;
	292	}
	293
	294	/** Sets the power state of the panel connected to the ivch */
	295	static void ivch_dpms(struct intel_dvo_device *dvo, int mode)
	296	{
	297	int i;
	298	uint16_t vr01, vr30, backlight;
	299
	300	/* Set the new power state of the panel. */
	301	if (!ivch_read(dvo, VR01, &vr01))
	302	return;
	303
	304	if (mode == DRM_MODE_DPMS_ON)
	305	backlight = 1;
	306	else
	307	backlight = 0;
	308	ivch_write(dvo, VR80, backlight);
	309
	310	if (mode == DRM_MODE_DPMS_ON)
	311	vr01 \|= VR01_LCD_ENABLE \| VR01_DVO_ENABLE;
	312	else
	313	vr01 &= ~(VR01_LCD_ENABLE \| VR01_DVO_ENABLE);
	314
	315	ivch_write(dvo, VR01, vr01);
316
317	/* Wait for the panel to make its state transition */
318	for (i = 0; i < 100; i++) {
319	if (!ivch_read(dvo, VR30, &vr30))
320	break;
321
322	if (((vr30 & VR30_PANEL_ON) != 0) == (mode == DRM_MODE_DPMS_ON))
323	break;
324	udelay(1000);
325	}
326	/* wait some more; vch may fail to resync sometimes without this */
327	udelay(16 * 1000);
328	}
329
330	static void ivch_mode_set(struct intel_dvo_device *dvo,
331	struct drm_display_mode *mode,
332	struct drm_display_mode *adjusted_mode)
333	{
334	uint16_t vr40 = 0;
335	uint16_t vr01;
336
337	vr01 = 0;
338	vr40 = (VR40_STALL_ENABLE \| VR40_VERTICAL_INTERP_ENABLE \|
339	VR40_HORIZONTAL_INTERP_ENABLE);
340
341	if (mode->hdisplay != adjusted_mode->hdisplay \|\|
342	mode->vdisplay != adjusted_mode->vdisplay) {
343	uint16_t x_ratio, y_ratio;
344
345	vr01 \|= VR01_PANEL_FIT_ENABLE;
346	vr40 \|= VR40_CLOCK_GATING_ENABLE;
347	x_ratio = (((mode->hdisplay - 1) << 16) /
348	(adjusted_mode->hdisplay - 1)) >> 2;
349	y_ratio = (((mode->vdisplay - 1) << 16) /
350	(adjusted_mode->vdisplay - 1)) >> 2;
351	ivch_write (dvo, VR42, x_ratio);
352	ivch_write (dvo, VR41, y_ratio);
353	} else {
354	vr01 &= ~VR01_PANEL_FIT_ENABLE;
355	vr40 &= ~VR40_CLOCK_GATING_ENABLE;
356	}
357	vr40 &= ~VR40_AUTO_RATIO_ENABLE;
358
359	ivch_write(dvo, VR01, vr01);
360	ivch_write(dvo, VR40, vr40);
361
362	ivch_dump_regs(dvo);
363	}
364
365	static void ivch_dump_regs(struct intel_dvo_device *dvo)
366	{
367	uint16_t val;
368
369	ivch_read(dvo, VR00, &val);
370	DRM_DEBUG("VR00: 0x%04x\n", val);
371	ivch_read(dvo, VR01, &val);
372	DRM_DEBUG("VR01: 0x%04x\n", val);
373	ivch_read(dvo, VR30, &val);
374	DRM_DEBUG("VR30: 0x%04x\n", val);
375	ivch_read(dvo, VR40, &val);
376	DRM_DEBUG("VR40: 0x%04x\n", val);
377
378	/* GPIO registers */
379	ivch_read(dvo, VR80, &val);
380	DRM_DEBUG("VR80: 0x%04x\n", val);
381	ivch_read(dvo, VR81, &val);
382	DRM_DEBUG("VR81: 0x%04x\n", val);
383	ivch_read(dvo, VR82, &val);
384	DRM_DEBUG("VR82: 0x%04x\n", val);
385	ivch_read(dvo, VR83, &val);
386	DRM_DEBUG("VR83: 0x%04x\n", val);
387	ivch_read(dvo, VR84, &val);
388	DRM_DEBUG("VR84: 0x%04x\n", val);
389	ivch_read(dvo, VR85, &val);
390	DRM_DEBUG("VR85: 0x%04x\n", val);
391	ivch_read(dvo, VR86, &val);
392	DRM_DEBUG("VR86: 0x%04x\n", val);
393	ivch_read(dvo, VR87, &val);
394	DRM_DEBUG("VR87: 0x%04x\n", val);
395	ivch_read(dvo, VR88, &val);
396	DRM_DEBUG("VR88: 0x%04x\n", val);
397
398	/* Scratch register 0 - AIM Panel type */
399	ivch_read(dvo, VR8E, &val);
400	DRM_DEBUG("VR8E: 0x%04x\n", val);
401
402	/* Scratch register 1 - Status register */
403	ivch_read(dvo, VR8F, &val);
404	DRM_DEBUG("VR8F: 0x%04x\n", val);
405	}
406
407	static void ivch_save(struct intel_dvo_device *dvo)
408	{
409	struct ivch_priv *priv = dvo->dev_priv;
410
411	ivch_read(dvo, VR01, &priv->save_VR01);
412	ivch_read(dvo, VR40, &priv->save_VR40);
413	}
414
415	static void ivch_restore(struct intel_dvo_device *dvo)
416	{
417	struct ivch_priv *priv = dvo->dev_priv;
418
419	ivch_write(dvo, VR01, priv->save_VR01);
420	ivch_write(dvo, VR40, priv->save_VR40);
421	}
422
423	static void ivch_destroy(struct intel_dvo_device *dvo)
424	{
425	struct ivch_priv *priv = dvo->dev_priv;
426
427	if (priv) {
428	kfree(priv);
429	dvo->dev_priv = NULL;
430	}
431	}
432
433	struct intel_dvo_dev_ops ivch_ops= {
434	.init = ivch_init,
435	.dpms = ivch_dpms,
436	.save = ivch_save,
437	.restore = ivch_restore,
438	.mode_valid = ivch_mode_valid,
439	.mode_set = ivch_mode_set,
440	.detect = ivch_detect,
441	.dump_regs = ivch_dump_regs,
442	.destroy = ivch_destroy,
443	};