Commit | Line | Data |
---|---|---|
2017263e BG |
1 | /* |
2 | * Copyright © 2008 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | * Keith Packard <keithp@keithp.com> | |
26 | * | |
27 | */ | |
28 | ||
29 | #include <linux/seq_file.h> | |
f3cd474b | 30 | #include <linux/debugfs.h> |
5a0e3ad6 | 31 | #include <linux/slab.h> |
2d1a8a48 | 32 | #include <linux/export.h> |
6d2b8885 | 33 | #include <linux/list_sort.h> |
ec013e7f | 34 | #include <asm/msr-index.h> |
760285e7 | 35 | #include <drm/drmP.h> |
4e5359cd | 36 | #include "intel_drv.h" |
e5c65260 | 37 | #include "intel_ringbuffer.h" |
760285e7 | 38 | #include <drm/i915_drm.h> |
2017263e BG |
39 | #include "i915_drv.h" |
40 | ||
41 | #define DRM_I915_RING_DEBUG 1 | |
42 | ||
43 | ||
44 | #if defined(CONFIG_DEBUG_FS) | |
45 | ||
f13d3f73 | 46 | enum { |
69dc4987 | 47 | ACTIVE_LIST, |
f13d3f73 | 48 | INACTIVE_LIST, |
d21d5975 | 49 | PINNED_LIST, |
f13d3f73 | 50 | }; |
2017263e | 51 | |
70d39fe4 CW |
52 | static const char *yesno(int v) |
53 | { | |
54 | return v ? "yes" : "no"; | |
55 | } | |
56 | ||
57 | static int i915_capabilities(struct seq_file *m, void *data) | |
58 | { | |
59 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
60 | struct drm_device *dev = node->minor->dev; | |
61 | const struct intel_device_info *info = INTEL_INFO(dev); | |
62 | ||
63 | seq_printf(m, "gen: %d\n", info->gen); | |
03d00ac5 | 64 | seq_printf(m, "pch: %d\n", INTEL_PCH_TYPE(dev)); |
79fc46df DL |
65 | #define PRINT_FLAG(x) seq_printf(m, #x ": %s\n", yesno(info->x)) |
66 | #define SEP_SEMICOLON ; | |
67 | DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG, SEP_SEMICOLON); | |
68 | #undef PRINT_FLAG | |
69 | #undef SEP_SEMICOLON | |
70d39fe4 CW |
70 | |
71 | return 0; | |
72 | } | |
2017263e | 73 | |
05394f39 | 74 | static const char *get_pin_flag(struct drm_i915_gem_object *obj) |
a6172a80 | 75 | { |
05394f39 | 76 | if (obj->user_pin_count > 0) |
a6172a80 | 77 | return "P"; |
05394f39 | 78 | else if (obj->pin_count > 0) |
a6172a80 CW |
79 | return "p"; |
80 | else | |
81 | return " "; | |
82 | } | |
83 | ||
05394f39 | 84 | static const char *get_tiling_flag(struct drm_i915_gem_object *obj) |
a6172a80 | 85 | { |
0206e353 AJ |
86 | switch (obj->tiling_mode) { |
87 | default: | |
88 | case I915_TILING_NONE: return " "; | |
89 | case I915_TILING_X: return "X"; | |
90 | case I915_TILING_Y: return "Y"; | |
91 | } | |
a6172a80 CW |
92 | } |
93 | ||
1d693bcc BW |
94 | static inline const char *get_global_flag(struct drm_i915_gem_object *obj) |
95 | { | |
96 | return obj->has_global_gtt_mapping ? "g" : " "; | |
97 | } | |
98 | ||
37811fcc CW |
99 | static void |
100 | describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj) | |
101 | { | |
1d693bcc | 102 | struct i915_vma *vma; |
fb1ae911 | 103 | seq_printf(m, "%pK: %s%s%s %8zdKiB %02x %02x %u %u %u%s%s%s", |
37811fcc CW |
104 | &obj->base, |
105 | get_pin_flag(obj), | |
106 | get_tiling_flag(obj), | |
1d693bcc | 107 | get_global_flag(obj), |
a05a5862 | 108 | obj->base.size / 1024, |
37811fcc CW |
109 | obj->base.read_domains, |
110 | obj->base.write_domain, | |
0201f1ec CW |
111 | obj->last_read_seqno, |
112 | obj->last_write_seqno, | |
caea7476 | 113 | obj->last_fenced_seqno, |
84734a04 | 114 | i915_cache_level_str(obj->cache_level), |
37811fcc CW |
115 | obj->dirty ? " dirty" : "", |
116 | obj->madv == I915_MADV_DONTNEED ? " purgeable" : ""); | |
117 | if (obj->base.name) | |
118 | seq_printf(m, " (name: %d)", obj->base.name); | |
c110a6d7 CW |
119 | if (obj->pin_count) |
120 | seq_printf(m, " (pinned x %d)", obj->pin_count); | |
cc98b413 CW |
121 | if (obj->pin_display) |
122 | seq_printf(m, " (display)"); | |
37811fcc CW |
123 | if (obj->fence_reg != I915_FENCE_REG_NONE) |
124 | seq_printf(m, " (fence: %d)", obj->fence_reg); | |
1d693bcc BW |
125 | list_for_each_entry(vma, &obj->vma_list, vma_link) { |
126 | if (!i915_is_ggtt(vma->vm)) | |
127 | seq_puts(m, " (pp"); | |
128 | else | |
129 | seq_puts(m, " (g"); | |
130 | seq_printf(m, "gtt offset: %08lx, size: %08lx)", | |
131 | vma->node.start, vma->node.size); | |
132 | } | |
c1ad11fc CW |
133 | if (obj->stolen) |
134 | seq_printf(m, " (stolen: %08lx)", obj->stolen->start); | |
6299f992 CW |
135 | if (obj->pin_mappable || obj->fault_mappable) { |
136 | char s[3], *t = s; | |
137 | if (obj->pin_mappable) | |
138 | *t++ = 'p'; | |
139 | if (obj->fault_mappable) | |
140 | *t++ = 'f'; | |
141 | *t = '\0'; | |
142 | seq_printf(m, " (%s mappable)", s); | |
143 | } | |
69dc4987 CW |
144 | if (obj->ring != NULL) |
145 | seq_printf(m, " (%s)", obj->ring->name); | |
37811fcc CW |
146 | } |
147 | ||
3ccfd19d BW |
148 | static void describe_ctx(struct seq_file *m, struct i915_hw_context *ctx) |
149 | { | |
150 | seq_putc(m, ctx->is_initialized ? 'I' : 'i'); | |
151 | seq_putc(m, ctx->remap_slice ? 'R' : 'r'); | |
152 | seq_putc(m, ' '); | |
153 | } | |
154 | ||
433e12f7 | 155 | static int i915_gem_object_list_info(struct seq_file *m, void *data) |
2017263e BG |
156 | { |
157 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
433e12f7 BG |
158 | uintptr_t list = (uintptr_t) node->info_ent->data; |
159 | struct list_head *head; | |
2017263e | 160 | struct drm_device *dev = node->minor->dev; |
5cef07e1 BW |
161 | struct drm_i915_private *dev_priv = dev->dev_private; |
162 | struct i915_address_space *vm = &dev_priv->gtt.base; | |
ca191b13 | 163 | struct i915_vma *vma; |
8f2480fb CW |
164 | size_t total_obj_size, total_gtt_size; |
165 | int count, ret; | |
de227ef0 CW |
166 | |
167 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
168 | if (ret) | |
169 | return ret; | |
2017263e | 170 | |
ca191b13 | 171 | /* FIXME: the user of this interface might want more than just GGTT */ |
433e12f7 BG |
172 | switch (list) { |
173 | case ACTIVE_LIST: | |
267f0c90 | 174 | seq_puts(m, "Active:\n"); |
5cef07e1 | 175 | head = &vm->active_list; |
433e12f7 BG |
176 | break; |
177 | case INACTIVE_LIST: | |
267f0c90 | 178 | seq_puts(m, "Inactive:\n"); |
5cef07e1 | 179 | head = &vm->inactive_list; |
433e12f7 | 180 | break; |
433e12f7 | 181 | default: |
de227ef0 CW |
182 | mutex_unlock(&dev->struct_mutex); |
183 | return -EINVAL; | |
2017263e | 184 | } |
2017263e | 185 | |
8f2480fb | 186 | total_obj_size = total_gtt_size = count = 0; |
ca191b13 BW |
187 | list_for_each_entry(vma, head, mm_list) { |
188 | seq_printf(m, " "); | |
189 | describe_obj(m, vma->obj); | |
190 | seq_printf(m, "\n"); | |
191 | total_obj_size += vma->obj->base.size; | |
192 | total_gtt_size += vma->node.size; | |
8f2480fb | 193 | count++; |
2017263e | 194 | } |
de227ef0 | 195 | mutex_unlock(&dev->struct_mutex); |
5e118f41 | 196 | |
8f2480fb CW |
197 | seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n", |
198 | count, total_obj_size, total_gtt_size); | |
2017263e BG |
199 | return 0; |
200 | } | |
201 | ||
6d2b8885 CW |
202 | static int obj_rank_by_stolen(void *priv, |
203 | struct list_head *A, struct list_head *B) | |
204 | { | |
205 | struct drm_i915_gem_object *a = | |
b25cb2f8 | 206 | container_of(A, struct drm_i915_gem_object, obj_exec_link); |
6d2b8885 | 207 | struct drm_i915_gem_object *b = |
b25cb2f8 | 208 | container_of(B, struct drm_i915_gem_object, obj_exec_link); |
6d2b8885 CW |
209 | |
210 | return a->stolen->start - b->stolen->start; | |
211 | } | |
212 | ||
213 | static int i915_gem_stolen_list_info(struct seq_file *m, void *data) | |
214 | { | |
215 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
216 | struct drm_device *dev = node->minor->dev; | |
217 | struct drm_i915_private *dev_priv = dev->dev_private; | |
218 | struct drm_i915_gem_object *obj; | |
219 | size_t total_obj_size, total_gtt_size; | |
220 | LIST_HEAD(stolen); | |
221 | int count, ret; | |
222 | ||
223 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
224 | if (ret) | |
225 | return ret; | |
226 | ||
227 | total_obj_size = total_gtt_size = count = 0; | |
228 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) { | |
229 | if (obj->stolen == NULL) | |
230 | continue; | |
231 | ||
b25cb2f8 | 232 | list_add(&obj->obj_exec_link, &stolen); |
6d2b8885 CW |
233 | |
234 | total_obj_size += obj->base.size; | |
235 | total_gtt_size += i915_gem_obj_ggtt_size(obj); | |
236 | count++; | |
237 | } | |
238 | list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) { | |
239 | if (obj->stolen == NULL) | |
240 | continue; | |
241 | ||
b25cb2f8 | 242 | list_add(&obj->obj_exec_link, &stolen); |
6d2b8885 CW |
243 | |
244 | total_obj_size += obj->base.size; | |
245 | count++; | |
246 | } | |
247 | list_sort(NULL, &stolen, obj_rank_by_stolen); | |
248 | seq_puts(m, "Stolen:\n"); | |
249 | while (!list_empty(&stolen)) { | |
b25cb2f8 | 250 | obj = list_first_entry(&stolen, typeof(*obj), obj_exec_link); |
6d2b8885 CW |
251 | seq_puts(m, " "); |
252 | describe_obj(m, obj); | |
253 | seq_putc(m, '\n'); | |
b25cb2f8 | 254 | list_del_init(&obj->obj_exec_link); |
6d2b8885 CW |
255 | } |
256 | mutex_unlock(&dev->struct_mutex); | |
257 | ||
258 | seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n", | |
259 | count, total_obj_size, total_gtt_size); | |
260 | return 0; | |
261 | } | |
262 | ||
6299f992 CW |
263 | #define count_objects(list, member) do { \ |
264 | list_for_each_entry(obj, list, member) { \ | |
f343c5f6 | 265 | size += i915_gem_obj_ggtt_size(obj); \ |
6299f992 CW |
266 | ++count; \ |
267 | if (obj->map_and_fenceable) { \ | |
f343c5f6 | 268 | mappable_size += i915_gem_obj_ggtt_size(obj); \ |
6299f992 CW |
269 | ++mappable_count; \ |
270 | } \ | |
271 | } \ | |
0206e353 | 272 | } while (0) |
6299f992 | 273 | |
2db8e9d6 CW |
274 | struct file_stats { |
275 | int count; | |
276 | size_t total, active, inactive, unbound; | |
277 | }; | |
278 | ||
279 | static int per_file_stats(int id, void *ptr, void *data) | |
280 | { | |
281 | struct drm_i915_gem_object *obj = ptr; | |
282 | struct file_stats *stats = data; | |
283 | ||
284 | stats->count++; | |
285 | stats->total += obj->base.size; | |
286 | ||
f343c5f6 | 287 | if (i915_gem_obj_ggtt_bound(obj)) { |
2db8e9d6 CW |
288 | if (!list_empty(&obj->ring_list)) |
289 | stats->active += obj->base.size; | |
290 | else | |
291 | stats->inactive += obj->base.size; | |
292 | } else { | |
293 | if (!list_empty(&obj->global_list)) | |
294 | stats->unbound += obj->base.size; | |
295 | } | |
296 | ||
297 | return 0; | |
298 | } | |
299 | ||
ca191b13 BW |
300 | #define count_vmas(list, member) do { \ |
301 | list_for_each_entry(vma, list, member) { \ | |
302 | size += i915_gem_obj_ggtt_size(vma->obj); \ | |
303 | ++count; \ | |
304 | if (vma->obj->map_and_fenceable) { \ | |
305 | mappable_size += i915_gem_obj_ggtt_size(vma->obj); \ | |
306 | ++mappable_count; \ | |
307 | } \ | |
308 | } \ | |
309 | } while (0) | |
310 | ||
311 | static int i915_gem_object_info(struct seq_file *m, void* data) | |
73aa808f CW |
312 | { |
313 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
314 | struct drm_device *dev = node->minor->dev; | |
315 | struct drm_i915_private *dev_priv = dev->dev_private; | |
b7abb714 CW |
316 | u32 count, mappable_count, purgeable_count; |
317 | size_t size, mappable_size, purgeable_size; | |
6299f992 | 318 | struct drm_i915_gem_object *obj; |
5cef07e1 | 319 | struct i915_address_space *vm = &dev_priv->gtt.base; |
2db8e9d6 | 320 | struct drm_file *file; |
ca191b13 | 321 | struct i915_vma *vma; |
73aa808f CW |
322 | int ret; |
323 | ||
324 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
325 | if (ret) | |
326 | return ret; | |
327 | ||
6299f992 CW |
328 | seq_printf(m, "%u objects, %zu bytes\n", |
329 | dev_priv->mm.object_count, | |
330 | dev_priv->mm.object_memory); | |
331 | ||
332 | size = count = mappable_size = mappable_count = 0; | |
35c20a60 | 333 | count_objects(&dev_priv->mm.bound_list, global_list); |
6299f992 CW |
334 | seq_printf(m, "%u [%u] objects, %zu [%zu] bytes in gtt\n", |
335 | count, mappable_count, size, mappable_size); | |
336 | ||
337 | size = count = mappable_size = mappable_count = 0; | |
ca191b13 | 338 | count_vmas(&vm->active_list, mm_list); |
6299f992 CW |
339 | seq_printf(m, " %u [%u] active objects, %zu [%zu] bytes\n", |
340 | count, mappable_count, size, mappable_size); | |
341 | ||
6299f992 | 342 | size = count = mappable_size = mappable_count = 0; |
ca191b13 | 343 | count_vmas(&vm->inactive_list, mm_list); |
6299f992 CW |
344 | seq_printf(m, " %u [%u] inactive objects, %zu [%zu] bytes\n", |
345 | count, mappable_count, size, mappable_size); | |
346 | ||
b7abb714 | 347 | size = count = purgeable_size = purgeable_count = 0; |
35c20a60 | 348 | list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) { |
6c085a72 | 349 | size += obj->base.size, ++count; |
b7abb714 CW |
350 | if (obj->madv == I915_MADV_DONTNEED) |
351 | purgeable_size += obj->base.size, ++purgeable_count; | |
352 | } | |
6c085a72 CW |
353 | seq_printf(m, "%u unbound objects, %zu bytes\n", count, size); |
354 | ||
6299f992 | 355 | size = count = mappable_size = mappable_count = 0; |
35c20a60 | 356 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) { |
6299f992 | 357 | if (obj->fault_mappable) { |
f343c5f6 | 358 | size += i915_gem_obj_ggtt_size(obj); |
6299f992 CW |
359 | ++count; |
360 | } | |
361 | if (obj->pin_mappable) { | |
f343c5f6 | 362 | mappable_size += i915_gem_obj_ggtt_size(obj); |
6299f992 CW |
363 | ++mappable_count; |
364 | } | |
b7abb714 CW |
365 | if (obj->madv == I915_MADV_DONTNEED) { |
366 | purgeable_size += obj->base.size; | |
367 | ++purgeable_count; | |
368 | } | |
6299f992 | 369 | } |
b7abb714 CW |
370 | seq_printf(m, "%u purgeable objects, %zu bytes\n", |
371 | purgeable_count, purgeable_size); | |
6299f992 CW |
372 | seq_printf(m, "%u pinned mappable objects, %zu bytes\n", |
373 | mappable_count, mappable_size); | |
374 | seq_printf(m, "%u fault mappable objects, %zu bytes\n", | |
375 | count, size); | |
376 | ||
93d18799 | 377 | seq_printf(m, "%zu [%lu] gtt total\n", |
853ba5d2 BW |
378 | dev_priv->gtt.base.total, |
379 | dev_priv->gtt.mappable_end - dev_priv->gtt.base.start); | |
73aa808f | 380 | |
267f0c90 | 381 | seq_putc(m, '\n'); |
2db8e9d6 CW |
382 | list_for_each_entry_reverse(file, &dev->filelist, lhead) { |
383 | struct file_stats stats; | |
384 | ||
385 | memset(&stats, 0, sizeof(stats)); | |
386 | idr_for_each(&file->object_idr, per_file_stats, &stats); | |
387 | seq_printf(m, "%s: %u objects, %zu bytes (%zu active, %zu inactive, %zu unbound)\n", | |
388 | get_pid_task(file->pid, PIDTYPE_PID)->comm, | |
389 | stats.count, | |
390 | stats.total, | |
391 | stats.active, | |
392 | stats.inactive, | |
393 | stats.unbound); | |
394 | } | |
395 | ||
73aa808f CW |
396 | mutex_unlock(&dev->struct_mutex); |
397 | ||
398 | return 0; | |
399 | } | |
400 | ||
aee56cff | 401 | static int i915_gem_gtt_info(struct seq_file *m, void *data) |
08c18323 CW |
402 | { |
403 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
404 | struct drm_device *dev = node->minor->dev; | |
1b50247a | 405 | uintptr_t list = (uintptr_t) node->info_ent->data; |
08c18323 CW |
406 | struct drm_i915_private *dev_priv = dev->dev_private; |
407 | struct drm_i915_gem_object *obj; | |
408 | size_t total_obj_size, total_gtt_size; | |
409 | int count, ret; | |
410 | ||
411 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
412 | if (ret) | |
413 | return ret; | |
414 | ||
415 | total_obj_size = total_gtt_size = count = 0; | |
35c20a60 | 416 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) { |
1b50247a CW |
417 | if (list == PINNED_LIST && obj->pin_count == 0) |
418 | continue; | |
419 | ||
267f0c90 | 420 | seq_puts(m, " "); |
08c18323 | 421 | describe_obj(m, obj); |
267f0c90 | 422 | seq_putc(m, '\n'); |
08c18323 | 423 | total_obj_size += obj->base.size; |
f343c5f6 | 424 | total_gtt_size += i915_gem_obj_ggtt_size(obj); |
08c18323 CW |
425 | count++; |
426 | } | |
427 | ||
428 | mutex_unlock(&dev->struct_mutex); | |
429 | ||
430 | seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n", | |
431 | count, total_obj_size, total_gtt_size); | |
432 | ||
433 | return 0; | |
434 | } | |
435 | ||
4e5359cd SF |
436 | static int i915_gem_pageflip_info(struct seq_file *m, void *data) |
437 | { | |
438 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
439 | struct drm_device *dev = node->minor->dev; | |
440 | unsigned long flags; | |
441 | struct intel_crtc *crtc; | |
442 | ||
443 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) { | |
9db4a9c7 JB |
444 | const char pipe = pipe_name(crtc->pipe); |
445 | const char plane = plane_name(crtc->plane); | |
4e5359cd SF |
446 | struct intel_unpin_work *work; |
447 | ||
448 | spin_lock_irqsave(&dev->event_lock, flags); | |
449 | work = crtc->unpin_work; | |
450 | if (work == NULL) { | |
9db4a9c7 | 451 | seq_printf(m, "No flip due on pipe %c (plane %c)\n", |
4e5359cd SF |
452 | pipe, plane); |
453 | } else { | |
e7d841ca | 454 | if (atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) { |
9db4a9c7 | 455 | seq_printf(m, "Flip queued on pipe %c (plane %c)\n", |
4e5359cd SF |
456 | pipe, plane); |
457 | } else { | |
9db4a9c7 | 458 | seq_printf(m, "Flip pending (waiting for vsync) on pipe %c (plane %c)\n", |
4e5359cd SF |
459 | pipe, plane); |
460 | } | |
461 | if (work->enable_stall_check) | |
267f0c90 | 462 | seq_puts(m, "Stall check enabled, "); |
4e5359cd | 463 | else |
267f0c90 | 464 | seq_puts(m, "Stall check waiting for page flip ioctl, "); |
e7d841ca | 465 | seq_printf(m, "%d prepares\n", atomic_read(&work->pending)); |
4e5359cd SF |
466 | |
467 | if (work->old_fb_obj) { | |
05394f39 CW |
468 | struct drm_i915_gem_object *obj = work->old_fb_obj; |
469 | if (obj) | |
f343c5f6 BW |
470 | seq_printf(m, "Old framebuffer gtt_offset 0x%08lx\n", |
471 | i915_gem_obj_ggtt_offset(obj)); | |
4e5359cd SF |
472 | } |
473 | if (work->pending_flip_obj) { | |
05394f39 CW |
474 | struct drm_i915_gem_object *obj = work->pending_flip_obj; |
475 | if (obj) | |
f343c5f6 BW |
476 | seq_printf(m, "New framebuffer gtt_offset 0x%08lx\n", |
477 | i915_gem_obj_ggtt_offset(obj)); | |
4e5359cd SF |
478 | } |
479 | } | |
480 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
481 | } | |
482 | ||
483 | return 0; | |
484 | } | |
485 | ||
2017263e BG |
486 | static int i915_gem_request_info(struct seq_file *m, void *data) |
487 | { | |
488 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
489 | struct drm_device *dev = node->minor->dev; | |
490 | drm_i915_private_t *dev_priv = dev->dev_private; | |
a2c7f6fd | 491 | struct intel_ring_buffer *ring; |
2017263e | 492 | struct drm_i915_gem_request *gem_request; |
a2c7f6fd | 493 | int ret, count, i; |
de227ef0 CW |
494 | |
495 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
496 | if (ret) | |
497 | return ret; | |
2017263e | 498 | |
c2c347a9 | 499 | count = 0; |
a2c7f6fd CW |
500 | for_each_ring(ring, dev_priv, i) { |
501 | if (list_empty(&ring->request_list)) | |
502 | continue; | |
503 | ||
504 | seq_printf(m, "%s requests:\n", ring->name); | |
c2c347a9 | 505 | list_for_each_entry(gem_request, |
a2c7f6fd | 506 | &ring->request_list, |
c2c347a9 CW |
507 | list) { |
508 | seq_printf(m, " %d @ %d\n", | |
509 | gem_request->seqno, | |
510 | (int) (jiffies - gem_request->emitted_jiffies)); | |
511 | } | |
512 | count++; | |
2017263e | 513 | } |
de227ef0 CW |
514 | mutex_unlock(&dev->struct_mutex); |
515 | ||
c2c347a9 | 516 | if (count == 0) |
267f0c90 | 517 | seq_puts(m, "No requests\n"); |
c2c347a9 | 518 | |
2017263e BG |
519 | return 0; |
520 | } | |
521 | ||
b2223497 CW |
522 | static void i915_ring_seqno_info(struct seq_file *m, |
523 | struct intel_ring_buffer *ring) | |
524 | { | |
525 | if (ring->get_seqno) { | |
43a7b924 | 526 | seq_printf(m, "Current sequence (%s): %u\n", |
b2eadbc8 | 527 | ring->name, ring->get_seqno(ring, false)); |
b2223497 CW |
528 | } |
529 | } | |
530 | ||
2017263e BG |
531 | static int i915_gem_seqno_info(struct seq_file *m, void *data) |
532 | { | |
533 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
534 | struct drm_device *dev = node->minor->dev; | |
535 | drm_i915_private_t *dev_priv = dev->dev_private; | |
a2c7f6fd | 536 | struct intel_ring_buffer *ring; |
1ec14ad3 | 537 | int ret, i; |
de227ef0 CW |
538 | |
539 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
540 | if (ret) | |
541 | return ret; | |
2017263e | 542 | |
a2c7f6fd CW |
543 | for_each_ring(ring, dev_priv, i) |
544 | i915_ring_seqno_info(m, ring); | |
de227ef0 CW |
545 | |
546 | mutex_unlock(&dev->struct_mutex); | |
547 | ||
2017263e BG |
548 | return 0; |
549 | } | |
550 | ||
551 | ||
552 | static int i915_interrupt_info(struct seq_file *m, void *data) | |
553 | { | |
554 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
555 | struct drm_device *dev = node->minor->dev; | |
556 | drm_i915_private_t *dev_priv = dev->dev_private; | |
a2c7f6fd | 557 | struct intel_ring_buffer *ring; |
9db4a9c7 | 558 | int ret, i, pipe; |
de227ef0 CW |
559 | |
560 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
561 | if (ret) | |
562 | return ret; | |
2017263e | 563 | |
7e231dbe JB |
564 | if (IS_VALLEYVIEW(dev)) { |
565 | seq_printf(m, "Display IER:\t%08x\n", | |
566 | I915_READ(VLV_IER)); | |
567 | seq_printf(m, "Display IIR:\t%08x\n", | |
568 | I915_READ(VLV_IIR)); | |
569 | seq_printf(m, "Display IIR_RW:\t%08x\n", | |
570 | I915_READ(VLV_IIR_RW)); | |
571 | seq_printf(m, "Display IMR:\t%08x\n", | |
572 | I915_READ(VLV_IMR)); | |
573 | for_each_pipe(pipe) | |
574 | seq_printf(m, "Pipe %c stat:\t%08x\n", | |
575 | pipe_name(pipe), | |
576 | I915_READ(PIPESTAT(pipe))); | |
577 | ||
578 | seq_printf(m, "Master IER:\t%08x\n", | |
579 | I915_READ(VLV_MASTER_IER)); | |
580 | ||
581 | seq_printf(m, "Render IER:\t%08x\n", | |
582 | I915_READ(GTIER)); | |
583 | seq_printf(m, "Render IIR:\t%08x\n", | |
584 | I915_READ(GTIIR)); | |
585 | seq_printf(m, "Render IMR:\t%08x\n", | |
586 | I915_READ(GTIMR)); | |
587 | ||
588 | seq_printf(m, "PM IER:\t\t%08x\n", | |
589 | I915_READ(GEN6_PMIER)); | |
590 | seq_printf(m, "PM IIR:\t\t%08x\n", | |
591 | I915_READ(GEN6_PMIIR)); | |
592 | seq_printf(m, "PM IMR:\t\t%08x\n", | |
593 | I915_READ(GEN6_PMIMR)); | |
594 | ||
595 | seq_printf(m, "Port hotplug:\t%08x\n", | |
596 | I915_READ(PORT_HOTPLUG_EN)); | |
597 | seq_printf(m, "DPFLIPSTAT:\t%08x\n", | |
598 | I915_READ(VLV_DPFLIPSTAT)); | |
599 | seq_printf(m, "DPINVGTT:\t%08x\n", | |
600 | I915_READ(DPINVGTT)); | |
601 | ||
602 | } else if (!HAS_PCH_SPLIT(dev)) { | |
5f6a1695 ZW |
603 | seq_printf(m, "Interrupt enable: %08x\n", |
604 | I915_READ(IER)); | |
605 | seq_printf(m, "Interrupt identity: %08x\n", | |
606 | I915_READ(IIR)); | |
607 | seq_printf(m, "Interrupt mask: %08x\n", | |
608 | I915_READ(IMR)); | |
9db4a9c7 JB |
609 | for_each_pipe(pipe) |
610 | seq_printf(m, "Pipe %c stat: %08x\n", | |
611 | pipe_name(pipe), | |
612 | I915_READ(PIPESTAT(pipe))); | |
5f6a1695 ZW |
613 | } else { |
614 | seq_printf(m, "North Display Interrupt enable: %08x\n", | |
615 | I915_READ(DEIER)); | |
616 | seq_printf(m, "North Display Interrupt identity: %08x\n", | |
617 | I915_READ(DEIIR)); | |
618 | seq_printf(m, "North Display Interrupt mask: %08x\n", | |
619 | I915_READ(DEIMR)); | |
620 | seq_printf(m, "South Display Interrupt enable: %08x\n", | |
621 | I915_READ(SDEIER)); | |
622 | seq_printf(m, "South Display Interrupt identity: %08x\n", | |
623 | I915_READ(SDEIIR)); | |
624 | seq_printf(m, "South Display Interrupt mask: %08x\n", | |
625 | I915_READ(SDEIMR)); | |
626 | seq_printf(m, "Graphics Interrupt enable: %08x\n", | |
627 | I915_READ(GTIER)); | |
628 | seq_printf(m, "Graphics Interrupt identity: %08x\n", | |
629 | I915_READ(GTIIR)); | |
630 | seq_printf(m, "Graphics Interrupt mask: %08x\n", | |
631 | I915_READ(GTIMR)); | |
632 | } | |
2017263e BG |
633 | seq_printf(m, "Interrupts received: %d\n", |
634 | atomic_read(&dev_priv->irq_received)); | |
a2c7f6fd | 635 | for_each_ring(ring, dev_priv, i) { |
da64c6fc | 636 | if (IS_GEN6(dev) || IS_GEN7(dev)) { |
a2c7f6fd CW |
637 | seq_printf(m, |
638 | "Graphics Interrupt mask (%s): %08x\n", | |
639 | ring->name, I915_READ_IMR(ring)); | |
9862e600 | 640 | } |
a2c7f6fd | 641 | i915_ring_seqno_info(m, ring); |
9862e600 | 642 | } |
de227ef0 CW |
643 | mutex_unlock(&dev->struct_mutex); |
644 | ||
2017263e BG |
645 | return 0; |
646 | } | |
647 | ||
a6172a80 CW |
648 | static int i915_gem_fence_regs_info(struct seq_file *m, void *data) |
649 | { | |
650 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
651 | struct drm_device *dev = node->minor->dev; | |
652 | drm_i915_private_t *dev_priv = dev->dev_private; | |
de227ef0 CW |
653 | int i, ret; |
654 | ||
655 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
656 | if (ret) | |
657 | return ret; | |
a6172a80 CW |
658 | |
659 | seq_printf(m, "Reserved fences = %d\n", dev_priv->fence_reg_start); | |
660 | seq_printf(m, "Total fences = %d\n", dev_priv->num_fence_regs); | |
661 | for (i = 0; i < dev_priv->num_fence_regs; i++) { | |
05394f39 | 662 | struct drm_i915_gem_object *obj = dev_priv->fence_regs[i].obj; |
a6172a80 | 663 | |
6c085a72 CW |
664 | seq_printf(m, "Fence %d, pin count = %d, object = ", |
665 | i, dev_priv->fence_regs[i].pin_count); | |
c2c347a9 | 666 | if (obj == NULL) |
267f0c90 | 667 | seq_puts(m, "unused"); |
c2c347a9 | 668 | else |
05394f39 | 669 | describe_obj(m, obj); |
267f0c90 | 670 | seq_putc(m, '\n'); |
a6172a80 CW |
671 | } |
672 | ||
05394f39 | 673 | mutex_unlock(&dev->struct_mutex); |
a6172a80 CW |
674 | return 0; |
675 | } | |
676 | ||
2017263e BG |
677 | static int i915_hws_info(struct seq_file *m, void *data) |
678 | { | |
679 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
680 | struct drm_device *dev = node->minor->dev; | |
681 | drm_i915_private_t *dev_priv = dev->dev_private; | |
4066c0ae | 682 | struct intel_ring_buffer *ring; |
1a240d4d | 683 | const u32 *hws; |
4066c0ae CW |
684 | int i; |
685 | ||
1ec14ad3 | 686 | ring = &dev_priv->ring[(uintptr_t)node->info_ent->data]; |
1a240d4d | 687 | hws = ring->status_page.page_addr; |
2017263e BG |
688 | if (hws == NULL) |
689 | return 0; | |
690 | ||
691 | for (i = 0; i < 4096 / sizeof(u32) / 4; i += 4) { | |
692 | seq_printf(m, "0x%08x: 0x%08x 0x%08x 0x%08x 0x%08x\n", | |
693 | i * 4, | |
694 | hws[i], hws[i + 1], hws[i + 2], hws[i + 3]); | |
695 | } | |
696 | return 0; | |
697 | } | |
698 | ||
d5442303 DV |
699 | static ssize_t |
700 | i915_error_state_write(struct file *filp, | |
701 | const char __user *ubuf, | |
702 | size_t cnt, | |
703 | loff_t *ppos) | |
704 | { | |
edc3d884 | 705 | struct i915_error_state_file_priv *error_priv = filp->private_data; |
d5442303 | 706 | struct drm_device *dev = error_priv->dev; |
22bcfc6a | 707 | int ret; |
d5442303 DV |
708 | |
709 | DRM_DEBUG_DRIVER("Resetting error state\n"); | |
710 | ||
22bcfc6a DV |
711 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
712 | if (ret) | |
713 | return ret; | |
714 | ||
d5442303 DV |
715 | i915_destroy_error_state(dev); |
716 | mutex_unlock(&dev->struct_mutex); | |
717 | ||
718 | return cnt; | |
719 | } | |
720 | ||
721 | static int i915_error_state_open(struct inode *inode, struct file *file) | |
722 | { | |
723 | struct drm_device *dev = inode->i_private; | |
d5442303 | 724 | struct i915_error_state_file_priv *error_priv; |
d5442303 DV |
725 | |
726 | error_priv = kzalloc(sizeof(*error_priv), GFP_KERNEL); | |
727 | if (!error_priv) | |
728 | return -ENOMEM; | |
729 | ||
730 | error_priv->dev = dev; | |
731 | ||
95d5bfb3 | 732 | i915_error_state_get(dev, error_priv); |
d5442303 | 733 | |
edc3d884 MK |
734 | file->private_data = error_priv; |
735 | ||
736 | return 0; | |
d5442303 DV |
737 | } |
738 | ||
739 | static int i915_error_state_release(struct inode *inode, struct file *file) | |
740 | { | |
edc3d884 | 741 | struct i915_error_state_file_priv *error_priv = file->private_data; |
d5442303 | 742 | |
95d5bfb3 | 743 | i915_error_state_put(error_priv); |
d5442303 DV |
744 | kfree(error_priv); |
745 | ||
edc3d884 MK |
746 | return 0; |
747 | } | |
748 | ||
4dc955f7 MK |
749 | static ssize_t i915_error_state_read(struct file *file, char __user *userbuf, |
750 | size_t count, loff_t *pos) | |
751 | { | |
752 | struct i915_error_state_file_priv *error_priv = file->private_data; | |
753 | struct drm_i915_error_state_buf error_str; | |
754 | loff_t tmp_pos = 0; | |
755 | ssize_t ret_count = 0; | |
756 | int ret; | |
757 | ||
758 | ret = i915_error_state_buf_init(&error_str, count, *pos); | |
759 | if (ret) | |
760 | return ret; | |
edc3d884 | 761 | |
fc16b48b | 762 | ret = i915_error_state_to_str(&error_str, error_priv); |
edc3d884 MK |
763 | if (ret) |
764 | goto out; | |
765 | ||
edc3d884 MK |
766 | ret_count = simple_read_from_buffer(userbuf, count, &tmp_pos, |
767 | error_str.buf, | |
768 | error_str.bytes); | |
769 | ||
770 | if (ret_count < 0) | |
771 | ret = ret_count; | |
772 | else | |
773 | *pos = error_str.start + ret_count; | |
774 | out: | |
4dc955f7 | 775 | i915_error_state_buf_release(&error_str); |
edc3d884 | 776 | return ret ?: ret_count; |
d5442303 DV |
777 | } |
778 | ||
779 | static const struct file_operations i915_error_state_fops = { | |
780 | .owner = THIS_MODULE, | |
781 | .open = i915_error_state_open, | |
edc3d884 | 782 | .read = i915_error_state_read, |
d5442303 DV |
783 | .write = i915_error_state_write, |
784 | .llseek = default_llseek, | |
785 | .release = i915_error_state_release, | |
786 | }; | |
787 | ||
647416f9 KC |
788 | static int |
789 | i915_next_seqno_get(void *data, u64 *val) | |
40633219 | 790 | { |
647416f9 | 791 | struct drm_device *dev = data; |
40633219 | 792 | drm_i915_private_t *dev_priv = dev->dev_private; |
40633219 MK |
793 | int ret; |
794 | ||
795 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
796 | if (ret) | |
797 | return ret; | |
798 | ||
647416f9 | 799 | *val = dev_priv->next_seqno; |
40633219 MK |
800 | mutex_unlock(&dev->struct_mutex); |
801 | ||
647416f9 | 802 | return 0; |
40633219 MK |
803 | } |
804 | ||
647416f9 KC |
805 | static int |
806 | i915_next_seqno_set(void *data, u64 val) | |
807 | { | |
808 | struct drm_device *dev = data; | |
40633219 MK |
809 | int ret; |
810 | ||
40633219 MK |
811 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
812 | if (ret) | |
813 | return ret; | |
814 | ||
e94fbaa8 | 815 | ret = i915_gem_set_seqno(dev, val); |
40633219 MK |
816 | mutex_unlock(&dev->struct_mutex); |
817 | ||
647416f9 | 818 | return ret; |
40633219 MK |
819 | } |
820 | ||
647416f9 KC |
821 | DEFINE_SIMPLE_ATTRIBUTE(i915_next_seqno_fops, |
822 | i915_next_seqno_get, i915_next_seqno_set, | |
3a3b4f98 | 823 | "0x%llx\n"); |
40633219 | 824 | |
f97108d1 JB |
825 | static int i915_rstdby_delays(struct seq_file *m, void *unused) |
826 | { | |
827 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
828 | struct drm_device *dev = node->minor->dev; | |
829 | drm_i915_private_t *dev_priv = dev->dev_private; | |
616fdb5a BW |
830 | u16 crstanddelay; |
831 | int ret; | |
832 | ||
833 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
834 | if (ret) | |
835 | return ret; | |
836 | ||
837 | crstanddelay = I915_READ16(CRSTANDVID); | |
838 | ||
839 | mutex_unlock(&dev->struct_mutex); | |
f97108d1 JB |
840 | |
841 | seq_printf(m, "w/ctx: %d, w/o ctx: %d\n", (crstanddelay >> 8) & 0x3f, (crstanddelay & 0x3f)); | |
842 | ||
843 | return 0; | |
844 | } | |
845 | ||
846 | static int i915_cur_delayinfo(struct seq_file *m, void *unused) | |
847 | { | |
848 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
849 | struct drm_device *dev = node->minor->dev; | |
850 | drm_i915_private_t *dev_priv = dev->dev_private; | |
d1ebd816 | 851 | int ret; |
3b8d8d91 JB |
852 | |
853 | if (IS_GEN5(dev)) { | |
854 | u16 rgvswctl = I915_READ16(MEMSWCTL); | |
855 | u16 rgvstat = I915_READ16(MEMSTAT_ILK); | |
856 | ||
857 | seq_printf(m, "Requested P-state: %d\n", (rgvswctl >> 8) & 0xf); | |
858 | seq_printf(m, "Requested VID: %d\n", rgvswctl & 0x3f); | |
859 | seq_printf(m, "Current VID: %d\n", (rgvstat & MEMSTAT_VID_MASK) >> | |
860 | MEMSTAT_VID_SHIFT); | |
861 | seq_printf(m, "Current P-state: %d\n", | |
862 | (rgvstat & MEMSTAT_PSTATE_MASK) >> MEMSTAT_PSTATE_SHIFT); | |
0a073b84 | 863 | } else if ((IS_GEN6(dev) || IS_GEN7(dev)) && !IS_VALLEYVIEW(dev)) { |
3b8d8d91 JB |
864 | u32 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS); |
865 | u32 rp_state_limits = I915_READ(GEN6_RP_STATE_LIMITS); | |
866 | u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP); | |
8e8c06cd | 867 | u32 rpstat, cagf, reqf; |
ccab5c82 JB |
868 | u32 rpupei, rpcurup, rpprevup; |
869 | u32 rpdownei, rpcurdown, rpprevdown; | |
3b8d8d91 JB |
870 | int max_freq; |
871 | ||
872 | /* RPSTAT1 is in the GT power well */ | |
d1ebd816 BW |
873 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
874 | if (ret) | |
875 | return ret; | |
876 | ||
fcca7926 | 877 | gen6_gt_force_wake_get(dev_priv); |
3b8d8d91 | 878 | |
8e8c06cd CW |
879 | reqf = I915_READ(GEN6_RPNSWREQ); |
880 | reqf &= ~GEN6_TURBO_DISABLE; | |
881 | if (IS_HASWELL(dev)) | |
882 | reqf >>= 24; | |
883 | else | |
884 | reqf >>= 25; | |
885 | reqf *= GT_FREQUENCY_MULTIPLIER; | |
886 | ||
ccab5c82 JB |
887 | rpstat = I915_READ(GEN6_RPSTAT1); |
888 | rpupei = I915_READ(GEN6_RP_CUR_UP_EI); | |
889 | rpcurup = I915_READ(GEN6_RP_CUR_UP); | |
890 | rpprevup = I915_READ(GEN6_RP_PREV_UP); | |
891 | rpdownei = I915_READ(GEN6_RP_CUR_DOWN_EI); | |
892 | rpcurdown = I915_READ(GEN6_RP_CUR_DOWN); | |
893 | rpprevdown = I915_READ(GEN6_RP_PREV_DOWN); | |
f82855d3 BW |
894 | if (IS_HASWELL(dev)) |
895 | cagf = (rpstat & HSW_CAGF_MASK) >> HSW_CAGF_SHIFT; | |
896 | else | |
897 | cagf = (rpstat & GEN6_CAGF_MASK) >> GEN6_CAGF_SHIFT; | |
898 | cagf *= GT_FREQUENCY_MULTIPLIER; | |
ccab5c82 | 899 | |
d1ebd816 BW |
900 | gen6_gt_force_wake_put(dev_priv); |
901 | mutex_unlock(&dev->struct_mutex); | |
902 | ||
3b8d8d91 | 903 | seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status); |
ccab5c82 | 904 | seq_printf(m, "RPSTAT1: 0x%08x\n", rpstat); |
3b8d8d91 JB |
905 | seq_printf(m, "Render p-state ratio: %d\n", |
906 | (gt_perf_status & 0xff00) >> 8); | |
907 | seq_printf(m, "Render p-state VID: %d\n", | |
908 | gt_perf_status & 0xff); | |
909 | seq_printf(m, "Render p-state limit: %d\n", | |
910 | rp_state_limits & 0xff); | |
8e8c06cd | 911 | seq_printf(m, "RPNSWREQ: %dMHz\n", reqf); |
f82855d3 | 912 | seq_printf(m, "CAGF: %dMHz\n", cagf); |
ccab5c82 JB |
913 | seq_printf(m, "RP CUR UP EI: %dus\n", rpupei & |
914 | GEN6_CURICONT_MASK); | |
915 | seq_printf(m, "RP CUR UP: %dus\n", rpcurup & | |
916 | GEN6_CURBSYTAVG_MASK); | |
917 | seq_printf(m, "RP PREV UP: %dus\n", rpprevup & | |
918 | GEN6_CURBSYTAVG_MASK); | |
919 | seq_printf(m, "RP CUR DOWN EI: %dus\n", rpdownei & | |
920 | GEN6_CURIAVG_MASK); | |
921 | seq_printf(m, "RP CUR DOWN: %dus\n", rpcurdown & | |
922 | GEN6_CURBSYTAVG_MASK); | |
923 | seq_printf(m, "RP PREV DOWN: %dus\n", rpprevdown & | |
924 | GEN6_CURBSYTAVG_MASK); | |
3b8d8d91 JB |
925 | |
926 | max_freq = (rp_state_cap & 0xff0000) >> 16; | |
927 | seq_printf(m, "Lowest (RPN) frequency: %dMHz\n", | |
c8735b0c | 928 | max_freq * GT_FREQUENCY_MULTIPLIER); |
3b8d8d91 JB |
929 | |
930 | max_freq = (rp_state_cap & 0xff00) >> 8; | |
931 | seq_printf(m, "Nominal (RP1) frequency: %dMHz\n", | |
c8735b0c | 932 | max_freq * GT_FREQUENCY_MULTIPLIER); |
3b8d8d91 JB |
933 | |
934 | max_freq = rp_state_cap & 0xff; | |
935 | seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n", | |
c8735b0c | 936 | max_freq * GT_FREQUENCY_MULTIPLIER); |
31c77388 BW |
937 | |
938 | seq_printf(m, "Max overclocked frequency: %dMHz\n", | |
939 | dev_priv->rps.hw_max * GT_FREQUENCY_MULTIPLIER); | |
0a073b84 JB |
940 | } else if (IS_VALLEYVIEW(dev)) { |
941 | u32 freq_sts, val; | |
942 | ||
259bd5d4 | 943 | mutex_lock(&dev_priv->rps.hw_lock); |
64936258 | 944 | freq_sts = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS); |
0a073b84 JB |
945 | seq_printf(m, "PUNIT_REG_GPU_FREQ_STS: 0x%08x\n", freq_sts); |
946 | seq_printf(m, "DDR freq: %d MHz\n", dev_priv->mem_freq); | |
947 | ||
64936258 | 948 | val = vlv_punit_read(dev_priv, PUNIT_FUSE_BUS1); |
0a073b84 JB |
949 | seq_printf(m, "max GPU freq: %d MHz\n", |
950 | vlv_gpu_freq(dev_priv->mem_freq, val)); | |
951 | ||
64936258 | 952 | val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_LFM); |
0a073b84 JB |
953 | seq_printf(m, "min GPU freq: %d MHz\n", |
954 | vlv_gpu_freq(dev_priv->mem_freq, val)); | |
955 | ||
956 | seq_printf(m, "current GPU freq: %d MHz\n", | |
957 | vlv_gpu_freq(dev_priv->mem_freq, | |
958 | (freq_sts >> 8) & 0xff)); | |
259bd5d4 | 959 | mutex_unlock(&dev_priv->rps.hw_lock); |
3b8d8d91 | 960 | } else { |
267f0c90 | 961 | seq_puts(m, "no P-state info available\n"); |
3b8d8d91 | 962 | } |
f97108d1 JB |
963 | |
964 | return 0; | |
965 | } | |
966 | ||
967 | static int i915_delayfreq_table(struct seq_file *m, void *unused) | |
968 | { | |
969 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
970 | struct drm_device *dev = node->minor->dev; | |
971 | drm_i915_private_t *dev_priv = dev->dev_private; | |
972 | u32 delayfreq; | |
616fdb5a BW |
973 | int ret, i; |
974 | ||
975 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
976 | if (ret) | |
977 | return ret; | |
f97108d1 JB |
978 | |
979 | for (i = 0; i < 16; i++) { | |
980 | delayfreq = I915_READ(PXVFREQ_BASE + i * 4); | |
7648fa99 JB |
981 | seq_printf(m, "P%02dVIDFREQ: 0x%08x (VID: %d)\n", i, delayfreq, |
982 | (delayfreq & PXVFREQ_PX_MASK) >> PXVFREQ_PX_SHIFT); | |
f97108d1 JB |
983 | } |
984 | ||
616fdb5a BW |
985 | mutex_unlock(&dev->struct_mutex); |
986 | ||
f97108d1 JB |
987 | return 0; |
988 | } | |
989 | ||
990 | static inline int MAP_TO_MV(int map) | |
991 | { | |
992 | return 1250 - (map * 25); | |
993 | } | |
994 | ||
995 | static int i915_inttoext_table(struct seq_file *m, void *unused) | |
996 | { | |
997 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
998 | struct drm_device *dev = node->minor->dev; | |
999 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1000 | u32 inttoext; | |
616fdb5a BW |
1001 | int ret, i; |
1002 | ||
1003 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
1004 | if (ret) | |
1005 | return ret; | |
f97108d1 JB |
1006 | |
1007 | for (i = 1; i <= 32; i++) { | |
1008 | inttoext = I915_READ(INTTOEXT_BASE_ILK + i * 4); | |
1009 | seq_printf(m, "INTTOEXT%02d: 0x%08x\n", i, inttoext); | |
1010 | } | |
1011 | ||
616fdb5a BW |
1012 | mutex_unlock(&dev->struct_mutex); |
1013 | ||
f97108d1 JB |
1014 | return 0; |
1015 | } | |
1016 | ||
4d85529d | 1017 | static int ironlake_drpc_info(struct seq_file *m) |
f97108d1 JB |
1018 | { |
1019 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1020 | struct drm_device *dev = node->minor->dev; | |
1021 | drm_i915_private_t *dev_priv = dev->dev_private; | |
616fdb5a BW |
1022 | u32 rgvmodectl, rstdbyctl; |
1023 | u16 crstandvid; | |
1024 | int ret; | |
1025 | ||
1026 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
1027 | if (ret) | |
1028 | return ret; | |
1029 | ||
1030 | rgvmodectl = I915_READ(MEMMODECTL); | |
1031 | rstdbyctl = I915_READ(RSTDBYCTL); | |
1032 | crstandvid = I915_READ16(CRSTANDVID); | |
1033 | ||
1034 | mutex_unlock(&dev->struct_mutex); | |
f97108d1 JB |
1035 | |
1036 | seq_printf(m, "HD boost: %s\n", (rgvmodectl & MEMMODE_BOOST_EN) ? | |
1037 | "yes" : "no"); | |
1038 | seq_printf(m, "Boost freq: %d\n", | |
1039 | (rgvmodectl & MEMMODE_BOOST_FREQ_MASK) >> | |
1040 | MEMMODE_BOOST_FREQ_SHIFT); | |
1041 | seq_printf(m, "HW control enabled: %s\n", | |
1042 | rgvmodectl & MEMMODE_HWIDLE_EN ? "yes" : "no"); | |
1043 | seq_printf(m, "SW control enabled: %s\n", | |
1044 | rgvmodectl & MEMMODE_SWMODE_EN ? "yes" : "no"); | |
1045 | seq_printf(m, "Gated voltage change: %s\n", | |
1046 | rgvmodectl & MEMMODE_RCLK_GATE ? "yes" : "no"); | |
1047 | seq_printf(m, "Starting frequency: P%d\n", | |
1048 | (rgvmodectl & MEMMODE_FSTART_MASK) >> MEMMODE_FSTART_SHIFT); | |
7648fa99 | 1049 | seq_printf(m, "Max P-state: P%d\n", |
f97108d1 | 1050 | (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT); |
7648fa99 JB |
1051 | seq_printf(m, "Min P-state: P%d\n", (rgvmodectl & MEMMODE_FMIN_MASK)); |
1052 | seq_printf(m, "RS1 VID: %d\n", (crstandvid & 0x3f)); | |
1053 | seq_printf(m, "RS2 VID: %d\n", ((crstandvid >> 8) & 0x3f)); | |
1054 | seq_printf(m, "Render standby enabled: %s\n", | |
1055 | (rstdbyctl & RCX_SW_EXIT) ? "no" : "yes"); | |
267f0c90 | 1056 | seq_puts(m, "Current RS state: "); |
88271da3 JB |
1057 | switch (rstdbyctl & RSX_STATUS_MASK) { |
1058 | case RSX_STATUS_ON: | |
267f0c90 | 1059 | seq_puts(m, "on\n"); |
88271da3 JB |
1060 | break; |
1061 | case RSX_STATUS_RC1: | |
267f0c90 | 1062 | seq_puts(m, "RC1\n"); |
88271da3 JB |
1063 | break; |
1064 | case RSX_STATUS_RC1E: | |
267f0c90 | 1065 | seq_puts(m, "RC1E\n"); |
88271da3 JB |
1066 | break; |
1067 | case RSX_STATUS_RS1: | |
267f0c90 | 1068 | seq_puts(m, "RS1\n"); |
88271da3 JB |
1069 | break; |
1070 | case RSX_STATUS_RS2: | |
267f0c90 | 1071 | seq_puts(m, "RS2 (RC6)\n"); |
88271da3 JB |
1072 | break; |
1073 | case RSX_STATUS_RS3: | |
267f0c90 | 1074 | seq_puts(m, "RC3 (RC6+)\n"); |
88271da3 JB |
1075 | break; |
1076 | default: | |
267f0c90 | 1077 | seq_puts(m, "unknown\n"); |
88271da3 JB |
1078 | break; |
1079 | } | |
f97108d1 JB |
1080 | |
1081 | return 0; | |
1082 | } | |
1083 | ||
4d85529d BW |
1084 | static int gen6_drpc_info(struct seq_file *m) |
1085 | { | |
1086 | ||
1087 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1088 | struct drm_device *dev = node->minor->dev; | |
1089 | struct drm_i915_private *dev_priv = dev->dev_private; | |
ecd8faea | 1090 | u32 rpmodectl1, gt_core_status, rcctl1, rc6vids = 0; |
93b525dc | 1091 | unsigned forcewake_count; |
aee56cff | 1092 | int count = 0, ret; |
4d85529d BW |
1093 | |
1094 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
1095 | if (ret) | |
1096 | return ret; | |
1097 | ||
907b28c5 CW |
1098 | spin_lock_irq(&dev_priv->uncore.lock); |
1099 | forcewake_count = dev_priv->uncore.forcewake_count; | |
1100 | spin_unlock_irq(&dev_priv->uncore.lock); | |
93b525dc DV |
1101 | |
1102 | if (forcewake_count) { | |
267f0c90 DL |
1103 | seq_puts(m, "RC information inaccurate because somebody " |
1104 | "holds a forcewake reference \n"); | |
4d85529d BW |
1105 | } else { |
1106 | /* NB: we cannot use forcewake, else we read the wrong values */ | |
1107 | while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1)) | |
1108 | udelay(10); | |
1109 | seq_printf(m, "RC information accurate: %s\n", yesno(count < 51)); | |
1110 | } | |
1111 | ||
1112 | gt_core_status = readl(dev_priv->regs + GEN6_GT_CORE_STATUS); | |
ed71f1b4 | 1113 | trace_i915_reg_rw(false, GEN6_GT_CORE_STATUS, gt_core_status, 4, true); |
4d85529d BW |
1114 | |
1115 | rpmodectl1 = I915_READ(GEN6_RP_CONTROL); | |
1116 | rcctl1 = I915_READ(GEN6_RC_CONTROL); | |
1117 | mutex_unlock(&dev->struct_mutex); | |
44cbd338 BW |
1118 | mutex_lock(&dev_priv->rps.hw_lock); |
1119 | sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids); | |
1120 | mutex_unlock(&dev_priv->rps.hw_lock); | |
4d85529d BW |
1121 | |
1122 | seq_printf(m, "Video Turbo Mode: %s\n", | |
1123 | yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO)); | |
1124 | seq_printf(m, "HW control enabled: %s\n", | |
1125 | yesno(rpmodectl1 & GEN6_RP_ENABLE)); | |
1126 | seq_printf(m, "SW control enabled: %s\n", | |
1127 | yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) == | |
1128 | GEN6_RP_MEDIA_SW_MODE)); | |
fff24e21 | 1129 | seq_printf(m, "RC1e Enabled: %s\n", |
4d85529d BW |
1130 | yesno(rcctl1 & GEN6_RC_CTL_RC1e_ENABLE)); |
1131 | seq_printf(m, "RC6 Enabled: %s\n", | |
1132 | yesno(rcctl1 & GEN6_RC_CTL_RC6_ENABLE)); | |
1133 | seq_printf(m, "Deep RC6 Enabled: %s\n", | |
1134 | yesno(rcctl1 & GEN6_RC_CTL_RC6p_ENABLE)); | |
1135 | seq_printf(m, "Deepest RC6 Enabled: %s\n", | |
1136 | yesno(rcctl1 & GEN6_RC_CTL_RC6pp_ENABLE)); | |
267f0c90 | 1137 | seq_puts(m, "Current RC state: "); |
4d85529d BW |
1138 | switch (gt_core_status & GEN6_RCn_MASK) { |
1139 | case GEN6_RC0: | |
1140 | if (gt_core_status & GEN6_CORE_CPD_STATE_MASK) | |
267f0c90 | 1141 | seq_puts(m, "Core Power Down\n"); |
4d85529d | 1142 | else |
267f0c90 | 1143 | seq_puts(m, "on\n"); |
4d85529d BW |
1144 | break; |
1145 | case GEN6_RC3: | |
267f0c90 | 1146 | seq_puts(m, "RC3\n"); |
4d85529d BW |
1147 | break; |
1148 | case GEN6_RC6: | |
267f0c90 | 1149 | seq_puts(m, "RC6\n"); |
4d85529d BW |
1150 | break; |
1151 | case GEN6_RC7: | |
267f0c90 | 1152 | seq_puts(m, "RC7\n"); |
4d85529d BW |
1153 | break; |
1154 | default: | |
267f0c90 | 1155 | seq_puts(m, "Unknown\n"); |
4d85529d BW |
1156 | break; |
1157 | } | |
1158 | ||
1159 | seq_printf(m, "Core Power Down: %s\n", | |
1160 | yesno(gt_core_status & GEN6_CORE_CPD_STATE_MASK)); | |
cce66a28 BW |
1161 | |
1162 | /* Not exactly sure what this is */ | |
1163 | seq_printf(m, "RC6 \"Locked to RPn\" residency since boot: %u\n", | |
1164 | I915_READ(GEN6_GT_GFX_RC6_LOCKED)); | |
1165 | seq_printf(m, "RC6 residency since boot: %u\n", | |
1166 | I915_READ(GEN6_GT_GFX_RC6)); | |
1167 | seq_printf(m, "RC6+ residency since boot: %u\n", | |
1168 | I915_READ(GEN6_GT_GFX_RC6p)); | |
1169 | seq_printf(m, "RC6++ residency since boot: %u\n", | |
1170 | I915_READ(GEN6_GT_GFX_RC6pp)); | |
1171 | ||
ecd8faea BW |
1172 | seq_printf(m, "RC6 voltage: %dmV\n", |
1173 | GEN6_DECODE_RC6_VID(((rc6vids >> 0) & 0xff))); | |
1174 | seq_printf(m, "RC6+ voltage: %dmV\n", | |
1175 | GEN6_DECODE_RC6_VID(((rc6vids >> 8) & 0xff))); | |
1176 | seq_printf(m, "RC6++ voltage: %dmV\n", | |
1177 | GEN6_DECODE_RC6_VID(((rc6vids >> 16) & 0xff))); | |
4d85529d BW |
1178 | return 0; |
1179 | } | |
1180 | ||
1181 | static int i915_drpc_info(struct seq_file *m, void *unused) | |
1182 | { | |
1183 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1184 | struct drm_device *dev = node->minor->dev; | |
1185 | ||
1186 | if (IS_GEN6(dev) || IS_GEN7(dev)) | |
1187 | return gen6_drpc_info(m); | |
1188 | else | |
1189 | return ironlake_drpc_info(m); | |
1190 | } | |
1191 | ||
b5e50c3f JB |
1192 | static int i915_fbc_status(struct seq_file *m, void *unused) |
1193 | { | |
1194 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1195 | struct drm_device *dev = node->minor->dev; | |
b5e50c3f | 1196 | drm_i915_private_t *dev_priv = dev->dev_private; |
b5e50c3f | 1197 | |
ee5382ae | 1198 | if (!I915_HAS_FBC(dev)) { |
267f0c90 | 1199 | seq_puts(m, "FBC unsupported on this chipset\n"); |
b5e50c3f JB |
1200 | return 0; |
1201 | } | |
1202 | ||
ee5382ae | 1203 | if (intel_fbc_enabled(dev)) { |
267f0c90 | 1204 | seq_puts(m, "FBC enabled\n"); |
b5e50c3f | 1205 | } else { |
267f0c90 | 1206 | seq_puts(m, "FBC disabled: "); |
5c3fe8b0 | 1207 | switch (dev_priv->fbc.no_fbc_reason) { |
29ebf90f CW |
1208 | case FBC_OK: |
1209 | seq_puts(m, "FBC actived, but currently disabled in hardware"); | |
1210 | break; | |
1211 | case FBC_UNSUPPORTED: | |
1212 | seq_puts(m, "unsupported by this chipset"); | |
1213 | break; | |
bed4a673 | 1214 | case FBC_NO_OUTPUT: |
267f0c90 | 1215 | seq_puts(m, "no outputs"); |
bed4a673 | 1216 | break; |
b5e50c3f | 1217 | case FBC_STOLEN_TOO_SMALL: |
267f0c90 | 1218 | seq_puts(m, "not enough stolen memory"); |
b5e50c3f JB |
1219 | break; |
1220 | case FBC_UNSUPPORTED_MODE: | |
267f0c90 | 1221 | seq_puts(m, "mode not supported"); |
b5e50c3f JB |
1222 | break; |
1223 | case FBC_MODE_TOO_LARGE: | |
267f0c90 | 1224 | seq_puts(m, "mode too large"); |
b5e50c3f JB |
1225 | break; |
1226 | case FBC_BAD_PLANE: | |
267f0c90 | 1227 | seq_puts(m, "FBC unsupported on plane"); |
b5e50c3f JB |
1228 | break; |
1229 | case FBC_NOT_TILED: | |
267f0c90 | 1230 | seq_puts(m, "scanout buffer not tiled"); |
b5e50c3f | 1231 | break; |
9c928d16 | 1232 | case FBC_MULTIPLE_PIPES: |
267f0c90 | 1233 | seq_puts(m, "multiple pipes are enabled"); |
9c928d16 | 1234 | break; |
c1a9f047 | 1235 | case FBC_MODULE_PARAM: |
267f0c90 | 1236 | seq_puts(m, "disabled per module param (default off)"); |
c1a9f047 | 1237 | break; |
8a5729a3 | 1238 | case FBC_CHIP_DEFAULT: |
267f0c90 | 1239 | seq_puts(m, "disabled per chip default"); |
8a5729a3 | 1240 | break; |
b5e50c3f | 1241 | default: |
267f0c90 | 1242 | seq_puts(m, "unknown reason"); |
b5e50c3f | 1243 | } |
267f0c90 | 1244 | seq_putc(m, '\n'); |
b5e50c3f JB |
1245 | } |
1246 | return 0; | |
1247 | } | |
1248 | ||
92d44621 PZ |
1249 | static int i915_ips_status(struct seq_file *m, void *unused) |
1250 | { | |
1251 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1252 | struct drm_device *dev = node->minor->dev; | |
1253 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1254 | ||
f5adf94e | 1255 | if (!HAS_IPS(dev)) { |
92d44621 PZ |
1256 | seq_puts(m, "not supported\n"); |
1257 | return 0; | |
1258 | } | |
1259 | ||
1260 | if (I915_READ(IPS_CTL) & IPS_ENABLE) | |
1261 | seq_puts(m, "enabled\n"); | |
1262 | else | |
1263 | seq_puts(m, "disabled\n"); | |
1264 | ||
1265 | return 0; | |
1266 | } | |
1267 | ||
4a9bef37 JB |
1268 | static int i915_sr_status(struct seq_file *m, void *unused) |
1269 | { | |
1270 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1271 | struct drm_device *dev = node->minor->dev; | |
1272 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1273 | bool sr_enabled = false; | |
1274 | ||
1398261a | 1275 | if (HAS_PCH_SPLIT(dev)) |
5ba2aaaa | 1276 | sr_enabled = I915_READ(WM1_LP_ILK) & WM1_LP_SR_EN; |
a6c45cf0 | 1277 | else if (IS_CRESTLINE(dev) || IS_I945G(dev) || IS_I945GM(dev)) |
4a9bef37 JB |
1278 | sr_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN; |
1279 | else if (IS_I915GM(dev)) | |
1280 | sr_enabled = I915_READ(INSTPM) & INSTPM_SELF_EN; | |
1281 | else if (IS_PINEVIEW(dev)) | |
1282 | sr_enabled = I915_READ(DSPFW3) & PINEVIEW_SELF_REFRESH_EN; | |
1283 | ||
5ba2aaaa CW |
1284 | seq_printf(m, "self-refresh: %s\n", |
1285 | sr_enabled ? "enabled" : "disabled"); | |
4a9bef37 JB |
1286 | |
1287 | return 0; | |
1288 | } | |
1289 | ||
7648fa99 JB |
1290 | static int i915_emon_status(struct seq_file *m, void *unused) |
1291 | { | |
1292 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1293 | struct drm_device *dev = node->minor->dev; | |
1294 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1295 | unsigned long temp, chipset, gfx; | |
de227ef0 CW |
1296 | int ret; |
1297 | ||
582be6b4 CW |
1298 | if (!IS_GEN5(dev)) |
1299 | return -ENODEV; | |
1300 | ||
de227ef0 CW |
1301 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
1302 | if (ret) | |
1303 | return ret; | |
7648fa99 JB |
1304 | |
1305 | temp = i915_mch_val(dev_priv); | |
1306 | chipset = i915_chipset_val(dev_priv); | |
1307 | gfx = i915_gfx_val(dev_priv); | |
de227ef0 | 1308 | mutex_unlock(&dev->struct_mutex); |
7648fa99 JB |
1309 | |
1310 | seq_printf(m, "GMCH temp: %ld\n", temp); | |
1311 | seq_printf(m, "Chipset power: %ld\n", chipset); | |
1312 | seq_printf(m, "GFX power: %ld\n", gfx); | |
1313 | seq_printf(m, "Total power: %ld\n", chipset + gfx); | |
1314 | ||
1315 | return 0; | |
1316 | } | |
1317 | ||
23b2f8bb JB |
1318 | static int i915_ring_freq_table(struct seq_file *m, void *unused) |
1319 | { | |
1320 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1321 | struct drm_device *dev = node->minor->dev; | |
1322 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1323 | int ret; | |
1324 | int gpu_freq, ia_freq; | |
1325 | ||
1c70c0ce | 1326 | if (!(IS_GEN6(dev) || IS_GEN7(dev))) { |
267f0c90 | 1327 | seq_puts(m, "unsupported on this chipset\n"); |
23b2f8bb JB |
1328 | return 0; |
1329 | } | |
1330 | ||
4fc688ce | 1331 | ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock); |
23b2f8bb JB |
1332 | if (ret) |
1333 | return ret; | |
1334 | ||
267f0c90 | 1335 | seq_puts(m, "GPU freq (MHz)\tEffective CPU freq (MHz)\tEffective Ring freq (MHz)\n"); |
23b2f8bb | 1336 | |
c6a828d3 DV |
1337 | for (gpu_freq = dev_priv->rps.min_delay; |
1338 | gpu_freq <= dev_priv->rps.max_delay; | |
23b2f8bb | 1339 | gpu_freq++) { |
42c0526c BW |
1340 | ia_freq = gpu_freq; |
1341 | sandybridge_pcode_read(dev_priv, | |
1342 | GEN6_PCODE_READ_MIN_FREQ_TABLE, | |
1343 | &ia_freq); | |
3ebecd07 CW |
1344 | seq_printf(m, "%d\t\t%d\t\t\t\t%d\n", |
1345 | gpu_freq * GT_FREQUENCY_MULTIPLIER, | |
1346 | ((ia_freq >> 0) & 0xff) * 100, | |
1347 | ((ia_freq >> 8) & 0xff) * 100); | |
23b2f8bb JB |
1348 | } |
1349 | ||
4fc688ce | 1350 | mutex_unlock(&dev_priv->rps.hw_lock); |
23b2f8bb JB |
1351 | |
1352 | return 0; | |
1353 | } | |
1354 | ||
7648fa99 JB |
1355 | static int i915_gfxec(struct seq_file *m, void *unused) |
1356 | { | |
1357 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1358 | struct drm_device *dev = node->minor->dev; | |
1359 | drm_i915_private_t *dev_priv = dev->dev_private; | |
616fdb5a BW |
1360 | int ret; |
1361 | ||
1362 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
1363 | if (ret) | |
1364 | return ret; | |
7648fa99 JB |
1365 | |
1366 | seq_printf(m, "GFXEC: %ld\n", (unsigned long)I915_READ(0x112f4)); | |
1367 | ||
616fdb5a BW |
1368 | mutex_unlock(&dev->struct_mutex); |
1369 | ||
7648fa99 JB |
1370 | return 0; |
1371 | } | |
1372 | ||
44834a67 CW |
1373 | static int i915_opregion(struct seq_file *m, void *unused) |
1374 | { | |
1375 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1376 | struct drm_device *dev = node->minor->dev; | |
1377 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1378 | struct intel_opregion *opregion = &dev_priv->opregion; | |
0d38f009 | 1379 | void *data = kmalloc(OPREGION_SIZE, GFP_KERNEL); |
44834a67 CW |
1380 | int ret; |
1381 | ||
0d38f009 DV |
1382 | if (data == NULL) |
1383 | return -ENOMEM; | |
1384 | ||
44834a67 CW |
1385 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
1386 | if (ret) | |
0d38f009 | 1387 | goto out; |
44834a67 | 1388 | |
0d38f009 DV |
1389 | if (opregion->header) { |
1390 | memcpy_fromio(data, opregion->header, OPREGION_SIZE); | |
1391 | seq_write(m, data, OPREGION_SIZE); | |
1392 | } | |
44834a67 CW |
1393 | |
1394 | mutex_unlock(&dev->struct_mutex); | |
1395 | ||
0d38f009 DV |
1396 | out: |
1397 | kfree(data); | |
44834a67 CW |
1398 | return 0; |
1399 | } | |
1400 | ||
37811fcc CW |
1401 | static int i915_gem_framebuffer_info(struct seq_file *m, void *data) |
1402 | { | |
1403 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1404 | struct drm_device *dev = node->minor->dev; | |
1405 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1406 | struct intel_fbdev *ifbdev; | |
1407 | struct intel_framebuffer *fb; | |
1408 | int ret; | |
1409 | ||
1410 | ret = mutex_lock_interruptible(&dev->mode_config.mutex); | |
1411 | if (ret) | |
1412 | return ret; | |
1413 | ||
1414 | ifbdev = dev_priv->fbdev; | |
1415 | fb = to_intel_framebuffer(ifbdev->helper.fb); | |
1416 | ||
623f9783 | 1417 | seq_printf(m, "fbcon size: %d x %d, depth %d, %d bpp, refcount %d, obj ", |
37811fcc CW |
1418 | fb->base.width, |
1419 | fb->base.height, | |
1420 | fb->base.depth, | |
623f9783 DV |
1421 | fb->base.bits_per_pixel, |
1422 | atomic_read(&fb->base.refcount.refcount)); | |
05394f39 | 1423 | describe_obj(m, fb->obj); |
267f0c90 | 1424 | seq_putc(m, '\n'); |
4b096ac1 | 1425 | mutex_unlock(&dev->mode_config.mutex); |
37811fcc | 1426 | |
4b096ac1 | 1427 | mutex_lock(&dev->mode_config.fb_lock); |
37811fcc CW |
1428 | list_for_each_entry(fb, &dev->mode_config.fb_list, base.head) { |
1429 | if (&fb->base == ifbdev->helper.fb) | |
1430 | continue; | |
1431 | ||
623f9783 | 1432 | seq_printf(m, "user size: %d x %d, depth %d, %d bpp, refcount %d, obj ", |
37811fcc CW |
1433 | fb->base.width, |
1434 | fb->base.height, | |
1435 | fb->base.depth, | |
623f9783 DV |
1436 | fb->base.bits_per_pixel, |
1437 | atomic_read(&fb->base.refcount.refcount)); | |
05394f39 | 1438 | describe_obj(m, fb->obj); |
267f0c90 | 1439 | seq_putc(m, '\n'); |
37811fcc | 1440 | } |
4b096ac1 | 1441 | mutex_unlock(&dev->mode_config.fb_lock); |
37811fcc CW |
1442 | |
1443 | return 0; | |
1444 | } | |
1445 | ||
e76d3630 BW |
1446 | static int i915_context_status(struct seq_file *m, void *unused) |
1447 | { | |
1448 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1449 | struct drm_device *dev = node->minor->dev; | |
1450 | drm_i915_private_t *dev_priv = dev->dev_private; | |
a168c293 | 1451 | struct intel_ring_buffer *ring; |
a33afea5 | 1452 | struct i915_hw_context *ctx; |
a168c293 | 1453 | int ret, i; |
e76d3630 BW |
1454 | |
1455 | ret = mutex_lock_interruptible(&dev->mode_config.mutex); | |
1456 | if (ret) | |
1457 | return ret; | |
1458 | ||
3e373948 | 1459 | if (dev_priv->ips.pwrctx) { |
267f0c90 | 1460 | seq_puts(m, "power context "); |
3e373948 | 1461 | describe_obj(m, dev_priv->ips.pwrctx); |
267f0c90 | 1462 | seq_putc(m, '\n'); |
dc501fbc | 1463 | } |
e76d3630 | 1464 | |
3e373948 | 1465 | if (dev_priv->ips.renderctx) { |
267f0c90 | 1466 | seq_puts(m, "render context "); |
3e373948 | 1467 | describe_obj(m, dev_priv->ips.renderctx); |
267f0c90 | 1468 | seq_putc(m, '\n'); |
dc501fbc | 1469 | } |
e76d3630 | 1470 | |
a33afea5 BW |
1471 | list_for_each_entry(ctx, &dev_priv->context_list, link) { |
1472 | seq_puts(m, "HW context "); | |
3ccfd19d | 1473 | describe_ctx(m, ctx); |
a33afea5 BW |
1474 | for_each_ring(ring, dev_priv, i) |
1475 | if (ring->default_context == ctx) | |
1476 | seq_printf(m, "(default context %s) ", ring->name); | |
1477 | ||
1478 | describe_obj(m, ctx->obj); | |
1479 | seq_putc(m, '\n'); | |
a168c293 BW |
1480 | } |
1481 | ||
e76d3630 BW |
1482 | mutex_unlock(&dev->mode_config.mutex); |
1483 | ||
1484 | return 0; | |
1485 | } | |
1486 | ||
6d794d42 BW |
1487 | static int i915_gen6_forcewake_count_info(struct seq_file *m, void *data) |
1488 | { | |
1489 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1490 | struct drm_device *dev = node->minor->dev; | |
1491 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9f1f46a4 | 1492 | unsigned forcewake_count; |
6d794d42 | 1493 | |
907b28c5 CW |
1494 | spin_lock_irq(&dev_priv->uncore.lock); |
1495 | forcewake_count = dev_priv->uncore.forcewake_count; | |
1496 | spin_unlock_irq(&dev_priv->uncore.lock); | |
6d794d42 | 1497 | |
9f1f46a4 | 1498 | seq_printf(m, "forcewake count = %u\n", forcewake_count); |
6d794d42 BW |
1499 | |
1500 | return 0; | |
1501 | } | |
1502 | ||
ea16a3cd DV |
1503 | static const char *swizzle_string(unsigned swizzle) |
1504 | { | |
aee56cff | 1505 | switch (swizzle) { |
ea16a3cd DV |
1506 | case I915_BIT_6_SWIZZLE_NONE: |
1507 | return "none"; | |
1508 | case I915_BIT_6_SWIZZLE_9: | |
1509 | return "bit9"; | |
1510 | case I915_BIT_6_SWIZZLE_9_10: | |
1511 | return "bit9/bit10"; | |
1512 | case I915_BIT_6_SWIZZLE_9_11: | |
1513 | return "bit9/bit11"; | |
1514 | case I915_BIT_6_SWIZZLE_9_10_11: | |
1515 | return "bit9/bit10/bit11"; | |
1516 | case I915_BIT_6_SWIZZLE_9_17: | |
1517 | return "bit9/bit17"; | |
1518 | case I915_BIT_6_SWIZZLE_9_10_17: | |
1519 | return "bit9/bit10/bit17"; | |
1520 | case I915_BIT_6_SWIZZLE_UNKNOWN: | |
8a168ca7 | 1521 | return "unknown"; |
ea16a3cd DV |
1522 | } |
1523 | ||
1524 | return "bug"; | |
1525 | } | |
1526 | ||
1527 | static int i915_swizzle_info(struct seq_file *m, void *data) | |
1528 | { | |
1529 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1530 | struct drm_device *dev = node->minor->dev; | |
1531 | struct drm_i915_private *dev_priv = dev->dev_private; | |
22bcfc6a DV |
1532 | int ret; |
1533 | ||
1534 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
1535 | if (ret) | |
1536 | return ret; | |
ea16a3cd | 1537 | |
ea16a3cd DV |
1538 | seq_printf(m, "bit6 swizzle for X-tiling = %s\n", |
1539 | swizzle_string(dev_priv->mm.bit_6_swizzle_x)); | |
1540 | seq_printf(m, "bit6 swizzle for Y-tiling = %s\n", | |
1541 | swizzle_string(dev_priv->mm.bit_6_swizzle_y)); | |
1542 | ||
1543 | if (IS_GEN3(dev) || IS_GEN4(dev)) { | |
1544 | seq_printf(m, "DDC = 0x%08x\n", | |
1545 | I915_READ(DCC)); | |
1546 | seq_printf(m, "C0DRB3 = 0x%04x\n", | |
1547 | I915_READ16(C0DRB3)); | |
1548 | seq_printf(m, "C1DRB3 = 0x%04x\n", | |
1549 | I915_READ16(C1DRB3)); | |
3fa7d235 DV |
1550 | } else if (IS_GEN6(dev) || IS_GEN7(dev)) { |
1551 | seq_printf(m, "MAD_DIMM_C0 = 0x%08x\n", | |
1552 | I915_READ(MAD_DIMM_C0)); | |
1553 | seq_printf(m, "MAD_DIMM_C1 = 0x%08x\n", | |
1554 | I915_READ(MAD_DIMM_C1)); | |
1555 | seq_printf(m, "MAD_DIMM_C2 = 0x%08x\n", | |
1556 | I915_READ(MAD_DIMM_C2)); | |
1557 | seq_printf(m, "TILECTL = 0x%08x\n", | |
1558 | I915_READ(TILECTL)); | |
1559 | seq_printf(m, "ARB_MODE = 0x%08x\n", | |
1560 | I915_READ(ARB_MODE)); | |
1561 | seq_printf(m, "DISP_ARB_CTL = 0x%08x\n", | |
1562 | I915_READ(DISP_ARB_CTL)); | |
ea16a3cd DV |
1563 | } |
1564 | mutex_unlock(&dev->struct_mutex); | |
1565 | ||
1566 | return 0; | |
1567 | } | |
1568 | ||
3cf17fc5 DV |
1569 | static int i915_ppgtt_info(struct seq_file *m, void *data) |
1570 | { | |
1571 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1572 | struct drm_device *dev = node->minor->dev; | |
1573 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1574 | struct intel_ring_buffer *ring; | |
1575 | int i, ret; | |
1576 | ||
1577 | ||
1578 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
1579 | if (ret) | |
1580 | return ret; | |
1581 | if (INTEL_INFO(dev)->gen == 6) | |
1582 | seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(GFX_MODE)); | |
1583 | ||
a2c7f6fd | 1584 | for_each_ring(ring, dev_priv, i) { |
3cf17fc5 DV |
1585 | seq_printf(m, "%s\n", ring->name); |
1586 | if (INTEL_INFO(dev)->gen == 7) | |
1587 | seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(RING_MODE_GEN7(ring))); | |
1588 | seq_printf(m, "PP_DIR_BASE: 0x%08x\n", I915_READ(RING_PP_DIR_BASE(ring))); | |
1589 | seq_printf(m, "PP_DIR_BASE_READ: 0x%08x\n", I915_READ(RING_PP_DIR_BASE_READ(ring))); | |
1590 | seq_printf(m, "PP_DIR_DCLV: 0x%08x\n", I915_READ(RING_PP_DIR_DCLV(ring))); | |
1591 | } | |
1592 | if (dev_priv->mm.aliasing_ppgtt) { | |
1593 | struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt; | |
1594 | ||
267f0c90 | 1595 | seq_puts(m, "aliasing PPGTT:\n"); |
3cf17fc5 DV |
1596 | seq_printf(m, "pd gtt offset: 0x%08x\n", ppgtt->pd_offset); |
1597 | } | |
1598 | seq_printf(m, "ECOCHK: 0x%08x\n", I915_READ(GAM_ECOCHK)); | |
1599 | mutex_unlock(&dev->struct_mutex); | |
1600 | ||
1601 | return 0; | |
1602 | } | |
1603 | ||
57f350b6 JB |
1604 | static int i915_dpio_info(struct seq_file *m, void *data) |
1605 | { | |
1606 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1607 | struct drm_device *dev = node->minor->dev; | |
1608 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1609 | int ret; | |
1610 | ||
1611 | ||
1612 | if (!IS_VALLEYVIEW(dev)) { | |
267f0c90 | 1613 | seq_puts(m, "unsupported\n"); |
57f350b6 JB |
1614 | return 0; |
1615 | } | |
1616 | ||
09153000 | 1617 | ret = mutex_lock_interruptible(&dev_priv->dpio_lock); |
57f350b6 JB |
1618 | if (ret) |
1619 | return ret; | |
1620 | ||
1621 | seq_printf(m, "DPIO_CTL: 0x%08x\n", I915_READ(DPIO_CTL)); | |
1622 | ||
1623 | seq_printf(m, "DPIO_DIV_A: 0x%08x\n", | |
5e69f97f | 1624 | vlv_dpio_read(dev_priv, PIPE_A, _DPIO_DIV_A)); |
57f350b6 | 1625 | seq_printf(m, "DPIO_DIV_B: 0x%08x\n", |
5e69f97f | 1626 | vlv_dpio_read(dev_priv, PIPE_A, _DPIO_DIV_B)); |
57f350b6 JB |
1627 | |
1628 | seq_printf(m, "DPIO_REFSFR_A: 0x%08x\n", | |
5e69f97f | 1629 | vlv_dpio_read(dev_priv, PIPE_A, _DPIO_REFSFR_A)); |
57f350b6 | 1630 | seq_printf(m, "DPIO_REFSFR_B: 0x%08x\n", |
5e69f97f | 1631 | vlv_dpio_read(dev_priv, PIPE_A, _DPIO_REFSFR_B)); |
57f350b6 JB |
1632 | |
1633 | seq_printf(m, "DPIO_CORE_CLK_A: 0x%08x\n", | |
5e69f97f | 1634 | vlv_dpio_read(dev_priv, PIPE_A, _DPIO_CORE_CLK_A)); |
57f350b6 | 1635 | seq_printf(m, "DPIO_CORE_CLK_B: 0x%08x\n", |
5e69f97f | 1636 | vlv_dpio_read(dev_priv, PIPE_A, _DPIO_CORE_CLK_B)); |
57f350b6 | 1637 | |
4abb2c39 | 1638 | seq_printf(m, "DPIO_LPF_COEFF_A: 0x%08x\n", |
5e69f97f | 1639 | vlv_dpio_read(dev_priv, PIPE_A, _DPIO_LPF_COEFF_A)); |
4abb2c39 | 1640 | seq_printf(m, "DPIO_LPF_COEFF_B: 0x%08x\n", |
5e69f97f | 1641 | vlv_dpio_read(dev_priv, PIPE_A, _DPIO_LPF_COEFF_B)); |
57f350b6 JB |
1642 | |
1643 | seq_printf(m, "DPIO_FASTCLK_DISABLE: 0x%08x\n", | |
5e69f97f | 1644 | vlv_dpio_read(dev_priv, PIPE_A, DPIO_FASTCLK_DISABLE)); |
57f350b6 | 1645 | |
09153000 | 1646 | mutex_unlock(&dev_priv->dpio_lock); |
57f350b6 JB |
1647 | |
1648 | return 0; | |
1649 | } | |
1650 | ||
63573eb7 BW |
1651 | static int i915_llc(struct seq_file *m, void *data) |
1652 | { | |
1653 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1654 | struct drm_device *dev = node->minor->dev; | |
1655 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1656 | ||
1657 | /* Size calculation for LLC is a bit of a pain. Ignore for now. */ | |
1658 | seq_printf(m, "LLC: %s\n", yesno(HAS_LLC(dev))); | |
1659 | seq_printf(m, "eLLC: %zuMB\n", dev_priv->ellc_size); | |
1660 | ||
1661 | return 0; | |
1662 | } | |
1663 | ||
e91fd8c6 RV |
1664 | static int i915_edp_psr_status(struct seq_file *m, void *data) |
1665 | { | |
1666 | struct drm_info_node *node = m->private; | |
1667 | struct drm_device *dev = node->minor->dev; | |
1668 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3f51e471 | 1669 | u32 psrstat, psrperf; |
e91fd8c6 | 1670 | |
18b5992c | 1671 | if (!HAS_PSR(dev)) { |
e91fd8c6 | 1672 | seq_puts(m, "PSR not supported on this platform\n"); |
18b5992c BW |
1673 | } else if (HAS_PSR(dev) && |
1674 | I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE) { | |
3f51e471 RV |
1675 | seq_puts(m, "PSR enabled\n"); |
1676 | } else { | |
1677 | seq_puts(m, "PSR disabled: "); | |
1678 | switch (dev_priv->no_psr_reason) { | |
1679 | case PSR_NO_SOURCE: | |
1680 | seq_puts(m, "not supported on this platform"); | |
1681 | break; | |
1682 | case PSR_NO_SINK: | |
1683 | seq_puts(m, "not supported by panel"); | |
1684 | break; | |
105b7c11 RV |
1685 | case PSR_MODULE_PARAM: |
1686 | seq_puts(m, "disabled by flag"); | |
1687 | break; | |
3f51e471 RV |
1688 | case PSR_CRTC_NOT_ACTIVE: |
1689 | seq_puts(m, "crtc not active"); | |
1690 | break; | |
1691 | case PSR_PWR_WELL_ENABLED: | |
1692 | seq_puts(m, "power well enabled"); | |
1693 | break; | |
1694 | case PSR_NOT_TILED: | |
1695 | seq_puts(m, "not tiled"); | |
1696 | break; | |
1697 | case PSR_SPRITE_ENABLED: | |
1698 | seq_puts(m, "sprite enabled"); | |
1699 | break; | |
1700 | case PSR_S3D_ENABLED: | |
1701 | seq_puts(m, "stereo 3d enabled"); | |
1702 | break; | |
1703 | case PSR_INTERLACED_ENABLED: | |
1704 | seq_puts(m, "interlaced enabled"); | |
1705 | break; | |
1706 | case PSR_HSW_NOT_DDIA: | |
1707 | seq_puts(m, "HSW ties PSR to DDI A (eDP)"); | |
1708 | break; | |
1709 | default: | |
1710 | seq_puts(m, "unknown reason"); | |
1711 | } | |
1712 | seq_puts(m, "\n"); | |
e91fd8c6 RV |
1713 | return 0; |
1714 | } | |
1715 | ||
18b5992c | 1716 | psrstat = I915_READ(EDP_PSR_STATUS_CTL(dev)); |
e91fd8c6 RV |
1717 | |
1718 | seq_puts(m, "PSR Current State: "); | |
1719 | switch (psrstat & EDP_PSR_STATUS_STATE_MASK) { | |
1720 | case EDP_PSR_STATUS_STATE_IDLE: | |
1721 | seq_puts(m, "Reset state\n"); | |
1722 | break; | |
1723 | case EDP_PSR_STATUS_STATE_SRDONACK: | |
1724 | seq_puts(m, "Wait for TG/Stream to send on frame of data after SRD conditions are met\n"); | |
1725 | break; | |
1726 | case EDP_PSR_STATUS_STATE_SRDENT: | |
1727 | seq_puts(m, "SRD entry\n"); | |
1728 | break; | |
1729 | case EDP_PSR_STATUS_STATE_BUFOFF: | |
1730 | seq_puts(m, "Wait for buffer turn off\n"); | |
1731 | break; | |
1732 | case EDP_PSR_STATUS_STATE_BUFON: | |
1733 | seq_puts(m, "Wait for buffer turn on\n"); | |
1734 | break; | |
1735 | case EDP_PSR_STATUS_STATE_AUXACK: | |
1736 | seq_puts(m, "Wait for AUX to acknowledge on SRD exit\n"); | |
1737 | break; | |
1738 | case EDP_PSR_STATUS_STATE_SRDOFFACK: | |
1739 | seq_puts(m, "Wait for TG/Stream to acknowledge the SRD VDM exit\n"); | |
1740 | break; | |
1741 | default: | |
1742 | seq_puts(m, "Unknown\n"); | |
1743 | break; | |
1744 | } | |
1745 | ||
1746 | seq_puts(m, "Link Status: "); | |
1747 | switch (psrstat & EDP_PSR_STATUS_LINK_MASK) { | |
1748 | case EDP_PSR_STATUS_LINK_FULL_OFF: | |
1749 | seq_puts(m, "Link is fully off\n"); | |
1750 | break; | |
1751 | case EDP_PSR_STATUS_LINK_FULL_ON: | |
1752 | seq_puts(m, "Link is fully on\n"); | |
1753 | break; | |
1754 | case EDP_PSR_STATUS_LINK_STANDBY: | |
1755 | seq_puts(m, "Link is in standby\n"); | |
1756 | break; | |
1757 | default: | |
1758 | seq_puts(m, "Unknown\n"); | |
1759 | break; | |
1760 | } | |
1761 | ||
1762 | seq_printf(m, "PSR Entry Count: %u\n", | |
1763 | psrstat >> EDP_PSR_STATUS_COUNT_SHIFT & | |
1764 | EDP_PSR_STATUS_COUNT_MASK); | |
1765 | ||
1766 | seq_printf(m, "Max Sleep Timer Counter: %u\n", | |
1767 | psrstat >> EDP_PSR_STATUS_MAX_SLEEP_TIMER_SHIFT & | |
1768 | EDP_PSR_STATUS_MAX_SLEEP_TIMER_MASK); | |
1769 | ||
1770 | seq_printf(m, "Had AUX error: %s\n", | |
1771 | yesno(psrstat & EDP_PSR_STATUS_AUX_ERROR)); | |
1772 | ||
1773 | seq_printf(m, "Sending AUX: %s\n", | |
1774 | yesno(psrstat & EDP_PSR_STATUS_AUX_SENDING)); | |
1775 | ||
1776 | seq_printf(m, "Sending Idle: %s\n", | |
1777 | yesno(psrstat & EDP_PSR_STATUS_SENDING_IDLE)); | |
1778 | ||
1779 | seq_printf(m, "Sending TP2 TP3: %s\n", | |
1780 | yesno(psrstat & EDP_PSR_STATUS_SENDING_TP2_TP3)); | |
1781 | ||
1782 | seq_printf(m, "Sending TP1: %s\n", | |
1783 | yesno(psrstat & EDP_PSR_STATUS_SENDING_TP1)); | |
1784 | ||
1785 | seq_printf(m, "Idle Count: %u\n", | |
1786 | psrstat & EDP_PSR_STATUS_IDLE_MASK); | |
1787 | ||
18b5992c | 1788 | psrperf = (I915_READ(EDP_PSR_PERF_CNT(dev))) & EDP_PSR_PERF_CNT_MASK; |
e91fd8c6 RV |
1789 | seq_printf(m, "Performance Counter: %u\n", psrperf); |
1790 | ||
1791 | return 0; | |
1792 | } | |
1793 | ||
ec013e7f JB |
1794 | static int i915_energy_uJ(struct seq_file *m, void *data) |
1795 | { | |
1796 | struct drm_info_node *node = m->private; | |
1797 | struct drm_device *dev = node->minor->dev; | |
1798 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1799 | u64 power; | |
1800 | u32 units; | |
1801 | ||
1802 | if (INTEL_INFO(dev)->gen < 6) | |
1803 | return -ENODEV; | |
1804 | ||
1805 | rdmsrl(MSR_RAPL_POWER_UNIT, power); | |
1806 | power = (power & 0x1f00) >> 8; | |
1807 | units = 1000000 / (1 << power); /* convert to uJ */ | |
1808 | power = I915_READ(MCH_SECP_NRG_STTS); | |
1809 | power *= units; | |
1810 | ||
1811 | seq_printf(m, "%llu", (long long unsigned)power); | |
371db66a PZ |
1812 | |
1813 | return 0; | |
1814 | } | |
1815 | ||
1816 | static int i915_pc8_status(struct seq_file *m, void *unused) | |
1817 | { | |
1818 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1819 | struct drm_device *dev = node->minor->dev; | |
1820 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1821 | ||
1822 | if (!IS_HASWELL(dev)) { | |
1823 | seq_puts(m, "not supported\n"); | |
1824 | return 0; | |
1825 | } | |
1826 | ||
1827 | mutex_lock(&dev_priv->pc8.lock); | |
1828 | seq_printf(m, "Requirements met: %s\n", | |
1829 | yesno(dev_priv->pc8.requirements_met)); | |
1830 | seq_printf(m, "GPU idle: %s\n", yesno(dev_priv->pc8.gpu_idle)); | |
1831 | seq_printf(m, "Disable count: %d\n", dev_priv->pc8.disable_count); | |
1832 | seq_printf(m, "IRQs disabled: %s\n", | |
1833 | yesno(dev_priv->pc8.irqs_disabled)); | |
1834 | seq_printf(m, "Enabled: %s\n", yesno(dev_priv->pc8.enabled)); | |
1835 | mutex_unlock(&dev_priv->pc8.lock); | |
1836 | ||
ec013e7f JB |
1837 | return 0; |
1838 | } | |
1839 | ||
647416f9 KC |
1840 | static int |
1841 | i915_wedged_get(void *data, u64 *val) | |
f3cd474b | 1842 | { |
647416f9 | 1843 | struct drm_device *dev = data; |
f3cd474b | 1844 | drm_i915_private_t *dev_priv = dev->dev_private; |
f3cd474b | 1845 | |
647416f9 | 1846 | *val = atomic_read(&dev_priv->gpu_error.reset_counter); |
f3cd474b | 1847 | |
647416f9 | 1848 | return 0; |
f3cd474b CW |
1849 | } |
1850 | ||
647416f9 KC |
1851 | static int |
1852 | i915_wedged_set(void *data, u64 val) | |
f3cd474b | 1853 | { |
647416f9 | 1854 | struct drm_device *dev = data; |
f3cd474b | 1855 | |
647416f9 | 1856 | DRM_INFO("Manually setting wedged to %llu\n", val); |
527f9e90 | 1857 | i915_handle_error(dev, val); |
f3cd474b | 1858 | |
647416f9 | 1859 | return 0; |
f3cd474b CW |
1860 | } |
1861 | ||
647416f9 KC |
1862 | DEFINE_SIMPLE_ATTRIBUTE(i915_wedged_fops, |
1863 | i915_wedged_get, i915_wedged_set, | |
3a3b4f98 | 1864 | "%llu\n"); |
f3cd474b | 1865 | |
647416f9 KC |
1866 | static int |
1867 | i915_ring_stop_get(void *data, u64 *val) | |
e5eb3d63 | 1868 | { |
647416f9 | 1869 | struct drm_device *dev = data; |
e5eb3d63 | 1870 | drm_i915_private_t *dev_priv = dev->dev_private; |
e5eb3d63 | 1871 | |
647416f9 | 1872 | *val = dev_priv->gpu_error.stop_rings; |
e5eb3d63 | 1873 | |
647416f9 | 1874 | return 0; |
e5eb3d63 DV |
1875 | } |
1876 | ||
647416f9 KC |
1877 | static int |
1878 | i915_ring_stop_set(void *data, u64 val) | |
e5eb3d63 | 1879 | { |
647416f9 | 1880 | struct drm_device *dev = data; |
e5eb3d63 | 1881 | struct drm_i915_private *dev_priv = dev->dev_private; |
647416f9 | 1882 | int ret; |
e5eb3d63 | 1883 | |
647416f9 | 1884 | DRM_DEBUG_DRIVER("Stopping rings 0x%08llx\n", val); |
e5eb3d63 | 1885 | |
22bcfc6a DV |
1886 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
1887 | if (ret) | |
1888 | return ret; | |
1889 | ||
99584db3 | 1890 | dev_priv->gpu_error.stop_rings = val; |
e5eb3d63 DV |
1891 | mutex_unlock(&dev->struct_mutex); |
1892 | ||
647416f9 | 1893 | return 0; |
e5eb3d63 DV |
1894 | } |
1895 | ||
647416f9 KC |
1896 | DEFINE_SIMPLE_ATTRIBUTE(i915_ring_stop_fops, |
1897 | i915_ring_stop_get, i915_ring_stop_set, | |
1898 | "0x%08llx\n"); | |
d5442303 | 1899 | |
094f9a54 CW |
1900 | static int |
1901 | i915_ring_missed_irq_get(void *data, u64 *val) | |
1902 | { | |
1903 | struct drm_device *dev = data; | |
1904 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1905 | ||
1906 | *val = dev_priv->gpu_error.missed_irq_rings; | |
1907 | return 0; | |
1908 | } | |
1909 | ||
1910 | static int | |
1911 | i915_ring_missed_irq_set(void *data, u64 val) | |
1912 | { | |
1913 | struct drm_device *dev = data; | |
1914 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1915 | int ret; | |
1916 | ||
1917 | /* Lock against concurrent debugfs callers */ | |
1918 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
1919 | if (ret) | |
1920 | return ret; | |
1921 | dev_priv->gpu_error.missed_irq_rings = val; | |
1922 | mutex_unlock(&dev->struct_mutex); | |
1923 | ||
1924 | return 0; | |
1925 | } | |
1926 | ||
1927 | DEFINE_SIMPLE_ATTRIBUTE(i915_ring_missed_irq_fops, | |
1928 | i915_ring_missed_irq_get, i915_ring_missed_irq_set, | |
1929 | "0x%08llx\n"); | |
1930 | ||
1931 | static int | |
1932 | i915_ring_test_irq_get(void *data, u64 *val) | |
1933 | { | |
1934 | struct drm_device *dev = data; | |
1935 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1936 | ||
1937 | *val = dev_priv->gpu_error.test_irq_rings; | |
1938 | ||
1939 | return 0; | |
1940 | } | |
1941 | ||
1942 | static int | |
1943 | i915_ring_test_irq_set(void *data, u64 val) | |
1944 | { | |
1945 | struct drm_device *dev = data; | |
1946 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1947 | int ret; | |
1948 | ||
1949 | DRM_DEBUG_DRIVER("Masking interrupts on rings 0x%08llx\n", val); | |
1950 | ||
1951 | /* Lock against concurrent debugfs callers */ | |
1952 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
1953 | if (ret) | |
1954 | return ret; | |
1955 | ||
1956 | dev_priv->gpu_error.test_irq_rings = val; | |
1957 | mutex_unlock(&dev->struct_mutex); | |
1958 | ||
1959 | return 0; | |
1960 | } | |
1961 | ||
1962 | DEFINE_SIMPLE_ATTRIBUTE(i915_ring_test_irq_fops, | |
1963 | i915_ring_test_irq_get, i915_ring_test_irq_set, | |
1964 | "0x%08llx\n"); | |
1965 | ||
dd624afd CW |
1966 | #define DROP_UNBOUND 0x1 |
1967 | #define DROP_BOUND 0x2 | |
1968 | #define DROP_RETIRE 0x4 | |
1969 | #define DROP_ACTIVE 0x8 | |
1970 | #define DROP_ALL (DROP_UNBOUND | \ | |
1971 | DROP_BOUND | \ | |
1972 | DROP_RETIRE | \ | |
1973 | DROP_ACTIVE) | |
647416f9 KC |
1974 | static int |
1975 | i915_drop_caches_get(void *data, u64 *val) | |
dd624afd | 1976 | { |
647416f9 | 1977 | *val = DROP_ALL; |
dd624afd | 1978 | |
647416f9 | 1979 | return 0; |
dd624afd CW |
1980 | } |
1981 | ||
647416f9 KC |
1982 | static int |
1983 | i915_drop_caches_set(void *data, u64 val) | |
dd624afd | 1984 | { |
647416f9 | 1985 | struct drm_device *dev = data; |
dd624afd CW |
1986 | struct drm_i915_private *dev_priv = dev->dev_private; |
1987 | struct drm_i915_gem_object *obj, *next; | |
ca191b13 BW |
1988 | struct i915_address_space *vm; |
1989 | struct i915_vma *vma, *x; | |
647416f9 | 1990 | int ret; |
dd624afd | 1991 | |
647416f9 | 1992 | DRM_DEBUG_DRIVER("Dropping caches: 0x%08llx\n", val); |
dd624afd CW |
1993 | |
1994 | /* No need to check and wait for gpu resets, only libdrm auto-restarts | |
1995 | * on ioctls on -EAGAIN. */ | |
1996 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
1997 | if (ret) | |
1998 | return ret; | |
1999 | ||
2000 | if (val & DROP_ACTIVE) { | |
2001 | ret = i915_gpu_idle(dev); | |
2002 | if (ret) | |
2003 | goto unlock; | |
2004 | } | |
2005 | ||
2006 | if (val & (DROP_RETIRE | DROP_ACTIVE)) | |
2007 | i915_gem_retire_requests(dev); | |
2008 | ||
2009 | if (val & DROP_BOUND) { | |
ca191b13 BW |
2010 | list_for_each_entry(vm, &dev_priv->vm_list, global_link) { |
2011 | list_for_each_entry_safe(vma, x, &vm->inactive_list, | |
2012 | mm_list) { | |
2013 | if (vma->obj->pin_count) | |
2014 | continue; | |
2015 | ||
2016 | ret = i915_vma_unbind(vma); | |
2017 | if (ret) | |
2018 | goto unlock; | |
2019 | } | |
31a46c9c | 2020 | } |
dd624afd CW |
2021 | } |
2022 | ||
2023 | if (val & DROP_UNBOUND) { | |
35c20a60 BW |
2024 | list_for_each_entry_safe(obj, next, &dev_priv->mm.unbound_list, |
2025 | global_list) | |
dd624afd CW |
2026 | if (obj->pages_pin_count == 0) { |
2027 | ret = i915_gem_object_put_pages(obj); | |
2028 | if (ret) | |
2029 | goto unlock; | |
2030 | } | |
2031 | } | |
2032 | ||
2033 | unlock: | |
2034 | mutex_unlock(&dev->struct_mutex); | |
2035 | ||
647416f9 | 2036 | return ret; |
dd624afd CW |
2037 | } |
2038 | ||
647416f9 KC |
2039 | DEFINE_SIMPLE_ATTRIBUTE(i915_drop_caches_fops, |
2040 | i915_drop_caches_get, i915_drop_caches_set, | |
2041 | "0x%08llx\n"); | |
dd624afd | 2042 | |
647416f9 KC |
2043 | static int |
2044 | i915_max_freq_get(void *data, u64 *val) | |
358733e9 | 2045 | { |
647416f9 | 2046 | struct drm_device *dev = data; |
358733e9 | 2047 | drm_i915_private_t *dev_priv = dev->dev_private; |
647416f9 | 2048 | int ret; |
004777cb DV |
2049 | |
2050 | if (!(IS_GEN6(dev) || IS_GEN7(dev))) | |
2051 | return -ENODEV; | |
2052 | ||
4fc688ce | 2053 | ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock); |
004777cb DV |
2054 | if (ret) |
2055 | return ret; | |
358733e9 | 2056 | |
0a073b84 JB |
2057 | if (IS_VALLEYVIEW(dev)) |
2058 | *val = vlv_gpu_freq(dev_priv->mem_freq, | |
2059 | dev_priv->rps.max_delay); | |
2060 | else | |
2061 | *val = dev_priv->rps.max_delay * GT_FREQUENCY_MULTIPLIER; | |
4fc688ce | 2062 | mutex_unlock(&dev_priv->rps.hw_lock); |
358733e9 | 2063 | |
647416f9 | 2064 | return 0; |
358733e9 JB |
2065 | } |
2066 | ||
647416f9 KC |
2067 | static int |
2068 | i915_max_freq_set(void *data, u64 val) | |
358733e9 | 2069 | { |
647416f9 | 2070 | struct drm_device *dev = data; |
358733e9 | 2071 | struct drm_i915_private *dev_priv = dev->dev_private; |
647416f9 | 2072 | int ret; |
004777cb DV |
2073 | |
2074 | if (!(IS_GEN6(dev) || IS_GEN7(dev))) | |
2075 | return -ENODEV; | |
358733e9 | 2076 | |
647416f9 | 2077 | DRM_DEBUG_DRIVER("Manually setting max freq to %llu\n", val); |
358733e9 | 2078 | |
4fc688ce | 2079 | ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock); |
004777cb DV |
2080 | if (ret) |
2081 | return ret; | |
2082 | ||
358733e9 JB |
2083 | /* |
2084 | * Turbo will still be enabled, but won't go above the set value. | |
2085 | */ | |
0a073b84 JB |
2086 | if (IS_VALLEYVIEW(dev)) { |
2087 | val = vlv_freq_opcode(dev_priv->mem_freq, val); | |
2088 | dev_priv->rps.max_delay = val; | |
2089 | gen6_set_rps(dev, val); | |
2090 | } else { | |
2091 | do_div(val, GT_FREQUENCY_MULTIPLIER); | |
2092 | dev_priv->rps.max_delay = val; | |
2093 | gen6_set_rps(dev, val); | |
2094 | } | |
2095 | ||
4fc688ce | 2096 | mutex_unlock(&dev_priv->rps.hw_lock); |
358733e9 | 2097 | |
647416f9 | 2098 | return 0; |
358733e9 JB |
2099 | } |
2100 | ||
647416f9 KC |
2101 | DEFINE_SIMPLE_ATTRIBUTE(i915_max_freq_fops, |
2102 | i915_max_freq_get, i915_max_freq_set, | |
3a3b4f98 | 2103 | "%llu\n"); |
358733e9 | 2104 | |
647416f9 KC |
2105 | static int |
2106 | i915_min_freq_get(void *data, u64 *val) | |
1523c310 | 2107 | { |
647416f9 | 2108 | struct drm_device *dev = data; |
1523c310 | 2109 | drm_i915_private_t *dev_priv = dev->dev_private; |
647416f9 | 2110 | int ret; |
004777cb DV |
2111 | |
2112 | if (!(IS_GEN6(dev) || IS_GEN7(dev))) | |
2113 | return -ENODEV; | |
2114 | ||
4fc688ce | 2115 | ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock); |
004777cb DV |
2116 | if (ret) |
2117 | return ret; | |
1523c310 | 2118 | |
0a073b84 JB |
2119 | if (IS_VALLEYVIEW(dev)) |
2120 | *val = vlv_gpu_freq(dev_priv->mem_freq, | |
2121 | dev_priv->rps.min_delay); | |
2122 | else | |
2123 | *val = dev_priv->rps.min_delay * GT_FREQUENCY_MULTIPLIER; | |
4fc688ce | 2124 | mutex_unlock(&dev_priv->rps.hw_lock); |
1523c310 | 2125 | |
647416f9 | 2126 | return 0; |
1523c310 JB |
2127 | } |
2128 | ||
647416f9 KC |
2129 | static int |
2130 | i915_min_freq_set(void *data, u64 val) | |
1523c310 | 2131 | { |
647416f9 | 2132 | struct drm_device *dev = data; |
1523c310 | 2133 | struct drm_i915_private *dev_priv = dev->dev_private; |
647416f9 | 2134 | int ret; |
004777cb DV |
2135 | |
2136 | if (!(IS_GEN6(dev) || IS_GEN7(dev))) | |
2137 | return -ENODEV; | |
1523c310 | 2138 | |
647416f9 | 2139 | DRM_DEBUG_DRIVER("Manually setting min freq to %llu\n", val); |
1523c310 | 2140 | |
4fc688ce | 2141 | ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock); |
004777cb DV |
2142 | if (ret) |
2143 | return ret; | |
2144 | ||
1523c310 JB |
2145 | /* |
2146 | * Turbo will still be enabled, but won't go below the set value. | |
2147 | */ | |
0a073b84 JB |
2148 | if (IS_VALLEYVIEW(dev)) { |
2149 | val = vlv_freq_opcode(dev_priv->mem_freq, val); | |
2150 | dev_priv->rps.min_delay = val; | |
2151 | valleyview_set_rps(dev, val); | |
2152 | } else { | |
2153 | do_div(val, GT_FREQUENCY_MULTIPLIER); | |
2154 | dev_priv->rps.min_delay = val; | |
2155 | gen6_set_rps(dev, val); | |
2156 | } | |
4fc688ce | 2157 | mutex_unlock(&dev_priv->rps.hw_lock); |
1523c310 | 2158 | |
647416f9 | 2159 | return 0; |
1523c310 JB |
2160 | } |
2161 | ||
647416f9 KC |
2162 | DEFINE_SIMPLE_ATTRIBUTE(i915_min_freq_fops, |
2163 | i915_min_freq_get, i915_min_freq_set, | |
3a3b4f98 | 2164 | "%llu\n"); |
1523c310 | 2165 | |
647416f9 KC |
2166 | static int |
2167 | i915_cache_sharing_get(void *data, u64 *val) | |
07b7ddd9 | 2168 | { |
647416f9 | 2169 | struct drm_device *dev = data; |
07b7ddd9 | 2170 | drm_i915_private_t *dev_priv = dev->dev_private; |
07b7ddd9 | 2171 | u32 snpcr; |
647416f9 | 2172 | int ret; |
07b7ddd9 | 2173 | |
004777cb DV |
2174 | if (!(IS_GEN6(dev) || IS_GEN7(dev))) |
2175 | return -ENODEV; | |
2176 | ||
22bcfc6a DV |
2177 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
2178 | if (ret) | |
2179 | return ret; | |
2180 | ||
07b7ddd9 JB |
2181 | snpcr = I915_READ(GEN6_MBCUNIT_SNPCR); |
2182 | mutex_unlock(&dev_priv->dev->struct_mutex); | |
2183 | ||
647416f9 | 2184 | *val = (snpcr & GEN6_MBC_SNPCR_MASK) >> GEN6_MBC_SNPCR_SHIFT; |
07b7ddd9 | 2185 | |
647416f9 | 2186 | return 0; |
07b7ddd9 JB |
2187 | } |
2188 | ||
647416f9 KC |
2189 | static int |
2190 | i915_cache_sharing_set(void *data, u64 val) | |
07b7ddd9 | 2191 | { |
647416f9 | 2192 | struct drm_device *dev = data; |
07b7ddd9 | 2193 | struct drm_i915_private *dev_priv = dev->dev_private; |
07b7ddd9 | 2194 | u32 snpcr; |
07b7ddd9 | 2195 | |
004777cb DV |
2196 | if (!(IS_GEN6(dev) || IS_GEN7(dev))) |
2197 | return -ENODEV; | |
2198 | ||
647416f9 | 2199 | if (val > 3) |
07b7ddd9 JB |
2200 | return -EINVAL; |
2201 | ||
647416f9 | 2202 | DRM_DEBUG_DRIVER("Manually setting uncore sharing to %llu\n", val); |
07b7ddd9 JB |
2203 | |
2204 | /* Update the cache sharing policy here as well */ | |
2205 | snpcr = I915_READ(GEN6_MBCUNIT_SNPCR); | |
2206 | snpcr &= ~GEN6_MBC_SNPCR_MASK; | |
2207 | snpcr |= (val << GEN6_MBC_SNPCR_SHIFT); | |
2208 | I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr); | |
2209 | ||
647416f9 | 2210 | return 0; |
07b7ddd9 JB |
2211 | } |
2212 | ||
647416f9 KC |
2213 | DEFINE_SIMPLE_ATTRIBUTE(i915_cache_sharing_fops, |
2214 | i915_cache_sharing_get, i915_cache_sharing_set, | |
2215 | "%llu\n"); | |
07b7ddd9 | 2216 | |
f3cd474b CW |
2217 | /* As the drm_debugfs_init() routines are called before dev->dev_private is |
2218 | * allocated we need to hook into the minor for release. */ | |
2219 | static int | |
2220 | drm_add_fake_info_node(struct drm_minor *minor, | |
2221 | struct dentry *ent, | |
2222 | const void *key) | |
2223 | { | |
2224 | struct drm_info_node *node; | |
2225 | ||
b14c5679 | 2226 | node = kmalloc(sizeof(*node), GFP_KERNEL); |
f3cd474b CW |
2227 | if (node == NULL) { |
2228 | debugfs_remove(ent); | |
2229 | return -ENOMEM; | |
2230 | } | |
2231 | ||
2232 | node->minor = minor; | |
2233 | node->dent = ent; | |
2234 | node->info_ent = (void *) key; | |
b3e067c0 MS |
2235 | |
2236 | mutex_lock(&minor->debugfs_lock); | |
2237 | list_add(&node->list, &minor->debugfs_list); | |
2238 | mutex_unlock(&minor->debugfs_lock); | |
f3cd474b CW |
2239 | |
2240 | return 0; | |
2241 | } | |
2242 | ||
6d794d42 BW |
2243 | static int i915_forcewake_open(struct inode *inode, struct file *file) |
2244 | { | |
2245 | struct drm_device *dev = inode->i_private; | |
2246 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6d794d42 | 2247 | |
075edca4 | 2248 | if (INTEL_INFO(dev)->gen < 6) |
6d794d42 BW |
2249 | return 0; |
2250 | ||
6d794d42 | 2251 | gen6_gt_force_wake_get(dev_priv); |
6d794d42 BW |
2252 | |
2253 | return 0; | |
2254 | } | |
2255 | ||
c43b5634 | 2256 | static int i915_forcewake_release(struct inode *inode, struct file *file) |
6d794d42 BW |
2257 | { |
2258 | struct drm_device *dev = inode->i_private; | |
2259 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2260 | ||
075edca4 | 2261 | if (INTEL_INFO(dev)->gen < 6) |
6d794d42 BW |
2262 | return 0; |
2263 | ||
6d794d42 | 2264 | gen6_gt_force_wake_put(dev_priv); |
6d794d42 BW |
2265 | |
2266 | return 0; | |
2267 | } | |
2268 | ||
2269 | static const struct file_operations i915_forcewake_fops = { | |
2270 | .owner = THIS_MODULE, | |
2271 | .open = i915_forcewake_open, | |
2272 | .release = i915_forcewake_release, | |
2273 | }; | |
2274 | ||
2275 | static int i915_forcewake_create(struct dentry *root, struct drm_minor *minor) | |
2276 | { | |
2277 | struct drm_device *dev = minor->dev; | |
2278 | struct dentry *ent; | |
2279 | ||
2280 | ent = debugfs_create_file("i915_forcewake_user", | |
8eb57294 | 2281 | S_IRUSR, |
6d794d42 BW |
2282 | root, dev, |
2283 | &i915_forcewake_fops); | |
2284 | if (IS_ERR(ent)) | |
2285 | return PTR_ERR(ent); | |
2286 | ||
8eb57294 | 2287 | return drm_add_fake_info_node(minor, ent, &i915_forcewake_fops); |
6d794d42 BW |
2288 | } |
2289 | ||
6a9c308d DV |
2290 | static int i915_debugfs_create(struct dentry *root, |
2291 | struct drm_minor *minor, | |
2292 | const char *name, | |
2293 | const struct file_operations *fops) | |
07b7ddd9 JB |
2294 | { |
2295 | struct drm_device *dev = minor->dev; | |
2296 | struct dentry *ent; | |
2297 | ||
6a9c308d | 2298 | ent = debugfs_create_file(name, |
07b7ddd9 JB |
2299 | S_IRUGO | S_IWUSR, |
2300 | root, dev, | |
6a9c308d | 2301 | fops); |
07b7ddd9 JB |
2302 | if (IS_ERR(ent)) |
2303 | return PTR_ERR(ent); | |
2304 | ||
6a9c308d | 2305 | return drm_add_fake_info_node(minor, ent, fops); |
07b7ddd9 JB |
2306 | } |
2307 | ||
27c202ad | 2308 | static struct drm_info_list i915_debugfs_list[] = { |
311bd68e | 2309 | {"i915_capabilities", i915_capabilities, 0}, |
73aa808f | 2310 | {"i915_gem_objects", i915_gem_object_info, 0}, |
08c18323 | 2311 | {"i915_gem_gtt", i915_gem_gtt_info, 0}, |
1b50247a | 2312 | {"i915_gem_pinned", i915_gem_gtt_info, 0, (void *) PINNED_LIST}, |
433e12f7 | 2313 | {"i915_gem_active", i915_gem_object_list_info, 0, (void *) ACTIVE_LIST}, |
433e12f7 | 2314 | {"i915_gem_inactive", i915_gem_object_list_info, 0, (void *) INACTIVE_LIST}, |
6d2b8885 | 2315 | {"i915_gem_stolen", i915_gem_stolen_list_info }, |
4e5359cd | 2316 | {"i915_gem_pageflip", i915_gem_pageflip_info, 0}, |
2017263e BG |
2317 | {"i915_gem_request", i915_gem_request_info, 0}, |
2318 | {"i915_gem_seqno", i915_gem_seqno_info, 0}, | |
a6172a80 | 2319 | {"i915_gem_fence_regs", i915_gem_fence_regs_info, 0}, |
2017263e | 2320 | {"i915_gem_interrupt", i915_interrupt_info, 0}, |
1ec14ad3 CW |
2321 | {"i915_gem_hws", i915_hws_info, 0, (void *)RCS}, |
2322 | {"i915_gem_hws_blt", i915_hws_info, 0, (void *)BCS}, | |
2323 | {"i915_gem_hws_bsd", i915_hws_info, 0, (void *)VCS}, | |
9010ebfd | 2324 | {"i915_gem_hws_vebox", i915_hws_info, 0, (void *)VECS}, |
f97108d1 JB |
2325 | {"i915_rstdby_delays", i915_rstdby_delays, 0}, |
2326 | {"i915_cur_delayinfo", i915_cur_delayinfo, 0}, | |
2327 | {"i915_delayfreq_table", i915_delayfreq_table, 0}, | |
2328 | {"i915_inttoext_table", i915_inttoext_table, 0}, | |
2329 | {"i915_drpc_info", i915_drpc_info, 0}, | |
7648fa99 | 2330 | {"i915_emon_status", i915_emon_status, 0}, |
23b2f8bb | 2331 | {"i915_ring_freq_table", i915_ring_freq_table, 0}, |
7648fa99 | 2332 | {"i915_gfxec", i915_gfxec, 0}, |
b5e50c3f | 2333 | {"i915_fbc_status", i915_fbc_status, 0}, |
92d44621 | 2334 | {"i915_ips_status", i915_ips_status, 0}, |
4a9bef37 | 2335 | {"i915_sr_status", i915_sr_status, 0}, |
44834a67 | 2336 | {"i915_opregion", i915_opregion, 0}, |
37811fcc | 2337 | {"i915_gem_framebuffer", i915_gem_framebuffer_info, 0}, |
e76d3630 | 2338 | {"i915_context_status", i915_context_status, 0}, |
6d794d42 | 2339 | {"i915_gen6_forcewake_count", i915_gen6_forcewake_count_info, 0}, |
ea16a3cd | 2340 | {"i915_swizzle_info", i915_swizzle_info, 0}, |
3cf17fc5 | 2341 | {"i915_ppgtt_info", i915_ppgtt_info, 0}, |
57f350b6 | 2342 | {"i915_dpio", i915_dpio_info, 0}, |
63573eb7 | 2343 | {"i915_llc", i915_llc, 0}, |
e91fd8c6 | 2344 | {"i915_edp_psr_status", i915_edp_psr_status, 0}, |
ec013e7f | 2345 | {"i915_energy_uJ", i915_energy_uJ, 0}, |
371db66a | 2346 | {"i915_pc8_status", i915_pc8_status, 0}, |
2017263e | 2347 | }; |
27c202ad | 2348 | #define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list) |
2017263e | 2349 | |
2b4bd0e0 | 2350 | static struct i915_debugfs_files { |
34b9674c DV |
2351 | const char *name; |
2352 | const struct file_operations *fops; | |
2353 | } i915_debugfs_files[] = { | |
2354 | {"i915_wedged", &i915_wedged_fops}, | |
2355 | {"i915_max_freq", &i915_max_freq_fops}, | |
2356 | {"i915_min_freq", &i915_min_freq_fops}, | |
2357 | {"i915_cache_sharing", &i915_cache_sharing_fops}, | |
2358 | {"i915_ring_stop", &i915_ring_stop_fops}, | |
094f9a54 CW |
2359 | {"i915_ring_missed_irq", &i915_ring_missed_irq_fops}, |
2360 | {"i915_ring_test_irq", &i915_ring_test_irq_fops}, | |
34b9674c DV |
2361 | {"i915_gem_drop_caches", &i915_drop_caches_fops}, |
2362 | {"i915_error_state", &i915_error_state_fops}, | |
2363 | {"i915_next_seqno", &i915_next_seqno_fops}, | |
2364 | }; | |
2365 | ||
27c202ad | 2366 | int i915_debugfs_init(struct drm_minor *minor) |
2017263e | 2367 | { |
34b9674c | 2368 | int ret, i; |
f3cd474b | 2369 | |
6d794d42 | 2370 | ret = i915_forcewake_create(minor->debugfs_root, minor); |
358733e9 JB |
2371 | if (ret) |
2372 | return ret; | |
6a9c308d | 2373 | |
34b9674c DV |
2374 | for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) { |
2375 | ret = i915_debugfs_create(minor->debugfs_root, minor, | |
2376 | i915_debugfs_files[i].name, | |
2377 | i915_debugfs_files[i].fops); | |
2378 | if (ret) | |
2379 | return ret; | |
2380 | } | |
40633219 | 2381 | |
27c202ad BG |
2382 | return drm_debugfs_create_files(i915_debugfs_list, |
2383 | I915_DEBUGFS_ENTRIES, | |
2017263e BG |
2384 | minor->debugfs_root, minor); |
2385 | } | |
2386 | ||
27c202ad | 2387 | void i915_debugfs_cleanup(struct drm_minor *minor) |
2017263e | 2388 | { |
34b9674c DV |
2389 | int i; |
2390 | ||
27c202ad BG |
2391 | drm_debugfs_remove_files(i915_debugfs_list, |
2392 | I915_DEBUGFS_ENTRIES, minor); | |
6d794d42 BW |
2393 | drm_debugfs_remove_files((struct drm_info_list *) &i915_forcewake_fops, |
2394 | 1, minor); | |
34b9674c DV |
2395 | for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) { |
2396 | struct drm_info_list *info_list = | |
2397 | (struct drm_info_list *) i915_debugfs_files[i].fops; | |
2398 | ||
2399 | drm_debugfs_remove_files(info_list, 1, minor); | |
2400 | } | |
2017263e BG |
2401 | } |
2402 | ||
2403 | #endif /* CONFIG_DEBUG_FS */ |