Commit | Line | Data |
---|---|---|
2017263e BG |
1 | /* |
2 | * Copyright © 2008 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | * Keith Packard <keithp@keithp.com> | |
26 | * | |
27 | */ | |
28 | ||
29 | #include <linux/seq_file.h> | |
b2c88f5b | 30 | #include <linux/circ_buf.h> |
926321d5 | 31 | #include <linux/ctype.h> |
f3cd474b | 32 | #include <linux/debugfs.h> |
5a0e3ad6 | 33 | #include <linux/slab.h> |
2d1a8a48 | 34 | #include <linux/export.h> |
6d2b8885 | 35 | #include <linux/list_sort.h> |
ec013e7f | 36 | #include <asm/msr-index.h> |
760285e7 | 37 | #include <drm/drmP.h> |
4e5359cd | 38 | #include "intel_drv.h" |
e5c65260 | 39 | #include "intel_ringbuffer.h" |
760285e7 | 40 | #include <drm/i915_drm.h> |
2017263e BG |
41 | #include "i915_drv.h" |
42 | ||
f13d3f73 | 43 | enum { |
69dc4987 | 44 | ACTIVE_LIST, |
f13d3f73 | 45 | INACTIVE_LIST, |
d21d5975 | 46 | PINNED_LIST, |
f13d3f73 | 47 | }; |
2017263e | 48 | |
497666d8 DL |
49 | /* As the drm_debugfs_init() routines are called before dev->dev_private is |
50 | * allocated we need to hook into the minor for release. */ | |
51 | static int | |
52 | drm_add_fake_info_node(struct drm_minor *minor, | |
53 | struct dentry *ent, | |
54 | const void *key) | |
55 | { | |
56 | struct drm_info_node *node; | |
57 | ||
58 | node = kmalloc(sizeof(*node), GFP_KERNEL); | |
59 | if (node == NULL) { | |
60 | debugfs_remove(ent); | |
61 | return -ENOMEM; | |
62 | } | |
63 | ||
64 | node->minor = minor; | |
65 | node->dent = ent; | |
66 | node->info_ent = (void *) key; | |
67 | ||
68 | mutex_lock(&minor->debugfs_lock); | |
69 | list_add(&node->list, &minor->debugfs_list); | |
70 | mutex_unlock(&minor->debugfs_lock); | |
71 | ||
72 | return 0; | |
73 | } | |
74 | ||
70d39fe4 CW |
75 | static int i915_capabilities(struct seq_file *m, void *data) |
76 | { | |
9f25d007 | 77 | struct drm_info_node *node = m->private; |
70d39fe4 CW |
78 | struct drm_device *dev = node->minor->dev; |
79 | const struct intel_device_info *info = INTEL_INFO(dev); | |
80 | ||
81 | seq_printf(m, "gen: %d\n", info->gen); | |
03d00ac5 | 82 | seq_printf(m, "pch: %d\n", INTEL_PCH_TYPE(dev)); |
79fc46df DL |
83 | #define PRINT_FLAG(x) seq_printf(m, #x ": %s\n", yesno(info->x)) |
84 | #define SEP_SEMICOLON ; | |
85 | DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG, SEP_SEMICOLON); | |
86 | #undef PRINT_FLAG | |
87 | #undef SEP_SEMICOLON | |
70d39fe4 CW |
88 | |
89 | return 0; | |
90 | } | |
2017263e | 91 | |
05394f39 | 92 | static const char *get_pin_flag(struct drm_i915_gem_object *obj) |
a6172a80 | 93 | { |
baaa5cfb | 94 | if (obj->pin_display) |
a6172a80 CW |
95 | return "p"; |
96 | else | |
97 | return " "; | |
98 | } | |
99 | ||
05394f39 | 100 | static const char *get_tiling_flag(struct drm_i915_gem_object *obj) |
a6172a80 | 101 | { |
0206e353 AJ |
102 | switch (obj->tiling_mode) { |
103 | default: | |
104 | case I915_TILING_NONE: return " "; | |
105 | case I915_TILING_X: return "X"; | |
106 | case I915_TILING_Y: return "Y"; | |
107 | } | |
a6172a80 CW |
108 | } |
109 | ||
1d693bcc BW |
110 | static inline const char *get_global_flag(struct drm_i915_gem_object *obj) |
111 | { | |
aff43766 | 112 | return i915_gem_obj_to_ggtt(obj) ? "g" : " "; |
1d693bcc BW |
113 | } |
114 | ||
ca1543be TU |
115 | static u64 i915_gem_obj_total_ggtt_size(struct drm_i915_gem_object *obj) |
116 | { | |
117 | u64 size = 0; | |
118 | struct i915_vma *vma; | |
119 | ||
1c7f4bca | 120 | list_for_each_entry(vma, &obj->vma_list, obj_link) { |
596c5923 | 121 | if (vma->is_ggtt && drm_mm_node_allocated(&vma->node)) |
ca1543be TU |
122 | size += vma->node.size; |
123 | } | |
124 | ||
125 | return size; | |
126 | } | |
127 | ||
37811fcc CW |
128 | static void |
129 | describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj) | |
130 | { | |
b4716185 | 131 | struct drm_i915_private *dev_priv = to_i915(obj->base.dev); |
e2f80391 | 132 | struct intel_engine_cs *engine; |
1d693bcc | 133 | struct i915_vma *vma; |
d7f46fc4 | 134 | int pin_count = 0; |
c3232b18 | 135 | enum intel_engine_id id; |
d7f46fc4 | 136 | |
188c1ab7 CW |
137 | lockdep_assert_held(&obj->base.dev->struct_mutex); |
138 | ||
b4716185 | 139 | seq_printf(m, "%pK: %s%s%s%s %8zdKiB %02x %02x [ ", |
37811fcc | 140 | &obj->base, |
481a3d43 | 141 | obj->active ? "*" : " ", |
37811fcc CW |
142 | get_pin_flag(obj), |
143 | get_tiling_flag(obj), | |
1d693bcc | 144 | get_global_flag(obj), |
a05a5862 | 145 | obj->base.size / 1024, |
37811fcc | 146 | obj->base.read_domains, |
b4716185 | 147 | obj->base.write_domain); |
c3232b18 | 148 | for_each_engine_id(engine, dev_priv, id) |
b4716185 | 149 | seq_printf(m, "%x ", |
c3232b18 | 150 | i915_gem_request_get_seqno(obj->last_read_req[id])); |
b4716185 | 151 | seq_printf(m, "] %x %x%s%s%s", |
97b2a6a1 JH |
152 | i915_gem_request_get_seqno(obj->last_write_req), |
153 | i915_gem_request_get_seqno(obj->last_fenced_req), | |
0a4cd7c8 | 154 | i915_cache_level_str(to_i915(obj->base.dev), obj->cache_level), |
37811fcc CW |
155 | obj->dirty ? " dirty" : "", |
156 | obj->madv == I915_MADV_DONTNEED ? " purgeable" : ""); | |
157 | if (obj->base.name) | |
158 | seq_printf(m, " (name: %d)", obj->base.name); | |
1c7f4bca | 159 | list_for_each_entry(vma, &obj->vma_list, obj_link) { |
d7f46fc4 BW |
160 | if (vma->pin_count > 0) |
161 | pin_count++; | |
ba0635ff DC |
162 | } |
163 | seq_printf(m, " (pinned x %d)", pin_count); | |
cc98b413 CW |
164 | if (obj->pin_display) |
165 | seq_printf(m, " (display)"); | |
37811fcc CW |
166 | if (obj->fence_reg != I915_FENCE_REG_NONE) |
167 | seq_printf(m, " (fence: %d)", obj->fence_reg); | |
1c7f4bca | 168 | list_for_each_entry(vma, &obj->vma_list, obj_link) { |
8d2fdc3f | 169 | seq_printf(m, " (%sgtt offset: %08llx, size: %08llx", |
596c5923 | 170 | vma->is_ggtt ? "g" : "pp", |
8d2fdc3f | 171 | vma->node.start, vma->node.size); |
596c5923 CW |
172 | if (vma->is_ggtt) |
173 | seq_printf(m, ", type: %u", vma->ggtt_view.type); | |
174 | seq_puts(m, ")"); | |
1d693bcc | 175 | } |
c1ad11fc | 176 | if (obj->stolen) |
440fd528 | 177 | seq_printf(m, " (stolen: %08llx)", obj->stolen->start); |
30154650 | 178 | if (obj->pin_display || obj->fault_mappable) { |
6299f992 | 179 | char s[3], *t = s; |
30154650 | 180 | if (obj->pin_display) |
6299f992 CW |
181 | *t++ = 'p'; |
182 | if (obj->fault_mappable) | |
183 | *t++ = 'f'; | |
184 | *t = '\0'; | |
185 | seq_printf(m, " (%s mappable)", s); | |
186 | } | |
b4716185 | 187 | if (obj->last_write_req != NULL) |
41c52415 | 188 | seq_printf(m, " (%s)", |
666796da | 189 | i915_gem_request_get_engine(obj->last_write_req)->name); |
d5a81ef1 DV |
190 | if (obj->frontbuffer_bits) |
191 | seq_printf(m, " (frontbuffer: 0x%03x)", obj->frontbuffer_bits); | |
37811fcc CW |
192 | } |
193 | ||
273497e5 | 194 | static void describe_ctx(struct seq_file *m, struct intel_context *ctx) |
3ccfd19d | 195 | { |
ea0c76f8 | 196 | seq_putc(m, ctx->legacy_hw_ctx.initialized ? 'I' : 'i'); |
3ccfd19d BW |
197 | seq_putc(m, ctx->remap_slice ? 'R' : 'r'); |
198 | seq_putc(m, ' '); | |
199 | } | |
200 | ||
433e12f7 | 201 | static int i915_gem_object_list_info(struct seq_file *m, void *data) |
2017263e | 202 | { |
9f25d007 | 203 | struct drm_info_node *node = m->private; |
433e12f7 BG |
204 | uintptr_t list = (uintptr_t) node->info_ent->data; |
205 | struct list_head *head; | |
2017263e | 206 | struct drm_device *dev = node->minor->dev; |
72e96d64 JL |
207 | struct drm_i915_private *dev_priv = to_i915(dev); |
208 | struct i915_ggtt *ggtt = &dev_priv->ggtt; | |
ca191b13 | 209 | struct i915_vma *vma; |
c44ef60e | 210 | u64 total_obj_size, total_gtt_size; |
8f2480fb | 211 | int count, ret; |
de227ef0 CW |
212 | |
213 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
214 | if (ret) | |
215 | return ret; | |
2017263e | 216 | |
ca191b13 | 217 | /* FIXME: the user of this interface might want more than just GGTT */ |
433e12f7 BG |
218 | switch (list) { |
219 | case ACTIVE_LIST: | |
267f0c90 | 220 | seq_puts(m, "Active:\n"); |
72e96d64 | 221 | head = &ggtt->base.active_list; |
433e12f7 BG |
222 | break; |
223 | case INACTIVE_LIST: | |
267f0c90 | 224 | seq_puts(m, "Inactive:\n"); |
72e96d64 | 225 | head = &ggtt->base.inactive_list; |
433e12f7 | 226 | break; |
433e12f7 | 227 | default: |
de227ef0 CW |
228 | mutex_unlock(&dev->struct_mutex); |
229 | return -EINVAL; | |
2017263e | 230 | } |
2017263e | 231 | |
8f2480fb | 232 | total_obj_size = total_gtt_size = count = 0; |
1c7f4bca | 233 | list_for_each_entry(vma, head, vm_link) { |
ca191b13 BW |
234 | seq_printf(m, " "); |
235 | describe_obj(m, vma->obj); | |
236 | seq_printf(m, "\n"); | |
237 | total_obj_size += vma->obj->base.size; | |
238 | total_gtt_size += vma->node.size; | |
8f2480fb | 239 | count++; |
2017263e | 240 | } |
de227ef0 | 241 | mutex_unlock(&dev->struct_mutex); |
5e118f41 | 242 | |
c44ef60e | 243 | seq_printf(m, "Total %d objects, %llu bytes, %llu GTT size\n", |
8f2480fb | 244 | count, total_obj_size, total_gtt_size); |
2017263e BG |
245 | return 0; |
246 | } | |
247 | ||
6d2b8885 CW |
248 | static int obj_rank_by_stolen(void *priv, |
249 | struct list_head *A, struct list_head *B) | |
250 | { | |
251 | struct drm_i915_gem_object *a = | |
b25cb2f8 | 252 | container_of(A, struct drm_i915_gem_object, obj_exec_link); |
6d2b8885 | 253 | struct drm_i915_gem_object *b = |
b25cb2f8 | 254 | container_of(B, struct drm_i915_gem_object, obj_exec_link); |
6d2b8885 | 255 | |
2d05fa16 RV |
256 | if (a->stolen->start < b->stolen->start) |
257 | return -1; | |
258 | if (a->stolen->start > b->stolen->start) | |
259 | return 1; | |
260 | return 0; | |
6d2b8885 CW |
261 | } |
262 | ||
263 | static int i915_gem_stolen_list_info(struct seq_file *m, void *data) | |
264 | { | |
9f25d007 | 265 | struct drm_info_node *node = m->private; |
6d2b8885 CW |
266 | struct drm_device *dev = node->minor->dev; |
267 | struct drm_i915_private *dev_priv = dev->dev_private; | |
268 | struct drm_i915_gem_object *obj; | |
c44ef60e | 269 | u64 total_obj_size, total_gtt_size; |
6d2b8885 CW |
270 | LIST_HEAD(stolen); |
271 | int count, ret; | |
272 | ||
273 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
274 | if (ret) | |
275 | return ret; | |
276 | ||
277 | total_obj_size = total_gtt_size = count = 0; | |
278 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) { | |
279 | if (obj->stolen == NULL) | |
280 | continue; | |
281 | ||
b25cb2f8 | 282 | list_add(&obj->obj_exec_link, &stolen); |
6d2b8885 CW |
283 | |
284 | total_obj_size += obj->base.size; | |
ca1543be | 285 | total_gtt_size += i915_gem_obj_total_ggtt_size(obj); |
6d2b8885 CW |
286 | count++; |
287 | } | |
288 | list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) { | |
289 | if (obj->stolen == NULL) | |
290 | continue; | |
291 | ||
b25cb2f8 | 292 | list_add(&obj->obj_exec_link, &stolen); |
6d2b8885 CW |
293 | |
294 | total_obj_size += obj->base.size; | |
295 | count++; | |
296 | } | |
297 | list_sort(NULL, &stolen, obj_rank_by_stolen); | |
298 | seq_puts(m, "Stolen:\n"); | |
299 | while (!list_empty(&stolen)) { | |
b25cb2f8 | 300 | obj = list_first_entry(&stolen, typeof(*obj), obj_exec_link); |
6d2b8885 CW |
301 | seq_puts(m, " "); |
302 | describe_obj(m, obj); | |
303 | seq_putc(m, '\n'); | |
b25cb2f8 | 304 | list_del_init(&obj->obj_exec_link); |
6d2b8885 CW |
305 | } |
306 | mutex_unlock(&dev->struct_mutex); | |
307 | ||
c44ef60e | 308 | seq_printf(m, "Total %d objects, %llu bytes, %llu GTT size\n", |
6d2b8885 CW |
309 | count, total_obj_size, total_gtt_size); |
310 | return 0; | |
311 | } | |
312 | ||
6299f992 CW |
313 | #define count_objects(list, member) do { \ |
314 | list_for_each_entry(obj, list, member) { \ | |
ca1543be | 315 | size += i915_gem_obj_total_ggtt_size(obj); \ |
6299f992 CW |
316 | ++count; \ |
317 | if (obj->map_and_fenceable) { \ | |
f343c5f6 | 318 | mappable_size += i915_gem_obj_ggtt_size(obj); \ |
6299f992 CW |
319 | ++mappable_count; \ |
320 | } \ | |
321 | } \ | |
0206e353 | 322 | } while (0) |
6299f992 | 323 | |
2db8e9d6 | 324 | struct file_stats { |
6313c204 | 325 | struct drm_i915_file_private *file_priv; |
c44ef60e MK |
326 | unsigned long count; |
327 | u64 total, unbound; | |
328 | u64 global, shared; | |
329 | u64 active, inactive; | |
2db8e9d6 CW |
330 | }; |
331 | ||
332 | static int per_file_stats(int id, void *ptr, void *data) | |
333 | { | |
334 | struct drm_i915_gem_object *obj = ptr; | |
335 | struct file_stats *stats = data; | |
6313c204 | 336 | struct i915_vma *vma; |
2db8e9d6 CW |
337 | |
338 | stats->count++; | |
339 | stats->total += obj->base.size; | |
340 | ||
c67a17e9 CW |
341 | if (obj->base.name || obj->base.dma_buf) |
342 | stats->shared += obj->base.size; | |
343 | ||
6313c204 | 344 | if (USES_FULL_PPGTT(obj->base.dev)) { |
1c7f4bca | 345 | list_for_each_entry(vma, &obj->vma_list, obj_link) { |
6313c204 CW |
346 | struct i915_hw_ppgtt *ppgtt; |
347 | ||
348 | if (!drm_mm_node_allocated(&vma->node)) | |
349 | continue; | |
350 | ||
596c5923 | 351 | if (vma->is_ggtt) { |
6313c204 CW |
352 | stats->global += obj->base.size; |
353 | continue; | |
354 | } | |
355 | ||
356 | ppgtt = container_of(vma->vm, struct i915_hw_ppgtt, base); | |
4d884705 | 357 | if (ppgtt->file_priv != stats->file_priv) |
6313c204 CW |
358 | continue; |
359 | ||
41c52415 | 360 | if (obj->active) /* XXX per-vma statistic */ |
6313c204 CW |
361 | stats->active += obj->base.size; |
362 | else | |
363 | stats->inactive += obj->base.size; | |
364 | ||
365 | return 0; | |
366 | } | |
2db8e9d6 | 367 | } else { |
6313c204 CW |
368 | if (i915_gem_obj_ggtt_bound(obj)) { |
369 | stats->global += obj->base.size; | |
41c52415 | 370 | if (obj->active) |
6313c204 CW |
371 | stats->active += obj->base.size; |
372 | else | |
373 | stats->inactive += obj->base.size; | |
374 | return 0; | |
375 | } | |
2db8e9d6 CW |
376 | } |
377 | ||
6313c204 CW |
378 | if (!list_empty(&obj->global_list)) |
379 | stats->unbound += obj->base.size; | |
380 | ||
2db8e9d6 CW |
381 | return 0; |
382 | } | |
383 | ||
b0da1b79 CW |
384 | #define print_file_stats(m, name, stats) do { \ |
385 | if (stats.count) \ | |
c44ef60e | 386 | seq_printf(m, "%s: %lu objects, %llu bytes (%llu active, %llu inactive, %llu global, %llu shared, %llu unbound)\n", \ |
b0da1b79 CW |
387 | name, \ |
388 | stats.count, \ | |
389 | stats.total, \ | |
390 | stats.active, \ | |
391 | stats.inactive, \ | |
392 | stats.global, \ | |
393 | stats.shared, \ | |
394 | stats.unbound); \ | |
395 | } while (0) | |
493018dc BV |
396 | |
397 | static void print_batch_pool_stats(struct seq_file *m, | |
398 | struct drm_i915_private *dev_priv) | |
399 | { | |
400 | struct drm_i915_gem_object *obj; | |
401 | struct file_stats stats; | |
e2f80391 | 402 | struct intel_engine_cs *engine; |
b4ac5afc | 403 | int j; |
493018dc BV |
404 | |
405 | memset(&stats, 0, sizeof(stats)); | |
406 | ||
b4ac5afc | 407 | for_each_engine(engine, dev_priv) { |
e2f80391 | 408 | for (j = 0; j < ARRAY_SIZE(engine->batch_pool.cache_list); j++) { |
8d9d5744 | 409 | list_for_each_entry(obj, |
e2f80391 | 410 | &engine->batch_pool.cache_list[j], |
8d9d5744 CW |
411 | batch_pool_link) |
412 | per_file_stats(0, obj, &stats); | |
413 | } | |
06fbca71 | 414 | } |
493018dc | 415 | |
b0da1b79 | 416 | print_file_stats(m, "[k]batch pool", stats); |
493018dc BV |
417 | } |
418 | ||
ca191b13 BW |
419 | #define count_vmas(list, member) do { \ |
420 | list_for_each_entry(vma, list, member) { \ | |
ca1543be | 421 | size += i915_gem_obj_total_ggtt_size(vma->obj); \ |
ca191b13 BW |
422 | ++count; \ |
423 | if (vma->obj->map_and_fenceable) { \ | |
424 | mappable_size += i915_gem_obj_ggtt_size(vma->obj); \ | |
425 | ++mappable_count; \ | |
426 | } \ | |
427 | } \ | |
428 | } while (0) | |
429 | ||
430 | static int i915_gem_object_info(struct seq_file *m, void* data) | |
73aa808f | 431 | { |
9f25d007 | 432 | struct drm_info_node *node = m->private; |
73aa808f | 433 | struct drm_device *dev = node->minor->dev; |
72e96d64 JL |
434 | struct drm_i915_private *dev_priv = to_i915(dev); |
435 | struct i915_ggtt *ggtt = &dev_priv->ggtt; | |
b7abb714 | 436 | u32 count, mappable_count, purgeable_count; |
c44ef60e | 437 | u64 size, mappable_size, purgeable_size; |
6299f992 | 438 | struct drm_i915_gem_object *obj; |
2db8e9d6 | 439 | struct drm_file *file; |
ca191b13 | 440 | struct i915_vma *vma; |
73aa808f CW |
441 | int ret; |
442 | ||
443 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
444 | if (ret) | |
445 | return ret; | |
446 | ||
6299f992 CW |
447 | seq_printf(m, "%u objects, %zu bytes\n", |
448 | dev_priv->mm.object_count, | |
449 | dev_priv->mm.object_memory); | |
450 | ||
451 | size = count = mappable_size = mappable_count = 0; | |
35c20a60 | 452 | count_objects(&dev_priv->mm.bound_list, global_list); |
c44ef60e | 453 | seq_printf(m, "%u [%u] objects, %llu [%llu] bytes in gtt\n", |
6299f992 CW |
454 | count, mappable_count, size, mappable_size); |
455 | ||
456 | size = count = mappable_size = mappable_count = 0; | |
72e96d64 | 457 | count_vmas(&ggtt->base.active_list, vm_link); |
c44ef60e | 458 | seq_printf(m, " %u [%u] active objects, %llu [%llu] bytes\n", |
6299f992 CW |
459 | count, mappable_count, size, mappable_size); |
460 | ||
6299f992 | 461 | size = count = mappable_size = mappable_count = 0; |
72e96d64 | 462 | count_vmas(&ggtt->base.inactive_list, vm_link); |
c44ef60e | 463 | seq_printf(m, " %u [%u] inactive objects, %llu [%llu] bytes\n", |
6299f992 CW |
464 | count, mappable_count, size, mappable_size); |
465 | ||
b7abb714 | 466 | size = count = purgeable_size = purgeable_count = 0; |
35c20a60 | 467 | list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) { |
6c085a72 | 468 | size += obj->base.size, ++count; |
b7abb714 CW |
469 | if (obj->madv == I915_MADV_DONTNEED) |
470 | purgeable_size += obj->base.size, ++purgeable_count; | |
471 | } | |
c44ef60e | 472 | seq_printf(m, "%u unbound objects, %llu bytes\n", count, size); |
6c085a72 | 473 | |
6299f992 | 474 | size = count = mappable_size = mappable_count = 0; |
35c20a60 | 475 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) { |
6299f992 | 476 | if (obj->fault_mappable) { |
f343c5f6 | 477 | size += i915_gem_obj_ggtt_size(obj); |
6299f992 CW |
478 | ++count; |
479 | } | |
30154650 | 480 | if (obj->pin_display) { |
f343c5f6 | 481 | mappable_size += i915_gem_obj_ggtt_size(obj); |
6299f992 CW |
482 | ++mappable_count; |
483 | } | |
b7abb714 CW |
484 | if (obj->madv == I915_MADV_DONTNEED) { |
485 | purgeable_size += obj->base.size; | |
486 | ++purgeable_count; | |
487 | } | |
6299f992 | 488 | } |
c44ef60e | 489 | seq_printf(m, "%u purgeable objects, %llu bytes\n", |
b7abb714 | 490 | purgeable_count, purgeable_size); |
c44ef60e | 491 | seq_printf(m, "%u pinned mappable objects, %llu bytes\n", |
6299f992 | 492 | mappable_count, mappable_size); |
c44ef60e | 493 | seq_printf(m, "%u fault mappable objects, %llu bytes\n", |
6299f992 CW |
494 | count, size); |
495 | ||
c44ef60e | 496 | seq_printf(m, "%llu [%llu] gtt total\n", |
72e96d64 | 497 | ggtt->base.total, ggtt->mappable_end - ggtt->base.start); |
73aa808f | 498 | |
493018dc BV |
499 | seq_putc(m, '\n'); |
500 | print_batch_pool_stats(m, dev_priv); | |
2db8e9d6 CW |
501 | list_for_each_entry_reverse(file, &dev->filelist, lhead) { |
502 | struct file_stats stats; | |
3ec2f427 | 503 | struct task_struct *task; |
2db8e9d6 CW |
504 | |
505 | memset(&stats, 0, sizeof(stats)); | |
6313c204 | 506 | stats.file_priv = file->driver_priv; |
5b5ffff0 | 507 | spin_lock(&file->table_lock); |
2db8e9d6 | 508 | idr_for_each(&file->object_idr, per_file_stats, &stats); |
5b5ffff0 | 509 | spin_unlock(&file->table_lock); |
3ec2f427 TH |
510 | /* |
511 | * Although we have a valid reference on file->pid, that does | |
512 | * not guarantee that the task_struct who called get_pid() is | |
513 | * still alive (e.g. get_pid(current) => fork() => exit()). | |
514 | * Therefore, we need to protect this ->comm access using RCU. | |
515 | */ | |
516 | rcu_read_lock(); | |
517 | task = pid_task(file->pid, PIDTYPE_PID); | |
493018dc | 518 | print_file_stats(m, task ? task->comm : "<unknown>", stats); |
3ec2f427 | 519 | rcu_read_unlock(); |
2db8e9d6 CW |
520 | } |
521 | ||
73aa808f CW |
522 | mutex_unlock(&dev->struct_mutex); |
523 | ||
524 | return 0; | |
525 | } | |
526 | ||
aee56cff | 527 | static int i915_gem_gtt_info(struct seq_file *m, void *data) |
08c18323 | 528 | { |
9f25d007 | 529 | struct drm_info_node *node = m->private; |
08c18323 | 530 | struct drm_device *dev = node->minor->dev; |
1b50247a | 531 | uintptr_t list = (uintptr_t) node->info_ent->data; |
08c18323 CW |
532 | struct drm_i915_private *dev_priv = dev->dev_private; |
533 | struct drm_i915_gem_object *obj; | |
c44ef60e | 534 | u64 total_obj_size, total_gtt_size; |
08c18323 CW |
535 | int count, ret; |
536 | ||
537 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
538 | if (ret) | |
539 | return ret; | |
540 | ||
541 | total_obj_size = total_gtt_size = count = 0; | |
35c20a60 | 542 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) { |
d7f46fc4 | 543 | if (list == PINNED_LIST && !i915_gem_obj_is_pinned(obj)) |
1b50247a CW |
544 | continue; |
545 | ||
267f0c90 | 546 | seq_puts(m, " "); |
08c18323 | 547 | describe_obj(m, obj); |
267f0c90 | 548 | seq_putc(m, '\n'); |
08c18323 | 549 | total_obj_size += obj->base.size; |
ca1543be | 550 | total_gtt_size += i915_gem_obj_total_ggtt_size(obj); |
08c18323 CW |
551 | count++; |
552 | } | |
553 | ||
554 | mutex_unlock(&dev->struct_mutex); | |
555 | ||
c44ef60e | 556 | seq_printf(m, "Total %d objects, %llu bytes, %llu GTT size\n", |
08c18323 CW |
557 | count, total_obj_size, total_gtt_size); |
558 | ||
559 | return 0; | |
560 | } | |
561 | ||
4e5359cd SF |
562 | static int i915_gem_pageflip_info(struct seq_file *m, void *data) |
563 | { | |
9f25d007 | 564 | struct drm_info_node *node = m->private; |
4e5359cd | 565 | struct drm_device *dev = node->minor->dev; |
d6bbafa1 | 566 | struct drm_i915_private *dev_priv = dev->dev_private; |
4e5359cd | 567 | struct intel_crtc *crtc; |
8a270ebf DV |
568 | int ret; |
569 | ||
570 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
571 | if (ret) | |
572 | return ret; | |
4e5359cd | 573 | |
d3fcc808 | 574 | for_each_intel_crtc(dev, crtc) { |
9db4a9c7 JB |
575 | const char pipe = pipe_name(crtc->pipe); |
576 | const char plane = plane_name(crtc->plane); | |
4e5359cd SF |
577 | struct intel_unpin_work *work; |
578 | ||
5e2d7afc | 579 | spin_lock_irq(&dev->event_lock); |
4e5359cd SF |
580 | work = crtc->unpin_work; |
581 | if (work == NULL) { | |
9db4a9c7 | 582 | seq_printf(m, "No flip due on pipe %c (plane %c)\n", |
4e5359cd SF |
583 | pipe, plane); |
584 | } else { | |
d6bbafa1 CW |
585 | u32 addr; |
586 | ||
e7d841ca | 587 | if (atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) { |
9db4a9c7 | 588 | seq_printf(m, "Flip queued on pipe %c (plane %c)\n", |
4e5359cd SF |
589 | pipe, plane); |
590 | } else { | |
9db4a9c7 | 591 | seq_printf(m, "Flip pending (waiting for vsync) on pipe %c (plane %c)\n", |
4e5359cd SF |
592 | pipe, plane); |
593 | } | |
3a8a946e | 594 | if (work->flip_queued_req) { |
666796da | 595 | struct intel_engine_cs *engine = i915_gem_request_get_engine(work->flip_queued_req); |
3a8a946e | 596 | |
20e28fba | 597 | seq_printf(m, "Flip queued on %s at seqno %x, next seqno %x [current breadcrumb %x], completed? %d\n", |
e2f80391 | 598 | engine->name, |
f06cc1b9 | 599 | i915_gem_request_get_seqno(work->flip_queued_req), |
d6bbafa1 | 600 | dev_priv->next_seqno, |
c04e0f3b | 601 | engine->get_seqno(engine), |
1b5a433a | 602 | i915_gem_request_completed(work->flip_queued_req, true)); |
d6bbafa1 CW |
603 | } else |
604 | seq_printf(m, "Flip not associated with any ring\n"); | |
605 | seq_printf(m, "Flip queued on frame %d, (was ready on frame %d), now %d\n", | |
606 | work->flip_queued_vblank, | |
607 | work->flip_ready_vblank, | |
1e3feefd | 608 | drm_crtc_vblank_count(&crtc->base)); |
4e5359cd | 609 | if (work->enable_stall_check) |
267f0c90 | 610 | seq_puts(m, "Stall check enabled, "); |
4e5359cd | 611 | else |
267f0c90 | 612 | seq_puts(m, "Stall check waiting for page flip ioctl, "); |
e7d841ca | 613 | seq_printf(m, "%d prepares\n", atomic_read(&work->pending)); |
4e5359cd | 614 | |
d6bbafa1 CW |
615 | if (INTEL_INFO(dev)->gen >= 4) |
616 | addr = I915_HI_DISPBASE(I915_READ(DSPSURF(crtc->plane))); | |
617 | else | |
618 | addr = I915_READ(DSPADDR(crtc->plane)); | |
619 | seq_printf(m, "Current scanout address 0x%08x\n", addr); | |
620 | ||
4e5359cd | 621 | if (work->pending_flip_obj) { |
d6bbafa1 CW |
622 | seq_printf(m, "New framebuffer address 0x%08lx\n", (long)work->gtt_offset); |
623 | seq_printf(m, "MMIO update completed? %d\n", addr == work->gtt_offset); | |
4e5359cd SF |
624 | } |
625 | } | |
5e2d7afc | 626 | spin_unlock_irq(&dev->event_lock); |
4e5359cd SF |
627 | } |
628 | ||
8a270ebf DV |
629 | mutex_unlock(&dev->struct_mutex); |
630 | ||
4e5359cd SF |
631 | return 0; |
632 | } | |
633 | ||
493018dc BV |
634 | static int i915_gem_batch_pool_info(struct seq_file *m, void *data) |
635 | { | |
636 | struct drm_info_node *node = m->private; | |
637 | struct drm_device *dev = node->minor->dev; | |
638 | struct drm_i915_private *dev_priv = dev->dev_private; | |
639 | struct drm_i915_gem_object *obj; | |
e2f80391 | 640 | struct intel_engine_cs *engine; |
8d9d5744 | 641 | int total = 0; |
b4ac5afc | 642 | int ret, j; |
493018dc BV |
643 | |
644 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
645 | if (ret) | |
646 | return ret; | |
647 | ||
b4ac5afc | 648 | for_each_engine(engine, dev_priv) { |
e2f80391 | 649 | for (j = 0; j < ARRAY_SIZE(engine->batch_pool.cache_list); j++) { |
8d9d5744 CW |
650 | int count; |
651 | ||
652 | count = 0; | |
653 | list_for_each_entry(obj, | |
e2f80391 | 654 | &engine->batch_pool.cache_list[j], |
8d9d5744 CW |
655 | batch_pool_link) |
656 | count++; | |
657 | seq_printf(m, "%s cache[%d]: %d objects\n", | |
e2f80391 | 658 | engine->name, j, count); |
8d9d5744 CW |
659 | |
660 | list_for_each_entry(obj, | |
e2f80391 | 661 | &engine->batch_pool.cache_list[j], |
8d9d5744 CW |
662 | batch_pool_link) { |
663 | seq_puts(m, " "); | |
664 | describe_obj(m, obj); | |
665 | seq_putc(m, '\n'); | |
666 | } | |
667 | ||
668 | total += count; | |
06fbca71 | 669 | } |
493018dc BV |
670 | } |
671 | ||
8d9d5744 | 672 | seq_printf(m, "total: %d\n", total); |
493018dc BV |
673 | |
674 | mutex_unlock(&dev->struct_mutex); | |
675 | ||
676 | return 0; | |
677 | } | |
678 | ||
2017263e BG |
679 | static int i915_gem_request_info(struct seq_file *m, void *data) |
680 | { | |
9f25d007 | 681 | struct drm_info_node *node = m->private; |
2017263e | 682 | struct drm_device *dev = node->minor->dev; |
e277a1f8 | 683 | struct drm_i915_private *dev_priv = dev->dev_private; |
e2f80391 | 684 | struct intel_engine_cs *engine; |
eed29a5b | 685 | struct drm_i915_gem_request *req; |
b4ac5afc | 686 | int ret, any; |
de227ef0 CW |
687 | |
688 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
689 | if (ret) | |
690 | return ret; | |
2017263e | 691 | |
2d1070b2 | 692 | any = 0; |
b4ac5afc | 693 | for_each_engine(engine, dev_priv) { |
2d1070b2 CW |
694 | int count; |
695 | ||
696 | count = 0; | |
e2f80391 | 697 | list_for_each_entry(req, &engine->request_list, list) |
2d1070b2 CW |
698 | count++; |
699 | if (count == 0) | |
a2c7f6fd CW |
700 | continue; |
701 | ||
e2f80391 TU |
702 | seq_printf(m, "%s requests: %d\n", engine->name, count); |
703 | list_for_each_entry(req, &engine->request_list, list) { | |
2d1070b2 CW |
704 | struct task_struct *task; |
705 | ||
706 | rcu_read_lock(); | |
707 | task = NULL; | |
eed29a5b DV |
708 | if (req->pid) |
709 | task = pid_task(req->pid, PIDTYPE_PID); | |
2d1070b2 | 710 | seq_printf(m, " %x @ %d: %s [%d]\n", |
eed29a5b DV |
711 | req->seqno, |
712 | (int) (jiffies - req->emitted_jiffies), | |
2d1070b2 CW |
713 | task ? task->comm : "<unknown>", |
714 | task ? task->pid : -1); | |
715 | rcu_read_unlock(); | |
c2c347a9 | 716 | } |
2d1070b2 CW |
717 | |
718 | any++; | |
2017263e | 719 | } |
de227ef0 CW |
720 | mutex_unlock(&dev->struct_mutex); |
721 | ||
2d1070b2 | 722 | if (any == 0) |
267f0c90 | 723 | seq_puts(m, "No requests\n"); |
c2c347a9 | 724 | |
2017263e BG |
725 | return 0; |
726 | } | |
727 | ||
b2223497 | 728 | static void i915_ring_seqno_info(struct seq_file *m, |
0bc40be8 | 729 | struct intel_engine_cs *engine) |
b2223497 | 730 | { |
12471ba8 CW |
731 | seq_printf(m, "Current sequence (%s): %x\n", |
732 | engine->name, engine->get_seqno(engine)); | |
733 | seq_printf(m, "Current user interrupts (%s): %x\n", | |
734 | engine->name, READ_ONCE(engine->user_interrupts)); | |
b2223497 CW |
735 | } |
736 | ||
2017263e BG |
737 | static int i915_gem_seqno_info(struct seq_file *m, void *data) |
738 | { | |
9f25d007 | 739 | struct drm_info_node *node = m->private; |
2017263e | 740 | struct drm_device *dev = node->minor->dev; |
e277a1f8 | 741 | struct drm_i915_private *dev_priv = dev->dev_private; |
e2f80391 | 742 | struct intel_engine_cs *engine; |
b4ac5afc | 743 | int ret; |
de227ef0 CW |
744 | |
745 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
746 | if (ret) | |
747 | return ret; | |
c8c8fb33 | 748 | intel_runtime_pm_get(dev_priv); |
2017263e | 749 | |
b4ac5afc | 750 | for_each_engine(engine, dev_priv) |
e2f80391 | 751 | i915_ring_seqno_info(m, engine); |
de227ef0 | 752 | |
c8c8fb33 | 753 | intel_runtime_pm_put(dev_priv); |
de227ef0 CW |
754 | mutex_unlock(&dev->struct_mutex); |
755 | ||
2017263e BG |
756 | return 0; |
757 | } | |
758 | ||
759 | ||
760 | static int i915_interrupt_info(struct seq_file *m, void *data) | |
761 | { | |
9f25d007 | 762 | struct drm_info_node *node = m->private; |
2017263e | 763 | struct drm_device *dev = node->minor->dev; |
e277a1f8 | 764 | struct drm_i915_private *dev_priv = dev->dev_private; |
e2f80391 | 765 | struct intel_engine_cs *engine; |
9db4a9c7 | 766 | int ret, i, pipe; |
de227ef0 CW |
767 | |
768 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
769 | if (ret) | |
770 | return ret; | |
c8c8fb33 | 771 | intel_runtime_pm_get(dev_priv); |
2017263e | 772 | |
74e1ca8c | 773 | if (IS_CHERRYVIEW(dev)) { |
74e1ca8c VS |
774 | seq_printf(m, "Master Interrupt Control:\t%08x\n", |
775 | I915_READ(GEN8_MASTER_IRQ)); | |
776 | ||
777 | seq_printf(m, "Display IER:\t%08x\n", | |
778 | I915_READ(VLV_IER)); | |
779 | seq_printf(m, "Display IIR:\t%08x\n", | |
780 | I915_READ(VLV_IIR)); | |
781 | seq_printf(m, "Display IIR_RW:\t%08x\n", | |
782 | I915_READ(VLV_IIR_RW)); | |
783 | seq_printf(m, "Display IMR:\t%08x\n", | |
784 | I915_READ(VLV_IMR)); | |
055e393f | 785 | for_each_pipe(dev_priv, pipe) |
74e1ca8c VS |
786 | seq_printf(m, "Pipe %c stat:\t%08x\n", |
787 | pipe_name(pipe), | |
788 | I915_READ(PIPESTAT(pipe))); | |
789 | ||
790 | seq_printf(m, "Port hotplug:\t%08x\n", | |
791 | I915_READ(PORT_HOTPLUG_EN)); | |
792 | seq_printf(m, "DPFLIPSTAT:\t%08x\n", | |
793 | I915_READ(VLV_DPFLIPSTAT)); | |
794 | seq_printf(m, "DPINVGTT:\t%08x\n", | |
795 | I915_READ(DPINVGTT)); | |
796 | ||
797 | for (i = 0; i < 4; i++) { | |
798 | seq_printf(m, "GT Interrupt IMR %d:\t%08x\n", | |
799 | i, I915_READ(GEN8_GT_IMR(i))); | |
800 | seq_printf(m, "GT Interrupt IIR %d:\t%08x\n", | |
801 | i, I915_READ(GEN8_GT_IIR(i))); | |
802 | seq_printf(m, "GT Interrupt IER %d:\t%08x\n", | |
803 | i, I915_READ(GEN8_GT_IER(i))); | |
804 | } | |
805 | ||
806 | seq_printf(m, "PCU interrupt mask:\t%08x\n", | |
807 | I915_READ(GEN8_PCU_IMR)); | |
808 | seq_printf(m, "PCU interrupt identity:\t%08x\n", | |
809 | I915_READ(GEN8_PCU_IIR)); | |
810 | seq_printf(m, "PCU interrupt enable:\t%08x\n", | |
811 | I915_READ(GEN8_PCU_IER)); | |
812 | } else if (INTEL_INFO(dev)->gen >= 8) { | |
a123f157 BW |
813 | seq_printf(m, "Master Interrupt Control:\t%08x\n", |
814 | I915_READ(GEN8_MASTER_IRQ)); | |
815 | ||
816 | for (i = 0; i < 4; i++) { | |
817 | seq_printf(m, "GT Interrupt IMR %d:\t%08x\n", | |
818 | i, I915_READ(GEN8_GT_IMR(i))); | |
819 | seq_printf(m, "GT Interrupt IIR %d:\t%08x\n", | |
820 | i, I915_READ(GEN8_GT_IIR(i))); | |
821 | seq_printf(m, "GT Interrupt IER %d:\t%08x\n", | |
822 | i, I915_READ(GEN8_GT_IER(i))); | |
823 | } | |
824 | ||
055e393f | 825 | for_each_pipe(dev_priv, pipe) { |
e129649b ID |
826 | enum intel_display_power_domain power_domain; |
827 | ||
828 | power_domain = POWER_DOMAIN_PIPE(pipe); | |
829 | if (!intel_display_power_get_if_enabled(dev_priv, | |
830 | power_domain)) { | |
22c59960 PZ |
831 | seq_printf(m, "Pipe %c power disabled\n", |
832 | pipe_name(pipe)); | |
833 | continue; | |
834 | } | |
a123f157 | 835 | seq_printf(m, "Pipe %c IMR:\t%08x\n", |
07d27e20 DL |
836 | pipe_name(pipe), |
837 | I915_READ(GEN8_DE_PIPE_IMR(pipe))); | |
a123f157 | 838 | seq_printf(m, "Pipe %c IIR:\t%08x\n", |
07d27e20 DL |
839 | pipe_name(pipe), |
840 | I915_READ(GEN8_DE_PIPE_IIR(pipe))); | |
a123f157 | 841 | seq_printf(m, "Pipe %c IER:\t%08x\n", |
07d27e20 DL |
842 | pipe_name(pipe), |
843 | I915_READ(GEN8_DE_PIPE_IER(pipe))); | |
e129649b ID |
844 | |
845 | intel_display_power_put(dev_priv, power_domain); | |
a123f157 BW |
846 | } |
847 | ||
848 | seq_printf(m, "Display Engine port interrupt mask:\t%08x\n", | |
849 | I915_READ(GEN8_DE_PORT_IMR)); | |
850 | seq_printf(m, "Display Engine port interrupt identity:\t%08x\n", | |
851 | I915_READ(GEN8_DE_PORT_IIR)); | |
852 | seq_printf(m, "Display Engine port interrupt enable:\t%08x\n", | |
853 | I915_READ(GEN8_DE_PORT_IER)); | |
854 | ||
855 | seq_printf(m, "Display Engine misc interrupt mask:\t%08x\n", | |
856 | I915_READ(GEN8_DE_MISC_IMR)); | |
857 | seq_printf(m, "Display Engine misc interrupt identity:\t%08x\n", | |
858 | I915_READ(GEN8_DE_MISC_IIR)); | |
859 | seq_printf(m, "Display Engine misc interrupt enable:\t%08x\n", | |
860 | I915_READ(GEN8_DE_MISC_IER)); | |
861 | ||
862 | seq_printf(m, "PCU interrupt mask:\t%08x\n", | |
863 | I915_READ(GEN8_PCU_IMR)); | |
864 | seq_printf(m, "PCU interrupt identity:\t%08x\n", | |
865 | I915_READ(GEN8_PCU_IIR)); | |
866 | seq_printf(m, "PCU interrupt enable:\t%08x\n", | |
867 | I915_READ(GEN8_PCU_IER)); | |
868 | } else if (IS_VALLEYVIEW(dev)) { | |
7e231dbe JB |
869 | seq_printf(m, "Display IER:\t%08x\n", |
870 | I915_READ(VLV_IER)); | |
871 | seq_printf(m, "Display IIR:\t%08x\n", | |
872 | I915_READ(VLV_IIR)); | |
873 | seq_printf(m, "Display IIR_RW:\t%08x\n", | |
874 | I915_READ(VLV_IIR_RW)); | |
875 | seq_printf(m, "Display IMR:\t%08x\n", | |
876 | I915_READ(VLV_IMR)); | |
055e393f | 877 | for_each_pipe(dev_priv, pipe) |
7e231dbe JB |
878 | seq_printf(m, "Pipe %c stat:\t%08x\n", |
879 | pipe_name(pipe), | |
880 | I915_READ(PIPESTAT(pipe))); | |
881 | ||
882 | seq_printf(m, "Master IER:\t%08x\n", | |
883 | I915_READ(VLV_MASTER_IER)); | |
884 | ||
885 | seq_printf(m, "Render IER:\t%08x\n", | |
886 | I915_READ(GTIER)); | |
887 | seq_printf(m, "Render IIR:\t%08x\n", | |
888 | I915_READ(GTIIR)); | |
889 | seq_printf(m, "Render IMR:\t%08x\n", | |
890 | I915_READ(GTIMR)); | |
891 | ||
892 | seq_printf(m, "PM IER:\t\t%08x\n", | |
893 | I915_READ(GEN6_PMIER)); | |
894 | seq_printf(m, "PM IIR:\t\t%08x\n", | |
895 | I915_READ(GEN6_PMIIR)); | |
896 | seq_printf(m, "PM IMR:\t\t%08x\n", | |
897 | I915_READ(GEN6_PMIMR)); | |
898 | ||
899 | seq_printf(m, "Port hotplug:\t%08x\n", | |
900 | I915_READ(PORT_HOTPLUG_EN)); | |
901 | seq_printf(m, "DPFLIPSTAT:\t%08x\n", | |
902 | I915_READ(VLV_DPFLIPSTAT)); | |
903 | seq_printf(m, "DPINVGTT:\t%08x\n", | |
904 | I915_READ(DPINVGTT)); | |
905 | ||
906 | } else if (!HAS_PCH_SPLIT(dev)) { | |
5f6a1695 ZW |
907 | seq_printf(m, "Interrupt enable: %08x\n", |
908 | I915_READ(IER)); | |
909 | seq_printf(m, "Interrupt identity: %08x\n", | |
910 | I915_READ(IIR)); | |
911 | seq_printf(m, "Interrupt mask: %08x\n", | |
912 | I915_READ(IMR)); | |
055e393f | 913 | for_each_pipe(dev_priv, pipe) |
9db4a9c7 JB |
914 | seq_printf(m, "Pipe %c stat: %08x\n", |
915 | pipe_name(pipe), | |
916 | I915_READ(PIPESTAT(pipe))); | |
5f6a1695 ZW |
917 | } else { |
918 | seq_printf(m, "North Display Interrupt enable: %08x\n", | |
919 | I915_READ(DEIER)); | |
920 | seq_printf(m, "North Display Interrupt identity: %08x\n", | |
921 | I915_READ(DEIIR)); | |
922 | seq_printf(m, "North Display Interrupt mask: %08x\n", | |
923 | I915_READ(DEIMR)); | |
924 | seq_printf(m, "South Display Interrupt enable: %08x\n", | |
925 | I915_READ(SDEIER)); | |
926 | seq_printf(m, "South Display Interrupt identity: %08x\n", | |
927 | I915_READ(SDEIIR)); | |
928 | seq_printf(m, "South Display Interrupt mask: %08x\n", | |
929 | I915_READ(SDEIMR)); | |
930 | seq_printf(m, "Graphics Interrupt enable: %08x\n", | |
931 | I915_READ(GTIER)); | |
932 | seq_printf(m, "Graphics Interrupt identity: %08x\n", | |
933 | I915_READ(GTIIR)); | |
934 | seq_printf(m, "Graphics Interrupt mask: %08x\n", | |
935 | I915_READ(GTIMR)); | |
936 | } | |
b4ac5afc | 937 | for_each_engine(engine, dev_priv) { |
a123f157 | 938 | if (INTEL_INFO(dev)->gen >= 6) { |
a2c7f6fd CW |
939 | seq_printf(m, |
940 | "Graphics Interrupt mask (%s): %08x\n", | |
e2f80391 | 941 | engine->name, I915_READ_IMR(engine)); |
9862e600 | 942 | } |
e2f80391 | 943 | i915_ring_seqno_info(m, engine); |
9862e600 | 944 | } |
c8c8fb33 | 945 | intel_runtime_pm_put(dev_priv); |
de227ef0 CW |
946 | mutex_unlock(&dev->struct_mutex); |
947 | ||
2017263e BG |
948 | return 0; |
949 | } | |
950 | ||
a6172a80 CW |
951 | static int i915_gem_fence_regs_info(struct seq_file *m, void *data) |
952 | { | |
9f25d007 | 953 | struct drm_info_node *node = m->private; |
a6172a80 | 954 | struct drm_device *dev = node->minor->dev; |
e277a1f8 | 955 | struct drm_i915_private *dev_priv = dev->dev_private; |
de227ef0 CW |
956 | int i, ret; |
957 | ||
958 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
959 | if (ret) | |
960 | return ret; | |
a6172a80 | 961 | |
a6172a80 CW |
962 | seq_printf(m, "Total fences = %d\n", dev_priv->num_fence_regs); |
963 | for (i = 0; i < dev_priv->num_fence_regs; i++) { | |
05394f39 | 964 | struct drm_i915_gem_object *obj = dev_priv->fence_regs[i].obj; |
a6172a80 | 965 | |
6c085a72 CW |
966 | seq_printf(m, "Fence %d, pin count = %d, object = ", |
967 | i, dev_priv->fence_regs[i].pin_count); | |
c2c347a9 | 968 | if (obj == NULL) |
267f0c90 | 969 | seq_puts(m, "unused"); |
c2c347a9 | 970 | else |
05394f39 | 971 | describe_obj(m, obj); |
267f0c90 | 972 | seq_putc(m, '\n'); |
a6172a80 CW |
973 | } |
974 | ||
05394f39 | 975 | mutex_unlock(&dev->struct_mutex); |
a6172a80 CW |
976 | return 0; |
977 | } | |
978 | ||
2017263e BG |
979 | static int i915_hws_info(struct seq_file *m, void *data) |
980 | { | |
9f25d007 | 981 | struct drm_info_node *node = m->private; |
2017263e | 982 | struct drm_device *dev = node->minor->dev; |
e277a1f8 | 983 | struct drm_i915_private *dev_priv = dev->dev_private; |
e2f80391 | 984 | struct intel_engine_cs *engine; |
1a240d4d | 985 | const u32 *hws; |
4066c0ae CW |
986 | int i; |
987 | ||
4a570db5 | 988 | engine = &dev_priv->engine[(uintptr_t)node->info_ent->data]; |
e2f80391 | 989 | hws = engine->status_page.page_addr; |
2017263e BG |
990 | if (hws == NULL) |
991 | return 0; | |
992 | ||
993 | for (i = 0; i < 4096 / sizeof(u32) / 4; i += 4) { | |
994 | seq_printf(m, "0x%08x: 0x%08x 0x%08x 0x%08x 0x%08x\n", | |
995 | i * 4, | |
996 | hws[i], hws[i + 1], hws[i + 2], hws[i + 3]); | |
997 | } | |
998 | return 0; | |
999 | } | |
1000 | ||
d5442303 DV |
1001 | static ssize_t |
1002 | i915_error_state_write(struct file *filp, | |
1003 | const char __user *ubuf, | |
1004 | size_t cnt, | |
1005 | loff_t *ppos) | |
1006 | { | |
edc3d884 | 1007 | struct i915_error_state_file_priv *error_priv = filp->private_data; |
d5442303 | 1008 | struct drm_device *dev = error_priv->dev; |
22bcfc6a | 1009 | int ret; |
d5442303 DV |
1010 | |
1011 | DRM_DEBUG_DRIVER("Resetting error state\n"); | |
1012 | ||
22bcfc6a DV |
1013 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
1014 | if (ret) | |
1015 | return ret; | |
1016 | ||
d5442303 DV |
1017 | i915_destroy_error_state(dev); |
1018 | mutex_unlock(&dev->struct_mutex); | |
1019 | ||
1020 | return cnt; | |
1021 | } | |
1022 | ||
1023 | static int i915_error_state_open(struct inode *inode, struct file *file) | |
1024 | { | |
1025 | struct drm_device *dev = inode->i_private; | |
d5442303 | 1026 | struct i915_error_state_file_priv *error_priv; |
d5442303 DV |
1027 | |
1028 | error_priv = kzalloc(sizeof(*error_priv), GFP_KERNEL); | |
1029 | if (!error_priv) | |
1030 | return -ENOMEM; | |
1031 | ||
1032 | error_priv->dev = dev; | |
1033 | ||
95d5bfb3 | 1034 | i915_error_state_get(dev, error_priv); |
d5442303 | 1035 | |
edc3d884 MK |
1036 | file->private_data = error_priv; |
1037 | ||
1038 | return 0; | |
d5442303 DV |
1039 | } |
1040 | ||
1041 | static int i915_error_state_release(struct inode *inode, struct file *file) | |
1042 | { | |
edc3d884 | 1043 | struct i915_error_state_file_priv *error_priv = file->private_data; |
d5442303 | 1044 | |
95d5bfb3 | 1045 | i915_error_state_put(error_priv); |
d5442303 DV |
1046 | kfree(error_priv); |
1047 | ||
edc3d884 MK |
1048 | return 0; |
1049 | } | |
1050 | ||
4dc955f7 MK |
1051 | static ssize_t i915_error_state_read(struct file *file, char __user *userbuf, |
1052 | size_t count, loff_t *pos) | |
1053 | { | |
1054 | struct i915_error_state_file_priv *error_priv = file->private_data; | |
1055 | struct drm_i915_error_state_buf error_str; | |
1056 | loff_t tmp_pos = 0; | |
1057 | ssize_t ret_count = 0; | |
1058 | int ret; | |
1059 | ||
0a4cd7c8 | 1060 | ret = i915_error_state_buf_init(&error_str, to_i915(error_priv->dev), count, *pos); |
4dc955f7 MK |
1061 | if (ret) |
1062 | return ret; | |
edc3d884 | 1063 | |
fc16b48b | 1064 | ret = i915_error_state_to_str(&error_str, error_priv); |
edc3d884 MK |
1065 | if (ret) |
1066 | goto out; | |
1067 | ||
edc3d884 MK |
1068 | ret_count = simple_read_from_buffer(userbuf, count, &tmp_pos, |
1069 | error_str.buf, | |
1070 | error_str.bytes); | |
1071 | ||
1072 | if (ret_count < 0) | |
1073 | ret = ret_count; | |
1074 | else | |
1075 | *pos = error_str.start + ret_count; | |
1076 | out: | |
4dc955f7 | 1077 | i915_error_state_buf_release(&error_str); |
edc3d884 | 1078 | return ret ?: ret_count; |
d5442303 DV |
1079 | } |
1080 | ||
1081 | static const struct file_operations i915_error_state_fops = { | |
1082 | .owner = THIS_MODULE, | |
1083 | .open = i915_error_state_open, | |
edc3d884 | 1084 | .read = i915_error_state_read, |
d5442303 DV |
1085 | .write = i915_error_state_write, |
1086 | .llseek = default_llseek, | |
1087 | .release = i915_error_state_release, | |
1088 | }; | |
1089 | ||
647416f9 KC |
1090 | static int |
1091 | i915_next_seqno_get(void *data, u64 *val) | |
40633219 | 1092 | { |
647416f9 | 1093 | struct drm_device *dev = data; |
e277a1f8 | 1094 | struct drm_i915_private *dev_priv = dev->dev_private; |
40633219 MK |
1095 | int ret; |
1096 | ||
1097 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
1098 | if (ret) | |
1099 | return ret; | |
1100 | ||
647416f9 | 1101 | *val = dev_priv->next_seqno; |
40633219 MK |
1102 | mutex_unlock(&dev->struct_mutex); |
1103 | ||
647416f9 | 1104 | return 0; |
40633219 MK |
1105 | } |
1106 | ||
647416f9 KC |
1107 | static int |
1108 | i915_next_seqno_set(void *data, u64 val) | |
1109 | { | |
1110 | struct drm_device *dev = data; | |
40633219 MK |
1111 | int ret; |
1112 | ||
40633219 MK |
1113 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
1114 | if (ret) | |
1115 | return ret; | |
1116 | ||
e94fbaa8 | 1117 | ret = i915_gem_set_seqno(dev, val); |
40633219 MK |
1118 | mutex_unlock(&dev->struct_mutex); |
1119 | ||
647416f9 | 1120 | return ret; |
40633219 MK |
1121 | } |
1122 | ||
647416f9 KC |
1123 | DEFINE_SIMPLE_ATTRIBUTE(i915_next_seqno_fops, |
1124 | i915_next_seqno_get, i915_next_seqno_set, | |
3a3b4f98 | 1125 | "0x%llx\n"); |
40633219 | 1126 | |
adb4bd12 | 1127 | static int i915_frequency_info(struct seq_file *m, void *unused) |
f97108d1 | 1128 | { |
9f25d007 | 1129 | struct drm_info_node *node = m->private; |
f97108d1 | 1130 | struct drm_device *dev = node->minor->dev; |
e277a1f8 | 1131 | struct drm_i915_private *dev_priv = dev->dev_private; |
c8c8fb33 PZ |
1132 | int ret = 0; |
1133 | ||
1134 | intel_runtime_pm_get(dev_priv); | |
3b8d8d91 | 1135 | |
5c9669ce TR |
1136 | flush_delayed_work(&dev_priv->rps.delayed_resume_work); |
1137 | ||
3b8d8d91 JB |
1138 | if (IS_GEN5(dev)) { |
1139 | u16 rgvswctl = I915_READ16(MEMSWCTL); | |
1140 | u16 rgvstat = I915_READ16(MEMSTAT_ILK); | |
1141 | ||
1142 | seq_printf(m, "Requested P-state: %d\n", (rgvswctl >> 8) & 0xf); | |
1143 | seq_printf(m, "Requested VID: %d\n", rgvswctl & 0x3f); | |
1144 | seq_printf(m, "Current VID: %d\n", (rgvstat & MEMSTAT_VID_MASK) >> | |
1145 | MEMSTAT_VID_SHIFT); | |
1146 | seq_printf(m, "Current P-state: %d\n", | |
1147 | (rgvstat & MEMSTAT_PSTATE_MASK) >> MEMSTAT_PSTATE_SHIFT); | |
666a4537 WB |
1148 | } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { |
1149 | u32 freq_sts; | |
1150 | ||
1151 | mutex_lock(&dev_priv->rps.hw_lock); | |
1152 | freq_sts = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS); | |
1153 | seq_printf(m, "PUNIT_REG_GPU_FREQ_STS: 0x%08x\n", freq_sts); | |
1154 | seq_printf(m, "DDR freq: %d MHz\n", dev_priv->mem_freq); | |
1155 | ||
1156 | seq_printf(m, "actual GPU freq: %d MHz\n", | |
1157 | intel_gpu_freq(dev_priv, (freq_sts >> 8) & 0xff)); | |
1158 | ||
1159 | seq_printf(m, "current GPU freq: %d MHz\n", | |
1160 | intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq)); | |
1161 | ||
1162 | seq_printf(m, "max GPU freq: %d MHz\n", | |
1163 | intel_gpu_freq(dev_priv, dev_priv->rps.max_freq)); | |
1164 | ||
1165 | seq_printf(m, "min GPU freq: %d MHz\n", | |
1166 | intel_gpu_freq(dev_priv, dev_priv->rps.min_freq)); | |
1167 | ||
1168 | seq_printf(m, "idle GPU freq: %d MHz\n", | |
1169 | intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq)); | |
1170 | ||
1171 | seq_printf(m, | |
1172 | "efficient (RPe) frequency: %d MHz\n", | |
1173 | intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq)); | |
1174 | mutex_unlock(&dev_priv->rps.hw_lock); | |
1175 | } else if (INTEL_INFO(dev)->gen >= 6) { | |
35040562 BP |
1176 | u32 rp_state_limits; |
1177 | u32 gt_perf_status; | |
1178 | u32 rp_state_cap; | |
0d8f9491 | 1179 | u32 rpmodectl, rpinclimit, rpdeclimit; |
8e8c06cd | 1180 | u32 rpstat, cagf, reqf; |
ccab5c82 JB |
1181 | u32 rpupei, rpcurup, rpprevup; |
1182 | u32 rpdownei, rpcurdown, rpprevdown; | |
9dd3c605 | 1183 | u32 pm_ier, pm_imr, pm_isr, pm_iir, pm_mask; |
3b8d8d91 JB |
1184 | int max_freq; |
1185 | ||
35040562 BP |
1186 | rp_state_limits = I915_READ(GEN6_RP_STATE_LIMITS); |
1187 | if (IS_BROXTON(dev)) { | |
1188 | rp_state_cap = I915_READ(BXT_RP_STATE_CAP); | |
1189 | gt_perf_status = I915_READ(BXT_GT_PERF_STATUS); | |
1190 | } else { | |
1191 | rp_state_cap = I915_READ(GEN6_RP_STATE_CAP); | |
1192 | gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS); | |
1193 | } | |
1194 | ||
3b8d8d91 | 1195 | /* RPSTAT1 is in the GT power well */ |
d1ebd816 BW |
1196 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
1197 | if (ret) | |
c8c8fb33 | 1198 | goto out; |
d1ebd816 | 1199 | |
59bad947 | 1200 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); |
3b8d8d91 | 1201 | |
8e8c06cd | 1202 | reqf = I915_READ(GEN6_RPNSWREQ); |
60260a5b AG |
1203 | if (IS_GEN9(dev)) |
1204 | reqf >>= 23; | |
1205 | else { | |
1206 | reqf &= ~GEN6_TURBO_DISABLE; | |
1207 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) | |
1208 | reqf >>= 24; | |
1209 | else | |
1210 | reqf >>= 25; | |
1211 | } | |
7c59a9c1 | 1212 | reqf = intel_gpu_freq(dev_priv, reqf); |
8e8c06cd | 1213 | |
0d8f9491 CW |
1214 | rpmodectl = I915_READ(GEN6_RP_CONTROL); |
1215 | rpinclimit = I915_READ(GEN6_RP_UP_THRESHOLD); | |
1216 | rpdeclimit = I915_READ(GEN6_RP_DOWN_THRESHOLD); | |
1217 | ||
ccab5c82 JB |
1218 | rpstat = I915_READ(GEN6_RPSTAT1); |
1219 | rpupei = I915_READ(GEN6_RP_CUR_UP_EI); | |
1220 | rpcurup = I915_READ(GEN6_RP_CUR_UP); | |
1221 | rpprevup = I915_READ(GEN6_RP_PREV_UP); | |
1222 | rpdownei = I915_READ(GEN6_RP_CUR_DOWN_EI); | |
1223 | rpcurdown = I915_READ(GEN6_RP_CUR_DOWN); | |
1224 | rpprevdown = I915_READ(GEN6_RP_PREV_DOWN); | |
60260a5b AG |
1225 | if (IS_GEN9(dev)) |
1226 | cagf = (rpstat & GEN9_CAGF_MASK) >> GEN9_CAGF_SHIFT; | |
1227 | else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) | |
f82855d3 BW |
1228 | cagf = (rpstat & HSW_CAGF_MASK) >> HSW_CAGF_SHIFT; |
1229 | else | |
1230 | cagf = (rpstat & GEN6_CAGF_MASK) >> GEN6_CAGF_SHIFT; | |
7c59a9c1 | 1231 | cagf = intel_gpu_freq(dev_priv, cagf); |
ccab5c82 | 1232 | |
59bad947 | 1233 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); |
d1ebd816 BW |
1234 | mutex_unlock(&dev->struct_mutex); |
1235 | ||
9dd3c605 PZ |
1236 | if (IS_GEN6(dev) || IS_GEN7(dev)) { |
1237 | pm_ier = I915_READ(GEN6_PMIER); | |
1238 | pm_imr = I915_READ(GEN6_PMIMR); | |
1239 | pm_isr = I915_READ(GEN6_PMISR); | |
1240 | pm_iir = I915_READ(GEN6_PMIIR); | |
1241 | pm_mask = I915_READ(GEN6_PMINTRMSK); | |
1242 | } else { | |
1243 | pm_ier = I915_READ(GEN8_GT_IER(2)); | |
1244 | pm_imr = I915_READ(GEN8_GT_IMR(2)); | |
1245 | pm_isr = I915_READ(GEN8_GT_ISR(2)); | |
1246 | pm_iir = I915_READ(GEN8_GT_IIR(2)); | |
1247 | pm_mask = I915_READ(GEN6_PMINTRMSK); | |
1248 | } | |
0d8f9491 | 1249 | seq_printf(m, "PM IER=0x%08x IMR=0x%08x ISR=0x%08x IIR=0x%08x, MASK=0x%08x\n", |
9dd3c605 | 1250 | pm_ier, pm_imr, pm_isr, pm_iir, pm_mask); |
3b8d8d91 | 1251 | seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status); |
3b8d8d91 | 1252 | seq_printf(m, "Render p-state ratio: %d\n", |
60260a5b | 1253 | (gt_perf_status & (IS_GEN9(dev) ? 0x1ff00 : 0xff00)) >> 8); |
3b8d8d91 JB |
1254 | seq_printf(m, "Render p-state VID: %d\n", |
1255 | gt_perf_status & 0xff); | |
1256 | seq_printf(m, "Render p-state limit: %d\n", | |
1257 | rp_state_limits & 0xff); | |
0d8f9491 CW |
1258 | seq_printf(m, "RPSTAT1: 0x%08x\n", rpstat); |
1259 | seq_printf(m, "RPMODECTL: 0x%08x\n", rpmodectl); | |
1260 | seq_printf(m, "RPINCLIMIT: 0x%08x\n", rpinclimit); | |
1261 | seq_printf(m, "RPDECLIMIT: 0x%08x\n", rpdeclimit); | |
8e8c06cd | 1262 | seq_printf(m, "RPNSWREQ: %dMHz\n", reqf); |
f82855d3 | 1263 | seq_printf(m, "CAGF: %dMHz\n", cagf); |
ccab5c82 JB |
1264 | seq_printf(m, "RP CUR UP EI: %dus\n", rpupei & |
1265 | GEN6_CURICONT_MASK); | |
1266 | seq_printf(m, "RP CUR UP: %dus\n", rpcurup & | |
1267 | GEN6_CURBSYTAVG_MASK); | |
1268 | seq_printf(m, "RP PREV UP: %dus\n", rpprevup & | |
1269 | GEN6_CURBSYTAVG_MASK); | |
d86ed34a CW |
1270 | seq_printf(m, "Up threshold: %d%%\n", |
1271 | dev_priv->rps.up_threshold); | |
1272 | ||
ccab5c82 JB |
1273 | seq_printf(m, "RP CUR DOWN EI: %dus\n", rpdownei & |
1274 | GEN6_CURIAVG_MASK); | |
1275 | seq_printf(m, "RP CUR DOWN: %dus\n", rpcurdown & | |
1276 | GEN6_CURBSYTAVG_MASK); | |
1277 | seq_printf(m, "RP PREV DOWN: %dus\n", rpprevdown & | |
1278 | GEN6_CURBSYTAVG_MASK); | |
d86ed34a CW |
1279 | seq_printf(m, "Down threshold: %d%%\n", |
1280 | dev_priv->rps.down_threshold); | |
3b8d8d91 | 1281 | |
35040562 BP |
1282 | max_freq = (IS_BROXTON(dev) ? rp_state_cap >> 0 : |
1283 | rp_state_cap >> 16) & 0xff; | |
ef11bdb3 RV |
1284 | max_freq *= (IS_SKYLAKE(dev) || IS_KABYLAKE(dev) ? |
1285 | GEN9_FREQ_SCALER : 1); | |
3b8d8d91 | 1286 | seq_printf(m, "Lowest (RPN) frequency: %dMHz\n", |
7c59a9c1 | 1287 | intel_gpu_freq(dev_priv, max_freq)); |
3b8d8d91 JB |
1288 | |
1289 | max_freq = (rp_state_cap & 0xff00) >> 8; | |
ef11bdb3 RV |
1290 | max_freq *= (IS_SKYLAKE(dev) || IS_KABYLAKE(dev) ? |
1291 | GEN9_FREQ_SCALER : 1); | |
3b8d8d91 | 1292 | seq_printf(m, "Nominal (RP1) frequency: %dMHz\n", |
7c59a9c1 | 1293 | intel_gpu_freq(dev_priv, max_freq)); |
3b8d8d91 | 1294 | |
35040562 BP |
1295 | max_freq = (IS_BROXTON(dev) ? rp_state_cap >> 16 : |
1296 | rp_state_cap >> 0) & 0xff; | |
ef11bdb3 RV |
1297 | max_freq *= (IS_SKYLAKE(dev) || IS_KABYLAKE(dev) ? |
1298 | GEN9_FREQ_SCALER : 1); | |
3b8d8d91 | 1299 | seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n", |
7c59a9c1 | 1300 | intel_gpu_freq(dev_priv, max_freq)); |
31c77388 | 1301 | seq_printf(m, "Max overclocked frequency: %dMHz\n", |
7c59a9c1 | 1302 | intel_gpu_freq(dev_priv, dev_priv->rps.max_freq)); |
aed242ff | 1303 | |
d86ed34a CW |
1304 | seq_printf(m, "Current freq: %d MHz\n", |
1305 | intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq)); | |
1306 | seq_printf(m, "Actual freq: %d MHz\n", cagf); | |
aed242ff CW |
1307 | seq_printf(m, "Idle freq: %d MHz\n", |
1308 | intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq)); | |
d86ed34a CW |
1309 | seq_printf(m, "Min freq: %d MHz\n", |
1310 | intel_gpu_freq(dev_priv, dev_priv->rps.min_freq)); | |
1311 | seq_printf(m, "Max freq: %d MHz\n", | |
1312 | intel_gpu_freq(dev_priv, dev_priv->rps.max_freq)); | |
1313 | seq_printf(m, | |
1314 | "efficient (RPe) frequency: %d MHz\n", | |
1315 | intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq)); | |
3b8d8d91 | 1316 | } else { |
267f0c90 | 1317 | seq_puts(m, "no P-state info available\n"); |
3b8d8d91 | 1318 | } |
f97108d1 | 1319 | |
1170f28c MK |
1320 | seq_printf(m, "Current CD clock frequency: %d kHz\n", dev_priv->cdclk_freq); |
1321 | seq_printf(m, "Max CD clock frequency: %d kHz\n", dev_priv->max_cdclk_freq); | |
1322 | seq_printf(m, "Max pixel clock frequency: %d kHz\n", dev_priv->max_dotclk_freq); | |
1323 | ||
c8c8fb33 PZ |
1324 | out: |
1325 | intel_runtime_pm_put(dev_priv); | |
1326 | return ret; | |
f97108d1 JB |
1327 | } |
1328 | ||
f654449a CW |
1329 | static int i915_hangcheck_info(struct seq_file *m, void *unused) |
1330 | { | |
1331 | struct drm_info_node *node = m->private; | |
ebbc7546 MK |
1332 | struct drm_device *dev = node->minor->dev; |
1333 | struct drm_i915_private *dev_priv = dev->dev_private; | |
e2f80391 | 1334 | struct intel_engine_cs *engine; |
666796da TU |
1335 | u64 acthd[I915_NUM_ENGINES]; |
1336 | u32 seqno[I915_NUM_ENGINES]; | |
61642ff0 | 1337 | u32 instdone[I915_NUM_INSTDONE_REG]; |
c3232b18 DG |
1338 | enum intel_engine_id id; |
1339 | int j; | |
f654449a CW |
1340 | |
1341 | if (!i915.enable_hangcheck) { | |
1342 | seq_printf(m, "Hangcheck disabled\n"); | |
1343 | return 0; | |
1344 | } | |
1345 | ||
ebbc7546 MK |
1346 | intel_runtime_pm_get(dev_priv); |
1347 | ||
c3232b18 | 1348 | for_each_engine_id(engine, dev_priv, id) { |
c3232b18 | 1349 | acthd[id] = intel_ring_get_active_head(engine); |
c04e0f3b | 1350 | seqno[id] = engine->get_seqno(engine); |
ebbc7546 MK |
1351 | } |
1352 | ||
61642ff0 MK |
1353 | i915_get_extra_instdone(dev, instdone); |
1354 | ||
ebbc7546 MK |
1355 | intel_runtime_pm_put(dev_priv); |
1356 | ||
f654449a CW |
1357 | if (delayed_work_pending(&dev_priv->gpu_error.hangcheck_work)) { |
1358 | seq_printf(m, "Hangcheck active, fires in %dms\n", | |
1359 | jiffies_to_msecs(dev_priv->gpu_error.hangcheck_work.timer.expires - | |
1360 | jiffies)); | |
1361 | } else | |
1362 | seq_printf(m, "Hangcheck inactive\n"); | |
1363 | ||
c3232b18 | 1364 | for_each_engine_id(engine, dev_priv, id) { |
e2f80391 | 1365 | seq_printf(m, "%s:\n", engine->name); |
14fd0d6d CW |
1366 | seq_printf(m, "\tseqno = %x [current %x, last %x]\n", |
1367 | engine->hangcheck.seqno, | |
1368 | seqno[id], | |
1369 | engine->last_submitted_seqno); | |
12471ba8 CW |
1370 | seq_printf(m, "\tuser interrupts = %x [current %x]\n", |
1371 | engine->hangcheck.user_interrupts, | |
1372 | READ_ONCE(engine->user_interrupts)); | |
f654449a | 1373 | seq_printf(m, "\tACTHD = 0x%08llx [current 0x%08llx]\n", |
e2f80391 | 1374 | (long long)engine->hangcheck.acthd, |
c3232b18 | 1375 | (long long)acthd[id]); |
e2f80391 TU |
1376 | seq_printf(m, "\tscore = %d\n", engine->hangcheck.score); |
1377 | seq_printf(m, "\taction = %d\n", engine->hangcheck.action); | |
61642ff0 | 1378 | |
e2f80391 | 1379 | if (engine->id == RCS) { |
61642ff0 MK |
1380 | seq_puts(m, "\tinstdone read ="); |
1381 | ||
1382 | for (j = 0; j < I915_NUM_INSTDONE_REG; j++) | |
1383 | seq_printf(m, " 0x%08x", instdone[j]); | |
1384 | ||
1385 | seq_puts(m, "\n\tinstdone accu ="); | |
1386 | ||
1387 | for (j = 0; j < I915_NUM_INSTDONE_REG; j++) | |
1388 | seq_printf(m, " 0x%08x", | |
e2f80391 | 1389 | engine->hangcheck.instdone[j]); |
61642ff0 MK |
1390 | |
1391 | seq_puts(m, "\n"); | |
1392 | } | |
f654449a CW |
1393 | } |
1394 | ||
1395 | return 0; | |
1396 | } | |
1397 | ||
4d85529d | 1398 | static int ironlake_drpc_info(struct seq_file *m) |
f97108d1 | 1399 | { |
9f25d007 | 1400 | struct drm_info_node *node = m->private; |
f97108d1 | 1401 | struct drm_device *dev = node->minor->dev; |
e277a1f8 | 1402 | struct drm_i915_private *dev_priv = dev->dev_private; |
616fdb5a BW |
1403 | u32 rgvmodectl, rstdbyctl; |
1404 | u16 crstandvid; | |
1405 | int ret; | |
1406 | ||
1407 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
1408 | if (ret) | |
1409 | return ret; | |
c8c8fb33 | 1410 | intel_runtime_pm_get(dev_priv); |
616fdb5a BW |
1411 | |
1412 | rgvmodectl = I915_READ(MEMMODECTL); | |
1413 | rstdbyctl = I915_READ(RSTDBYCTL); | |
1414 | crstandvid = I915_READ16(CRSTANDVID); | |
1415 | ||
c8c8fb33 | 1416 | intel_runtime_pm_put(dev_priv); |
616fdb5a | 1417 | mutex_unlock(&dev->struct_mutex); |
f97108d1 | 1418 | |
742f491d | 1419 | seq_printf(m, "HD boost: %s\n", yesno(rgvmodectl & MEMMODE_BOOST_EN)); |
f97108d1 JB |
1420 | seq_printf(m, "Boost freq: %d\n", |
1421 | (rgvmodectl & MEMMODE_BOOST_FREQ_MASK) >> | |
1422 | MEMMODE_BOOST_FREQ_SHIFT); | |
1423 | seq_printf(m, "HW control enabled: %s\n", | |
742f491d | 1424 | yesno(rgvmodectl & MEMMODE_HWIDLE_EN)); |
f97108d1 | 1425 | seq_printf(m, "SW control enabled: %s\n", |
742f491d | 1426 | yesno(rgvmodectl & MEMMODE_SWMODE_EN)); |
f97108d1 | 1427 | seq_printf(m, "Gated voltage change: %s\n", |
742f491d | 1428 | yesno(rgvmodectl & MEMMODE_RCLK_GATE)); |
f97108d1 JB |
1429 | seq_printf(m, "Starting frequency: P%d\n", |
1430 | (rgvmodectl & MEMMODE_FSTART_MASK) >> MEMMODE_FSTART_SHIFT); | |
7648fa99 | 1431 | seq_printf(m, "Max P-state: P%d\n", |
f97108d1 | 1432 | (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT); |
7648fa99 JB |
1433 | seq_printf(m, "Min P-state: P%d\n", (rgvmodectl & MEMMODE_FMIN_MASK)); |
1434 | seq_printf(m, "RS1 VID: %d\n", (crstandvid & 0x3f)); | |
1435 | seq_printf(m, "RS2 VID: %d\n", ((crstandvid >> 8) & 0x3f)); | |
1436 | seq_printf(m, "Render standby enabled: %s\n", | |
742f491d | 1437 | yesno(!(rstdbyctl & RCX_SW_EXIT))); |
267f0c90 | 1438 | seq_puts(m, "Current RS state: "); |
88271da3 JB |
1439 | switch (rstdbyctl & RSX_STATUS_MASK) { |
1440 | case RSX_STATUS_ON: | |
267f0c90 | 1441 | seq_puts(m, "on\n"); |
88271da3 JB |
1442 | break; |
1443 | case RSX_STATUS_RC1: | |
267f0c90 | 1444 | seq_puts(m, "RC1\n"); |
88271da3 JB |
1445 | break; |
1446 | case RSX_STATUS_RC1E: | |
267f0c90 | 1447 | seq_puts(m, "RC1E\n"); |
88271da3 JB |
1448 | break; |
1449 | case RSX_STATUS_RS1: | |
267f0c90 | 1450 | seq_puts(m, "RS1\n"); |
88271da3 JB |
1451 | break; |
1452 | case RSX_STATUS_RS2: | |
267f0c90 | 1453 | seq_puts(m, "RS2 (RC6)\n"); |
88271da3 JB |
1454 | break; |
1455 | case RSX_STATUS_RS3: | |
267f0c90 | 1456 | seq_puts(m, "RC3 (RC6+)\n"); |
88271da3 JB |
1457 | break; |
1458 | default: | |
267f0c90 | 1459 | seq_puts(m, "unknown\n"); |
88271da3 JB |
1460 | break; |
1461 | } | |
f97108d1 JB |
1462 | |
1463 | return 0; | |
1464 | } | |
1465 | ||
f65367b5 | 1466 | static int i915_forcewake_domains(struct seq_file *m, void *data) |
669ab5aa | 1467 | { |
b2cff0db CW |
1468 | struct drm_info_node *node = m->private; |
1469 | struct drm_device *dev = node->minor->dev; | |
1470 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1471 | struct intel_uncore_forcewake_domain *fw_domain; | |
b2cff0db CW |
1472 | int i; |
1473 | ||
1474 | spin_lock_irq(&dev_priv->uncore.lock); | |
1475 | for_each_fw_domain(fw_domain, dev_priv, i) { | |
1476 | seq_printf(m, "%s.wake_count = %u\n", | |
05a2fb15 | 1477 | intel_uncore_forcewake_domain_to_str(i), |
b2cff0db CW |
1478 | fw_domain->wake_count); |
1479 | } | |
1480 | spin_unlock_irq(&dev_priv->uncore.lock); | |
669ab5aa | 1481 | |
b2cff0db CW |
1482 | return 0; |
1483 | } | |
1484 | ||
1485 | static int vlv_drpc_info(struct seq_file *m) | |
1486 | { | |
9f25d007 | 1487 | struct drm_info_node *node = m->private; |
669ab5aa D |
1488 | struct drm_device *dev = node->minor->dev; |
1489 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6b312cd3 | 1490 | u32 rpmodectl1, rcctl1, pw_status; |
669ab5aa | 1491 | |
d46c0517 ID |
1492 | intel_runtime_pm_get(dev_priv); |
1493 | ||
6b312cd3 | 1494 | pw_status = I915_READ(VLV_GTLC_PW_STATUS); |
669ab5aa D |
1495 | rpmodectl1 = I915_READ(GEN6_RP_CONTROL); |
1496 | rcctl1 = I915_READ(GEN6_RC_CONTROL); | |
1497 | ||
d46c0517 ID |
1498 | intel_runtime_pm_put(dev_priv); |
1499 | ||
669ab5aa D |
1500 | seq_printf(m, "Video Turbo Mode: %s\n", |
1501 | yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO)); | |
1502 | seq_printf(m, "Turbo enabled: %s\n", | |
1503 | yesno(rpmodectl1 & GEN6_RP_ENABLE)); | |
1504 | seq_printf(m, "HW control enabled: %s\n", | |
1505 | yesno(rpmodectl1 & GEN6_RP_ENABLE)); | |
1506 | seq_printf(m, "SW control enabled: %s\n", | |
1507 | yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) == | |
1508 | GEN6_RP_MEDIA_SW_MODE)); | |
1509 | seq_printf(m, "RC6 Enabled: %s\n", | |
1510 | yesno(rcctl1 & (GEN7_RC_CTL_TO_MODE | | |
1511 | GEN6_RC_CTL_EI_MODE(1)))); | |
1512 | seq_printf(m, "Render Power Well: %s\n", | |
6b312cd3 | 1513 | (pw_status & VLV_GTLC_PW_RENDER_STATUS_MASK) ? "Up" : "Down"); |
669ab5aa | 1514 | seq_printf(m, "Media Power Well: %s\n", |
6b312cd3 | 1515 | (pw_status & VLV_GTLC_PW_MEDIA_STATUS_MASK) ? "Up" : "Down"); |
669ab5aa | 1516 | |
9cc19be5 ID |
1517 | seq_printf(m, "Render RC6 residency since boot: %u\n", |
1518 | I915_READ(VLV_GT_RENDER_RC6)); | |
1519 | seq_printf(m, "Media RC6 residency since boot: %u\n", | |
1520 | I915_READ(VLV_GT_MEDIA_RC6)); | |
1521 | ||
f65367b5 | 1522 | return i915_forcewake_domains(m, NULL); |
669ab5aa D |
1523 | } |
1524 | ||
4d85529d BW |
1525 | static int gen6_drpc_info(struct seq_file *m) |
1526 | { | |
9f25d007 | 1527 | struct drm_info_node *node = m->private; |
4d85529d BW |
1528 | struct drm_device *dev = node->minor->dev; |
1529 | struct drm_i915_private *dev_priv = dev->dev_private; | |
ecd8faea | 1530 | u32 rpmodectl1, gt_core_status, rcctl1, rc6vids = 0; |
93b525dc | 1531 | unsigned forcewake_count; |
aee56cff | 1532 | int count = 0, ret; |
4d85529d BW |
1533 | |
1534 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
1535 | if (ret) | |
1536 | return ret; | |
c8c8fb33 | 1537 | intel_runtime_pm_get(dev_priv); |
4d85529d | 1538 | |
907b28c5 | 1539 | spin_lock_irq(&dev_priv->uncore.lock); |
b2cff0db | 1540 | forcewake_count = dev_priv->uncore.fw_domain[FW_DOMAIN_ID_RENDER].wake_count; |
907b28c5 | 1541 | spin_unlock_irq(&dev_priv->uncore.lock); |
93b525dc DV |
1542 | |
1543 | if (forcewake_count) { | |
267f0c90 DL |
1544 | seq_puts(m, "RC information inaccurate because somebody " |
1545 | "holds a forcewake reference \n"); | |
4d85529d BW |
1546 | } else { |
1547 | /* NB: we cannot use forcewake, else we read the wrong values */ | |
1548 | while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1)) | |
1549 | udelay(10); | |
1550 | seq_printf(m, "RC information accurate: %s\n", yesno(count < 51)); | |
1551 | } | |
1552 | ||
75aa3f63 | 1553 | gt_core_status = I915_READ_FW(GEN6_GT_CORE_STATUS); |
ed71f1b4 | 1554 | trace_i915_reg_rw(false, GEN6_GT_CORE_STATUS, gt_core_status, 4, true); |
4d85529d BW |
1555 | |
1556 | rpmodectl1 = I915_READ(GEN6_RP_CONTROL); | |
1557 | rcctl1 = I915_READ(GEN6_RC_CONTROL); | |
1558 | mutex_unlock(&dev->struct_mutex); | |
44cbd338 BW |
1559 | mutex_lock(&dev_priv->rps.hw_lock); |
1560 | sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids); | |
1561 | mutex_unlock(&dev_priv->rps.hw_lock); | |
4d85529d | 1562 | |
c8c8fb33 PZ |
1563 | intel_runtime_pm_put(dev_priv); |
1564 | ||
4d85529d BW |
1565 | seq_printf(m, "Video Turbo Mode: %s\n", |
1566 | yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO)); | |
1567 | seq_printf(m, "HW control enabled: %s\n", | |
1568 | yesno(rpmodectl1 & GEN6_RP_ENABLE)); | |
1569 | seq_printf(m, "SW control enabled: %s\n", | |
1570 | yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) == | |
1571 | GEN6_RP_MEDIA_SW_MODE)); | |
fff24e21 | 1572 | seq_printf(m, "RC1e Enabled: %s\n", |
4d85529d BW |
1573 | yesno(rcctl1 & GEN6_RC_CTL_RC1e_ENABLE)); |
1574 | seq_printf(m, "RC6 Enabled: %s\n", | |
1575 | yesno(rcctl1 & GEN6_RC_CTL_RC6_ENABLE)); | |
1576 | seq_printf(m, "Deep RC6 Enabled: %s\n", | |
1577 | yesno(rcctl1 & GEN6_RC_CTL_RC6p_ENABLE)); | |
1578 | seq_printf(m, "Deepest RC6 Enabled: %s\n", | |
1579 | yesno(rcctl1 & GEN6_RC_CTL_RC6pp_ENABLE)); | |
267f0c90 | 1580 | seq_puts(m, "Current RC state: "); |
4d85529d BW |
1581 | switch (gt_core_status & GEN6_RCn_MASK) { |
1582 | case GEN6_RC0: | |
1583 | if (gt_core_status & GEN6_CORE_CPD_STATE_MASK) | |
267f0c90 | 1584 | seq_puts(m, "Core Power Down\n"); |
4d85529d | 1585 | else |
267f0c90 | 1586 | seq_puts(m, "on\n"); |
4d85529d BW |
1587 | break; |
1588 | case GEN6_RC3: | |
267f0c90 | 1589 | seq_puts(m, "RC3\n"); |
4d85529d BW |
1590 | break; |
1591 | case GEN6_RC6: | |
267f0c90 | 1592 | seq_puts(m, "RC6\n"); |
4d85529d BW |
1593 | break; |
1594 | case GEN6_RC7: | |
267f0c90 | 1595 | seq_puts(m, "RC7\n"); |
4d85529d BW |
1596 | break; |
1597 | default: | |
267f0c90 | 1598 | seq_puts(m, "Unknown\n"); |
4d85529d BW |
1599 | break; |
1600 | } | |
1601 | ||
1602 | seq_printf(m, "Core Power Down: %s\n", | |
1603 | yesno(gt_core_status & GEN6_CORE_CPD_STATE_MASK)); | |
cce66a28 BW |
1604 | |
1605 | /* Not exactly sure what this is */ | |
1606 | seq_printf(m, "RC6 \"Locked to RPn\" residency since boot: %u\n", | |
1607 | I915_READ(GEN6_GT_GFX_RC6_LOCKED)); | |
1608 | seq_printf(m, "RC6 residency since boot: %u\n", | |
1609 | I915_READ(GEN6_GT_GFX_RC6)); | |
1610 | seq_printf(m, "RC6+ residency since boot: %u\n", | |
1611 | I915_READ(GEN6_GT_GFX_RC6p)); | |
1612 | seq_printf(m, "RC6++ residency since boot: %u\n", | |
1613 | I915_READ(GEN6_GT_GFX_RC6pp)); | |
1614 | ||
ecd8faea BW |
1615 | seq_printf(m, "RC6 voltage: %dmV\n", |
1616 | GEN6_DECODE_RC6_VID(((rc6vids >> 0) & 0xff))); | |
1617 | seq_printf(m, "RC6+ voltage: %dmV\n", | |
1618 | GEN6_DECODE_RC6_VID(((rc6vids >> 8) & 0xff))); | |
1619 | seq_printf(m, "RC6++ voltage: %dmV\n", | |
1620 | GEN6_DECODE_RC6_VID(((rc6vids >> 16) & 0xff))); | |
4d85529d BW |
1621 | return 0; |
1622 | } | |
1623 | ||
1624 | static int i915_drpc_info(struct seq_file *m, void *unused) | |
1625 | { | |
9f25d007 | 1626 | struct drm_info_node *node = m->private; |
4d85529d BW |
1627 | struct drm_device *dev = node->minor->dev; |
1628 | ||
666a4537 | 1629 | if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) |
669ab5aa | 1630 | return vlv_drpc_info(m); |
ac66cf4b | 1631 | else if (INTEL_INFO(dev)->gen >= 6) |
4d85529d BW |
1632 | return gen6_drpc_info(m); |
1633 | else | |
1634 | return ironlake_drpc_info(m); | |
1635 | } | |
1636 | ||
9a851789 DV |
1637 | static int i915_frontbuffer_tracking(struct seq_file *m, void *unused) |
1638 | { | |
1639 | struct drm_info_node *node = m->private; | |
1640 | struct drm_device *dev = node->minor->dev; | |
1641 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1642 | ||
1643 | seq_printf(m, "FB tracking busy bits: 0x%08x\n", | |
1644 | dev_priv->fb_tracking.busy_bits); | |
1645 | ||
1646 | seq_printf(m, "FB tracking flip bits: 0x%08x\n", | |
1647 | dev_priv->fb_tracking.flip_bits); | |
1648 | ||
1649 | return 0; | |
1650 | } | |
1651 | ||
b5e50c3f JB |
1652 | static int i915_fbc_status(struct seq_file *m, void *unused) |
1653 | { | |
9f25d007 | 1654 | struct drm_info_node *node = m->private; |
b5e50c3f | 1655 | struct drm_device *dev = node->minor->dev; |
e277a1f8 | 1656 | struct drm_i915_private *dev_priv = dev->dev_private; |
b5e50c3f | 1657 | |
3a77c4c4 | 1658 | if (!HAS_FBC(dev)) { |
267f0c90 | 1659 | seq_puts(m, "FBC unsupported on this chipset\n"); |
b5e50c3f JB |
1660 | return 0; |
1661 | } | |
1662 | ||
36623ef8 | 1663 | intel_runtime_pm_get(dev_priv); |
25ad93fd | 1664 | mutex_lock(&dev_priv->fbc.lock); |
36623ef8 | 1665 | |
0e631adc | 1666 | if (intel_fbc_is_active(dev_priv)) |
267f0c90 | 1667 | seq_puts(m, "FBC enabled\n"); |
2e8144a5 PZ |
1668 | else |
1669 | seq_printf(m, "FBC disabled: %s\n", | |
bf6189c6 | 1670 | dev_priv->fbc.no_fbc_reason); |
36623ef8 | 1671 | |
31b9df10 PZ |
1672 | if (INTEL_INFO(dev_priv)->gen >= 7) |
1673 | seq_printf(m, "Compressing: %s\n", | |
1674 | yesno(I915_READ(FBC_STATUS2) & | |
1675 | FBC_COMPRESSION_MASK)); | |
1676 | ||
25ad93fd | 1677 | mutex_unlock(&dev_priv->fbc.lock); |
36623ef8 PZ |
1678 | intel_runtime_pm_put(dev_priv); |
1679 | ||
b5e50c3f JB |
1680 | return 0; |
1681 | } | |
1682 | ||
da46f936 RV |
1683 | static int i915_fbc_fc_get(void *data, u64 *val) |
1684 | { | |
1685 | struct drm_device *dev = data; | |
1686 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1687 | ||
1688 | if (INTEL_INFO(dev)->gen < 7 || !HAS_FBC(dev)) | |
1689 | return -ENODEV; | |
1690 | ||
da46f936 | 1691 | *val = dev_priv->fbc.false_color; |
da46f936 RV |
1692 | |
1693 | return 0; | |
1694 | } | |
1695 | ||
1696 | static int i915_fbc_fc_set(void *data, u64 val) | |
1697 | { | |
1698 | struct drm_device *dev = data; | |
1699 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1700 | u32 reg; | |
1701 | ||
1702 | if (INTEL_INFO(dev)->gen < 7 || !HAS_FBC(dev)) | |
1703 | return -ENODEV; | |
1704 | ||
25ad93fd | 1705 | mutex_lock(&dev_priv->fbc.lock); |
da46f936 RV |
1706 | |
1707 | reg = I915_READ(ILK_DPFC_CONTROL); | |
1708 | dev_priv->fbc.false_color = val; | |
1709 | ||
1710 | I915_WRITE(ILK_DPFC_CONTROL, val ? | |
1711 | (reg | FBC_CTL_FALSE_COLOR) : | |
1712 | (reg & ~FBC_CTL_FALSE_COLOR)); | |
1713 | ||
25ad93fd | 1714 | mutex_unlock(&dev_priv->fbc.lock); |
da46f936 RV |
1715 | return 0; |
1716 | } | |
1717 | ||
1718 | DEFINE_SIMPLE_ATTRIBUTE(i915_fbc_fc_fops, | |
1719 | i915_fbc_fc_get, i915_fbc_fc_set, | |
1720 | "%llu\n"); | |
1721 | ||
92d44621 PZ |
1722 | static int i915_ips_status(struct seq_file *m, void *unused) |
1723 | { | |
9f25d007 | 1724 | struct drm_info_node *node = m->private; |
92d44621 PZ |
1725 | struct drm_device *dev = node->minor->dev; |
1726 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1727 | ||
f5adf94e | 1728 | if (!HAS_IPS(dev)) { |
92d44621 PZ |
1729 | seq_puts(m, "not supported\n"); |
1730 | return 0; | |
1731 | } | |
1732 | ||
36623ef8 PZ |
1733 | intel_runtime_pm_get(dev_priv); |
1734 | ||
0eaa53f0 RV |
1735 | seq_printf(m, "Enabled by kernel parameter: %s\n", |
1736 | yesno(i915.enable_ips)); | |
1737 | ||
1738 | if (INTEL_INFO(dev)->gen >= 8) { | |
1739 | seq_puts(m, "Currently: unknown\n"); | |
1740 | } else { | |
1741 | if (I915_READ(IPS_CTL) & IPS_ENABLE) | |
1742 | seq_puts(m, "Currently: enabled\n"); | |
1743 | else | |
1744 | seq_puts(m, "Currently: disabled\n"); | |
1745 | } | |
92d44621 | 1746 | |
36623ef8 PZ |
1747 | intel_runtime_pm_put(dev_priv); |
1748 | ||
92d44621 PZ |
1749 | return 0; |
1750 | } | |
1751 | ||
4a9bef37 JB |
1752 | static int i915_sr_status(struct seq_file *m, void *unused) |
1753 | { | |
9f25d007 | 1754 | struct drm_info_node *node = m->private; |
4a9bef37 | 1755 | struct drm_device *dev = node->minor->dev; |
e277a1f8 | 1756 | struct drm_i915_private *dev_priv = dev->dev_private; |
4a9bef37 JB |
1757 | bool sr_enabled = false; |
1758 | ||
36623ef8 PZ |
1759 | intel_runtime_pm_get(dev_priv); |
1760 | ||
1398261a | 1761 | if (HAS_PCH_SPLIT(dev)) |
5ba2aaaa | 1762 | sr_enabled = I915_READ(WM1_LP_ILK) & WM1_LP_SR_EN; |
77b64555 ACO |
1763 | else if (IS_CRESTLINE(dev) || IS_G4X(dev) || |
1764 | IS_I945G(dev) || IS_I945GM(dev)) | |
4a9bef37 JB |
1765 | sr_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN; |
1766 | else if (IS_I915GM(dev)) | |
1767 | sr_enabled = I915_READ(INSTPM) & INSTPM_SELF_EN; | |
1768 | else if (IS_PINEVIEW(dev)) | |
1769 | sr_enabled = I915_READ(DSPFW3) & PINEVIEW_SELF_REFRESH_EN; | |
666a4537 | 1770 | else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) |
77b64555 | 1771 | sr_enabled = I915_READ(FW_BLC_SELF_VLV) & FW_CSPWRDWNEN; |
4a9bef37 | 1772 | |
36623ef8 PZ |
1773 | intel_runtime_pm_put(dev_priv); |
1774 | ||
5ba2aaaa CW |
1775 | seq_printf(m, "self-refresh: %s\n", |
1776 | sr_enabled ? "enabled" : "disabled"); | |
4a9bef37 JB |
1777 | |
1778 | return 0; | |
1779 | } | |
1780 | ||
7648fa99 JB |
1781 | static int i915_emon_status(struct seq_file *m, void *unused) |
1782 | { | |
9f25d007 | 1783 | struct drm_info_node *node = m->private; |
7648fa99 | 1784 | struct drm_device *dev = node->minor->dev; |
e277a1f8 | 1785 | struct drm_i915_private *dev_priv = dev->dev_private; |
7648fa99 | 1786 | unsigned long temp, chipset, gfx; |
de227ef0 CW |
1787 | int ret; |
1788 | ||
582be6b4 CW |
1789 | if (!IS_GEN5(dev)) |
1790 | return -ENODEV; | |
1791 | ||
de227ef0 CW |
1792 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
1793 | if (ret) | |
1794 | return ret; | |
7648fa99 JB |
1795 | |
1796 | temp = i915_mch_val(dev_priv); | |
1797 | chipset = i915_chipset_val(dev_priv); | |
1798 | gfx = i915_gfx_val(dev_priv); | |
de227ef0 | 1799 | mutex_unlock(&dev->struct_mutex); |
7648fa99 JB |
1800 | |
1801 | seq_printf(m, "GMCH temp: %ld\n", temp); | |
1802 | seq_printf(m, "Chipset power: %ld\n", chipset); | |
1803 | seq_printf(m, "GFX power: %ld\n", gfx); | |
1804 | seq_printf(m, "Total power: %ld\n", chipset + gfx); | |
1805 | ||
1806 | return 0; | |
1807 | } | |
1808 | ||
23b2f8bb JB |
1809 | static int i915_ring_freq_table(struct seq_file *m, void *unused) |
1810 | { | |
9f25d007 | 1811 | struct drm_info_node *node = m->private; |
23b2f8bb | 1812 | struct drm_device *dev = node->minor->dev; |
e277a1f8 | 1813 | struct drm_i915_private *dev_priv = dev->dev_private; |
5bfa0199 | 1814 | int ret = 0; |
23b2f8bb | 1815 | int gpu_freq, ia_freq; |
f936ec34 | 1816 | unsigned int max_gpu_freq, min_gpu_freq; |
23b2f8bb | 1817 | |
97d3308a | 1818 | if (!HAS_CORE_RING_FREQ(dev)) { |
267f0c90 | 1819 | seq_puts(m, "unsupported on this chipset\n"); |
23b2f8bb JB |
1820 | return 0; |
1821 | } | |
1822 | ||
5bfa0199 PZ |
1823 | intel_runtime_pm_get(dev_priv); |
1824 | ||
5c9669ce TR |
1825 | flush_delayed_work(&dev_priv->rps.delayed_resume_work); |
1826 | ||
4fc688ce | 1827 | ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock); |
23b2f8bb | 1828 | if (ret) |
5bfa0199 | 1829 | goto out; |
23b2f8bb | 1830 | |
ef11bdb3 | 1831 | if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) { |
f936ec34 AG |
1832 | /* Convert GT frequency to 50 HZ units */ |
1833 | min_gpu_freq = | |
1834 | dev_priv->rps.min_freq_softlimit / GEN9_FREQ_SCALER; | |
1835 | max_gpu_freq = | |
1836 | dev_priv->rps.max_freq_softlimit / GEN9_FREQ_SCALER; | |
1837 | } else { | |
1838 | min_gpu_freq = dev_priv->rps.min_freq_softlimit; | |
1839 | max_gpu_freq = dev_priv->rps.max_freq_softlimit; | |
1840 | } | |
1841 | ||
267f0c90 | 1842 | seq_puts(m, "GPU freq (MHz)\tEffective CPU freq (MHz)\tEffective Ring freq (MHz)\n"); |
23b2f8bb | 1843 | |
f936ec34 | 1844 | for (gpu_freq = min_gpu_freq; gpu_freq <= max_gpu_freq; gpu_freq++) { |
42c0526c BW |
1845 | ia_freq = gpu_freq; |
1846 | sandybridge_pcode_read(dev_priv, | |
1847 | GEN6_PCODE_READ_MIN_FREQ_TABLE, | |
1848 | &ia_freq); | |
3ebecd07 | 1849 | seq_printf(m, "%d\t\t%d\t\t\t\t%d\n", |
f936ec34 | 1850 | intel_gpu_freq(dev_priv, (gpu_freq * |
ef11bdb3 RV |
1851 | (IS_SKYLAKE(dev) || IS_KABYLAKE(dev) ? |
1852 | GEN9_FREQ_SCALER : 1))), | |
3ebecd07 CW |
1853 | ((ia_freq >> 0) & 0xff) * 100, |
1854 | ((ia_freq >> 8) & 0xff) * 100); | |
23b2f8bb JB |
1855 | } |
1856 | ||
4fc688ce | 1857 | mutex_unlock(&dev_priv->rps.hw_lock); |
23b2f8bb | 1858 | |
5bfa0199 PZ |
1859 | out: |
1860 | intel_runtime_pm_put(dev_priv); | |
1861 | return ret; | |
23b2f8bb JB |
1862 | } |
1863 | ||
44834a67 CW |
1864 | static int i915_opregion(struct seq_file *m, void *unused) |
1865 | { | |
9f25d007 | 1866 | struct drm_info_node *node = m->private; |
44834a67 | 1867 | struct drm_device *dev = node->minor->dev; |
e277a1f8 | 1868 | struct drm_i915_private *dev_priv = dev->dev_private; |
44834a67 CW |
1869 | struct intel_opregion *opregion = &dev_priv->opregion; |
1870 | int ret; | |
1871 | ||
1872 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
1873 | if (ret) | |
0d38f009 | 1874 | goto out; |
44834a67 | 1875 | |
2455a8e4 JN |
1876 | if (opregion->header) |
1877 | seq_write(m, opregion->header, OPREGION_SIZE); | |
44834a67 CW |
1878 | |
1879 | mutex_unlock(&dev->struct_mutex); | |
1880 | ||
0d38f009 | 1881 | out: |
44834a67 CW |
1882 | return 0; |
1883 | } | |
1884 | ||
ada8f955 JN |
1885 | static int i915_vbt(struct seq_file *m, void *unused) |
1886 | { | |
1887 | struct drm_info_node *node = m->private; | |
1888 | struct drm_device *dev = node->minor->dev; | |
1889 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1890 | struct intel_opregion *opregion = &dev_priv->opregion; | |
1891 | ||
1892 | if (opregion->vbt) | |
1893 | seq_write(m, opregion->vbt, opregion->vbt_size); | |
1894 | ||
1895 | return 0; | |
1896 | } | |
1897 | ||
37811fcc CW |
1898 | static int i915_gem_framebuffer_info(struct seq_file *m, void *data) |
1899 | { | |
9f25d007 | 1900 | struct drm_info_node *node = m->private; |
37811fcc | 1901 | struct drm_device *dev = node->minor->dev; |
b13b8402 | 1902 | struct intel_framebuffer *fbdev_fb = NULL; |
3a58ee10 | 1903 | struct drm_framebuffer *drm_fb; |
188c1ab7 CW |
1904 | int ret; |
1905 | ||
1906 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
1907 | if (ret) | |
1908 | return ret; | |
37811fcc | 1909 | |
0695726e | 1910 | #ifdef CONFIG_DRM_FBDEV_EMULATION |
b13b8402 NS |
1911 | if (to_i915(dev)->fbdev) { |
1912 | fbdev_fb = to_intel_framebuffer(to_i915(dev)->fbdev->helper.fb); | |
1913 | ||
1914 | seq_printf(m, "fbcon size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj ", | |
1915 | fbdev_fb->base.width, | |
1916 | fbdev_fb->base.height, | |
1917 | fbdev_fb->base.depth, | |
1918 | fbdev_fb->base.bits_per_pixel, | |
1919 | fbdev_fb->base.modifier[0], | |
1920 | atomic_read(&fbdev_fb->base.refcount.refcount)); | |
1921 | describe_obj(m, fbdev_fb->obj); | |
1922 | seq_putc(m, '\n'); | |
1923 | } | |
4520f53a | 1924 | #endif |
37811fcc | 1925 | |
4b096ac1 | 1926 | mutex_lock(&dev->mode_config.fb_lock); |
3a58ee10 | 1927 | drm_for_each_fb(drm_fb, dev) { |
b13b8402 NS |
1928 | struct intel_framebuffer *fb = to_intel_framebuffer(drm_fb); |
1929 | if (fb == fbdev_fb) | |
37811fcc CW |
1930 | continue; |
1931 | ||
c1ca506d | 1932 | seq_printf(m, "user size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj ", |
37811fcc CW |
1933 | fb->base.width, |
1934 | fb->base.height, | |
1935 | fb->base.depth, | |
623f9783 | 1936 | fb->base.bits_per_pixel, |
c1ca506d | 1937 | fb->base.modifier[0], |
623f9783 | 1938 | atomic_read(&fb->base.refcount.refcount)); |
05394f39 | 1939 | describe_obj(m, fb->obj); |
267f0c90 | 1940 | seq_putc(m, '\n'); |
37811fcc | 1941 | } |
4b096ac1 | 1942 | mutex_unlock(&dev->mode_config.fb_lock); |
188c1ab7 | 1943 | mutex_unlock(&dev->struct_mutex); |
37811fcc CW |
1944 | |
1945 | return 0; | |
1946 | } | |
1947 | ||
c9fe99bd OM |
1948 | static void describe_ctx_ringbuf(struct seq_file *m, |
1949 | struct intel_ringbuffer *ringbuf) | |
1950 | { | |
1951 | seq_printf(m, " (ringbuffer, space: %d, head: %u, tail: %u, last head: %d)", | |
1952 | ringbuf->space, ringbuf->head, ringbuf->tail, | |
1953 | ringbuf->last_retired_head); | |
1954 | } | |
1955 | ||
e76d3630 BW |
1956 | static int i915_context_status(struct seq_file *m, void *unused) |
1957 | { | |
9f25d007 | 1958 | struct drm_info_node *node = m->private; |
e76d3630 | 1959 | struct drm_device *dev = node->minor->dev; |
e277a1f8 | 1960 | struct drm_i915_private *dev_priv = dev->dev_private; |
e2f80391 | 1961 | struct intel_engine_cs *engine; |
273497e5 | 1962 | struct intel_context *ctx; |
c3232b18 DG |
1963 | enum intel_engine_id id; |
1964 | int ret; | |
e76d3630 | 1965 | |
f3d28878 | 1966 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
e76d3630 BW |
1967 | if (ret) |
1968 | return ret; | |
1969 | ||
a33afea5 | 1970 | list_for_each_entry(ctx, &dev_priv->context_list, link) { |
c9fe99bd OM |
1971 | if (!i915.enable_execlists && |
1972 | ctx->legacy_hw_ctx.rcs_state == NULL) | |
b77f6997 CW |
1973 | continue; |
1974 | ||
a33afea5 | 1975 | seq_puts(m, "HW context "); |
3ccfd19d | 1976 | describe_ctx(m, ctx); |
e28e404c DG |
1977 | if (ctx == dev_priv->kernel_context) |
1978 | seq_printf(m, "(kernel context) "); | |
c9fe99bd OM |
1979 | |
1980 | if (i915.enable_execlists) { | |
1981 | seq_putc(m, '\n'); | |
c3232b18 | 1982 | for_each_engine_id(engine, dev_priv, id) { |
c9fe99bd | 1983 | struct drm_i915_gem_object *ctx_obj = |
c3232b18 | 1984 | ctx->engine[id].state; |
c9fe99bd | 1985 | struct intel_ringbuffer *ringbuf = |
c3232b18 | 1986 | ctx->engine[id].ringbuf; |
c9fe99bd | 1987 | |
e2f80391 | 1988 | seq_printf(m, "%s: ", engine->name); |
c9fe99bd OM |
1989 | if (ctx_obj) |
1990 | describe_obj(m, ctx_obj); | |
1991 | if (ringbuf) | |
1992 | describe_ctx_ringbuf(m, ringbuf); | |
1993 | seq_putc(m, '\n'); | |
1994 | } | |
1995 | } else { | |
1996 | describe_obj(m, ctx->legacy_hw_ctx.rcs_state); | |
1997 | } | |
a33afea5 | 1998 | |
a33afea5 | 1999 | seq_putc(m, '\n'); |
a168c293 BW |
2000 | } |
2001 | ||
f3d28878 | 2002 | mutex_unlock(&dev->struct_mutex); |
e76d3630 BW |
2003 | |
2004 | return 0; | |
2005 | } | |
2006 | ||
064ca1d2 | 2007 | static void i915_dump_lrc_obj(struct seq_file *m, |
ca82580c | 2008 | struct intel_context *ctx, |
0bc40be8 | 2009 | struct intel_engine_cs *engine) |
064ca1d2 TD |
2010 | { |
2011 | struct page *page; | |
2012 | uint32_t *reg_state; | |
2013 | int j; | |
0bc40be8 | 2014 | struct drm_i915_gem_object *ctx_obj = ctx->engine[engine->id].state; |
064ca1d2 TD |
2015 | unsigned long ggtt_offset = 0; |
2016 | ||
2017 | if (ctx_obj == NULL) { | |
2018 | seq_printf(m, "Context on %s with no gem object\n", | |
0bc40be8 | 2019 | engine->name); |
064ca1d2 TD |
2020 | return; |
2021 | } | |
2022 | ||
0bc40be8 TU |
2023 | seq_printf(m, "CONTEXT: %s %u\n", engine->name, |
2024 | intel_execlists_ctx_id(ctx, engine)); | |
064ca1d2 TD |
2025 | |
2026 | if (!i915_gem_obj_ggtt_bound(ctx_obj)) | |
2027 | seq_puts(m, "\tNot bound in GGTT\n"); | |
2028 | else | |
2029 | ggtt_offset = i915_gem_obj_ggtt_offset(ctx_obj); | |
2030 | ||
2031 | if (i915_gem_object_get_pages(ctx_obj)) { | |
2032 | seq_puts(m, "\tFailed to get pages for context object\n"); | |
2033 | return; | |
2034 | } | |
2035 | ||
d1675198 | 2036 | page = i915_gem_object_get_page(ctx_obj, LRC_STATE_PN); |
064ca1d2 TD |
2037 | if (!WARN_ON(page == NULL)) { |
2038 | reg_state = kmap_atomic(page); | |
2039 | ||
2040 | for (j = 0; j < 0x600 / sizeof(u32) / 4; j += 4) { | |
2041 | seq_printf(m, "\t[0x%08lx] 0x%08x 0x%08x 0x%08x 0x%08x\n", | |
2042 | ggtt_offset + 4096 + (j * 4), | |
2043 | reg_state[j], reg_state[j + 1], | |
2044 | reg_state[j + 2], reg_state[j + 3]); | |
2045 | } | |
2046 | kunmap_atomic(reg_state); | |
2047 | } | |
2048 | ||
2049 | seq_putc(m, '\n'); | |
2050 | } | |
2051 | ||
c0ab1ae9 BW |
2052 | static int i915_dump_lrc(struct seq_file *m, void *unused) |
2053 | { | |
2054 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
2055 | struct drm_device *dev = node->minor->dev; | |
2056 | struct drm_i915_private *dev_priv = dev->dev_private; | |
e2f80391 | 2057 | struct intel_engine_cs *engine; |
c0ab1ae9 | 2058 | struct intel_context *ctx; |
b4ac5afc | 2059 | int ret; |
c0ab1ae9 BW |
2060 | |
2061 | if (!i915.enable_execlists) { | |
2062 | seq_printf(m, "Logical Ring Contexts are disabled\n"); | |
2063 | return 0; | |
2064 | } | |
2065 | ||
2066 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
2067 | if (ret) | |
2068 | return ret; | |
2069 | ||
e28e404c DG |
2070 | list_for_each_entry(ctx, &dev_priv->context_list, link) |
2071 | if (ctx != dev_priv->kernel_context) | |
b4ac5afc | 2072 | for_each_engine(engine, dev_priv) |
e2f80391 | 2073 | i915_dump_lrc_obj(m, ctx, engine); |
c0ab1ae9 BW |
2074 | |
2075 | mutex_unlock(&dev->struct_mutex); | |
2076 | ||
2077 | return 0; | |
2078 | } | |
2079 | ||
4ba70e44 OM |
2080 | static int i915_execlists(struct seq_file *m, void *data) |
2081 | { | |
2082 | struct drm_info_node *node = (struct drm_info_node *)m->private; | |
2083 | struct drm_device *dev = node->minor->dev; | |
2084 | struct drm_i915_private *dev_priv = dev->dev_private; | |
e2f80391 | 2085 | struct intel_engine_cs *engine; |
4ba70e44 OM |
2086 | u32 status_pointer; |
2087 | u8 read_pointer; | |
2088 | u8 write_pointer; | |
2089 | u32 status; | |
2090 | u32 ctx_id; | |
2091 | struct list_head *cursor; | |
b4ac5afc | 2092 | int i, ret; |
4ba70e44 OM |
2093 | |
2094 | if (!i915.enable_execlists) { | |
2095 | seq_puts(m, "Logical Ring Contexts are disabled\n"); | |
2096 | return 0; | |
2097 | } | |
2098 | ||
2099 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
2100 | if (ret) | |
2101 | return ret; | |
2102 | ||
fc0412ec MT |
2103 | intel_runtime_pm_get(dev_priv); |
2104 | ||
b4ac5afc | 2105 | for_each_engine(engine, dev_priv) { |
6d3d8274 | 2106 | struct drm_i915_gem_request *head_req = NULL; |
4ba70e44 | 2107 | int count = 0; |
4ba70e44 | 2108 | |
e2f80391 | 2109 | seq_printf(m, "%s\n", engine->name); |
4ba70e44 | 2110 | |
e2f80391 TU |
2111 | status = I915_READ(RING_EXECLIST_STATUS_LO(engine)); |
2112 | ctx_id = I915_READ(RING_EXECLIST_STATUS_HI(engine)); | |
4ba70e44 OM |
2113 | seq_printf(m, "\tExeclist status: 0x%08X, context: %u\n", |
2114 | status, ctx_id); | |
2115 | ||
e2f80391 | 2116 | status_pointer = I915_READ(RING_CONTEXT_STATUS_PTR(engine)); |
4ba70e44 OM |
2117 | seq_printf(m, "\tStatus pointer: 0x%08X\n", status_pointer); |
2118 | ||
e2f80391 | 2119 | read_pointer = engine->next_context_status_buffer; |
5590a5f0 | 2120 | write_pointer = GEN8_CSB_WRITE_PTR(status_pointer); |
4ba70e44 | 2121 | if (read_pointer > write_pointer) |
5590a5f0 | 2122 | write_pointer += GEN8_CSB_ENTRIES; |
4ba70e44 OM |
2123 | seq_printf(m, "\tRead pointer: 0x%08X, write pointer 0x%08X\n", |
2124 | read_pointer, write_pointer); | |
2125 | ||
5590a5f0 | 2126 | for (i = 0; i < GEN8_CSB_ENTRIES; i++) { |
e2f80391 TU |
2127 | status = I915_READ(RING_CONTEXT_STATUS_BUF_LO(engine, i)); |
2128 | ctx_id = I915_READ(RING_CONTEXT_STATUS_BUF_HI(engine, i)); | |
4ba70e44 OM |
2129 | |
2130 | seq_printf(m, "\tStatus buffer %d: 0x%08X, context: %u\n", | |
2131 | i, status, ctx_id); | |
2132 | } | |
2133 | ||
27af5eea | 2134 | spin_lock_bh(&engine->execlist_lock); |
e2f80391 | 2135 | list_for_each(cursor, &engine->execlist_queue) |
4ba70e44 | 2136 | count++; |
e2f80391 TU |
2137 | head_req = list_first_entry_or_null(&engine->execlist_queue, |
2138 | struct drm_i915_gem_request, | |
2139 | execlist_link); | |
27af5eea | 2140 | spin_unlock_bh(&engine->execlist_lock); |
4ba70e44 OM |
2141 | |
2142 | seq_printf(m, "\t%d requests in queue\n", count); | |
2143 | if (head_req) { | |
4ba70e44 | 2144 | seq_printf(m, "\tHead request id: %u\n", |
e2f80391 | 2145 | intel_execlists_ctx_id(head_req->ctx, engine)); |
4ba70e44 | 2146 | seq_printf(m, "\tHead request tail: %u\n", |
6d3d8274 | 2147 | head_req->tail); |
4ba70e44 OM |
2148 | } |
2149 | ||
2150 | seq_putc(m, '\n'); | |
2151 | } | |
2152 | ||
fc0412ec | 2153 | intel_runtime_pm_put(dev_priv); |
4ba70e44 OM |
2154 | mutex_unlock(&dev->struct_mutex); |
2155 | ||
2156 | return 0; | |
2157 | } | |
2158 | ||
ea16a3cd DV |
2159 | static const char *swizzle_string(unsigned swizzle) |
2160 | { | |
aee56cff | 2161 | switch (swizzle) { |
ea16a3cd DV |
2162 | case I915_BIT_6_SWIZZLE_NONE: |
2163 | return "none"; | |
2164 | case I915_BIT_6_SWIZZLE_9: | |
2165 | return "bit9"; | |
2166 | case I915_BIT_6_SWIZZLE_9_10: | |
2167 | return "bit9/bit10"; | |
2168 | case I915_BIT_6_SWIZZLE_9_11: | |
2169 | return "bit9/bit11"; | |
2170 | case I915_BIT_6_SWIZZLE_9_10_11: | |
2171 | return "bit9/bit10/bit11"; | |
2172 | case I915_BIT_6_SWIZZLE_9_17: | |
2173 | return "bit9/bit17"; | |
2174 | case I915_BIT_6_SWIZZLE_9_10_17: | |
2175 | return "bit9/bit10/bit17"; | |
2176 | case I915_BIT_6_SWIZZLE_UNKNOWN: | |
8a168ca7 | 2177 | return "unknown"; |
ea16a3cd DV |
2178 | } |
2179 | ||
2180 | return "bug"; | |
2181 | } | |
2182 | ||
2183 | static int i915_swizzle_info(struct seq_file *m, void *data) | |
2184 | { | |
9f25d007 | 2185 | struct drm_info_node *node = m->private; |
ea16a3cd DV |
2186 | struct drm_device *dev = node->minor->dev; |
2187 | struct drm_i915_private *dev_priv = dev->dev_private; | |
22bcfc6a DV |
2188 | int ret; |
2189 | ||
2190 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
2191 | if (ret) | |
2192 | return ret; | |
c8c8fb33 | 2193 | intel_runtime_pm_get(dev_priv); |
ea16a3cd | 2194 | |
ea16a3cd DV |
2195 | seq_printf(m, "bit6 swizzle for X-tiling = %s\n", |
2196 | swizzle_string(dev_priv->mm.bit_6_swizzle_x)); | |
2197 | seq_printf(m, "bit6 swizzle for Y-tiling = %s\n", | |
2198 | swizzle_string(dev_priv->mm.bit_6_swizzle_y)); | |
2199 | ||
2200 | if (IS_GEN3(dev) || IS_GEN4(dev)) { | |
2201 | seq_printf(m, "DDC = 0x%08x\n", | |
2202 | I915_READ(DCC)); | |
656bfa3a DV |
2203 | seq_printf(m, "DDC2 = 0x%08x\n", |
2204 | I915_READ(DCC2)); | |
ea16a3cd DV |
2205 | seq_printf(m, "C0DRB3 = 0x%04x\n", |
2206 | I915_READ16(C0DRB3)); | |
2207 | seq_printf(m, "C1DRB3 = 0x%04x\n", | |
2208 | I915_READ16(C1DRB3)); | |
9d3203e1 | 2209 | } else if (INTEL_INFO(dev)->gen >= 6) { |
3fa7d235 DV |
2210 | seq_printf(m, "MAD_DIMM_C0 = 0x%08x\n", |
2211 | I915_READ(MAD_DIMM_C0)); | |
2212 | seq_printf(m, "MAD_DIMM_C1 = 0x%08x\n", | |
2213 | I915_READ(MAD_DIMM_C1)); | |
2214 | seq_printf(m, "MAD_DIMM_C2 = 0x%08x\n", | |
2215 | I915_READ(MAD_DIMM_C2)); | |
2216 | seq_printf(m, "TILECTL = 0x%08x\n", | |
2217 | I915_READ(TILECTL)); | |
5907f5fb | 2218 | if (INTEL_INFO(dev)->gen >= 8) |
9d3203e1 BW |
2219 | seq_printf(m, "GAMTARBMODE = 0x%08x\n", |
2220 | I915_READ(GAMTARBMODE)); | |
2221 | else | |
2222 | seq_printf(m, "ARB_MODE = 0x%08x\n", | |
2223 | I915_READ(ARB_MODE)); | |
3fa7d235 DV |
2224 | seq_printf(m, "DISP_ARB_CTL = 0x%08x\n", |
2225 | I915_READ(DISP_ARB_CTL)); | |
ea16a3cd | 2226 | } |
656bfa3a DV |
2227 | |
2228 | if (dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES) | |
2229 | seq_puts(m, "L-shaped memory detected\n"); | |
2230 | ||
c8c8fb33 | 2231 | intel_runtime_pm_put(dev_priv); |
ea16a3cd DV |
2232 | mutex_unlock(&dev->struct_mutex); |
2233 | ||
2234 | return 0; | |
2235 | } | |
2236 | ||
1c60fef5 BW |
2237 | static int per_file_ctx(int id, void *ptr, void *data) |
2238 | { | |
273497e5 | 2239 | struct intel_context *ctx = ptr; |
1c60fef5 | 2240 | struct seq_file *m = data; |
ae6c4806 DV |
2241 | struct i915_hw_ppgtt *ppgtt = ctx->ppgtt; |
2242 | ||
2243 | if (!ppgtt) { | |
2244 | seq_printf(m, " no ppgtt for context %d\n", | |
2245 | ctx->user_handle); | |
2246 | return 0; | |
2247 | } | |
1c60fef5 | 2248 | |
f83d6518 OM |
2249 | if (i915_gem_context_is_default(ctx)) |
2250 | seq_puts(m, " default context:\n"); | |
2251 | else | |
821d66dd | 2252 | seq_printf(m, " context %d:\n", ctx->user_handle); |
1c60fef5 BW |
2253 | ppgtt->debug_dump(ppgtt, m); |
2254 | ||
2255 | return 0; | |
2256 | } | |
2257 | ||
77df6772 | 2258 | static void gen8_ppgtt_info(struct seq_file *m, struct drm_device *dev) |
3cf17fc5 | 2259 | { |
3cf17fc5 | 2260 | struct drm_i915_private *dev_priv = dev->dev_private; |
e2f80391 | 2261 | struct intel_engine_cs *engine; |
77df6772 | 2262 | struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt; |
b4ac5afc | 2263 | int i; |
3cf17fc5 | 2264 | |
77df6772 BW |
2265 | if (!ppgtt) |
2266 | return; | |
2267 | ||
b4ac5afc | 2268 | for_each_engine(engine, dev_priv) { |
e2f80391 | 2269 | seq_printf(m, "%s\n", engine->name); |
77df6772 | 2270 | for (i = 0; i < 4; i++) { |
e2f80391 | 2271 | u64 pdp = I915_READ(GEN8_RING_PDP_UDW(engine, i)); |
77df6772 | 2272 | pdp <<= 32; |
e2f80391 | 2273 | pdp |= I915_READ(GEN8_RING_PDP_LDW(engine, i)); |
a2a5b15c | 2274 | seq_printf(m, "\tPDP%d 0x%016llx\n", i, pdp); |
77df6772 BW |
2275 | } |
2276 | } | |
2277 | } | |
2278 | ||
2279 | static void gen6_ppgtt_info(struct seq_file *m, struct drm_device *dev) | |
2280 | { | |
2281 | struct drm_i915_private *dev_priv = dev->dev_private; | |
e2f80391 | 2282 | struct intel_engine_cs *engine; |
3cf17fc5 | 2283 | |
3cf17fc5 DV |
2284 | if (INTEL_INFO(dev)->gen == 6) |
2285 | seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(GFX_MODE)); | |
2286 | ||
b4ac5afc | 2287 | for_each_engine(engine, dev_priv) { |
e2f80391 | 2288 | seq_printf(m, "%s\n", engine->name); |
3cf17fc5 | 2289 | if (INTEL_INFO(dev)->gen == 7) |
e2f80391 TU |
2290 | seq_printf(m, "GFX_MODE: 0x%08x\n", |
2291 | I915_READ(RING_MODE_GEN7(engine))); | |
2292 | seq_printf(m, "PP_DIR_BASE: 0x%08x\n", | |
2293 | I915_READ(RING_PP_DIR_BASE(engine))); | |
2294 | seq_printf(m, "PP_DIR_BASE_READ: 0x%08x\n", | |
2295 | I915_READ(RING_PP_DIR_BASE_READ(engine))); | |
2296 | seq_printf(m, "PP_DIR_DCLV: 0x%08x\n", | |
2297 | I915_READ(RING_PP_DIR_DCLV(engine))); | |
3cf17fc5 DV |
2298 | } |
2299 | if (dev_priv->mm.aliasing_ppgtt) { | |
2300 | struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt; | |
2301 | ||
267f0c90 | 2302 | seq_puts(m, "aliasing PPGTT:\n"); |
44159ddb | 2303 | seq_printf(m, "pd gtt offset: 0x%08x\n", ppgtt->pd.base.ggtt_offset); |
1c60fef5 | 2304 | |
87d60b63 | 2305 | ppgtt->debug_dump(ppgtt, m); |
ae6c4806 | 2306 | } |
1c60fef5 | 2307 | |
3cf17fc5 | 2308 | seq_printf(m, "ECOCHK: 0x%08x\n", I915_READ(GAM_ECOCHK)); |
77df6772 BW |
2309 | } |
2310 | ||
2311 | static int i915_ppgtt_info(struct seq_file *m, void *data) | |
2312 | { | |
9f25d007 | 2313 | struct drm_info_node *node = m->private; |
77df6772 | 2314 | struct drm_device *dev = node->minor->dev; |
c8c8fb33 | 2315 | struct drm_i915_private *dev_priv = dev->dev_private; |
ea91e401 | 2316 | struct drm_file *file; |
77df6772 BW |
2317 | |
2318 | int ret = mutex_lock_interruptible(&dev->struct_mutex); | |
2319 | if (ret) | |
2320 | return ret; | |
c8c8fb33 | 2321 | intel_runtime_pm_get(dev_priv); |
77df6772 BW |
2322 | |
2323 | if (INTEL_INFO(dev)->gen >= 8) | |
2324 | gen8_ppgtt_info(m, dev); | |
2325 | else if (INTEL_INFO(dev)->gen >= 6) | |
2326 | gen6_ppgtt_info(m, dev); | |
2327 | ||
ea91e401 MT |
2328 | list_for_each_entry_reverse(file, &dev->filelist, lhead) { |
2329 | struct drm_i915_file_private *file_priv = file->driver_priv; | |
7cb5dff8 | 2330 | struct task_struct *task; |
ea91e401 | 2331 | |
7cb5dff8 | 2332 | task = get_pid_task(file->pid, PIDTYPE_PID); |
06812760 DC |
2333 | if (!task) { |
2334 | ret = -ESRCH; | |
2335 | goto out_put; | |
2336 | } | |
7cb5dff8 GT |
2337 | seq_printf(m, "\nproc: %s\n", task->comm); |
2338 | put_task_struct(task); | |
ea91e401 MT |
2339 | idr_for_each(&file_priv->context_idr, per_file_ctx, |
2340 | (void *)(unsigned long)m); | |
2341 | } | |
2342 | ||
06812760 | 2343 | out_put: |
c8c8fb33 | 2344 | intel_runtime_pm_put(dev_priv); |
3cf17fc5 DV |
2345 | mutex_unlock(&dev->struct_mutex); |
2346 | ||
06812760 | 2347 | return ret; |
3cf17fc5 DV |
2348 | } |
2349 | ||
f5a4c67d CW |
2350 | static int count_irq_waiters(struct drm_i915_private *i915) |
2351 | { | |
e2f80391 | 2352 | struct intel_engine_cs *engine; |
f5a4c67d | 2353 | int count = 0; |
f5a4c67d | 2354 | |
b4ac5afc | 2355 | for_each_engine(engine, i915) |
e2f80391 | 2356 | count += engine->irq_refcount; |
f5a4c67d CW |
2357 | |
2358 | return count; | |
2359 | } | |
2360 | ||
1854d5ca CW |
2361 | static int i915_rps_boost_info(struct seq_file *m, void *data) |
2362 | { | |
2363 | struct drm_info_node *node = m->private; | |
2364 | struct drm_device *dev = node->minor->dev; | |
2365 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2366 | struct drm_file *file; | |
1854d5ca | 2367 | |
f5a4c67d CW |
2368 | seq_printf(m, "RPS enabled? %d\n", dev_priv->rps.enabled); |
2369 | seq_printf(m, "GPU busy? %d\n", dev_priv->mm.busy); | |
2370 | seq_printf(m, "CPU waiting? %d\n", count_irq_waiters(dev_priv)); | |
2371 | seq_printf(m, "Frequency requested %d; min hard:%d, soft:%d; max soft:%d, hard:%d\n", | |
2372 | intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq), | |
2373 | intel_gpu_freq(dev_priv, dev_priv->rps.min_freq), | |
2374 | intel_gpu_freq(dev_priv, dev_priv->rps.min_freq_softlimit), | |
2375 | intel_gpu_freq(dev_priv, dev_priv->rps.max_freq_softlimit), | |
2376 | intel_gpu_freq(dev_priv, dev_priv->rps.max_freq)); | |
8d3afd7d | 2377 | spin_lock(&dev_priv->rps.client_lock); |
1854d5ca CW |
2378 | list_for_each_entry_reverse(file, &dev->filelist, lhead) { |
2379 | struct drm_i915_file_private *file_priv = file->driver_priv; | |
2380 | struct task_struct *task; | |
2381 | ||
2382 | rcu_read_lock(); | |
2383 | task = pid_task(file->pid, PIDTYPE_PID); | |
2384 | seq_printf(m, "%s [%d]: %d boosts%s\n", | |
2385 | task ? task->comm : "<unknown>", | |
2386 | task ? task->pid : -1, | |
2e1b8730 CW |
2387 | file_priv->rps.boosts, |
2388 | list_empty(&file_priv->rps.link) ? "" : ", active"); | |
1854d5ca CW |
2389 | rcu_read_unlock(); |
2390 | } | |
2e1b8730 CW |
2391 | seq_printf(m, "Semaphore boosts: %d%s\n", |
2392 | dev_priv->rps.semaphores.boosts, | |
2393 | list_empty(&dev_priv->rps.semaphores.link) ? "" : ", active"); | |
2394 | seq_printf(m, "MMIO flip boosts: %d%s\n", | |
2395 | dev_priv->rps.mmioflips.boosts, | |
2396 | list_empty(&dev_priv->rps.mmioflips.link) ? "" : ", active"); | |
1854d5ca | 2397 | seq_printf(m, "Kernel boosts: %d\n", dev_priv->rps.boosts); |
8d3afd7d | 2398 | spin_unlock(&dev_priv->rps.client_lock); |
1854d5ca | 2399 | |
8d3afd7d | 2400 | return 0; |
1854d5ca CW |
2401 | } |
2402 | ||
63573eb7 BW |
2403 | static int i915_llc(struct seq_file *m, void *data) |
2404 | { | |
9f25d007 | 2405 | struct drm_info_node *node = m->private; |
63573eb7 BW |
2406 | struct drm_device *dev = node->minor->dev; |
2407 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2408 | ||
2409 | /* Size calculation for LLC is a bit of a pain. Ignore for now. */ | |
2410 | seq_printf(m, "LLC: %s\n", yesno(HAS_LLC(dev))); | |
2411 | seq_printf(m, "eLLC: %zuMB\n", dev_priv->ellc_size); | |
2412 | ||
2413 | return 0; | |
2414 | } | |
2415 | ||
fdf5d357 AD |
2416 | static int i915_guc_load_status_info(struct seq_file *m, void *data) |
2417 | { | |
2418 | struct drm_info_node *node = m->private; | |
2419 | struct drm_i915_private *dev_priv = node->minor->dev->dev_private; | |
2420 | struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw; | |
2421 | u32 tmp, i; | |
2422 | ||
2d1fe073 | 2423 | if (!HAS_GUC_UCODE(dev_priv)) |
fdf5d357 AD |
2424 | return 0; |
2425 | ||
2426 | seq_printf(m, "GuC firmware status:\n"); | |
2427 | seq_printf(m, "\tpath: %s\n", | |
2428 | guc_fw->guc_fw_path); | |
2429 | seq_printf(m, "\tfetch: %s\n", | |
2430 | intel_guc_fw_status_repr(guc_fw->guc_fw_fetch_status)); | |
2431 | seq_printf(m, "\tload: %s\n", | |
2432 | intel_guc_fw_status_repr(guc_fw->guc_fw_load_status)); | |
2433 | seq_printf(m, "\tversion wanted: %d.%d\n", | |
2434 | guc_fw->guc_fw_major_wanted, guc_fw->guc_fw_minor_wanted); | |
2435 | seq_printf(m, "\tversion found: %d.%d\n", | |
2436 | guc_fw->guc_fw_major_found, guc_fw->guc_fw_minor_found); | |
feda33ef AD |
2437 | seq_printf(m, "\theader: offset is %d; size = %d\n", |
2438 | guc_fw->header_offset, guc_fw->header_size); | |
2439 | seq_printf(m, "\tuCode: offset is %d; size = %d\n", | |
2440 | guc_fw->ucode_offset, guc_fw->ucode_size); | |
2441 | seq_printf(m, "\tRSA: offset is %d; size = %d\n", | |
2442 | guc_fw->rsa_offset, guc_fw->rsa_size); | |
fdf5d357 AD |
2443 | |
2444 | tmp = I915_READ(GUC_STATUS); | |
2445 | ||
2446 | seq_printf(m, "\nGuC status 0x%08x:\n", tmp); | |
2447 | seq_printf(m, "\tBootrom status = 0x%x\n", | |
2448 | (tmp & GS_BOOTROM_MASK) >> GS_BOOTROM_SHIFT); | |
2449 | seq_printf(m, "\tuKernel status = 0x%x\n", | |
2450 | (tmp & GS_UKERNEL_MASK) >> GS_UKERNEL_SHIFT); | |
2451 | seq_printf(m, "\tMIA Core status = 0x%x\n", | |
2452 | (tmp & GS_MIA_MASK) >> GS_MIA_SHIFT); | |
2453 | seq_puts(m, "\nScratch registers:\n"); | |
2454 | for (i = 0; i < 16; i++) | |
2455 | seq_printf(m, "\t%2d: \t0x%x\n", i, I915_READ(SOFT_SCRATCH(i))); | |
2456 | ||
2457 | return 0; | |
2458 | } | |
2459 | ||
8b417c26 DG |
2460 | static void i915_guc_client_info(struct seq_file *m, |
2461 | struct drm_i915_private *dev_priv, | |
2462 | struct i915_guc_client *client) | |
2463 | { | |
e2f80391 | 2464 | struct intel_engine_cs *engine; |
8b417c26 | 2465 | uint64_t tot = 0; |
8b417c26 DG |
2466 | |
2467 | seq_printf(m, "\tPriority %d, GuC ctx index: %u, PD offset 0x%x\n", | |
2468 | client->priority, client->ctx_index, client->proc_desc_offset); | |
2469 | seq_printf(m, "\tDoorbell id %d, offset: 0x%x, cookie 0x%x\n", | |
2470 | client->doorbell_id, client->doorbell_offset, client->cookie); | |
2471 | seq_printf(m, "\tWQ size %d, offset: 0x%x, tail %d\n", | |
2472 | client->wq_size, client->wq_offset, client->wq_tail); | |
2473 | ||
2474 | seq_printf(m, "\tFailed to queue: %u\n", client->q_fail); | |
2475 | seq_printf(m, "\tFailed doorbell: %u\n", client->b_fail); | |
2476 | seq_printf(m, "\tLast submission result: %d\n", client->retcode); | |
2477 | ||
b4ac5afc | 2478 | for_each_engine(engine, dev_priv) { |
8b417c26 | 2479 | seq_printf(m, "\tSubmissions: %llu %s\n", |
e2f80391 TU |
2480 | client->submissions[engine->guc_id], |
2481 | engine->name); | |
2482 | tot += client->submissions[engine->guc_id]; | |
8b417c26 DG |
2483 | } |
2484 | seq_printf(m, "\tTotal: %llu\n", tot); | |
2485 | } | |
2486 | ||
2487 | static int i915_guc_info(struct seq_file *m, void *data) | |
2488 | { | |
2489 | struct drm_info_node *node = m->private; | |
2490 | struct drm_device *dev = node->minor->dev; | |
2491 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2492 | struct intel_guc guc; | |
0a0b457f | 2493 | struct i915_guc_client client = {}; |
e2f80391 | 2494 | struct intel_engine_cs *engine; |
8b417c26 DG |
2495 | u64 total = 0; |
2496 | ||
2d1fe073 | 2497 | if (!HAS_GUC_SCHED(dev_priv)) |
8b417c26 DG |
2498 | return 0; |
2499 | ||
5a843307 AD |
2500 | if (mutex_lock_interruptible(&dev->struct_mutex)) |
2501 | return 0; | |
2502 | ||
8b417c26 | 2503 | /* Take a local copy of the GuC data, so we can dump it at leisure */ |
8b417c26 | 2504 | guc = dev_priv->guc; |
5a843307 | 2505 | if (guc.execbuf_client) |
8b417c26 | 2506 | client = *guc.execbuf_client; |
5a843307 AD |
2507 | |
2508 | mutex_unlock(&dev->struct_mutex); | |
8b417c26 DG |
2509 | |
2510 | seq_printf(m, "GuC total action count: %llu\n", guc.action_count); | |
2511 | seq_printf(m, "GuC action failure count: %u\n", guc.action_fail); | |
2512 | seq_printf(m, "GuC last action command: 0x%x\n", guc.action_cmd); | |
2513 | seq_printf(m, "GuC last action status: 0x%x\n", guc.action_status); | |
2514 | seq_printf(m, "GuC last action error code: %d\n", guc.action_err); | |
2515 | ||
2516 | seq_printf(m, "\nGuC submissions:\n"); | |
b4ac5afc | 2517 | for_each_engine(engine, dev_priv) { |
397097b0 | 2518 | seq_printf(m, "\t%-24s: %10llu, last seqno 0x%08x\n", |
e2f80391 TU |
2519 | engine->name, guc.submissions[engine->guc_id], |
2520 | guc.last_seqno[engine->guc_id]); | |
2521 | total += guc.submissions[engine->guc_id]; | |
8b417c26 DG |
2522 | } |
2523 | seq_printf(m, "\t%s: %llu\n", "Total", total); | |
2524 | ||
2525 | seq_printf(m, "\nGuC execbuf client @ %p:\n", guc.execbuf_client); | |
2526 | i915_guc_client_info(m, dev_priv, &client); | |
2527 | ||
2528 | /* Add more as required ... */ | |
2529 | ||
2530 | return 0; | |
2531 | } | |
2532 | ||
4c7e77fc AD |
2533 | static int i915_guc_log_dump(struct seq_file *m, void *data) |
2534 | { | |
2535 | struct drm_info_node *node = m->private; | |
2536 | struct drm_device *dev = node->minor->dev; | |
2537 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2538 | struct drm_i915_gem_object *log_obj = dev_priv->guc.log_obj; | |
2539 | u32 *log; | |
2540 | int i = 0, pg; | |
2541 | ||
2542 | if (!log_obj) | |
2543 | return 0; | |
2544 | ||
2545 | for (pg = 0; pg < log_obj->base.size / PAGE_SIZE; pg++) { | |
2546 | log = kmap_atomic(i915_gem_object_get_page(log_obj, pg)); | |
2547 | ||
2548 | for (i = 0; i < PAGE_SIZE / sizeof(u32); i += 4) | |
2549 | seq_printf(m, "0x%08x 0x%08x 0x%08x 0x%08x\n", | |
2550 | *(log + i), *(log + i + 1), | |
2551 | *(log + i + 2), *(log + i + 3)); | |
2552 | ||
2553 | kunmap_atomic(log); | |
2554 | } | |
2555 | ||
2556 | seq_putc(m, '\n'); | |
2557 | ||
2558 | return 0; | |
2559 | } | |
2560 | ||
e91fd8c6 RV |
2561 | static int i915_edp_psr_status(struct seq_file *m, void *data) |
2562 | { | |
2563 | struct drm_info_node *node = m->private; | |
2564 | struct drm_device *dev = node->minor->dev; | |
2565 | struct drm_i915_private *dev_priv = dev->dev_private; | |
a031d709 | 2566 | u32 psrperf = 0; |
a6cbdb8e RV |
2567 | u32 stat[3]; |
2568 | enum pipe pipe; | |
a031d709 | 2569 | bool enabled = false; |
e91fd8c6 | 2570 | |
3553a8ea DL |
2571 | if (!HAS_PSR(dev)) { |
2572 | seq_puts(m, "PSR not supported\n"); | |
2573 | return 0; | |
2574 | } | |
2575 | ||
c8c8fb33 PZ |
2576 | intel_runtime_pm_get(dev_priv); |
2577 | ||
fa128fa6 | 2578 | mutex_lock(&dev_priv->psr.lock); |
a031d709 RV |
2579 | seq_printf(m, "Sink_Support: %s\n", yesno(dev_priv->psr.sink_support)); |
2580 | seq_printf(m, "Source_OK: %s\n", yesno(dev_priv->psr.source_ok)); | |
2807cf69 | 2581 | seq_printf(m, "Enabled: %s\n", yesno((bool)dev_priv->psr.enabled)); |
5755c78f | 2582 | seq_printf(m, "Active: %s\n", yesno(dev_priv->psr.active)); |
fa128fa6 DV |
2583 | seq_printf(m, "Busy frontbuffer bits: 0x%03x\n", |
2584 | dev_priv->psr.busy_frontbuffer_bits); | |
2585 | seq_printf(m, "Re-enable work scheduled: %s\n", | |
2586 | yesno(work_busy(&dev_priv->psr.work.work))); | |
e91fd8c6 | 2587 | |
3553a8ea | 2588 | if (HAS_DDI(dev)) |
443a389f | 2589 | enabled = I915_READ(EDP_PSR_CTL) & EDP_PSR_ENABLE; |
3553a8ea DL |
2590 | else { |
2591 | for_each_pipe(dev_priv, pipe) { | |
2592 | stat[pipe] = I915_READ(VLV_PSRSTAT(pipe)) & | |
2593 | VLV_EDP_PSR_CURR_STATE_MASK; | |
2594 | if ((stat[pipe] == VLV_EDP_PSR_ACTIVE_NORFB_UP) || | |
2595 | (stat[pipe] == VLV_EDP_PSR_ACTIVE_SF_UPDATE)) | |
2596 | enabled = true; | |
a6cbdb8e RV |
2597 | } |
2598 | } | |
60e5ffe3 RV |
2599 | |
2600 | seq_printf(m, "Main link in standby mode: %s\n", | |
2601 | yesno(dev_priv->psr.link_standby)); | |
2602 | ||
a6cbdb8e RV |
2603 | seq_printf(m, "HW Enabled & Active bit: %s", yesno(enabled)); |
2604 | ||
2605 | if (!HAS_DDI(dev)) | |
2606 | for_each_pipe(dev_priv, pipe) { | |
2607 | if ((stat[pipe] == VLV_EDP_PSR_ACTIVE_NORFB_UP) || | |
2608 | (stat[pipe] == VLV_EDP_PSR_ACTIVE_SF_UPDATE)) | |
2609 | seq_printf(m, " pipe %c", pipe_name(pipe)); | |
2610 | } | |
2611 | seq_puts(m, "\n"); | |
e91fd8c6 | 2612 | |
05eec3c2 RV |
2613 | /* |
2614 | * VLV/CHV PSR has no kind of performance counter | |
2615 | * SKL+ Perf counter is reset to 0 everytime DC state is entered | |
2616 | */ | |
2617 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { | |
443a389f | 2618 | psrperf = I915_READ(EDP_PSR_PERF_CNT) & |
a031d709 | 2619 | EDP_PSR_PERF_CNT_MASK; |
a6cbdb8e RV |
2620 | |
2621 | seq_printf(m, "Performance_Counter: %u\n", psrperf); | |
2622 | } | |
fa128fa6 | 2623 | mutex_unlock(&dev_priv->psr.lock); |
e91fd8c6 | 2624 | |
c8c8fb33 | 2625 | intel_runtime_pm_put(dev_priv); |
e91fd8c6 RV |
2626 | return 0; |
2627 | } | |
2628 | ||
d2e216d0 RV |
2629 | static int i915_sink_crc(struct seq_file *m, void *data) |
2630 | { | |
2631 | struct drm_info_node *node = m->private; | |
2632 | struct drm_device *dev = node->minor->dev; | |
2633 | struct intel_encoder *encoder; | |
2634 | struct intel_connector *connector; | |
2635 | struct intel_dp *intel_dp = NULL; | |
2636 | int ret; | |
2637 | u8 crc[6]; | |
2638 | ||
2639 | drm_modeset_lock_all(dev); | |
aca5e361 | 2640 | for_each_intel_connector(dev, connector) { |
d2e216d0 RV |
2641 | |
2642 | if (connector->base.dpms != DRM_MODE_DPMS_ON) | |
2643 | continue; | |
2644 | ||
b6ae3c7c PZ |
2645 | if (!connector->base.encoder) |
2646 | continue; | |
2647 | ||
d2e216d0 RV |
2648 | encoder = to_intel_encoder(connector->base.encoder); |
2649 | if (encoder->type != INTEL_OUTPUT_EDP) | |
2650 | continue; | |
2651 | ||
2652 | intel_dp = enc_to_intel_dp(&encoder->base); | |
2653 | ||
2654 | ret = intel_dp_sink_crc(intel_dp, crc); | |
2655 | if (ret) | |
2656 | goto out; | |
2657 | ||
2658 | seq_printf(m, "%02x%02x%02x%02x%02x%02x\n", | |
2659 | crc[0], crc[1], crc[2], | |
2660 | crc[3], crc[4], crc[5]); | |
2661 | goto out; | |
2662 | } | |
2663 | ret = -ENODEV; | |
2664 | out: | |
2665 | drm_modeset_unlock_all(dev); | |
2666 | return ret; | |
2667 | } | |
2668 | ||
ec013e7f JB |
2669 | static int i915_energy_uJ(struct seq_file *m, void *data) |
2670 | { | |
2671 | struct drm_info_node *node = m->private; | |
2672 | struct drm_device *dev = node->minor->dev; | |
2673 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2674 | u64 power; | |
2675 | u32 units; | |
2676 | ||
2677 | if (INTEL_INFO(dev)->gen < 6) | |
2678 | return -ENODEV; | |
2679 | ||
36623ef8 PZ |
2680 | intel_runtime_pm_get(dev_priv); |
2681 | ||
ec013e7f JB |
2682 | rdmsrl(MSR_RAPL_POWER_UNIT, power); |
2683 | power = (power & 0x1f00) >> 8; | |
2684 | units = 1000000 / (1 << power); /* convert to uJ */ | |
2685 | power = I915_READ(MCH_SECP_NRG_STTS); | |
2686 | power *= units; | |
2687 | ||
36623ef8 PZ |
2688 | intel_runtime_pm_put(dev_priv); |
2689 | ||
ec013e7f | 2690 | seq_printf(m, "%llu", (long long unsigned)power); |
371db66a PZ |
2691 | |
2692 | return 0; | |
2693 | } | |
2694 | ||
6455c870 | 2695 | static int i915_runtime_pm_status(struct seq_file *m, void *unused) |
371db66a | 2696 | { |
9f25d007 | 2697 | struct drm_info_node *node = m->private; |
371db66a PZ |
2698 | struct drm_device *dev = node->minor->dev; |
2699 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2700 | ||
a156e64d CW |
2701 | if (!HAS_RUNTIME_PM(dev_priv)) |
2702 | seq_puts(m, "Runtime power management not supported\n"); | |
371db66a | 2703 | |
86c4ec0d | 2704 | seq_printf(m, "GPU idle: %s\n", yesno(!dev_priv->mm.busy)); |
371db66a | 2705 | seq_printf(m, "IRQs disabled: %s\n", |
9df7575f | 2706 | yesno(!intel_irqs_enabled(dev_priv))); |
0d804184 | 2707 | #ifdef CONFIG_PM |
a6aaec8b DL |
2708 | seq_printf(m, "Usage count: %d\n", |
2709 | atomic_read(&dev->dev->power.usage_count)); | |
0d804184 CW |
2710 | #else |
2711 | seq_printf(m, "Device Power Management (CONFIG_PM) disabled\n"); | |
2712 | #endif | |
a156e64d CW |
2713 | seq_printf(m, "PCI device power state: %s [%d]\n", |
2714 | pci_power_name(dev_priv->dev->pdev->current_state), | |
2715 | dev_priv->dev->pdev->current_state); | |
371db66a | 2716 | |
ec013e7f JB |
2717 | return 0; |
2718 | } | |
2719 | ||
1da51581 ID |
2720 | static int i915_power_domain_info(struct seq_file *m, void *unused) |
2721 | { | |
9f25d007 | 2722 | struct drm_info_node *node = m->private; |
1da51581 ID |
2723 | struct drm_device *dev = node->minor->dev; |
2724 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2725 | struct i915_power_domains *power_domains = &dev_priv->power_domains; | |
2726 | int i; | |
2727 | ||
2728 | mutex_lock(&power_domains->lock); | |
2729 | ||
2730 | seq_printf(m, "%-25s %s\n", "Power well/domain", "Use count"); | |
2731 | for (i = 0; i < power_domains->power_well_count; i++) { | |
2732 | struct i915_power_well *power_well; | |
2733 | enum intel_display_power_domain power_domain; | |
2734 | ||
2735 | power_well = &power_domains->power_wells[i]; | |
2736 | seq_printf(m, "%-25s %d\n", power_well->name, | |
2737 | power_well->count); | |
2738 | ||
2739 | for (power_domain = 0; power_domain < POWER_DOMAIN_NUM; | |
2740 | power_domain++) { | |
2741 | if (!(BIT(power_domain) & power_well->domains)) | |
2742 | continue; | |
2743 | ||
2744 | seq_printf(m, " %-23s %d\n", | |
9895ad03 | 2745 | intel_display_power_domain_str(power_domain), |
1da51581 ID |
2746 | power_domains->domain_use_count[power_domain]); |
2747 | } | |
2748 | } | |
2749 | ||
2750 | mutex_unlock(&power_domains->lock); | |
2751 | ||
2752 | return 0; | |
2753 | } | |
2754 | ||
b7cec66d DL |
2755 | static int i915_dmc_info(struct seq_file *m, void *unused) |
2756 | { | |
2757 | struct drm_info_node *node = m->private; | |
2758 | struct drm_device *dev = node->minor->dev; | |
2759 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2760 | struct intel_csr *csr; | |
2761 | ||
2762 | if (!HAS_CSR(dev)) { | |
2763 | seq_puts(m, "not supported\n"); | |
2764 | return 0; | |
2765 | } | |
2766 | ||
2767 | csr = &dev_priv->csr; | |
2768 | ||
6fb403de MK |
2769 | intel_runtime_pm_get(dev_priv); |
2770 | ||
b7cec66d DL |
2771 | seq_printf(m, "fw loaded: %s\n", yesno(csr->dmc_payload != NULL)); |
2772 | seq_printf(m, "path: %s\n", csr->fw_path); | |
2773 | ||
2774 | if (!csr->dmc_payload) | |
6fb403de | 2775 | goto out; |
b7cec66d DL |
2776 | |
2777 | seq_printf(m, "version: %d.%d\n", CSR_VERSION_MAJOR(csr->version), | |
2778 | CSR_VERSION_MINOR(csr->version)); | |
2779 | ||
8337206d DL |
2780 | if (IS_SKYLAKE(dev) && csr->version >= CSR_VERSION(1, 6)) { |
2781 | seq_printf(m, "DC3 -> DC5 count: %d\n", | |
2782 | I915_READ(SKL_CSR_DC3_DC5_COUNT)); | |
2783 | seq_printf(m, "DC5 -> DC6 count: %d\n", | |
2784 | I915_READ(SKL_CSR_DC5_DC6_COUNT)); | |
16e11b99 MK |
2785 | } else if (IS_BROXTON(dev) && csr->version >= CSR_VERSION(1, 4)) { |
2786 | seq_printf(m, "DC3 -> DC5 count: %d\n", | |
2787 | I915_READ(BXT_CSR_DC3_DC5_COUNT)); | |
8337206d DL |
2788 | } |
2789 | ||
6fb403de MK |
2790 | out: |
2791 | seq_printf(m, "program base: 0x%08x\n", I915_READ(CSR_PROGRAM(0))); | |
2792 | seq_printf(m, "ssp base: 0x%08x\n", I915_READ(CSR_SSP_BASE)); | |
2793 | seq_printf(m, "htp: 0x%08x\n", I915_READ(CSR_HTP_SKL)); | |
2794 | ||
8337206d DL |
2795 | intel_runtime_pm_put(dev_priv); |
2796 | ||
b7cec66d DL |
2797 | return 0; |
2798 | } | |
2799 | ||
53f5e3ca JB |
2800 | static void intel_seq_print_mode(struct seq_file *m, int tabs, |
2801 | struct drm_display_mode *mode) | |
2802 | { | |
2803 | int i; | |
2804 | ||
2805 | for (i = 0; i < tabs; i++) | |
2806 | seq_putc(m, '\t'); | |
2807 | ||
2808 | seq_printf(m, "id %d:\"%s\" freq %d clock %d hdisp %d hss %d hse %d htot %d vdisp %d vss %d vse %d vtot %d type 0x%x flags 0x%x\n", | |
2809 | mode->base.id, mode->name, | |
2810 | mode->vrefresh, mode->clock, | |
2811 | mode->hdisplay, mode->hsync_start, | |
2812 | mode->hsync_end, mode->htotal, | |
2813 | mode->vdisplay, mode->vsync_start, | |
2814 | mode->vsync_end, mode->vtotal, | |
2815 | mode->type, mode->flags); | |
2816 | } | |
2817 | ||
2818 | static void intel_encoder_info(struct seq_file *m, | |
2819 | struct intel_crtc *intel_crtc, | |
2820 | struct intel_encoder *intel_encoder) | |
2821 | { | |
9f25d007 | 2822 | struct drm_info_node *node = m->private; |
53f5e3ca JB |
2823 | struct drm_device *dev = node->minor->dev; |
2824 | struct drm_crtc *crtc = &intel_crtc->base; | |
2825 | struct intel_connector *intel_connector; | |
2826 | struct drm_encoder *encoder; | |
2827 | ||
2828 | encoder = &intel_encoder->base; | |
2829 | seq_printf(m, "\tencoder %d: type: %s, connectors:\n", | |
8e329a03 | 2830 | encoder->base.id, encoder->name); |
53f5e3ca JB |
2831 | for_each_connector_on_encoder(dev, encoder, intel_connector) { |
2832 | struct drm_connector *connector = &intel_connector->base; | |
2833 | seq_printf(m, "\t\tconnector %d: type: %s, status: %s", | |
2834 | connector->base.id, | |
c23cc417 | 2835 | connector->name, |
53f5e3ca JB |
2836 | drm_get_connector_status_name(connector->status)); |
2837 | if (connector->status == connector_status_connected) { | |
2838 | struct drm_display_mode *mode = &crtc->mode; | |
2839 | seq_printf(m, ", mode:\n"); | |
2840 | intel_seq_print_mode(m, 2, mode); | |
2841 | } else { | |
2842 | seq_putc(m, '\n'); | |
2843 | } | |
2844 | } | |
2845 | } | |
2846 | ||
2847 | static void intel_crtc_info(struct seq_file *m, struct intel_crtc *intel_crtc) | |
2848 | { | |
9f25d007 | 2849 | struct drm_info_node *node = m->private; |
53f5e3ca JB |
2850 | struct drm_device *dev = node->minor->dev; |
2851 | struct drm_crtc *crtc = &intel_crtc->base; | |
2852 | struct intel_encoder *intel_encoder; | |
23a48d53 ML |
2853 | struct drm_plane_state *plane_state = crtc->primary->state; |
2854 | struct drm_framebuffer *fb = plane_state->fb; | |
53f5e3ca | 2855 | |
23a48d53 | 2856 | if (fb) |
5aa8a937 | 2857 | seq_printf(m, "\tfb: %d, pos: %dx%d, size: %dx%d\n", |
23a48d53 ML |
2858 | fb->base.id, plane_state->src_x >> 16, |
2859 | plane_state->src_y >> 16, fb->width, fb->height); | |
5aa8a937 MR |
2860 | else |
2861 | seq_puts(m, "\tprimary plane disabled\n"); | |
53f5e3ca JB |
2862 | for_each_encoder_on_crtc(dev, crtc, intel_encoder) |
2863 | intel_encoder_info(m, intel_crtc, intel_encoder); | |
2864 | } | |
2865 | ||
2866 | static void intel_panel_info(struct seq_file *m, struct intel_panel *panel) | |
2867 | { | |
2868 | struct drm_display_mode *mode = panel->fixed_mode; | |
2869 | ||
2870 | seq_printf(m, "\tfixed mode:\n"); | |
2871 | intel_seq_print_mode(m, 2, mode); | |
2872 | } | |
2873 | ||
2874 | static void intel_dp_info(struct seq_file *m, | |
2875 | struct intel_connector *intel_connector) | |
2876 | { | |
2877 | struct intel_encoder *intel_encoder = intel_connector->encoder; | |
2878 | struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base); | |
2879 | ||
2880 | seq_printf(m, "\tDPCD rev: %x\n", intel_dp->dpcd[DP_DPCD_REV]); | |
742f491d | 2881 | seq_printf(m, "\taudio support: %s\n", yesno(intel_dp->has_audio)); |
53f5e3ca JB |
2882 | if (intel_encoder->type == INTEL_OUTPUT_EDP) |
2883 | intel_panel_info(m, &intel_connector->panel); | |
2884 | } | |
2885 | ||
3d52ccf5 LY |
2886 | static void intel_dp_mst_info(struct seq_file *m, |
2887 | struct intel_connector *intel_connector) | |
2888 | { | |
2889 | struct intel_encoder *intel_encoder = intel_connector->encoder; | |
2890 | struct intel_dp_mst_encoder *intel_mst = | |
2891 | enc_to_mst(&intel_encoder->base); | |
2892 | struct intel_digital_port *intel_dig_port = intel_mst->primary; | |
2893 | struct intel_dp *intel_dp = &intel_dig_port->dp; | |
2894 | bool has_audio = drm_dp_mst_port_has_audio(&intel_dp->mst_mgr, | |
2895 | intel_connector->port); | |
2896 | ||
2897 | seq_printf(m, "\taudio support: %s\n", yesno(has_audio)); | |
2898 | } | |
2899 | ||
53f5e3ca JB |
2900 | static void intel_hdmi_info(struct seq_file *m, |
2901 | struct intel_connector *intel_connector) | |
2902 | { | |
2903 | struct intel_encoder *intel_encoder = intel_connector->encoder; | |
2904 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&intel_encoder->base); | |
2905 | ||
742f491d | 2906 | seq_printf(m, "\taudio support: %s\n", yesno(intel_hdmi->has_audio)); |
53f5e3ca JB |
2907 | } |
2908 | ||
2909 | static void intel_lvds_info(struct seq_file *m, | |
2910 | struct intel_connector *intel_connector) | |
2911 | { | |
2912 | intel_panel_info(m, &intel_connector->panel); | |
2913 | } | |
2914 | ||
2915 | static void intel_connector_info(struct seq_file *m, | |
2916 | struct drm_connector *connector) | |
2917 | { | |
2918 | struct intel_connector *intel_connector = to_intel_connector(connector); | |
2919 | struct intel_encoder *intel_encoder = intel_connector->encoder; | |
f103fc7d | 2920 | struct drm_display_mode *mode; |
53f5e3ca JB |
2921 | |
2922 | seq_printf(m, "connector %d: type %s, status: %s\n", | |
c23cc417 | 2923 | connector->base.id, connector->name, |
53f5e3ca JB |
2924 | drm_get_connector_status_name(connector->status)); |
2925 | if (connector->status == connector_status_connected) { | |
2926 | seq_printf(m, "\tname: %s\n", connector->display_info.name); | |
2927 | seq_printf(m, "\tphysical dimensions: %dx%dmm\n", | |
2928 | connector->display_info.width_mm, | |
2929 | connector->display_info.height_mm); | |
2930 | seq_printf(m, "\tsubpixel order: %s\n", | |
2931 | drm_get_subpixel_order_name(connector->display_info.subpixel_order)); | |
2932 | seq_printf(m, "\tCEA rev: %d\n", | |
2933 | connector->display_info.cea_rev); | |
2934 | } | |
36cd7444 DA |
2935 | if (intel_encoder) { |
2936 | if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT || | |
2937 | intel_encoder->type == INTEL_OUTPUT_EDP) | |
2938 | intel_dp_info(m, intel_connector); | |
2939 | else if (intel_encoder->type == INTEL_OUTPUT_HDMI) | |
2940 | intel_hdmi_info(m, intel_connector); | |
2941 | else if (intel_encoder->type == INTEL_OUTPUT_LVDS) | |
2942 | intel_lvds_info(m, intel_connector); | |
3d52ccf5 LY |
2943 | else if (intel_encoder->type == INTEL_OUTPUT_DP_MST) |
2944 | intel_dp_mst_info(m, intel_connector); | |
36cd7444 | 2945 | } |
53f5e3ca | 2946 | |
f103fc7d JB |
2947 | seq_printf(m, "\tmodes:\n"); |
2948 | list_for_each_entry(mode, &connector->modes, head) | |
2949 | intel_seq_print_mode(m, 2, mode); | |
53f5e3ca JB |
2950 | } |
2951 | ||
065f2ec2 CW |
2952 | static bool cursor_active(struct drm_device *dev, int pipe) |
2953 | { | |
2954 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2955 | u32 state; | |
2956 | ||
2957 | if (IS_845G(dev) || IS_I865G(dev)) | |
0b87c24e | 2958 | state = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE; |
065f2ec2 | 2959 | else |
5efb3e28 | 2960 | state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE; |
065f2ec2 CW |
2961 | |
2962 | return state; | |
2963 | } | |
2964 | ||
2965 | static bool cursor_position(struct drm_device *dev, int pipe, int *x, int *y) | |
2966 | { | |
2967 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2968 | u32 pos; | |
2969 | ||
5efb3e28 | 2970 | pos = I915_READ(CURPOS(pipe)); |
065f2ec2 CW |
2971 | |
2972 | *x = (pos >> CURSOR_X_SHIFT) & CURSOR_POS_MASK; | |
2973 | if (pos & (CURSOR_POS_SIGN << CURSOR_X_SHIFT)) | |
2974 | *x = -*x; | |
2975 | ||
2976 | *y = (pos >> CURSOR_Y_SHIFT) & CURSOR_POS_MASK; | |
2977 | if (pos & (CURSOR_POS_SIGN << CURSOR_Y_SHIFT)) | |
2978 | *y = -*y; | |
2979 | ||
2980 | return cursor_active(dev, pipe); | |
2981 | } | |
2982 | ||
3abc4e09 RF |
2983 | static const char *plane_type(enum drm_plane_type type) |
2984 | { | |
2985 | switch (type) { | |
2986 | case DRM_PLANE_TYPE_OVERLAY: | |
2987 | return "OVL"; | |
2988 | case DRM_PLANE_TYPE_PRIMARY: | |
2989 | return "PRI"; | |
2990 | case DRM_PLANE_TYPE_CURSOR: | |
2991 | return "CUR"; | |
2992 | /* | |
2993 | * Deliberately omitting default: to generate compiler warnings | |
2994 | * when a new drm_plane_type gets added. | |
2995 | */ | |
2996 | } | |
2997 | ||
2998 | return "unknown"; | |
2999 | } | |
3000 | ||
3001 | static const char *plane_rotation(unsigned int rotation) | |
3002 | { | |
3003 | static char buf[48]; | |
3004 | /* | |
3005 | * According to doc only one DRM_ROTATE_ is allowed but this | |
3006 | * will print them all to visualize if the values are misused | |
3007 | */ | |
3008 | snprintf(buf, sizeof(buf), | |
3009 | "%s%s%s%s%s%s(0x%08x)", | |
3010 | (rotation & BIT(DRM_ROTATE_0)) ? "0 " : "", | |
3011 | (rotation & BIT(DRM_ROTATE_90)) ? "90 " : "", | |
3012 | (rotation & BIT(DRM_ROTATE_180)) ? "180 " : "", | |
3013 | (rotation & BIT(DRM_ROTATE_270)) ? "270 " : "", | |
3014 | (rotation & BIT(DRM_REFLECT_X)) ? "FLIPX " : "", | |
3015 | (rotation & BIT(DRM_REFLECT_Y)) ? "FLIPY " : "", | |
3016 | rotation); | |
3017 | ||
3018 | return buf; | |
3019 | } | |
3020 | ||
3021 | static void intel_plane_info(struct seq_file *m, struct intel_crtc *intel_crtc) | |
3022 | { | |
3023 | struct drm_info_node *node = m->private; | |
3024 | struct drm_device *dev = node->minor->dev; | |
3025 | struct intel_plane *intel_plane; | |
3026 | ||
3027 | for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) { | |
3028 | struct drm_plane_state *state; | |
3029 | struct drm_plane *plane = &intel_plane->base; | |
3030 | ||
3031 | if (!plane->state) { | |
3032 | seq_puts(m, "plane->state is NULL!\n"); | |
3033 | continue; | |
3034 | } | |
3035 | ||
3036 | state = plane->state; | |
3037 | ||
3038 | seq_printf(m, "\t--Plane id %d: type=%s, crtc_pos=%4dx%4d, crtc_size=%4dx%4d, src_pos=%d.%04ux%d.%04u, src_size=%d.%04ux%d.%04u, format=%s, rotation=%s\n", | |
3039 | plane->base.id, | |
3040 | plane_type(intel_plane->base.type), | |
3041 | state->crtc_x, state->crtc_y, | |
3042 | state->crtc_w, state->crtc_h, | |
3043 | (state->src_x >> 16), | |
3044 | ((state->src_x & 0xffff) * 15625) >> 10, | |
3045 | (state->src_y >> 16), | |
3046 | ((state->src_y & 0xffff) * 15625) >> 10, | |
3047 | (state->src_w >> 16), | |
3048 | ((state->src_w & 0xffff) * 15625) >> 10, | |
3049 | (state->src_h >> 16), | |
3050 | ((state->src_h & 0xffff) * 15625) >> 10, | |
3051 | state->fb ? drm_get_format_name(state->fb->pixel_format) : "N/A", | |
3052 | plane_rotation(state->rotation)); | |
3053 | } | |
3054 | } | |
3055 | ||
3056 | static void intel_scaler_info(struct seq_file *m, struct intel_crtc *intel_crtc) | |
3057 | { | |
3058 | struct intel_crtc_state *pipe_config; | |
3059 | int num_scalers = intel_crtc->num_scalers; | |
3060 | int i; | |
3061 | ||
3062 | pipe_config = to_intel_crtc_state(intel_crtc->base.state); | |
3063 | ||
3064 | /* Not all platformas have a scaler */ | |
3065 | if (num_scalers) { | |
3066 | seq_printf(m, "\tnum_scalers=%d, scaler_users=%x scaler_id=%d", | |
3067 | num_scalers, | |
3068 | pipe_config->scaler_state.scaler_users, | |
3069 | pipe_config->scaler_state.scaler_id); | |
3070 | ||
3071 | for (i = 0; i < SKL_NUM_SCALERS; i++) { | |
3072 | struct intel_scaler *sc = | |
3073 | &pipe_config->scaler_state.scalers[i]; | |
3074 | ||
3075 | seq_printf(m, ", scalers[%d]: use=%s, mode=%x", | |
3076 | i, yesno(sc->in_use), sc->mode); | |
3077 | } | |
3078 | seq_puts(m, "\n"); | |
3079 | } else { | |
3080 | seq_puts(m, "\tNo scalers available on this platform\n"); | |
3081 | } | |
3082 | } | |
3083 | ||
53f5e3ca JB |
3084 | static int i915_display_info(struct seq_file *m, void *unused) |
3085 | { | |
9f25d007 | 3086 | struct drm_info_node *node = m->private; |
53f5e3ca | 3087 | struct drm_device *dev = node->minor->dev; |
b0e5ddf3 | 3088 | struct drm_i915_private *dev_priv = dev->dev_private; |
065f2ec2 | 3089 | struct intel_crtc *crtc; |
53f5e3ca JB |
3090 | struct drm_connector *connector; |
3091 | ||
b0e5ddf3 | 3092 | intel_runtime_pm_get(dev_priv); |
53f5e3ca JB |
3093 | drm_modeset_lock_all(dev); |
3094 | seq_printf(m, "CRTC info\n"); | |
3095 | seq_printf(m, "---------\n"); | |
d3fcc808 | 3096 | for_each_intel_crtc(dev, crtc) { |
065f2ec2 | 3097 | bool active; |
f77076c9 | 3098 | struct intel_crtc_state *pipe_config; |
065f2ec2 | 3099 | int x, y; |
53f5e3ca | 3100 | |
f77076c9 ML |
3101 | pipe_config = to_intel_crtc_state(crtc->base.state); |
3102 | ||
3abc4e09 | 3103 | seq_printf(m, "CRTC %d: pipe: %c, active=%s, (size=%dx%d), dither=%s, bpp=%d\n", |
065f2ec2 | 3104 | crtc->base.base.id, pipe_name(crtc->pipe), |
f77076c9 | 3105 | yesno(pipe_config->base.active), |
3abc4e09 RF |
3106 | pipe_config->pipe_src_w, pipe_config->pipe_src_h, |
3107 | yesno(pipe_config->dither), pipe_config->pipe_bpp); | |
3108 | ||
f77076c9 | 3109 | if (pipe_config->base.active) { |
065f2ec2 CW |
3110 | intel_crtc_info(m, crtc); |
3111 | ||
a23dc658 | 3112 | active = cursor_position(dev, crtc->pipe, &x, &y); |
57127efa | 3113 | seq_printf(m, "\tcursor visible? %s, position (%d, %d), size %dx%d, addr 0x%08x, active? %s\n", |
4b0e333e | 3114 | yesno(crtc->cursor_base), |
3dd512fb MR |
3115 | x, y, crtc->base.cursor->state->crtc_w, |
3116 | crtc->base.cursor->state->crtc_h, | |
57127efa | 3117 | crtc->cursor_addr, yesno(active)); |
3abc4e09 RF |
3118 | intel_scaler_info(m, crtc); |
3119 | intel_plane_info(m, crtc); | |
a23dc658 | 3120 | } |
cace841c DV |
3121 | |
3122 | seq_printf(m, "\tunderrun reporting: cpu=%s pch=%s \n", | |
3123 | yesno(!crtc->cpu_fifo_underrun_disabled), | |
3124 | yesno(!crtc->pch_fifo_underrun_disabled)); | |
53f5e3ca JB |
3125 | } |
3126 | ||
3127 | seq_printf(m, "\n"); | |
3128 | seq_printf(m, "Connector info\n"); | |
3129 | seq_printf(m, "--------------\n"); | |
3130 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { | |
3131 | intel_connector_info(m, connector); | |
3132 | } | |
3133 | drm_modeset_unlock_all(dev); | |
b0e5ddf3 | 3134 | intel_runtime_pm_put(dev_priv); |
53f5e3ca JB |
3135 | |
3136 | return 0; | |
3137 | } | |
3138 | ||
e04934cf BW |
3139 | static int i915_semaphore_status(struct seq_file *m, void *unused) |
3140 | { | |
3141 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
3142 | struct drm_device *dev = node->minor->dev; | |
3143 | struct drm_i915_private *dev_priv = dev->dev_private; | |
e2f80391 | 3144 | struct intel_engine_cs *engine; |
e04934cf | 3145 | int num_rings = hweight32(INTEL_INFO(dev)->ring_mask); |
c3232b18 DG |
3146 | enum intel_engine_id id; |
3147 | int j, ret; | |
e04934cf BW |
3148 | |
3149 | if (!i915_semaphore_is_enabled(dev)) { | |
3150 | seq_puts(m, "Semaphores are disabled\n"); | |
3151 | return 0; | |
3152 | } | |
3153 | ||
3154 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
3155 | if (ret) | |
3156 | return ret; | |
03872064 | 3157 | intel_runtime_pm_get(dev_priv); |
e04934cf BW |
3158 | |
3159 | if (IS_BROADWELL(dev)) { | |
3160 | struct page *page; | |
3161 | uint64_t *seqno; | |
3162 | ||
3163 | page = i915_gem_object_get_page(dev_priv->semaphore_obj, 0); | |
3164 | ||
3165 | seqno = (uint64_t *)kmap_atomic(page); | |
c3232b18 | 3166 | for_each_engine_id(engine, dev_priv, id) { |
e04934cf BW |
3167 | uint64_t offset; |
3168 | ||
e2f80391 | 3169 | seq_printf(m, "%s\n", engine->name); |
e04934cf BW |
3170 | |
3171 | seq_puts(m, " Last signal:"); | |
3172 | for (j = 0; j < num_rings; j++) { | |
c3232b18 | 3173 | offset = id * I915_NUM_ENGINES + j; |
e04934cf BW |
3174 | seq_printf(m, "0x%08llx (0x%02llx) ", |
3175 | seqno[offset], offset * 8); | |
3176 | } | |
3177 | seq_putc(m, '\n'); | |
3178 | ||
3179 | seq_puts(m, " Last wait: "); | |
3180 | for (j = 0; j < num_rings; j++) { | |
c3232b18 | 3181 | offset = id + (j * I915_NUM_ENGINES); |
e04934cf BW |
3182 | seq_printf(m, "0x%08llx (0x%02llx) ", |
3183 | seqno[offset], offset * 8); | |
3184 | } | |
3185 | seq_putc(m, '\n'); | |
3186 | ||
3187 | } | |
3188 | kunmap_atomic(seqno); | |
3189 | } else { | |
3190 | seq_puts(m, " Last signal:"); | |
b4ac5afc | 3191 | for_each_engine(engine, dev_priv) |
e04934cf BW |
3192 | for (j = 0; j < num_rings; j++) |
3193 | seq_printf(m, "0x%08x\n", | |
e2f80391 | 3194 | I915_READ(engine->semaphore.mbox.signal[j])); |
e04934cf BW |
3195 | seq_putc(m, '\n'); |
3196 | } | |
3197 | ||
3198 | seq_puts(m, "\nSync seqno:\n"); | |
b4ac5afc DG |
3199 | for_each_engine(engine, dev_priv) { |
3200 | for (j = 0; j < num_rings; j++) | |
e2f80391 TU |
3201 | seq_printf(m, " 0x%08x ", |
3202 | engine->semaphore.sync_seqno[j]); | |
e04934cf BW |
3203 | seq_putc(m, '\n'); |
3204 | } | |
3205 | seq_putc(m, '\n'); | |
3206 | ||
03872064 | 3207 | intel_runtime_pm_put(dev_priv); |
e04934cf BW |
3208 | mutex_unlock(&dev->struct_mutex); |
3209 | return 0; | |
3210 | } | |
3211 | ||
728e29d7 DV |
3212 | static int i915_shared_dplls_info(struct seq_file *m, void *unused) |
3213 | { | |
3214 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
3215 | struct drm_device *dev = node->minor->dev; | |
3216 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3217 | int i; | |
3218 | ||
3219 | drm_modeset_lock_all(dev); | |
3220 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { | |
3221 | struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; | |
3222 | ||
3223 | seq_printf(m, "DPLL%i: %s, id: %i\n", i, pll->name, pll->id); | |
2dd66ebd ML |
3224 | seq_printf(m, " crtc_mask: 0x%08x, active: 0x%x, on: %s\n", |
3225 | pll->config.crtc_mask, pll->active_mask, yesno(pll->on)); | |
728e29d7 | 3226 | seq_printf(m, " tracked hardware state:\n"); |
3e369b76 ACO |
3227 | seq_printf(m, " dpll: 0x%08x\n", pll->config.hw_state.dpll); |
3228 | seq_printf(m, " dpll_md: 0x%08x\n", | |
3229 | pll->config.hw_state.dpll_md); | |
3230 | seq_printf(m, " fp0: 0x%08x\n", pll->config.hw_state.fp0); | |
3231 | seq_printf(m, " fp1: 0x%08x\n", pll->config.hw_state.fp1); | |
3232 | seq_printf(m, " wrpll: 0x%08x\n", pll->config.hw_state.wrpll); | |
728e29d7 DV |
3233 | } |
3234 | drm_modeset_unlock_all(dev); | |
3235 | ||
3236 | return 0; | |
3237 | } | |
3238 | ||
1ed1ef9d | 3239 | static int i915_wa_registers(struct seq_file *m, void *unused) |
888b5995 AS |
3240 | { |
3241 | int i; | |
3242 | int ret; | |
e2f80391 | 3243 | struct intel_engine_cs *engine; |
888b5995 AS |
3244 | struct drm_info_node *node = (struct drm_info_node *) m->private; |
3245 | struct drm_device *dev = node->minor->dev; | |
3246 | struct drm_i915_private *dev_priv = dev->dev_private; | |
33136b06 | 3247 | struct i915_workarounds *workarounds = &dev_priv->workarounds; |
c3232b18 | 3248 | enum intel_engine_id id; |
888b5995 | 3249 | |
888b5995 AS |
3250 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
3251 | if (ret) | |
3252 | return ret; | |
3253 | ||
3254 | intel_runtime_pm_get(dev_priv); | |
3255 | ||
33136b06 | 3256 | seq_printf(m, "Workarounds applied: %d\n", workarounds->count); |
c3232b18 | 3257 | for_each_engine_id(engine, dev_priv, id) |
33136b06 | 3258 | seq_printf(m, "HW whitelist count for %s: %d\n", |
c3232b18 | 3259 | engine->name, workarounds->hw_whitelist_count[id]); |
33136b06 | 3260 | for (i = 0; i < workarounds->count; ++i) { |
f0f59a00 VS |
3261 | i915_reg_t addr; |
3262 | u32 mask, value, read; | |
2fa60f6d | 3263 | bool ok; |
888b5995 | 3264 | |
33136b06 AS |
3265 | addr = workarounds->reg[i].addr; |
3266 | mask = workarounds->reg[i].mask; | |
3267 | value = workarounds->reg[i].value; | |
2fa60f6d MK |
3268 | read = I915_READ(addr); |
3269 | ok = (value & mask) == (read & mask); | |
3270 | seq_printf(m, "0x%X: 0x%08X, mask: 0x%08X, read: 0x%08x, status: %s\n", | |
f0f59a00 | 3271 | i915_mmio_reg_offset(addr), value, mask, read, ok ? "OK" : "FAIL"); |
888b5995 AS |
3272 | } |
3273 | ||
3274 | intel_runtime_pm_put(dev_priv); | |
3275 | mutex_unlock(&dev->struct_mutex); | |
3276 | ||
3277 | return 0; | |
3278 | } | |
3279 | ||
c5511e44 DL |
3280 | static int i915_ddb_info(struct seq_file *m, void *unused) |
3281 | { | |
3282 | struct drm_info_node *node = m->private; | |
3283 | struct drm_device *dev = node->minor->dev; | |
3284 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3285 | struct skl_ddb_allocation *ddb; | |
3286 | struct skl_ddb_entry *entry; | |
3287 | enum pipe pipe; | |
3288 | int plane; | |
3289 | ||
2fcffe19 DL |
3290 | if (INTEL_INFO(dev)->gen < 9) |
3291 | return 0; | |
3292 | ||
c5511e44 DL |
3293 | drm_modeset_lock_all(dev); |
3294 | ||
3295 | ddb = &dev_priv->wm.skl_hw.ddb; | |
3296 | ||
3297 | seq_printf(m, "%-15s%8s%8s%8s\n", "", "Start", "End", "Size"); | |
3298 | ||
3299 | for_each_pipe(dev_priv, pipe) { | |
3300 | seq_printf(m, "Pipe %c\n", pipe_name(pipe)); | |
3301 | ||
dd740780 | 3302 | for_each_plane(dev_priv, pipe, plane) { |
c5511e44 DL |
3303 | entry = &ddb->plane[pipe][plane]; |
3304 | seq_printf(m, " Plane%-8d%8u%8u%8u\n", plane + 1, | |
3305 | entry->start, entry->end, | |
3306 | skl_ddb_entry_size(entry)); | |
3307 | } | |
3308 | ||
4969d33e | 3309 | entry = &ddb->plane[pipe][PLANE_CURSOR]; |
c5511e44 DL |
3310 | seq_printf(m, " %-13s%8u%8u%8u\n", "Cursor", entry->start, |
3311 | entry->end, skl_ddb_entry_size(entry)); | |
3312 | } | |
3313 | ||
3314 | drm_modeset_unlock_all(dev); | |
3315 | ||
3316 | return 0; | |
3317 | } | |
3318 | ||
a54746e3 VK |
3319 | static void drrs_status_per_crtc(struct seq_file *m, |
3320 | struct drm_device *dev, struct intel_crtc *intel_crtc) | |
3321 | { | |
3322 | struct intel_encoder *intel_encoder; | |
3323 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3324 | struct i915_drrs *drrs = &dev_priv->drrs; | |
3325 | int vrefresh = 0; | |
3326 | ||
3327 | for_each_encoder_on_crtc(dev, &intel_crtc->base, intel_encoder) { | |
3328 | /* Encoder connected on this CRTC */ | |
3329 | switch (intel_encoder->type) { | |
3330 | case INTEL_OUTPUT_EDP: | |
3331 | seq_puts(m, "eDP:\n"); | |
3332 | break; | |
3333 | case INTEL_OUTPUT_DSI: | |
3334 | seq_puts(m, "DSI:\n"); | |
3335 | break; | |
3336 | case INTEL_OUTPUT_HDMI: | |
3337 | seq_puts(m, "HDMI:\n"); | |
3338 | break; | |
3339 | case INTEL_OUTPUT_DISPLAYPORT: | |
3340 | seq_puts(m, "DP:\n"); | |
3341 | break; | |
3342 | default: | |
3343 | seq_printf(m, "Other encoder (id=%d).\n", | |
3344 | intel_encoder->type); | |
3345 | return; | |
3346 | } | |
3347 | } | |
3348 | ||
3349 | if (dev_priv->vbt.drrs_type == STATIC_DRRS_SUPPORT) | |
3350 | seq_puts(m, "\tVBT: DRRS_type: Static"); | |
3351 | else if (dev_priv->vbt.drrs_type == SEAMLESS_DRRS_SUPPORT) | |
3352 | seq_puts(m, "\tVBT: DRRS_type: Seamless"); | |
3353 | else if (dev_priv->vbt.drrs_type == DRRS_NOT_SUPPORTED) | |
3354 | seq_puts(m, "\tVBT: DRRS_type: None"); | |
3355 | else | |
3356 | seq_puts(m, "\tVBT: DRRS_type: FIXME: Unrecognized Value"); | |
3357 | ||
3358 | seq_puts(m, "\n\n"); | |
3359 | ||
f77076c9 | 3360 | if (to_intel_crtc_state(intel_crtc->base.state)->has_drrs) { |
a54746e3 VK |
3361 | struct intel_panel *panel; |
3362 | ||
3363 | mutex_lock(&drrs->mutex); | |
3364 | /* DRRS Supported */ | |
3365 | seq_puts(m, "\tDRRS Supported: Yes\n"); | |
3366 | ||
3367 | /* disable_drrs() will make drrs->dp NULL */ | |
3368 | if (!drrs->dp) { | |
3369 | seq_puts(m, "Idleness DRRS: Disabled"); | |
3370 | mutex_unlock(&drrs->mutex); | |
3371 | return; | |
3372 | } | |
3373 | ||
3374 | panel = &drrs->dp->attached_connector->panel; | |
3375 | seq_printf(m, "\t\tBusy_frontbuffer_bits: 0x%X", | |
3376 | drrs->busy_frontbuffer_bits); | |
3377 | ||
3378 | seq_puts(m, "\n\t\t"); | |
3379 | if (drrs->refresh_rate_type == DRRS_HIGH_RR) { | |
3380 | seq_puts(m, "DRRS_State: DRRS_HIGH_RR\n"); | |
3381 | vrefresh = panel->fixed_mode->vrefresh; | |
3382 | } else if (drrs->refresh_rate_type == DRRS_LOW_RR) { | |
3383 | seq_puts(m, "DRRS_State: DRRS_LOW_RR\n"); | |
3384 | vrefresh = panel->downclock_mode->vrefresh; | |
3385 | } else { | |
3386 | seq_printf(m, "DRRS_State: Unknown(%d)\n", | |
3387 | drrs->refresh_rate_type); | |
3388 | mutex_unlock(&drrs->mutex); | |
3389 | return; | |
3390 | } | |
3391 | seq_printf(m, "\t\tVrefresh: %d", vrefresh); | |
3392 | ||
3393 | seq_puts(m, "\n\t\t"); | |
3394 | mutex_unlock(&drrs->mutex); | |
3395 | } else { | |
3396 | /* DRRS not supported. Print the VBT parameter*/ | |
3397 | seq_puts(m, "\tDRRS Supported : No"); | |
3398 | } | |
3399 | seq_puts(m, "\n"); | |
3400 | } | |
3401 | ||
3402 | static int i915_drrs_status(struct seq_file *m, void *unused) | |
3403 | { | |
3404 | struct drm_info_node *node = m->private; | |
3405 | struct drm_device *dev = node->minor->dev; | |
3406 | struct intel_crtc *intel_crtc; | |
3407 | int active_crtc_cnt = 0; | |
3408 | ||
3409 | for_each_intel_crtc(dev, intel_crtc) { | |
3410 | drm_modeset_lock(&intel_crtc->base.mutex, NULL); | |
3411 | ||
f77076c9 | 3412 | if (intel_crtc->base.state->active) { |
a54746e3 VK |
3413 | active_crtc_cnt++; |
3414 | seq_printf(m, "\nCRTC %d: ", active_crtc_cnt); | |
3415 | ||
3416 | drrs_status_per_crtc(m, dev, intel_crtc); | |
3417 | } | |
3418 | ||
3419 | drm_modeset_unlock(&intel_crtc->base.mutex); | |
3420 | } | |
3421 | ||
3422 | if (!active_crtc_cnt) | |
3423 | seq_puts(m, "No active crtc found\n"); | |
3424 | ||
3425 | return 0; | |
3426 | } | |
3427 | ||
07144428 DL |
3428 | struct pipe_crc_info { |
3429 | const char *name; | |
3430 | struct drm_device *dev; | |
3431 | enum pipe pipe; | |
3432 | }; | |
3433 | ||
11bed958 DA |
3434 | static int i915_dp_mst_info(struct seq_file *m, void *unused) |
3435 | { | |
3436 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
3437 | struct drm_device *dev = node->minor->dev; | |
3438 | struct drm_encoder *encoder; | |
3439 | struct intel_encoder *intel_encoder; | |
3440 | struct intel_digital_port *intel_dig_port; | |
3441 | drm_modeset_lock_all(dev); | |
3442 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { | |
3443 | intel_encoder = to_intel_encoder(encoder); | |
3444 | if (intel_encoder->type != INTEL_OUTPUT_DISPLAYPORT) | |
3445 | continue; | |
3446 | intel_dig_port = enc_to_dig_port(encoder); | |
3447 | if (!intel_dig_port->dp.can_mst) | |
3448 | continue; | |
40ae80cc JB |
3449 | seq_printf(m, "MST Source Port %c\n", |
3450 | port_name(intel_dig_port->port)); | |
11bed958 DA |
3451 | drm_dp_mst_dump_topology(m, &intel_dig_port->dp.mst_mgr); |
3452 | } | |
3453 | drm_modeset_unlock_all(dev); | |
3454 | return 0; | |
3455 | } | |
3456 | ||
07144428 DL |
3457 | static int i915_pipe_crc_open(struct inode *inode, struct file *filep) |
3458 | { | |
be5c7a90 DL |
3459 | struct pipe_crc_info *info = inode->i_private; |
3460 | struct drm_i915_private *dev_priv = info->dev->dev_private; | |
3461 | struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe]; | |
3462 | ||
7eb1c496 DV |
3463 | if (info->pipe >= INTEL_INFO(info->dev)->num_pipes) |
3464 | return -ENODEV; | |
3465 | ||
d538bbdf DL |
3466 | spin_lock_irq(&pipe_crc->lock); |
3467 | ||
3468 | if (pipe_crc->opened) { | |
3469 | spin_unlock_irq(&pipe_crc->lock); | |
be5c7a90 DL |
3470 | return -EBUSY; /* already open */ |
3471 | } | |
3472 | ||
d538bbdf | 3473 | pipe_crc->opened = true; |
07144428 DL |
3474 | filep->private_data = inode->i_private; |
3475 | ||
d538bbdf DL |
3476 | spin_unlock_irq(&pipe_crc->lock); |
3477 | ||
07144428 DL |
3478 | return 0; |
3479 | } | |
3480 | ||
3481 | static int i915_pipe_crc_release(struct inode *inode, struct file *filep) | |
3482 | { | |
be5c7a90 DL |
3483 | struct pipe_crc_info *info = inode->i_private; |
3484 | struct drm_i915_private *dev_priv = info->dev->dev_private; | |
3485 | struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe]; | |
3486 | ||
d538bbdf DL |
3487 | spin_lock_irq(&pipe_crc->lock); |
3488 | pipe_crc->opened = false; | |
3489 | spin_unlock_irq(&pipe_crc->lock); | |
be5c7a90 | 3490 | |
07144428 DL |
3491 | return 0; |
3492 | } | |
3493 | ||
3494 | /* (6 fields, 8 chars each, space separated (5) + '\n') */ | |
3495 | #define PIPE_CRC_LINE_LEN (6 * 8 + 5 + 1) | |
3496 | /* account for \'0' */ | |
3497 | #define PIPE_CRC_BUFFER_LEN (PIPE_CRC_LINE_LEN + 1) | |
3498 | ||
3499 | static int pipe_crc_data_count(struct intel_pipe_crc *pipe_crc) | |
8bf1e9f1 | 3500 | { |
d538bbdf DL |
3501 | assert_spin_locked(&pipe_crc->lock); |
3502 | return CIRC_CNT(pipe_crc->head, pipe_crc->tail, | |
3503 | INTEL_PIPE_CRC_ENTRIES_NR); | |
07144428 DL |
3504 | } |
3505 | ||
3506 | static ssize_t | |
3507 | i915_pipe_crc_read(struct file *filep, char __user *user_buf, size_t count, | |
3508 | loff_t *pos) | |
3509 | { | |
3510 | struct pipe_crc_info *info = filep->private_data; | |
3511 | struct drm_device *dev = info->dev; | |
3512 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3513 | struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe]; | |
3514 | char buf[PIPE_CRC_BUFFER_LEN]; | |
9ad6d99f | 3515 | int n_entries; |
07144428 DL |
3516 | ssize_t bytes_read; |
3517 | ||
3518 | /* | |
3519 | * Don't allow user space to provide buffers not big enough to hold | |
3520 | * a line of data. | |
3521 | */ | |
3522 | if (count < PIPE_CRC_LINE_LEN) | |
3523 | return -EINVAL; | |
3524 | ||
3525 | if (pipe_crc->source == INTEL_PIPE_CRC_SOURCE_NONE) | |
8bf1e9f1 | 3526 | return 0; |
07144428 DL |
3527 | |
3528 | /* nothing to read */ | |
d538bbdf | 3529 | spin_lock_irq(&pipe_crc->lock); |
07144428 | 3530 | while (pipe_crc_data_count(pipe_crc) == 0) { |
d538bbdf DL |
3531 | int ret; |
3532 | ||
3533 | if (filep->f_flags & O_NONBLOCK) { | |
3534 | spin_unlock_irq(&pipe_crc->lock); | |
07144428 | 3535 | return -EAGAIN; |
d538bbdf | 3536 | } |
07144428 | 3537 | |
d538bbdf DL |
3538 | ret = wait_event_interruptible_lock_irq(pipe_crc->wq, |
3539 | pipe_crc_data_count(pipe_crc), pipe_crc->lock); | |
3540 | if (ret) { | |
3541 | spin_unlock_irq(&pipe_crc->lock); | |
3542 | return ret; | |
3543 | } | |
8bf1e9f1 SH |
3544 | } |
3545 | ||
07144428 | 3546 | /* We now have one or more entries to read */ |
9ad6d99f | 3547 | n_entries = count / PIPE_CRC_LINE_LEN; |
d538bbdf | 3548 | |
07144428 | 3549 | bytes_read = 0; |
9ad6d99f VS |
3550 | while (n_entries > 0) { |
3551 | struct intel_pipe_crc_entry *entry = | |
3552 | &pipe_crc->entries[pipe_crc->tail]; | |
07144428 | 3553 | int ret; |
8bf1e9f1 | 3554 | |
9ad6d99f VS |
3555 | if (CIRC_CNT(pipe_crc->head, pipe_crc->tail, |
3556 | INTEL_PIPE_CRC_ENTRIES_NR) < 1) | |
3557 | break; | |
3558 | ||
3559 | BUILD_BUG_ON_NOT_POWER_OF_2(INTEL_PIPE_CRC_ENTRIES_NR); | |
3560 | pipe_crc->tail = (pipe_crc->tail + 1) & (INTEL_PIPE_CRC_ENTRIES_NR - 1); | |
3561 | ||
07144428 DL |
3562 | bytes_read += snprintf(buf, PIPE_CRC_BUFFER_LEN, |
3563 | "%8u %8x %8x %8x %8x %8x\n", | |
3564 | entry->frame, entry->crc[0], | |
3565 | entry->crc[1], entry->crc[2], | |
3566 | entry->crc[3], entry->crc[4]); | |
3567 | ||
9ad6d99f VS |
3568 | spin_unlock_irq(&pipe_crc->lock); |
3569 | ||
3570 | ret = copy_to_user(user_buf, buf, PIPE_CRC_LINE_LEN); | |
07144428 DL |
3571 | if (ret == PIPE_CRC_LINE_LEN) |
3572 | return -EFAULT; | |
b2c88f5b | 3573 | |
9ad6d99f VS |
3574 | user_buf += PIPE_CRC_LINE_LEN; |
3575 | n_entries--; | |
3576 | ||
3577 | spin_lock_irq(&pipe_crc->lock); | |
3578 | } | |
8bf1e9f1 | 3579 | |
d538bbdf DL |
3580 | spin_unlock_irq(&pipe_crc->lock); |
3581 | ||
07144428 DL |
3582 | return bytes_read; |
3583 | } | |
3584 | ||
3585 | static const struct file_operations i915_pipe_crc_fops = { | |
3586 | .owner = THIS_MODULE, | |
3587 | .open = i915_pipe_crc_open, | |
3588 | .read = i915_pipe_crc_read, | |
3589 | .release = i915_pipe_crc_release, | |
3590 | }; | |
3591 | ||
3592 | static struct pipe_crc_info i915_pipe_crc_data[I915_MAX_PIPES] = { | |
3593 | { | |
3594 | .name = "i915_pipe_A_crc", | |
3595 | .pipe = PIPE_A, | |
3596 | }, | |
3597 | { | |
3598 | .name = "i915_pipe_B_crc", | |
3599 | .pipe = PIPE_B, | |
3600 | }, | |
3601 | { | |
3602 | .name = "i915_pipe_C_crc", | |
3603 | .pipe = PIPE_C, | |
3604 | }, | |
3605 | }; | |
3606 | ||
3607 | static int i915_pipe_crc_create(struct dentry *root, struct drm_minor *minor, | |
3608 | enum pipe pipe) | |
3609 | { | |
3610 | struct drm_device *dev = minor->dev; | |
3611 | struct dentry *ent; | |
3612 | struct pipe_crc_info *info = &i915_pipe_crc_data[pipe]; | |
3613 | ||
3614 | info->dev = dev; | |
3615 | ent = debugfs_create_file(info->name, S_IRUGO, root, info, | |
3616 | &i915_pipe_crc_fops); | |
f3c5fe97 WY |
3617 | if (!ent) |
3618 | return -ENOMEM; | |
07144428 DL |
3619 | |
3620 | return drm_add_fake_info_node(minor, ent, info); | |
8bf1e9f1 SH |
3621 | } |
3622 | ||
e8dfcf78 | 3623 | static const char * const pipe_crc_sources[] = { |
926321d5 DV |
3624 | "none", |
3625 | "plane1", | |
3626 | "plane2", | |
3627 | "pf", | |
5b3a856b | 3628 | "pipe", |
3d099a05 DV |
3629 | "TV", |
3630 | "DP-B", | |
3631 | "DP-C", | |
3632 | "DP-D", | |
46a19188 | 3633 | "auto", |
926321d5 DV |
3634 | }; |
3635 | ||
3636 | static const char *pipe_crc_source_name(enum intel_pipe_crc_source source) | |
3637 | { | |
3638 | BUILD_BUG_ON(ARRAY_SIZE(pipe_crc_sources) != INTEL_PIPE_CRC_SOURCE_MAX); | |
3639 | return pipe_crc_sources[source]; | |
3640 | } | |
3641 | ||
bd9db02f | 3642 | static int display_crc_ctl_show(struct seq_file *m, void *data) |
926321d5 DV |
3643 | { |
3644 | struct drm_device *dev = m->private; | |
3645 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3646 | int i; | |
3647 | ||
3648 | for (i = 0; i < I915_MAX_PIPES; i++) | |
3649 | seq_printf(m, "%c %s\n", pipe_name(i), | |
3650 | pipe_crc_source_name(dev_priv->pipe_crc[i].source)); | |
3651 | ||
3652 | return 0; | |
3653 | } | |
3654 | ||
bd9db02f | 3655 | static int display_crc_ctl_open(struct inode *inode, struct file *file) |
926321d5 DV |
3656 | { |
3657 | struct drm_device *dev = inode->i_private; | |
3658 | ||
bd9db02f | 3659 | return single_open(file, display_crc_ctl_show, dev); |
926321d5 DV |
3660 | } |
3661 | ||
46a19188 | 3662 | static int i8xx_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source, |
52f843f6 DV |
3663 | uint32_t *val) |
3664 | { | |
46a19188 DV |
3665 | if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) |
3666 | *source = INTEL_PIPE_CRC_SOURCE_PIPE; | |
3667 | ||
3668 | switch (*source) { | |
52f843f6 DV |
3669 | case INTEL_PIPE_CRC_SOURCE_PIPE: |
3670 | *val = PIPE_CRC_ENABLE | PIPE_CRC_INCLUDE_BORDER_I8XX; | |
3671 | break; | |
3672 | case INTEL_PIPE_CRC_SOURCE_NONE: | |
3673 | *val = 0; | |
3674 | break; | |
3675 | default: | |
3676 | return -EINVAL; | |
3677 | } | |
3678 | ||
3679 | return 0; | |
3680 | } | |
3681 | ||
46a19188 DV |
3682 | static int i9xx_pipe_crc_auto_source(struct drm_device *dev, enum pipe pipe, |
3683 | enum intel_pipe_crc_source *source) | |
3684 | { | |
3685 | struct intel_encoder *encoder; | |
3686 | struct intel_crtc *crtc; | |
26756809 | 3687 | struct intel_digital_port *dig_port; |
46a19188 DV |
3688 | int ret = 0; |
3689 | ||
3690 | *source = INTEL_PIPE_CRC_SOURCE_PIPE; | |
3691 | ||
6e9f798d | 3692 | drm_modeset_lock_all(dev); |
b2784e15 | 3693 | for_each_intel_encoder(dev, encoder) { |
46a19188 DV |
3694 | if (!encoder->base.crtc) |
3695 | continue; | |
3696 | ||
3697 | crtc = to_intel_crtc(encoder->base.crtc); | |
3698 | ||
3699 | if (crtc->pipe != pipe) | |
3700 | continue; | |
3701 | ||
3702 | switch (encoder->type) { | |
3703 | case INTEL_OUTPUT_TVOUT: | |
3704 | *source = INTEL_PIPE_CRC_SOURCE_TV; | |
3705 | break; | |
3706 | case INTEL_OUTPUT_DISPLAYPORT: | |
3707 | case INTEL_OUTPUT_EDP: | |
26756809 DV |
3708 | dig_port = enc_to_dig_port(&encoder->base); |
3709 | switch (dig_port->port) { | |
3710 | case PORT_B: | |
3711 | *source = INTEL_PIPE_CRC_SOURCE_DP_B; | |
3712 | break; | |
3713 | case PORT_C: | |
3714 | *source = INTEL_PIPE_CRC_SOURCE_DP_C; | |
3715 | break; | |
3716 | case PORT_D: | |
3717 | *source = INTEL_PIPE_CRC_SOURCE_DP_D; | |
3718 | break; | |
3719 | default: | |
3720 | WARN(1, "nonexisting DP port %c\n", | |
3721 | port_name(dig_port->port)); | |
3722 | break; | |
3723 | } | |
46a19188 | 3724 | break; |
6847d71b PZ |
3725 | default: |
3726 | break; | |
46a19188 DV |
3727 | } |
3728 | } | |
6e9f798d | 3729 | drm_modeset_unlock_all(dev); |
46a19188 DV |
3730 | |
3731 | return ret; | |
3732 | } | |
3733 | ||
3734 | static int vlv_pipe_crc_ctl_reg(struct drm_device *dev, | |
3735 | enum pipe pipe, | |
3736 | enum intel_pipe_crc_source *source, | |
7ac0129b DV |
3737 | uint32_t *val) |
3738 | { | |
8d2f24ca DV |
3739 | struct drm_i915_private *dev_priv = dev->dev_private; |
3740 | bool need_stable_symbols = false; | |
3741 | ||
46a19188 DV |
3742 | if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) { |
3743 | int ret = i9xx_pipe_crc_auto_source(dev, pipe, source); | |
3744 | if (ret) | |
3745 | return ret; | |
3746 | } | |
3747 | ||
3748 | switch (*source) { | |
7ac0129b DV |
3749 | case INTEL_PIPE_CRC_SOURCE_PIPE: |
3750 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_VLV; | |
3751 | break; | |
3752 | case INTEL_PIPE_CRC_SOURCE_DP_B: | |
3753 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_VLV; | |
8d2f24ca | 3754 | need_stable_symbols = true; |
7ac0129b DV |
3755 | break; |
3756 | case INTEL_PIPE_CRC_SOURCE_DP_C: | |
3757 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_VLV; | |
8d2f24ca | 3758 | need_stable_symbols = true; |
7ac0129b | 3759 | break; |
2be57922 VS |
3760 | case INTEL_PIPE_CRC_SOURCE_DP_D: |
3761 | if (!IS_CHERRYVIEW(dev)) | |
3762 | return -EINVAL; | |
3763 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_D_VLV; | |
3764 | need_stable_symbols = true; | |
3765 | break; | |
7ac0129b DV |
3766 | case INTEL_PIPE_CRC_SOURCE_NONE: |
3767 | *val = 0; | |
3768 | break; | |
3769 | default: | |
3770 | return -EINVAL; | |
3771 | } | |
3772 | ||
8d2f24ca DV |
3773 | /* |
3774 | * When the pipe CRC tap point is after the transcoders we need | |
3775 | * to tweak symbol-level features to produce a deterministic series of | |
3776 | * symbols for a given frame. We need to reset those features only once | |
3777 | * a frame (instead of every nth symbol): | |
3778 | * - DC-balance: used to ensure a better clock recovery from the data | |
3779 | * link (SDVO) | |
3780 | * - DisplayPort scrambling: used for EMI reduction | |
3781 | */ | |
3782 | if (need_stable_symbols) { | |
3783 | uint32_t tmp = I915_READ(PORT_DFT2_G4X); | |
3784 | ||
8d2f24ca | 3785 | tmp |= DC_BALANCE_RESET_VLV; |
eb736679 VS |
3786 | switch (pipe) { |
3787 | case PIPE_A: | |
8d2f24ca | 3788 | tmp |= PIPE_A_SCRAMBLE_RESET; |
eb736679 VS |
3789 | break; |
3790 | case PIPE_B: | |
8d2f24ca | 3791 | tmp |= PIPE_B_SCRAMBLE_RESET; |
eb736679 VS |
3792 | break; |
3793 | case PIPE_C: | |
3794 | tmp |= PIPE_C_SCRAMBLE_RESET; | |
3795 | break; | |
3796 | default: | |
3797 | return -EINVAL; | |
3798 | } | |
8d2f24ca DV |
3799 | I915_WRITE(PORT_DFT2_G4X, tmp); |
3800 | } | |
3801 | ||
7ac0129b DV |
3802 | return 0; |
3803 | } | |
3804 | ||
4b79ebf7 | 3805 | static int i9xx_pipe_crc_ctl_reg(struct drm_device *dev, |
46a19188 DV |
3806 | enum pipe pipe, |
3807 | enum intel_pipe_crc_source *source, | |
4b79ebf7 DV |
3808 | uint32_t *val) |
3809 | { | |
84093603 DV |
3810 | struct drm_i915_private *dev_priv = dev->dev_private; |
3811 | bool need_stable_symbols = false; | |
3812 | ||
46a19188 DV |
3813 | if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) { |
3814 | int ret = i9xx_pipe_crc_auto_source(dev, pipe, source); | |
3815 | if (ret) | |
3816 | return ret; | |
3817 | } | |
3818 | ||
3819 | switch (*source) { | |
4b79ebf7 DV |
3820 | case INTEL_PIPE_CRC_SOURCE_PIPE: |
3821 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_I9XX; | |
3822 | break; | |
3823 | case INTEL_PIPE_CRC_SOURCE_TV: | |
3824 | if (!SUPPORTS_TV(dev)) | |
3825 | return -EINVAL; | |
3826 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_TV_PRE; | |
3827 | break; | |
3828 | case INTEL_PIPE_CRC_SOURCE_DP_B: | |
3829 | if (!IS_G4X(dev)) | |
3830 | return -EINVAL; | |
3831 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_G4X; | |
84093603 | 3832 | need_stable_symbols = true; |
4b79ebf7 DV |
3833 | break; |
3834 | case INTEL_PIPE_CRC_SOURCE_DP_C: | |
3835 | if (!IS_G4X(dev)) | |
3836 | return -EINVAL; | |
3837 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_G4X; | |
84093603 | 3838 | need_stable_symbols = true; |
4b79ebf7 DV |
3839 | break; |
3840 | case INTEL_PIPE_CRC_SOURCE_DP_D: | |
3841 | if (!IS_G4X(dev)) | |
3842 | return -EINVAL; | |
3843 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_D_G4X; | |
84093603 | 3844 | need_stable_symbols = true; |
4b79ebf7 DV |
3845 | break; |
3846 | case INTEL_PIPE_CRC_SOURCE_NONE: | |
3847 | *val = 0; | |
3848 | break; | |
3849 | default: | |
3850 | return -EINVAL; | |
3851 | } | |
3852 | ||
84093603 DV |
3853 | /* |
3854 | * When the pipe CRC tap point is after the transcoders we need | |
3855 | * to tweak symbol-level features to produce a deterministic series of | |
3856 | * symbols for a given frame. We need to reset those features only once | |
3857 | * a frame (instead of every nth symbol): | |
3858 | * - DC-balance: used to ensure a better clock recovery from the data | |
3859 | * link (SDVO) | |
3860 | * - DisplayPort scrambling: used for EMI reduction | |
3861 | */ | |
3862 | if (need_stable_symbols) { | |
3863 | uint32_t tmp = I915_READ(PORT_DFT2_G4X); | |
3864 | ||
3865 | WARN_ON(!IS_G4X(dev)); | |
3866 | ||
3867 | I915_WRITE(PORT_DFT_I9XX, | |
3868 | I915_READ(PORT_DFT_I9XX) | DC_BALANCE_RESET); | |
3869 | ||
3870 | if (pipe == PIPE_A) | |
3871 | tmp |= PIPE_A_SCRAMBLE_RESET; | |
3872 | else | |
3873 | tmp |= PIPE_B_SCRAMBLE_RESET; | |
3874 | ||
3875 | I915_WRITE(PORT_DFT2_G4X, tmp); | |
3876 | } | |
3877 | ||
4b79ebf7 DV |
3878 | return 0; |
3879 | } | |
3880 | ||
8d2f24ca DV |
3881 | static void vlv_undo_pipe_scramble_reset(struct drm_device *dev, |
3882 | enum pipe pipe) | |
3883 | { | |
3884 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3885 | uint32_t tmp = I915_READ(PORT_DFT2_G4X); | |
3886 | ||
eb736679 VS |
3887 | switch (pipe) { |
3888 | case PIPE_A: | |
8d2f24ca | 3889 | tmp &= ~PIPE_A_SCRAMBLE_RESET; |
eb736679 VS |
3890 | break; |
3891 | case PIPE_B: | |
8d2f24ca | 3892 | tmp &= ~PIPE_B_SCRAMBLE_RESET; |
eb736679 VS |
3893 | break; |
3894 | case PIPE_C: | |
3895 | tmp &= ~PIPE_C_SCRAMBLE_RESET; | |
3896 | break; | |
3897 | default: | |
3898 | return; | |
3899 | } | |
8d2f24ca DV |
3900 | if (!(tmp & PIPE_SCRAMBLE_RESET_MASK)) |
3901 | tmp &= ~DC_BALANCE_RESET_VLV; | |
3902 | I915_WRITE(PORT_DFT2_G4X, tmp); | |
3903 | ||
3904 | } | |
3905 | ||
84093603 DV |
3906 | static void g4x_undo_pipe_scramble_reset(struct drm_device *dev, |
3907 | enum pipe pipe) | |
3908 | { | |
3909 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3910 | uint32_t tmp = I915_READ(PORT_DFT2_G4X); | |
3911 | ||
3912 | if (pipe == PIPE_A) | |
3913 | tmp &= ~PIPE_A_SCRAMBLE_RESET; | |
3914 | else | |
3915 | tmp &= ~PIPE_B_SCRAMBLE_RESET; | |
3916 | I915_WRITE(PORT_DFT2_G4X, tmp); | |
3917 | ||
3918 | if (!(tmp & PIPE_SCRAMBLE_RESET_MASK)) { | |
3919 | I915_WRITE(PORT_DFT_I9XX, | |
3920 | I915_READ(PORT_DFT_I9XX) & ~DC_BALANCE_RESET); | |
3921 | } | |
3922 | } | |
3923 | ||
46a19188 | 3924 | static int ilk_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source, |
5b3a856b DV |
3925 | uint32_t *val) |
3926 | { | |
46a19188 DV |
3927 | if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) |
3928 | *source = INTEL_PIPE_CRC_SOURCE_PIPE; | |
3929 | ||
3930 | switch (*source) { | |
5b3a856b DV |
3931 | case INTEL_PIPE_CRC_SOURCE_PLANE1: |
3932 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_ILK; | |
3933 | break; | |
3934 | case INTEL_PIPE_CRC_SOURCE_PLANE2: | |
3935 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_ILK; | |
3936 | break; | |
5b3a856b DV |
3937 | case INTEL_PIPE_CRC_SOURCE_PIPE: |
3938 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_ILK; | |
3939 | break; | |
3d099a05 | 3940 | case INTEL_PIPE_CRC_SOURCE_NONE: |
5b3a856b DV |
3941 | *val = 0; |
3942 | break; | |
3d099a05 DV |
3943 | default: |
3944 | return -EINVAL; | |
5b3a856b DV |
3945 | } |
3946 | ||
3947 | return 0; | |
3948 | } | |
3949 | ||
c4e2d043 | 3950 | static void hsw_trans_edp_pipe_A_crc_wa(struct drm_device *dev, bool enable) |
fabf6e51 DV |
3951 | { |
3952 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3953 | struct intel_crtc *crtc = | |
3954 | to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_A]); | |
f77076c9 | 3955 | struct intel_crtc_state *pipe_config; |
c4e2d043 ML |
3956 | struct drm_atomic_state *state; |
3957 | int ret = 0; | |
fabf6e51 DV |
3958 | |
3959 | drm_modeset_lock_all(dev); | |
c4e2d043 ML |
3960 | state = drm_atomic_state_alloc(dev); |
3961 | if (!state) { | |
3962 | ret = -ENOMEM; | |
3963 | goto out; | |
fabf6e51 | 3964 | } |
fabf6e51 | 3965 | |
c4e2d043 ML |
3966 | state->acquire_ctx = drm_modeset_legacy_acquire_ctx(&crtc->base); |
3967 | pipe_config = intel_atomic_get_crtc_state(state, crtc); | |
3968 | if (IS_ERR(pipe_config)) { | |
3969 | ret = PTR_ERR(pipe_config); | |
3970 | goto out; | |
3971 | } | |
fabf6e51 | 3972 | |
c4e2d043 ML |
3973 | pipe_config->pch_pfit.force_thru = enable; |
3974 | if (pipe_config->cpu_transcoder == TRANSCODER_EDP && | |
3975 | pipe_config->pch_pfit.enabled != enable) | |
3976 | pipe_config->base.connectors_changed = true; | |
1b509259 | 3977 | |
c4e2d043 ML |
3978 | ret = drm_atomic_commit(state); |
3979 | out: | |
fabf6e51 | 3980 | drm_modeset_unlock_all(dev); |
c4e2d043 ML |
3981 | WARN(ret, "Toggling workaround to %i returns %i\n", enable, ret); |
3982 | if (ret) | |
3983 | drm_atomic_state_free(state); | |
fabf6e51 DV |
3984 | } |
3985 | ||
3986 | static int ivb_pipe_crc_ctl_reg(struct drm_device *dev, | |
3987 | enum pipe pipe, | |
3988 | enum intel_pipe_crc_source *source, | |
5b3a856b DV |
3989 | uint32_t *val) |
3990 | { | |
46a19188 DV |
3991 | if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) |
3992 | *source = INTEL_PIPE_CRC_SOURCE_PF; | |
3993 | ||
3994 | switch (*source) { | |
5b3a856b DV |
3995 | case INTEL_PIPE_CRC_SOURCE_PLANE1: |
3996 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_IVB; | |
3997 | break; | |
3998 | case INTEL_PIPE_CRC_SOURCE_PLANE2: | |
3999 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_IVB; | |
4000 | break; | |
4001 | case INTEL_PIPE_CRC_SOURCE_PF: | |
fabf6e51 | 4002 | if (IS_HASWELL(dev) && pipe == PIPE_A) |
c4e2d043 | 4003 | hsw_trans_edp_pipe_A_crc_wa(dev, true); |
fabf6e51 | 4004 | |
5b3a856b DV |
4005 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PF_IVB; |
4006 | break; | |
3d099a05 | 4007 | case INTEL_PIPE_CRC_SOURCE_NONE: |
5b3a856b DV |
4008 | *val = 0; |
4009 | break; | |
3d099a05 DV |
4010 | default: |
4011 | return -EINVAL; | |
5b3a856b DV |
4012 | } |
4013 | ||
4014 | return 0; | |
4015 | } | |
4016 | ||
926321d5 DV |
4017 | static int pipe_crc_set_source(struct drm_device *dev, enum pipe pipe, |
4018 | enum intel_pipe_crc_source source) | |
4019 | { | |
4020 | struct drm_i915_private *dev_priv = dev->dev_private; | |
cc3da175 | 4021 | struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe]; |
8c740dce PZ |
4022 | struct intel_crtc *crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, |
4023 | pipe)); | |
e129649b | 4024 | enum intel_display_power_domain power_domain; |
432f3342 | 4025 | u32 val = 0; /* shut up gcc */ |
5b3a856b | 4026 | int ret; |
926321d5 | 4027 | |
cc3da175 DL |
4028 | if (pipe_crc->source == source) |
4029 | return 0; | |
4030 | ||
ae676fcd DL |
4031 | /* forbid changing the source without going back to 'none' */ |
4032 | if (pipe_crc->source && source) | |
4033 | return -EINVAL; | |
4034 | ||
e129649b ID |
4035 | power_domain = POWER_DOMAIN_PIPE(pipe); |
4036 | if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) { | |
9d8b0588 DV |
4037 | DRM_DEBUG_KMS("Trying to capture CRC while pipe is off\n"); |
4038 | return -EIO; | |
4039 | } | |
4040 | ||
52f843f6 | 4041 | if (IS_GEN2(dev)) |
46a19188 | 4042 | ret = i8xx_pipe_crc_ctl_reg(&source, &val); |
52f843f6 | 4043 | else if (INTEL_INFO(dev)->gen < 5) |
46a19188 | 4044 | ret = i9xx_pipe_crc_ctl_reg(dev, pipe, &source, &val); |
666a4537 | 4045 | else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) |
fabf6e51 | 4046 | ret = vlv_pipe_crc_ctl_reg(dev, pipe, &source, &val); |
4b79ebf7 | 4047 | else if (IS_GEN5(dev) || IS_GEN6(dev)) |
46a19188 | 4048 | ret = ilk_pipe_crc_ctl_reg(&source, &val); |
5b3a856b | 4049 | else |
fabf6e51 | 4050 | ret = ivb_pipe_crc_ctl_reg(dev, pipe, &source, &val); |
5b3a856b DV |
4051 | |
4052 | if (ret != 0) | |
e129649b | 4053 | goto out; |
5b3a856b | 4054 | |
4b584369 DL |
4055 | /* none -> real source transition */ |
4056 | if (source) { | |
4252fbc3 VS |
4057 | struct intel_pipe_crc_entry *entries; |
4058 | ||
7cd6ccff DL |
4059 | DRM_DEBUG_DRIVER("collecting CRCs for pipe %c, %s\n", |
4060 | pipe_name(pipe), pipe_crc_source_name(source)); | |
4061 | ||
3cf54b34 VS |
4062 | entries = kcalloc(INTEL_PIPE_CRC_ENTRIES_NR, |
4063 | sizeof(pipe_crc->entries[0]), | |
4252fbc3 | 4064 | GFP_KERNEL); |
e129649b ID |
4065 | if (!entries) { |
4066 | ret = -ENOMEM; | |
4067 | goto out; | |
4068 | } | |
e5f75aca | 4069 | |
8c740dce PZ |
4070 | /* |
4071 | * When IPS gets enabled, the pipe CRC changes. Since IPS gets | |
4072 | * enabled and disabled dynamically based on package C states, | |
4073 | * user space can't make reliable use of the CRCs, so let's just | |
4074 | * completely disable it. | |
4075 | */ | |
4076 | hsw_disable_ips(crtc); | |
4077 | ||
d538bbdf | 4078 | spin_lock_irq(&pipe_crc->lock); |
64387b61 | 4079 | kfree(pipe_crc->entries); |
4252fbc3 | 4080 | pipe_crc->entries = entries; |
d538bbdf DL |
4081 | pipe_crc->head = 0; |
4082 | pipe_crc->tail = 0; | |
4083 | spin_unlock_irq(&pipe_crc->lock); | |
4b584369 DL |
4084 | } |
4085 | ||
cc3da175 | 4086 | pipe_crc->source = source; |
926321d5 | 4087 | |
926321d5 DV |
4088 | I915_WRITE(PIPE_CRC_CTL(pipe), val); |
4089 | POSTING_READ(PIPE_CRC_CTL(pipe)); | |
4090 | ||
e5f75aca DL |
4091 | /* real source -> none transition */ |
4092 | if (source == INTEL_PIPE_CRC_SOURCE_NONE) { | |
d538bbdf | 4093 | struct intel_pipe_crc_entry *entries; |
a33d7105 DV |
4094 | struct intel_crtc *crtc = |
4095 | to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); | |
d538bbdf | 4096 | |
7cd6ccff DL |
4097 | DRM_DEBUG_DRIVER("stopping CRCs for pipe %c\n", |
4098 | pipe_name(pipe)); | |
4099 | ||
a33d7105 | 4100 | drm_modeset_lock(&crtc->base.mutex, NULL); |
f77076c9 | 4101 | if (crtc->base.state->active) |
a33d7105 DV |
4102 | intel_wait_for_vblank(dev, pipe); |
4103 | drm_modeset_unlock(&crtc->base.mutex); | |
bcf17ab2 | 4104 | |
d538bbdf DL |
4105 | spin_lock_irq(&pipe_crc->lock); |
4106 | entries = pipe_crc->entries; | |
e5f75aca | 4107 | pipe_crc->entries = NULL; |
9ad6d99f VS |
4108 | pipe_crc->head = 0; |
4109 | pipe_crc->tail = 0; | |
d538bbdf DL |
4110 | spin_unlock_irq(&pipe_crc->lock); |
4111 | ||
4112 | kfree(entries); | |
84093603 DV |
4113 | |
4114 | if (IS_G4X(dev)) | |
4115 | g4x_undo_pipe_scramble_reset(dev, pipe); | |
666a4537 | 4116 | else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) |
8d2f24ca | 4117 | vlv_undo_pipe_scramble_reset(dev, pipe); |
fabf6e51 | 4118 | else if (IS_HASWELL(dev) && pipe == PIPE_A) |
c4e2d043 | 4119 | hsw_trans_edp_pipe_A_crc_wa(dev, false); |
8c740dce PZ |
4120 | |
4121 | hsw_enable_ips(crtc); | |
e5f75aca DL |
4122 | } |
4123 | ||
e129649b ID |
4124 | ret = 0; |
4125 | ||
4126 | out: | |
4127 | intel_display_power_put(dev_priv, power_domain); | |
4128 | ||
4129 | return ret; | |
926321d5 DV |
4130 | } |
4131 | ||
4132 | /* | |
4133 | * Parse pipe CRC command strings: | |
b94dec87 DL |
4134 | * command: wsp* object wsp+ name wsp+ source wsp* |
4135 | * object: 'pipe' | |
4136 | * name: (A | B | C) | |
926321d5 DV |
4137 | * source: (none | plane1 | plane2 | pf) |
4138 | * wsp: (#0x20 | #0x9 | #0xA)+ | |
4139 | * | |
4140 | * eg.: | |
b94dec87 DL |
4141 | * "pipe A plane1" -> Start CRC computations on plane1 of pipe A |
4142 | * "pipe A none" -> Stop CRC | |
926321d5 | 4143 | */ |
bd9db02f | 4144 | static int display_crc_ctl_tokenize(char *buf, char *words[], int max_words) |
926321d5 DV |
4145 | { |
4146 | int n_words = 0; | |
4147 | ||
4148 | while (*buf) { | |
4149 | char *end; | |
4150 | ||
4151 | /* skip leading white space */ | |
4152 | buf = skip_spaces(buf); | |
4153 | if (!*buf) | |
4154 | break; /* end of buffer */ | |
4155 | ||
4156 | /* find end of word */ | |
4157 | for (end = buf; *end && !isspace(*end); end++) | |
4158 | ; | |
4159 | ||
4160 | if (n_words == max_words) { | |
4161 | DRM_DEBUG_DRIVER("too many words, allowed <= %d\n", | |
4162 | max_words); | |
4163 | return -EINVAL; /* ran out of words[] before bytes */ | |
4164 | } | |
4165 | ||
4166 | if (*end) | |
4167 | *end++ = '\0'; | |
4168 | words[n_words++] = buf; | |
4169 | buf = end; | |
4170 | } | |
4171 | ||
4172 | return n_words; | |
4173 | } | |
4174 | ||
b94dec87 DL |
4175 | enum intel_pipe_crc_object { |
4176 | PIPE_CRC_OBJECT_PIPE, | |
4177 | }; | |
4178 | ||
e8dfcf78 | 4179 | static const char * const pipe_crc_objects[] = { |
b94dec87 DL |
4180 | "pipe", |
4181 | }; | |
4182 | ||
4183 | static int | |
bd9db02f | 4184 | display_crc_ctl_parse_object(const char *buf, enum intel_pipe_crc_object *o) |
b94dec87 DL |
4185 | { |
4186 | int i; | |
4187 | ||
4188 | for (i = 0; i < ARRAY_SIZE(pipe_crc_objects); i++) | |
4189 | if (!strcmp(buf, pipe_crc_objects[i])) { | |
bd9db02f | 4190 | *o = i; |
b94dec87 DL |
4191 | return 0; |
4192 | } | |
4193 | ||
4194 | return -EINVAL; | |
4195 | } | |
4196 | ||
bd9db02f | 4197 | static int display_crc_ctl_parse_pipe(const char *buf, enum pipe *pipe) |
926321d5 DV |
4198 | { |
4199 | const char name = buf[0]; | |
4200 | ||
4201 | if (name < 'A' || name >= pipe_name(I915_MAX_PIPES)) | |
4202 | return -EINVAL; | |
4203 | ||
4204 | *pipe = name - 'A'; | |
4205 | ||
4206 | return 0; | |
4207 | } | |
4208 | ||
4209 | static int | |
bd9db02f | 4210 | display_crc_ctl_parse_source(const char *buf, enum intel_pipe_crc_source *s) |
926321d5 DV |
4211 | { |
4212 | int i; | |
4213 | ||
4214 | for (i = 0; i < ARRAY_SIZE(pipe_crc_sources); i++) | |
4215 | if (!strcmp(buf, pipe_crc_sources[i])) { | |
bd9db02f | 4216 | *s = i; |
926321d5 DV |
4217 | return 0; |
4218 | } | |
4219 | ||
4220 | return -EINVAL; | |
4221 | } | |
4222 | ||
bd9db02f | 4223 | static int display_crc_ctl_parse(struct drm_device *dev, char *buf, size_t len) |
926321d5 | 4224 | { |
b94dec87 | 4225 | #define N_WORDS 3 |
926321d5 | 4226 | int n_words; |
b94dec87 | 4227 | char *words[N_WORDS]; |
926321d5 | 4228 | enum pipe pipe; |
b94dec87 | 4229 | enum intel_pipe_crc_object object; |
926321d5 DV |
4230 | enum intel_pipe_crc_source source; |
4231 | ||
bd9db02f | 4232 | n_words = display_crc_ctl_tokenize(buf, words, N_WORDS); |
b94dec87 DL |
4233 | if (n_words != N_WORDS) { |
4234 | DRM_DEBUG_DRIVER("tokenize failed, a command is %d words\n", | |
4235 | N_WORDS); | |
4236 | return -EINVAL; | |
4237 | } | |
4238 | ||
bd9db02f | 4239 | if (display_crc_ctl_parse_object(words[0], &object) < 0) { |
b94dec87 | 4240 | DRM_DEBUG_DRIVER("unknown object %s\n", words[0]); |
926321d5 DV |
4241 | return -EINVAL; |
4242 | } | |
4243 | ||
bd9db02f | 4244 | if (display_crc_ctl_parse_pipe(words[1], &pipe) < 0) { |
b94dec87 | 4245 | DRM_DEBUG_DRIVER("unknown pipe %s\n", words[1]); |
926321d5 DV |
4246 | return -EINVAL; |
4247 | } | |
4248 | ||
bd9db02f | 4249 | if (display_crc_ctl_parse_source(words[2], &source) < 0) { |
b94dec87 | 4250 | DRM_DEBUG_DRIVER("unknown source %s\n", words[2]); |
926321d5 DV |
4251 | return -EINVAL; |
4252 | } | |
4253 | ||
4254 | return pipe_crc_set_source(dev, pipe, source); | |
4255 | } | |
4256 | ||
bd9db02f DL |
4257 | static ssize_t display_crc_ctl_write(struct file *file, const char __user *ubuf, |
4258 | size_t len, loff_t *offp) | |
926321d5 DV |
4259 | { |
4260 | struct seq_file *m = file->private_data; | |
4261 | struct drm_device *dev = m->private; | |
4262 | char *tmpbuf; | |
4263 | int ret; | |
4264 | ||
4265 | if (len == 0) | |
4266 | return 0; | |
4267 | ||
4268 | if (len > PAGE_SIZE - 1) { | |
4269 | DRM_DEBUG_DRIVER("expected <%lu bytes into pipe crc control\n", | |
4270 | PAGE_SIZE); | |
4271 | return -E2BIG; | |
4272 | } | |
4273 | ||
4274 | tmpbuf = kmalloc(len + 1, GFP_KERNEL); | |
4275 | if (!tmpbuf) | |
4276 | return -ENOMEM; | |
4277 | ||
4278 | if (copy_from_user(tmpbuf, ubuf, len)) { | |
4279 | ret = -EFAULT; | |
4280 | goto out; | |
4281 | } | |
4282 | tmpbuf[len] = '\0'; | |
4283 | ||
bd9db02f | 4284 | ret = display_crc_ctl_parse(dev, tmpbuf, len); |
926321d5 DV |
4285 | |
4286 | out: | |
4287 | kfree(tmpbuf); | |
4288 | if (ret < 0) | |
4289 | return ret; | |
4290 | ||
4291 | *offp += len; | |
4292 | return len; | |
4293 | } | |
4294 | ||
bd9db02f | 4295 | static const struct file_operations i915_display_crc_ctl_fops = { |
926321d5 | 4296 | .owner = THIS_MODULE, |
bd9db02f | 4297 | .open = display_crc_ctl_open, |
926321d5 DV |
4298 | .read = seq_read, |
4299 | .llseek = seq_lseek, | |
4300 | .release = single_release, | |
bd9db02f | 4301 | .write = display_crc_ctl_write |
926321d5 DV |
4302 | }; |
4303 | ||
eb3394fa TP |
4304 | static ssize_t i915_displayport_test_active_write(struct file *file, |
4305 | const char __user *ubuf, | |
4306 | size_t len, loff_t *offp) | |
4307 | { | |
4308 | char *input_buffer; | |
4309 | int status = 0; | |
eb3394fa TP |
4310 | struct drm_device *dev; |
4311 | struct drm_connector *connector; | |
4312 | struct list_head *connector_list; | |
4313 | struct intel_dp *intel_dp; | |
4314 | int val = 0; | |
4315 | ||
9aaffa34 | 4316 | dev = ((struct seq_file *)file->private_data)->private; |
eb3394fa | 4317 | |
eb3394fa TP |
4318 | connector_list = &dev->mode_config.connector_list; |
4319 | ||
4320 | if (len == 0) | |
4321 | return 0; | |
4322 | ||
4323 | input_buffer = kmalloc(len + 1, GFP_KERNEL); | |
4324 | if (!input_buffer) | |
4325 | return -ENOMEM; | |
4326 | ||
4327 | if (copy_from_user(input_buffer, ubuf, len)) { | |
4328 | status = -EFAULT; | |
4329 | goto out; | |
4330 | } | |
4331 | ||
4332 | input_buffer[len] = '\0'; | |
4333 | DRM_DEBUG_DRIVER("Copied %d bytes from user\n", (unsigned int)len); | |
4334 | ||
4335 | list_for_each_entry(connector, connector_list, head) { | |
4336 | ||
4337 | if (connector->connector_type != | |
4338 | DRM_MODE_CONNECTOR_DisplayPort) | |
4339 | continue; | |
4340 | ||
b8bb08ec | 4341 | if (connector->status == connector_status_connected && |
eb3394fa TP |
4342 | connector->encoder != NULL) { |
4343 | intel_dp = enc_to_intel_dp(connector->encoder); | |
4344 | status = kstrtoint(input_buffer, 10, &val); | |
4345 | if (status < 0) | |
4346 | goto out; | |
4347 | DRM_DEBUG_DRIVER("Got %d for test active\n", val); | |
4348 | /* To prevent erroneous activation of the compliance | |
4349 | * testing code, only accept an actual value of 1 here | |
4350 | */ | |
4351 | if (val == 1) | |
4352 | intel_dp->compliance_test_active = 1; | |
4353 | else | |
4354 | intel_dp->compliance_test_active = 0; | |
4355 | } | |
4356 | } | |
4357 | out: | |
4358 | kfree(input_buffer); | |
4359 | if (status < 0) | |
4360 | return status; | |
4361 | ||
4362 | *offp += len; | |
4363 | return len; | |
4364 | } | |
4365 | ||
4366 | static int i915_displayport_test_active_show(struct seq_file *m, void *data) | |
4367 | { | |
4368 | struct drm_device *dev = m->private; | |
4369 | struct drm_connector *connector; | |
4370 | struct list_head *connector_list = &dev->mode_config.connector_list; | |
4371 | struct intel_dp *intel_dp; | |
4372 | ||
eb3394fa TP |
4373 | list_for_each_entry(connector, connector_list, head) { |
4374 | ||
4375 | if (connector->connector_type != | |
4376 | DRM_MODE_CONNECTOR_DisplayPort) | |
4377 | continue; | |
4378 | ||
4379 | if (connector->status == connector_status_connected && | |
4380 | connector->encoder != NULL) { | |
4381 | intel_dp = enc_to_intel_dp(connector->encoder); | |
4382 | if (intel_dp->compliance_test_active) | |
4383 | seq_puts(m, "1"); | |
4384 | else | |
4385 | seq_puts(m, "0"); | |
4386 | } else | |
4387 | seq_puts(m, "0"); | |
4388 | } | |
4389 | ||
4390 | return 0; | |
4391 | } | |
4392 | ||
4393 | static int i915_displayport_test_active_open(struct inode *inode, | |
4394 | struct file *file) | |
4395 | { | |
4396 | struct drm_device *dev = inode->i_private; | |
4397 | ||
4398 | return single_open(file, i915_displayport_test_active_show, dev); | |
4399 | } | |
4400 | ||
4401 | static const struct file_operations i915_displayport_test_active_fops = { | |
4402 | .owner = THIS_MODULE, | |
4403 | .open = i915_displayport_test_active_open, | |
4404 | .read = seq_read, | |
4405 | .llseek = seq_lseek, | |
4406 | .release = single_release, | |
4407 | .write = i915_displayport_test_active_write | |
4408 | }; | |
4409 | ||
4410 | static int i915_displayport_test_data_show(struct seq_file *m, void *data) | |
4411 | { | |
4412 | struct drm_device *dev = m->private; | |
4413 | struct drm_connector *connector; | |
4414 | struct list_head *connector_list = &dev->mode_config.connector_list; | |
4415 | struct intel_dp *intel_dp; | |
4416 | ||
eb3394fa TP |
4417 | list_for_each_entry(connector, connector_list, head) { |
4418 | ||
4419 | if (connector->connector_type != | |
4420 | DRM_MODE_CONNECTOR_DisplayPort) | |
4421 | continue; | |
4422 | ||
4423 | if (connector->status == connector_status_connected && | |
4424 | connector->encoder != NULL) { | |
4425 | intel_dp = enc_to_intel_dp(connector->encoder); | |
4426 | seq_printf(m, "%lx", intel_dp->compliance_test_data); | |
4427 | } else | |
4428 | seq_puts(m, "0"); | |
4429 | } | |
4430 | ||
4431 | return 0; | |
4432 | } | |
4433 | static int i915_displayport_test_data_open(struct inode *inode, | |
4434 | struct file *file) | |
4435 | { | |
4436 | struct drm_device *dev = inode->i_private; | |
4437 | ||
4438 | return single_open(file, i915_displayport_test_data_show, dev); | |
4439 | } | |
4440 | ||
4441 | static const struct file_operations i915_displayport_test_data_fops = { | |
4442 | .owner = THIS_MODULE, | |
4443 | .open = i915_displayport_test_data_open, | |
4444 | .read = seq_read, | |
4445 | .llseek = seq_lseek, | |
4446 | .release = single_release | |
4447 | }; | |
4448 | ||
4449 | static int i915_displayport_test_type_show(struct seq_file *m, void *data) | |
4450 | { | |
4451 | struct drm_device *dev = m->private; | |
4452 | struct drm_connector *connector; | |
4453 | struct list_head *connector_list = &dev->mode_config.connector_list; | |
4454 | struct intel_dp *intel_dp; | |
4455 | ||
eb3394fa TP |
4456 | list_for_each_entry(connector, connector_list, head) { |
4457 | ||
4458 | if (connector->connector_type != | |
4459 | DRM_MODE_CONNECTOR_DisplayPort) | |
4460 | continue; | |
4461 | ||
4462 | if (connector->status == connector_status_connected && | |
4463 | connector->encoder != NULL) { | |
4464 | intel_dp = enc_to_intel_dp(connector->encoder); | |
4465 | seq_printf(m, "%02lx", intel_dp->compliance_test_type); | |
4466 | } else | |
4467 | seq_puts(m, "0"); | |
4468 | } | |
4469 | ||
4470 | return 0; | |
4471 | } | |
4472 | ||
4473 | static int i915_displayport_test_type_open(struct inode *inode, | |
4474 | struct file *file) | |
4475 | { | |
4476 | struct drm_device *dev = inode->i_private; | |
4477 | ||
4478 | return single_open(file, i915_displayport_test_type_show, dev); | |
4479 | } | |
4480 | ||
4481 | static const struct file_operations i915_displayport_test_type_fops = { | |
4482 | .owner = THIS_MODULE, | |
4483 | .open = i915_displayport_test_type_open, | |
4484 | .read = seq_read, | |
4485 | .llseek = seq_lseek, | |
4486 | .release = single_release | |
4487 | }; | |
4488 | ||
97e94b22 | 4489 | static void wm_latency_show(struct seq_file *m, const uint16_t wm[8]) |
369a1342 VS |
4490 | { |
4491 | struct drm_device *dev = m->private; | |
369a1342 | 4492 | int level; |
de38b95c VS |
4493 | int num_levels; |
4494 | ||
4495 | if (IS_CHERRYVIEW(dev)) | |
4496 | num_levels = 3; | |
4497 | else if (IS_VALLEYVIEW(dev)) | |
4498 | num_levels = 1; | |
4499 | else | |
4500 | num_levels = ilk_wm_max_level(dev) + 1; | |
369a1342 VS |
4501 | |
4502 | drm_modeset_lock_all(dev); | |
4503 | ||
4504 | for (level = 0; level < num_levels; level++) { | |
4505 | unsigned int latency = wm[level]; | |
4506 | ||
97e94b22 DL |
4507 | /* |
4508 | * - WM1+ latency values in 0.5us units | |
de38b95c | 4509 | * - latencies are in us on gen9/vlv/chv |
97e94b22 | 4510 | */ |
666a4537 WB |
4511 | if (INTEL_INFO(dev)->gen >= 9 || IS_VALLEYVIEW(dev) || |
4512 | IS_CHERRYVIEW(dev)) | |
97e94b22 DL |
4513 | latency *= 10; |
4514 | else if (level > 0) | |
369a1342 VS |
4515 | latency *= 5; |
4516 | ||
4517 | seq_printf(m, "WM%d %u (%u.%u usec)\n", | |
97e94b22 | 4518 | level, wm[level], latency / 10, latency % 10); |
369a1342 VS |
4519 | } |
4520 | ||
4521 | drm_modeset_unlock_all(dev); | |
4522 | } | |
4523 | ||
4524 | static int pri_wm_latency_show(struct seq_file *m, void *data) | |
4525 | { | |
4526 | struct drm_device *dev = m->private; | |
97e94b22 DL |
4527 | struct drm_i915_private *dev_priv = dev->dev_private; |
4528 | const uint16_t *latencies; | |
4529 | ||
4530 | if (INTEL_INFO(dev)->gen >= 9) | |
4531 | latencies = dev_priv->wm.skl_latency; | |
4532 | else | |
4533 | latencies = to_i915(dev)->wm.pri_latency; | |
369a1342 | 4534 | |
97e94b22 | 4535 | wm_latency_show(m, latencies); |
369a1342 VS |
4536 | |
4537 | return 0; | |
4538 | } | |
4539 | ||
4540 | static int spr_wm_latency_show(struct seq_file *m, void *data) | |
4541 | { | |
4542 | struct drm_device *dev = m->private; | |
97e94b22 DL |
4543 | struct drm_i915_private *dev_priv = dev->dev_private; |
4544 | const uint16_t *latencies; | |
4545 | ||
4546 | if (INTEL_INFO(dev)->gen >= 9) | |
4547 | latencies = dev_priv->wm.skl_latency; | |
4548 | else | |
4549 | latencies = to_i915(dev)->wm.spr_latency; | |
369a1342 | 4550 | |
97e94b22 | 4551 | wm_latency_show(m, latencies); |
369a1342 VS |
4552 | |
4553 | return 0; | |
4554 | } | |
4555 | ||
4556 | static int cur_wm_latency_show(struct seq_file *m, void *data) | |
4557 | { | |
4558 | struct drm_device *dev = m->private; | |
97e94b22 DL |
4559 | struct drm_i915_private *dev_priv = dev->dev_private; |
4560 | const uint16_t *latencies; | |
4561 | ||
4562 | if (INTEL_INFO(dev)->gen >= 9) | |
4563 | latencies = dev_priv->wm.skl_latency; | |
4564 | else | |
4565 | latencies = to_i915(dev)->wm.cur_latency; | |
369a1342 | 4566 | |
97e94b22 | 4567 | wm_latency_show(m, latencies); |
369a1342 VS |
4568 | |
4569 | return 0; | |
4570 | } | |
4571 | ||
4572 | static int pri_wm_latency_open(struct inode *inode, struct file *file) | |
4573 | { | |
4574 | struct drm_device *dev = inode->i_private; | |
4575 | ||
de38b95c | 4576 | if (INTEL_INFO(dev)->gen < 5) |
369a1342 VS |
4577 | return -ENODEV; |
4578 | ||
4579 | return single_open(file, pri_wm_latency_show, dev); | |
4580 | } | |
4581 | ||
4582 | static int spr_wm_latency_open(struct inode *inode, struct file *file) | |
4583 | { | |
4584 | struct drm_device *dev = inode->i_private; | |
4585 | ||
9ad0257c | 4586 | if (HAS_GMCH_DISPLAY(dev)) |
369a1342 VS |
4587 | return -ENODEV; |
4588 | ||
4589 | return single_open(file, spr_wm_latency_show, dev); | |
4590 | } | |
4591 | ||
4592 | static int cur_wm_latency_open(struct inode *inode, struct file *file) | |
4593 | { | |
4594 | struct drm_device *dev = inode->i_private; | |
4595 | ||
9ad0257c | 4596 | if (HAS_GMCH_DISPLAY(dev)) |
369a1342 VS |
4597 | return -ENODEV; |
4598 | ||
4599 | return single_open(file, cur_wm_latency_show, dev); | |
4600 | } | |
4601 | ||
4602 | static ssize_t wm_latency_write(struct file *file, const char __user *ubuf, | |
97e94b22 | 4603 | size_t len, loff_t *offp, uint16_t wm[8]) |
369a1342 VS |
4604 | { |
4605 | struct seq_file *m = file->private_data; | |
4606 | struct drm_device *dev = m->private; | |
97e94b22 | 4607 | uint16_t new[8] = { 0 }; |
de38b95c | 4608 | int num_levels; |
369a1342 VS |
4609 | int level; |
4610 | int ret; | |
4611 | char tmp[32]; | |
4612 | ||
de38b95c VS |
4613 | if (IS_CHERRYVIEW(dev)) |
4614 | num_levels = 3; | |
4615 | else if (IS_VALLEYVIEW(dev)) | |
4616 | num_levels = 1; | |
4617 | else | |
4618 | num_levels = ilk_wm_max_level(dev) + 1; | |
4619 | ||
369a1342 VS |
4620 | if (len >= sizeof(tmp)) |
4621 | return -EINVAL; | |
4622 | ||
4623 | if (copy_from_user(tmp, ubuf, len)) | |
4624 | return -EFAULT; | |
4625 | ||
4626 | tmp[len] = '\0'; | |
4627 | ||
97e94b22 DL |
4628 | ret = sscanf(tmp, "%hu %hu %hu %hu %hu %hu %hu %hu", |
4629 | &new[0], &new[1], &new[2], &new[3], | |
4630 | &new[4], &new[5], &new[6], &new[7]); | |
369a1342 VS |
4631 | if (ret != num_levels) |
4632 | return -EINVAL; | |
4633 | ||
4634 | drm_modeset_lock_all(dev); | |
4635 | ||
4636 | for (level = 0; level < num_levels; level++) | |
4637 | wm[level] = new[level]; | |
4638 | ||
4639 | drm_modeset_unlock_all(dev); | |
4640 | ||
4641 | return len; | |
4642 | } | |
4643 | ||
4644 | ||
4645 | static ssize_t pri_wm_latency_write(struct file *file, const char __user *ubuf, | |
4646 | size_t len, loff_t *offp) | |
4647 | { | |
4648 | struct seq_file *m = file->private_data; | |
4649 | struct drm_device *dev = m->private; | |
97e94b22 DL |
4650 | struct drm_i915_private *dev_priv = dev->dev_private; |
4651 | uint16_t *latencies; | |
369a1342 | 4652 | |
97e94b22 DL |
4653 | if (INTEL_INFO(dev)->gen >= 9) |
4654 | latencies = dev_priv->wm.skl_latency; | |
4655 | else | |
4656 | latencies = to_i915(dev)->wm.pri_latency; | |
4657 | ||
4658 | return wm_latency_write(file, ubuf, len, offp, latencies); | |
369a1342 VS |
4659 | } |
4660 | ||
4661 | static ssize_t spr_wm_latency_write(struct file *file, const char __user *ubuf, | |
4662 | size_t len, loff_t *offp) | |
4663 | { | |
4664 | struct seq_file *m = file->private_data; | |
4665 | struct drm_device *dev = m->private; | |
97e94b22 DL |
4666 | struct drm_i915_private *dev_priv = dev->dev_private; |
4667 | uint16_t *latencies; | |
369a1342 | 4668 | |
97e94b22 DL |
4669 | if (INTEL_INFO(dev)->gen >= 9) |
4670 | latencies = dev_priv->wm.skl_latency; | |
4671 | else | |
4672 | latencies = to_i915(dev)->wm.spr_latency; | |
4673 | ||
4674 | return wm_latency_write(file, ubuf, len, offp, latencies); | |
369a1342 VS |
4675 | } |
4676 | ||
4677 | static ssize_t cur_wm_latency_write(struct file *file, const char __user *ubuf, | |
4678 | size_t len, loff_t *offp) | |
4679 | { | |
4680 | struct seq_file *m = file->private_data; | |
4681 | struct drm_device *dev = m->private; | |
97e94b22 DL |
4682 | struct drm_i915_private *dev_priv = dev->dev_private; |
4683 | uint16_t *latencies; | |
4684 | ||
4685 | if (INTEL_INFO(dev)->gen >= 9) | |
4686 | latencies = dev_priv->wm.skl_latency; | |
4687 | else | |
4688 | latencies = to_i915(dev)->wm.cur_latency; | |
369a1342 | 4689 | |
97e94b22 | 4690 | return wm_latency_write(file, ubuf, len, offp, latencies); |
369a1342 VS |
4691 | } |
4692 | ||
4693 | static const struct file_operations i915_pri_wm_latency_fops = { | |
4694 | .owner = THIS_MODULE, | |
4695 | .open = pri_wm_latency_open, | |
4696 | .read = seq_read, | |
4697 | .llseek = seq_lseek, | |
4698 | .release = single_release, | |
4699 | .write = pri_wm_latency_write | |
4700 | }; | |
4701 | ||
4702 | static const struct file_operations i915_spr_wm_latency_fops = { | |
4703 | .owner = THIS_MODULE, | |
4704 | .open = spr_wm_latency_open, | |
4705 | .read = seq_read, | |
4706 | .llseek = seq_lseek, | |
4707 | .release = single_release, | |
4708 | .write = spr_wm_latency_write | |
4709 | }; | |
4710 | ||
4711 | static const struct file_operations i915_cur_wm_latency_fops = { | |
4712 | .owner = THIS_MODULE, | |
4713 | .open = cur_wm_latency_open, | |
4714 | .read = seq_read, | |
4715 | .llseek = seq_lseek, | |
4716 | .release = single_release, | |
4717 | .write = cur_wm_latency_write | |
4718 | }; | |
4719 | ||
647416f9 KC |
4720 | static int |
4721 | i915_wedged_get(void *data, u64 *val) | |
f3cd474b | 4722 | { |
647416f9 | 4723 | struct drm_device *dev = data; |
e277a1f8 | 4724 | struct drm_i915_private *dev_priv = dev->dev_private; |
f3cd474b | 4725 | |
647416f9 | 4726 | *val = atomic_read(&dev_priv->gpu_error.reset_counter); |
f3cd474b | 4727 | |
647416f9 | 4728 | return 0; |
f3cd474b CW |
4729 | } |
4730 | ||
647416f9 KC |
4731 | static int |
4732 | i915_wedged_set(void *data, u64 val) | |
f3cd474b | 4733 | { |
647416f9 | 4734 | struct drm_device *dev = data; |
d46c0517 ID |
4735 | struct drm_i915_private *dev_priv = dev->dev_private; |
4736 | ||
b8d24a06 MK |
4737 | /* |
4738 | * There is no safeguard against this debugfs entry colliding | |
4739 | * with the hangcheck calling same i915_handle_error() in | |
4740 | * parallel, causing an explosion. For now we assume that the | |
4741 | * test harness is responsible enough not to inject gpu hangs | |
4742 | * while it is writing to 'i915_wedged' | |
4743 | */ | |
4744 | ||
4745 | if (i915_reset_in_progress(&dev_priv->gpu_error)) | |
4746 | return -EAGAIN; | |
4747 | ||
d46c0517 | 4748 | intel_runtime_pm_get(dev_priv); |
f3cd474b | 4749 | |
58174462 MK |
4750 | i915_handle_error(dev, val, |
4751 | "Manually setting wedged to %llu", val); | |
d46c0517 ID |
4752 | |
4753 | intel_runtime_pm_put(dev_priv); | |
4754 | ||
647416f9 | 4755 | return 0; |
f3cd474b CW |
4756 | } |
4757 | ||
647416f9 KC |
4758 | DEFINE_SIMPLE_ATTRIBUTE(i915_wedged_fops, |
4759 | i915_wedged_get, i915_wedged_set, | |
3a3b4f98 | 4760 | "%llu\n"); |
f3cd474b | 4761 | |
647416f9 KC |
4762 | static int |
4763 | i915_ring_stop_get(void *data, u64 *val) | |
e5eb3d63 | 4764 | { |
647416f9 | 4765 | struct drm_device *dev = data; |
e277a1f8 | 4766 | struct drm_i915_private *dev_priv = dev->dev_private; |
e5eb3d63 | 4767 | |
647416f9 | 4768 | *val = dev_priv->gpu_error.stop_rings; |
e5eb3d63 | 4769 | |
647416f9 | 4770 | return 0; |
e5eb3d63 DV |
4771 | } |
4772 | ||
647416f9 KC |
4773 | static int |
4774 | i915_ring_stop_set(void *data, u64 val) | |
e5eb3d63 | 4775 | { |
647416f9 | 4776 | struct drm_device *dev = data; |
e5eb3d63 | 4777 | struct drm_i915_private *dev_priv = dev->dev_private; |
647416f9 | 4778 | int ret; |
e5eb3d63 | 4779 | |
647416f9 | 4780 | DRM_DEBUG_DRIVER("Stopping rings 0x%08llx\n", val); |
e5eb3d63 | 4781 | |
22bcfc6a DV |
4782 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
4783 | if (ret) | |
4784 | return ret; | |
4785 | ||
99584db3 | 4786 | dev_priv->gpu_error.stop_rings = val; |
e5eb3d63 DV |
4787 | mutex_unlock(&dev->struct_mutex); |
4788 | ||
647416f9 | 4789 | return 0; |
e5eb3d63 DV |
4790 | } |
4791 | ||
647416f9 KC |
4792 | DEFINE_SIMPLE_ATTRIBUTE(i915_ring_stop_fops, |
4793 | i915_ring_stop_get, i915_ring_stop_set, | |
4794 | "0x%08llx\n"); | |
d5442303 | 4795 | |
094f9a54 CW |
4796 | static int |
4797 | i915_ring_missed_irq_get(void *data, u64 *val) | |
4798 | { | |
4799 | struct drm_device *dev = data; | |
4800 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4801 | ||
4802 | *val = dev_priv->gpu_error.missed_irq_rings; | |
4803 | return 0; | |
4804 | } | |
4805 | ||
4806 | static int | |
4807 | i915_ring_missed_irq_set(void *data, u64 val) | |
4808 | { | |
4809 | struct drm_device *dev = data; | |
4810 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4811 | int ret; | |
4812 | ||
4813 | /* Lock against concurrent debugfs callers */ | |
4814 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
4815 | if (ret) | |
4816 | return ret; | |
4817 | dev_priv->gpu_error.missed_irq_rings = val; | |
4818 | mutex_unlock(&dev->struct_mutex); | |
4819 | ||
4820 | return 0; | |
4821 | } | |
4822 | ||
4823 | DEFINE_SIMPLE_ATTRIBUTE(i915_ring_missed_irq_fops, | |
4824 | i915_ring_missed_irq_get, i915_ring_missed_irq_set, | |
4825 | "0x%08llx\n"); | |
4826 | ||
4827 | static int | |
4828 | i915_ring_test_irq_get(void *data, u64 *val) | |
4829 | { | |
4830 | struct drm_device *dev = data; | |
4831 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4832 | ||
4833 | *val = dev_priv->gpu_error.test_irq_rings; | |
4834 | ||
4835 | return 0; | |
4836 | } | |
4837 | ||
4838 | static int | |
4839 | i915_ring_test_irq_set(void *data, u64 val) | |
4840 | { | |
4841 | struct drm_device *dev = data; | |
4842 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4843 | int ret; | |
4844 | ||
4845 | DRM_DEBUG_DRIVER("Masking interrupts on rings 0x%08llx\n", val); | |
4846 | ||
4847 | /* Lock against concurrent debugfs callers */ | |
4848 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
4849 | if (ret) | |
4850 | return ret; | |
4851 | ||
4852 | dev_priv->gpu_error.test_irq_rings = val; | |
4853 | mutex_unlock(&dev->struct_mutex); | |
4854 | ||
4855 | return 0; | |
4856 | } | |
4857 | ||
4858 | DEFINE_SIMPLE_ATTRIBUTE(i915_ring_test_irq_fops, | |
4859 | i915_ring_test_irq_get, i915_ring_test_irq_set, | |
4860 | "0x%08llx\n"); | |
4861 | ||
dd624afd CW |
4862 | #define DROP_UNBOUND 0x1 |
4863 | #define DROP_BOUND 0x2 | |
4864 | #define DROP_RETIRE 0x4 | |
4865 | #define DROP_ACTIVE 0x8 | |
4866 | #define DROP_ALL (DROP_UNBOUND | \ | |
4867 | DROP_BOUND | \ | |
4868 | DROP_RETIRE | \ | |
4869 | DROP_ACTIVE) | |
647416f9 KC |
4870 | static int |
4871 | i915_drop_caches_get(void *data, u64 *val) | |
dd624afd | 4872 | { |
647416f9 | 4873 | *val = DROP_ALL; |
dd624afd | 4874 | |
647416f9 | 4875 | return 0; |
dd624afd CW |
4876 | } |
4877 | ||
647416f9 KC |
4878 | static int |
4879 | i915_drop_caches_set(void *data, u64 val) | |
dd624afd | 4880 | { |
647416f9 | 4881 | struct drm_device *dev = data; |
dd624afd | 4882 | struct drm_i915_private *dev_priv = dev->dev_private; |
647416f9 | 4883 | int ret; |
dd624afd | 4884 | |
2f9fe5ff | 4885 | DRM_DEBUG("Dropping caches: 0x%08llx\n", val); |
dd624afd CW |
4886 | |
4887 | /* No need to check and wait for gpu resets, only libdrm auto-restarts | |
4888 | * on ioctls on -EAGAIN. */ | |
4889 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
4890 | if (ret) | |
4891 | return ret; | |
4892 | ||
4893 | if (val & DROP_ACTIVE) { | |
4894 | ret = i915_gpu_idle(dev); | |
4895 | if (ret) | |
4896 | goto unlock; | |
4897 | } | |
4898 | ||
4899 | if (val & (DROP_RETIRE | DROP_ACTIVE)) | |
4900 | i915_gem_retire_requests(dev); | |
4901 | ||
21ab4e74 CW |
4902 | if (val & DROP_BOUND) |
4903 | i915_gem_shrink(dev_priv, LONG_MAX, I915_SHRINK_BOUND); | |
4ad72b7f | 4904 | |
21ab4e74 CW |
4905 | if (val & DROP_UNBOUND) |
4906 | i915_gem_shrink(dev_priv, LONG_MAX, I915_SHRINK_UNBOUND); | |
dd624afd CW |
4907 | |
4908 | unlock: | |
4909 | mutex_unlock(&dev->struct_mutex); | |
4910 | ||
647416f9 | 4911 | return ret; |
dd624afd CW |
4912 | } |
4913 | ||
647416f9 KC |
4914 | DEFINE_SIMPLE_ATTRIBUTE(i915_drop_caches_fops, |
4915 | i915_drop_caches_get, i915_drop_caches_set, | |
4916 | "0x%08llx\n"); | |
dd624afd | 4917 | |
647416f9 KC |
4918 | static int |
4919 | i915_max_freq_get(void *data, u64 *val) | |
358733e9 | 4920 | { |
647416f9 | 4921 | struct drm_device *dev = data; |
e277a1f8 | 4922 | struct drm_i915_private *dev_priv = dev->dev_private; |
647416f9 | 4923 | int ret; |
004777cb | 4924 | |
daa3afb2 | 4925 | if (INTEL_INFO(dev)->gen < 6) |
004777cb DV |
4926 | return -ENODEV; |
4927 | ||
5c9669ce TR |
4928 | flush_delayed_work(&dev_priv->rps.delayed_resume_work); |
4929 | ||
4fc688ce | 4930 | ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock); |
004777cb DV |
4931 | if (ret) |
4932 | return ret; | |
358733e9 | 4933 | |
7c59a9c1 | 4934 | *val = intel_gpu_freq(dev_priv, dev_priv->rps.max_freq_softlimit); |
4fc688ce | 4935 | mutex_unlock(&dev_priv->rps.hw_lock); |
358733e9 | 4936 | |
647416f9 | 4937 | return 0; |
358733e9 JB |
4938 | } |
4939 | ||
647416f9 KC |
4940 | static int |
4941 | i915_max_freq_set(void *data, u64 val) | |
358733e9 | 4942 | { |
647416f9 | 4943 | struct drm_device *dev = data; |
358733e9 | 4944 | struct drm_i915_private *dev_priv = dev->dev_private; |
bc4d91f6 | 4945 | u32 hw_max, hw_min; |
647416f9 | 4946 | int ret; |
004777cb | 4947 | |
daa3afb2 | 4948 | if (INTEL_INFO(dev)->gen < 6) |
004777cb | 4949 | return -ENODEV; |
358733e9 | 4950 | |
5c9669ce TR |
4951 | flush_delayed_work(&dev_priv->rps.delayed_resume_work); |
4952 | ||
647416f9 | 4953 | DRM_DEBUG_DRIVER("Manually setting max freq to %llu\n", val); |
358733e9 | 4954 | |
4fc688ce | 4955 | ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock); |
004777cb DV |
4956 | if (ret) |
4957 | return ret; | |
4958 | ||
358733e9 JB |
4959 | /* |
4960 | * Turbo will still be enabled, but won't go above the set value. | |
4961 | */ | |
bc4d91f6 | 4962 | val = intel_freq_opcode(dev_priv, val); |
dd0a1aa1 | 4963 | |
bc4d91f6 AG |
4964 | hw_max = dev_priv->rps.max_freq; |
4965 | hw_min = dev_priv->rps.min_freq; | |
dd0a1aa1 | 4966 | |
b39fb297 | 4967 | if (val < hw_min || val > hw_max || val < dev_priv->rps.min_freq_softlimit) { |
dd0a1aa1 JM |
4968 | mutex_unlock(&dev_priv->rps.hw_lock); |
4969 | return -EINVAL; | |
0a073b84 JB |
4970 | } |
4971 | ||
b39fb297 | 4972 | dev_priv->rps.max_freq_softlimit = val; |
dd0a1aa1 | 4973 | |
ffe02b40 | 4974 | intel_set_rps(dev, val); |
dd0a1aa1 | 4975 | |
4fc688ce | 4976 | mutex_unlock(&dev_priv->rps.hw_lock); |
358733e9 | 4977 | |
647416f9 | 4978 | return 0; |
358733e9 JB |
4979 | } |
4980 | ||
647416f9 KC |
4981 | DEFINE_SIMPLE_ATTRIBUTE(i915_max_freq_fops, |
4982 | i915_max_freq_get, i915_max_freq_set, | |
3a3b4f98 | 4983 | "%llu\n"); |
358733e9 | 4984 | |
647416f9 KC |
4985 | static int |
4986 | i915_min_freq_get(void *data, u64 *val) | |
1523c310 | 4987 | { |
647416f9 | 4988 | struct drm_device *dev = data; |
e277a1f8 | 4989 | struct drm_i915_private *dev_priv = dev->dev_private; |
647416f9 | 4990 | int ret; |
004777cb | 4991 | |
daa3afb2 | 4992 | if (INTEL_INFO(dev)->gen < 6) |
004777cb DV |
4993 | return -ENODEV; |
4994 | ||
5c9669ce TR |
4995 | flush_delayed_work(&dev_priv->rps.delayed_resume_work); |
4996 | ||
4fc688ce | 4997 | ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock); |
004777cb DV |
4998 | if (ret) |
4999 | return ret; | |
1523c310 | 5000 | |
7c59a9c1 | 5001 | *val = intel_gpu_freq(dev_priv, dev_priv->rps.min_freq_softlimit); |
4fc688ce | 5002 | mutex_unlock(&dev_priv->rps.hw_lock); |
1523c310 | 5003 | |
647416f9 | 5004 | return 0; |
1523c310 JB |
5005 | } |
5006 | ||
647416f9 KC |
5007 | static int |
5008 | i915_min_freq_set(void *data, u64 val) | |
1523c310 | 5009 | { |
647416f9 | 5010 | struct drm_device *dev = data; |
1523c310 | 5011 | struct drm_i915_private *dev_priv = dev->dev_private; |
bc4d91f6 | 5012 | u32 hw_max, hw_min; |
647416f9 | 5013 | int ret; |
004777cb | 5014 | |
daa3afb2 | 5015 | if (INTEL_INFO(dev)->gen < 6) |
004777cb | 5016 | return -ENODEV; |
1523c310 | 5017 | |
5c9669ce TR |
5018 | flush_delayed_work(&dev_priv->rps.delayed_resume_work); |
5019 | ||
647416f9 | 5020 | DRM_DEBUG_DRIVER("Manually setting min freq to %llu\n", val); |
1523c310 | 5021 | |
4fc688ce | 5022 | ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock); |
004777cb DV |
5023 | if (ret) |
5024 | return ret; | |
5025 | ||
1523c310 JB |
5026 | /* |
5027 | * Turbo will still be enabled, but won't go below the set value. | |
5028 | */ | |
bc4d91f6 | 5029 | val = intel_freq_opcode(dev_priv, val); |
dd0a1aa1 | 5030 | |
bc4d91f6 AG |
5031 | hw_max = dev_priv->rps.max_freq; |
5032 | hw_min = dev_priv->rps.min_freq; | |
dd0a1aa1 | 5033 | |
b39fb297 | 5034 | if (val < hw_min || val > hw_max || val > dev_priv->rps.max_freq_softlimit) { |
dd0a1aa1 JM |
5035 | mutex_unlock(&dev_priv->rps.hw_lock); |
5036 | return -EINVAL; | |
0a073b84 | 5037 | } |
dd0a1aa1 | 5038 | |
b39fb297 | 5039 | dev_priv->rps.min_freq_softlimit = val; |
dd0a1aa1 | 5040 | |
ffe02b40 | 5041 | intel_set_rps(dev, val); |
dd0a1aa1 | 5042 | |
4fc688ce | 5043 | mutex_unlock(&dev_priv->rps.hw_lock); |
1523c310 | 5044 | |
647416f9 | 5045 | return 0; |
1523c310 JB |
5046 | } |
5047 | ||
647416f9 KC |
5048 | DEFINE_SIMPLE_ATTRIBUTE(i915_min_freq_fops, |
5049 | i915_min_freq_get, i915_min_freq_set, | |
3a3b4f98 | 5050 | "%llu\n"); |
1523c310 | 5051 | |
647416f9 KC |
5052 | static int |
5053 | i915_cache_sharing_get(void *data, u64 *val) | |
07b7ddd9 | 5054 | { |
647416f9 | 5055 | struct drm_device *dev = data; |
e277a1f8 | 5056 | struct drm_i915_private *dev_priv = dev->dev_private; |
07b7ddd9 | 5057 | u32 snpcr; |
647416f9 | 5058 | int ret; |
07b7ddd9 | 5059 | |
004777cb DV |
5060 | if (!(IS_GEN6(dev) || IS_GEN7(dev))) |
5061 | return -ENODEV; | |
5062 | ||
22bcfc6a DV |
5063 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
5064 | if (ret) | |
5065 | return ret; | |
c8c8fb33 | 5066 | intel_runtime_pm_get(dev_priv); |
22bcfc6a | 5067 | |
07b7ddd9 | 5068 | snpcr = I915_READ(GEN6_MBCUNIT_SNPCR); |
c8c8fb33 PZ |
5069 | |
5070 | intel_runtime_pm_put(dev_priv); | |
07b7ddd9 JB |
5071 | mutex_unlock(&dev_priv->dev->struct_mutex); |
5072 | ||
647416f9 | 5073 | *val = (snpcr & GEN6_MBC_SNPCR_MASK) >> GEN6_MBC_SNPCR_SHIFT; |
07b7ddd9 | 5074 | |
647416f9 | 5075 | return 0; |
07b7ddd9 JB |
5076 | } |
5077 | ||
647416f9 KC |
5078 | static int |
5079 | i915_cache_sharing_set(void *data, u64 val) | |
07b7ddd9 | 5080 | { |
647416f9 | 5081 | struct drm_device *dev = data; |
07b7ddd9 | 5082 | struct drm_i915_private *dev_priv = dev->dev_private; |
07b7ddd9 | 5083 | u32 snpcr; |
07b7ddd9 | 5084 | |
004777cb DV |
5085 | if (!(IS_GEN6(dev) || IS_GEN7(dev))) |
5086 | return -ENODEV; | |
5087 | ||
647416f9 | 5088 | if (val > 3) |
07b7ddd9 JB |
5089 | return -EINVAL; |
5090 | ||
c8c8fb33 | 5091 | intel_runtime_pm_get(dev_priv); |
647416f9 | 5092 | DRM_DEBUG_DRIVER("Manually setting uncore sharing to %llu\n", val); |
07b7ddd9 JB |
5093 | |
5094 | /* Update the cache sharing policy here as well */ | |
5095 | snpcr = I915_READ(GEN6_MBCUNIT_SNPCR); | |
5096 | snpcr &= ~GEN6_MBC_SNPCR_MASK; | |
5097 | snpcr |= (val << GEN6_MBC_SNPCR_SHIFT); | |
5098 | I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr); | |
5099 | ||
c8c8fb33 | 5100 | intel_runtime_pm_put(dev_priv); |
647416f9 | 5101 | return 0; |
07b7ddd9 JB |
5102 | } |
5103 | ||
647416f9 KC |
5104 | DEFINE_SIMPLE_ATTRIBUTE(i915_cache_sharing_fops, |
5105 | i915_cache_sharing_get, i915_cache_sharing_set, | |
5106 | "%llu\n"); | |
07b7ddd9 | 5107 | |
5d39525a JM |
5108 | struct sseu_dev_status { |
5109 | unsigned int slice_total; | |
5110 | unsigned int subslice_total; | |
5111 | unsigned int subslice_per_slice; | |
5112 | unsigned int eu_total; | |
5113 | unsigned int eu_per_subslice; | |
5114 | }; | |
5115 | ||
5116 | static void cherryview_sseu_device_status(struct drm_device *dev, | |
5117 | struct sseu_dev_status *stat) | |
5118 | { | |
5119 | struct drm_i915_private *dev_priv = dev->dev_private; | |
0a0b457f | 5120 | int ss_max = 2; |
5d39525a JM |
5121 | int ss; |
5122 | u32 sig1[ss_max], sig2[ss_max]; | |
5123 | ||
5124 | sig1[0] = I915_READ(CHV_POWER_SS0_SIG1); | |
5125 | sig1[1] = I915_READ(CHV_POWER_SS1_SIG1); | |
5126 | sig2[0] = I915_READ(CHV_POWER_SS0_SIG2); | |
5127 | sig2[1] = I915_READ(CHV_POWER_SS1_SIG2); | |
5128 | ||
5129 | for (ss = 0; ss < ss_max; ss++) { | |
5130 | unsigned int eu_cnt; | |
5131 | ||
5132 | if (sig1[ss] & CHV_SS_PG_ENABLE) | |
5133 | /* skip disabled subslice */ | |
5134 | continue; | |
5135 | ||
5136 | stat->slice_total = 1; | |
5137 | stat->subslice_per_slice++; | |
5138 | eu_cnt = ((sig1[ss] & CHV_EU08_PG_ENABLE) ? 0 : 2) + | |
5139 | ((sig1[ss] & CHV_EU19_PG_ENABLE) ? 0 : 2) + | |
5140 | ((sig1[ss] & CHV_EU210_PG_ENABLE) ? 0 : 2) + | |
5141 | ((sig2[ss] & CHV_EU311_PG_ENABLE) ? 0 : 2); | |
5142 | stat->eu_total += eu_cnt; | |
5143 | stat->eu_per_subslice = max(stat->eu_per_subslice, eu_cnt); | |
5144 | } | |
5145 | stat->subslice_total = stat->subslice_per_slice; | |
5146 | } | |
5147 | ||
5148 | static void gen9_sseu_device_status(struct drm_device *dev, | |
5149 | struct sseu_dev_status *stat) | |
5150 | { | |
5151 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1c046bc1 | 5152 | int s_max = 3, ss_max = 4; |
5d39525a JM |
5153 | int s, ss; |
5154 | u32 s_reg[s_max], eu_reg[2*s_max], eu_mask[2]; | |
5155 | ||
1c046bc1 JM |
5156 | /* BXT has a single slice and at most 3 subslices. */ |
5157 | if (IS_BROXTON(dev)) { | |
5158 | s_max = 1; | |
5159 | ss_max = 3; | |
5160 | } | |
5161 | ||
5162 | for (s = 0; s < s_max; s++) { | |
5163 | s_reg[s] = I915_READ(GEN9_SLICE_PGCTL_ACK(s)); | |
5164 | eu_reg[2*s] = I915_READ(GEN9_SS01_EU_PGCTL_ACK(s)); | |
5165 | eu_reg[2*s + 1] = I915_READ(GEN9_SS23_EU_PGCTL_ACK(s)); | |
5166 | } | |
5167 | ||
5d39525a JM |
5168 | eu_mask[0] = GEN9_PGCTL_SSA_EU08_ACK | |
5169 | GEN9_PGCTL_SSA_EU19_ACK | | |
5170 | GEN9_PGCTL_SSA_EU210_ACK | | |
5171 | GEN9_PGCTL_SSA_EU311_ACK; | |
5172 | eu_mask[1] = GEN9_PGCTL_SSB_EU08_ACK | | |
5173 | GEN9_PGCTL_SSB_EU19_ACK | | |
5174 | GEN9_PGCTL_SSB_EU210_ACK | | |
5175 | GEN9_PGCTL_SSB_EU311_ACK; | |
5176 | ||
5177 | for (s = 0; s < s_max; s++) { | |
1c046bc1 JM |
5178 | unsigned int ss_cnt = 0; |
5179 | ||
5d39525a JM |
5180 | if ((s_reg[s] & GEN9_PGCTL_SLICE_ACK) == 0) |
5181 | /* skip disabled slice */ | |
5182 | continue; | |
5183 | ||
5184 | stat->slice_total++; | |
1c046bc1 | 5185 | |
ef11bdb3 | 5186 | if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) |
1c046bc1 JM |
5187 | ss_cnt = INTEL_INFO(dev)->subslice_per_slice; |
5188 | ||
5d39525a JM |
5189 | for (ss = 0; ss < ss_max; ss++) { |
5190 | unsigned int eu_cnt; | |
5191 | ||
1c046bc1 JM |
5192 | if (IS_BROXTON(dev) && |
5193 | !(s_reg[s] & (GEN9_PGCTL_SS_ACK(ss)))) | |
5194 | /* skip disabled subslice */ | |
5195 | continue; | |
5196 | ||
5197 | if (IS_BROXTON(dev)) | |
5198 | ss_cnt++; | |
5199 | ||
5d39525a JM |
5200 | eu_cnt = 2 * hweight32(eu_reg[2*s + ss/2] & |
5201 | eu_mask[ss%2]); | |
5202 | stat->eu_total += eu_cnt; | |
5203 | stat->eu_per_subslice = max(stat->eu_per_subslice, | |
5204 | eu_cnt); | |
5205 | } | |
1c046bc1 JM |
5206 | |
5207 | stat->subslice_total += ss_cnt; | |
5208 | stat->subslice_per_slice = max(stat->subslice_per_slice, | |
5209 | ss_cnt); | |
5d39525a JM |
5210 | } |
5211 | } | |
5212 | ||
91bedd34 ŁD |
5213 | static void broadwell_sseu_device_status(struct drm_device *dev, |
5214 | struct sseu_dev_status *stat) | |
5215 | { | |
5216 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5217 | int s; | |
5218 | u32 slice_info = I915_READ(GEN8_GT_SLICE_INFO); | |
5219 | ||
5220 | stat->slice_total = hweight32(slice_info & GEN8_LSLICESTAT_MASK); | |
5221 | ||
5222 | if (stat->slice_total) { | |
5223 | stat->subslice_per_slice = INTEL_INFO(dev)->subslice_per_slice; | |
5224 | stat->subslice_total = stat->slice_total * | |
5225 | stat->subslice_per_slice; | |
5226 | stat->eu_per_subslice = INTEL_INFO(dev)->eu_per_subslice; | |
5227 | stat->eu_total = stat->eu_per_subslice * stat->subslice_total; | |
5228 | ||
5229 | /* subtract fused off EU(s) from enabled slice(s) */ | |
5230 | for (s = 0; s < stat->slice_total; s++) { | |
5231 | u8 subslice_7eu = INTEL_INFO(dev)->subslice_7eu[s]; | |
5232 | ||
5233 | stat->eu_total -= hweight8(subslice_7eu); | |
5234 | } | |
5235 | } | |
5236 | } | |
5237 | ||
3873218f JM |
5238 | static int i915_sseu_status(struct seq_file *m, void *unused) |
5239 | { | |
5240 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
5241 | struct drm_device *dev = node->minor->dev; | |
5d39525a | 5242 | struct sseu_dev_status stat; |
3873218f | 5243 | |
91bedd34 | 5244 | if (INTEL_INFO(dev)->gen < 8) |
3873218f JM |
5245 | return -ENODEV; |
5246 | ||
5247 | seq_puts(m, "SSEU Device Info\n"); | |
5248 | seq_printf(m, " Available Slice Total: %u\n", | |
5249 | INTEL_INFO(dev)->slice_total); | |
5250 | seq_printf(m, " Available Subslice Total: %u\n", | |
5251 | INTEL_INFO(dev)->subslice_total); | |
5252 | seq_printf(m, " Available Subslice Per Slice: %u\n", | |
5253 | INTEL_INFO(dev)->subslice_per_slice); | |
5254 | seq_printf(m, " Available EU Total: %u\n", | |
5255 | INTEL_INFO(dev)->eu_total); | |
5256 | seq_printf(m, " Available EU Per Subslice: %u\n", | |
5257 | INTEL_INFO(dev)->eu_per_subslice); | |
5258 | seq_printf(m, " Has Slice Power Gating: %s\n", | |
5259 | yesno(INTEL_INFO(dev)->has_slice_pg)); | |
5260 | seq_printf(m, " Has Subslice Power Gating: %s\n", | |
5261 | yesno(INTEL_INFO(dev)->has_subslice_pg)); | |
5262 | seq_printf(m, " Has EU Power Gating: %s\n", | |
5263 | yesno(INTEL_INFO(dev)->has_eu_pg)); | |
5264 | ||
7f992aba | 5265 | seq_puts(m, "SSEU Device Status\n"); |
5d39525a | 5266 | memset(&stat, 0, sizeof(stat)); |
5575f03a | 5267 | if (IS_CHERRYVIEW(dev)) { |
5d39525a | 5268 | cherryview_sseu_device_status(dev, &stat); |
91bedd34 ŁD |
5269 | } else if (IS_BROADWELL(dev)) { |
5270 | broadwell_sseu_device_status(dev, &stat); | |
1c046bc1 | 5271 | } else if (INTEL_INFO(dev)->gen >= 9) { |
5d39525a | 5272 | gen9_sseu_device_status(dev, &stat); |
7f992aba | 5273 | } |
5d39525a JM |
5274 | seq_printf(m, " Enabled Slice Total: %u\n", |
5275 | stat.slice_total); | |
5276 | seq_printf(m, " Enabled Subslice Total: %u\n", | |
5277 | stat.subslice_total); | |
5278 | seq_printf(m, " Enabled Subslice Per Slice: %u\n", | |
5279 | stat.subslice_per_slice); | |
5280 | seq_printf(m, " Enabled EU Total: %u\n", | |
5281 | stat.eu_total); | |
5282 | seq_printf(m, " Enabled EU Per Subslice: %u\n", | |
5283 | stat.eu_per_subslice); | |
7f992aba | 5284 | |
3873218f JM |
5285 | return 0; |
5286 | } | |
5287 | ||
6d794d42 BW |
5288 | static int i915_forcewake_open(struct inode *inode, struct file *file) |
5289 | { | |
5290 | struct drm_device *dev = inode->i_private; | |
5291 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6d794d42 | 5292 | |
075edca4 | 5293 | if (INTEL_INFO(dev)->gen < 6) |
6d794d42 BW |
5294 | return 0; |
5295 | ||
6daccb0b | 5296 | intel_runtime_pm_get(dev_priv); |
59bad947 | 5297 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); |
6d794d42 BW |
5298 | |
5299 | return 0; | |
5300 | } | |
5301 | ||
c43b5634 | 5302 | static int i915_forcewake_release(struct inode *inode, struct file *file) |
6d794d42 BW |
5303 | { |
5304 | struct drm_device *dev = inode->i_private; | |
5305 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5306 | ||
075edca4 | 5307 | if (INTEL_INFO(dev)->gen < 6) |
6d794d42 BW |
5308 | return 0; |
5309 | ||
59bad947 | 5310 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); |
6daccb0b | 5311 | intel_runtime_pm_put(dev_priv); |
6d794d42 BW |
5312 | |
5313 | return 0; | |
5314 | } | |
5315 | ||
5316 | static const struct file_operations i915_forcewake_fops = { | |
5317 | .owner = THIS_MODULE, | |
5318 | .open = i915_forcewake_open, | |
5319 | .release = i915_forcewake_release, | |
5320 | }; | |
5321 | ||
5322 | static int i915_forcewake_create(struct dentry *root, struct drm_minor *minor) | |
5323 | { | |
5324 | struct drm_device *dev = minor->dev; | |
5325 | struct dentry *ent; | |
5326 | ||
5327 | ent = debugfs_create_file("i915_forcewake_user", | |
8eb57294 | 5328 | S_IRUSR, |
6d794d42 BW |
5329 | root, dev, |
5330 | &i915_forcewake_fops); | |
f3c5fe97 WY |
5331 | if (!ent) |
5332 | return -ENOMEM; | |
6d794d42 | 5333 | |
8eb57294 | 5334 | return drm_add_fake_info_node(minor, ent, &i915_forcewake_fops); |
6d794d42 BW |
5335 | } |
5336 | ||
6a9c308d DV |
5337 | static int i915_debugfs_create(struct dentry *root, |
5338 | struct drm_minor *minor, | |
5339 | const char *name, | |
5340 | const struct file_operations *fops) | |
07b7ddd9 JB |
5341 | { |
5342 | struct drm_device *dev = minor->dev; | |
5343 | struct dentry *ent; | |
5344 | ||
6a9c308d | 5345 | ent = debugfs_create_file(name, |
07b7ddd9 JB |
5346 | S_IRUGO | S_IWUSR, |
5347 | root, dev, | |
6a9c308d | 5348 | fops); |
f3c5fe97 WY |
5349 | if (!ent) |
5350 | return -ENOMEM; | |
07b7ddd9 | 5351 | |
6a9c308d | 5352 | return drm_add_fake_info_node(minor, ent, fops); |
07b7ddd9 JB |
5353 | } |
5354 | ||
06c5bf8c | 5355 | static const struct drm_info_list i915_debugfs_list[] = { |
311bd68e | 5356 | {"i915_capabilities", i915_capabilities, 0}, |
73aa808f | 5357 | {"i915_gem_objects", i915_gem_object_info, 0}, |
08c18323 | 5358 | {"i915_gem_gtt", i915_gem_gtt_info, 0}, |
1b50247a | 5359 | {"i915_gem_pinned", i915_gem_gtt_info, 0, (void *) PINNED_LIST}, |
433e12f7 | 5360 | {"i915_gem_active", i915_gem_object_list_info, 0, (void *) ACTIVE_LIST}, |
433e12f7 | 5361 | {"i915_gem_inactive", i915_gem_object_list_info, 0, (void *) INACTIVE_LIST}, |
6d2b8885 | 5362 | {"i915_gem_stolen", i915_gem_stolen_list_info }, |
4e5359cd | 5363 | {"i915_gem_pageflip", i915_gem_pageflip_info, 0}, |
2017263e BG |
5364 | {"i915_gem_request", i915_gem_request_info, 0}, |
5365 | {"i915_gem_seqno", i915_gem_seqno_info, 0}, | |
a6172a80 | 5366 | {"i915_gem_fence_regs", i915_gem_fence_regs_info, 0}, |
2017263e | 5367 | {"i915_gem_interrupt", i915_interrupt_info, 0}, |
1ec14ad3 CW |
5368 | {"i915_gem_hws", i915_hws_info, 0, (void *)RCS}, |
5369 | {"i915_gem_hws_blt", i915_hws_info, 0, (void *)BCS}, | |
5370 | {"i915_gem_hws_bsd", i915_hws_info, 0, (void *)VCS}, | |
9010ebfd | 5371 | {"i915_gem_hws_vebox", i915_hws_info, 0, (void *)VECS}, |
493018dc | 5372 | {"i915_gem_batch_pool", i915_gem_batch_pool_info, 0}, |
8b417c26 | 5373 | {"i915_guc_info", i915_guc_info, 0}, |
fdf5d357 | 5374 | {"i915_guc_load_status", i915_guc_load_status_info, 0}, |
4c7e77fc | 5375 | {"i915_guc_log_dump", i915_guc_log_dump, 0}, |
adb4bd12 | 5376 | {"i915_frequency_info", i915_frequency_info, 0}, |
f654449a | 5377 | {"i915_hangcheck_info", i915_hangcheck_info, 0}, |
f97108d1 | 5378 | {"i915_drpc_info", i915_drpc_info, 0}, |
7648fa99 | 5379 | {"i915_emon_status", i915_emon_status, 0}, |
23b2f8bb | 5380 | {"i915_ring_freq_table", i915_ring_freq_table, 0}, |
9a851789 | 5381 | {"i915_frontbuffer_tracking", i915_frontbuffer_tracking, 0}, |
b5e50c3f | 5382 | {"i915_fbc_status", i915_fbc_status, 0}, |
92d44621 | 5383 | {"i915_ips_status", i915_ips_status, 0}, |
4a9bef37 | 5384 | {"i915_sr_status", i915_sr_status, 0}, |
44834a67 | 5385 | {"i915_opregion", i915_opregion, 0}, |
ada8f955 | 5386 | {"i915_vbt", i915_vbt, 0}, |
37811fcc | 5387 | {"i915_gem_framebuffer", i915_gem_framebuffer_info, 0}, |
e76d3630 | 5388 | {"i915_context_status", i915_context_status, 0}, |
c0ab1ae9 | 5389 | {"i915_dump_lrc", i915_dump_lrc, 0}, |
4ba70e44 | 5390 | {"i915_execlists", i915_execlists, 0}, |
f65367b5 | 5391 | {"i915_forcewake_domains", i915_forcewake_domains, 0}, |
ea16a3cd | 5392 | {"i915_swizzle_info", i915_swizzle_info, 0}, |
3cf17fc5 | 5393 | {"i915_ppgtt_info", i915_ppgtt_info, 0}, |
63573eb7 | 5394 | {"i915_llc", i915_llc, 0}, |
e91fd8c6 | 5395 | {"i915_edp_psr_status", i915_edp_psr_status, 0}, |
d2e216d0 | 5396 | {"i915_sink_crc_eDP1", i915_sink_crc, 0}, |
ec013e7f | 5397 | {"i915_energy_uJ", i915_energy_uJ, 0}, |
6455c870 | 5398 | {"i915_runtime_pm_status", i915_runtime_pm_status, 0}, |
1da51581 | 5399 | {"i915_power_domain_info", i915_power_domain_info, 0}, |
b7cec66d | 5400 | {"i915_dmc_info", i915_dmc_info, 0}, |
53f5e3ca | 5401 | {"i915_display_info", i915_display_info, 0}, |
e04934cf | 5402 | {"i915_semaphore_status", i915_semaphore_status, 0}, |
728e29d7 | 5403 | {"i915_shared_dplls_info", i915_shared_dplls_info, 0}, |
11bed958 | 5404 | {"i915_dp_mst_info", i915_dp_mst_info, 0}, |
1ed1ef9d | 5405 | {"i915_wa_registers", i915_wa_registers, 0}, |
c5511e44 | 5406 | {"i915_ddb_info", i915_ddb_info, 0}, |
3873218f | 5407 | {"i915_sseu_status", i915_sseu_status, 0}, |
a54746e3 | 5408 | {"i915_drrs_status", i915_drrs_status, 0}, |
1854d5ca | 5409 | {"i915_rps_boost_info", i915_rps_boost_info, 0}, |
2017263e | 5410 | }; |
27c202ad | 5411 | #define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list) |
2017263e | 5412 | |
06c5bf8c | 5413 | static const struct i915_debugfs_files { |
34b9674c DV |
5414 | const char *name; |
5415 | const struct file_operations *fops; | |
5416 | } i915_debugfs_files[] = { | |
5417 | {"i915_wedged", &i915_wedged_fops}, | |
5418 | {"i915_max_freq", &i915_max_freq_fops}, | |
5419 | {"i915_min_freq", &i915_min_freq_fops}, | |
5420 | {"i915_cache_sharing", &i915_cache_sharing_fops}, | |
5421 | {"i915_ring_stop", &i915_ring_stop_fops}, | |
094f9a54 CW |
5422 | {"i915_ring_missed_irq", &i915_ring_missed_irq_fops}, |
5423 | {"i915_ring_test_irq", &i915_ring_test_irq_fops}, | |
34b9674c DV |
5424 | {"i915_gem_drop_caches", &i915_drop_caches_fops}, |
5425 | {"i915_error_state", &i915_error_state_fops}, | |
5426 | {"i915_next_seqno", &i915_next_seqno_fops}, | |
bd9db02f | 5427 | {"i915_display_crc_ctl", &i915_display_crc_ctl_fops}, |
369a1342 VS |
5428 | {"i915_pri_wm_latency", &i915_pri_wm_latency_fops}, |
5429 | {"i915_spr_wm_latency", &i915_spr_wm_latency_fops}, | |
5430 | {"i915_cur_wm_latency", &i915_cur_wm_latency_fops}, | |
da46f936 | 5431 | {"i915_fbc_false_color", &i915_fbc_fc_fops}, |
eb3394fa TP |
5432 | {"i915_dp_test_data", &i915_displayport_test_data_fops}, |
5433 | {"i915_dp_test_type", &i915_displayport_test_type_fops}, | |
5434 | {"i915_dp_test_active", &i915_displayport_test_active_fops} | |
34b9674c DV |
5435 | }; |
5436 | ||
07144428 DL |
5437 | void intel_display_crc_init(struct drm_device *dev) |
5438 | { | |
5439 | struct drm_i915_private *dev_priv = dev->dev_private; | |
b378360e | 5440 | enum pipe pipe; |
07144428 | 5441 | |
055e393f | 5442 | for_each_pipe(dev_priv, pipe) { |
b378360e | 5443 | struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe]; |
07144428 | 5444 | |
d538bbdf DL |
5445 | pipe_crc->opened = false; |
5446 | spin_lock_init(&pipe_crc->lock); | |
07144428 DL |
5447 | init_waitqueue_head(&pipe_crc->wq); |
5448 | } | |
5449 | } | |
5450 | ||
27c202ad | 5451 | int i915_debugfs_init(struct drm_minor *minor) |
2017263e | 5452 | { |
34b9674c | 5453 | int ret, i; |
f3cd474b | 5454 | |
6d794d42 | 5455 | ret = i915_forcewake_create(minor->debugfs_root, minor); |
358733e9 JB |
5456 | if (ret) |
5457 | return ret; | |
6a9c308d | 5458 | |
07144428 DL |
5459 | for (i = 0; i < ARRAY_SIZE(i915_pipe_crc_data); i++) { |
5460 | ret = i915_pipe_crc_create(minor->debugfs_root, minor, i); | |
5461 | if (ret) | |
5462 | return ret; | |
5463 | } | |
5464 | ||
34b9674c DV |
5465 | for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) { |
5466 | ret = i915_debugfs_create(minor->debugfs_root, minor, | |
5467 | i915_debugfs_files[i].name, | |
5468 | i915_debugfs_files[i].fops); | |
5469 | if (ret) | |
5470 | return ret; | |
5471 | } | |
40633219 | 5472 | |
27c202ad BG |
5473 | return drm_debugfs_create_files(i915_debugfs_list, |
5474 | I915_DEBUGFS_ENTRIES, | |
2017263e BG |
5475 | minor->debugfs_root, minor); |
5476 | } | |
5477 | ||
27c202ad | 5478 | void i915_debugfs_cleanup(struct drm_minor *minor) |
2017263e | 5479 | { |
34b9674c DV |
5480 | int i; |
5481 | ||
27c202ad BG |
5482 | drm_debugfs_remove_files(i915_debugfs_list, |
5483 | I915_DEBUGFS_ENTRIES, minor); | |
07144428 | 5484 | |
6d794d42 BW |
5485 | drm_debugfs_remove_files((struct drm_info_list *) &i915_forcewake_fops, |
5486 | 1, minor); | |
07144428 | 5487 | |
e309a997 | 5488 | for (i = 0; i < ARRAY_SIZE(i915_pipe_crc_data); i++) { |
07144428 DL |
5489 | struct drm_info_list *info_list = |
5490 | (struct drm_info_list *)&i915_pipe_crc_data[i]; | |
5491 | ||
5492 | drm_debugfs_remove_files(info_list, 1, minor); | |
5493 | } | |
5494 | ||
34b9674c DV |
5495 | for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) { |
5496 | struct drm_info_list *info_list = | |
5497 | (struct drm_info_list *) i915_debugfs_files[i].fops; | |
5498 | ||
5499 | drm_debugfs_remove_files(info_list, 1, minor); | |
5500 | } | |
2017263e | 5501 | } |
aa7471d2 JN |
5502 | |
5503 | struct dpcd_block { | |
5504 | /* DPCD dump start address. */ | |
5505 | unsigned int offset; | |
5506 | /* DPCD dump end address, inclusive. If unset, .size will be used. */ | |
5507 | unsigned int end; | |
5508 | /* DPCD dump size. Used if .end is unset. If unset, defaults to 1. */ | |
5509 | size_t size; | |
5510 | /* Only valid for eDP. */ | |
5511 | bool edp; | |
5512 | }; | |
5513 | ||
5514 | static const struct dpcd_block i915_dpcd_debug[] = { | |
5515 | { .offset = DP_DPCD_REV, .size = DP_RECEIVER_CAP_SIZE }, | |
5516 | { .offset = DP_PSR_SUPPORT, .end = DP_PSR_CAPS }, | |
5517 | { .offset = DP_DOWNSTREAM_PORT_0, .size = 16 }, | |
5518 | { .offset = DP_LINK_BW_SET, .end = DP_EDP_CONFIGURATION_SET }, | |
5519 | { .offset = DP_SINK_COUNT, .end = DP_ADJUST_REQUEST_LANE2_3 }, | |
5520 | { .offset = DP_SET_POWER }, | |
5521 | { .offset = DP_EDP_DPCD_REV }, | |
5522 | { .offset = DP_EDP_GENERAL_CAP_1, .end = DP_EDP_GENERAL_CAP_3 }, | |
5523 | { .offset = DP_EDP_DISPLAY_CONTROL_REGISTER, .end = DP_EDP_BACKLIGHT_FREQ_CAP_MAX_LSB }, | |
5524 | { .offset = DP_EDP_DBC_MINIMUM_BRIGHTNESS_SET, .end = DP_EDP_DBC_MAXIMUM_BRIGHTNESS_SET }, | |
5525 | }; | |
5526 | ||
5527 | static int i915_dpcd_show(struct seq_file *m, void *data) | |
5528 | { | |
5529 | struct drm_connector *connector = m->private; | |
5530 | struct intel_dp *intel_dp = | |
5531 | enc_to_intel_dp(&intel_attached_encoder(connector)->base); | |
5532 | uint8_t buf[16]; | |
5533 | ssize_t err; | |
5534 | int i; | |
5535 | ||
5c1a8875 MK |
5536 | if (connector->status != connector_status_connected) |
5537 | return -ENODEV; | |
5538 | ||
aa7471d2 JN |
5539 | for (i = 0; i < ARRAY_SIZE(i915_dpcd_debug); i++) { |
5540 | const struct dpcd_block *b = &i915_dpcd_debug[i]; | |
5541 | size_t size = b->end ? b->end - b->offset + 1 : (b->size ?: 1); | |
5542 | ||
5543 | if (b->edp && | |
5544 | connector->connector_type != DRM_MODE_CONNECTOR_eDP) | |
5545 | continue; | |
5546 | ||
5547 | /* low tech for now */ | |
5548 | if (WARN_ON(size > sizeof(buf))) | |
5549 | continue; | |
5550 | ||
5551 | err = drm_dp_dpcd_read(&intel_dp->aux, b->offset, buf, size); | |
5552 | if (err <= 0) { | |
5553 | DRM_ERROR("dpcd read (%zu bytes at %u) failed (%zd)\n", | |
5554 | size, b->offset, err); | |
5555 | continue; | |
5556 | } | |
5557 | ||
5558 | seq_printf(m, "%04x: %*ph\n", b->offset, (int) size, buf); | |
b3f9d7d7 | 5559 | } |
aa7471d2 JN |
5560 | |
5561 | return 0; | |
5562 | } | |
5563 | ||
5564 | static int i915_dpcd_open(struct inode *inode, struct file *file) | |
5565 | { | |
5566 | return single_open(file, i915_dpcd_show, inode->i_private); | |
5567 | } | |
5568 | ||
5569 | static const struct file_operations i915_dpcd_fops = { | |
5570 | .owner = THIS_MODULE, | |
5571 | .open = i915_dpcd_open, | |
5572 | .read = seq_read, | |
5573 | .llseek = seq_lseek, | |
5574 | .release = single_release, | |
5575 | }; | |
5576 | ||
5577 | /** | |
5578 | * i915_debugfs_connector_add - add i915 specific connector debugfs files | |
5579 | * @connector: pointer to a registered drm_connector | |
5580 | * | |
5581 | * Cleanup will be done by drm_connector_unregister() through a call to | |
5582 | * drm_debugfs_connector_remove(). | |
5583 | * | |
5584 | * Returns 0 on success, negative error codes on error. | |
5585 | */ | |
5586 | int i915_debugfs_connector_add(struct drm_connector *connector) | |
5587 | { | |
5588 | struct dentry *root = connector->debugfs_entry; | |
5589 | ||
5590 | /* The connector must have been registered beforehands. */ | |
5591 | if (!root) | |
5592 | return -ENODEV; | |
5593 | ||
5594 | if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort || | |
5595 | connector->connector_type == DRM_MODE_CONNECTOR_eDP) | |
5596 | debugfs_create_file("i915_dpcd", S_IRUGO, root, connector, | |
5597 | &i915_dpcd_fops); | |
5598 | ||
5599 | return 0; | |
5600 | } |