Commit | Line | Data |
---|---|---|
2017263e BG |
1 | /* |
2 | * Copyright © 2008 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | * Keith Packard <keithp@keithp.com> | |
26 | * | |
27 | */ | |
28 | ||
29 | #include <linux/seq_file.h> | |
b2c88f5b | 30 | #include <linux/circ_buf.h> |
926321d5 | 31 | #include <linux/ctype.h> |
f3cd474b | 32 | #include <linux/debugfs.h> |
5a0e3ad6 | 33 | #include <linux/slab.h> |
2d1a8a48 | 34 | #include <linux/export.h> |
6d2b8885 | 35 | #include <linux/list_sort.h> |
ec013e7f | 36 | #include <asm/msr-index.h> |
760285e7 | 37 | #include <drm/drmP.h> |
4e5359cd | 38 | #include "intel_drv.h" |
e5c65260 | 39 | #include "intel_ringbuffer.h" |
760285e7 | 40 | #include <drm/i915_drm.h> |
2017263e BG |
41 | #include "i915_drv.h" |
42 | ||
f13d3f73 | 43 | enum { |
69dc4987 | 44 | ACTIVE_LIST, |
f13d3f73 | 45 | INACTIVE_LIST, |
d21d5975 | 46 | PINNED_LIST, |
f13d3f73 | 47 | }; |
2017263e | 48 | |
497666d8 DL |
49 | /* As the drm_debugfs_init() routines are called before dev->dev_private is |
50 | * allocated we need to hook into the minor for release. */ | |
51 | static int | |
52 | drm_add_fake_info_node(struct drm_minor *minor, | |
53 | struct dentry *ent, | |
54 | const void *key) | |
55 | { | |
56 | struct drm_info_node *node; | |
57 | ||
58 | node = kmalloc(sizeof(*node), GFP_KERNEL); | |
59 | if (node == NULL) { | |
60 | debugfs_remove(ent); | |
61 | return -ENOMEM; | |
62 | } | |
63 | ||
64 | node->minor = minor; | |
65 | node->dent = ent; | |
66 | node->info_ent = (void *) key; | |
67 | ||
68 | mutex_lock(&minor->debugfs_lock); | |
69 | list_add(&node->list, &minor->debugfs_list); | |
70 | mutex_unlock(&minor->debugfs_lock); | |
71 | ||
72 | return 0; | |
73 | } | |
74 | ||
70d39fe4 CW |
75 | static int i915_capabilities(struct seq_file *m, void *data) |
76 | { | |
9f25d007 | 77 | struct drm_info_node *node = m->private; |
70d39fe4 CW |
78 | struct drm_device *dev = node->minor->dev; |
79 | const struct intel_device_info *info = INTEL_INFO(dev); | |
80 | ||
81 | seq_printf(m, "gen: %d\n", info->gen); | |
03d00ac5 | 82 | seq_printf(m, "pch: %d\n", INTEL_PCH_TYPE(dev)); |
79fc46df DL |
83 | #define PRINT_FLAG(x) seq_printf(m, #x ": %s\n", yesno(info->x)) |
84 | #define SEP_SEMICOLON ; | |
85 | DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG, SEP_SEMICOLON); | |
86 | #undef PRINT_FLAG | |
87 | #undef SEP_SEMICOLON | |
70d39fe4 CW |
88 | |
89 | return 0; | |
90 | } | |
2017263e | 91 | |
a7363de7 | 92 | static char get_active_flag(struct drm_i915_gem_object *obj) |
a6172a80 | 93 | { |
be12a86b | 94 | return obj->active ? '*' : ' '; |
a6172a80 CW |
95 | } |
96 | ||
a7363de7 | 97 | static char get_pin_flag(struct drm_i915_gem_object *obj) |
be12a86b TU |
98 | { |
99 | return obj->pin_display ? 'p' : ' '; | |
100 | } | |
101 | ||
a7363de7 | 102 | static char get_tiling_flag(struct drm_i915_gem_object *obj) |
a6172a80 | 103 | { |
0206e353 AJ |
104 | switch (obj->tiling_mode) { |
105 | default: | |
be12a86b TU |
106 | case I915_TILING_NONE: return ' '; |
107 | case I915_TILING_X: return 'X'; | |
108 | case I915_TILING_Y: return 'Y'; | |
0206e353 | 109 | } |
a6172a80 CW |
110 | } |
111 | ||
a7363de7 | 112 | static char get_global_flag(struct drm_i915_gem_object *obj) |
be12a86b TU |
113 | { |
114 | return i915_gem_obj_to_ggtt(obj) ? 'g' : ' '; | |
115 | } | |
116 | ||
a7363de7 | 117 | static char get_pin_mapped_flag(struct drm_i915_gem_object *obj) |
1d693bcc | 118 | { |
be12a86b | 119 | return obj->mapping ? 'M' : ' '; |
1d693bcc BW |
120 | } |
121 | ||
ca1543be TU |
122 | static u64 i915_gem_obj_total_ggtt_size(struct drm_i915_gem_object *obj) |
123 | { | |
124 | u64 size = 0; | |
125 | struct i915_vma *vma; | |
126 | ||
1c7f4bca | 127 | list_for_each_entry(vma, &obj->vma_list, obj_link) { |
596c5923 | 128 | if (vma->is_ggtt && drm_mm_node_allocated(&vma->node)) |
ca1543be TU |
129 | size += vma->node.size; |
130 | } | |
131 | ||
132 | return size; | |
133 | } | |
134 | ||
37811fcc CW |
135 | static void |
136 | describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj) | |
137 | { | |
b4716185 | 138 | struct drm_i915_private *dev_priv = to_i915(obj->base.dev); |
e2f80391 | 139 | struct intel_engine_cs *engine; |
1d693bcc | 140 | struct i915_vma *vma; |
d7f46fc4 | 141 | int pin_count = 0; |
c3232b18 | 142 | enum intel_engine_id id; |
d7f46fc4 | 143 | |
188c1ab7 CW |
144 | lockdep_assert_held(&obj->base.dev->struct_mutex); |
145 | ||
be12a86b | 146 | seq_printf(m, "%pK: %c%c%c%c%c %8zdKiB %02x %02x [ ", |
37811fcc | 147 | &obj->base, |
be12a86b | 148 | get_active_flag(obj), |
37811fcc CW |
149 | get_pin_flag(obj), |
150 | get_tiling_flag(obj), | |
1d693bcc | 151 | get_global_flag(obj), |
be12a86b | 152 | get_pin_mapped_flag(obj), |
a05a5862 | 153 | obj->base.size / 1024, |
37811fcc | 154 | obj->base.read_domains, |
b4716185 | 155 | obj->base.write_domain); |
c3232b18 | 156 | for_each_engine_id(engine, dev_priv, id) |
b4716185 | 157 | seq_printf(m, "%x ", |
c3232b18 | 158 | i915_gem_request_get_seqno(obj->last_read_req[id])); |
b4716185 | 159 | seq_printf(m, "] %x %x%s%s%s", |
97b2a6a1 JH |
160 | i915_gem_request_get_seqno(obj->last_write_req), |
161 | i915_gem_request_get_seqno(obj->last_fenced_req), | |
0a4cd7c8 | 162 | i915_cache_level_str(to_i915(obj->base.dev), obj->cache_level), |
37811fcc CW |
163 | obj->dirty ? " dirty" : "", |
164 | obj->madv == I915_MADV_DONTNEED ? " purgeable" : ""); | |
165 | if (obj->base.name) | |
166 | seq_printf(m, " (name: %d)", obj->base.name); | |
1c7f4bca | 167 | list_for_each_entry(vma, &obj->vma_list, obj_link) { |
d7f46fc4 BW |
168 | if (vma->pin_count > 0) |
169 | pin_count++; | |
ba0635ff DC |
170 | } |
171 | seq_printf(m, " (pinned x %d)", pin_count); | |
cc98b413 CW |
172 | if (obj->pin_display) |
173 | seq_printf(m, " (display)"); | |
37811fcc CW |
174 | if (obj->fence_reg != I915_FENCE_REG_NONE) |
175 | seq_printf(m, " (fence: %d)", obj->fence_reg); | |
1c7f4bca | 176 | list_for_each_entry(vma, &obj->vma_list, obj_link) { |
8d2fdc3f | 177 | seq_printf(m, " (%sgtt offset: %08llx, size: %08llx", |
596c5923 | 178 | vma->is_ggtt ? "g" : "pp", |
8d2fdc3f | 179 | vma->node.start, vma->node.size); |
596c5923 CW |
180 | if (vma->is_ggtt) |
181 | seq_printf(m, ", type: %u", vma->ggtt_view.type); | |
182 | seq_puts(m, ")"); | |
1d693bcc | 183 | } |
c1ad11fc | 184 | if (obj->stolen) |
440fd528 | 185 | seq_printf(m, " (stolen: %08llx)", obj->stolen->start); |
30154650 | 186 | if (obj->pin_display || obj->fault_mappable) { |
6299f992 | 187 | char s[3], *t = s; |
30154650 | 188 | if (obj->pin_display) |
6299f992 CW |
189 | *t++ = 'p'; |
190 | if (obj->fault_mappable) | |
191 | *t++ = 'f'; | |
192 | *t = '\0'; | |
193 | seq_printf(m, " (%s mappable)", s); | |
194 | } | |
b4716185 | 195 | if (obj->last_write_req != NULL) |
41c52415 | 196 | seq_printf(m, " (%s)", |
666796da | 197 | i915_gem_request_get_engine(obj->last_write_req)->name); |
d5a81ef1 DV |
198 | if (obj->frontbuffer_bits) |
199 | seq_printf(m, " (frontbuffer: 0x%03x)", obj->frontbuffer_bits); | |
37811fcc CW |
200 | } |
201 | ||
433e12f7 | 202 | static int i915_gem_object_list_info(struct seq_file *m, void *data) |
2017263e | 203 | { |
9f25d007 | 204 | struct drm_info_node *node = m->private; |
433e12f7 BG |
205 | uintptr_t list = (uintptr_t) node->info_ent->data; |
206 | struct list_head *head; | |
2017263e | 207 | struct drm_device *dev = node->minor->dev; |
72e96d64 JL |
208 | struct drm_i915_private *dev_priv = to_i915(dev); |
209 | struct i915_ggtt *ggtt = &dev_priv->ggtt; | |
ca191b13 | 210 | struct i915_vma *vma; |
c44ef60e | 211 | u64 total_obj_size, total_gtt_size; |
8f2480fb | 212 | int count, ret; |
de227ef0 CW |
213 | |
214 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
215 | if (ret) | |
216 | return ret; | |
2017263e | 217 | |
ca191b13 | 218 | /* FIXME: the user of this interface might want more than just GGTT */ |
433e12f7 BG |
219 | switch (list) { |
220 | case ACTIVE_LIST: | |
267f0c90 | 221 | seq_puts(m, "Active:\n"); |
72e96d64 | 222 | head = &ggtt->base.active_list; |
433e12f7 BG |
223 | break; |
224 | case INACTIVE_LIST: | |
267f0c90 | 225 | seq_puts(m, "Inactive:\n"); |
72e96d64 | 226 | head = &ggtt->base.inactive_list; |
433e12f7 | 227 | break; |
433e12f7 | 228 | default: |
de227ef0 CW |
229 | mutex_unlock(&dev->struct_mutex); |
230 | return -EINVAL; | |
2017263e | 231 | } |
2017263e | 232 | |
8f2480fb | 233 | total_obj_size = total_gtt_size = count = 0; |
1c7f4bca | 234 | list_for_each_entry(vma, head, vm_link) { |
ca191b13 BW |
235 | seq_printf(m, " "); |
236 | describe_obj(m, vma->obj); | |
237 | seq_printf(m, "\n"); | |
238 | total_obj_size += vma->obj->base.size; | |
239 | total_gtt_size += vma->node.size; | |
8f2480fb | 240 | count++; |
2017263e | 241 | } |
de227ef0 | 242 | mutex_unlock(&dev->struct_mutex); |
5e118f41 | 243 | |
c44ef60e | 244 | seq_printf(m, "Total %d objects, %llu bytes, %llu GTT size\n", |
8f2480fb | 245 | count, total_obj_size, total_gtt_size); |
2017263e BG |
246 | return 0; |
247 | } | |
248 | ||
6d2b8885 CW |
249 | static int obj_rank_by_stolen(void *priv, |
250 | struct list_head *A, struct list_head *B) | |
251 | { | |
252 | struct drm_i915_gem_object *a = | |
b25cb2f8 | 253 | container_of(A, struct drm_i915_gem_object, obj_exec_link); |
6d2b8885 | 254 | struct drm_i915_gem_object *b = |
b25cb2f8 | 255 | container_of(B, struct drm_i915_gem_object, obj_exec_link); |
6d2b8885 | 256 | |
2d05fa16 RV |
257 | if (a->stolen->start < b->stolen->start) |
258 | return -1; | |
259 | if (a->stolen->start > b->stolen->start) | |
260 | return 1; | |
261 | return 0; | |
6d2b8885 CW |
262 | } |
263 | ||
264 | static int i915_gem_stolen_list_info(struct seq_file *m, void *data) | |
265 | { | |
9f25d007 | 266 | struct drm_info_node *node = m->private; |
6d2b8885 CW |
267 | struct drm_device *dev = node->minor->dev; |
268 | struct drm_i915_private *dev_priv = dev->dev_private; | |
269 | struct drm_i915_gem_object *obj; | |
c44ef60e | 270 | u64 total_obj_size, total_gtt_size; |
6d2b8885 CW |
271 | LIST_HEAD(stolen); |
272 | int count, ret; | |
273 | ||
274 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
275 | if (ret) | |
276 | return ret; | |
277 | ||
278 | total_obj_size = total_gtt_size = count = 0; | |
279 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) { | |
280 | if (obj->stolen == NULL) | |
281 | continue; | |
282 | ||
b25cb2f8 | 283 | list_add(&obj->obj_exec_link, &stolen); |
6d2b8885 CW |
284 | |
285 | total_obj_size += obj->base.size; | |
ca1543be | 286 | total_gtt_size += i915_gem_obj_total_ggtt_size(obj); |
6d2b8885 CW |
287 | count++; |
288 | } | |
289 | list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) { | |
290 | if (obj->stolen == NULL) | |
291 | continue; | |
292 | ||
b25cb2f8 | 293 | list_add(&obj->obj_exec_link, &stolen); |
6d2b8885 CW |
294 | |
295 | total_obj_size += obj->base.size; | |
296 | count++; | |
297 | } | |
298 | list_sort(NULL, &stolen, obj_rank_by_stolen); | |
299 | seq_puts(m, "Stolen:\n"); | |
300 | while (!list_empty(&stolen)) { | |
b25cb2f8 | 301 | obj = list_first_entry(&stolen, typeof(*obj), obj_exec_link); |
6d2b8885 CW |
302 | seq_puts(m, " "); |
303 | describe_obj(m, obj); | |
304 | seq_putc(m, '\n'); | |
b25cb2f8 | 305 | list_del_init(&obj->obj_exec_link); |
6d2b8885 CW |
306 | } |
307 | mutex_unlock(&dev->struct_mutex); | |
308 | ||
c44ef60e | 309 | seq_printf(m, "Total %d objects, %llu bytes, %llu GTT size\n", |
6d2b8885 CW |
310 | count, total_obj_size, total_gtt_size); |
311 | return 0; | |
312 | } | |
313 | ||
6299f992 CW |
314 | #define count_objects(list, member) do { \ |
315 | list_for_each_entry(obj, list, member) { \ | |
ca1543be | 316 | size += i915_gem_obj_total_ggtt_size(obj); \ |
6299f992 CW |
317 | ++count; \ |
318 | if (obj->map_and_fenceable) { \ | |
f343c5f6 | 319 | mappable_size += i915_gem_obj_ggtt_size(obj); \ |
6299f992 CW |
320 | ++mappable_count; \ |
321 | } \ | |
322 | } \ | |
0206e353 | 323 | } while (0) |
6299f992 | 324 | |
2db8e9d6 | 325 | struct file_stats { |
6313c204 | 326 | struct drm_i915_file_private *file_priv; |
c44ef60e MK |
327 | unsigned long count; |
328 | u64 total, unbound; | |
329 | u64 global, shared; | |
330 | u64 active, inactive; | |
2db8e9d6 CW |
331 | }; |
332 | ||
333 | static int per_file_stats(int id, void *ptr, void *data) | |
334 | { | |
335 | struct drm_i915_gem_object *obj = ptr; | |
336 | struct file_stats *stats = data; | |
6313c204 | 337 | struct i915_vma *vma; |
2db8e9d6 CW |
338 | |
339 | stats->count++; | |
340 | stats->total += obj->base.size; | |
341 | ||
c67a17e9 CW |
342 | if (obj->base.name || obj->base.dma_buf) |
343 | stats->shared += obj->base.size; | |
344 | ||
6313c204 | 345 | if (USES_FULL_PPGTT(obj->base.dev)) { |
1c7f4bca | 346 | list_for_each_entry(vma, &obj->vma_list, obj_link) { |
6313c204 CW |
347 | struct i915_hw_ppgtt *ppgtt; |
348 | ||
349 | if (!drm_mm_node_allocated(&vma->node)) | |
350 | continue; | |
351 | ||
596c5923 | 352 | if (vma->is_ggtt) { |
6313c204 CW |
353 | stats->global += obj->base.size; |
354 | continue; | |
355 | } | |
356 | ||
357 | ppgtt = container_of(vma->vm, struct i915_hw_ppgtt, base); | |
4d884705 | 358 | if (ppgtt->file_priv != stats->file_priv) |
6313c204 CW |
359 | continue; |
360 | ||
41c52415 | 361 | if (obj->active) /* XXX per-vma statistic */ |
6313c204 CW |
362 | stats->active += obj->base.size; |
363 | else | |
364 | stats->inactive += obj->base.size; | |
365 | ||
366 | return 0; | |
367 | } | |
2db8e9d6 | 368 | } else { |
6313c204 CW |
369 | if (i915_gem_obj_ggtt_bound(obj)) { |
370 | stats->global += obj->base.size; | |
41c52415 | 371 | if (obj->active) |
6313c204 CW |
372 | stats->active += obj->base.size; |
373 | else | |
374 | stats->inactive += obj->base.size; | |
375 | return 0; | |
376 | } | |
2db8e9d6 CW |
377 | } |
378 | ||
6313c204 CW |
379 | if (!list_empty(&obj->global_list)) |
380 | stats->unbound += obj->base.size; | |
381 | ||
2db8e9d6 CW |
382 | return 0; |
383 | } | |
384 | ||
b0da1b79 CW |
385 | #define print_file_stats(m, name, stats) do { \ |
386 | if (stats.count) \ | |
c44ef60e | 387 | seq_printf(m, "%s: %lu objects, %llu bytes (%llu active, %llu inactive, %llu global, %llu shared, %llu unbound)\n", \ |
b0da1b79 CW |
388 | name, \ |
389 | stats.count, \ | |
390 | stats.total, \ | |
391 | stats.active, \ | |
392 | stats.inactive, \ | |
393 | stats.global, \ | |
394 | stats.shared, \ | |
395 | stats.unbound); \ | |
396 | } while (0) | |
493018dc BV |
397 | |
398 | static void print_batch_pool_stats(struct seq_file *m, | |
399 | struct drm_i915_private *dev_priv) | |
400 | { | |
401 | struct drm_i915_gem_object *obj; | |
402 | struct file_stats stats; | |
e2f80391 | 403 | struct intel_engine_cs *engine; |
b4ac5afc | 404 | int j; |
493018dc BV |
405 | |
406 | memset(&stats, 0, sizeof(stats)); | |
407 | ||
b4ac5afc | 408 | for_each_engine(engine, dev_priv) { |
e2f80391 | 409 | for (j = 0; j < ARRAY_SIZE(engine->batch_pool.cache_list); j++) { |
8d9d5744 | 410 | list_for_each_entry(obj, |
e2f80391 | 411 | &engine->batch_pool.cache_list[j], |
8d9d5744 CW |
412 | batch_pool_link) |
413 | per_file_stats(0, obj, &stats); | |
414 | } | |
06fbca71 | 415 | } |
493018dc | 416 | |
b0da1b79 | 417 | print_file_stats(m, "[k]batch pool", stats); |
493018dc BV |
418 | } |
419 | ||
15da9565 CW |
420 | static int per_file_ctx_stats(int id, void *ptr, void *data) |
421 | { | |
422 | struct i915_gem_context *ctx = ptr; | |
423 | int n; | |
424 | ||
425 | for (n = 0; n < ARRAY_SIZE(ctx->engine); n++) { | |
426 | if (ctx->engine[n].state) | |
427 | per_file_stats(0, ctx->engine[n].state, data); | |
428 | if (ctx->engine[n].ringbuf) | |
429 | per_file_stats(0, ctx->engine[n].ringbuf->obj, data); | |
430 | } | |
431 | ||
432 | return 0; | |
433 | } | |
434 | ||
435 | static void print_context_stats(struct seq_file *m, | |
436 | struct drm_i915_private *dev_priv) | |
437 | { | |
438 | struct file_stats stats; | |
439 | struct drm_file *file; | |
440 | ||
441 | memset(&stats, 0, sizeof(stats)); | |
442 | ||
443 | mutex_lock(&dev_priv->dev->struct_mutex); | |
444 | if (dev_priv->kernel_context) | |
445 | per_file_ctx_stats(0, dev_priv->kernel_context, &stats); | |
446 | ||
447 | list_for_each_entry(file, &dev_priv->dev->filelist, lhead) { | |
448 | struct drm_i915_file_private *fpriv = file->driver_priv; | |
449 | idr_for_each(&fpriv->context_idr, per_file_ctx_stats, &stats); | |
450 | } | |
451 | mutex_unlock(&dev_priv->dev->struct_mutex); | |
452 | ||
453 | print_file_stats(m, "[k]contexts", stats); | |
454 | } | |
455 | ||
ca191b13 BW |
456 | #define count_vmas(list, member) do { \ |
457 | list_for_each_entry(vma, list, member) { \ | |
ca1543be | 458 | size += i915_gem_obj_total_ggtt_size(vma->obj); \ |
ca191b13 BW |
459 | ++count; \ |
460 | if (vma->obj->map_and_fenceable) { \ | |
461 | mappable_size += i915_gem_obj_ggtt_size(vma->obj); \ | |
462 | ++mappable_count; \ | |
463 | } \ | |
464 | } \ | |
465 | } while (0) | |
466 | ||
467 | static int i915_gem_object_info(struct seq_file *m, void* data) | |
73aa808f | 468 | { |
9f25d007 | 469 | struct drm_info_node *node = m->private; |
73aa808f | 470 | struct drm_device *dev = node->minor->dev; |
72e96d64 JL |
471 | struct drm_i915_private *dev_priv = to_i915(dev); |
472 | struct i915_ggtt *ggtt = &dev_priv->ggtt; | |
b7abb714 | 473 | u32 count, mappable_count, purgeable_count; |
c44ef60e | 474 | u64 size, mappable_size, purgeable_size; |
be19b10d TU |
475 | unsigned long pin_mapped_count = 0, pin_mapped_purgeable_count = 0; |
476 | u64 pin_mapped_size = 0, pin_mapped_purgeable_size = 0; | |
6299f992 | 477 | struct drm_i915_gem_object *obj; |
2db8e9d6 | 478 | struct drm_file *file; |
ca191b13 | 479 | struct i915_vma *vma; |
73aa808f CW |
480 | int ret; |
481 | ||
482 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
483 | if (ret) | |
484 | return ret; | |
485 | ||
6299f992 CW |
486 | seq_printf(m, "%u objects, %zu bytes\n", |
487 | dev_priv->mm.object_count, | |
488 | dev_priv->mm.object_memory); | |
489 | ||
490 | size = count = mappable_size = mappable_count = 0; | |
35c20a60 | 491 | count_objects(&dev_priv->mm.bound_list, global_list); |
c44ef60e | 492 | seq_printf(m, "%u [%u] objects, %llu [%llu] bytes in gtt\n", |
6299f992 CW |
493 | count, mappable_count, size, mappable_size); |
494 | ||
495 | size = count = mappable_size = mappable_count = 0; | |
72e96d64 | 496 | count_vmas(&ggtt->base.active_list, vm_link); |
c44ef60e | 497 | seq_printf(m, " %u [%u] active objects, %llu [%llu] bytes\n", |
6299f992 CW |
498 | count, mappable_count, size, mappable_size); |
499 | ||
6299f992 | 500 | size = count = mappable_size = mappable_count = 0; |
72e96d64 | 501 | count_vmas(&ggtt->base.inactive_list, vm_link); |
c44ef60e | 502 | seq_printf(m, " %u [%u] inactive objects, %llu [%llu] bytes\n", |
6299f992 CW |
503 | count, mappable_count, size, mappable_size); |
504 | ||
b7abb714 | 505 | size = count = purgeable_size = purgeable_count = 0; |
35c20a60 | 506 | list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) { |
6c085a72 | 507 | size += obj->base.size, ++count; |
b7abb714 CW |
508 | if (obj->madv == I915_MADV_DONTNEED) |
509 | purgeable_size += obj->base.size, ++purgeable_count; | |
be19b10d TU |
510 | if (obj->mapping) { |
511 | pin_mapped_count++; | |
512 | pin_mapped_size += obj->base.size; | |
513 | if (obj->pages_pin_count == 0) { | |
514 | pin_mapped_purgeable_count++; | |
515 | pin_mapped_purgeable_size += obj->base.size; | |
516 | } | |
517 | } | |
b7abb714 | 518 | } |
c44ef60e | 519 | seq_printf(m, "%u unbound objects, %llu bytes\n", count, size); |
6c085a72 | 520 | |
6299f992 | 521 | size = count = mappable_size = mappable_count = 0; |
35c20a60 | 522 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) { |
6299f992 | 523 | if (obj->fault_mappable) { |
f343c5f6 | 524 | size += i915_gem_obj_ggtt_size(obj); |
6299f992 CW |
525 | ++count; |
526 | } | |
30154650 | 527 | if (obj->pin_display) { |
f343c5f6 | 528 | mappable_size += i915_gem_obj_ggtt_size(obj); |
6299f992 CW |
529 | ++mappable_count; |
530 | } | |
b7abb714 CW |
531 | if (obj->madv == I915_MADV_DONTNEED) { |
532 | purgeable_size += obj->base.size; | |
533 | ++purgeable_count; | |
534 | } | |
be19b10d TU |
535 | if (obj->mapping) { |
536 | pin_mapped_count++; | |
537 | pin_mapped_size += obj->base.size; | |
538 | if (obj->pages_pin_count == 0) { | |
539 | pin_mapped_purgeable_count++; | |
540 | pin_mapped_purgeable_size += obj->base.size; | |
541 | } | |
542 | } | |
6299f992 | 543 | } |
c44ef60e | 544 | seq_printf(m, "%u purgeable objects, %llu bytes\n", |
b7abb714 | 545 | purgeable_count, purgeable_size); |
c44ef60e | 546 | seq_printf(m, "%u pinned mappable objects, %llu bytes\n", |
6299f992 | 547 | mappable_count, mappable_size); |
c44ef60e | 548 | seq_printf(m, "%u fault mappable objects, %llu bytes\n", |
6299f992 | 549 | count, size); |
be19b10d TU |
550 | seq_printf(m, |
551 | "%lu [%lu] pin mapped objects, %llu [%llu] bytes [purgeable]\n", | |
552 | pin_mapped_count, pin_mapped_purgeable_count, | |
553 | pin_mapped_size, pin_mapped_purgeable_size); | |
6299f992 | 554 | |
c44ef60e | 555 | seq_printf(m, "%llu [%llu] gtt total\n", |
72e96d64 | 556 | ggtt->base.total, ggtt->mappable_end - ggtt->base.start); |
73aa808f | 557 | |
493018dc BV |
558 | seq_putc(m, '\n'); |
559 | print_batch_pool_stats(m, dev_priv); | |
1d2ac403 DV |
560 | mutex_unlock(&dev->struct_mutex); |
561 | ||
562 | mutex_lock(&dev->filelist_mutex); | |
15da9565 | 563 | print_context_stats(m, dev_priv); |
2db8e9d6 CW |
564 | list_for_each_entry_reverse(file, &dev->filelist, lhead) { |
565 | struct file_stats stats; | |
3ec2f427 | 566 | struct task_struct *task; |
2db8e9d6 CW |
567 | |
568 | memset(&stats, 0, sizeof(stats)); | |
6313c204 | 569 | stats.file_priv = file->driver_priv; |
5b5ffff0 | 570 | spin_lock(&file->table_lock); |
2db8e9d6 | 571 | idr_for_each(&file->object_idr, per_file_stats, &stats); |
5b5ffff0 | 572 | spin_unlock(&file->table_lock); |
3ec2f427 TH |
573 | /* |
574 | * Although we have a valid reference on file->pid, that does | |
575 | * not guarantee that the task_struct who called get_pid() is | |
576 | * still alive (e.g. get_pid(current) => fork() => exit()). | |
577 | * Therefore, we need to protect this ->comm access using RCU. | |
578 | */ | |
579 | rcu_read_lock(); | |
580 | task = pid_task(file->pid, PIDTYPE_PID); | |
493018dc | 581 | print_file_stats(m, task ? task->comm : "<unknown>", stats); |
3ec2f427 | 582 | rcu_read_unlock(); |
2db8e9d6 | 583 | } |
1d2ac403 | 584 | mutex_unlock(&dev->filelist_mutex); |
73aa808f CW |
585 | |
586 | return 0; | |
587 | } | |
588 | ||
aee56cff | 589 | static int i915_gem_gtt_info(struct seq_file *m, void *data) |
08c18323 | 590 | { |
9f25d007 | 591 | struct drm_info_node *node = m->private; |
08c18323 | 592 | struct drm_device *dev = node->minor->dev; |
1b50247a | 593 | uintptr_t list = (uintptr_t) node->info_ent->data; |
08c18323 CW |
594 | struct drm_i915_private *dev_priv = dev->dev_private; |
595 | struct drm_i915_gem_object *obj; | |
c44ef60e | 596 | u64 total_obj_size, total_gtt_size; |
08c18323 CW |
597 | int count, ret; |
598 | ||
599 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
600 | if (ret) | |
601 | return ret; | |
602 | ||
603 | total_obj_size = total_gtt_size = count = 0; | |
35c20a60 | 604 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) { |
d7f46fc4 | 605 | if (list == PINNED_LIST && !i915_gem_obj_is_pinned(obj)) |
1b50247a CW |
606 | continue; |
607 | ||
267f0c90 | 608 | seq_puts(m, " "); |
08c18323 | 609 | describe_obj(m, obj); |
267f0c90 | 610 | seq_putc(m, '\n'); |
08c18323 | 611 | total_obj_size += obj->base.size; |
ca1543be | 612 | total_gtt_size += i915_gem_obj_total_ggtt_size(obj); |
08c18323 CW |
613 | count++; |
614 | } | |
615 | ||
616 | mutex_unlock(&dev->struct_mutex); | |
617 | ||
c44ef60e | 618 | seq_printf(m, "Total %d objects, %llu bytes, %llu GTT size\n", |
08c18323 CW |
619 | count, total_obj_size, total_gtt_size); |
620 | ||
621 | return 0; | |
622 | } | |
623 | ||
4e5359cd SF |
624 | static int i915_gem_pageflip_info(struct seq_file *m, void *data) |
625 | { | |
9f25d007 | 626 | struct drm_info_node *node = m->private; |
4e5359cd | 627 | struct drm_device *dev = node->minor->dev; |
d6bbafa1 | 628 | struct drm_i915_private *dev_priv = dev->dev_private; |
4e5359cd | 629 | struct intel_crtc *crtc; |
8a270ebf DV |
630 | int ret; |
631 | ||
632 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
633 | if (ret) | |
634 | return ret; | |
4e5359cd | 635 | |
d3fcc808 | 636 | for_each_intel_crtc(dev, crtc) { |
9db4a9c7 JB |
637 | const char pipe = pipe_name(crtc->pipe); |
638 | const char plane = plane_name(crtc->plane); | |
51cbaf01 | 639 | struct intel_flip_work *work; |
4e5359cd | 640 | |
5e2d7afc | 641 | spin_lock_irq(&dev->event_lock); |
5a21b665 DV |
642 | work = crtc->flip_work; |
643 | if (work == NULL) { | |
9db4a9c7 | 644 | seq_printf(m, "No flip due on pipe %c (plane %c)\n", |
4e5359cd SF |
645 | pipe, plane); |
646 | } else { | |
5a21b665 DV |
647 | u32 pending; |
648 | u32 addr; | |
649 | ||
650 | pending = atomic_read(&work->pending); | |
651 | if (pending) { | |
652 | seq_printf(m, "Flip ioctl preparing on pipe %c (plane %c)\n", | |
653 | pipe, plane); | |
654 | } else { | |
655 | seq_printf(m, "Flip pending (waiting for vsync) on pipe %c (plane %c)\n", | |
656 | pipe, plane); | |
657 | } | |
658 | if (work->flip_queued_req) { | |
659 | struct intel_engine_cs *engine = i915_gem_request_get_engine(work->flip_queued_req); | |
660 | ||
661 | seq_printf(m, "Flip queued on %s at seqno %x, next seqno %x [current breadcrumb %x], completed? %d\n", | |
662 | engine->name, | |
663 | i915_gem_request_get_seqno(work->flip_queued_req), | |
664 | dev_priv->next_seqno, | |
665 | engine->get_seqno(engine), | |
666 | i915_gem_request_completed(work->flip_queued_req, true)); | |
667 | } else | |
668 | seq_printf(m, "Flip not associated with any ring\n"); | |
669 | seq_printf(m, "Flip queued on frame %d, (was ready on frame %d), now %d\n", | |
670 | work->flip_queued_vblank, | |
671 | work->flip_ready_vblank, | |
672 | intel_crtc_get_vblank_counter(crtc)); | |
673 | seq_printf(m, "%d prepares\n", atomic_read(&work->pending)); | |
674 | ||
675 | if (INTEL_INFO(dev)->gen >= 4) | |
676 | addr = I915_HI_DISPBASE(I915_READ(DSPSURF(crtc->plane))); | |
677 | else | |
678 | addr = I915_READ(DSPADDR(crtc->plane)); | |
679 | seq_printf(m, "Current scanout address 0x%08x\n", addr); | |
680 | ||
681 | if (work->pending_flip_obj) { | |
682 | seq_printf(m, "New framebuffer address 0x%08lx\n", (long)work->gtt_offset); | |
683 | seq_printf(m, "MMIO update completed? %d\n", addr == work->gtt_offset); | |
4e5359cd SF |
684 | } |
685 | } | |
5e2d7afc | 686 | spin_unlock_irq(&dev->event_lock); |
4e5359cd SF |
687 | } |
688 | ||
8a270ebf DV |
689 | mutex_unlock(&dev->struct_mutex); |
690 | ||
4e5359cd SF |
691 | return 0; |
692 | } | |
693 | ||
493018dc BV |
694 | static int i915_gem_batch_pool_info(struct seq_file *m, void *data) |
695 | { | |
696 | struct drm_info_node *node = m->private; | |
697 | struct drm_device *dev = node->minor->dev; | |
698 | struct drm_i915_private *dev_priv = dev->dev_private; | |
699 | struct drm_i915_gem_object *obj; | |
e2f80391 | 700 | struct intel_engine_cs *engine; |
8d9d5744 | 701 | int total = 0; |
b4ac5afc | 702 | int ret, j; |
493018dc BV |
703 | |
704 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
705 | if (ret) | |
706 | return ret; | |
707 | ||
b4ac5afc | 708 | for_each_engine(engine, dev_priv) { |
e2f80391 | 709 | for (j = 0; j < ARRAY_SIZE(engine->batch_pool.cache_list); j++) { |
8d9d5744 CW |
710 | int count; |
711 | ||
712 | count = 0; | |
713 | list_for_each_entry(obj, | |
e2f80391 | 714 | &engine->batch_pool.cache_list[j], |
8d9d5744 CW |
715 | batch_pool_link) |
716 | count++; | |
717 | seq_printf(m, "%s cache[%d]: %d objects\n", | |
e2f80391 | 718 | engine->name, j, count); |
8d9d5744 CW |
719 | |
720 | list_for_each_entry(obj, | |
e2f80391 | 721 | &engine->batch_pool.cache_list[j], |
8d9d5744 CW |
722 | batch_pool_link) { |
723 | seq_puts(m, " "); | |
724 | describe_obj(m, obj); | |
725 | seq_putc(m, '\n'); | |
726 | } | |
727 | ||
728 | total += count; | |
06fbca71 | 729 | } |
493018dc BV |
730 | } |
731 | ||
8d9d5744 | 732 | seq_printf(m, "total: %d\n", total); |
493018dc BV |
733 | |
734 | mutex_unlock(&dev->struct_mutex); | |
735 | ||
736 | return 0; | |
737 | } | |
738 | ||
2017263e BG |
739 | static int i915_gem_request_info(struct seq_file *m, void *data) |
740 | { | |
9f25d007 | 741 | struct drm_info_node *node = m->private; |
2017263e | 742 | struct drm_device *dev = node->minor->dev; |
e277a1f8 | 743 | struct drm_i915_private *dev_priv = dev->dev_private; |
e2f80391 | 744 | struct intel_engine_cs *engine; |
eed29a5b | 745 | struct drm_i915_gem_request *req; |
b4ac5afc | 746 | int ret, any; |
de227ef0 CW |
747 | |
748 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
749 | if (ret) | |
750 | return ret; | |
2017263e | 751 | |
2d1070b2 | 752 | any = 0; |
b4ac5afc | 753 | for_each_engine(engine, dev_priv) { |
2d1070b2 CW |
754 | int count; |
755 | ||
756 | count = 0; | |
e2f80391 | 757 | list_for_each_entry(req, &engine->request_list, list) |
2d1070b2 CW |
758 | count++; |
759 | if (count == 0) | |
a2c7f6fd CW |
760 | continue; |
761 | ||
e2f80391 TU |
762 | seq_printf(m, "%s requests: %d\n", engine->name, count); |
763 | list_for_each_entry(req, &engine->request_list, list) { | |
2d1070b2 CW |
764 | struct task_struct *task; |
765 | ||
766 | rcu_read_lock(); | |
767 | task = NULL; | |
eed29a5b DV |
768 | if (req->pid) |
769 | task = pid_task(req->pid, PIDTYPE_PID); | |
2d1070b2 | 770 | seq_printf(m, " %x @ %d: %s [%d]\n", |
eed29a5b DV |
771 | req->seqno, |
772 | (int) (jiffies - req->emitted_jiffies), | |
2d1070b2 CW |
773 | task ? task->comm : "<unknown>", |
774 | task ? task->pid : -1); | |
775 | rcu_read_unlock(); | |
c2c347a9 | 776 | } |
2d1070b2 CW |
777 | |
778 | any++; | |
2017263e | 779 | } |
de227ef0 CW |
780 | mutex_unlock(&dev->struct_mutex); |
781 | ||
2d1070b2 | 782 | if (any == 0) |
267f0c90 | 783 | seq_puts(m, "No requests\n"); |
c2c347a9 | 784 | |
2017263e BG |
785 | return 0; |
786 | } | |
787 | ||
b2223497 | 788 | static void i915_ring_seqno_info(struct seq_file *m, |
0bc40be8 | 789 | struct intel_engine_cs *engine) |
b2223497 | 790 | { |
12471ba8 CW |
791 | seq_printf(m, "Current sequence (%s): %x\n", |
792 | engine->name, engine->get_seqno(engine)); | |
793 | seq_printf(m, "Current user interrupts (%s): %x\n", | |
794 | engine->name, READ_ONCE(engine->user_interrupts)); | |
b2223497 CW |
795 | } |
796 | ||
2017263e BG |
797 | static int i915_gem_seqno_info(struct seq_file *m, void *data) |
798 | { | |
9f25d007 | 799 | struct drm_info_node *node = m->private; |
2017263e | 800 | struct drm_device *dev = node->minor->dev; |
e277a1f8 | 801 | struct drm_i915_private *dev_priv = dev->dev_private; |
e2f80391 | 802 | struct intel_engine_cs *engine; |
b4ac5afc | 803 | int ret; |
de227ef0 CW |
804 | |
805 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
806 | if (ret) | |
807 | return ret; | |
c8c8fb33 | 808 | intel_runtime_pm_get(dev_priv); |
2017263e | 809 | |
b4ac5afc | 810 | for_each_engine(engine, dev_priv) |
e2f80391 | 811 | i915_ring_seqno_info(m, engine); |
de227ef0 | 812 | |
c8c8fb33 | 813 | intel_runtime_pm_put(dev_priv); |
de227ef0 CW |
814 | mutex_unlock(&dev->struct_mutex); |
815 | ||
2017263e BG |
816 | return 0; |
817 | } | |
818 | ||
819 | ||
820 | static int i915_interrupt_info(struct seq_file *m, void *data) | |
821 | { | |
9f25d007 | 822 | struct drm_info_node *node = m->private; |
2017263e | 823 | struct drm_device *dev = node->minor->dev; |
e277a1f8 | 824 | struct drm_i915_private *dev_priv = dev->dev_private; |
e2f80391 | 825 | struct intel_engine_cs *engine; |
9db4a9c7 | 826 | int ret, i, pipe; |
de227ef0 CW |
827 | |
828 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
829 | if (ret) | |
830 | return ret; | |
c8c8fb33 | 831 | intel_runtime_pm_get(dev_priv); |
2017263e | 832 | |
74e1ca8c | 833 | if (IS_CHERRYVIEW(dev)) { |
74e1ca8c VS |
834 | seq_printf(m, "Master Interrupt Control:\t%08x\n", |
835 | I915_READ(GEN8_MASTER_IRQ)); | |
836 | ||
837 | seq_printf(m, "Display IER:\t%08x\n", | |
838 | I915_READ(VLV_IER)); | |
839 | seq_printf(m, "Display IIR:\t%08x\n", | |
840 | I915_READ(VLV_IIR)); | |
841 | seq_printf(m, "Display IIR_RW:\t%08x\n", | |
842 | I915_READ(VLV_IIR_RW)); | |
843 | seq_printf(m, "Display IMR:\t%08x\n", | |
844 | I915_READ(VLV_IMR)); | |
055e393f | 845 | for_each_pipe(dev_priv, pipe) |
74e1ca8c VS |
846 | seq_printf(m, "Pipe %c stat:\t%08x\n", |
847 | pipe_name(pipe), | |
848 | I915_READ(PIPESTAT(pipe))); | |
849 | ||
850 | seq_printf(m, "Port hotplug:\t%08x\n", | |
851 | I915_READ(PORT_HOTPLUG_EN)); | |
852 | seq_printf(m, "DPFLIPSTAT:\t%08x\n", | |
853 | I915_READ(VLV_DPFLIPSTAT)); | |
854 | seq_printf(m, "DPINVGTT:\t%08x\n", | |
855 | I915_READ(DPINVGTT)); | |
856 | ||
857 | for (i = 0; i < 4; i++) { | |
858 | seq_printf(m, "GT Interrupt IMR %d:\t%08x\n", | |
859 | i, I915_READ(GEN8_GT_IMR(i))); | |
860 | seq_printf(m, "GT Interrupt IIR %d:\t%08x\n", | |
861 | i, I915_READ(GEN8_GT_IIR(i))); | |
862 | seq_printf(m, "GT Interrupt IER %d:\t%08x\n", | |
863 | i, I915_READ(GEN8_GT_IER(i))); | |
864 | } | |
865 | ||
866 | seq_printf(m, "PCU interrupt mask:\t%08x\n", | |
867 | I915_READ(GEN8_PCU_IMR)); | |
868 | seq_printf(m, "PCU interrupt identity:\t%08x\n", | |
869 | I915_READ(GEN8_PCU_IIR)); | |
870 | seq_printf(m, "PCU interrupt enable:\t%08x\n", | |
871 | I915_READ(GEN8_PCU_IER)); | |
872 | } else if (INTEL_INFO(dev)->gen >= 8) { | |
a123f157 BW |
873 | seq_printf(m, "Master Interrupt Control:\t%08x\n", |
874 | I915_READ(GEN8_MASTER_IRQ)); | |
875 | ||
876 | for (i = 0; i < 4; i++) { | |
877 | seq_printf(m, "GT Interrupt IMR %d:\t%08x\n", | |
878 | i, I915_READ(GEN8_GT_IMR(i))); | |
879 | seq_printf(m, "GT Interrupt IIR %d:\t%08x\n", | |
880 | i, I915_READ(GEN8_GT_IIR(i))); | |
881 | seq_printf(m, "GT Interrupt IER %d:\t%08x\n", | |
882 | i, I915_READ(GEN8_GT_IER(i))); | |
883 | } | |
884 | ||
055e393f | 885 | for_each_pipe(dev_priv, pipe) { |
e129649b ID |
886 | enum intel_display_power_domain power_domain; |
887 | ||
888 | power_domain = POWER_DOMAIN_PIPE(pipe); | |
889 | if (!intel_display_power_get_if_enabled(dev_priv, | |
890 | power_domain)) { | |
22c59960 PZ |
891 | seq_printf(m, "Pipe %c power disabled\n", |
892 | pipe_name(pipe)); | |
893 | continue; | |
894 | } | |
a123f157 | 895 | seq_printf(m, "Pipe %c IMR:\t%08x\n", |
07d27e20 DL |
896 | pipe_name(pipe), |
897 | I915_READ(GEN8_DE_PIPE_IMR(pipe))); | |
a123f157 | 898 | seq_printf(m, "Pipe %c IIR:\t%08x\n", |
07d27e20 DL |
899 | pipe_name(pipe), |
900 | I915_READ(GEN8_DE_PIPE_IIR(pipe))); | |
a123f157 | 901 | seq_printf(m, "Pipe %c IER:\t%08x\n", |
07d27e20 DL |
902 | pipe_name(pipe), |
903 | I915_READ(GEN8_DE_PIPE_IER(pipe))); | |
e129649b ID |
904 | |
905 | intel_display_power_put(dev_priv, power_domain); | |
a123f157 BW |
906 | } |
907 | ||
908 | seq_printf(m, "Display Engine port interrupt mask:\t%08x\n", | |
909 | I915_READ(GEN8_DE_PORT_IMR)); | |
910 | seq_printf(m, "Display Engine port interrupt identity:\t%08x\n", | |
911 | I915_READ(GEN8_DE_PORT_IIR)); | |
912 | seq_printf(m, "Display Engine port interrupt enable:\t%08x\n", | |
913 | I915_READ(GEN8_DE_PORT_IER)); | |
914 | ||
915 | seq_printf(m, "Display Engine misc interrupt mask:\t%08x\n", | |
916 | I915_READ(GEN8_DE_MISC_IMR)); | |
917 | seq_printf(m, "Display Engine misc interrupt identity:\t%08x\n", | |
918 | I915_READ(GEN8_DE_MISC_IIR)); | |
919 | seq_printf(m, "Display Engine misc interrupt enable:\t%08x\n", | |
920 | I915_READ(GEN8_DE_MISC_IER)); | |
921 | ||
922 | seq_printf(m, "PCU interrupt mask:\t%08x\n", | |
923 | I915_READ(GEN8_PCU_IMR)); | |
924 | seq_printf(m, "PCU interrupt identity:\t%08x\n", | |
925 | I915_READ(GEN8_PCU_IIR)); | |
926 | seq_printf(m, "PCU interrupt enable:\t%08x\n", | |
927 | I915_READ(GEN8_PCU_IER)); | |
928 | } else if (IS_VALLEYVIEW(dev)) { | |
7e231dbe JB |
929 | seq_printf(m, "Display IER:\t%08x\n", |
930 | I915_READ(VLV_IER)); | |
931 | seq_printf(m, "Display IIR:\t%08x\n", | |
932 | I915_READ(VLV_IIR)); | |
933 | seq_printf(m, "Display IIR_RW:\t%08x\n", | |
934 | I915_READ(VLV_IIR_RW)); | |
935 | seq_printf(m, "Display IMR:\t%08x\n", | |
936 | I915_READ(VLV_IMR)); | |
055e393f | 937 | for_each_pipe(dev_priv, pipe) |
7e231dbe JB |
938 | seq_printf(m, "Pipe %c stat:\t%08x\n", |
939 | pipe_name(pipe), | |
940 | I915_READ(PIPESTAT(pipe))); | |
941 | ||
942 | seq_printf(m, "Master IER:\t%08x\n", | |
943 | I915_READ(VLV_MASTER_IER)); | |
944 | ||
945 | seq_printf(m, "Render IER:\t%08x\n", | |
946 | I915_READ(GTIER)); | |
947 | seq_printf(m, "Render IIR:\t%08x\n", | |
948 | I915_READ(GTIIR)); | |
949 | seq_printf(m, "Render IMR:\t%08x\n", | |
950 | I915_READ(GTIMR)); | |
951 | ||
952 | seq_printf(m, "PM IER:\t\t%08x\n", | |
953 | I915_READ(GEN6_PMIER)); | |
954 | seq_printf(m, "PM IIR:\t\t%08x\n", | |
955 | I915_READ(GEN6_PMIIR)); | |
956 | seq_printf(m, "PM IMR:\t\t%08x\n", | |
957 | I915_READ(GEN6_PMIMR)); | |
958 | ||
959 | seq_printf(m, "Port hotplug:\t%08x\n", | |
960 | I915_READ(PORT_HOTPLUG_EN)); | |
961 | seq_printf(m, "DPFLIPSTAT:\t%08x\n", | |
962 | I915_READ(VLV_DPFLIPSTAT)); | |
963 | seq_printf(m, "DPINVGTT:\t%08x\n", | |
964 | I915_READ(DPINVGTT)); | |
965 | ||
966 | } else if (!HAS_PCH_SPLIT(dev)) { | |
5f6a1695 ZW |
967 | seq_printf(m, "Interrupt enable: %08x\n", |
968 | I915_READ(IER)); | |
969 | seq_printf(m, "Interrupt identity: %08x\n", | |
970 | I915_READ(IIR)); | |
971 | seq_printf(m, "Interrupt mask: %08x\n", | |
972 | I915_READ(IMR)); | |
055e393f | 973 | for_each_pipe(dev_priv, pipe) |
9db4a9c7 JB |
974 | seq_printf(m, "Pipe %c stat: %08x\n", |
975 | pipe_name(pipe), | |
976 | I915_READ(PIPESTAT(pipe))); | |
5f6a1695 ZW |
977 | } else { |
978 | seq_printf(m, "North Display Interrupt enable: %08x\n", | |
979 | I915_READ(DEIER)); | |
980 | seq_printf(m, "North Display Interrupt identity: %08x\n", | |
981 | I915_READ(DEIIR)); | |
982 | seq_printf(m, "North Display Interrupt mask: %08x\n", | |
983 | I915_READ(DEIMR)); | |
984 | seq_printf(m, "South Display Interrupt enable: %08x\n", | |
985 | I915_READ(SDEIER)); | |
986 | seq_printf(m, "South Display Interrupt identity: %08x\n", | |
987 | I915_READ(SDEIIR)); | |
988 | seq_printf(m, "South Display Interrupt mask: %08x\n", | |
989 | I915_READ(SDEIMR)); | |
990 | seq_printf(m, "Graphics Interrupt enable: %08x\n", | |
991 | I915_READ(GTIER)); | |
992 | seq_printf(m, "Graphics Interrupt identity: %08x\n", | |
993 | I915_READ(GTIIR)); | |
994 | seq_printf(m, "Graphics Interrupt mask: %08x\n", | |
995 | I915_READ(GTIMR)); | |
996 | } | |
b4ac5afc | 997 | for_each_engine(engine, dev_priv) { |
a123f157 | 998 | if (INTEL_INFO(dev)->gen >= 6) { |
a2c7f6fd CW |
999 | seq_printf(m, |
1000 | "Graphics Interrupt mask (%s): %08x\n", | |
e2f80391 | 1001 | engine->name, I915_READ_IMR(engine)); |
9862e600 | 1002 | } |
e2f80391 | 1003 | i915_ring_seqno_info(m, engine); |
9862e600 | 1004 | } |
c8c8fb33 | 1005 | intel_runtime_pm_put(dev_priv); |
de227ef0 CW |
1006 | mutex_unlock(&dev->struct_mutex); |
1007 | ||
2017263e BG |
1008 | return 0; |
1009 | } | |
1010 | ||
a6172a80 CW |
1011 | static int i915_gem_fence_regs_info(struct seq_file *m, void *data) |
1012 | { | |
9f25d007 | 1013 | struct drm_info_node *node = m->private; |
a6172a80 | 1014 | struct drm_device *dev = node->minor->dev; |
e277a1f8 | 1015 | struct drm_i915_private *dev_priv = dev->dev_private; |
de227ef0 CW |
1016 | int i, ret; |
1017 | ||
1018 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
1019 | if (ret) | |
1020 | return ret; | |
a6172a80 | 1021 | |
a6172a80 CW |
1022 | seq_printf(m, "Total fences = %d\n", dev_priv->num_fence_regs); |
1023 | for (i = 0; i < dev_priv->num_fence_regs; i++) { | |
05394f39 | 1024 | struct drm_i915_gem_object *obj = dev_priv->fence_regs[i].obj; |
a6172a80 | 1025 | |
6c085a72 CW |
1026 | seq_printf(m, "Fence %d, pin count = %d, object = ", |
1027 | i, dev_priv->fence_regs[i].pin_count); | |
c2c347a9 | 1028 | if (obj == NULL) |
267f0c90 | 1029 | seq_puts(m, "unused"); |
c2c347a9 | 1030 | else |
05394f39 | 1031 | describe_obj(m, obj); |
267f0c90 | 1032 | seq_putc(m, '\n'); |
a6172a80 CW |
1033 | } |
1034 | ||
05394f39 | 1035 | mutex_unlock(&dev->struct_mutex); |
a6172a80 CW |
1036 | return 0; |
1037 | } | |
1038 | ||
2017263e BG |
1039 | static int i915_hws_info(struct seq_file *m, void *data) |
1040 | { | |
9f25d007 | 1041 | struct drm_info_node *node = m->private; |
2017263e | 1042 | struct drm_device *dev = node->minor->dev; |
e277a1f8 | 1043 | struct drm_i915_private *dev_priv = dev->dev_private; |
e2f80391 | 1044 | struct intel_engine_cs *engine; |
1a240d4d | 1045 | const u32 *hws; |
4066c0ae CW |
1046 | int i; |
1047 | ||
4a570db5 | 1048 | engine = &dev_priv->engine[(uintptr_t)node->info_ent->data]; |
e2f80391 | 1049 | hws = engine->status_page.page_addr; |
2017263e BG |
1050 | if (hws == NULL) |
1051 | return 0; | |
1052 | ||
1053 | for (i = 0; i < 4096 / sizeof(u32) / 4; i += 4) { | |
1054 | seq_printf(m, "0x%08x: 0x%08x 0x%08x 0x%08x 0x%08x\n", | |
1055 | i * 4, | |
1056 | hws[i], hws[i + 1], hws[i + 2], hws[i + 3]); | |
1057 | } | |
1058 | return 0; | |
1059 | } | |
1060 | ||
d5442303 DV |
1061 | static ssize_t |
1062 | i915_error_state_write(struct file *filp, | |
1063 | const char __user *ubuf, | |
1064 | size_t cnt, | |
1065 | loff_t *ppos) | |
1066 | { | |
edc3d884 | 1067 | struct i915_error_state_file_priv *error_priv = filp->private_data; |
d5442303 | 1068 | struct drm_device *dev = error_priv->dev; |
22bcfc6a | 1069 | int ret; |
d5442303 DV |
1070 | |
1071 | DRM_DEBUG_DRIVER("Resetting error state\n"); | |
1072 | ||
22bcfc6a DV |
1073 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
1074 | if (ret) | |
1075 | return ret; | |
1076 | ||
d5442303 DV |
1077 | i915_destroy_error_state(dev); |
1078 | mutex_unlock(&dev->struct_mutex); | |
1079 | ||
1080 | return cnt; | |
1081 | } | |
1082 | ||
1083 | static int i915_error_state_open(struct inode *inode, struct file *file) | |
1084 | { | |
1085 | struct drm_device *dev = inode->i_private; | |
d5442303 | 1086 | struct i915_error_state_file_priv *error_priv; |
d5442303 DV |
1087 | |
1088 | error_priv = kzalloc(sizeof(*error_priv), GFP_KERNEL); | |
1089 | if (!error_priv) | |
1090 | return -ENOMEM; | |
1091 | ||
1092 | error_priv->dev = dev; | |
1093 | ||
95d5bfb3 | 1094 | i915_error_state_get(dev, error_priv); |
d5442303 | 1095 | |
edc3d884 MK |
1096 | file->private_data = error_priv; |
1097 | ||
1098 | return 0; | |
d5442303 DV |
1099 | } |
1100 | ||
1101 | static int i915_error_state_release(struct inode *inode, struct file *file) | |
1102 | { | |
edc3d884 | 1103 | struct i915_error_state_file_priv *error_priv = file->private_data; |
d5442303 | 1104 | |
95d5bfb3 | 1105 | i915_error_state_put(error_priv); |
d5442303 DV |
1106 | kfree(error_priv); |
1107 | ||
edc3d884 MK |
1108 | return 0; |
1109 | } | |
1110 | ||
4dc955f7 MK |
1111 | static ssize_t i915_error_state_read(struct file *file, char __user *userbuf, |
1112 | size_t count, loff_t *pos) | |
1113 | { | |
1114 | struct i915_error_state_file_priv *error_priv = file->private_data; | |
1115 | struct drm_i915_error_state_buf error_str; | |
1116 | loff_t tmp_pos = 0; | |
1117 | ssize_t ret_count = 0; | |
1118 | int ret; | |
1119 | ||
0a4cd7c8 | 1120 | ret = i915_error_state_buf_init(&error_str, to_i915(error_priv->dev), count, *pos); |
4dc955f7 MK |
1121 | if (ret) |
1122 | return ret; | |
edc3d884 | 1123 | |
fc16b48b | 1124 | ret = i915_error_state_to_str(&error_str, error_priv); |
edc3d884 MK |
1125 | if (ret) |
1126 | goto out; | |
1127 | ||
edc3d884 MK |
1128 | ret_count = simple_read_from_buffer(userbuf, count, &tmp_pos, |
1129 | error_str.buf, | |
1130 | error_str.bytes); | |
1131 | ||
1132 | if (ret_count < 0) | |
1133 | ret = ret_count; | |
1134 | else | |
1135 | *pos = error_str.start + ret_count; | |
1136 | out: | |
4dc955f7 | 1137 | i915_error_state_buf_release(&error_str); |
edc3d884 | 1138 | return ret ?: ret_count; |
d5442303 DV |
1139 | } |
1140 | ||
1141 | static const struct file_operations i915_error_state_fops = { | |
1142 | .owner = THIS_MODULE, | |
1143 | .open = i915_error_state_open, | |
edc3d884 | 1144 | .read = i915_error_state_read, |
d5442303 DV |
1145 | .write = i915_error_state_write, |
1146 | .llseek = default_llseek, | |
1147 | .release = i915_error_state_release, | |
1148 | }; | |
1149 | ||
647416f9 KC |
1150 | static int |
1151 | i915_next_seqno_get(void *data, u64 *val) | |
40633219 | 1152 | { |
647416f9 | 1153 | struct drm_device *dev = data; |
e277a1f8 | 1154 | struct drm_i915_private *dev_priv = dev->dev_private; |
40633219 MK |
1155 | int ret; |
1156 | ||
1157 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
1158 | if (ret) | |
1159 | return ret; | |
1160 | ||
647416f9 | 1161 | *val = dev_priv->next_seqno; |
40633219 MK |
1162 | mutex_unlock(&dev->struct_mutex); |
1163 | ||
647416f9 | 1164 | return 0; |
40633219 MK |
1165 | } |
1166 | ||
647416f9 KC |
1167 | static int |
1168 | i915_next_seqno_set(void *data, u64 val) | |
1169 | { | |
1170 | struct drm_device *dev = data; | |
40633219 MK |
1171 | int ret; |
1172 | ||
40633219 MK |
1173 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
1174 | if (ret) | |
1175 | return ret; | |
1176 | ||
e94fbaa8 | 1177 | ret = i915_gem_set_seqno(dev, val); |
40633219 MK |
1178 | mutex_unlock(&dev->struct_mutex); |
1179 | ||
647416f9 | 1180 | return ret; |
40633219 MK |
1181 | } |
1182 | ||
647416f9 KC |
1183 | DEFINE_SIMPLE_ATTRIBUTE(i915_next_seqno_fops, |
1184 | i915_next_seqno_get, i915_next_seqno_set, | |
3a3b4f98 | 1185 | "0x%llx\n"); |
40633219 | 1186 | |
adb4bd12 | 1187 | static int i915_frequency_info(struct seq_file *m, void *unused) |
f97108d1 | 1188 | { |
9f25d007 | 1189 | struct drm_info_node *node = m->private; |
f97108d1 | 1190 | struct drm_device *dev = node->minor->dev; |
e277a1f8 | 1191 | struct drm_i915_private *dev_priv = dev->dev_private; |
c8c8fb33 PZ |
1192 | int ret = 0; |
1193 | ||
1194 | intel_runtime_pm_get(dev_priv); | |
3b8d8d91 | 1195 | |
5c9669ce TR |
1196 | flush_delayed_work(&dev_priv->rps.delayed_resume_work); |
1197 | ||
3b8d8d91 JB |
1198 | if (IS_GEN5(dev)) { |
1199 | u16 rgvswctl = I915_READ16(MEMSWCTL); | |
1200 | u16 rgvstat = I915_READ16(MEMSTAT_ILK); | |
1201 | ||
1202 | seq_printf(m, "Requested P-state: %d\n", (rgvswctl >> 8) & 0xf); | |
1203 | seq_printf(m, "Requested VID: %d\n", rgvswctl & 0x3f); | |
1204 | seq_printf(m, "Current VID: %d\n", (rgvstat & MEMSTAT_VID_MASK) >> | |
1205 | MEMSTAT_VID_SHIFT); | |
1206 | seq_printf(m, "Current P-state: %d\n", | |
1207 | (rgvstat & MEMSTAT_PSTATE_MASK) >> MEMSTAT_PSTATE_SHIFT); | |
666a4537 WB |
1208 | } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { |
1209 | u32 freq_sts; | |
1210 | ||
1211 | mutex_lock(&dev_priv->rps.hw_lock); | |
1212 | freq_sts = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS); | |
1213 | seq_printf(m, "PUNIT_REG_GPU_FREQ_STS: 0x%08x\n", freq_sts); | |
1214 | seq_printf(m, "DDR freq: %d MHz\n", dev_priv->mem_freq); | |
1215 | ||
1216 | seq_printf(m, "actual GPU freq: %d MHz\n", | |
1217 | intel_gpu_freq(dev_priv, (freq_sts >> 8) & 0xff)); | |
1218 | ||
1219 | seq_printf(m, "current GPU freq: %d MHz\n", | |
1220 | intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq)); | |
1221 | ||
1222 | seq_printf(m, "max GPU freq: %d MHz\n", | |
1223 | intel_gpu_freq(dev_priv, dev_priv->rps.max_freq)); | |
1224 | ||
1225 | seq_printf(m, "min GPU freq: %d MHz\n", | |
1226 | intel_gpu_freq(dev_priv, dev_priv->rps.min_freq)); | |
1227 | ||
1228 | seq_printf(m, "idle GPU freq: %d MHz\n", | |
1229 | intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq)); | |
1230 | ||
1231 | seq_printf(m, | |
1232 | "efficient (RPe) frequency: %d MHz\n", | |
1233 | intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq)); | |
1234 | mutex_unlock(&dev_priv->rps.hw_lock); | |
1235 | } else if (INTEL_INFO(dev)->gen >= 6) { | |
35040562 BP |
1236 | u32 rp_state_limits; |
1237 | u32 gt_perf_status; | |
1238 | u32 rp_state_cap; | |
0d8f9491 | 1239 | u32 rpmodectl, rpinclimit, rpdeclimit; |
8e8c06cd | 1240 | u32 rpstat, cagf, reqf; |
ccab5c82 JB |
1241 | u32 rpupei, rpcurup, rpprevup; |
1242 | u32 rpdownei, rpcurdown, rpprevdown; | |
9dd3c605 | 1243 | u32 pm_ier, pm_imr, pm_isr, pm_iir, pm_mask; |
3b8d8d91 JB |
1244 | int max_freq; |
1245 | ||
35040562 BP |
1246 | rp_state_limits = I915_READ(GEN6_RP_STATE_LIMITS); |
1247 | if (IS_BROXTON(dev)) { | |
1248 | rp_state_cap = I915_READ(BXT_RP_STATE_CAP); | |
1249 | gt_perf_status = I915_READ(BXT_GT_PERF_STATUS); | |
1250 | } else { | |
1251 | rp_state_cap = I915_READ(GEN6_RP_STATE_CAP); | |
1252 | gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS); | |
1253 | } | |
1254 | ||
3b8d8d91 | 1255 | /* RPSTAT1 is in the GT power well */ |
d1ebd816 BW |
1256 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
1257 | if (ret) | |
c8c8fb33 | 1258 | goto out; |
d1ebd816 | 1259 | |
59bad947 | 1260 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); |
3b8d8d91 | 1261 | |
8e8c06cd | 1262 | reqf = I915_READ(GEN6_RPNSWREQ); |
60260a5b AG |
1263 | if (IS_GEN9(dev)) |
1264 | reqf >>= 23; | |
1265 | else { | |
1266 | reqf &= ~GEN6_TURBO_DISABLE; | |
1267 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) | |
1268 | reqf >>= 24; | |
1269 | else | |
1270 | reqf >>= 25; | |
1271 | } | |
7c59a9c1 | 1272 | reqf = intel_gpu_freq(dev_priv, reqf); |
8e8c06cd | 1273 | |
0d8f9491 CW |
1274 | rpmodectl = I915_READ(GEN6_RP_CONTROL); |
1275 | rpinclimit = I915_READ(GEN6_RP_UP_THRESHOLD); | |
1276 | rpdeclimit = I915_READ(GEN6_RP_DOWN_THRESHOLD); | |
1277 | ||
ccab5c82 | 1278 | rpstat = I915_READ(GEN6_RPSTAT1); |
d6cda9c7 AG |
1279 | rpupei = I915_READ(GEN6_RP_CUR_UP_EI) & GEN6_CURICONT_MASK; |
1280 | rpcurup = I915_READ(GEN6_RP_CUR_UP) & GEN6_CURBSYTAVG_MASK; | |
1281 | rpprevup = I915_READ(GEN6_RP_PREV_UP) & GEN6_CURBSYTAVG_MASK; | |
1282 | rpdownei = I915_READ(GEN6_RP_CUR_DOWN_EI) & GEN6_CURIAVG_MASK; | |
1283 | rpcurdown = I915_READ(GEN6_RP_CUR_DOWN) & GEN6_CURBSYTAVG_MASK; | |
1284 | rpprevdown = I915_READ(GEN6_RP_PREV_DOWN) & GEN6_CURBSYTAVG_MASK; | |
60260a5b AG |
1285 | if (IS_GEN9(dev)) |
1286 | cagf = (rpstat & GEN9_CAGF_MASK) >> GEN9_CAGF_SHIFT; | |
1287 | else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) | |
f82855d3 BW |
1288 | cagf = (rpstat & HSW_CAGF_MASK) >> HSW_CAGF_SHIFT; |
1289 | else | |
1290 | cagf = (rpstat & GEN6_CAGF_MASK) >> GEN6_CAGF_SHIFT; | |
7c59a9c1 | 1291 | cagf = intel_gpu_freq(dev_priv, cagf); |
ccab5c82 | 1292 | |
59bad947 | 1293 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); |
d1ebd816 BW |
1294 | mutex_unlock(&dev->struct_mutex); |
1295 | ||
9dd3c605 PZ |
1296 | if (IS_GEN6(dev) || IS_GEN7(dev)) { |
1297 | pm_ier = I915_READ(GEN6_PMIER); | |
1298 | pm_imr = I915_READ(GEN6_PMIMR); | |
1299 | pm_isr = I915_READ(GEN6_PMISR); | |
1300 | pm_iir = I915_READ(GEN6_PMIIR); | |
1301 | pm_mask = I915_READ(GEN6_PMINTRMSK); | |
1302 | } else { | |
1303 | pm_ier = I915_READ(GEN8_GT_IER(2)); | |
1304 | pm_imr = I915_READ(GEN8_GT_IMR(2)); | |
1305 | pm_isr = I915_READ(GEN8_GT_ISR(2)); | |
1306 | pm_iir = I915_READ(GEN8_GT_IIR(2)); | |
1307 | pm_mask = I915_READ(GEN6_PMINTRMSK); | |
1308 | } | |
0d8f9491 | 1309 | seq_printf(m, "PM IER=0x%08x IMR=0x%08x ISR=0x%08x IIR=0x%08x, MASK=0x%08x\n", |
9dd3c605 | 1310 | pm_ier, pm_imr, pm_isr, pm_iir, pm_mask); |
3b8d8d91 | 1311 | seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status); |
3b8d8d91 | 1312 | seq_printf(m, "Render p-state ratio: %d\n", |
60260a5b | 1313 | (gt_perf_status & (IS_GEN9(dev) ? 0x1ff00 : 0xff00)) >> 8); |
3b8d8d91 JB |
1314 | seq_printf(m, "Render p-state VID: %d\n", |
1315 | gt_perf_status & 0xff); | |
1316 | seq_printf(m, "Render p-state limit: %d\n", | |
1317 | rp_state_limits & 0xff); | |
0d8f9491 CW |
1318 | seq_printf(m, "RPSTAT1: 0x%08x\n", rpstat); |
1319 | seq_printf(m, "RPMODECTL: 0x%08x\n", rpmodectl); | |
1320 | seq_printf(m, "RPINCLIMIT: 0x%08x\n", rpinclimit); | |
1321 | seq_printf(m, "RPDECLIMIT: 0x%08x\n", rpdeclimit); | |
8e8c06cd | 1322 | seq_printf(m, "RPNSWREQ: %dMHz\n", reqf); |
f82855d3 | 1323 | seq_printf(m, "CAGF: %dMHz\n", cagf); |
d6cda9c7 AG |
1324 | seq_printf(m, "RP CUR UP EI: %d (%dus)\n", |
1325 | rpupei, GT_PM_INTERVAL_TO_US(dev_priv, rpupei)); | |
1326 | seq_printf(m, "RP CUR UP: %d (%dus)\n", | |
1327 | rpcurup, GT_PM_INTERVAL_TO_US(dev_priv, rpcurup)); | |
1328 | seq_printf(m, "RP PREV UP: %d (%dus)\n", | |
1329 | rpprevup, GT_PM_INTERVAL_TO_US(dev_priv, rpprevup)); | |
d86ed34a CW |
1330 | seq_printf(m, "Up threshold: %d%%\n", |
1331 | dev_priv->rps.up_threshold); | |
1332 | ||
d6cda9c7 AG |
1333 | seq_printf(m, "RP CUR DOWN EI: %d (%dus)\n", |
1334 | rpdownei, GT_PM_INTERVAL_TO_US(dev_priv, rpdownei)); | |
1335 | seq_printf(m, "RP CUR DOWN: %d (%dus)\n", | |
1336 | rpcurdown, GT_PM_INTERVAL_TO_US(dev_priv, rpcurdown)); | |
1337 | seq_printf(m, "RP PREV DOWN: %d (%dus)\n", | |
1338 | rpprevdown, GT_PM_INTERVAL_TO_US(dev_priv, rpprevdown)); | |
d86ed34a CW |
1339 | seq_printf(m, "Down threshold: %d%%\n", |
1340 | dev_priv->rps.down_threshold); | |
3b8d8d91 | 1341 | |
35040562 BP |
1342 | max_freq = (IS_BROXTON(dev) ? rp_state_cap >> 0 : |
1343 | rp_state_cap >> 16) & 0xff; | |
ef11bdb3 RV |
1344 | max_freq *= (IS_SKYLAKE(dev) || IS_KABYLAKE(dev) ? |
1345 | GEN9_FREQ_SCALER : 1); | |
3b8d8d91 | 1346 | seq_printf(m, "Lowest (RPN) frequency: %dMHz\n", |
7c59a9c1 | 1347 | intel_gpu_freq(dev_priv, max_freq)); |
3b8d8d91 JB |
1348 | |
1349 | max_freq = (rp_state_cap & 0xff00) >> 8; | |
ef11bdb3 RV |
1350 | max_freq *= (IS_SKYLAKE(dev) || IS_KABYLAKE(dev) ? |
1351 | GEN9_FREQ_SCALER : 1); | |
3b8d8d91 | 1352 | seq_printf(m, "Nominal (RP1) frequency: %dMHz\n", |
7c59a9c1 | 1353 | intel_gpu_freq(dev_priv, max_freq)); |
3b8d8d91 | 1354 | |
35040562 BP |
1355 | max_freq = (IS_BROXTON(dev) ? rp_state_cap >> 16 : |
1356 | rp_state_cap >> 0) & 0xff; | |
ef11bdb3 RV |
1357 | max_freq *= (IS_SKYLAKE(dev) || IS_KABYLAKE(dev) ? |
1358 | GEN9_FREQ_SCALER : 1); | |
3b8d8d91 | 1359 | seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n", |
7c59a9c1 | 1360 | intel_gpu_freq(dev_priv, max_freq)); |
31c77388 | 1361 | seq_printf(m, "Max overclocked frequency: %dMHz\n", |
7c59a9c1 | 1362 | intel_gpu_freq(dev_priv, dev_priv->rps.max_freq)); |
aed242ff | 1363 | |
d86ed34a CW |
1364 | seq_printf(m, "Current freq: %d MHz\n", |
1365 | intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq)); | |
1366 | seq_printf(m, "Actual freq: %d MHz\n", cagf); | |
aed242ff CW |
1367 | seq_printf(m, "Idle freq: %d MHz\n", |
1368 | intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq)); | |
d86ed34a CW |
1369 | seq_printf(m, "Min freq: %d MHz\n", |
1370 | intel_gpu_freq(dev_priv, dev_priv->rps.min_freq)); | |
1371 | seq_printf(m, "Max freq: %d MHz\n", | |
1372 | intel_gpu_freq(dev_priv, dev_priv->rps.max_freq)); | |
1373 | seq_printf(m, | |
1374 | "efficient (RPe) frequency: %d MHz\n", | |
1375 | intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq)); | |
3b8d8d91 | 1376 | } else { |
267f0c90 | 1377 | seq_puts(m, "no P-state info available\n"); |
3b8d8d91 | 1378 | } |
f97108d1 | 1379 | |
1170f28c MK |
1380 | seq_printf(m, "Current CD clock frequency: %d kHz\n", dev_priv->cdclk_freq); |
1381 | seq_printf(m, "Max CD clock frequency: %d kHz\n", dev_priv->max_cdclk_freq); | |
1382 | seq_printf(m, "Max pixel clock frequency: %d kHz\n", dev_priv->max_dotclk_freq); | |
1383 | ||
c8c8fb33 PZ |
1384 | out: |
1385 | intel_runtime_pm_put(dev_priv); | |
1386 | return ret; | |
f97108d1 JB |
1387 | } |
1388 | ||
f654449a CW |
1389 | static int i915_hangcheck_info(struct seq_file *m, void *unused) |
1390 | { | |
1391 | struct drm_info_node *node = m->private; | |
ebbc7546 MK |
1392 | struct drm_device *dev = node->minor->dev; |
1393 | struct drm_i915_private *dev_priv = dev->dev_private; | |
e2f80391 | 1394 | struct intel_engine_cs *engine; |
666796da TU |
1395 | u64 acthd[I915_NUM_ENGINES]; |
1396 | u32 seqno[I915_NUM_ENGINES]; | |
61642ff0 | 1397 | u32 instdone[I915_NUM_INSTDONE_REG]; |
c3232b18 DG |
1398 | enum intel_engine_id id; |
1399 | int j; | |
f654449a CW |
1400 | |
1401 | if (!i915.enable_hangcheck) { | |
1402 | seq_printf(m, "Hangcheck disabled\n"); | |
1403 | return 0; | |
1404 | } | |
1405 | ||
ebbc7546 MK |
1406 | intel_runtime_pm_get(dev_priv); |
1407 | ||
c3232b18 | 1408 | for_each_engine_id(engine, dev_priv, id) { |
c3232b18 | 1409 | acthd[id] = intel_ring_get_active_head(engine); |
c04e0f3b | 1410 | seqno[id] = engine->get_seqno(engine); |
ebbc7546 MK |
1411 | } |
1412 | ||
c033666a | 1413 | i915_get_extra_instdone(dev_priv, instdone); |
61642ff0 | 1414 | |
ebbc7546 MK |
1415 | intel_runtime_pm_put(dev_priv); |
1416 | ||
f654449a CW |
1417 | if (delayed_work_pending(&dev_priv->gpu_error.hangcheck_work)) { |
1418 | seq_printf(m, "Hangcheck active, fires in %dms\n", | |
1419 | jiffies_to_msecs(dev_priv->gpu_error.hangcheck_work.timer.expires - | |
1420 | jiffies)); | |
1421 | } else | |
1422 | seq_printf(m, "Hangcheck inactive\n"); | |
1423 | ||
c3232b18 | 1424 | for_each_engine_id(engine, dev_priv, id) { |
e2f80391 | 1425 | seq_printf(m, "%s:\n", engine->name); |
14fd0d6d CW |
1426 | seq_printf(m, "\tseqno = %x [current %x, last %x]\n", |
1427 | engine->hangcheck.seqno, | |
1428 | seqno[id], | |
1429 | engine->last_submitted_seqno); | |
12471ba8 CW |
1430 | seq_printf(m, "\tuser interrupts = %x [current %x]\n", |
1431 | engine->hangcheck.user_interrupts, | |
1432 | READ_ONCE(engine->user_interrupts)); | |
f654449a | 1433 | seq_printf(m, "\tACTHD = 0x%08llx [current 0x%08llx]\n", |
e2f80391 | 1434 | (long long)engine->hangcheck.acthd, |
c3232b18 | 1435 | (long long)acthd[id]); |
e2f80391 TU |
1436 | seq_printf(m, "\tscore = %d\n", engine->hangcheck.score); |
1437 | seq_printf(m, "\taction = %d\n", engine->hangcheck.action); | |
61642ff0 | 1438 | |
e2f80391 | 1439 | if (engine->id == RCS) { |
61642ff0 MK |
1440 | seq_puts(m, "\tinstdone read ="); |
1441 | ||
1442 | for (j = 0; j < I915_NUM_INSTDONE_REG; j++) | |
1443 | seq_printf(m, " 0x%08x", instdone[j]); | |
1444 | ||
1445 | seq_puts(m, "\n\tinstdone accu ="); | |
1446 | ||
1447 | for (j = 0; j < I915_NUM_INSTDONE_REG; j++) | |
1448 | seq_printf(m, " 0x%08x", | |
e2f80391 | 1449 | engine->hangcheck.instdone[j]); |
61642ff0 MK |
1450 | |
1451 | seq_puts(m, "\n"); | |
1452 | } | |
f654449a CW |
1453 | } |
1454 | ||
1455 | return 0; | |
1456 | } | |
1457 | ||
4d85529d | 1458 | static int ironlake_drpc_info(struct seq_file *m) |
f97108d1 | 1459 | { |
9f25d007 | 1460 | struct drm_info_node *node = m->private; |
f97108d1 | 1461 | struct drm_device *dev = node->minor->dev; |
e277a1f8 | 1462 | struct drm_i915_private *dev_priv = dev->dev_private; |
616fdb5a BW |
1463 | u32 rgvmodectl, rstdbyctl; |
1464 | u16 crstandvid; | |
1465 | int ret; | |
1466 | ||
1467 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
1468 | if (ret) | |
1469 | return ret; | |
c8c8fb33 | 1470 | intel_runtime_pm_get(dev_priv); |
616fdb5a BW |
1471 | |
1472 | rgvmodectl = I915_READ(MEMMODECTL); | |
1473 | rstdbyctl = I915_READ(RSTDBYCTL); | |
1474 | crstandvid = I915_READ16(CRSTANDVID); | |
1475 | ||
c8c8fb33 | 1476 | intel_runtime_pm_put(dev_priv); |
616fdb5a | 1477 | mutex_unlock(&dev->struct_mutex); |
f97108d1 | 1478 | |
742f491d | 1479 | seq_printf(m, "HD boost: %s\n", yesno(rgvmodectl & MEMMODE_BOOST_EN)); |
f97108d1 JB |
1480 | seq_printf(m, "Boost freq: %d\n", |
1481 | (rgvmodectl & MEMMODE_BOOST_FREQ_MASK) >> | |
1482 | MEMMODE_BOOST_FREQ_SHIFT); | |
1483 | seq_printf(m, "HW control enabled: %s\n", | |
742f491d | 1484 | yesno(rgvmodectl & MEMMODE_HWIDLE_EN)); |
f97108d1 | 1485 | seq_printf(m, "SW control enabled: %s\n", |
742f491d | 1486 | yesno(rgvmodectl & MEMMODE_SWMODE_EN)); |
f97108d1 | 1487 | seq_printf(m, "Gated voltage change: %s\n", |
742f491d | 1488 | yesno(rgvmodectl & MEMMODE_RCLK_GATE)); |
f97108d1 JB |
1489 | seq_printf(m, "Starting frequency: P%d\n", |
1490 | (rgvmodectl & MEMMODE_FSTART_MASK) >> MEMMODE_FSTART_SHIFT); | |
7648fa99 | 1491 | seq_printf(m, "Max P-state: P%d\n", |
f97108d1 | 1492 | (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT); |
7648fa99 JB |
1493 | seq_printf(m, "Min P-state: P%d\n", (rgvmodectl & MEMMODE_FMIN_MASK)); |
1494 | seq_printf(m, "RS1 VID: %d\n", (crstandvid & 0x3f)); | |
1495 | seq_printf(m, "RS2 VID: %d\n", ((crstandvid >> 8) & 0x3f)); | |
1496 | seq_printf(m, "Render standby enabled: %s\n", | |
742f491d | 1497 | yesno(!(rstdbyctl & RCX_SW_EXIT))); |
267f0c90 | 1498 | seq_puts(m, "Current RS state: "); |
88271da3 JB |
1499 | switch (rstdbyctl & RSX_STATUS_MASK) { |
1500 | case RSX_STATUS_ON: | |
267f0c90 | 1501 | seq_puts(m, "on\n"); |
88271da3 JB |
1502 | break; |
1503 | case RSX_STATUS_RC1: | |
267f0c90 | 1504 | seq_puts(m, "RC1\n"); |
88271da3 JB |
1505 | break; |
1506 | case RSX_STATUS_RC1E: | |
267f0c90 | 1507 | seq_puts(m, "RC1E\n"); |
88271da3 JB |
1508 | break; |
1509 | case RSX_STATUS_RS1: | |
267f0c90 | 1510 | seq_puts(m, "RS1\n"); |
88271da3 JB |
1511 | break; |
1512 | case RSX_STATUS_RS2: | |
267f0c90 | 1513 | seq_puts(m, "RS2 (RC6)\n"); |
88271da3 JB |
1514 | break; |
1515 | case RSX_STATUS_RS3: | |
267f0c90 | 1516 | seq_puts(m, "RC3 (RC6+)\n"); |
88271da3 JB |
1517 | break; |
1518 | default: | |
267f0c90 | 1519 | seq_puts(m, "unknown\n"); |
88271da3 JB |
1520 | break; |
1521 | } | |
f97108d1 JB |
1522 | |
1523 | return 0; | |
1524 | } | |
1525 | ||
f65367b5 | 1526 | static int i915_forcewake_domains(struct seq_file *m, void *data) |
669ab5aa | 1527 | { |
b2cff0db CW |
1528 | struct drm_info_node *node = m->private; |
1529 | struct drm_device *dev = node->minor->dev; | |
1530 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1531 | struct intel_uncore_forcewake_domain *fw_domain; | |
b2cff0db CW |
1532 | |
1533 | spin_lock_irq(&dev_priv->uncore.lock); | |
33c582c1 | 1534 | for_each_fw_domain(fw_domain, dev_priv) { |
b2cff0db | 1535 | seq_printf(m, "%s.wake_count = %u\n", |
33c582c1 | 1536 | intel_uncore_forcewake_domain_to_str(fw_domain->id), |
b2cff0db CW |
1537 | fw_domain->wake_count); |
1538 | } | |
1539 | spin_unlock_irq(&dev_priv->uncore.lock); | |
669ab5aa | 1540 | |
b2cff0db CW |
1541 | return 0; |
1542 | } | |
1543 | ||
1544 | static int vlv_drpc_info(struct seq_file *m) | |
1545 | { | |
9f25d007 | 1546 | struct drm_info_node *node = m->private; |
669ab5aa D |
1547 | struct drm_device *dev = node->minor->dev; |
1548 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6b312cd3 | 1549 | u32 rpmodectl1, rcctl1, pw_status; |
669ab5aa | 1550 | |
d46c0517 ID |
1551 | intel_runtime_pm_get(dev_priv); |
1552 | ||
6b312cd3 | 1553 | pw_status = I915_READ(VLV_GTLC_PW_STATUS); |
669ab5aa D |
1554 | rpmodectl1 = I915_READ(GEN6_RP_CONTROL); |
1555 | rcctl1 = I915_READ(GEN6_RC_CONTROL); | |
1556 | ||
d46c0517 ID |
1557 | intel_runtime_pm_put(dev_priv); |
1558 | ||
669ab5aa D |
1559 | seq_printf(m, "Video Turbo Mode: %s\n", |
1560 | yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO)); | |
1561 | seq_printf(m, "Turbo enabled: %s\n", | |
1562 | yesno(rpmodectl1 & GEN6_RP_ENABLE)); | |
1563 | seq_printf(m, "HW control enabled: %s\n", | |
1564 | yesno(rpmodectl1 & GEN6_RP_ENABLE)); | |
1565 | seq_printf(m, "SW control enabled: %s\n", | |
1566 | yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) == | |
1567 | GEN6_RP_MEDIA_SW_MODE)); | |
1568 | seq_printf(m, "RC6 Enabled: %s\n", | |
1569 | yesno(rcctl1 & (GEN7_RC_CTL_TO_MODE | | |
1570 | GEN6_RC_CTL_EI_MODE(1)))); | |
1571 | seq_printf(m, "Render Power Well: %s\n", | |
6b312cd3 | 1572 | (pw_status & VLV_GTLC_PW_RENDER_STATUS_MASK) ? "Up" : "Down"); |
669ab5aa | 1573 | seq_printf(m, "Media Power Well: %s\n", |
6b312cd3 | 1574 | (pw_status & VLV_GTLC_PW_MEDIA_STATUS_MASK) ? "Up" : "Down"); |
669ab5aa | 1575 | |
9cc19be5 ID |
1576 | seq_printf(m, "Render RC6 residency since boot: %u\n", |
1577 | I915_READ(VLV_GT_RENDER_RC6)); | |
1578 | seq_printf(m, "Media RC6 residency since boot: %u\n", | |
1579 | I915_READ(VLV_GT_MEDIA_RC6)); | |
1580 | ||
f65367b5 | 1581 | return i915_forcewake_domains(m, NULL); |
669ab5aa D |
1582 | } |
1583 | ||
4d85529d BW |
1584 | static int gen6_drpc_info(struct seq_file *m) |
1585 | { | |
9f25d007 | 1586 | struct drm_info_node *node = m->private; |
4d85529d BW |
1587 | struct drm_device *dev = node->minor->dev; |
1588 | struct drm_i915_private *dev_priv = dev->dev_private; | |
ecd8faea | 1589 | u32 rpmodectl1, gt_core_status, rcctl1, rc6vids = 0; |
93b525dc | 1590 | unsigned forcewake_count; |
aee56cff | 1591 | int count = 0, ret; |
4d85529d BW |
1592 | |
1593 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
1594 | if (ret) | |
1595 | return ret; | |
c8c8fb33 | 1596 | intel_runtime_pm_get(dev_priv); |
4d85529d | 1597 | |
907b28c5 | 1598 | spin_lock_irq(&dev_priv->uncore.lock); |
b2cff0db | 1599 | forcewake_count = dev_priv->uncore.fw_domain[FW_DOMAIN_ID_RENDER].wake_count; |
907b28c5 | 1600 | spin_unlock_irq(&dev_priv->uncore.lock); |
93b525dc DV |
1601 | |
1602 | if (forcewake_count) { | |
267f0c90 DL |
1603 | seq_puts(m, "RC information inaccurate because somebody " |
1604 | "holds a forcewake reference \n"); | |
4d85529d BW |
1605 | } else { |
1606 | /* NB: we cannot use forcewake, else we read the wrong values */ | |
1607 | while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1)) | |
1608 | udelay(10); | |
1609 | seq_printf(m, "RC information accurate: %s\n", yesno(count < 51)); | |
1610 | } | |
1611 | ||
75aa3f63 | 1612 | gt_core_status = I915_READ_FW(GEN6_GT_CORE_STATUS); |
ed71f1b4 | 1613 | trace_i915_reg_rw(false, GEN6_GT_CORE_STATUS, gt_core_status, 4, true); |
4d85529d BW |
1614 | |
1615 | rpmodectl1 = I915_READ(GEN6_RP_CONTROL); | |
1616 | rcctl1 = I915_READ(GEN6_RC_CONTROL); | |
1617 | mutex_unlock(&dev->struct_mutex); | |
44cbd338 BW |
1618 | mutex_lock(&dev_priv->rps.hw_lock); |
1619 | sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids); | |
1620 | mutex_unlock(&dev_priv->rps.hw_lock); | |
4d85529d | 1621 | |
c8c8fb33 PZ |
1622 | intel_runtime_pm_put(dev_priv); |
1623 | ||
4d85529d BW |
1624 | seq_printf(m, "Video Turbo Mode: %s\n", |
1625 | yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO)); | |
1626 | seq_printf(m, "HW control enabled: %s\n", | |
1627 | yesno(rpmodectl1 & GEN6_RP_ENABLE)); | |
1628 | seq_printf(m, "SW control enabled: %s\n", | |
1629 | yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) == | |
1630 | GEN6_RP_MEDIA_SW_MODE)); | |
fff24e21 | 1631 | seq_printf(m, "RC1e Enabled: %s\n", |
4d85529d BW |
1632 | yesno(rcctl1 & GEN6_RC_CTL_RC1e_ENABLE)); |
1633 | seq_printf(m, "RC6 Enabled: %s\n", | |
1634 | yesno(rcctl1 & GEN6_RC_CTL_RC6_ENABLE)); | |
1635 | seq_printf(m, "Deep RC6 Enabled: %s\n", | |
1636 | yesno(rcctl1 & GEN6_RC_CTL_RC6p_ENABLE)); | |
1637 | seq_printf(m, "Deepest RC6 Enabled: %s\n", | |
1638 | yesno(rcctl1 & GEN6_RC_CTL_RC6pp_ENABLE)); | |
267f0c90 | 1639 | seq_puts(m, "Current RC state: "); |
4d85529d BW |
1640 | switch (gt_core_status & GEN6_RCn_MASK) { |
1641 | case GEN6_RC0: | |
1642 | if (gt_core_status & GEN6_CORE_CPD_STATE_MASK) | |
267f0c90 | 1643 | seq_puts(m, "Core Power Down\n"); |
4d85529d | 1644 | else |
267f0c90 | 1645 | seq_puts(m, "on\n"); |
4d85529d BW |
1646 | break; |
1647 | case GEN6_RC3: | |
267f0c90 | 1648 | seq_puts(m, "RC3\n"); |
4d85529d BW |
1649 | break; |
1650 | case GEN6_RC6: | |
267f0c90 | 1651 | seq_puts(m, "RC6\n"); |
4d85529d BW |
1652 | break; |
1653 | case GEN6_RC7: | |
267f0c90 | 1654 | seq_puts(m, "RC7\n"); |
4d85529d BW |
1655 | break; |
1656 | default: | |
267f0c90 | 1657 | seq_puts(m, "Unknown\n"); |
4d85529d BW |
1658 | break; |
1659 | } | |
1660 | ||
1661 | seq_printf(m, "Core Power Down: %s\n", | |
1662 | yesno(gt_core_status & GEN6_CORE_CPD_STATE_MASK)); | |
cce66a28 BW |
1663 | |
1664 | /* Not exactly sure what this is */ | |
1665 | seq_printf(m, "RC6 \"Locked to RPn\" residency since boot: %u\n", | |
1666 | I915_READ(GEN6_GT_GFX_RC6_LOCKED)); | |
1667 | seq_printf(m, "RC6 residency since boot: %u\n", | |
1668 | I915_READ(GEN6_GT_GFX_RC6)); | |
1669 | seq_printf(m, "RC6+ residency since boot: %u\n", | |
1670 | I915_READ(GEN6_GT_GFX_RC6p)); | |
1671 | seq_printf(m, "RC6++ residency since boot: %u\n", | |
1672 | I915_READ(GEN6_GT_GFX_RC6pp)); | |
1673 | ||
ecd8faea BW |
1674 | seq_printf(m, "RC6 voltage: %dmV\n", |
1675 | GEN6_DECODE_RC6_VID(((rc6vids >> 0) & 0xff))); | |
1676 | seq_printf(m, "RC6+ voltage: %dmV\n", | |
1677 | GEN6_DECODE_RC6_VID(((rc6vids >> 8) & 0xff))); | |
1678 | seq_printf(m, "RC6++ voltage: %dmV\n", | |
1679 | GEN6_DECODE_RC6_VID(((rc6vids >> 16) & 0xff))); | |
4d85529d BW |
1680 | return 0; |
1681 | } | |
1682 | ||
1683 | static int i915_drpc_info(struct seq_file *m, void *unused) | |
1684 | { | |
9f25d007 | 1685 | struct drm_info_node *node = m->private; |
4d85529d BW |
1686 | struct drm_device *dev = node->minor->dev; |
1687 | ||
666a4537 | 1688 | if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) |
669ab5aa | 1689 | return vlv_drpc_info(m); |
ac66cf4b | 1690 | else if (INTEL_INFO(dev)->gen >= 6) |
4d85529d BW |
1691 | return gen6_drpc_info(m); |
1692 | else | |
1693 | return ironlake_drpc_info(m); | |
1694 | } | |
1695 | ||
9a851789 DV |
1696 | static int i915_frontbuffer_tracking(struct seq_file *m, void *unused) |
1697 | { | |
1698 | struct drm_info_node *node = m->private; | |
1699 | struct drm_device *dev = node->minor->dev; | |
1700 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1701 | ||
1702 | seq_printf(m, "FB tracking busy bits: 0x%08x\n", | |
1703 | dev_priv->fb_tracking.busy_bits); | |
1704 | ||
1705 | seq_printf(m, "FB tracking flip bits: 0x%08x\n", | |
1706 | dev_priv->fb_tracking.flip_bits); | |
1707 | ||
1708 | return 0; | |
1709 | } | |
1710 | ||
b5e50c3f JB |
1711 | static int i915_fbc_status(struct seq_file *m, void *unused) |
1712 | { | |
9f25d007 | 1713 | struct drm_info_node *node = m->private; |
b5e50c3f | 1714 | struct drm_device *dev = node->minor->dev; |
e277a1f8 | 1715 | struct drm_i915_private *dev_priv = dev->dev_private; |
b5e50c3f | 1716 | |
3a77c4c4 | 1717 | if (!HAS_FBC(dev)) { |
267f0c90 | 1718 | seq_puts(m, "FBC unsupported on this chipset\n"); |
b5e50c3f JB |
1719 | return 0; |
1720 | } | |
1721 | ||
36623ef8 | 1722 | intel_runtime_pm_get(dev_priv); |
25ad93fd | 1723 | mutex_lock(&dev_priv->fbc.lock); |
36623ef8 | 1724 | |
0e631adc | 1725 | if (intel_fbc_is_active(dev_priv)) |
267f0c90 | 1726 | seq_puts(m, "FBC enabled\n"); |
2e8144a5 PZ |
1727 | else |
1728 | seq_printf(m, "FBC disabled: %s\n", | |
bf6189c6 | 1729 | dev_priv->fbc.no_fbc_reason); |
36623ef8 | 1730 | |
31b9df10 PZ |
1731 | if (INTEL_INFO(dev_priv)->gen >= 7) |
1732 | seq_printf(m, "Compressing: %s\n", | |
1733 | yesno(I915_READ(FBC_STATUS2) & | |
1734 | FBC_COMPRESSION_MASK)); | |
1735 | ||
25ad93fd | 1736 | mutex_unlock(&dev_priv->fbc.lock); |
36623ef8 PZ |
1737 | intel_runtime_pm_put(dev_priv); |
1738 | ||
b5e50c3f JB |
1739 | return 0; |
1740 | } | |
1741 | ||
da46f936 RV |
1742 | static int i915_fbc_fc_get(void *data, u64 *val) |
1743 | { | |
1744 | struct drm_device *dev = data; | |
1745 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1746 | ||
1747 | if (INTEL_INFO(dev)->gen < 7 || !HAS_FBC(dev)) | |
1748 | return -ENODEV; | |
1749 | ||
da46f936 | 1750 | *val = dev_priv->fbc.false_color; |
da46f936 RV |
1751 | |
1752 | return 0; | |
1753 | } | |
1754 | ||
1755 | static int i915_fbc_fc_set(void *data, u64 val) | |
1756 | { | |
1757 | struct drm_device *dev = data; | |
1758 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1759 | u32 reg; | |
1760 | ||
1761 | if (INTEL_INFO(dev)->gen < 7 || !HAS_FBC(dev)) | |
1762 | return -ENODEV; | |
1763 | ||
25ad93fd | 1764 | mutex_lock(&dev_priv->fbc.lock); |
da46f936 RV |
1765 | |
1766 | reg = I915_READ(ILK_DPFC_CONTROL); | |
1767 | dev_priv->fbc.false_color = val; | |
1768 | ||
1769 | I915_WRITE(ILK_DPFC_CONTROL, val ? | |
1770 | (reg | FBC_CTL_FALSE_COLOR) : | |
1771 | (reg & ~FBC_CTL_FALSE_COLOR)); | |
1772 | ||
25ad93fd | 1773 | mutex_unlock(&dev_priv->fbc.lock); |
da46f936 RV |
1774 | return 0; |
1775 | } | |
1776 | ||
1777 | DEFINE_SIMPLE_ATTRIBUTE(i915_fbc_fc_fops, | |
1778 | i915_fbc_fc_get, i915_fbc_fc_set, | |
1779 | "%llu\n"); | |
1780 | ||
92d44621 PZ |
1781 | static int i915_ips_status(struct seq_file *m, void *unused) |
1782 | { | |
9f25d007 | 1783 | struct drm_info_node *node = m->private; |
92d44621 PZ |
1784 | struct drm_device *dev = node->minor->dev; |
1785 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1786 | ||
f5adf94e | 1787 | if (!HAS_IPS(dev)) { |
92d44621 PZ |
1788 | seq_puts(m, "not supported\n"); |
1789 | return 0; | |
1790 | } | |
1791 | ||
36623ef8 PZ |
1792 | intel_runtime_pm_get(dev_priv); |
1793 | ||
0eaa53f0 RV |
1794 | seq_printf(m, "Enabled by kernel parameter: %s\n", |
1795 | yesno(i915.enable_ips)); | |
1796 | ||
1797 | if (INTEL_INFO(dev)->gen >= 8) { | |
1798 | seq_puts(m, "Currently: unknown\n"); | |
1799 | } else { | |
1800 | if (I915_READ(IPS_CTL) & IPS_ENABLE) | |
1801 | seq_puts(m, "Currently: enabled\n"); | |
1802 | else | |
1803 | seq_puts(m, "Currently: disabled\n"); | |
1804 | } | |
92d44621 | 1805 | |
36623ef8 PZ |
1806 | intel_runtime_pm_put(dev_priv); |
1807 | ||
92d44621 PZ |
1808 | return 0; |
1809 | } | |
1810 | ||
4a9bef37 JB |
1811 | static int i915_sr_status(struct seq_file *m, void *unused) |
1812 | { | |
9f25d007 | 1813 | struct drm_info_node *node = m->private; |
4a9bef37 | 1814 | struct drm_device *dev = node->minor->dev; |
e277a1f8 | 1815 | struct drm_i915_private *dev_priv = dev->dev_private; |
4a9bef37 JB |
1816 | bool sr_enabled = false; |
1817 | ||
36623ef8 PZ |
1818 | intel_runtime_pm_get(dev_priv); |
1819 | ||
1398261a | 1820 | if (HAS_PCH_SPLIT(dev)) |
5ba2aaaa | 1821 | sr_enabled = I915_READ(WM1_LP_ILK) & WM1_LP_SR_EN; |
77b64555 ACO |
1822 | else if (IS_CRESTLINE(dev) || IS_G4X(dev) || |
1823 | IS_I945G(dev) || IS_I945GM(dev)) | |
4a9bef37 JB |
1824 | sr_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN; |
1825 | else if (IS_I915GM(dev)) | |
1826 | sr_enabled = I915_READ(INSTPM) & INSTPM_SELF_EN; | |
1827 | else if (IS_PINEVIEW(dev)) | |
1828 | sr_enabled = I915_READ(DSPFW3) & PINEVIEW_SELF_REFRESH_EN; | |
666a4537 | 1829 | else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) |
77b64555 | 1830 | sr_enabled = I915_READ(FW_BLC_SELF_VLV) & FW_CSPWRDWNEN; |
4a9bef37 | 1831 | |
36623ef8 PZ |
1832 | intel_runtime_pm_put(dev_priv); |
1833 | ||
5ba2aaaa CW |
1834 | seq_printf(m, "self-refresh: %s\n", |
1835 | sr_enabled ? "enabled" : "disabled"); | |
4a9bef37 JB |
1836 | |
1837 | return 0; | |
1838 | } | |
1839 | ||
7648fa99 JB |
1840 | static int i915_emon_status(struct seq_file *m, void *unused) |
1841 | { | |
9f25d007 | 1842 | struct drm_info_node *node = m->private; |
7648fa99 | 1843 | struct drm_device *dev = node->minor->dev; |
e277a1f8 | 1844 | struct drm_i915_private *dev_priv = dev->dev_private; |
7648fa99 | 1845 | unsigned long temp, chipset, gfx; |
de227ef0 CW |
1846 | int ret; |
1847 | ||
582be6b4 CW |
1848 | if (!IS_GEN5(dev)) |
1849 | return -ENODEV; | |
1850 | ||
de227ef0 CW |
1851 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
1852 | if (ret) | |
1853 | return ret; | |
7648fa99 JB |
1854 | |
1855 | temp = i915_mch_val(dev_priv); | |
1856 | chipset = i915_chipset_val(dev_priv); | |
1857 | gfx = i915_gfx_val(dev_priv); | |
de227ef0 | 1858 | mutex_unlock(&dev->struct_mutex); |
7648fa99 JB |
1859 | |
1860 | seq_printf(m, "GMCH temp: %ld\n", temp); | |
1861 | seq_printf(m, "Chipset power: %ld\n", chipset); | |
1862 | seq_printf(m, "GFX power: %ld\n", gfx); | |
1863 | seq_printf(m, "Total power: %ld\n", chipset + gfx); | |
1864 | ||
1865 | return 0; | |
1866 | } | |
1867 | ||
23b2f8bb JB |
1868 | static int i915_ring_freq_table(struct seq_file *m, void *unused) |
1869 | { | |
9f25d007 | 1870 | struct drm_info_node *node = m->private; |
23b2f8bb | 1871 | struct drm_device *dev = node->minor->dev; |
e277a1f8 | 1872 | struct drm_i915_private *dev_priv = dev->dev_private; |
5bfa0199 | 1873 | int ret = 0; |
23b2f8bb | 1874 | int gpu_freq, ia_freq; |
f936ec34 | 1875 | unsigned int max_gpu_freq, min_gpu_freq; |
23b2f8bb | 1876 | |
97d3308a | 1877 | if (!HAS_CORE_RING_FREQ(dev)) { |
267f0c90 | 1878 | seq_puts(m, "unsupported on this chipset\n"); |
23b2f8bb JB |
1879 | return 0; |
1880 | } | |
1881 | ||
5bfa0199 PZ |
1882 | intel_runtime_pm_get(dev_priv); |
1883 | ||
5c9669ce TR |
1884 | flush_delayed_work(&dev_priv->rps.delayed_resume_work); |
1885 | ||
4fc688ce | 1886 | ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock); |
23b2f8bb | 1887 | if (ret) |
5bfa0199 | 1888 | goto out; |
23b2f8bb | 1889 | |
ef11bdb3 | 1890 | if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) { |
f936ec34 AG |
1891 | /* Convert GT frequency to 50 HZ units */ |
1892 | min_gpu_freq = | |
1893 | dev_priv->rps.min_freq_softlimit / GEN9_FREQ_SCALER; | |
1894 | max_gpu_freq = | |
1895 | dev_priv->rps.max_freq_softlimit / GEN9_FREQ_SCALER; | |
1896 | } else { | |
1897 | min_gpu_freq = dev_priv->rps.min_freq_softlimit; | |
1898 | max_gpu_freq = dev_priv->rps.max_freq_softlimit; | |
1899 | } | |
1900 | ||
267f0c90 | 1901 | seq_puts(m, "GPU freq (MHz)\tEffective CPU freq (MHz)\tEffective Ring freq (MHz)\n"); |
23b2f8bb | 1902 | |
f936ec34 | 1903 | for (gpu_freq = min_gpu_freq; gpu_freq <= max_gpu_freq; gpu_freq++) { |
42c0526c BW |
1904 | ia_freq = gpu_freq; |
1905 | sandybridge_pcode_read(dev_priv, | |
1906 | GEN6_PCODE_READ_MIN_FREQ_TABLE, | |
1907 | &ia_freq); | |
3ebecd07 | 1908 | seq_printf(m, "%d\t\t%d\t\t\t\t%d\n", |
f936ec34 | 1909 | intel_gpu_freq(dev_priv, (gpu_freq * |
ef11bdb3 RV |
1910 | (IS_SKYLAKE(dev) || IS_KABYLAKE(dev) ? |
1911 | GEN9_FREQ_SCALER : 1))), | |
3ebecd07 CW |
1912 | ((ia_freq >> 0) & 0xff) * 100, |
1913 | ((ia_freq >> 8) & 0xff) * 100); | |
23b2f8bb JB |
1914 | } |
1915 | ||
4fc688ce | 1916 | mutex_unlock(&dev_priv->rps.hw_lock); |
23b2f8bb | 1917 | |
5bfa0199 PZ |
1918 | out: |
1919 | intel_runtime_pm_put(dev_priv); | |
1920 | return ret; | |
23b2f8bb JB |
1921 | } |
1922 | ||
44834a67 CW |
1923 | static int i915_opregion(struct seq_file *m, void *unused) |
1924 | { | |
9f25d007 | 1925 | struct drm_info_node *node = m->private; |
44834a67 | 1926 | struct drm_device *dev = node->minor->dev; |
e277a1f8 | 1927 | struct drm_i915_private *dev_priv = dev->dev_private; |
44834a67 CW |
1928 | struct intel_opregion *opregion = &dev_priv->opregion; |
1929 | int ret; | |
1930 | ||
1931 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
1932 | if (ret) | |
0d38f009 | 1933 | goto out; |
44834a67 | 1934 | |
2455a8e4 JN |
1935 | if (opregion->header) |
1936 | seq_write(m, opregion->header, OPREGION_SIZE); | |
44834a67 CW |
1937 | |
1938 | mutex_unlock(&dev->struct_mutex); | |
1939 | ||
0d38f009 | 1940 | out: |
44834a67 CW |
1941 | return 0; |
1942 | } | |
1943 | ||
ada8f955 JN |
1944 | static int i915_vbt(struct seq_file *m, void *unused) |
1945 | { | |
1946 | struct drm_info_node *node = m->private; | |
1947 | struct drm_device *dev = node->minor->dev; | |
1948 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1949 | struct intel_opregion *opregion = &dev_priv->opregion; | |
1950 | ||
1951 | if (opregion->vbt) | |
1952 | seq_write(m, opregion->vbt, opregion->vbt_size); | |
1953 | ||
1954 | return 0; | |
1955 | } | |
1956 | ||
37811fcc CW |
1957 | static int i915_gem_framebuffer_info(struct seq_file *m, void *data) |
1958 | { | |
9f25d007 | 1959 | struct drm_info_node *node = m->private; |
37811fcc | 1960 | struct drm_device *dev = node->minor->dev; |
b13b8402 | 1961 | struct intel_framebuffer *fbdev_fb = NULL; |
3a58ee10 | 1962 | struct drm_framebuffer *drm_fb; |
188c1ab7 CW |
1963 | int ret; |
1964 | ||
1965 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
1966 | if (ret) | |
1967 | return ret; | |
37811fcc | 1968 | |
0695726e | 1969 | #ifdef CONFIG_DRM_FBDEV_EMULATION |
b13b8402 NS |
1970 | if (to_i915(dev)->fbdev) { |
1971 | fbdev_fb = to_intel_framebuffer(to_i915(dev)->fbdev->helper.fb); | |
1972 | ||
1973 | seq_printf(m, "fbcon size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj ", | |
1974 | fbdev_fb->base.width, | |
1975 | fbdev_fb->base.height, | |
1976 | fbdev_fb->base.depth, | |
1977 | fbdev_fb->base.bits_per_pixel, | |
1978 | fbdev_fb->base.modifier[0], | |
747a598f | 1979 | drm_framebuffer_read_refcount(&fbdev_fb->base)); |
b13b8402 NS |
1980 | describe_obj(m, fbdev_fb->obj); |
1981 | seq_putc(m, '\n'); | |
1982 | } | |
4520f53a | 1983 | #endif |
37811fcc | 1984 | |
4b096ac1 | 1985 | mutex_lock(&dev->mode_config.fb_lock); |
3a58ee10 | 1986 | drm_for_each_fb(drm_fb, dev) { |
b13b8402 NS |
1987 | struct intel_framebuffer *fb = to_intel_framebuffer(drm_fb); |
1988 | if (fb == fbdev_fb) | |
37811fcc CW |
1989 | continue; |
1990 | ||
c1ca506d | 1991 | seq_printf(m, "user size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj ", |
37811fcc CW |
1992 | fb->base.width, |
1993 | fb->base.height, | |
1994 | fb->base.depth, | |
623f9783 | 1995 | fb->base.bits_per_pixel, |
c1ca506d | 1996 | fb->base.modifier[0], |
747a598f | 1997 | drm_framebuffer_read_refcount(&fb->base)); |
05394f39 | 1998 | describe_obj(m, fb->obj); |
267f0c90 | 1999 | seq_putc(m, '\n'); |
37811fcc | 2000 | } |
4b096ac1 | 2001 | mutex_unlock(&dev->mode_config.fb_lock); |
188c1ab7 | 2002 | mutex_unlock(&dev->struct_mutex); |
37811fcc CW |
2003 | |
2004 | return 0; | |
2005 | } | |
2006 | ||
c9fe99bd OM |
2007 | static void describe_ctx_ringbuf(struct seq_file *m, |
2008 | struct intel_ringbuffer *ringbuf) | |
2009 | { | |
2010 | seq_printf(m, " (ringbuffer, space: %d, head: %u, tail: %u, last head: %d)", | |
2011 | ringbuf->space, ringbuf->head, ringbuf->tail, | |
2012 | ringbuf->last_retired_head); | |
2013 | } | |
2014 | ||
e76d3630 BW |
2015 | static int i915_context_status(struct seq_file *m, void *unused) |
2016 | { | |
9f25d007 | 2017 | struct drm_info_node *node = m->private; |
e76d3630 | 2018 | struct drm_device *dev = node->minor->dev; |
e277a1f8 | 2019 | struct drm_i915_private *dev_priv = dev->dev_private; |
e2f80391 | 2020 | struct intel_engine_cs *engine; |
e2efd130 | 2021 | struct i915_gem_context *ctx; |
c3232b18 | 2022 | int ret; |
e76d3630 | 2023 | |
f3d28878 | 2024 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
e76d3630 BW |
2025 | if (ret) |
2026 | return ret; | |
2027 | ||
a33afea5 | 2028 | list_for_each_entry(ctx, &dev_priv->context_list, link) { |
5d1808ec | 2029 | seq_printf(m, "HW context %u ", ctx->hw_id); |
d28b99ab CW |
2030 | if (IS_ERR(ctx->file_priv)) { |
2031 | seq_puts(m, "(deleted) "); | |
2032 | } else if (ctx->file_priv) { | |
2033 | struct pid *pid = ctx->file_priv->file->pid; | |
2034 | struct task_struct *task; | |
2035 | ||
2036 | task = get_pid_task(pid, PIDTYPE_PID); | |
2037 | if (task) { | |
2038 | seq_printf(m, "(%s [%d]) ", | |
2039 | task->comm, task->pid); | |
2040 | put_task_struct(task); | |
2041 | } | |
2042 | } else { | |
2043 | seq_puts(m, "(kernel) "); | |
2044 | } | |
2045 | ||
bca44d80 CW |
2046 | seq_putc(m, ctx->remap_slice ? 'R' : 'r'); |
2047 | seq_putc(m, '\n'); | |
c9fe99bd | 2048 | |
bca44d80 CW |
2049 | for_each_engine(engine, dev_priv) { |
2050 | struct intel_context *ce = &ctx->engine[engine->id]; | |
2051 | ||
2052 | seq_printf(m, "%s: ", engine->name); | |
2053 | seq_putc(m, ce->initialised ? 'I' : 'i'); | |
2054 | if (ce->state) | |
2055 | describe_obj(m, ce->state); | |
2056 | if (ce->ringbuf) | |
2057 | describe_ctx_ringbuf(m, ce->ringbuf); | |
c9fe99bd | 2058 | seq_putc(m, '\n'); |
c9fe99bd | 2059 | } |
a33afea5 | 2060 | |
a33afea5 | 2061 | seq_putc(m, '\n'); |
a168c293 BW |
2062 | } |
2063 | ||
f3d28878 | 2064 | mutex_unlock(&dev->struct_mutex); |
e76d3630 BW |
2065 | |
2066 | return 0; | |
2067 | } | |
2068 | ||
064ca1d2 | 2069 | static void i915_dump_lrc_obj(struct seq_file *m, |
e2efd130 | 2070 | struct i915_gem_context *ctx, |
0bc40be8 | 2071 | struct intel_engine_cs *engine) |
064ca1d2 | 2072 | { |
bca44d80 | 2073 | struct drm_i915_gem_object *ctx_obj = ctx->engine[engine->id].state; |
064ca1d2 TD |
2074 | struct page *page; |
2075 | uint32_t *reg_state; | |
2076 | int j; | |
2077 | unsigned long ggtt_offset = 0; | |
2078 | ||
7069b144 CW |
2079 | seq_printf(m, "CONTEXT: %s %u\n", engine->name, ctx->hw_id); |
2080 | ||
064ca1d2 | 2081 | if (ctx_obj == NULL) { |
7069b144 | 2082 | seq_puts(m, "\tNot allocated\n"); |
064ca1d2 TD |
2083 | return; |
2084 | } | |
2085 | ||
064ca1d2 TD |
2086 | if (!i915_gem_obj_ggtt_bound(ctx_obj)) |
2087 | seq_puts(m, "\tNot bound in GGTT\n"); | |
2088 | else | |
2089 | ggtt_offset = i915_gem_obj_ggtt_offset(ctx_obj); | |
2090 | ||
2091 | if (i915_gem_object_get_pages(ctx_obj)) { | |
2092 | seq_puts(m, "\tFailed to get pages for context object\n"); | |
2093 | return; | |
2094 | } | |
2095 | ||
d1675198 | 2096 | page = i915_gem_object_get_page(ctx_obj, LRC_STATE_PN); |
064ca1d2 TD |
2097 | if (!WARN_ON(page == NULL)) { |
2098 | reg_state = kmap_atomic(page); | |
2099 | ||
2100 | for (j = 0; j < 0x600 / sizeof(u32) / 4; j += 4) { | |
2101 | seq_printf(m, "\t[0x%08lx] 0x%08x 0x%08x 0x%08x 0x%08x\n", | |
2102 | ggtt_offset + 4096 + (j * 4), | |
2103 | reg_state[j], reg_state[j + 1], | |
2104 | reg_state[j + 2], reg_state[j + 3]); | |
2105 | } | |
2106 | kunmap_atomic(reg_state); | |
2107 | } | |
2108 | ||
2109 | seq_putc(m, '\n'); | |
2110 | } | |
2111 | ||
c0ab1ae9 BW |
2112 | static int i915_dump_lrc(struct seq_file *m, void *unused) |
2113 | { | |
2114 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
2115 | struct drm_device *dev = node->minor->dev; | |
2116 | struct drm_i915_private *dev_priv = dev->dev_private; | |
e2f80391 | 2117 | struct intel_engine_cs *engine; |
e2efd130 | 2118 | struct i915_gem_context *ctx; |
b4ac5afc | 2119 | int ret; |
c0ab1ae9 BW |
2120 | |
2121 | if (!i915.enable_execlists) { | |
2122 | seq_printf(m, "Logical Ring Contexts are disabled\n"); | |
2123 | return 0; | |
2124 | } | |
2125 | ||
2126 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
2127 | if (ret) | |
2128 | return ret; | |
2129 | ||
e28e404c | 2130 | list_for_each_entry(ctx, &dev_priv->context_list, link) |
24f1d3cc CW |
2131 | for_each_engine(engine, dev_priv) |
2132 | i915_dump_lrc_obj(m, ctx, engine); | |
c0ab1ae9 BW |
2133 | |
2134 | mutex_unlock(&dev->struct_mutex); | |
2135 | ||
2136 | return 0; | |
2137 | } | |
2138 | ||
4ba70e44 OM |
2139 | static int i915_execlists(struct seq_file *m, void *data) |
2140 | { | |
2141 | struct drm_info_node *node = (struct drm_info_node *)m->private; | |
2142 | struct drm_device *dev = node->minor->dev; | |
2143 | struct drm_i915_private *dev_priv = dev->dev_private; | |
e2f80391 | 2144 | struct intel_engine_cs *engine; |
4ba70e44 OM |
2145 | u32 status_pointer; |
2146 | u8 read_pointer; | |
2147 | u8 write_pointer; | |
2148 | u32 status; | |
2149 | u32 ctx_id; | |
2150 | struct list_head *cursor; | |
b4ac5afc | 2151 | int i, ret; |
4ba70e44 OM |
2152 | |
2153 | if (!i915.enable_execlists) { | |
2154 | seq_puts(m, "Logical Ring Contexts are disabled\n"); | |
2155 | return 0; | |
2156 | } | |
2157 | ||
2158 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
2159 | if (ret) | |
2160 | return ret; | |
2161 | ||
fc0412ec MT |
2162 | intel_runtime_pm_get(dev_priv); |
2163 | ||
b4ac5afc | 2164 | for_each_engine(engine, dev_priv) { |
6d3d8274 | 2165 | struct drm_i915_gem_request *head_req = NULL; |
4ba70e44 | 2166 | int count = 0; |
4ba70e44 | 2167 | |
e2f80391 | 2168 | seq_printf(m, "%s\n", engine->name); |
4ba70e44 | 2169 | |
e2f80391 TU |
2170 | status = I915_READ(RING_EXECLIST_STATUS_LO(engine)); |
2171 | ctx_id = I915_READ(RING_EXECLIST_STATUS_HI(engine)); | |
4ba70e44 OM |
2172 | seq_printf(m, "\tExeclist status: 0x%08X, context: %u\n", |
2173 | status, ctx_id); | |
2174 | ||
e2f80391 | 2175 | status_pointer = I915_READ(RING_CONTEXT_STATUS_PTR(engine)); |
4ba70e44 OM |
2176 | seq_printf(m, "\tStatus pointer: 0x%08X\n", status_pointer); |
2177 | ||
e2f80391 | 2178 | read_pointer = engine->next_context_status_buffer; |
5590a5f0 | 2179 | write_pointer = GEN8_CSB_WRITE_PTR(status_pointer); |
4ba70e44 | 2180 | if (read_pointer > write_pointer) |
5590a5f0 | 2181 | write_pointer += GEN8_CSB_ENTRIES; |
4ba70e44 OM |
2182 | seq_printf(m, "\tRead pointer: 0x%08X, write pointer 0x%08X\n", |
2183 | read_pointer, write_pointer); | |
2184 | ||
5590a5f0 | 2185 | for (i = 0; i < GEN8_CSB_ENTRIES; i++) { |
e2f80391 TU |
2186 | status = I915_READ(RING_CONTEXT_STATUS_BUF_LO(engine, i)); |
2187 | ctx_id = I915_READ(RING_CONTEXT_STATUS_BUF_HI(engine, i)); | |
4ba70e44 OM |
2188 | |
2189 | seq_printf(m, "\tStatus buffer %d: 0x%08X, context: %u\n", | |
2190 | i, status, ctx_id); | |
2191 | } | |
2192 | ||
27af5eea | 2193 | spin_lock_bh(&engine->execlist_lock); |
e2f80391 | 2194 | list_for_each(cursor, &engine->execlist_queue) |
4ba70e44 | 2195 | count++; |
e2f80391 TU |
2196 | head_req = list_first_entry_or_null(&engine->execlist_queue, |
2197 | struct drm_i915_gem_request, | |
2198 | execlist_link); | |
27af5eea | 2199 | spin_unlock_bh(&engine->execlist_lock); |
4ba70e44 OM |
2200 | |
2201 | seq_printf(m, "\t%d requests in queue\n", count); | |
2202 | if (head_req) { | |
7069b144 CW |
2203 | seq_printf(m, "\tHead request context: %u\n", |
2204 | head_req->ctx->hw_id); | |
4ba70e44 | 2205 | seq_printf(m, "\tHead request tail: %u\n", |
6d3d8274 | 2206 | head_req->tail); |
4ba70e44 OM |
2207 | } |
2208 | ||
2209 | seq_putc(m, '\n'); | |
2210 | } | |
2211 | ||
fc0412ec | 2212 | intel_runtime_pm_put(dev_priv); |
4ba70e44 OM |
2213 | mutex_unlock(&dev->struct_mutex); |
2214 | ||
2215 | return 0; | |
2216 | } | |
2217 | ||
ea16a3cd DV |
2218 | static const char *swizzle_string(unsigned swizzle) |
2219 | { | |
aee56cff | 2220 | switch (swizzle) { |
ea16a3cd DV |
2221 | case I915_BIT_6_SWIZZLE_NONE: |
2222 | return "none"; | |
2223 | case I915_BIT_6_SWIZZLE_9: | |
2224 | return "bit9"; | |
2225 | case I915_BIT_6_SWIZZLE_9_10: | |
2226 | return "bit9/bit10"; | |
2227 | case I915_BIT_6_SWIZZLE_9_11: | |
2228 | return "bit9/bit11"; | |
2229 | case I915_BIT_6_SWIZZLE_9_10_11: | |
2230 | return "bit9/bit10/bit11"; | |
2231 | case I915_BIT_6_SWIZZLE_9_17: | |
2232 | return "bit9/bit17"; | |
2233 | case I915_BIT_6_SWIZZLE_9_10_17: | |
2234 | return "bit9/bit10/bit17"; | |
2235 | case I915_BIT_6_SWIZZLE_UNKNOWN: | |
8a168ca7 | 2236 | return "unknown"; |
ea16a3cd DV |
2237 | } |
2238 | ||
2239 | return "bug"; | |
2240 | } | |
2241 | ||
2242 | static int i915_swizzle_info(struct seq_file *m, void *data) | |
2243 | { | |
9f25d007 | 2244 | struct drm_info_node *node = m->private; |
ea16a3cd DV |
2245 | struct drm_device *dev = node->minor->dev; |
2246 | struct drm_i915_private *dev_priv = dev->dev_private; | |
22bcfc6a DV |
2247 | int ret; |
2248 | ||
2249 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
2250 | if (ret) | |
2251 | return ret; | |
c8c8fb33 | 2252 | intel_runtime_pm_get(dev_priv); |
ea16a3cd | 2253 | |
ea16a3cd DV |
2254 | seq_printf(m, "bit6 swizzle for X-tiling = %s\n", |
2255 | swizzle_string(dev_priv->mm.bit_6_swizzle_x)); | |
2256 | seq_printf(m, "bit6 swizzle for Y-tiling = %s\n", | |
2257 | swizzle_string(dev_priv->mm.bit_6_swizzle_y)); | |
2258 | ||
2259 | if (IS_GEN3(dev) || IS_GEN4(dev)) { | |
2260 | seq_printf(m, "DDC = 0x%08x\n", | |
2261 | I915_READ(DCC)); | |
656bfa3a DV |
2262 | seq_printf(m, "DDC2 = 0x%08x\n", |
2263 | I915_READ(DCC2)); | |
ea16a3cd DV |
2264 | seq_printf(m, "C0DRB3 = 0x%04x\n", |
2265 | I915_READ16(C0DRB3)); | |
2266 | seq_printf(m, "C1DRB3 = 0x%04x\n", | |
2267 | I915_READ16(C1DRB3)); | |
9d3203e1 | 2268 | } else if (INTEL_INFO(dev)->gen >= 6) { |
3fa7d235 DV |
2269 | seq_printf(m, "MAD_DIMM_C0 = 0x%08x\n", |
2270 | I915_READ(MAD_DIMM_C0)); | |
2271 | seq_printf(m, "MAD_DIMM_C1 = 0x%08x\n", | |
2272 | I915_READ(MAD_DIMM_C1)); | |
2273 | seq_printf(m, "MAD_DIMM_C2 = 0x%08x\n", | |
2274 | I915_READ(MAD_DIMM_C2)); | |
2275 | seq_printf(m, "TILECTL = 0x%08x\n", | |
2276 | I915_READ(TILECTL)); | |
5907f5fb | 2277 | if (INTEL_INFO(dev)->gen >= 8) |
9d3203e1 BW |
2278 | seq_printf(m, "GAMTARBMODE = 0x%08x\n", |
2279 | I915_READ(GAMTARBMODE)); | |
2280 | else | |
2281 | seq_printf(m, "ARB_MODE = 0x%08x\n", | |
2282 | I915_READ(ARB_MODE)); | |
3fa7d235 DV |
2283 | seq_printf(m, "DISP_ARB_CTL = 0x%08x\n", |
2284 | I915_READ(DISP_ARB_CTL)); | |
ea16a3cd | 2285 | } |
656bfa3a DV |
2286 | |
2287 | if (dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES) | |
2288 | seq_puts(m, "L-shaped memory detected\n"); | |
2289 | ||
c8c8fb33 | 2290 | intel_runtime_pm_put(dev_priv); |
ea16a3cd DV |
2291 | mutex_unlock(&dev->struct_mutex); |
2292 | ||
2293 | return 0; | |
2294 | } | |
2295 | ||
1c60fef5 BW |
2296 | static int per_file_ctx(int id, void *ptr, void *data) |
2297 | { | |
e2efd130 | 2298 | struct i915_gem_context *ctx = ptr; |
1c60fef5 | 2299 | struct seq_file *m = data; |
ae6c4806 DV |
2300 | struct i915_hw_ppgtt *ppgtt = ctx->ppgtt; |
2301 | ||
2302 | if (!ppgtt) { | |
2303 | seq_printf(m, " no ppgtt for context %d\n", | |
2304 | ctx->user_handle); | |
2305 | return 0; | |
2306 | } | |
1c60fef5 | 2307 | |
f83d6518 OM |
2308 | if (i915_gem_context_is_default(ctx)) |
2309 | seq_puts(m, " default context:\n"); | |
2310 | else | |
821d66dd | 2311 | seq_printf(m, " context %d:\n", ctx->user_handle); |
1c60fef5 BW |
2312 | ppgtt->debug_dump(ppgtt, m); |
2313 | ||
2314 | return 0; | |
2315 | } | |
2316 | ||
77df6772 | 2317 | static void gen8_ppgtt_info(struct seq_file *m, struct drm_device *dev) |
3cf17fc5 | 2318 | { |
3cf17fc5 | 2319 | struct drm_i915_private *dev_priv = dev->dev_private; |
e2f80391 | 2320 | struct intel_engine_cs *engine; |
77df6772 | 2321 | struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt; |
b4ac5afc | 2322 | int i; |
3cf17fc5 | 2323 | |
77df6772 BW |
2324 | if (!ppgtt) |
2325 | return; | |
2326 | ||
b4ac5afc | 2327 | for_each_engine(engine, dev_priv) { |
e2f80391 | 2328 | seq_printf(m, "%s\n", engine->name); |
77df6772 | 2329 | for (i = 0; i < 4; i++) { |
e2f80391 | 2330 | u64 pdp = I915_READ(GEN8_RING_PDP_UDW(engine, i)); |
77df6772 | 2331 | pdp <<= 32; |
e2f80391 | 2332 | pdp |= I915_READ(GEN8_RING_PDP_LDW(engine, i)); |
a2a5b15c | 2333 | seq_printf(m, "\tPDP%d 0x%016llx\n", i, pdp); |
77df6772 BW |
2334 | } |
2335 | } | |
2336 | } | |
2337 | ||
2338 | static void gen6_ppgtt_info(struct seq_file *m, struct drm_device *dev) | |
2339 | { | |
2340 | struct drm_i915_private *dev_priv = dev->dev_private; | |
e2f80391 | 2341 | struct intel_engine_cs *engine; |
3cf17fc5 | 2342 | |
7e22dbbb | 2343 | if (IS_GEN6(dev_priv)) |
3cf17fc5 DV |
2344 | seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(GFX_MODE)); |
2345 | ||
b4ac5afc | 2346 | for_each_engine(engine, dev_priv) { |
e2f80391 | 2347 | seq_printf(m, "%s\n", engine->name); |
7e22dbbb | 2348 | if (IS_GEN7(dev_priv)) |
e2f80391 TU |
2349 | seq_printf(m, "GFX_MODE: 0x%08x\n", |
2350 | I915_READ(RING_MODE_GEN7(engine))); | |
2351 | seq_printf(m, "PP_DIR_BASE: 0x%08x\n", | |
2352 | I915_READ(RING_PP_DIR_BASE(engine))); | |
2353 | seq_printf(m, "PP_DIR_BASE_READ: 0x%08x\n", | |
2354 | I915_READ(RING_PP_DIR_BASE_READ(engine))); | |
2355 | seq_printf(m, "PP_DIR_DCLV: 0x%08x\n", | |
2356 | I915_READ(RING_PP_DIR_DCLV(engine))); | |
3cf17fc5 DV |
2357 | } |
2358 | if (dev_priv->mm.aliasing_ppgtt) { | |
2359 | struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt; | |
2360 | ||
267f0c90 | 2361 | seq_puts(m, "aliasing PPGTT:\n"); |
44159ddb | 2362 | seq_printf(m, "pd gtt offset: 0x%08x\n", ppgtt->pd.base.ggtt_offset); |
1c60fef5 | 2363 | |
87d60b63 | 2364 | ppgtt->debug_dump(ppgtt, m); |
ae6c4806 | 2365 | } |
1c60fef5 | 2366 | |
3cf17fc5 | 2367 | seq_printf(m, "ECOCHK: 0x%08x\n", I915_READ(GAM_ECOCHK)); |
77df6772 BW |
2368 | } |
2369 | ||
2370 | static int i915_ppgtt_info(struct seq_file *m, void *data) | |
2371 | { | |
9f25d007 | 2372 | struct drm_info_node *node = m->private; |
77df6772 | 2373 | struct drm_device *dev = node->minor->dev; |
c8c8fb33 | 2374 | struct drm_i915_private *dev_priv = dev->dev_private; |
ea91e401 | 2375 | struct drm_file *file; |
77df6772 BW |
2376 | |
2377 | int ret = mutex_lock_interruptible(&dev->struct_mutex); | |
2378 | if (ret) | |
2379 | return ret; | |
c8c8fb33 | 2380 | intel_runtime_pm_get(dev_priv); |
77df6772 BW |
2381 | |
2382 | if (INTEL_INFO(dev)->gen >= 8) | |
2383 | gen8_ppgtt_info(m, dev); | |
2384 | else if (INTEL_INFO(dev)->gen >= 6) | |
2385 | gen6_ppgtt_info(m, dev); | |
2386 | ||
1d2ac403 | 2387 | mutex_lock(&dev->filelist_mutex); |
ea91e401 MT |
2388 | list_for_each_entry_reverse(file, &dev->filelist, lhead) { |
2389 | struct drm_i915_file_private *file_priv = file->driver_priv; | |
7cb5dff8 | 2390 | struct task_struct *task; |
ea91e401 | 2391 | |
7cb5dff8 | 2392 | task = get_pid_task(file->pid, PIDTYPE_PID); |
06812760 DC |
2393 | if (!task) { |
2394 | ret = -ESRCH; | |
2395 | goto out_put; | |
2396 | } | |
7cb5dff8 GT |
2397 | seq_printf(m, "\nproc: %s\n", task->comm); |
2398 | put_task_struct(task); | |
ea91e401 MT |
2399 | idr_for_each(&file_priv->context_idr, per_file_ctx, |
2400 | (void *)(unsigned long)m); | |
2401 | } | |
1d2ac403 | 2402 | mutex_unlock(&dev->filelist_mutex); |
ea91e401 | 2403 | |
06812760 | 2404 | out_put: |
c8c8fb33 | 2405 | intel_runtime_pm_put(dev_priv); |
3cf17fc5 DV |
2406 | mutex_unlock(&dev->struct_mutex); |
2407 | ||
06812760 | 2408 | return ret; |
3cf17fc5 DV |
2409 | } |
2410 | ||
f5a4c67d CW |
2411 | static int count_irq_waiters(struct drm_i915_private *i915) |
2412 | { | |
e2f80391 | 2413 | struct intel_engine_cs *engine; |
f5a4c67d | 2414 | int count = 0; |
f5a4c67d | 2415 | |
b4ac5afc | 2416 | for_each_engine(engine, i915) |
e2f80391 | 2417 | count += engine->irq_refcount; |
f5a4c67d CW |
2418 | |
2419 | return count; | |
2420 | } | |
2421 | ||
1854d5ca CW |
2422 | static int i915_rps_boost_info(struct seq_file *m, void *data) |
2423 | { | |
2424 | struct drm_info_node *node = m->private; | |
2425 | struct drm_device *dev = node->minor->dev; | |
2426 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2427 | struct drm_file *file; | |
1854d5ca | 2428 | |
f5a4c67d CW |
2429 | seq_printf(m, "RPS enabled? %d\n", dev_priv->rps.enabled); |
2430 | seq_printf(m, "GPU busy? %d\n", dev_priv->mm.busy); | |
2431 | seq_printf(m, "CPU waiting? %d\n", count_irq_waiters(dev_priv)); | |
2432 | seq_printf(m, "Frequency requested %d; min hard:%d, soft:%d; max soft:%d, hard:%d\n", | |
2433 | intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq), | |
2434 | intel_gpu_freq(dev_priv, dev_priv->rps.min_freq), | |
2435 | intel_gpu_freq(dev_priv, dev_priv->rps.min_freq_softlimit), | |
2436 | intel_gpu_freq(dev_priv, dev_priv->rps.max_freq_softlimit), | |
2437 | intel_gpu_freq(dev_priv, dev_priv->rps.max_freq)); | |
1d2ac403 DV |
2438 | |
2439 | mutex_lock(&dev->filelist_mutex); | |
8d3afd7d | 2440 | spin_lock(&dev_priv->rps.client_lock); |
1854d5ca CW |
2441 | list_for_each_entry_reverse(file, &dev->filelist, lhead) { |
2442 | struct drm_i915_file_private *file_priv = file->driver_priv; | |
2443 | struct task_struct *task; | |
2444 | ||
2445 | rcu_read_lock(); | |
2446 | task = pid_task(file->pid, PIDTYPE_PID); | |
2447 | seq_printf(m, "%s [%d]: %d boosts%s\n", | |
2448 | task ? task->comm : "<unknown>", | |
2449 | task ? task->pid : -1, | |
2e1b8730 CW |
2450 | file_priv->rps.boosts, |
2451 | list_empty(&file_priv->rps.link) ? "" : ", active"); | |
1854d5ca CW |
2452 | rcu_read_unlock(); |
2453 | } | |
2e1b8730 CW |
2454 | seq_printf(m, "Semaphore boosts: %d%s\n", |
2455 | dev_priv->rps.semaphores.boosts, | |
2456 | list_empty(&dev_priv->rps.semaphores.link) ? "" : ", active"); | |
2457 | seq_printf(m, "MMIO flip boosts: %d%s\n", | |
2458 | dev_priv->rps.mmioflips.boosts, | |
2459 | list_empty(&dev_priv->rps.mmioflips.link) ? "" : ", active"); | |
1854d5ca | 2460 | seq_printf(m, "Kernel boosts: %d\n", dev_priv->rps.boosts); |
8d3afd7d | 2461 | spin_unlock(&dev_priv->rps.client_lock); |
1d2ac403 | 2462 | mutex_unlock(&dev->filelist_mutex); |
1854d5ca | 2463 | |
8d3afd7d | 2464 | return 0; |
1854d5ca CW |
2465 | } |
2466 | ||
63573eb7 BW |
2467 | static int i915_llc(struct seq_file *m, void *data) |
2468 | { | |
9f25d007 | 2469 | struct drm_info_node *node = m->private; |
63573eb7 BW |
2470 | struct drm_device *dev = node->minor->dev; |
2471 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3accaf7e | 2472 | const bool edram = INTEL_GEN(dev_priv) > 8; |
63573eb7 | 2473 | |
63573eb7 | 2474 | seq_printf(m, "LLC: %s\n", yesno(HAS_LLC(dev))); |
3accaf7e MK |
2475 | seq_printf(m, "%s: %lluMB\n", edram ? "eDRAM" : "eLLC", |
2476 | intel_uncore_edram_size(dev_priv)/1024/1024); | |
63573eb7 BW |
2477 | |
2478 | return 0; | |
2479 | } | |
2480 | ||
fdf5d357 AD |
2481 | static int i915_guc_load_status_info(struct seq_file *m, void *data) |
2482 | { | |
2483 | struct drm_info_node *node = m->private; | |
2484 | struct drm_i915_private *dev_priv = node->minor->dev->dev_private; | |
2485 | struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw; | |
2486 | u32 tmp, i; | |
2487 | ||
2d1fe073 | 2488 | if (!HAS_GUC_UCODE(dev_priv)) |
fdf5d357 AD |
2489 | return 0; |
2490 | ||
2491 | seq_printf(m, "GuC firmware status:\n"); | |
2492 | seq_printf(m, "\tpath: %s\n", | |
2493 | guc_fw->guc_fw_path); | |
2494 | seq_printf(m, "\tfetch: %s\n", | |
2495 | intel_guc_fw_status_repr(guc_fw->guc_fw_fetch_status)); | |
2496 | seq_printf(m, "\tload: %s\n", | |
2497 | intel_guc_fw_status_repr(guc_fw->guc_fw_load_status)); | |
2498 | seq_printf(m, "\tversion wanted: %d.%d\n", | |
2499 | guc_fw->guc_fw_major_wanted, guc_fw->guc_fw_minor_wanted); | |
2500 | seq_printf(m, "\tversion found: %d.%d\n", | |
2501 | guc_fw->guc_fw_major_found, guc_fw->guc_fw_minor_found); | |
feda33ef AD |
2502 | seq_printf(m, "\theader: offset is %d; size = %d\n", |
2503 | guc_fw->header_offset, guc_fw->header_size); | |
2504 | seq_printf(m, "\tuCode: offset is %d; size = %d\n", | |
2505 | guc_fw->ucode_offset, guc_fw->ucode_size); | |
2506 | seq_printf(m, "\tRSA: offset is %d; size = %d\n", | |
2507 | guc_fw->rsa_offset, guc_fw->rsa_size); | |
fdf5d357 AD |
2508 | |
2509 | tmp = I915_READ(GUC_STATUS); | |
2510 | ||
2511 | seq_printf(m, "\nGuC status 0x%08x:\n", tmp); | |
2512 | seq_printf(m, "\tBootrom status = 0x%x\n", | |
2513 | (tmp & GS_BOOTROM_MASK) >> GS_BOOTROM_SHIFT); | |
2514 | seq_printf(m, "\tuKernel status = 0x%x\n", | |
2515 | (tmp & GS_UKERNEL_MASK) >> GS_UKERNEL_SHIFT); | |
2516 | seq_printf(m, "\tMIA Core status = 0x%x\n", | |
2517 | (tmp & GS_MIA_MASK) >> GS_MIA_SHIFT); | |
2518 | seq_puts(m, "\nScratch registers:\n"); | |
2519 | for (i = 0; i < 16; i++) | |
2520 | seq_printf(m, "\t%2d: \t0x%x\n", i, I915_READ(SOFT_SCRATCH(i))); | |
2521 | ||
2522 | return 0; | |
2523 | } | |
2524 | ||
8b417c26 DG |
2525 | static void i915_guc_client_info(struct seq_file *m, |
2526 | struct drm_i915_private *dev_priv, | |
2527 | struct i915_guc_client *client) | |
2528 | { | |
e2f80391 | 2529 | struct intel_engine_cs *engine; |
8b417c26 | 2530 | uint64_t tot = 0; |
8b417c26 DG |
2531 | |
2532 | seq_printf(m, "\tPriority %d, GuC ctx index: %u, PD offset 0x%x\n", | |
2533 | client->priority, client->ctx_index, client->proc_desc_offset); | |
2534 | seq_printf(m, "\tDoorbell id %d, offset: 0x%x, cookie 0x%x\n", | |
2535 | client->doorbell_id, client->doorbell_offset, client->cookie); | |
2536 | seq_printf(m, "\tWQ size %d, offset: 0x%x, tail %d\n", | |
2537 | client->wq_size, client->wq_offset, client->wq_tail); | |
2538 | ||
551aaecd | 2539 | seq_printf(m, "\tWork queue full: %u\n", client->no_wq_space); |
8b417c26 DG |
2540 | seq_printf(m, "\tFailed to queue: %u\n", client->q_fail); |
2541 | seq_printf(m, "\tFailed doorbell: %u\n", client->b_fail); | |
2542 | seq_printf(m, "\tLast submission result: %d\n", client->retcode); | |
2543 | ||
b4ac5afc | 2544 | for_each_engine(engine, dev_priv) { |
8b417c26 | 2545 | seq_printf(m, "\tSubmissions: %llu %s\n", |
e2f80391 TU |
2546 | client->submissions[engine->guc_id], |
2547 | engine->name); | |
2548 | tot += client->submissions[engine->guc_id]; | |
8b417c26 DG |
2549 | } |
2550 | seq_printf(m, "\tTotal: %llu\n", tot); | |
2551 | } | |
2552 | ||
2553 | static int i915_guc_info(struct seq_file *m, void *data) | |
2554 | { | |
2555 | struct drm_info_node *node = m->private; | |
2556 | struct drm_device *dev = node->minor->dev; | |
2557 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2558 | struct intel_guc guc; | |
0a0b457f | 2559 | struct i915_guc_client client = {}; |
e2f80391 | 2560 | struct intel_engine_cs *engine; |
8b417c26 DG |
2561 | u64 total = 0; |
2562 | ||
2d1fe073 | 2563 | if (!HAS_GUC_SCHED(dev_priv)) |
8b417c26 DG |
2564 | return 0; |
2565 | ||
5a843307 AD |
2566 | if (mutex_lock_interruptible(&dev->struct_mutex)) |
2567 | return 0; | |
2568 | ||
8b417c26 | 2569 | /* Take a local copy of the GuC data, so we can dump it at leisure */ |
8b417c26 | 2570 | guc = dev_priv->guc; |
5a843307 | 2571 | if (guc.execbuf_client) |
8b417c26 | 2572 | client = *guc.execbuf_client; |
5a843307 AD |
2573 | |
2574 | mutex_unlock(&dev->struct_mutex); | |
8b417c26 DG |
2575 | |
2576 | seq_printf(m, "GuC total action count: %llu\n", guc.action_count); | |
2577 | seq_printf(m, "GuC action failure count: %u\n", guc.action_fail); | |
2578 | seq_printf(m, "GuC last action command: 0x%x\n", guc.action_cmd); | |
2579 | seq_printf(m, "GuC last action status: 0x%x\n", guc.action_status); | |
2580 | seq_printf(m, "GuC last action error code: %d\n", guc.action_err); | |
2581 | ||
2582 | seq_printf(m, "\nGuC submissions:\n"); | |
b4ac5afc | 2583 | for_each_engine(engine, dev_priv) { |
397097b0 | 2584 | seq_printf(m, "\t%-24s: %10llu, last seqno 0x%08x\n", |
e2f80391 TU |
2585 | engine->name, guc.submissions[engine->guc_id], |
2586 | guc.last_seqno[engine->guc_id]); | |
2587 | total += guc.submissions[engine->guc_id]; | |
8b417c26 DG |
2588 | } |
2589 | seq_printf(m, "\t%s: %llu\n", "Total", total); | |
2590 | ||
2591 | seq_printf(m, "\nGuC execbuf client @ %p:\n", guc.execbuf_client); | |
2592 | i915_guc_client_info(m, dev_priv, &client); | |
2593 | ||
2594 | /* Add more as required ... */ | |
2595 | ||
2596 | return 0; | |
2597 | } | |
2598 | ||
4c7e77fc AD |
2599 | static int i915_guc_log_dump(struct seq_file *m, void *data) |
2600 | { | |
2601 | struct drm_info_node *node = m->private; | |
2602 | struct drm_device *dev = node->minor->dev; | |
2603 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2604 | struct drm_i915_gem_object *log_obj = dev_priv->guc.log_obj; | |
2605 | u32 *log; | |
2606 | int i = 0, pg; | |
2607 | ||
2608 | if (!log_obj) | |
2609 | return 0; | |
2610 | ||
2611 | for (pg = 0; pg < log_obj->base.size / PAGE_SIZE; pg++) { | |
2612 | log = kmap_atomic(i915_gem_object_get_page(log_obj, pg)); | |
2613 | ||
2614 | for (i = 0; i < PAGE_SIZE / sizeof(u32); i += 4) | |
2615 | seq_printf(m, "0x%08x 0x%08x 0x%08x 0x%08x\n", | |
2616 | *(log + i), *(log + i + 1), | |
2617 | *(log + i + 2), *(log + i + 3)); | |
2618 | ||
2619 | kunmap_atomic(log); | |
2620 | } | |
2621 | ||
2622 | seq_putc(m, '\n'); | |
2623 | ||
2624 | return 0; | |
2625 | } | |
2626 | ||
e91fd8c6 RV |
2627 | static int i915_edp_psr_status(struct seq_file *m, void *data) |
2628 | { | |
2629 | struct drm_info_node *node = m->private; | |
2630 | struct drm_device *dev = node->minor->dev; | |
2631 | struct drm_i915_private *dev_priv = dev->dev_private; | |
a031d709 | 2632 | u32 psrperf = 0; |
a6cbdb8e RV |
2633 | u32 stat[3]; |
2634 | enum pipe pipe; | |
a031d709 | 2635 | bool enabled = false; |
e91fd8c6 | 2636 | |
3553a8ea DL |
2637 | if (!HAS_PSR(dev)) { |
2638 | seq_puts(m, "PSR not supported\n"); | |
2639 | return 0; | |
2640 | } | |
2641 | ||
c8c8fb33 PZ |
2642 | intel_runtime_pm_get(dev_priv); |
2643 | ||
fa128fa6 | 2644 | mutex_lock(&dev_priv->psr.lock); |
a031d709 RV |
2645 | seq_printf(m, "Sink_Support: %s\n", yesno(dev_priv->psr.sink_support)); |
2646 | seq_printf(m, "Source_OK: %s\n", yesno(dev_priv->psr.source_ok)); | |
2807cf69 | 2647 | seq_printf(m, "Enabled: %s\n", yesno((bool)dev_priv->psr.enabled)); |
5755c78f | 2648 | seq_printf(m, "Active: %s\n", yesno(dev_priv->psr.active)); |
fa128fa6 DV |
2649 | seq_printf(m, "Busy frontbuffer bits: 0x%03x\n", |
2650 | dev_priv->psr.busy_frontbuffer_bits); | |
2651 | seq_printf(m, "Re-enable work scheduled: %s\n", | |
2652 | yesno(work_busy(&dev_priv->psr.work.work))); | |
e91fd8c6 | 2653 | |
3553a8ea | 2654 | if (HAS_DDI(dev)) |
443a389f | 2655 | enabled = I915_READ(EDP_PSR_CTL) & EDP_PSR_ENABLE; |
3553a8ea DL |
2656 | else { |
2657 | for_each_pipe(dev_priv, pipe) { | |
2658 | stat[pipe] = I915_READ(VLV_PSRSTAT(pipe)) & | |
2659 | VLV_EDP_PSR_CURR_STATE_MASK; | |
2660 | if ((stat[pipe] == VLV_EDP_PSR_ACTIVE_NORFB_UP) || | |
2661 | (stat[pipe] == VLV_EDP_PSR_ACTIVE_SF_UPDATE)) | |
2662 | enabled = true; | |
a6cbdb8e RV |
2663 | } |
2664 | } | |
60e5ffe3 RV |
2665 | |
2666 | seq_printf(m, "Main link in standby mode: %s\n", | |
2667 | yesno(dev_priv->psr.link_standby)); | |
2668 | ||
a6cbdb8e RV |
2669 | seq_printf(m, "HW Enabled & Active bit: %s", yesno(enabled)); |
2670 | ||
2671 | if (!HAS_DDI(dev)) | |
2672 | for_each_pipe(dev_priv, pipe) { | |
2673 | if ((stat[pipe] == VLV_EDP_PSR_ACTIVE_NORFB_UP) || | |
2674 | (stat[pipe] == VLV_EDP_PSR_ACTIVE_SF_UPDATE)) | |
2675 | seq_printf(m, " pipe %c", pipe_name(pipe)); | |
2676 | } | |
2677 | seq_puts(m, "\n"); | |
e91fd8c6 | 2678 | |
05eec3c2 RV |
2679 | /* |
2680 | * VLV/CHV PSR has no kind of performance counter | |
2681 | * SKL+ Perf counter is reset to 0 everytime DC state is entered | |
2682 | */ | |
2683 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { | |
443a389f | 2684 | psrperf = I915_READ(EDP_PSR_PERF_CNT) & |
a031d709 | 2685 | EDP_PSR_PERF_CNT_MASK; |
a6cbdb8e RV |
2686 | |
2687 | seq_printf(m, "Performance_Counter: %u\n", psrperf); | |
2688 | } | |
fa128fa6 | 2689 | mutex_unlock(&dev_priv->psr.lock); |
e91fd8c6 | 2690 | |
c8c8fb33 | 2691 | intel_runtime_pm_put(dev_priv); |
e91fd8c6 RV |
2692 | return 0; |
2693 | } | |
2694 | ||
d2e216d0 RV |
2695 | static int i915_sink_crc(struct seq_file *m, void *data) |
2696 | { | |
2697 | struct drm_info_node *node = m->private; | |
2698 | struct drm_device *dev = node->minor->dev; | |
2699 | struct intel_encoder *encoder; | |
2700 | struct intel_connector *connector; | |
2701 | struct intel_dp *intel_dp = NULL; | |
2702 | int ret; | |
2703 | u8 crc[6]; | |
2704 | ||
2705 | drm_modeset_lock_all(dev); | |
aca5e361 | 2706 | for_each_intel_connector(dev, connector) { |
d2e216d0 RV |
2707 | |
2708 | if (connector->base.dpms != DRM_MODE_DPMS_ON) | |
2709 | continue; | |
2710 | ||
b6ae3c7c PZ |
2711 | if (!connector->base.encoder) |
2712 | continue; | |
2713 | ||
d2e216d0 RV |
2714 | encoder = to_intel_encoder(connector->base.encoder); |
2715 | if (encoder->type != INTEL_OUTPUT_EDP) | |
2716 | continue; | |
2717 | ||
2718 | intel_dp = enc_to_intel_dp(&encoder->base); | |
2719 | ||
2720 | ret = intel_dp_sink_crc(intel_dp, crc); | |
2721 | if (ret) | |
2722 | goto out; | |
2723 | ||
2724 | seq_printf(m, "%02x%02x%02x%02x%02x%02x\n", | |
2725 | crc[0], crc[1], crc[2], | |
2726 | crc[3], crc[4], crc[5]); | |
2727 | goto out; | |
2728 | } | |
2729 | ret = -ENODEV; | |
2730 | out: | |
2731 | drm_modeset_unlock_all(dev); | |
2732 | return ret; | |
2733 | } | |
2734 | ||
ec013e7f JB |
2735 | static int i915_energy_uJ(struct seq_file *m, void *data) |
2736 | { | |
2737 | struct drm_info_node *node = m->private; | |
2738 | struct drm_device *dev = node->minor->dev; | |
2739 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2740 | u64 power; | |
2741 | u32 units; | |
2742 | ||
2743 | if (INTEL_INFO(dev)->gen < 6) | |
2744 | return -ENODEV; | |
2745 | ||
36623ef8 PZ |
2746 | intel_runtime_pm_get(dev_priv); |
2747 | ||
ec013e7f JB |
2748 | rdmsrl(MSR_RAPL_POWER_UNIT, power); |
2749 | power = (power & 0x1f00) >> 8; | |
2750 | units = 1000000 / (1 << power); /* convert to uJ */ | |
2751 | power = I915_READ(MCH_SECP_NRG_STTS); | |
2752 | power *= units; | |
2753 | ||
36623ef8 PZ |
2754 | intel_runtime_pm_put(dev_priv); |
2755 | ||
ec013e7f | 2756 | seq_printf(m, "%llu", (long long unsigned)power); |
371db66a PZ |
2757 | |
2758 | return 0; | |
2759 | } | |
2760 | ||
6455c870 | 2761 | static int i915_runtime_pm_status(struct seq_file *m, void *unused) |
371db66a | 2762 | { |
9f25d007 | 2763 | struct drm_info_node *node = m->private; |
371db66a PZ |
2764 | struct drm_device *dev = node->minor->dev; |
2765 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2766 | ||
a156e64d CW |
2767 | if (!HAS_RUNTIME_PM(dev_priv)) |
2768 | seq_puts(m, "Runtime power management not supported\n"); | |
371db66a | 2769 | |
86c4ec0d | 2770 | seq_printf(m, "GPU idle: %s\n", yesno(!dev_priv->mm.busy)); |
371db66a | 2771 | seq_printf(m, "IRQs disabled: %s\n", |
9df7575f | 2772 | yesno(!intel_irqs_enabled(dev_priv))); |
0d804184 | 2773 | #ifdef CONFIG_PM |
a6aaec8b DL |
2774 | seq_printf(m, "Usage count: %d\n", |
2775 | atomic_read(&dev->dev->power.usage_count)); | |
0d804184 CW |
2776 | #else |
2777 | seq_printf(m, "Device Power Management (CONFIG_PM) disabled\n"); | |
2778 | #endif | |
a156e64d CW |
2779 | seq_printf(m, "PCI device power state: %s [%d]\n", |
2780 | pci_power_name(dev_priv->dev->pdev->current_state), | |
2781 | dev_priv->dev->pdev->current_state); | |
371db66a | 2782 | |
ec013e7f JB |
2783 | return 0; |
2784 | } | |
2785 | ||
1da51581 ID |
2786 | static int i915_power_domain_info(struct seq_file *m, void *unused) |
2787 | { | |
9f25d007 | 2788 | struct drm_info_node *node = m->private; |
1da51581 ID |
2789 | struct drm_device *dev = node->minor->dev; |
2790 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2791 | struct i915_power_domains *power_domains = &dev_priv->power_domains; | |
2792 | int i; | |
2793 | ||
2794 | mutex_lock(&power_domains->lock); | |
2795 | ||
2796 | seq_printf(m, "%-25s %s\n", "Power well/domain", "Use count"); | |
2797 | for (i = 0; i < power_domains->power_well_count; i++) { | |
2798 | struct i915_power_well *power_well; | |
2799 | enum intel_display_power_domain power_domain; | |
2800 | ||
2801 | power_well = &power_domains->power_wells[i]; | |
2802 | seq_printf(m, "%-25s %d\n", power_well->name, | |
2803 | power_well->count); | |
2804 | ||
2805 | for (power_domain = 0; power_domain < POWER_DOMAIN_NUM; | |
2806 | power_domain++) { | |
2807 | if (!(BIT(power_domain) & power_well->domains)) | |
2808 | continue; | |
2809 | ||
2810 | seq_printf(m, " %-23s %d\n", | |
9895ad03 | 2811 | intel_display_power_domain_str(power_domain), |
1da51581 ID |
2812 | power_domains->domain_use_count[power_domain]); |
2813 | } | |
2814 | } | |
2815 | ||
2816 | mutex_unlock(&power_domains->lock); | |
2817 | ||
2818 | return 0; | |
2819 | } | |
2820 | ||
b7cec66d DL |
2821 | static int i915_dmc_info(struct seq_file *m, void *unused) |
2822 | { | |
2823 | struct drm_info_node *node = m->private; | |
2824 | struct drm_device *dev = node->minor->dev; | |
2825 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2826 | struct intel_csr *csr; | |
2827 | ||
2828 | if (!HAS_CSR(dev)) { | |
2829 | seq_puts(m, "not supported\n"); | |
2830 | return 0; | |
2831 | } | |
2832 | ||
2833 | csr = &dev_priv->csr; | |
2834 | ||
6fb403de MK |
2835 | intel_runtime_pm_get(dev_priv); |
2836 | ||
b7cec66d DL |
2837 | seq_printf(m, "fw loaded: %s\n", yesno(csr->dmc_payload != NULL)); |
2838 | seq_printf(m, "path: %s\n", csr->fw_path); | |
2839 | ||
2840 | if (!csr->dmc_payload) | |
6fb403de | 2841 | goto out; |
b7cec66d DL |
2842 | |
2843 | seq_printf(m, "version: %d.%d\n", CSR_VERSION_MAJOR(csr->version), | |
2844 | CSR_VERSION_MINOR(csr->version)); | |
2845 | ||
8337206d DL |
2846 | if (IS_SKYLAKE(dev) && csr->version >= CSR_VERSION(1, 6)) { |
2847 | seq_printf(m, "DC3 -> DC5 count: %d\n", | |
2848 | I915_READ(SKL_CSR_DC3_DC5_COUNT)); | |
2849 | seq_printf(m, "DC5 -> DC6 count: %d\n", | |
2850 | I915_READ(SKL_CSR_DC5_DC6_COUNT)); | |
16e11b99 MK |
2851 | } else if (IS_BROXTON(dev) && csr->version >= CSR_VERSION(1, 4)) { |
2852 | seq_printf(m, "DC3 -> DC5 count: %d\n", | |
2853 | I915_READ(BXT_CSR_DC3_DC5_COUNT)); | |
8337206d DL |
2854 | } |
2855 | ||
6fb403de MK |
2856 | out: |
2857 | seq_printf(m, "program base: 0x%08x\n", I915_READ(CSR_PROGRAM(0))); | |
2858 | seq_printf(m, "ssp base: 0x%08x\n", I915_READ(CSR_SSP_BASE)); | |
2859 | seq_printf(m, "htp: 0x%08x\n", I915_READ(CSR_HTP_SKL)); | |
2860 | ||
8337206d DL |
2861 | intel_runtime_pm_put(dev_priv); |
2862 | ||
b7cec66d DL |
2863 | return 0; |
2864 | } | |
2865 | ||
53f5e3ca JB |
2866 | static void intel_seq_print_mode(struct seq_file *m, int tabs, |
2867 | struct drm_display_mode *mode) | |
2868 | { | |
2869 | int i; | |
2870 | ||
2871 | for (i = 0; i < tabs; i++) | |
2872 | seq_putc(m, '\t'); | |
2873 | ||
2874 | seq_printf(m, "id %d:\"%s\" freq %d clock %d hdisp %d hss %d hse %d htot %d vdisp %d vss %d vse %d vtot %d type 0x%x flags 0x%x\n", | |
2875 | mode->base.id, mode->name, | |
2876 | mode->vrefresh, mode->clock, | |
2877 | mode->hdisplay, mode->hsync_start, | |
2878 | mode->hsync_end, mode->htotal, | |
2879 | mode->vdisplay, mode->vsync_start, | |
2880 | mode->vsync_end, mode->vtotal, | |
2881 | mode->type, mode->flags); | |
2882 | } | |
2883 | ||
2884 | static void intel_encoder_info(struct seq_file *m, | |
2885 | struct intel_crtc *intel_crtc, | |
2886 | struct intel_encoder *intel_encoder) | |
2887 | { | |
9f25d007 | 2888 | struct drm_info_node *node = m->private; |
53f5e3ca JB |
2889 | struct drm_device *dev = node->minor->dev; |
2890 | struct drm_crtc *crtc = &intel_crtc->base; | |
2891 | struct intel_connector *intel_connector; | |
2892 | struct drm_encoder *encoder; | |
2893 | ||
2894 | encoder = &intel_encoder->base; | |
2895 | seq_printf(m, "\tencoder %d: type: %s, connectors:\n", | |
8e329a03 | 2896 | encoder->base.id, encoder->name); |
53f5e3ca JB |
2897 | for_each_connector_on_encoder(dev, encoder, intel_connector) { |
2898 | struct drm_connector *connector = &intel_connector->base; | |
2899 | seq_printf(m, "\t\tconnector %d: type: %s, status: %s", | |
2900 | connector->base.id, | |
c23cc417 | 2901 | connector->name, |
53f5e3ca JB |
2902 | drm_get_connector_status_name(connector->status)); |
2903 | if (connector->status == connector_status_connected) { | |
2904 | struct drm_display_mode *mode = &crtc->mode; | |
2905 | seq_printf(m, ", mode:\n"); | |
2906 | intel_seq_print_mode(m, 2, mode); | |
2907 | } else { | |
2908 | seq_putc(m, '\n'); | |
2909 | } | |
2910 | } | |
2911 | } | |
2912 | ||
2913 | static void intel_crtc_info(struct seq_file *m, struct intel_crtc *intel_crtc) | |
2914 | { | |
9f25d007 | 2915 | struct drm_info_node *node = m->private; |
53f5e3ca JB |
2916 | struct drm_device *dev = node->minor->dev; |
2917 | struct drm_crtc *crtc = &intel_crtc->base; | |
2918 | struct intel_encoder *intel_encoder; | |
23a48d53 ML |
2919 | struct drm_plane_state *plane_state = crtc->primary->state; |
2920 | struct drm_framebuffer *fb = plane_state->fb; | |
53f5e3ca | 2921 | |
23a48d53 | 2922 | if (fb) |
5aa8a937 | 2923 | seq_printf(m, "\tfb: %d, pos: %dx%d, size: %dx%d\n", |
23a48d53 ML |
2924 | fb->base.id, plane_state->src_x >> 16, |
2925 | plane_state->src_y >> 16, fb->width, fb->height); | |
5aa8a937 MR |
2926 | else |
2927 | seq_puts(m, "\tprimary plane disabled\n"); | |
53f5e3ca JB |
2928 | for_each_encoder_on_crtc(dev, crtc, intel_encoder) |
2929 | intel_encoder_info(m, intel_crtc, intel_encoder); | |
2930 | } | |
2931 | ||
2932 | static void intel_panel_info(struct seq_file *m, struct intel_panel *panel) | |
2933 | { | |
2934 | struct drm_display_mode *mode = panel->fixed_mode; | |
2935 | ||
2936 | seq_printf(m, "\tfixed mode:\n"); | |
2937 | intel_seq_print_mode(m, 2, mode); | |
2938 | } | |
2939 | ||
2940 | static void intel_dp_info(struct seq_file *m, | |
2941 | struct intel_connector *intel_connector) | |
2942 | { | |
2943 | struct intel_encoder *intel_encoder = intel_connector->encoder; | |
2944 | struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base); | |
2945 | ||
2946 | seq_printf(m, "\tDPCD rev: %x\n", intel_dp->dpcd[DP_DPCD_REV]); | |
742f491d | 2947 | seq_printf(m, "\taudio support: %s\n", yesno(intel_dp->has_audio)); |
53f5e3ca JB |
2948 | if (intel_encoder->type == INTEL_OUTPUT_EDP) |
2949 | intel_panel_info(m, &intel_connector->panel); | |
2950 | } | |
2951 | ||
2952 | static void intel_hdmi_info(struct seq_file *m, | |
2953 | struct intel_connector *intel_connector) | |
2954 | { | |
2955 | struct intel_encoder *intel_encoder = intel_connector->encoder; | |
2956 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&intel_encoder->base); | |
2957 | ||
742f491d | 2958 | seq_printf(m, "\taudio support: %s\n", yesno(intel_hdmi->has_audio)); |
53f5e3ca JB |
2959 | } |
2960 | ||
2961 | static void intel_lvds_info(struct seq_file *m, | |
2962 | struct intel_connector *intel_connector) | |
2963 | { | |
2964 | intel_panel_info(m, &intel_connector->panel); | |
2965 | } | |
2966 | ||
2967 | static void intel_connector_info(struct seq_file *m, | |
2968 | struct drm_connector *connector) | |
2969 | { | |
2970 | struct intel_connector *intel_connector = to_intel_connector(connector); | |
2971 | struct intel_encoder *intel_encoder = intel_connector->encoder; | |
f103fc7d | 2972 | struct drm_display_mode *mode; |
53f5e3ca JB |
2973 | |
2974 | seq_printf(m, "connector %d: type %s, status: %s\n", | |
c23cc417 | 2975 | connector->base.id, connector->name, |
53f5e3ca JB |
2976 | drm_get_connector_status_name(connector->status)); |
2977 | if (connector->status == connector_status_connected) { | |
2978 | seq_printf(m, "\tname: %s\n", connector->display_info.name); | |
2979 | seq_printf(m, "\tphysical dimensions: %dx%dmm\n", | |
2980 | connector->display_info.width_mm, | |
2981 | connector->display_info.height_mm); | |
2982 | seq_printf(m, "\tsubpixel order: %s\n", | |
2983 | drm_get_subpixel_order_name(connector->display_info.subpixel_order)); | |
2984 | seq_printf(m, "\tCEA rev: %d\n", | |
2985 | connector->display_info.cea_rev); | |
2986 | } | |
36cd7444 DA |
2987 | if (intel_encoder) { |
2988 | if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT || | |
2989 | intel_encoder->type == INTEL_OUTPUT_EDP) | |
2990 | intel_dp_info(m, intel_connector); | |
2991 | else if (intel_encoder->type == INTEL_OUTPUT_HDMI) | |
2992 | intel_hdmi_info(m, intel_connector); | |
2993 | else if (intel_encoder->type == INTEL_OUTPUT_LVDS) | |
2994 | intel_lvds_info(m, intel_connector); | |
2995 | } | |
53f5e3ca | 2996 | |
f103fc7d JB |
2997 | seq_printf(m, "\tmodes:\n"); |
2998 | list_for_each_entry(mode, &connector->modes, head) | |
2999 | intel_seq_print_mode(m, 2, mode); | |
53f5e3ca JB |
3000 | } |
3001 | ||
065f2ec2 CW |
3002 | static bool cursor_active(struct drm_device *dev, int pipe) |
3003 | { | |
3004 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3005 | u32 state; | |
3006 | ||
3007 | if (IS_845G(dev) || IS_I865G(dev)) | |
0b87c24e | 3008 | state = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE; |
065f2ec2 | 3009 | else |
5efb3e28 | 3010 | state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE; |
065f2ec2 CW |
3011 | |
3012 | return state; | |
3013 | } | |
3014 | ||
3015 | static bool cursor_position(struct drm_device *dev, int pipe, int *x, int *y) | |
3016 | { | |
3017 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3018 | u32 pos; | |
3019 | ||
5efb3e28 | 3020 | pos = I915_READ(CURPOS(pipe)); |
065f2ec2 CW |
3021 | |
3022 | *x = (pos >> CURSOR_X_SHIFT) & CURSOR_POS_MASK; | |
3023 | if (pos & (CURSOR_POS_SIGN << CURSOR_X_SHIFT)) | |
3024 | *x = -*x; | |
3025 | ||
3026 | *y = (pos >> CURSOR_Y_SHIFT) & CURSOR_POS_MASK; | |
3027 | if (pos & (CURSOR_POS_SIGN << CURSOR_Y_SHIFT)) | |
3028 | *y = -*y; | |
3029 | ||
3030 | return cursor_active(dev, pipe); | |
3031 | } | |
3032 | ||
3abc4e09 RF |
3033 | static const char *plane_type(enum drm_plane_type type) |
3034 | { | |
3035 | switch (type) { | |
3036 | case DRM_PLANE_TYPE_OVERLAY: | |
3037 | return "OVL"; | |
3038 | case DRM_PLANE_TYPE_PRIMARY: | |
3039 | return "PRI"; | |
3040 | case DRM_PLANE_TYPE_CURSOR: | |
3041 | return "CUR"; | |
3042 | /* | |
3043 | * Deliberately omitting default: to generate compiler warnings | |
3044 | * when a new drm_plane_type gets added. | |
3045 | */ | |
3046 | } | |
3047 | ||
3048 | return "unknown"; | |
3049 | } | |
3050 | ||
3051 | static const char *plane_rotation(unsigned int rotation) | |
3052 | { | |
3053 | static char buf[48]; | |
3054 | /* | |
3055 | * According to doc only one DRM_ROTATE_ is allowed but this | |
3056 | * will print them all to visualize if the values are misused | |
3057 | */ | |
3058 | snprintf(buf, sizeof(buf), | |
3059 | "%s%s%s%s%s%s(0x%08x)", | |
3060 | (rotation & BIT(DRM_ROTATE_0)) ? "0 " : "", | |
3061 | (rotation & BIT(DRM_ROTATE_90)) ? "90 " : "", | |
3062 | (rotation & BIT(DRM_ROTATE_180)) ? "180 " : "", | |
3063 | (rotation & BIT(DRM_ROTATE_270)) ? "270 " : "", | |
3064 | (rotation & BIT(DRM_REFLECT_X)) ? "FLIPX " : "", | |
3065 | (rotation & BIT(DRM_REFLECT_Y)) ? "FLIPY " : "", | |
3066 | rotation); | |
3067 | ||
3068 | return buf; | |
3069 | } | |
3070 | ||
3071 | static void intel_plane_info(struct seq_file *m, struct intel_crtc *intel_crtc) | |
3072 | { | |
3073 | struct drm_info_node *node = m->private; | |
3074 | struct drm_device *dev = node->minor->dev; | |
3075 | struct intel_plane *intel_plane; | |
3076 | ||
3077 | for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) { | |
3078 | struct drm_plane_state *state; | |
3079 | struct drm_plane *plane = &intel_plane->base; | |
3080 | ||
3081 | if (!plane->state) { | |
3082 | seq_puts(m, "plane->state is NULL!\n"); | |
3083 | continue; | |
3084 | } | |
3085 | ||
3086 | state = plane->state; | |
3087 | ||
3088 | seq_printf(m, "\t--Plane id %d: type=%s, crtc_pos=%4dx%4d, crtc_size=%4dx%4d, src_pos=%d.%04ux%d.%04u, src_size=%d.%04ux%d.%04u, format=%s, rotation=%s\n", | |
3089 | plane->base.id, | |
3090 | plane_type(intel_plane->base.type), | |
3091 | state->crtc_x, state->crtc_y, | |
3092 | state->crtc_w, state->crtc_h, | |
3093 | (state->src_x >> 16), | |
3094 | ((state->src_x & 0xffff) * 15625) >> 10, | |
3095 | (state->src_y >> 16), | |
3096 | ((state->src_y & 0xffff) * 15625) >> 10, | |
3097 | (state->src_w >> 16), | |
3098 | ((state->src_w & 0xffff) * 15625) >> 10, | |
3099 | (state->src_h >> 16), | |
3100 | ((state->src_h & 0xffff) * 15625) >> 10, | |
3101 | state->fb ? drm_get_format_name(state->fb->pixel_format) : "N/A", | |
3102 | plane_rotation(state->rotation)); | |
3103 | } | |
3104 | } | |
3105 | ||
3106 | static void intel_scaler_info(struct seq_file *m, struct intel_crtc *intel_crtc) | |
3107 | { | |
3108 | struct intel_crtc_state *pipe_config; | |
3109 | int num_scalers = intel_crtc->num_scalers; | |
3110 | int i; | |
3111 | ||
3112 | pipe_config = to_intel_crtc_state(intel_crtc->base.state); | |
3113 | ||
3114 | /* Not all platformas have a scaler */ | |
3115 | if (num_scalers) { | |
3116 | seq_printf(m, "\tnum_scalers=%d, scaler_users=%x scaler_id=%d", | |
3117 | num_scalers, | |
3118 | pipe_config->scaler_state.scaler_users, | |
3119 | pipe_config->scaler_state.scaler_id); | |
3120 | ||
3121 | for (i = 0; i < SKL_NUM_SCALERS; i++) { | |
3122 | struct intel_scaler *sc = | |
3123 | &pipe_config->scaler_state.scalers[i]; | |
3124 | ||
3125 | seq_printf(m, ", scalers[%d]: use=%s, mode=%x", | |
3126 | i, yesno(sc->in_use), sc->mode); | |
3127 | } | |
3128 | seq_puts(m, "\n"); | |
3129 | } else { | |
3130 | seq_puts(m, "\tNo scalers available on this platform\n"); | |
3131 | } | |
3132 | } | |
3133 | ||
53f5e3ca JB |
3134 | static int i915_display_info(struct seq_file *m, void *unused) |
3135 | { | |
9f25d007 | 3136 | struct drm_info_node *node = m->private; |
53f5e3ca | 3137 | struct drm_device *dev = node->minor->dev; |
b0e5ddf3 | 3138 | struct drm_i915_private *dev_priv = dev->dev_private; |
065f2ec2 | 3139 | struct intel_crtc *crtc; |
53f5e3ca JB |
3140 | struct drm_connector *connector; |
3141 | ||
b0e5ddf3 | 3142 | intel_runtime_pm_get(dev_priv); |
53f5e3ca JB |
3143 | drm_modeset_lock_all(dev); |
3144 | seq_printf(m, "CRTC info\n"); | |
3145 | seq_printf(m, "---------\n"); | |
d3fcc808 | 3146 | for_each_intel_crtc(dev, crtc) { |
065f2ec2 | 3147 | bool active; |
f77076c9 | 3148 | struct intel_crtc_state *pipe_config; |
065f2ec2 | 3149 | int x, y; |
53f5e3ca | 3150 | |
f77076c9 ML |
3151 | pipe_config = to_intel_crtc_state(crtc->base.state); |
3152 | ||
3abc4e09 | 3153 | seq_printf(m, "CRTC %d: pipe: %c, active=%s, (size=%dx%d), dither=%s, bpp=%d\n", |
065f2ec2 | 3154 | crtc->base.base.id, pipe_name(crtc->pipe), |
f77076c9 | 3155 | yesno(pipe_config->base.active), |
3abc4e09 RF |
3156 | pipe_config->pipe_src_w, pipe_config->pipe_src_h, |
3157 | yesno(pipe_config->dither), pipe_config->pipe_bpp); | |
3158 | ||
f77076c9 | 3159 | if (pipe_config->base.active) { |
065f2ec2 CW |
3160 | intel_crtc_info(m, crtc); |
3161 | ||
a23dc658 | 3162 | active = cursor_position(dev, crtc->pipe, &x, &y); |
57127efa | 3163 | seq_printf(m, "\tcursor visible? %s, position (%d, %d), size %dx%d, addr 0x%08x, active? %s\n", |
4b0e333e | 3164 | yesno(crtc->cursor_base), |
3dd512fb MR |
3165 | x, y, crtc->base.cursor->state->crtc_w, |
3166 | crtc->base.cursor->state->crtc_h, | |
57127efa | 3167 | crtc->cursor_addr, yesno(active)); |
3abc4e09 RF |
3168 | intel_scaler_info(m, crtc); |
3169 | intel_plane_info(m, crtc); | |
a23dc658 | 3170 | } |
cace841c DV |
3171 | |
3172 | seq_printf(m, "\tunderrun reporting: cpu=%s pch=%s \n", | |
3173 | yesno(!crtc->cpu_fifo_underrun_disabled), | |
3174 | yesno(!crtc->pch_fifo_underrun_disabled)); | |
53f5e3ca JB |
3175 | } |
3176 | ||
3177 | seq_printf(m, "\n"); | |
3178 | seq_printf(m, "Connector info\n"); | |
3179 | seq_printf(m, "--------------\n"); | |
3180 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { | |
3181 | intel_connector_info(m, connector); | |
3182 | } | |
3183 | drm_modeset_unlock_all(dev); | |
b0e5ddf3 | 3184 | intel_runtime_pm_put(dev_priv); |
53f5e3ca JB |
3185 | |
3186 | return 0; | |
3187 | } | |
3188 | ||
e04934cf BW |
3189 | static int i915_semaphore_status(struct seq_file *m, void *unused) |
3190 | { | |
3191 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
3192 | struct drm_device *dev = node->minor->dev; | |
3193 | struct drm_i915_private *dev_priv = dev->dev_private; | |
e2f80391 | 3194 | struct intel_engine_cs *engine; |
e04934cf | 3195 | int num_rings = hweight32(INTEL_INFO(dev)->ring_mask); |
c3232b18 DG |
3196 | enum intel_engine_id id; |
3197 | int j, ret; | |
e04934cf | 3198 | |
c033666a | 3199 | if (!i915_semaphore_is_enabled(dev_priv)) { |
e04934cf BW |
3200 | seq_puts(m, "Semaphores are disabled\n"); |
3201 | return 0; | |
3202 | } | |
3203 | ||
3204 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
3205 | if (ret) | |
3206 | return ret; | |
03872064 | 3207 | intel_runtime_pm_get(dev_priv); |
e04934cf BW |
3208 | |
3209 | if (IS_BROADWELL(dev)) { | |
3210 | struct page *page; | |
3211 | uint64_t *seqno; | |
3212 | ||
3213 | page = i915_gem_object_get_page(dev_priv->semaphore_obj, 0); | |
3214 | ||
3215 | seqno = (uint64_t *)kmap_atomic(page); | |
c3232b18 | 3216 | for_each_engine_id(engine, dev_priv, id) { |
e04934cf BW |
3217 | uint64_t offset; |
3218 | ||
e2f80391 | 3219 | seq_printf(m, "%s\n", engine->name); |
e04934cf BW |
3220 | |
3221 | seq_puts(m, " Last signal:"); | |
3222 | for (j = 0; j < num_rings; j++) { | |
c3232b18 | 3223 | offset = id * I915_NUM_ENGINES + j; |
e04934cf BW |
3224 | seq_printf(m, "0x%08llx (0x%02llx) ", |
3225 | seqno[offset], offset * 8); | |
3226 | } | |
3227 | seq_putc(m, '\n'); | |
3228 | ||
3229 | seq_puts(m, " Last wait: "); | |
3230 | for (j = 0; j < num_rings; j++) { | |
c3232b18 | 3231 | offset = id + (j * I915_NUM_ENGINES); |
e04934cf BW |
3232 | seq_printf(m, "0x%08llx (0x%02llx) ", |
3233 | seqno[offset], offset * 8); | |
3234 | } | |
3235 | seq_putc(m, '\n'); | |
3236 | ||
3237 | } | |
3238 | kunmap_atomic(seqno); | |
3239 | } else { | |
3240 | seq_puts(m, " Last signal:"); | |
b4ac5afc | 3241 | for_each_engine(engine, dev_priv) |
e04934cf BW |
3242 | for (j = 0; j < num_rings; j++) |
3243 | seq_printf(m, "0x%08x\n", | |
e2f80391 | 3244 | I915_READ(engine->semaphore.mbox.signal[j])); |
e04934cf BW |
3245 | seq_putc(m, '\n'); |
3246 | } | |
3247 | ||
3248 | seq_puts(m, "\nSync seqno:\n"); | |
b4ac5afc DG |
3249 | for_each_engine(engine, dev_priv) { |
3250 | for (j = 0; j < num_rings; j++) | |
e2f80391 TU |
3251 | seq_printf(m, " 0x%08x ", |
3252 | engine->semaphore.sync_seqno[j]); | |
e04934cf BW |
3253 | seq_putc(m, '\n'); |
3254 | } | |
3255 | seq_putc(m, '\n'); | |
3256 | ||
03872064 | 3257 | intel_runtime_pm_put(dev_priv); |
e04934cf BW |
3258 | mutex_unlock(&dev->struct_mutex); |
3259 | return 0; | |
3260 | } | |
3261 | ||
728e29d7 DV |
3262 | static int i915_shared_dplls_info(struct seq_file *m, void *unused) |
3263 | { | |
3264 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
3265 | struct drm_device *dev = node->minor->dev; | |
3266 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3267 | int i; | |
3268 | ||
3269 | drm_modeset_lock_all(dev); | |
3270 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { | |
3271 | struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; | |
3272 | ||
3273 | seq_printf(m, "DPLL%i: %s, id: %i\n", i, pll->name, pll->id); | |
2dd66ebd ML |
3274 | seq_printf(m, " crtc_mask: 0x%08x, active: 0x%x, on: %s\n", |
3275 | pll->config.crtc_mask, pll->active_mask, yesno(pll->on)); | |
728e29d7 | 3276 | seq_printf(m, " tracked hardware state:\n"); |
3e369b76 ACO |
3277 | seq_printf(m, " dpll: 0x%08x\n", pll->config.hw_state.dpll); |
3278 | seq_printf(m, " dpll_md: 0x%08x\n", | |
3279 | pll->config.hw_state.dpll_md); | |
3280 | seq_printf(m, " fp0: 0x%08x\n", pll->config.hw_state.fp0); | |
3281 | seq_printf(m, " fp1: 0x%08x\n", pll->config.hw_state.fp1); | |
3282 | seq_printf(m, " wrpll: 0x%08x\n", pll->config.hw_state.wrpll); | |
728e29d7 DV |
3283 | } |
3284 | drm_modeset_unlock_all(dev); | |
3285 | ||
3286 | return 0; | |
3287 | } | |
3288 | ||
1ed1ef9d | 3289 | static int i915_wa_registers(struct seq_file *m, void *unused) |
888b5995 AS |
3290 | { |
3291 | int i; | |
3292 | int ret; | |
e2f80391 | 3293 | struct intel_engine_cs *engine; |
888b5995 AS |
3294 | struct drm_info_node *node = (struct drm_info_node *) m->private; |
3295 | struct drm_device *dev = node->minor->dev; | |
3296 | struct drm_i915_private *dev_priv = dev->dev_private; | |
33136b06 | 3297 | struct i915_workarounds *workarounds = &dev_priv->workarounds; |
c3232b18 | 3298 | enum intel_engine_id id; |
888b5995 | 3299 | |
888b5995 AS |
3300 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
3301 | if (ret) | |
3302 | return ret; | |
3303 | ||
3304 | intel_runtime_pm_get(dev_priv); | |
3305 | ||
33136b06 | 3306 | seq_printf(m, "Workarounds applied: %d\n", workarounds->count); |
c3232b18 | 3307 | for_each_engine_id(engine, dev_priv, id) |
33136b06 | 3308 | seq_printf(m, "HW whitelist count for %s: %d\n", |
c3232b18 | 3309 | engine->name, workarounds->hw_whitelist_count[id]); |
33136b06 | 3310 | for (i = 0; i < workarounds->count; ++i) { |
f0f59a00 VS |
3311 | i915_reg_t addr; |
3312 | u32 mask, value, read; | |
2fa60f6d | 3313 | bool ok; |
888b5995 | 3314 | |
33136b06 AS |
3315 | addr = workarounds->reg[i].addr; |
3316 | mask = workarounds->reg[i].mask; | |
3317 | value = workarounds->reg[i].value; | |
2fa60f6d MK |
3318 | read = I915_READ(addr); |
3319 | ok = (value & mask) == (read & mask); | |
3320 | seq_printf(m, "0x%X: 0x%08X, mask: 0x%08X, read: 0x%08x, status: %s\n", | |
f0f59a00 | 3321 | i915_mmio_reg_offset(addr), value, mask, read, ok ? "OK" : "FAIL"); |
888b5995 AS |
3322 | } |
3323 | ||
3324 | intel_runtime_pm_put(dev_priv); | |
3325 | mutex_unlock(&dev->struct_mutex); | |
3326 | ||
3327 | return 0; | |
3328 | } | |
3329 | ||
c5511e44 DL |
3330 | static int i915_ddb_info(struct seq_file *m, void *unused) |
3331 | { | |
3332 | struct drm_info_node *node = m->private; | |
3333 | struct drm_device *dev = node->minor->dev; | |
3334 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3335 | struct skl_ddb_allocation *ddb; | |
3336 | struct skl_ddb_entry *entry; | |
3337 | enum pipe pipe; | |
3338 | int plane; | |
3339 | ||
2fcffe19 DL |
3340 | if (INTEL_INFO(dev)->gen < 9) |
3341 | return 0; | |
3342 | ||
c5511e44 DL |
3343 | drm_modeset_lock_all(dev); |
3344 | ||
3345 | ddb = &dev_priv->wm.skl_hw.ddb; | |
3346 | ||
3347 | seq_printf(m, "%-15s%8s%8s%8s\n", "", "Start", "End", "Size"); | |
3348 | ||
3349 | for_each_pipe(dev_priv, pipe) { | |
3350 | seq_printf(m, "Pipe %c\n", pipe_name(pipe)); | |
3351 | ||
dd740780 | 3352 | for_each_plane(dev_priv, pipe, plane) { |
c5511e44 DL |
3353 | entry = &ddb->plane[pipe][plane]; |
3354 | seq_printf(m, " Plane%-8d%8u%8u%8u\n", plane + 1, | |
3355 | entry->start, entry->end, | |
3356 | skl_ddb_entry_size(entry)); | |
3357 | } | |
3358 | ||
4969d33e | 3359 | entry = &ddb->plane[pipe][PLANE_CURSOR]; |
c5511e44 DL |
3360 | seq_printf(m, " %-13s%8u%8u%8u\n", "Cursor", entry->start, |
3361 | entry->end, skl_ddb_entry_size(entry)); | |
3362 | } | |
3363 | ||
3364 | drm_modeset_unlock_all(dev); | |
3365 | ||
3366 | return 0; | |
3367 | } | |
3368 | ||
a54746e3 VK |
3369 | static void drrs_status_per_crtc(struct seq_file *m, |
3370 | struct drm_device *dev, struct intel_crtc *intel_crtc) | |
3371 | { | |
3372 | struct intel_encoder *intel_encoder; | |
3373 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3374 | struct i915_drrs *drrs = &dev_priv->drrs; | |
3375 | int vrefresh = 0; | |
3376 | ||
3377 | for_each_encoder_on_crtc(dev, &intel_crtc->base, intel_encoder) { | |
3378 | /* Encoder connected on this CRTC */ | |
3379 | switch (intel_encoder->type) { | |
3380 | case INTEL_OUTPUT_EDP: | |
3381 | seq_puts(m, "eDP:\n"); | |
3382 | break; | |
3383 | case INTEL_OUTPUT_DSI: | |
3384 | seq_puts(m, "DSI:\n"); | |
3385 | break; | |
3386 | case INTEL_OUTPUT_HDMI: | |
3387 | seq_puts(m, "HDMI:\n"); | |
3388 | break; | |
3389 | case INTEL_OUTPUT_DISPLAYPORT: | |
3390 | seq_puts(m, "DP:\n"); | |
3391 | break; | |
3392 | default: | |
3393 | seq_printf(m, "Other encoder (id=%d).\n", | |
3394 | intel_encoder->type); | |
3395 | return; | |
3396 | } | |
3397 | } | |
3398 | ||
3399 | if (dev_priv->vbt.drrs_type == STATIC_DRRS_SUPPORT) | |
3400 | seq_puts(m, "\tVBT: DRRS_type: Static"); | |
3401 | else if (dev_priv->vbt.drrs_type == SEAMLESS_DRRS_SUPPORT) | |
3402 | seq_puts(m, "\tVBT: DRRS_type: Seamless"); | |
3403 | else if (dev_priv->vbt.drrs_type == DRRS_NOT_SUPPORTED) | |
3404 | seq_puts(m, "\tVBT: DRRS_type: None"); | |
3405 | else | |
3406 | seq_puts(m, "\tVBT: DRRS_type: FIXME: Unrecognized Value"); | |
3407 | ||
3408 | seq_puts(m, "\n\n"); | |
3409 | ||
f77076c9 | 3410 | if (to_intel_crtc_state(intel_crtc->base.state)->has_drrs) { |
a54746e3 VK |
3411 | struct intel_panel *panel; |
3412 | ||
3413 | mutex_lock(&drrs->mutex); | |
3414 | /* DRRS Supported */ | |
3415 | seq_puts(m, "\tDRRS Supported: Yes\n"); | |
3416 | ||
3417 | /* disable_drrs() will make drrs->dp NULL */ | |
3418 | if (!drrs->dp) { | |
3419 | seq_puts(m, "Idleness DRRS: Disabled"); | |
3420 | mutex_unlock(&drrs->mutex); | |
3421 | return; | |
3422 | } | |
3423 | ||
3424 | panel = &drrs->dp->attached_connector->panel; | |
3425 | seq_printf(m, "\t\tBusy_frontbuffer_bits: 0x%X", | |
3426 | drrs->busy_frontbuffer_bits); | |
3427 | ||
3428 | seq_puts(m, "\n\t\t"); | |
3429 | if (drrs->refresh_rate_type == DRRS_HIGH_RR) { | |
3430 | seq_puts(m, "DRRS_State: DRRS_HIGH_RR\n"); | |
3431 | vrefresh = panel->fixed_mode->vrefresh; | |
3432 | } else if (drrs->refresh_rate_type == DRRS_LOW_RR) { | |
3433 | seq_puts(m, "DRRS_State: DRRS_LOW_RR\n"); | |
3434 | vrefresh = panel->downclock_mode->vrefresh; | |
3435 | } else { | |
3436 | seq_printf(m, "DRRS_State: Unknown(%d)\n", | |
3437 | drrs->refresh_rate_type); | |
3438 | mutex_unlock(&drrs->mutex); | |
3439 | return; | |
3440 | } | |
3441 | seq_printf(m, "\t\tVrefresh: %d", vrefresh); | |
3442 | ||
3443 | seq_puts(m, "\n\t\t"); | |
3444 | mutex_unlock(&drrs->mutex); | |
3445 | } else { | |
3446 | /* DRRS not supported. Print the VBT parameter*/ | |
3447 | seq_puts(m, "\tDRRS Supported : No"); | |
3448 | } | |
3449 | seq_puts(m, "\n"); | |
3450 | } | |
3451 | ||
3452 | static int i915_drrs_status(struct seq_file *m, void *unused) | |
3453 | { | |
3454 | struct drm_info_node *node = m->private; | |
3455 | struct drm_device *dev = node->minor->dev; | |
3456 | struct intel_crtc *intel_crtc; | |
3457 | int active_crtc_cnt = 0; | |
3458 | ||
3459 | for_each_intel_crtc(dev, intel_crtc) { | |
3460 | drm_modeset_lock(&intel_crtc->base.mutex, NULL); | |
3461 | ||
f77076c9 | 3462 | if (intel_crtc->base.state->active) { |
a54746e3 VK |
3463 | active_crtc_cnt++; |
3464 | seq_printf(m, "\nCRTC %d: ", active_crtc_cnt); | |
3465 | ||
3466 | drrs_status_per_crtc(m, dev, intel_crtc); | |
3467 | } | |
3468 | ||
3469 | drm_modeset_unlock(&intel_crtc->base.mutex); | |
3470 | } | |
3471 | ||
3472 | if (!active_crtc_cnt) | |
3473 | seq_puts(m, "No active crtc found\n"); | |
3474 | ||
3475 | return 0; | |
3476 | } | |
3477 | ||
07144428 DL |
3478 | struct pipe_crc_info { |
3479 | const char *name; | |
3480 | struct drm_device *dev; | |
3481 | enum pipe pipe; | |
3482 | }; | |
3483 | ||
11bed958 DA |
3484 | static int i915_dp_mst_info(struct seq_file *m, void *unused) |
3485 | { | |
3486 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
3487 | struct drm_device *dev = node->minor->dev; | |
3488 | struct drm_encoder *encoder; | |
3489 | struct intel_encoder *intel_encoder; | |
3490 | struct intel_digital_port *intel_dig_port; | |
3491 | drm_modeset_lock_all(dev); | |
3492 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { | |
3493 | intel_encoder = to_intel_encoder(encoder); | |
3494 | if (intel_encoder->type != INTEL_OUTPUT_DISPLAYPORT) | |
3495 | continue; | |
3496 | intel_dig_port = enc_to_dig_port(encoder); | |
3497 | if (!intel_dig_port->dp.can_mst) | |
3498 | continue; | |
40ae80cc JB |
3499 | seq_printf(m, "MST Source Port %c\n", |
3500 | port_name(intel_dig_port->port)); | |
11bed958 DA |
3501 | drm_dp_mst_dump_topology(m, &intel_dig_port->dp.mst_mgr); |
3502 | } | |
3503 | drm_modeset_unlock_all(dev); | |
3504 | return 0; | |
3505 | } | |
3506 | ||
07144428 DL |
3507 | static int i915_pipe_crc_open(struct inode *inode, struct file *filep) |
3508 | { | |
be5c7a90 DL |
3509 | struct pipe_crc_info *info = inode->i_private; |
3510 | struct drm_i915_private *dev_priv = info->dev->dev_private; | |
3511 | struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe]; | |
3512 | ||
7eb1c496 DV |
3513 | if (info->pipe >= INTEL_INFO(info->dev)->num_pipes) |
3514 | return -ENODEV; | |
3515 | ||
d538bbdf DL |
3516 | spin_lock_irq(&pipe_crc->lock); |
3517 | ||
3518 | if (pipe_crc->opened) { | |
3519 | spin_unlock_irq(&pipe_crc->lock); | |
be5c7a90 DL |
3520 | return -EBUSY; /* already open */ |
3521 | } | |
3522 | ||
d538bbdf | 3523 | pipe_crc->opened = true; |
07144428 DL |
3524 | filep->private_data = inode->i_private; |
3525 | ||
d538bbdf DL |
3526 | spin_unlock_irq(&pipe_crc->lock); |
3527 | ||
07144428 DL |
3528 | return 0; |
3529 | } | |
3530 | ||
3531 | static int i915_pipe_crc_release(struct inode *inode, struct file *filep) | |
3532 | { | |
be5c7a90 DL |
3533 | struct pipe_crc_info *info = inode->i_private; |
3534 | struct drm_i915_private *dev_priv = info->dev->dev_private; | |
3535 | struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe]; | |
3536 | ||
d538bbdf DL |
3537 | spin_lock_irq(&pipe_crc->lock); |
3538 | pipe_crc->opened = false; | |
3539 | spin_unlock_irq(&pipe_crc->lock); | |
be5c7a90 | 3540 | |
07144428 DL |
3541 | return 0; |
3542 | } | |
3543 | ||
3544 | /* (6 fields, 8 chars each, space separated (5) + '\n') */ | |
3545 | #define PIPE_CRC_LINE_LEN (6 * 8 + 5 + 1) | |
3546 | /* account for \'0' */ | |
3547 | #define PIPE_CRC_BUFFER_LEN (PIPE_CRC_LINE_LEN + 1) | |
3548 | ||
3549 | static int pipe_crc_data_count(struct intel_pipe_crc *pipe_crc) | |
8bf1e9f1 | 3550 | { |
d538bbdf DL |
3551 | assert_spin_locked(&pipe_crc->lock); |
3552 | return CIRC_CNT(pipe_crc->head, pipe_crc->tail, | |
3553 | INTEL_PIPE_CRC_ENTRIES_NR); | |
07144428 DL |
3554 | } |
3555 | ||
3556 | static ssize_t | |
3557 | i915_pipe_crc_read(struct file *filep, char __user *user_buf, size_t count, | |
3558 | loff_t *pos) | |
3559 | { | |
3560 | struct pipe_crc_info *info = filep->private_data; | |
3561 | struct drm_device *dev = info->dev; | |
3562 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3563 | struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe]; | |
3564 | char buf[PIPE_CRC_BUFFER_LEN]; | |
9ad6d99f | 3565 | int n_entries; |
07144428 DL |
3566 | ssize_t bytes_read; |
3567 | ||
3568 | /* | |
3569 | * Don't allow user space to provide buffers not big enough to hold | |
3570 | * a line of data. | |
3571 | */ | |
3572 | if (count < PIPE_CRC_LINE_LEN) | |
3573 | return -EINVAL; | |
3574 | ||
3575 | if (pipe_crc->source == INTEL_PIPE_CRC_SOURCE_NONE) | |
8bf1e9f1 | 3576 | return 0; |
07144428 DL |
3577 | |
3578 | /* nothing to read */ | |
d538bbdf | 3579 | spin_lock_irq(&pipe_crc->lock); |
07144428 | 3580 | while (pipe_crc_data_count(pipe_crc) == 0) { |
d538bbdf DL |
3581 | int ret; |
3582 | ||
3583 | if (filep->f_flags & O_NONBLOCK) { | |
3584 | spin_unlock_irq(&pipe_crc->lock); | |
07144428 | 3585 | return -EAGAIN; |
d538bbdf | 3586 | } |
07144428 | 3587 | |
d538bbdf DL |
3588 | ret = wait_event_interruptible_lock_irq(pipe_crc->wq, |
3589 | pipe_crc_data_count(pipe_crc), pipe_crc->lock); | |
3590 | if (ret) { | |
3591 | spin_unlock_irq(&pipe_crc->lock); | |
3592 | return ret; | |
3593 | } | |
8bf1e9f1 SH |
3594 | } |
3595 | ||
07144428 | 3596 | /* We now have one or more entries to read */ |
9ad6d99f | 3597 | n_entries = count / PIPE_CRC_LINE_LEN; |
d538bbdf | 3598 | |
07144428 | 3599 | bytes_read = 0; |
9ad6d99f VS |
3600 | while (n_entries > 0) { |
3601 | struct intel_pipe_crc_entry *entry = | |
3602 | &pipe_crc->entries[pipe_crc->tail]; | |
07144428 | 3603 | int ret; |
8bf1e9f1 | 3604 | |
9ad6d99f VS |
3605 | if (CIRC_CNT(pipe_crc->head, pipe_crc->tail, |
3606 | INTEL_PIPE_CRC_ENTRIES_NR) < 1) | |
3607 | break; | |
3608 | ||
3609 | BUILD_BUG_ON_NOT_POWER_OF_2(INTEL_PIPE_CRC_ENTRIES_NR); | |
3610 | pipe_crc->tail = (pipe_crc->tail + 1) & (INTEL_PIPE_CRC_ENTRIES_NR - 1); | |
3611 | ||
07144428 DL |
3612 | bytes_read += snprintf(buf, PIPE_CRC_BUFFER_LEN, |
3613 | "%8u %8x %8x %8x %8x %8x\n", | |
3614 | entry->frame, entry->crc[0], | |
3615 | entry->crc[1], entry->crc[2], | |
3616 | entry->crc[3], entry->crc[4]); | |
3617 | ||
9ad6d99f VS |
3618 | spin_unlock_irq(&pipe_crc->lock); |
3619 | ||
3620 | ret = copy_to_user(user_buf, buf, PIPE_CRC_LINE_LEN); | |
07144428 DL |
3621 | if (ret == PIPE_CRC_LINE_LEN) |
3622 | return -EFAULT; | |
b2c88f5b | 3623 | |
9ad6d99f VS |
3624 | user_buf += PIPE_CRC_LINE_LEN; |
3625 | n_entries--; | |
3626 | ||
3627 | spin_lock_irq(&pipe_crc->lock); | |
3628 | } | |
8bf1e9f1 | 3629 | |
d538bbdf DL |
3630 | spin_unlock_irq(&pipe_crc->lock); |
3631 | ||
07144428 DL |
3632 | return bytes_read; |
3633 | } | |
3634 | ||
3635 | static const struct file_operations i915_pipe_crc_fops = { | |
3636 | .owner = THIS_MODULE, | |
3637 | .open = i915_pipe_crc_open, | |
3638 | .read = i915_pipe_crc_read, | |
3639 | .release = i915_pipe_crc_release, | |
3640 | }; | |
3641 | ||
3642 | static struct pipe_crc_info i915_pipe_crc_data[I915_MAX_PIPES] = { | |
3643 | { | |
3644 | .name = "i915_pipe_A_crc", | |
3645 | .pipe = PIPE_A, | |
3646 | }, | |
3647 | { | |
3648 | .name = "i915_pipe_B_crc", | |
3649 | .pipe = PIPE_B, | |
3650 | }, | |
3651 | { | |
3652 | .name = "i915_pipe_C_crc", | |
3653 | .pipe = PIPE_C, | |
3654 | }, | |
3655 | }; | |
3656 | ||
3657 | static int i915_pipe_crc_create(struct dentry *root, struct drm_minor *minor, | |
3658 | enum pipe pipe) | |
3659 | { | |
3660 | struct drm_device *dev = minor->dev; | |
3661 | struct dentry *ent; | |
3662 | struct pipe_crc_info *info = &i915_pipe_crc_data[pipe]; | |
3663 | ||
3664 | info->dev = dev; | |
3665 | ent = debugfs_create_file(info->name, S_IRUGO, root, info, | |
3666 | &i915_pipe_crc_fops); | |
f3c5fe97 WY |
3667 | if (!ent) |
3668 | return -ENOMEM; | |
07144428 DL |
3669 | |
3670 | return drm_add_fake_info_node(minor, ent, info); | |
8bf1e9f1 SH |
3671 | } |
3672 | ||
e8dfcf78 | 3673 | static const char * const pipe_crc_sources[] = { |
926321d5 DV |
3674 | "none", |
3675 | "plane1", | |
3676 | "plane2", | |
3677 | "pf", | |
5b3a856b | 3678 | "pipe", |
3d099a05 DV |
3679 | "TV", |
3680 | "DP-B", | |
3681 | "DP-C", | |
3682 | "DP-D", | |
46a19188 | 3683 | "auto", |
926321d5 DV |
3684 | }; |
3685 | ||
3686 | static const char *pipe_crc_source_name(enum intel_pipe_crc_source source) | |
3687 | { | |
3688 | BUILD_BUG_ON(ARRAY_SIZE(pipe_crc_sources) != INTEL_PIPE_CRC_SOURCE_MAX); | |
3689 | return pipe_crc_sources[source]; | |
3690 | } | |
3691 | ||
bd9db02f | 3692 | static int display_crc_ctl_show(struct seq_file *m, void *data) |
926321d5 DV |
3693 | { |
3694 | struct drm_device *dev = m->private; | |
3695 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3696 | int i; | |
3697 | ||
3698 | for (i = 0; i < I915_MAX_PIPES; i++) | |
3699 | seq_printf(m, "%c %s\n", pipe_name(i), | |
3700 | pipe_crc_source_name(dev_priv->pipe_crc[i].source)); | |
3701 | ||
3702 | return 0; | |
3703 | } | |
3704 | ||
bd9db02f | 3705 | static int display_crc_ctl_open(struct inode *inode, struct file *file) |
926321d5 DV |
3706 | { |
3707 | struct drm_device *dev = inode->i_private; | |
3708 | ||
bd9db02f | 3709 | return single_open(file, display_crc_ctl_show, dev); |
926321d5 DV |
3710 | } |
3711 | ||
46a19188 | 3712 | static int i8xx_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source, |
52f843f6 DV |
3713 | uint32_t *val) |
3714 | { | |
46a19188 DV |
3715 | if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) |
3716 | *source = INTEL_PIPE_CRC_SOURCE_PIPE; | |
3717 | ||
3718 | switch (*source) { | |
52f843f6 DV |
3719 | case INTEL_PIPE_CRC_SOURCE_PIPE: |
3720 | *val = PIPE_CRC_ENABLE | PIPE_CRC_INCLUDE_BORDER_I8XX; | |
3721 | break; | |
3722 | case INTEL_PIPE_CRC_SOURCE_NONE: | |
3723 | *val = 0; | |
3724 | break; | |
3725 | default: | |
3726 | return -EINVAL; | |
3727 | } | |
3728 | ||
3729 | return 0; | |
3730 | } | |
3731 | ||
46a19188 DV |
3732 | static int i9xx_pipe_crc_auto_source(struct drm_device *dev, enum pipe pipe, |
3733 | enum intel_pipe_crc_source *source) | |
3734 | { | |
3735 | struct intel_encoder *encoder; | |
3736 | struct intel_crtc *crtc; | |
26756809 | 3737 | struct intel_digital_port *dig_port; |
46a19188 DV |
3738 | int ret = 0; |
3739 | ||
3740 | *source = INTEL_PIPE_CRC_SOURCE_PIPE; | |
3741 | ||
6e9f798d | 3742 | drm_modeset_lock_all(dev); |
b2784e15 | 3743 | for_each_intel_encoder(dev, encoder) { |
46a19188 DV |
3744 | if (!encoder->base.crtc) |
3745 | continue; | |
3746 | ||
3747 | crtc = to_intel_crtc(encoder->base.crtc); | |
3748 | ||
3749 | if (crtc->pipe != pipe) | |
3750 | continue; | |
3751 | ||
3752 | switch (encoder->type) { | |
3753 | case INTEL_OUTPUT_TVOUT: | |
3754 | *source = INTEL_PIPE_CRC_SOURCE_TV; | |
3755 | break; | |
3756 | case INTEL_OUTPUT_DISPLAYPORT: | |
3757 | case INTEL_OUTPUT_EDP: | |
26756809 DV |
3758 | dig_port = enc_to_dig_port(&encoder->base); |
3759 | switch (dig_port->port) { | |
3760 | case PORT_B: | |
3761 | *source = INTEL_PIPE_CRC_SOURCE_DP_B; | |
3762 | break; | |
3763 | case PORT_C: | |
3764 | *source = INTEL_PIPE_CRC_SOURCE_DP_C; | |
3765 | break; | |
3766 | case PORT_D: | |
3767 | *source = INTEL_PIPE_CRC_SOURCE_DP_D; | |
3768 | break; | |
3769 | default: | |
3770 | WARN(1, "nonexisting DP port %c\n", | |
3771 | port_name(dig_port->port)); | |
3772 | break; | |
3773 | } | |
46a19188 | 3774 | break; |
6847d71b PZ |
3775 | default: |
3776 | break; | |
46a19188 DV |
3777 | } |
3778 | } | |
6e9f798d | 3779 | drm_modeset_unlock_all(dev); |
46a19188 DV |
3780 | |
3781 | return ret; | |
3782 | } | |
3783 | ||
3784 | static int vlv_pipe_crc_ctl_reg(struct drm_device *dev, | |
3785 | enum pipe pipe, | |
3786 | enum intel_pipe_crc_source *source, | |
7ac0129b DV |
3787 | uint32_t *val) |
3788 | { | |
8d2f24ca DV |
3789 | struct drm_i915_private *dev_priv = dev->dev_private; |
3790 | bool need_stable_symbols = false; | |
3791 | ||
46a19188 DV |
3792 | if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) { |
3793 | int ret = i9xx_pipe_crc_auto_source(dev, pipe, source); | |
3794 | if (ret) | |
3795 | return ret; | |
3796 | } | |
3797 | ||
3798 | switch (*source) { | |
7ac0129b DV |
3799 | case INTEL_PIPE_CRC_SOURCE_PIPE: |
3800 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_VLV; | |
3801 | break; | |
3802 | case INTEL_PIPE_CRC_SOURCE_DP_B: | |
3803 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_VLV; | |
8d2f24ca | 3804 | need_stable_symbols = true; |
7ac0129b DV |
3805 | break; |
3806 | case INTEL_PIPE_CRC_SOURCE_DP_C: | |
3807 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_VLV; | |
8d2f24ca | 3808 | need_stable_symbols = true; |
7ac0129b | 3809 | break; |
2be57922 VS |
3810 | case INTEL_PIPE_CRC_SOURCE_DP_D: |
3811 | if (!IS_CHERRYVIEW(dev)) | |
3812 | return -EINVAL; | |
3813 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_D_VLV; | |
3814 | need_stable_symbols = true; | |
3815 | break; | |
7ac0129b DV |
3816 | case INTEL_PIPE_CRC_SOURCE_NONE: |
3817 | *val = 0; | |
3818 | break; | |
3819 | default: | |
3820 | return -EINVAL; | |
3821 | } | |
3822 | ||
8d2f24ca DV |
3823 | /* |
3824 | * When the pipe CRC tap point is after the transcoders we need | |
3825 | * to tweak symbol-level features to produce a deterministic series of | |
3826 | * symbols for a given frame. We need to reset those features only once | |
3827 | * a frame (instead of every nth symbol): | |
3828 | * - DC-balance: used to ensure a better clock recovery from the data | |
3829 | * link (SDVO) | |
3830 | * - DisplayPort scrambling: used for EMI reduction | |
3831 | */ | |
3832 | if (need_stable_symbols) { | |
3833 | uint32_t tmp = I915_READ(PORT_DFT2_G4X); | |
3834 | ||
8d2f24ca | 3835 | tmp |= DC_BALANCE_RESET_VLV; |
eb736679 VS |
3836 | switch (pipe) { |
3837 | case PIPE_A: | |
8d2f24ca | 3838 | tmp |= PIPE_A_SCRAMBLE_RESET; |
eb736679 VS |
3839 | break; |
3840 | case PIPE_B: | |
8d2f24ca | 3841 | tmp |= PIPE_B_SCRAMBLE_RESET; |
eb736679 VS |
3842 | break; |
3843 | case PIPE_C: | |
3844 | tmp |= PIPE_C_SCRAMBLE_RESET; | |
3845 | break; | |
3846 | default: | |
3847 | return -EINVAL; | |
3848 | } | |
8d2f24ca DV |
3849 | I915_WRITE(PORT_DFT2_G4X, tmp); |
3850 | } | |
3851 | ||
7ac0129b DV |
3852 | return 0; |
3853 | } | |
3854 | ||
4b79ebf7 | 3855 | static int i9xx_pipe_crc_ctl_reg(struct drm_device *dev, |
46a19188 DV |
3856 | enum pipe pipe, |
3857 | enum intel_pipe_crc_source *source, | |
4b79ebf7 DV |
3858 | uint32_t *val) |
3859 | { | |
84093603 DV |
3860 | struct drm_i915_private *dev_priv = dev->dev_private; |
3861 | bool need_stable_symbols = false; | |
3862 | ||
46a19188 DV |
3863 | if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) { |
3864 | int ret = i9xx_pipe_crc_auto_source(dev, pipe, source); | |
3865 | if (ret) | |
3866 | return ret; | |
3867 | } | |
3868 | ||
3869 | switch (*source) { | |
4b79ebf7 DV |
3870 | case INTEL_PIPE_CRC_SOURCE_PIPE: |
3871 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_I9XX; | |
3872 | break; | |
3873 | case INTEL_PIPE_CRC_SOURCE_TV: | |
3874 | if (!SUPPORTS_TV(dev)) | |
3875 | return -EINVAL; | |
3876 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_TV_PRE; | |
3877 | break; | |
3878 | case INTEL_PIPE_CRC_SOURCE_DP_B: | |
3879 | if (!IS_G4X(dev)) | |
3880 | return -EINVAL; | |
3881 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_G4X; | |
84093603 | 3882 | need_stable_symbols = true; |
4b79ebf7 DV |
3883 | break; |
3884 | case INTEL_PIPE_CRC_SOURCE_DP_C: | |
3885 | if (!IS_G4X(dev)) | |
3886 | return -EINVAL; | |
3887 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_G4X; | |
84093603 | 3888 | need_stable_symbols = true; |
4b79ebf7 DV |
3889 | break; |
3890 | case INTEL_PIPE_CRC_SOURCE_DP_D: | |
3891 | if (!IS_G4X(dev)) | |
3892 | return -EINVAL; | |
3893 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_D_G4X; | |
84093603 | 3894 | need_stable_symbols = true; |
4b79ebf7 DV |
3895 | break; |
3896 | case INTEL_PIPE_CRC_SOURCE_NONE: | |
3897 | *val = 0; | |
3898 | break; | |
3899 | default: | |
3900 | return -EINVAL; | |
3901 | } | |
3902 | ||
84093603 DV |
3903 | /* |
3904 | * When the pipe CRC tap point is after the transcoders we need | |
3905 | * to tweak symbol-level features to produce a deterministic series of | |
3906 | * symbols for a given frame. We need to reset those features only once | |
3907 | * a frame (instead of every nth symbol): | |
3908 | * - DC-balance: used to ensure a better clock recovery from the data | |
3909 | * link (SDVO) | |
3910 | * - DisplayPort scrambling: used for EMI reduction | |
3911 | */ | |
3912 | if (need_stable_symbols) { | |
3913 | uint32_t tmp = I915_READ(PORT_DFT2_G4X); | |
3914 | ||
3915 | WARN_ON(!IS_G4X(dev)); | |
3916 | ||
3917 | I915_WRITE(PORT_DFT_I9XX, | |
3918 | I915_READ(PORT_DFT_I9XX) | DC_BALANCE_RESET); | |
3919 | ||
3920 | if (pipe == PIPE_A) | |
3921 | tmp |= PIPE_A_SCRAMBLE_RESET; | |
3922 | else | |
3923 | tmp |= PIPE_B_SCRAMBLE_RESET; | |
3924 | ||
3925 | I915_WRITE(PORT_DFT2_G4X, tmp); | |
3926 | } | |
3927 | ||
4b79ebf7 DV |
3928 | return 0; |
3929 | } | |
3930 | ||
8d2f24ca DV |
3931 | static void vlv_undo_pipe_scramble_reset(struct drm_device *dev, |
3932 | enum pipe pipe) | |
3933 | { | |
3934 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3935 | uint32_t tmp = I915_READ(PORT_DFT2_G4X); | |
3936 | ||
eb736679 VS |
3937 | switch (pipe) { |
3938 | case PIPE_A: | |
8d2f24ca | 3939 | tmp &= ~PIPE_A_SCRAMBLE_RESET; |
eb736679 VS |
3940 | break; |
3941 | case PIPE_B: | |
8d2f24ca | 3942 | tmp &= ~PIPE_B_SCRAMBLE_RESET; |
eb736679 VS |
3943 | break; |
3944 | case PIPE_C: | |
3945 | tmp &= ~PIPE_C_SCRAMBLE_RESET; | |
3946 | break; | |
3947 | default: | |
3948 | return; | |
3949 | } | |
8d2f24ca DV |
3950 | if (!(tmp & PIPE_SCRAMBLE_RESET_MASK)) |
3951 | tmp &= ~DC_BALANCE_RESET_VLV; | |
3952 | I915_WRITE(PORT_DFT2_G4X, tmp); | |
3953 | ||
3954 | } | |
3955 | ||
84093603 DV |
3956 | static void g4x_undo_pipe_scramble_reset(struct drm_device *dev, |
3957 | enum pipe pipe) | |
3958 | { | |
3959 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3960 | uint32_t tmp = I915_READ(PORT_DFT2_G4X); | |
3961 | ||
3962 | if (pipe == PIPE_A) | |
3963 | tmp &= ~PIPE_A_SCRAMBLE_RESET; | |
3964 | else | |
3965 | tmp &= ~PIPE_B_SCRAMBLE_RESET; | |
3966 | I915_WRITE(PORT_DFT2_G4X, tmp); | |
3967 | ||
3968 | if (!(tmp & PIPE_SCRAMBLE_RESET_MASK)) { | |
3969 | I915_WRITE(PORT_DFT_I9XX, | |
3970 | I915_READ(PORT_DFT_I9XX) & ~DC_BALANCE_RESET); | |
3971 | } | |
3972 | } | |
3973 | ||
46a19188 | 3974 | static int ilk_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source, |
5b3a856b DV |
3975 | uint32_t *val) |
3976 | { | |
46a19188 DV |
3977 | if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) |
3978 | *source = INTEL_PIPE_CRC_SOURCE_PIPE; | |
3979 | ||
3980 | switch (*source) { | |
5b3a856b DV |
3981 | case INTEL_PIPE_CRC_SOURCE_PLANE1: |
3982 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_ILK; | |
3983 | break; | |
3984 | case INTEL_PIPE_CRC_SOURCE_PLANE2: | |
3985 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_ILK; | |
3986 | break; | |
5b3a856b DV |
3987 | case INTEL_PIPE_CRC_SOURCE_PIPE: |
3988 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_ILK; | |
3989 | break; | |
3d099a05 | 3990 | case INTEL_PIPE_CRC_SOURCE_NONE: |
5b3a856b DV |
3991 | *val = 0; |
3992 | break; | |
3d099a05 DV |
3993 | default: |
3994 | return -EINVAL; | |
5b3a856b DV |
3995 | } |
3996 | ||
3997 | return 0; | |
3998 | } | |
3999 | ||
c4e2d043 | 4000 | static void hsw_trans_edp_pipe_A_crc_wa(struct drm_device *dev, bool enable) |
fabf6e51 DV |
4001 | { |
4002 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4003 | struct intel_crtc *crtc = | |
4004 | to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_A]); | |
f77076c9 | 4005 | struct intel_crtc_state *pipe_config; |
c4e2d043 ML |
4006 | struct drm_atomic_state *state; |
4007 | int ret = 0; | |
fabf6e51 DV |
4008 | |
4009 | drm_modeset_lock_all(dev); | |
c4e2d043 ML |
4010 | state = drm_atomic_state_alloc(dev); |
4011 | if (!state) { | |
4012 | ret = -ENOMEM; | |
4013 | goto out; | |
fabf6e51 | 4014 | } |
fabf6e51 | 4015 | |
c4e2d043 ML |
4016 | state->acquire_ctx = drm_modeset_legacy_acquire_ctx(&crtc->base); |
4017 | pipe_config = intel_atomic_get_crtc_state(state, crtc); | |
4018 | if (IS_ERR(pipe_config)) { | |
4019 | ret = PTR_ERR(pipe_config); | |
4020 | goto out; | |
4021 | } | |
fabf6e51 | 4022 | |
c4e2d043 ML |
4023 | pipe_config->pch_pfit.force_thru = enable; |
4024 | if (pipe_config->cpu_transcoder == TRANSCODER_EDP && | |
4025 | pipe_config->pch_pfit.enabled != enable) | |
4026 | pipe_config->base.connectors_changed = true; | |
1b509259 | 4027 | |
c4e2d043 ML |
4028 | ret = drm_atomic_commit(state); |
4029 | out: | |
fabf6e51 | 4030 | drm_modeset_unlock_all(dev); |
c4e2d043 ML |
4031 | WARN(ret, "Toggling workaround to %i returns %i\n", enable, ret); |
4032 | if (ret) | |
4033 | drm_atomic_state_free(state); | |
fabf6e51 DV |
4034 | } |
4035 | ||
4036 | static int ivb_pipe_crc_ctl_reg(struct drm_device *dev, | |
4037 | enum pipe pipe, | |
4038 | enum intel_pipe_crc_source *source, | |
5b3a856b DV |
4039 | uint32_t *val) |
4040 | { | |
46a19188 DV |
4041 | if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) |
4042 | *source = INTEL_PIPE_CRC_SOURCE_PF; | |
4043 | ||
4044 | switch (*source) { | |
5b3a856b DV |
4045 | case INTEL_PIPE_CRC_SOURCE_PLANE1: |
4046 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_IVB; | |
4047 | break; | |
4048 | case INTEL_PIPE_CRC_SOURCE_PLANE2: | |
4049 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_IVB; | |
4050 | break; | |
4051 | case INTEL_PIPE_CRC_SOURCE_PF: | |
fabf6e51 | 4052 | if (IS_HASWELL(dev) && pipe == PIPE_A) |
c4e2d043 | 4053 | hsw_trans_edp_pipe_A_crc_wa(dev, true); |
fabf6e51 | 4054 | |
5b3a856b DV |
4055 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PF_IVB; |
4056 | break; | |
3d099a05 | 4057 | case INTEL_PIPE_CRC_SOURCE_NONE: |
5b3a856b DV |
4058 | *val = 0; |
4059 | break; | |
3d099a05 DV |
4060 | default: |
4061 | return -EINVAL; | |
5b3a856b DV |
4062 | } |
4063 | ||
4064 | return 0; | |
4065 | } | |
4066 | ||
926321d5 DV |
4067 | static int pipe_crc_set_source(struct drm_device *dev, enum pipe pipe, |
4068 | enum intel_pipe_crc_source source) | |
4069 | { | |
4070 | struct drm_i915_private *dev_priv = dev->dev_private; | |
cc3da175 | 4071 | struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe]; |
8c740dce PZ |
4072 | struct intel_crtc *crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, |
4073 | pipe)); | |
e129649b | 4074 | enum intel_display_power_domain power_domain; |
432f3342 | 4075 | u32 val = 0; /* shut up gcc */ |
5b3a856b | 4076 | int ret; |
926321d5 | 4077 | |
cc3da175 DL |
4078 | if (pipe_crc->source == source) |
4079 | return 0; | |
4080 | ||
ae676fcd DL |
4081 | /* forbid changing the source without going back to 'none' */ |
4082 | if (pipe_crc->source && source) | |
4083 | return -EINVAL; | |
4084 | ||
e129649b ID |
4085 | power_domain = POWER_DOMAIN_PIPE(pipe); |
4086 | if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) { | |
9d8b0588 DV |
4087 | DRM_DEBUG_KMS("Trying to capture CRC while pipe is off\n"); |
4088 | return -EIO; | |
4089 | } | |
4090 | ||
52f843f6 | 4091 | if (IS_GEN2(dev)) |
46a19188 | 4092 | ret = i8xx_pipe_crc_ctl_reg(&source, &val); |
52f843f6 | 4093 | else if (INTEL_INFO(dev)->gen < 5) |
46a19188 | 4094 | ret = i9xx_pipe_crc_ctl_reg(dev, pipe, &source, &val); |
666a4537 | 4095 | else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) |
fabf6e51 | 4096 | ret = vlv_pipe_crc_ctl_reg(dev, pipe, &source, &val); |
4b79ebf7 | 4097 | else if (IS_GEN5(dev) || IS_GEN6(dev)) |
46a19188 | 4098 | ret = ilk_pipe_crc_ctl_reg(&source, &val); |
5b3a856b | 4099 | else |
fabf6e51 | 4100 | ret = ivb_pipe_crc_ctl_reg(dev, pipe, &source, &val); |
5b3a856b DV |
4101 | |
4102 | if (ret != 0) | |
e129649b | 4103 | goto out; |
5b3a856b | 4104 | |
4b584369 DL |
4105 | /* none -> real source transition */ |
4106 | if (source) { | |
4252fbc3 VS |
4107 | struct intel_pipe_crc_entry *entries; |
4108 | ||
7cd6ccff DL |
4109 | DRM_DEBUG_DRIVER("collecting CRCs for pipe %c, %s\n", |
4110 | pipe_name(pipe), pipe_crc_source_name(source)); | |
4111 | ||
3cf54b34 VS |
4112 | entries = kcalloc(INTEL_PIPE_CRC_ENTRIES_NR, |
4113 | sizeof(pipe_crc->entries[0]), | |
4252fbc3 | 4114 | GFP_KERNEL); |
e129649b ID |
4115 | if (!entries) { |
4116 | ret = -ENOMEM; | |
4117 | goto out; | |
4118 | } | |
e5f75aca | 4119 | |
8c740dce PZ |
4120 | /* |
4121 | * When IPS gets enabled, the pipe CRC changes. Since IPS gets | |
4122 | * enabled and disabled dynamically based on package C states, | |
4123 | * user space can't make reliable use of the CRCs, so let's just | |
4124 | * completely disable it. | |
4125 | */ | |
4126 | hsw_disable_ips(crtc); | |
4127 | ||
d538bbdf | 4128 | spin_lock_irq(&pipe_crc->lock); |
64387b61 | 4129 | kfree(pipe_crc->entries); |
4252fbc3 | 4130 | pipe_crc->entries = entries; |
d538bbdf DL |
4131 | pipe_crc->head = 0; |
4132 | pipe_crc->tail = 0; | |
4133 | spin_unlock_irq(&pipe_crc->lock); | |
4b584369 DL |
4134 | } |
4135 | ||
cc3da175 | 4136 | pipe_crc->source = source; |
926321d5 | 4137 | |
926321d5 DV |
4138 | I915_WRITE(PIPE_CRC_CTL(pipe), val); |
4139 | POSTING_READ(PIPE_CRC_CTL(pipe)); | |
4140 | ||
e5f75aca DL |
4141 | /* real source -> none transition */ |
4142 | if (source == INTEL_PIPE_CRC_SOURCE_NONE) { | |
d538bbdf | 4143 | struct intel_pipe_crc_entry *entries; |
a33d7105 DV |
4144 | struct intel_crtc *crtc = |
4145 | to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); | |
d538bbdf | 4146 | |
7cd6ccff DL |
4147 | DRM_DEBUG_DRIVER("stopping CRCs for pipe %c\n", |
4148 | pipe_name(pipe)); | |
4149 | ||
a33d7105 | 4150 | drm_modeset_lock(&crtc->base.mutex, NULL); |
f77076c9 | 4151 | if (crtc->base.state->active) |
a33d7105 DV |
4152 | intel_wait_for_vblank(dev, pipe); |
4153 | drm_modeset_unlock(&crtc->base.mutex); | |
bcf17ab2 | 4154 | |
d538bbdf DL |
4155 | spin_lock_irq(&pipe_crc->lock); |
4156 | entries = pipe_crc->entries; | |
e5f75aca | 4157 | pipe_crc->entries = NULL; |
9ad6d99f VS |
4158 | pipe_crc->head = 0; |
4159 | pipe_crc->tail = 0; | |
d538bbdf DL |
4160 | spin_unlock_irq(&pipe_crc->lock); |
4161 | ||
4162 | kfree(entries); | |
84093603 DV |
4163 | |
4164 | if (IS_G4X(dev)) | |
4165 | g4x_undo_pipe_scramble_reset(dev, pipe); | |
666a4537 | 4166 | else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) |
8d2f24ca | 4167 | vlv_undo_pipe_scramble_reset(dev, pipe); |
fabf6e51 | 4168 | else if (IS_HASWELL(dev) && pipe == PIPE_A) |
c4e2d043 | 4169 | hsw_trans_edp_pipe_A_crc_wa(dev, false); |
8c740dce PZ |
4170 | |
4171 | hsw_enable_ips(crtc); | |
e5f75aca DL |
4172 | } |
4173 | ||
e129649b ID |
4174 | ret = 0; |
4175 | ||
4176 | out: | |
4177 | intel_display_power_put(dev_priv, power_domain); | |
4178 | ||
4179 | return ret; | |
926321d5 DV |
4180 | } |
4181 | ||
4182 | /* | |
4183 | * Parse pipe CRC command strings: | |
b94dec87 DL |
4184 | * command: wsp* object wsp+ name wsp+ source wsp* |
4185 | * object: 'pipe' | |
4186 | * name: (A | B | C) | |
926321d5 DV |
4187 | * source: (none | plane1 | plane2 | pf) |
4188 | * wsp: (#0x20 | #0x9 | #0xA)+ | |
4189 | * | |
4190 | * eg.: | |
b94dec87 DL |
4191 | * "pipe A plane1" -> Start CRC computations on plane1 of pipe A |
4192 | * "pipe A none" -> Stop CRC | |
926321d5 | 4193 | */ |
bd9db02f | 4194 | static int display_crc_ctl_tokenize(char *buf, char *words[], int max_words) |
926321d5 DV |
4195 | { |
4196 | int n_words = 0; | |
4197 | ||
4198 | while (*buf) { | |
4199 | char *end; | |
4200 | ||
4201 | /* skip leading white space */ | |
4202 | buf = skip_spaces(buf); | |
4203 | if (!*buf) | |
4204 | break; /* end of buffer */ | |
4205 | ||
4206 | /* find end of word */ | |
4207 | for (end = buf; *end && !isspace(*end); end++) | |
4208 | ; | |
4209 | ||
4210 | if (n_words == max_words) { | |
4211 | DRM_DEBUG_DRIVER("too many words, allowed <= %d\n", | |
4212 | max_words); | |
4213 | return -EINVAL; /* ran out of words[] before bytes */ | |
4214 | } | |
4215 | ||
4216 | if (*end) | |
4217 | *end++ = '\0'; | |
4218 | words[n_words++] = buf; | |
4219 | buf = end; | |
4220 | } | |
4221 | ||
4222 | return n_words; | |
4223 | } | |
4224 | ||
b94dec87 DL |
4225 | enum intel_pipe_crc_object { |
4226 | PIPE_CRC_OBJECT_PIPE, | |
4227 | }; | |
4228 | ||
e8dfcf78 | 4229 | static const char * const pipe_crc_objects[] = { |
b94dec87 DL |
4230 | "pipe", |
4231 | }; | |
4232 | ||
4233 | static int | |
bd9db02f | 4234 | display_crc_ctl_parse_object(const char *buf, enum intel_pipe_crc_object *o) |
b94dec87 DL |
4235 | { |
4236 | int i; | |
4237 | ||
4238 | for (i = 0; i < ARRAY_SIZE(pipe_crc_objects); i++) | |
4239 | if (!strcmp(buf, pipe_crc_objects[i])) { | |
bd9db02f | 4240 | *o = i; |
b94dec87 DL |
4241 | return 0; |
4242 | } | |
4243 | ||
4244 | return -EINVAL; | |
4245 | } | |
4246 | ||
bd9db02f | 4247 | static int display_crc_ctl_parse_pipe(const char *buf, enum pipe *pipe) |
926321d5 DV |
4248 | { |
4249 | const char name = buf[0]; | |
4250 | ||
4251 | if (name < 'A' || name >= pipe_name(I915_MAX_PIPES)) | |
4252 | return -EINVAL; | |
4253 | ||
4254 | *pipe = name - 'A'; | |
4255 | ||
4256 | return 0; | |
4257 | } | |
4258 | ||
4259 | static int | |
bd9db02f | 4260 | display_crc_ctl_parse_source(const char *buf, enum intel_pipe_crc_source *s) |
926321d5 DV |
4261 | { |
4262 | int i; | |
4263 | ||
4264 | for (i = 0; i < ARRAY_SIZE(pipe_crc_sources); i++) | |
4265 | if (!strcmp(buf, pipe_crc_sources[i])) { | |
bd9db02f | 4266 | *s = i; |
926321d5 DV |
4267 | return 0; |
4268 | } | |
4269 | ||
4270 | return -EINVAL; | |
4271 | } | |
4272 | ||
bd9db02f | 4273 | static int display_crc_ctl_parse(struct drm_device *dev, char *buf, size_t len) |
926321d5 | 4274 | { |
b94dec87 | 4275 | #define N_WORDS 3 |
926321d5 | 4276 | int n_words; |
b94dec87 | 4277 | char *words[N_WORDS]; |
926321d5 | 4278 | enum pipe pipe; |
b94dec87 | 4279 | enum intel_pipe_crc_object object; |
926321d5 DV |
4280 | enum intel_pipe_crc_source source; |
4281 | ||
bd9db02f | 4282 | n_words = display_crc_ctl_tokenize(buf, words, N_WORDS); |
b94dec87 DL |
4283 | if (n_words != N_WORDS) { |
4284 | DRM_DEBUG_DRIVER("tokenize failed, a command is %d words\n", | |
4285 | N_WORDS); | |
4286 | return -EINVAL; | |
4287 | } | |
4288 | ||
bd9db02f | 4289 | if (display_crc_ctl_parse_object(words[0], &object) < 0) { |
b94dec87 | 4290 | DRM_DEBUG_DRIVER("unknown object %s\n", words[0]); |
926321d5 DV |
4291 | return -EINVAL; |
4292 | } | |
4293 | ||
bd9db02f | 4294 | if (display_crc_ctl_parse_pipe(words[1], &pipe) < 0) { |
b94dec87 | 4295 | DRM_DEBUG_DRIVER("unknown pipe %s\n", words[1]); |
926321d5 DV |
4296 | return -EINVAL; |
4297 | } | |
4298 | ||
bd9db02f | 4299 | if (display_crc_ctl_parse_source(words[2], &source) < 0) { |
b94dec87 | 4300 | DRM_DEBUG_DRIVER("unknown source %s\n", words[2]); |
926321d5 DV |
4301 | return -EINVAL; |
4302 | } | |
4303 | ||
4304 | return pipe_crc_set_source(dev, pipe, source); | |
4305 | } | |
4306 | ||
bd9db02f DL |
4307 | static ssize_t display_crc_ctl_write(struct file *file, const char __user *ubuf, |
4308 | size_t len, loff_t *offp) | |
926321d5 DV |
4309 | { |
4310 | struct seq_file *m = file->private_data; | |
4311 | struct drm_device *dev = m->private; | |
4312 | char *tmpbuf; | |
4313 | int ret; | |
4314 | ||
4315 | if (len == 0) | |
4316 | return 0; | |
4317 | ||
4318 | if (len > PAGE_SIZE - 1) { | |
4319 | DRM_DEBUG_DRIVER("expected <%lu bytes into pipe crc control\n", | |
4320 | PAGE_SIZE); | |
4321 | return -E2BIG; | |
4322 | } | |
4323 | ||
4324 | tmpbuf = kmalloc(len + 1, GFP_KERNEL); | |
4325 | if (!tmpbuf) | |
4326 | return -ENOMEM; | |
4327 | ||
4328 | if (copy_from_user(tmpbuf, ubuf, len)) { | |
4329 | ret = -EFAULT; | |
4330 | goto out; | |
4331 | } | |
4332 | tmpbuf[len] = '\0'; | |
4333 | ||
bd9db02f | 4334 | ret = display_crc_ctl_parse(dev, tmpbuf, len); |
926321d5 DV |
4335 | |
4336 | out: | |
4337 | kfree(tmpbuf); | |
4338 | if (ret < 0) | |
4339 | return ret; | |
4340 | ||
4341 | *offp += len; | |
4342 | return len; | |
4343 | } | |
4344 | ||
bd9db02f | 4345 | static const struct file_operations i915_display_crc_ctl_fops = { |
926321d5 | 4346 | .owner = THIS_MODULE, |
bd9db02f | 4347 | .open = display_crc_ctl_open, |
926321d5 DV |
4348 | .read = seq_read, |
4349 | .llseek = seq_lseek, | |
4350 | .release = single_release, | |
bd9db02f | 4351 | .write = display_crc_ctl_write |
926321d5 DV |
4352 | }; |
4353 | ||
eb3394fa TP |
4354 | static ssize_t i915_displayport_test_active_write(struct file *file, |
4355 | const char __user *ubuf, | |
4356 | size_t len, loff_t *offp) | |
4357 | { | |
4358 | char *input_buffer; | |
4359 | int status = 0; | |
eb3394fa TP |
4360 | struct drm_device *dev; |
4361 | struct drm_connector *connector; | |
4362 | struct list_head *connector_list; | |
4363 | struct intel_dp *intel_dp; | |
4364 | int val = 0; | |
4365 | ||
9aaffa34 | 4366 | dev = ((struct seq_file *)file->private_data)->private; |
eb3394fa | 4367 | |
eb3394fa TP |
4368 | connector_list = &dev->mode_config.connector_list; |
4369 | ||
4370 | if (len == 0) | |
4371 | return 0; | |
4372 | ||
4373 | input_buffer = kmalloc(len + 1, GFP_KERNEL); | |
4374 | if (!input_buffer) | |
4375 | return -ENOMEM; | |
4376 | ||
4377 | if (copy_from_user(input_buffer, ubuf, len)) { | |
4378 | status = -EFAULT; | |
4379 | goto out; | |
4380 | } | |
4381 | ||
4382 | input_buffer[len] = '\0'; | |
4383 | DRM_DEBUG_DRIVER("Copied %d bytes from user\n", (unsigned int)len); | |
4384 | ||
4385 | list_for_each_entry(connector, connector_list, head) { | |
4386 | ||
4387 | if (connector->connector_type != | |
4388 | DRM_MODE_CONNECTOR_DisplayPort) | |
4389 | continue; | |
4390 | ||
b8bb08ec | 4391 | if (connector->status == connector_status_connected && |
eb3394fa TP |
4392 | connector->encoder != NULL) { |
4393 | intel_dp = enc_to_intel_dp(connector->encoder); | |
4394 | status = kstrtoint(input_buffer, 10, &val); | |
4395 | if (status < 0) | |
4396 | goto out; | |
4397 | DRM_DEBUG_DRIVER("Got %d for test active\n", val); | |
4398 | /* To prevent erroneous activation of the compliance | |
4399 | * testing code, only accept an actual value of 1 here | |
4400 | */ | |
4401 | if (val == 1) | |
4402 | intel_dp->compliance_test_active = 1; | |
4403 | else | |
4404 | intel_dp->compliance_test_active = 0; | |
4405 | } | |
4406 | } | |
4407 | out: | |
4408 | kfree(input_buffer); | |
4409 | if (status < 0) | |
4410 | return status; | |
4411 | ||
4412 | *offp += len; | |
4413 | return len; | |
4414 | } | |
4415 | ||
4416 | static int i915_displayport_test_active_show(struct seq_file *m, void *data) | |
4417 | { | |
4418 | struct drm_device *dev = m->private; | |
4419 | struct drm_connector *connector; | |
4420 | struct list_head *connector_list = &dev->mode_config.connector_list; | |
4421 | struct intel_dp *intel_dp; | |
4422 | ||
eb3394fa TP |
4423 | list_for_each_entry(connector, connector_list, head) { |
4424 | ||
4425 | if (connector->connector_type != | |
4426 | DRM_MODE_CONNECTOR_DisplayPort) | |
4427 | continue; | |
4428 | ||
4429 | if (connector->status == connector_status_connected && | |
4430 | connector->encoder != NULL) { | |
4431 | intel_dp = enc_to_intel_dp(connector->encoder); | |
4432 | if (intel_dp->compliance_test_active) | |
4433 | seq_puts(m, "1"); | |
4434 | else | |
4435 | seq_puts(m, "0"); | |
4436 | } else | |
4437 | seq_puts(m, "0"); | |
4438 | } | |
4439 | ||
4440 | return 0; | |
4441 | } | |
4442 | ||
4443 | static int i915_displayport_test_active_open(struct inode *inode, | |
4444 | struct file *file) | |
4445 | { | |
4446 | struct drm_device *dev = inode->i_private; | |
4447 | ||
4448 | return single_open(file, i915_displayport_test_active_show, dev); | |
4449 | } | |
4450 | ||
4451 | static const struct file_operations i915_displayport_test_active_fops = { | |
4452 | .owner = THIS_MODULE, | |
4453 | .open = i915_displayport_test_active_open, | |
4454 | .read = seq_read, | |
4455 | .llseek = seq_lseek, | |
4456 | .release = single_release, | |
4457 | .write = i915_displayport_test_active_write | |
4458 | }; | |
4459 | ||
4460 | static int i915_displayport_test_data_show(struct seq_file *m, void *data) | |
4461 | { | |
4462 | struct drm_device *dev = m->private; | |
4463 | struct drm_connector *connector; | |
4464 | struct list_head *connector_list = &dev->mode_config.connector_list; | |
4465 | struct intel_dp *intel_dp; | |
4466 | ||
eb3394fa TP |
4467 | list_for_each_entry(connector, connector_list, head) { |
4468 | ||
4469 | if (connector->connector_type != | |
4470 | DRM_MODE_CONNECTOR_DisplayPort) | |
4471 | continue; | |
4472 | ||
4473 | if (connector->status == connector_status_connected && | |
4474 | connector->encoder != NULL) { | |
4475 | intel_dp = enc_to_intel_dp(connector->encoder); | |
4476 | seq_printf(m, "%lx", intel_dp->compliance_test_data); | |
4477 | } else | |
4478 | seq_puts(m, "0"); | |
4479 | } | |
4480 | ||
4481 | return 0; | |
4482 | } | |
4483 | static int i915_displayport_test_data_open(struct inode *inode, | |
4484 | struct file *file) | |
4485 | { | |
4486 | struct drm_device *dev = inode->i_private; | |
4487 | ||
4488 | return single_open(file, i915_displayport_test_data_show, dev); | |
4489 | } | |
4490 | ||
4491 | static const struct file_operations i915_displayport_test_data_fops = { | |
4492 | .owner = THIS_MODULE, | |
4493 | .open = i915_displayport_test_data_open, | |
4494 | .read = seq_read, | |
4495 | .llseek = seq_lseek, | |
4496 | .release = single_release | |
4497 | }; | |
4498 | ||
4499 | static int i915_displayport_test_type_show(struct seq_file *m, void *data) | |
4500 | { | |
4501 | struct drm_device *dev = m->private; | |
4502 | struct drm_connector *connector; | |
4503 | struct list_head *connector_list = &dev->mode_config.connector_list; | |
4504 | struct intel_dp *intel_dp; | |
4505 | ||
eb3394fa TP |
4506 | list_for_each_entry(connector, connector_list, head) { |
4507 | ||
4508 | if (connector->connector_type != | |
4509 | DRM_MODE_CONNECTOR_DisplayPort) | |
4510 | continue; | |
4511 | ||
4512 | if (connector->status == connector_status_connected && | |
4513 | connector->encoder != NULL) { | |
4514 | intel_dp = enc_to_intel_dp(connector->encoder); | |
4515 | seq_printf(m, "%02lx", intel_dp->compliance_test_type); | |
4516 | } else | |
4517 | seq_puts(m, "0"); | |
4518 | } | |
4519 | ||
4520 | return 0; | |
4521 | } | |
4522 | ||
4523 | static int i915_displayport_test_type_open(struct inode *inode, | |
4524 | struct file *file) | |
4525 | { | |
4526 | struct drm_device *dev = inode->i_private; | |
4527 | ||
4528 | return single_open(file, i915_displayport_test_type_show, dev); | |
4529 | } | |
4530 | ||
4531 | static const struct file_operations i915_displayport_test_type_fops = { | |
4532 | .owner = THIS_MODULE, | |
4533 | .open = i915_displayport_test_type_open, | |
4534 | .read = seq_read, | |
4535 | .llseek = seq_lseek, | |
4536 | .release = single_release | |
4537 | }; | |
4538 | ||
97e94b22 | 4539 | static void wm_latency_show(struct seq_file *m, const uint16_t wm[8]) |
369a1342 VS |
4540 | { |
4541 | struct drm_device *dev = m->private; | |
369a1342 | 4542 | int level; |
de38b95c VS |
4543 | int num_levels; |
4544 | ||
4545 | if (IS_CHERRYVIEW(dev)) | |
4546 | num_levels = 3; | |
4547 | else if (IS_VALLEYVIEW(dev)) | |
4548 | num_levels = 1; | |
4549 | else | |
4550 | num_levels = ilk_wm_max_level(dev) + 1; | |
369a1342 VS |
4551 | |
4552 | drm_modeset_lock_all(dev); | |
4553 | ||
4554 | for (level = 0; level < num_levels; level++) { | |
4555 | unsigned int latency = wm[level]; | |
4556 | ||
97e94b22 DL |
4557 | /* |
4558 | * - WM1+ latency values in 0.5us units | |
de38b95c | 4559 | * - latencies are in us on gen9/vlv/chv |
97e94b22 | 4560 | */ |
666a4537 WB |
4561 | if (INTEL_INFO(dev)->gen >= 9 || IS_VALLEYVIEW(dev) || |
4562 | IS_CHERRYVIEW(dev)) | |
97e94b22 DL |
4563 | latency *= 10; |
4564 | else if (level > 0) | |
369a1342 VS |
4565 | latency *= 5; |
4566 | ||
4567 | seq_printf(m, "WM%d %u (%u.%u usec)\n", | |
97e94b22 | 4568 | level, wm[level], latency / 10, latency % 10); |
369a1342 VS |
4569 | } |
4570 | ||
4571 | drm_modeset_unlock_all(dev); | |
4572 | } | |
4573 | ||
4574 | static int pri_wm_latency_show(struct seq_file *m, void *data) | |
4575 | { | |
4576 | struct drm_device *dev = m->private; | |
97e94b22 DL |
4577 | struct drm_i915_private *dev_priv = dev->dev_private; |
4578 | const uint16_t *latencies; | |
4579 | ||
4580 | if (INTEL_INFO(dev)->gen >= 9) | |
4581 | latencies = dev_priv->wm.skl_latency; | |
4582 | else | |
4583 | latencies = to_i915(dev)->wm.pri_latency; | |
369a1342 | 4584 | |
97e94b22 | 4585 | wm_latency_show(m, latencies); |
369a1342 VS |
4586 | |
4587 | return 0; | |
4588 | } | |
4589 | ||
4590 | static int spr_wm_latency_show(struct seq_file *m, void *data) | |
4591 | { | |
4592 | struct drm_device *dev = m->private; | |
97e94b22 DL |
4593 | struct drm_i915_private *dev_priv = dev->dev_private; |
4594 | const uint16_t *latencies; | |
4595 | ||
4596 | if (INTEL_INFO(dev)->gen >= 9) | |
4597 | latencies = dev_priv->wm.skl_latency; | |
4598 | else | |
4599 | latencies = to_i915(dev)->wm.spr_latency; | |
369a1342 | 4600 | |
97e94b22 | 4601 | wm_latency_show(m, latencies); |
369a1342 VS |
4602 | |
4603 | return 0; | |
4604 | } | |
4605 | ||
4606 | static int cur_wm_latency_show(struct seq_file *m, void *data) | |
4607 | { | |
4608 | struct drm_device *dev = m->private; | |
97e94b22 DL |
4609 | struct drm_i915_private *dev_priv = dev->dev_private; |
4610 | const uint16_t *latencies; | |
4611 | ||
4612 | if (INTEL_INFO(dev)->gen >= 9) | |
4613 | latencies = dev_priv->wm.skl_latency; | |
4614 | else | |
4615 | latencies = to_i915(dev)->wm.cur_latency; | |
369a1342 | 4616 | |
97e94b22 | 4617 | wm_latency_show(m, latencies); |
369a1342 VS |
4618 | |
4619 | return 0; | |
4620 | } | |
4621 | ||
4622 | static int pri_wm_latency_open(struct inode *inode, struct file *file) | |
4623 | { | |
4624 | struct drm_device *dev = inode->i_private; | |
4625 | ||
de38b95c | 4626 | if (INTEL_INFO(dev)->gen < 5) |
369a1342 VS |
4627 | return -ENODEV; |
4628 | ||
4629 | return single_open(file, pri_wm_latency_show, dev); | |
4630 | } | |
4631 | ||
4632 | static int spr_wm_latency_open(struct inode *inode, struct file *file) | |
4633 | { | |
4634 | struct drm_device *dev = inode->i_private; | |
4635 | ||
9ad0257c | 4636 | if (HAS_GMCH_DISPLAY(dev)) |
369a1342 VS |
4637 | return -ENODEV; |
4638 | ||
4639 | return single_open(file, spr_wm_latency_show, dev); | |
4640 | } | |
4641 | ||
4642 | static int cur_wm_latency_open(struct inode *inode, struct file *file) | |
4643 | { | |
4644 | struct drm_device *dev = inode->i_private; | |
4645 | ||
9ad0257c | 4646 | if (HAS_GMCH_DISPLAY(dev)) |
369a1342 VS |
4647 | return -ENODEV; |
4648 | ||
4649 | return single_open(file, cur_wm_latency_show, dev); | |
4650 | } | |
4651 | ||
4652 | static ssize_t wm_latency_write(struct file *file, const char __user *ubuf, | |
97e94b22 | 4653 | size_t len, loff_t *offp, uint16_t wm[8]) |
369a1342 VS |
4654 | { |
4655 | struct seq_file *m = file->private_data; | |
4656 | struct drm_device *dev = m->private; | |
97e94b22 | 4657 | uint16_t new[8] = { 0 }; |
de38b95c | 4658 | int num_levels; |
369a1342 VS |
4659 | int level; |
4660 | int ret; | |
4661 | char tmp[32]; | |
4662 | ||
de38b95c VS |
4663 | if (IS_CHERRYVIEW(dev)) |
4664 | num_levels = 3; | |
4665 | else if (IS_VALLEYVIEW(dev)) | |
4666 | num_levels = 1; | |
4667 | else | |
4668 | num_levels = ilk_wm_max_level(dev) + 1; | |
4669 | ||
369a1342 VS |
4670 | if (len >= sizeof(tmp)) |
4671 | return -EINVAL; | |
4672 | ||
4673 | if (copy_from_user(tmp, ubuf, len)) | |
4674 | return -EFAULT; | |
4675 | ||
4676 | tmp[len] = '\0'; | |
4677 | ||
97e94b22 DL |
4678 | ret = sscanf(tmp, "%hu %hu %hu %hu %hu %hu %hu %hu", |
4679 | &new[0], &new[1], &new[2], &new[3], | |
4680 | &new[4], &new[5], &new[6], &new[7]); | |
369a1342 VS |
4681 | if (ret != num_levels) |
4682 | return -EINVAL; | |
4683 | ||
4684 | drm_modeset_lock_all(dev); | |
4685 | ||
4686 | for (level = 0; level < num_levels; level++) | |
4687 | wm[level] = new[level]; | |
4688 | ||
4689 | drm_modeset_unlock_all(dev); | |
4690 | ||
4691 | return len; | |
4692 | } | |
4693 | ||
4694 | ||
4695 | static ssize_t pri_wm_latency_write(struct file *file, const char __user *ubuf, | |
4696 | size_t len, loff_t *offp) | |
4697 | { | |
4698 | struct seq_file *m = file->private_data; | |
4699 | struct drm_device *dev = m->private; | |
97e94b22 DL |
4700 | struct drm_i915_private *dev_priv = dev->dev_private; |
4701 | uint16_t *latencies; | |
369a1342 | 4702 | |
97e94b22 DL |
4703 | if (INTEL_INFO(dev)->gen >= 9) |
4704 | latencies = dev_priv->wm.skl_latency; | |
4705 | else | |
4706 | latencies = to_i915(dev)->wm.pri_latency; | |
4707 | ||
4708 | return wm_latency_write(file, ubuf, len, offp, latencies); | |
369a1342 VS |
4709 | } |
4710 | ||
4711 | static ssize_t spr_wm_latency_write(struct file *file, const char __user *ubuf, | |
4712 | size_t len, loff_t *offp) | |
4713 | { | |
4714 | struct seq_file *m = file->private_data; | |
4715 | struct drm_device *dev = m->private; | |
97e94b22 DL |
4716 | struct drm_i915_private *dev_priv = dev->dev_private; |
4717 | uint16_t *latencies; | |
369a1342 | 4718 | |
97e94b22 DL |
4719 | if (INTEL_INFO(dev)->gen >= 9) |
4720 | latencies = dev_priv->wm.skl_latency; | |
4721 | else | |
4722 | latencies = to_i915(dev)->wm.spr_latency; | |
4723 | ||
4724 | return wm_latency_write(file, ubuf, len, offp, latencies); | |
369a1342 VS |
4725 | } |
4726 | ||
4727 | static ssize_t cur_wm_latency_write(struct file *file, const char __user *ubuf, | |
4728 | size_t len, loff_t *offp) | |
4729 | { | |
4730 | struct seq_file *m = file->private_data; | |
4731 | struct drm_device *dev = m->private; | |
97e94b22 DL |
4732 | struct drm_i915_private *dev_priv = dev->dev_private; |
4733 | uint16_t *latencies; | |
4734 | ||
4735 | if (INTEL_INFO(dev)->gen >= 9) | |
4736 | latencies = dev_priv->wm.skl_latency; | |
4737 | else | |
4738 | latencies = to_i915(dev)->wm.cur_latency; | |
369a1342 | 4739 | |
97e94b22 | 4740 | return wm_latency_write(file, ubuf, len, offp, latencies); |
369a1342 VS |
4741 | } |
4742 | ||
4743 | static const struct file_operations i915_pri_wm_latency_fops = { | |
4744 | .owner = THIS_MODULE, | |
4745 | .open = pri_wm_latency_open, | |
4746 | .read = seq_read, | |
4747 | .llseek = seq_lseek, | |
4748 | .release = single_release, | |
4749 | .write = pri_wm_latency_write | |
4750 | }; | |
4751 | ||
4752 | static const struct file_operations i915_spr_wm_latency_fops = { | |
4753 | .owner = THIS_MODULE, | |
4754 | .open = spr_wm_latency_open, | |
4755 | .read = seq_read, | |
4756 | .llseek = seq_lseek, | |
4757 | .release = single_release, | |
4758 | .write = spr_wm_latency_write | |
4759 | }; | |
4760 | ||
4761 | static const struct file_operations i915_cur_wm_latency_fops = { | |
4762 | .owner = THIS_MODULE, | |
4763 | .open = cur_wm_latency_open, | |
4764 | .read = seq_read, | |
4765 | .llseek = seq_lseek, | |
4766 | .release = single_release, | |
4767 | .write = cur_wm_latency_write | |
4768 | }; | |
4769 | ||
647416f9 KC |
4770 | static int |
4771 | i915_wedged_get(void *data, u64 *val) | |
f3cd474b | 4772 | { |
647416f9 | 4773 | struct drm_device *dev = data; |
e277a1f8 | 4774 | struct drm_i915_private *dev_priv = dev->dev_private; |
f3cd474b | 4775 | |
d98c52cf | 4776 | *val = i915_terminally_wedged(&dev_priv->gpu_error); |
f3cd474b | 4777 | |
647416f9 | 4778 | return 0; |
f3cd474b CW |
4779 | } |
4780 | ||
647416f9 KC |
4781 | static int |
4782 | i915_wedged_set(void *data, u64 val) | |
f3cd474b | 4783 | { |
647416f9 | 4784 | struct drm_device *dev = data; |
d46c0517 ID |
4785 | struct drm_i915_private *dev_priv = dev->dev_private; |
4786 | ||
b8d24a06 MK |
4787 | /* |
4788 | * There is no safeguard against this debugfs entry colliding | |
4789 | * with the hangcheck calling same i915_handle_error() in | |
4790 | * parallel, causing an explosion. For now we assume that the | |
4791 | * test harness is responsible enough not to inject gpu hangs | |
4792 | * while it is writing to 'i915_wedged' | |
4793 | */ | |
4794 | ||
d98c52cf | 4795 | if (i915_reset_in_progress(&dev_priv->gpu_error)) |
b8d24a06 MK |
4796 | return -EAGAIN; |
4797 | ||
d46c0517 | 4798 | intel_runtime_pm_get(dev_priv); |
f3cd474b | 4799 | |
c033666a | 4800 | i915_handle_error(dev_priv, val, |
58174462 | 4801 | "Manually setting wedged to %llu", val); |
d46c0517 ID |
4802 | |
4803 | intel_runtime_pm_put(dev_priv); | |
4804 | ||
647416f9 | 4805 | return 0; |
f3cd474b CW |
4806 | } |
4807 | ||
647416f9 KC |
4808 | DEFINE_SIMPLE_ATTRIBUTE(i915_wedged_fops, |
4809 | i915_wedged_get, i915_wedged_set, | |
3a3b4f98 | 4810 | "%llu\n"); |
f3cd474b | 4811 | |
647416f9 KC |
4812 | static int |
4813 | i915_ring_stop_get(void *data, u64 *val) | |
e5eb3d63 | 4814 | { |
647416f9 | 4815 | struct drm_device *dev = data; |
e277a1f8 | 4816 | struct drm_i915_private *dev_priv = dev->dev_private; |
e5eb3d63 | 4817 | |
647416f9 | 4818 | *val = dev_priv->gpu_error.stop_rings; |
e5eb3d63 | 4819 | |
647416f9 | 4820 | return 0; |
e5eb3d63 DV |
4821 | } |
4822 | ||
647416f9 KC |
4823 | static int |
4824 | i915_ring_stop_set(void *data, u64 val) | |
e5eb3d63 | 4825 | { |
647416f9 | 4826 | struct drm_device *dev = data; |
e5eb3d63 | 4827 | struct drm_i915_private *dev_priv = dev->dev_private; |
647416f9 | 4828 | int ret; |
e5eb3d63 | 4829 | |
647416f9 | 4830 | DRM_DEBUG_DRIVER("Stopping rings 0x%08llx\n", val); |
e5eb3d63 | 4831 | |
22bcfc6a DV |
4832 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
4833 | if (ret) | |
4834 | return ret; | |
4835 | ||
99584db3 | 4836 | dev_priv->gpu_error.stop_rings = val; |
e5eb3d63 DV |
4837 | mutex_unlock(&dev->struct_mutex); |
4838 | ||
647416f9 | 4839 | return 0; |
e5eb3d63 DV |
4840 | } |
4841 | ||
647416f9 KC |
4842 | DEFINE_SIMPLE_ATTRIBUTE(i915_ring_stop_fops, |
4843 | i915_ring_stop_get, i915_ring_stop_set, | |
4844 | "0x%08llx\n"); | |
d5442303 | 4845 | |
094f9a54 CW |
4846 | static int |
4847 | i915_ring_missed_irq_get(void *data, u64 *val) | |
4848 | { | |
4849 | struct drm_device *dev = data; | |
4850 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4851 | ||
4852 | *val = dev_priv->gpu_error.missed_irq_rings; | |
4853 | return 0; | |
4854 | } | |
4855 | ||
4856 | static int | |
4857 | i915_ring_missed_irq_set(void *data, u64 val) | |
4858 | { | |
4859 | struct drm_device *dev = data; | |
4860 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4861 | int ret; | |
4862 | ||
4863 | /* Lock against concurrent debugfs callers */ | |
4864 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
4865 | if (ret) | |
4866 | return ret; | |
4867 | dev_priv->gpu_error.missed_irq_rings = val; | |
4868 | mutex_unlock(&dev->struct_mutex); | |
4869 | ||
4870 | return 0; | |
4871 | } | |
4872 | ||
4873 | DEFINE_SIMPLE_ATTRIBUTE(i915_ring_missed_irq_fops, | |
4874 | i915_ring_missed_irq_get, i915_ring_missed_irq_set, | |
4875 | "0x%08llx\n"); | |
4876 | ||
4877 | static int | |
4878 | i915_ring_test_irq_get(void *data, u64 *val) | |
4879 | { | |
4880 | struct drm_device *dev = data; | |
4881 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4882 | ||
4883 | *val = dev_priv->gpu_error.test_irq_rings; | |
4884 | ||
4885 | return 0; | |
4886 | } | |
4887 | ||
4888 | static int | |
4889 | i915_ring_test_irq_set(void *data, u64 val) | |
4890 | { | |
4891 | struct drm_device *dev = data; | |
4892 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4893 | int ret; | |
4894 | ||
4895 | DRM_DEBUG_DRIVER("Masking interrupts on rings 0x%08llx\n", val); | |
4896 | ||
4897 | /* Lock against concurrent debugfs callers */ | |
4898 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
4899 | if (ret) | |
4900 | return ret; | |
4901 | ||
4902 | dev_priv->gpu_error.test_irq_rings = val; | |
4903 | mutex_unlock(&dev->struct_mutex); | |
4904 | ||
4905 | return 0; | |
4906 | } | |
4907 | ||
4908 | DEFINE_SIMPLE_ATTRIBUTE(i915_ring_test_irq_fops, | |
4909 | i915_ring_test_irq_get, i915_ring_test_irq_set, | |
4910 | "0x%08llx\n"); | |
4911 | ||
dd624afd CW |
4912 | #define DROP_UNBOUND 0x1 |
4913 | #define DROP_BOUND 0x2 | |
4914 | #define DROP_RETIRE 0x4 | |
4915 | #define DROP_ACTIVE 0x8 | |
4916 | #define DROP_ALL (DROP_UNBOUND | \ | |
4917 | DROP_BOUND | \ | |
4918 | DROP_RETIRE | \ | |
4919 | DROP_ACTIVE) | |
647416f9 KC |
4920 | static int |
4921 | i915_drop_caches_get(void *data, u64 *val) | |
dd624afd | 4922 | { |
647416f9 | 4923 | *val = DROP_ALL; |
dd624afd | 4924 | |
647416f9 | 4925 | return 0; |
dd624afd CW |
4926 | } |
4927 | ||
647416f9 KC |
4928 | static int |
4929 | i915_drop_caches_set(void *data, u64 val) | |
dd624afd | 4930 | { |
647416f9 | 4931 | struct drm_device *dev = data; |
dd624afd | 4932 | struct drm_i915_private *dev_priv = dev->dev_private; |
647416f9 | 4933 | int ret; |
dd624afd | 4934 | |
2f9fe5ff | 4935 | DRM_DEBUG("Dropping caches: 0x%08llx\n", val); |
dd624afd CW |
4936 | |
4937 | /* No need to check and wait for gpu resets, only libdrm auto-restarts | |
4938 | * on ioctls on -EAGAIN. */ | |
4939 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
4940 | if (ret) | |
4941 | return ret; | |
4942 | ||
4943 | if (val & DROP_ACTIVE) { | |
4944 | ret = i915_gpu_idle(dev); | |
4945 | if (ret) | |
4946 | goto unlock; | |
4947 | } | |
4948 | ||
4949 | if (val & (DROP_RETIRE | DROP_ACTIVE)) | |
c033666a | 4950 | i915_gem_retire_requests(dev_priv); |
dd624afd | 4951 | |
21ab4e74 CW |
4952 | if (val & DROP_BOUND) |
4953 | i915_gem_shrink(dev_priv, LONG_MAX, I915_SHRINK_BOUND); | |
4ad72b7f | 4954 | |
21ab4e74 CW |
4955 | if (val & DROP_UNBOUND) |
4956 | i915_gem_shrink(dev_priv, LONG_MAX, I915_SHRINK_UNBOUND); | |
dd624afd CW |
4957 | |
4958 | unlock: | |
4959 | mutex_unlock(&dev->struct_mutex); | |
4960 | ||
647416f9 | 4961 | return ret; |
dd624afd CW |
4962 | } |
4963 | ||
647416f9 KC |
4964 | DEFINE_SIMPLE_ATTRIBUTE(i915_drop_caches_fops, |
4965 | i915_drop_caches_get, i915_drop_caches_set, | |
4966 | "0x%08llx\n"); | |
dd624afd | 4967 | |
647416f9 KC |
4968 | static int |
4969 | i915_max_freq_get(void *data, u64 *val) | |
358733e9 | 4970 | { |
647416f9 | 4971 | struct drm_device *dev = data; |
e277a1f8 | 4972 | struct drm_i915_private *dev_priv = dev->dev_private; |
647416f9 | 4973 | int ret; |
004777cb | 4974 | |
daa3afb2 | 4975 | if (INTEL_INFO(dev)->gen < 6) |
004777cb DV |
4976 | return -ENODEV; |
4977 | ||
5c9669ce TR |
4978 | flush_delayed_work(&dev_priv->rps.delayed_resume_work); |
4979 | ||
4fc688ce | 4980 | ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock); |
004777cb DV |
4981 | if (ret) |
4982 | return ret; | |
358733e9 | 4983 | |
7c59a9c1 | 4984 | *val = intel_gpu_freq(dev_priv, dev_priv->rps.max_freq_softlimit); |
4fc688ce | 4985 | mutex_unlock(&dev_priv->rps.hw_lock); |
358733e9 | 4986 | |
647416f9 | 4987 | return 0; |
358733e9 JB |
4988 | } |
4989 | ||
647416f9 KC |
4990 | static int |
4991 | i915_max_freq_set(void *data, u64 val) | |
358733e9 | 4992 | { |
647416f9 | 4993 | struct drm_device *dev = data; |
358733e9 | 4994 | struct drm_i915_private *dev_priv = dev->dev_private; |
bc4d91f6 | 4995 | u32 hw_max, hw_min; |
647416f9 | 4996 | int ret; |
004777cb | 4997 | |
daa3afb2 | 4998 | if (INTEL_INFO(dev)->gen < 6) |
004777cb | 4999 | return -ENODEV; |
358733e9 | 5000 | |
5c9669ce TR |
5001 | flush_delayed_work(&dev_priv->rps.delayed_resume_work); |
5002 | ||
647416f9 | 5003 | DRM_DEBUG_DRIVER("Manually setting max freq to %llu\n", val); |
358733e9 | 5004 | |
4fc688ce | 5005 | ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock); |
004777cb DV |
5006 | if (ret) |
5007 | return ret; | |
5008 | ||
358733e9 JB |
5009 | /* |
5010 | * Turbo will still be enabled, but won't go above the set value. | |
5011 | */ | |
bc4d91f6 | 5012 | val = intel_freq_opcode(dev_priv, val); |
dd0a1aa1 | 5013 | |
bc4d91f6 AG |
5014 | hw_max = dev_priv->rps.max_freq; |
5015 | hw_min = dev_priv->rps.min_freq; | |
dd0a1aa1 | 5016 | |
b39fb297 | 5017 | if (val < hw_min || val > hw_max || val < dev_priv->rps.min_freq_softlimit) { |
dd0a1aa1 JM |
5018 | mutex_unlock(&dev_priv->rps.hw_lock); |
5019 | return -EINVAL; | |
0a073b84 JB |
5020 | } |
5021 | ||
b39fb297 | 5022 | dev_priv->rps.max_freq_softlimit = val; |
dd0a1aa1 | 5023 | |
dc97997a | 5024 | intel_set_rps(dev_priv, val); |
dd0a1aa1 | 5025 | |
4fc688ce | 5026 | mutex_unlock(&dev_priv->rps.hw_lock); |
358733e9 | 5027 | |
647416f9 | 5028 | return 0; |
358733e9 JB |
5029 | } |
5030 | ||
647416f9 KC |
5031 | DEFINE_SIMPLE_ATTRIBUTE(i915_max_freq_fops, |
5032 | i915_max_freq_get, i915_max_freq_set, | |
3a3b4f98 | 5033 | "%llu\n"); |
358733e9 | 5034 | |
647416f9 KC |
5035 | static int |
5036 | i915_min_freq_get(void *data, u64 *val) | |
1523c310 | 5037 | { |
647416f9 | 5038 | struct drm_device *dev = data; |
e277a1f8 | 5039 | struct drm_i915_private *dev_priv = dev->dev_private; |
647416f9 | 5040 | int ret; |
004777cb | 5041 | |
daa3afb2 | 5042 | if (INTEL_INFO(dev)->gen < 6) |
004777cb DV |
5043 | return -ENODEV; |
5044 | ||
5c9669ce TR |
5045 | flush_delayed_work(&dev_priv->rps.delayed_resume_work); |
5046 | ||
4fc688ce | 5047 | ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock); |
004777cb DV |
5048 | if (ret) |
5049 | return ret; | |
1523c310 | 5050 | |
7c59a9c1 | 5051 | *val = intel_gpu_freq(dev_priv, dev_priv->rps.min_freq_softlimit); |
4fc688ce | 5052 | mutex_unlock(&dev_priv->rps.hw_lock); |
1523c310 | 5053 | |
647416f9 | 5054 | return 0; |
1523c310 JB |
5055 | } |
5056 | ||
647416f9 KC |
5057 | static int |
5058 | i915_min_freq_set(void *data, u64 val) | |
1523c310 | 5059 | { |
647416f9 | 5060 | struct drm_device *dev = data; |
1523c310 | 5061 | struct drm_i915_private *dev_priv = dev->dev_private; |
bc4d91f6 | 5062 | u32 hw_max, hw_min; |
647416f9 | 5063 | int ret; |
004777cb | 5064 | |
daa3afb2 | 5065 | if (INTEL_INFO(dev)->gen < 6) |
004777cb | 5066 | return -ENODEV; |
1523c310 | 5067 | |
5c9669ce TR |
5068 | flush_delayed_work(&dev_priv->rps.delayed_resume_work); |
5069 | ||
647416f9 | 5070 | DRM_DEBUG_DRIVER("Manually setting min freq to %llu\n", val); |
1523c310 | 5071 | |
4fc688ce | 5072 | ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock); |
004777cb DV |
5073 | if (ret) |
5074 | return ret; | |
5075 | ||
1523c310 JB |
5076 | /* |
5077 | * Turbo will still be enabled, but won't go below the set value. | |
5078 | */ | |
bc4d91f6 | 5079 | val = intel_freq_opcode(dev_priv, val); |
dd0a1aa1 | 5080 | |
bc4d91f6 AG |
5081 | hw_max = dev_priv->rps.max_freq; |
5082 | hw_min = dev_priv->rps.min_freq; | |
dd0a1aa1 | 5083 | |
b39fb297 | 5084 | if (val < hw_min || val > hw_max || val > dev_priv->rps.max_freq_softlimit) { |
dd0a1aa1 JM |
5085 | mutex_unlock(&dev_priv->rps.hw_lock); |
5086 | return -EINVAL; | |
0a073b84 | 5087 | } |
dd0a1aa1 | 5088 | |
b39fb297 | 5089 | dev_priv->rps.min_freq_softlimit = val; |
dd0a1aa1 | 5090 | |
dc97997a | 5091 | intel_set_rps(dev_priv, val); |
dd0a1aa1 | 5092 | |
4fc688ce | 5093 | mutex_unlock(&dev_priv->rps.hw_lock); |
1523c310 | 5094 | |
647416f9 | 5095 | return 0; |
1523c310 JB |
5096 | } |
5097 | ||
647416f9 KC |
5098 | DEFINE_SIMPLE_ATTRIBUTE(i915_min_freq_fops, |
5099 | i915_min_freq_get, i915_min_freq_set, | |
3a3b4f98 | 5100 | "%llu\n"); |
1523c310 | 5101 | |
647416f9 KC |
5102 | static int |
5103 | i915_cache_sharing_get(void *data, u64 *val) | |
07b7ddd9 | 5104 | { |
647416f9 | 5105 | struct drm_device *dev = data; |
e277a1f8 | 5106 | struct drm_i915_private *dev_priv = dev->dev_private; |
07b7ddd9 | 5107 | u32 snpcr; |
647416f9 | 5108 | int ret; |
07b7ddd9 | 5109 | |
004777cb DV |
5110 | if (!(IS_GEN6(dev) || IS_GEN7(dev))) |
5111 | return -ENODEV; | |
5112 | ||
22bcfc6a DV |
5113 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
5114 | if (ret) | |
5115 | return ret; | |
c8c8fb33 | 5116 | intel_runtime_pm_get(dev_priv); |
22bcfc6a | 5117 | |
07b7ddd9 | 5118 | snpcr = I915_READ(GEN6_MBCUNIT_SNPCR); |
c8c8fb33 PZ |
5119 | |
5120 | intel_runtime_pm_put(dev_priv); | |
07b7ddd9 JB |
5121 | mutex_unlock(&dev_priv->dev->struct_mutex); |
5122 | ||
647416f9 | 5123 | *val = (snpcr & GEN6_MBC_SNPCR_MASK) >> GEN6_MBC_SNPCR_SHIFT; |
07b7ddd9 | 5124 | |
647416f9 | 5125 | return 0; |
07b7ddd9 JB |
5126 | } |
5127 | ||
647416f9 KC |
5128 | static int |
5129 | i915_cache_sharing_set(void *data, u64 val) | |
07b7ddd9 | 5130 | { |
647416f9 | 5131 | struct drm_device *dev = data; |
07b7ddd9 | 5132 | struct drm_i915_private *dev_priv = dev->dev_private; |
07b7ddd9 | 5133 | u32 snpcr; |
07b7ddd9 | 5134 | |
004777cb DV |
5135 | if (!(IS_GEN6(dev) || IS_GEN7(dev))) |
5136 | return -ENODEV; | |
5137 | ||
647416f9 | 5138 | if (val > 3) |
07b7ddd9 JB |
5139 | return -EINVAL; |
5140 | ||
c8c8fb33 | 5141 | intel_runtime_pm_get(dev_priv); |
647416f9 | 5142 | DRM_DEBUG_DRIVER("Manually setting uncore sharing to %llu\n", val); |
07b7ddd9 JB |
5143 | |
5144 | /* Update the cache sharing policy here as well */ | |
5145 | snpcr = I915_READ(GEN6_MBCUNIT_SNPCR); | |
5146 | snpcr &= ~GEN6_MBC_SNPCR_MASK; | |
5147 | snpcr |= (val << GEN6_MBC_SNPCR_SHIFT); | |
5148 | I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr); | |
5149 | ||
c8c8fb33 | 5150 | intel_runtime_pm_put(dev_priv); |
647416f9 | 5151 | return 0; |
07b7ddd9 JB |
5152 | } |
5153 | ||
647416f9 KC |
5154 | DEFINE_SIMPLE_ATTRIBUTE(i915_cache_sharing_fops, |
5155 | i915_cache_sharing_get, i915_cache_sharing_set, | |
5156 | "%llu\n"); | |
07b7ddd9 | 5157 | |
5d39525a JM |
5158 | struct sseu_dev_status { |
5159 | unsigned int slice_total; | |
5160 | unsigned int subslice_total; | |
5161 | unsigned int subslice_per_slice; | |
5162 | unsigned int eu_total; | |
5163 | unsigned int eu_per_subslice; | |
5164 | }; | |
5165 | ||
5166 | static void cherryview_sseu_device_status(struct drm_device *dev, | |
5167 | struct sseu_dev_status *stat) | |
5168 | { | |
5169 | struct drm_i915_private *dev_priv = dev->dev_private; | |
0a0b457f | 5170 | int ss_max = 2; |
5d39525a JM |
5171 | int ss; |
5172 | u32 sig1[ss_max], sig2[ss_max]; | |
5173 | ||
5174 | sig1[0] = I915_READ(CHV_POWER_SS0_SIG1); | |
5175 | sig1[1] = I915_READ(CHV_POWER_SS1_SIG1); | |
5176 | sig2[0] = I915_READ(CHV_POWER_SS0_SIG2); | |
5177 | sig2[1] = I915_READ(CHV_POWER_SS1_SIG2); | |
5178 | ||
5179 | for (ss = 0; ss < ss_max; ss++) { | |
5180 | unsigned int eu_cnt; | |
5181 | ||
5182 | if (sig1[ss] & CHV_SS_PG_ENABLE) | |
5183 | /* skip disabled subslice */ | |
5184 | continue; | |
5185 | ||
5186 | stat->slice_total = 1; | |
5187 | stat->subslice_per_slice++; | |
5188 | eu_cnt = ((sig1[ss] & CHV_EU08_PG_ENABLE) ? 0 : 2) + | |
5189 | ((sig1[ss] & CHV_EU19_PG_ENABLE) ? 0 : 2) + | |
5190 | ((sig1[ss] & CHV_EU210_PG_ENABLE) ? 0 : 2) + | |
5191 | ((sig2[ss] & CHV_EU311_PG_ENABLE) ? 0 : 2); | |
5192 | stat->eu_total += eu_cnt; | |
5193 | stat->eu_per_subslice = max(stat->eu_per_subslice, eu_cnt); | |
5194 | } | |
5195 | stat->subslice_total = stat->subslice_per_slice; | |
5196 | } | |
5197 | ||
5198 | static void gen9_sseu_device_status(struct drm_device *dev, | |
5199 | struct sseu_dev_status *stat) | |
5200 | { | |
5201 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1c046bc1 | 5202 | int s_max = 3, ss_max = 4; |
5d39525a JM |
5203 | int s, ss; |
5204 | u32 s_reg[s_max], eu_reg[2*s_max], eu_mask[2]; | |
5205 | ||
1c046bc1 JM |
5206 | /* BXT has a single slice and at most 3 subslices. */ |
5207 | if (IS_BROXTON(dev)) { | |
5208 | s_max = 1; | |
5209 | ss_max = 3; | |
5210 | } | |
5211 | ||
5212 | for (s = 0; s < s_max; s++) { | |
5213 | s_reg[s] = I915_READ(GEN9_SLICE_PGCTL_ACK(s)); | |
5214 | eu_reg[2*s] = I915_READ(GEN9_SS01_EU_PGCTL_ACK(s)); | |
5215 | eu_reg[2*s + 1] = I915_READ(GEN9_SS23_EU_PGCTL_ACK(s)); | |
5216 | } | |
5217 | ||
5d39525a JM |
5218 | eu_mask[0] = GEN9_PGCTL_SSA_EU08_ACK | |
5219 | GEN9_PGCTL_SSA_EU19_ACK | | |
5220 | GEN9_PGCTL_SSA_EU210_ACK | | |
5221 | GEN9_PGCTL_SSA_EU311_ACK; | |
5222 | eu_mask[1] = GEN9_PGCTL_SSB_EU08_ACK | | |
5223 | GEN9_PGCTL_SSB_EU19_ACK | | |
5224 | GEN9_PGCTL_SSB_EU210_ACK | | |
5225 | GEN9_PGCTL_SSB_EU311_ACK; | |
5226 | ||
5227 | for (s = 0; s < s_max; s++) { | |
1c046bc1 JM |
5228 | unsigned int ss_cnt = 0; |
5229 | ||
5d39525a JM |
5230 | if ((s_reg[s] & GEN9_PGCTL_SLICE_ACK) == 0) |
5231 | /* skip disabled slice */ | |
5232 | continue; | |
5233 | ||
5234 | stat->slice_total++; | |
1c046bc1 | 5235 | |
ef11bdb3 | 5236 | if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) |
1c046bc1 JM |
5237 | ss_cnt = INTEL_INFO(dev)->subslice_per_slice; |
5238 | ||
5d39525a JM |
5239 | for (ss = 0; ss < ss_max; ss++) { |
5240 | unsigned int eu_cnt; | |
5241 | ||
1c046bc1 JM |
5242 | if (IS_BROXTON(dev) && |
5243 | !(s_reg[s] & (GEN9_PGCTL_SS_ACK(ss)))) | |
5244 | /* skip disabled subslice */ | |
5245 | continue; | |
5246 | ||
5247 | if (IS_BROXTON(dev)) | |
5248 | ss_cnt++; | |
5249 | ||
5d39525a JM |
5250 | eu_cnt = 2 * hweight32(eu_reg[2*s + ss/2] & |
5251 | eu_mask[ss%2]); | |
5252 | stat->eu_total += eu_cnt; | |
5253 | stat->eu_per_subslice = max(stat->eu_per_subslice, | |
5254 | eu_cnt); | |
5255 | } | |
1c046bc1 JM |
5256 | |
5257 | stat->subslice_total += ss_cnt; | |
5258 | stat->subslice_per_slice = max(stat->subslice_per_slice, | |
5259 | ss_cnt); | |
5d39525a JM |
5260 | } |
5261 | } | |
5262 | ||
91bedd34 ŁD |
5263 | static void broadwell_sseu_device_status(struct drm_device *dev, |
5264 | struct sseu_dev_status *stat) | |
5265 | { | |
5266 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5267 | int s; | |
5268 | u32 slice_info = I915_READ(GEN8_GT_SLICE_INFO); | |
5269 | ||
5270 | stat->slice_total = hweight32(slice_info & GEN8_LSLICESTAT_MASK); | |
5271 | ||
5272 | if (stat->slice_total) { | |
5273 | stat->subslice_per_slice = INTEL_INFO(dev)->subslice_per_slice; | |
5274 | stat->subslice_total = stat->slice_total * | |
5275 | stat->subslice_per_slice; | |
5276 | stat->eu_per_subslice = INTEL_INFO(dev)->eu_per_subslice; | |
5277 | stat->eu_total = stat->eu_per_subslice * stat->subslice_total; | |
5278 | ||
5279 | /* subtract fused off EU(s) from enabled slice(s) */ | |
5280 | for (s = 0; s < stat->slice_total; s++) { | |
5281 | u8 subslice_7eu = INTEL_INFO(dev)->subslice_7eu[s]; | |
5282 | ||
5283 | stat->eu_total -= hweight8(subslice_7eu); | |
5284 | } | |
5285 | } | |
5286 | } | |
5287 | ||
3873218f JM |
5288 | static int i915_sseu_status(struct seq_file *m, void *unused) |
5289 | { | |
5290 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
5291 | struct drm_device *dev = node->minor->dev; | |
5d39525a | 5292 | struct sseu_dev_status stat; |
3873218f | 5293 | |
91bedd34 | 5294 | if (INTEL_INFO(dev)->gen < 8) |
3873218f JM |
5295 | return -ENODEV; |
5296 | ||
5297 | seq_puts(m, "SSEU Device Info\n"); | |
5298 | seq_printf(m, " Available Slice Total: %u\n", | |
5299 | INTEL_INFO(dev)->slice_total); | |
5300 | seq_printf(m, " Available Subslice Total: %u\n", | |
5301 | INTEL_INFO(dev)->subslice_total); | |
5302 | seq_printf(m, " Available Subslice Per Slice: %u\n", | |
5303 | INTEL_INFO(dev)->subslice_per_slice); | |
5304 | seq_printf(m, " Available EU Total: %u\n", | |
5305 | INTEL_INFO(dev)->eu_total); | |
5306 | seq_printf(m, " Available EU Per Subslice: %u\n", | |
5307 | INTEL_INFO(dev)->eu_per_subslice); | |
5308 | seq_printf(m, " Has Slice Power Gating: %s\n", | |
5309 | yesno(INTEL_INFO(dev)->has_slice_pg)); | |
5310 | seq_printf(m, " Has Subslice Power Gating: %s\n", | |
5311 | yesno(INTEL_INFO(dev)->has_subslice_pg)); | |
5312 | seq_printf(m, " Has EU Power Gating: %s\n", | |
5313 | yesno(INTEL_INFO(dev)->has_eu_pg)); | |
5314 | ||
7f992aba | 5315 | seq_puts(m, "SSEU Device Status\n"); |
5d39525a | 5316 | memset(&stat, 0, sizeof(stat)); |
5575f03a | 5317 | if (IS_CHERRYVIEW(dev)) { |
5d39525a | 5318 | cherryview_sseu_device_status(dev, &stat); |
91bedd34 ŁD |
5319 | } else if (IS_BROADWELL(dev)) { |
5320 | broadwell_sseu_device_status(dev, &stat); | |
1c046bc1 | 5321 | } else if (INTEL_INFO(dev)->gen >= 9) { |
5d39525a | 5322 | gen9_sseu_device_status(dev, &stat); |
7f992aba | 5323 | } |
5d39525a JM |
5324 | seq_printf(m, " Enabled Slice Total: %u\n", |
5325 | stat.slice_total); | |
5326 | seq_printf(m, " Enabled Subslice Total: %u\n", | |
5327 | stat.subslice_total); | |
5328 | seq_printf(m, " Enabled Subslice Per Slice: %u\n", | |
5329 | stat.subslice_per_slice); | |
5330 | seq_printf(m, " Enabled EU Total: %u\n", | |
5331 | stat.eu_total); | |
5332 | seq_printf(m, " Enabled EU Per Subslice: %u\n", | |
5333 | stat.eu_per_subslice); | |
7f992aba | 5334 | |
3873218f JM |
5335 | return 0; |
5336 | } | |
5337 | ||
6d794d42 BW |
5338 | static int i915_forcewake_open(struct inode *inode, struct file *file) |
5339 | { | |
5340 | struct drm_device *dev = inode->i_private; | |
5341 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6d794d42 | 5342 | |
075edca4 | 5343 | if (INTEL_INFO(dev)->gen < 6) |
6d794d42 BW |
5344 | return 0; |
5345 | ||
6daccb0b | 5346 | intel_runtime_pm_get(dev_priv); |
59bad947 | 5347 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); |
6d794d42 BW |
5348 | |
5349 | return 0; | |
5350 | } | |
5351 | ||
c43b5634 | 5352 | static int i915_forcewake_release(struct inode *inode, struct file *file) |
6d794d42 BW |
5353 | { |
5354 | struct drm_device *dev = inode->i_private; | |
5355 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5356 | ||
075edca4 | 5357 | if (INTEL_INFO(dev)->gen < 6) |
6d794d42 BW |
5358 | return 0; |
5359 | ||
59bad947 | 5360 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); |
6daccb0b | 5361 | intel_runtime_pm_put(dev_priv); |
6d794d42 BW |
5362 | |
5363 | return 0; | |
5364 | } | |
5365 | ||
5366 | static const struct file_operations i915_forcewake_fops = { | |
5367 | .owner = THIS_MODULE, | |
5368 | .open = i915_forcewake_open, | |
5369 | .release = i915_forcewake_release, | |
5370 | }; | |
5371 | ||
5372 | static int i915_forcewake_create(struct dentry *root, struct drm_minor *minor) | |
5373 | { | |
5374 | struct drm_device *dev = minor->dev; | |
5375 | struct dentry *ent; | |
5376 | ||
5377 | ent = debugfs_create_file("i915_forcewake_user", | |
8eb57294 | 5378 | S_IRUSR, |
6d794d42 BW |
5379 | root, dev, |
5380 | &i915_forcewake_fops); | |
f3c5fe97 WY |
5381 | if (!ent) |
5382 | return -ENOMEM; | |
6d794d42 | 5383 | |
8eb57294 | 5384 | return drm_add_fake_info_node(minor, ent, &i915_forcewake_fops); |
6d794d42 BW |
5385 | } |
5386 | ||
6a9c308d DV |
5387 | static int i915_debugfs_create(struct dentry *root, |
5388 | struct drm_minor *minor, | |
5389 | const char *name, | |
5390 | const struct file_operations *fops) | |
07b7ddd9 JB |
5391 | { |
5392 | struct drm_device *dev = minor->dev; | |
5393 | struct dentry *ent; | |
5394 | ||
6a9c308d | 5395 | ent = debugfs_create_file(name, |
07b7ddd9 JB |
5396 | S_IRUGO | S_IWUSR, |
5397 | root, dev, | |
6a9c308d | 5398 | fops); |
f3c5fe97 WY |
5399 | if (!ent) |
5400 | return -ENOMEM; | |
07b7ddd9 | 5401 | |
6a9c308d | 5402 | return drm_add_fake_info_node(minor, ent, fops); |
07b7ddd9 JB |
5403 | } |
5404 | ||
06c5bf8c | 5405 | static const struct drm_info_list i915_debugfs_list[] = { |
311bd68e | 5406 | {"i915_capabilities", i915_capabilities, 0}, |
73aa808f | 5407 | {"i915_gem_objects", i915_gem_object_info, 0}, |
08c18323 | 5408 | {"i915_gem_gtt", i915_gem_gtt_info, 0}, |
1b50247a | 5409 | {"i915_gem_pinned", i915_gem_gtt_info, 0, (void *) PINNED_LIST}, |
433e12f7 | 5410 | {"i915_gem_active", i915_gem_object_list_info, 0, (void *) ACTIVE_LIST}, |
433e12f7 | 5411 | {"i915_gem_inactive", i915_gem_object_list_info, 0, (void *) INACTIVE_LIST}, |
6d2b8885 | 5412 | {"i915_gem_stolen", i915_gem_stolen_list_info }, |
4e5359cd | 5413 | {"i915_gem_pageflip", i915_gem_pageflip_info, 0}, |
2017263e BG |
5414 | {"i915_gem_request", i915_gem_request_info, 0}, |
5415 | {"i915_gem_seqno", i915_gem_seqno_info, 0}, | |
a6172a80 | 5416 | {"i915_gem_fence_regs", i915_gem_fence_regs_info, 0}, |
2017263e | 5417 | {"i915_gem_interrupt", i915_interrupt_info, 0}, |
1ec14ad3 CW |
5418 | {"i915_gem_hws", i915_hws_info, 0, (void *)RCS}, |
5419 | {"i915_gem_hws_blt", i915_hws_info, 0, (void *)BCS}, | |
5420 | {"i915_gem_hws_bsd", i915_hws_info, 0, (void *)VCS}, | |
9010ebfd | 5421 | {"i915_gem_hws_vebox", i915_hws_info, 0, (void *)VECS}, |
493018dc | 5422 | {"i915_gem_batch_pool", i915_gem_batch_pool_info, 0}, |
8b417c26 | 5423 | {"i915_guc_info", i915_guc_info, 0}, |
fdf5d357 | 5424 | {"i915_guc_load_status", i915_guc_load_status_info, 0}, |
4c7e77fc | 5425 | {"i915_guc_log_dump", i915_guc_log_dump, 0}, |
adb4bd12 | 5426 | {"i915_frequency_info", i915_frequency_info, 0}, |
f654449a | 5427 | {"i915_hangcheck_info", i915_hangcheck_info, 0}, |
f97108d1 | 5428 | {"i915_drpc_info", i915_drpc_info, 0}, |
7648fa99 | 5429 | {"i915_emon_status", i915_emon_status, 0}, |
23b2f8bb | 5430 | {"i915_ring_freq_table", i915_ring_freq_table, 0}, |
9a851789 | 5431 | {"i915_frontbuffer_tracking", i915_frontbuffer_tracking, 0}, |
b5e50c3f | 5432 | {"i915_fbc_status", i915_fbc_status, 0}, |
92d44621 | 5433 | {"i915_ips_status", i915_ips_status, 0}, |
4a9bef37 | 5434 | {"i915_sr_status", i915_sr_status, 0}, |
44834a67 | 5435 | {"i915_opregion", i915_opregion, 0}, |
ada8f955 | 5436 | {"i915_vbt", i915_vbt, 0}, |
37811fcc | 5437 | {"i915_gem_framebuffer", i915_gem_framebuffer_info, 0}, |
e76d3630 | 5438 | {"i915_context_status", i915_context_status, 0}, |
c0ab1ae9 | 5439 | {"i915_dump_lrc", i915_dump_lrc, 0}, |
4ba70e44 | 5440 | {"i915_execlists", i915_execlists, 0}, |
f65367b5 | 5441 | {"i915_forcewake_domains", i915_forcewake_domains, 0}, |
ea16a3cd | 5442 | {"i915_swizzle_info", i915_swizzle_info, 0}, |
3cf17fc5 | 5443 | {"i915_ppgtt_info", i915_ppgtt_info, 0}, |
63573eb7 | 5444 | {"i915_llc", i915_llc, 0}, |
e91fd8c6 | 5445 | {"i915_edp_psr_status", i915_edp_psr_status, 0}, |
d2e216d0 | 5446 | {"i915_sink_crc_eDP1", i915_sink_crc, 0}, |
ec013e7f | 5447 | {"i915_energy_uJ", i915_energy_uJ, 0}, |
6455c870 | 5448 | {"i915_runtime_pm_status", i915_runtime_pm_status, 0}, |
1da51581 | 5449 | {"i915_power_domain_info", i915_power_domain_info, 0}, |
b7cec66d | 5450 | {"i915_dmc_info", i915_dmc_info, 0}, |
53f5e3ca | 5451 | {"i915_display_info", i915_display_info, 0}, |
e04934cf | 5452 | {"i915_semaphore_status", i915_semaphore_status, 0}, |
728e29d7 | 5453 | {"i915_shared_dplls_info", i915_shared_dplls_info, 0}, |
11bed958 | 5454 | {"i915_dp_mst_info", i915_dp_mst_info, 0}, |
1ed1ef9d | 5455 | {"i915_wa_registers", i915_wa_registers, 0}, |
c5511e44 | 5456 | {"i915_ddb_info", i915_ddb_info, 0}, |
3873218f | 5457 | {"i915_sseu_status", i915_sseu_status, 0}, |
a54746e3 | 5458 | {"i915_drrs_status", i915_drrs_status, 0}, |
1854d5ca | 5459 | {"i915_rps_boost_info", i915_rps_boost_info, 0}, |
2017263e | 5460 | }; |
27c202ad | 5461 | #define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list) |
2017263e | 5462 | |
06c5bf8c | 5463 | static const struct i915_debugfs_files { |
34b9674c DV |
5464 | const char *name; |
5465 | const struct file_operations *fops; | |
5466 | } i915_debugfs_files[] = { | |
5467 | {"i915_wedged", &i915_wedged_fops}, | |
5468 | {"i915_max_freq", &i915_max_freq_fops}, | |
5469 | {"i915_min_freq", &i915_min_freq_fops}, | |
5470 | {"i915_cache_sharing", &i915_cache_sharing_fops}, | |
5471 | {"i915_ring_stop", &i915_ring_stop_fops}, | |
094f9a54 CW |
5472 | {"i915_ring_missed_irq", &i915_ring_missed_irq_fops}, |
5473 | {"i915_ring_test_irq", &i915_ring_test_irq_fops}, | |
34b9674c DV |
5474 | {"i915_gem_drop_caches", &i915_drop_caches_fops}, |
5475 | {"i915_error_state", &i915_error_state_fops}, | |
5476 | {"i915_next_seqno", &i915_next_seqno_fops}, | |
bd9db02f | 5477 | {"i915_display_crc_ctl", &i915_display_crc_ctl_fops}, |
369a1342 VS |
5478 | {"i915_pri_wm_latency", &i915_pri_wm_latency_fops}, |
5479 | {"i915_spr_wm_latency", &i915_spr_wm_latency_fops}, | |
5480 | {"i915_cur_wm_latency", &i915_cur_wm_latency_fops}, | |
da46f936 | 5481 | {"i915_fbc_false_color", &i915_fbc_fc_fops}, |
eb3394fa TP |
5482 | {"i915_dp_test_data", &i915_displayport_test_data_fops}, |
5483 | {"i915_dp_test_type", &i915_displayport_test_type_fops}, | |
5484 | {"i915_dp_test_active", &i915_displayport_test_active_fops} | |
34b9674c DV |
5485 | }; |
5486 | ||
07144428 DL |
5487 | void intel_display_crc_init(struct drm_device *dev) |
5488 | { | |
5489 | struct drm_i915_private *dev_priv = dev->dev_private; | |
b378360e | 5490 | enum pipe pipe; |
07144428 | 5491 | |
055e393f | 5492 | for_each_pipe(dev_priv, pipe) { |
b378360e | 5493 | struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe]; |
07144428 | 5494 | |
d538bbdf DL |
5495 | pipe_crc->opened = false; |
5496 | spin_lock_init(&pipe_crc->lock); | |
07144428 DL |
5497 | init_waitqueue_head(&pipe_crc->wq); |
5498 | } | |
5499 | } | |
5500 | ||
27c202ad | 5501 | int i915_debugfs_init(struct drm_minor *minor) |
2017263e | 5502 | { |
34b9674c | 5503 | int ret, i; |
f3cd474b | 5504 | |
6d794d42 | 5505 | ret = i915_forcewake_create(minor->debugfs_root, minor); |
358733e9 JB |
5506 | if (ret) |
5507 | return ret; | |
6a9c308d | 5508 | |
07144428 DL |
5509 | for (i = 0; i < ARRAY_SIZE(i915_pipe_crc_data); i++) { |
5510 | ret = i915_pipe_crc_create(minor->debugfs_root, minor, i); | |
5511 | if (ret) | |
5512 | return ret; | |
5513 | } | |
5514 | ||
34b9674c DV |
5515 | for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) { |
5516 | ret = i915_debugfs_create(minor->debugfs_root, minor, | |
5517 | i915_debugfs_files[i].name, | |
5518 | i915_debugfs_files[i].fops); | |
5519 | if (ret) | |
5520 | return ret; | |
5521 | } | |
40633219 | 5522 | |
27c202ad BG |
5523 | return drm_debugfs_create_files(i915_debugfs_list, |
5524 | I915_DEBUGFS_ENTRIES, | |
2017263e BG |
5525 | minor->debugfs_root, minor); |
5526 | } | |
5527 | ||
27c202ad | 5528 | void i915_debugfs_cleanup(struct drm_minor *minor) |
2017263e | 5529 | { |
34b9674c DV |
5530 | int i; |
5531 | ||
27c202ad BG |
5532 | drm_debugfs_remove_files(i915_debugfs_list, |
5533 | I915_DEBUGFS_ENTRIES, minor); | |
07144428 | 5534 | |
6d794d42 BW |
5535 | drm_debugfs_remove_files((struct drm_info_list *) &i915_forcewake_fops, |
5536 | 1, minor); | |
07144428 | 5537 | |
e309a997 | 5538 | for (i = 0; i < ARRAY_SIZE(i915_pipe_crc_data); i++) { |
07144428 DL |
5539 | struct drm_info_list *info_list = |
5540 | (struct drm_info_list *)&i915_pipe_crc_data[i]; | |
5541 | ||
5542 | drm_debugfs_remove_files(info_list, 1, minor); | |
5543 | } | |
5544 | ||
34b9674c DV |
5545 | for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) { |
5546 | struct drm_info_list *info_list = | |
5547 | (struct drm_info_list *) i915_debugfs_files[i].fops; | |
5548 | ||
5549 | drm_debugfs_remove_files(info_list, 1, minor); | |
5550 | } | |
2017263e | 5551 | } |
aa7471d2 JN |
5552 | |
5553 | struct dpcd_block { | |
5554 | /* DPCD dump start address. */ | |
5555 | unsigned int offset; | |
5556 | /* DPCD dump end address, inclusive. If unset, .size will be used. */ | |
5557 | unsigned int end; | |
5558 | /* DPCD dump size. Used if .end is unset. If unset, defaults to 1. */ | |
5559 | size_t size; | |
5560 | /* Only valid for eDP. */ | |
5561 | bool edp; | |
5562 | }; | |
5563 | ||
5564 | static const struct dpcd_block i915_dpcd_debug[] = { | |
5565 | { .offset = DP_DPCD_REV, .size = DP_RECEIVER_CAP_SIZE }, | |
5566 | { .offset = DP_PSR_SUPPORT, .end = DP_PSR_CAPS }, | |
5567 | { .offset = DP_DOWNSTREAM_PORT_0, .size = 16 }, | |
5568 | { .offset = DP_LINK_BW_SET, .end = DP_EDP_CONFIGURATION_SET }, | |
5569 | { .offset = DP_SINK_COUNT, .end = DP_ADJUST_REQUEST_LANE2_3 }, | |
5570 | { .offset = DP_SET_POWER }, | |
5571 | { .offset = DP_EDP_DPCD_REV }, | |
5572 | { .offset = DP_EDP_GENERAL_CAP_1, .end = DP_EDP_GENERAL_CAP_3 }, | |
5573 | { .offset = DP_EDP_DISPLAY_CONTROL_REGISTER, .end = DP_EDP_BACKLIGHT_FREQ_CAP_MAX_LSB }, | |
5574 | { .offset = DP_EDP_DBC_MINIMUM_BRIGHTNESS_SET, .end = DP_EDP_DBC_MAXIMUM_BRIGHTNESS_SET }, | |
5575 | }; | |
5576 | ||
5577 | static int i915_dpcd_show(struct seq_file *m, void *data) | |
5578 | { | |
5579 | struct drm_connector *connector = m->private; | |
5580 | struct intel_dp *intel_dp = | |
5581 | enc_to_intel_dp(&intel_attached_encoder(connector)->base); | |
5582 | uint8_t buf[16]; | |
5583 | ssize_t err; | |
5584 | int i; | |
5585 | ||
5c1a8875 MK |
5586 | if (connector->status != connector_status_connected) |
5587 | return -ENODEV; | |
5588 | ||
aa7471d2 JN |
5589 | for (i = 0; i < ARRAY_SIZE(i915_dpcd_debug); i++) { |
5590 | const struct dpcd_block *b = &i915_dpcd_debug[i]; | |
5591 | size_t size = b->end ? b->end - b->offset + 1 : (b->size ?: 1); | |
5592 | ||
5593 | if (b->edp && | |
5594 | connector->connector_type != DRM_MODE_CONNECTOR_eDP) | |
5595 | continue; | |
5596 | ||
5597 | /* low tech for now */ | |
5598 | if (WARN_ON(size > sizeof(buf))) | |
5599 | continue; | |
5600 | ||
5601 | err = drm_dp_dpcd_read(&intel_dp->aux, b->offset, buf, size); | |
5602 | if (err <= 0) { | |
5603 | DRM_ERROR("dpcd read (%zu bytes at %u) failed (%zd)\n", | |
5604 | size, b->offset, err); | |
5605 | continue; | |
5606 | } | |
5607 | ||
5608 | seq_printf(m, "%04x: %*ph\n", b->offset, (int) size, buf); | |
b3f9d7d7 | 5609 | } |
aa7471d2 JN |
5610 | |
5611 | return 0; | |
5612 | } | |
5613 | ||
5614 | static int i915_dpcd_open(struct inode *inode, struct file *file) | |
5615 | { | |
5616 | return single_open(file, i915_dpcd_show, inode->i_private); | |
5617 | } | |
5618 | ||
5619 | static const struct file_operations i915_dpcd_fops = { | |
5620 | .owner = THIS_MODULE, | |
5621 | .open = i915_dpcd_open, | |
5622 | .read = seq_read, | |
5623 | .llseek = seq_lseek, | |
5624 | .release = single_release, | |
5625 | }; | |
5626 | ||
5627 | /** | |
5628 | * i915_debugfs_connector_add - add i915 specific connector debugfs files | |
5629 | * @connector: pointer to a registered drm_connector | |
5630 | * | |
5631 | * Cleanup will be done by drm_connector_unregister() through a call to | |
5632 | * drm_debugfs_connector_remove(). | |
5633 | * | |
5634 | * Returns 0 on success, negative error codes on error. | |
5635 | */ | |
5636 | int i915_debugfs_connector_add(struct drm_connector *connector) | |
5637 | { | |
5638 | struct dentry *root = connector->debugfs_entry; | |
5639 | ||
5640 | /* The connector must have been registered beforehands. */ | |
5641 | if (!root) | |
5642 | return -ENODEV; | |
5643 | ||
5644 | if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort || | |
5645 | connector->connector_type == DRM_MODE_CONNECTOR_eDP) | |
5646 | debugfs_create_file("i915_dpcd", S_IRUGO, root, connector, | |
5647 | &i915_dpcd_fops); | |
5648 | ||
5649 | return 0; | |
5650 | } |