Commit | Line | Data |
---|---|---|
2017263e BG |
1 | /* |
2 | * Copyright © 2008 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | * Keith Packard <keithp@keithp.com> | |
26 | * | |
27 | */ | |
28 | ||
29 | #include <linux/seq_file.h> | |
f3cd474b | 30 | #include <linux/debugfs.h> |
5a0e3ad6 | 31 | #include <linux/slab.h> |
2017263e BG |
32 | #include "drmP.h" |
33 | #include "drm.h" | |
4e5359cd | 34 | #include "intel_drv.h" |
2017263e BG |
35 | #include "i915_drm.h" |
36 | #include "i915_drv.h" | |
37 | ||
38 | #define DRM_I915_RING_DEBUG 1 | |
39 | ||
40 | ||
41 | #if defined(CONFIG_DEBUG_FS) | |
42 | ||
f13d3f73 CW |
43 | enum { |
44 | RENDER_LIST, | |
45 | BSD_LIST, | |
46 | FLUSHING_LIST, | |
47 | INACTIVE_LIST, | |
48 | PINNED_LIST | |
49 | }; | |
2017263e | 50 | |
70d39fe4 CW |
51 | static const char *yesno(int v) |
52 | { | |
53 | return v ? "yes" : "no"; | |
54 | } | |
55 | ||
56 | static int i915_capabilities(struct seq_file *m, void *data) | |
57 | { | |
58 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
59 | struct drm_device *dev = node->minor->dev; | |
60 | const struct intel_device_info *info = INTEL_INFO(dev); | |
61 | ||
62 | seq_printf(m, "gen: %d\n", info->gen); | |
63 | #define B(x) seq_printf(m, #x ": %s\n", yesno(info->x)) | |
64 | B(is_mobile); | |
70d39fe4 CW |
65 | B(is_i85x); |
66 | B(is_i915g); | |
70d39fe4 | 67 | B(is_i945gm); |
70d39fe4 CW |
68 | B(is_g33); |
69 | B(need_gfx_hws); | |
70 | B(is_g4x); | |
71 | B(is_pineview); | |
72 | B(is_broadwater); | |
73 | B(is_crestline); | |
74 | B(is_ironlake); | |
75 | B(has_fbc); | |
76 | B(has_rc6); | |
77 | B(has_pipe_cxsr); | |
78 | B(has_hotplug); | |
79 | B(cursor_needs_physical); | |
80 | B(has_overlay); | |
81 | B(overlay_needs_physical); | |
a6c45cf0 | 82 | B(supports_tv); |
70d39fe4 CW |
83 | #undef B |
84 | ||
85 | return 0; | |
86 | } | |
87 | ||
a6172a80 CW |
88 | static const char *get_pin_flag(struct drm_i915_gem_object *obj_priv) |
89 | { | |
90 | if (obj_priv->user_pin_count > 0) | |
91 | return "P"; | |
92 | else if (obj_priv->pin_count > 0) | |
93 | return "p"; | |
94 | else | |
95 | return " "; | |
96 | } | |
97 | ||
98 | static const char *get_tiling_flag(struct drm_i915_gem_object *obj_priv) | |
99 | { | |
100 | switch (obj_priv->tiling_mode) { | |
101 | default: | |
102 | case I915_TILING_NONE: return " "; | |
103 | case I915_TILING_X: return "X"; | |
104 | case I915_TILING_Y: return "Y"; | |
105 | } | |
106 | } | |
107 | ||
37811fcc CW |
108 | static void |
109 | describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj) | |
110 | { | |
111 | seq_printf(m, "%p: %s%s %8zd %08x %08x %d%s%s", | |
112 | &obj->base, | |
113 | get_pin_flag(obj), | |
114 | get_tiling_flag(obj), | |
115 | obj->base.size, | |
116 | obj->base.read_domains, | |
117 | obj->base.write_domain, | |
118 | obj->last_rendering_seqno, | |
119 | obj->dirty ? " dirty" : "", | |
120 | obj->madv == I915_MADV_DONTNEED ? " purgeable" : ""); | |
121 | if (obj->base.name) | |
122 | seq_printf(m, " (name: %d)", obj->base.name); | |
123 | if (obj->fence_reg != I915_FENCE_REG_NONE) | |
124 | seq_printf(m, " (fence: %d)", obj->fence_reg); | |
125 | if (obj->gtt_space != NULL) | |
126 | seq_printf(m, " (gtt_offset: %08x)", obj->gtt_offset); | |
127 | } | |
128 | ||
433e12f7 | 129 | static int i915_gem_object_list_info(struct seq_file *m, void *data) |
2017263e BG |
130 | { |
131 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
433e12f7 BG |
132 | uintptr_t list = (uintptr_t) node->info_ent->data; |
133 | struct list_head *head; | |
2017263e BG |
134 | struct drm_device *dev = node->minor->dev; |
135 | drm_i915_private_t *dev_priv = dev->dev_private; | |
136 | struct drm_i915_gem_object *obj_priv; | |
de227ef0 CW |
137 | int ret; |
138 | ||
139 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
140 | if (ret) | |
141 | return ret; | |
2017263e | 142 | |
433e12f7 | 143 | switch (list) { |
82690bba CW |
144 | case RENDER_LIST: |
145 | seq_printf(m, "Render:\n"); | |
852835f3 | 146 | head = &dev_priv->render_ring.active_list; |
433e12f7 | 147 | break; |
82690bba CW |
148 | case BSD_LIST: |
149 | seq_printf(m, "BSD:\n"); | |
150 | head = &dev_priv->bsd_ring.active_list; | |
151 | break; | |
433e12f7 | 152 | case INACTIVE_LIST: |
a17458fc | 153 | seq_printf(m, "Inactive:\n"); |
433e12f7 BG |
154 | head = &dev_priv->mm.inactive_list; |
155 | break; | |
f13d3f73 CW |
156 | case PINNED_LIST: |
157 | seq_printf(m, "Pinned:\n"); | |
158 | head = &dev_priv->mm.pinned_list; | |
159 | break; | |
433e12f7 BG |
160 | case FLUSHING_LIST: |
161 | seq_printf(m, "Flushing:\n"); | |
162 | head = &dev_priv->mm.flushing_list; | |
163 | break; | |
164 | default: | |
de227ef0 CW |
165 | mutex_unlock(&dev->struct_mutex); |
166 | return -EINVAL; | |
2017263e | 167 | } |
2017263e | 168 | |
de227ef0 | 169 | list_for_each_entry(obj_priv, head, list) { |
37811fcc CW |
170 | seq_printf(m, " "); |
171 | describe_obj(m, obj_priv); | |
f4ceda89 | 172 | seq_printf(m, "\n"); |
2017263e | 173 | } |
5e118f41 | 174 | |
de227ef0 | 175 | mutex_unlock(&dev->struct_mutex); |
2017263e BG |
176 | return 0; |
177 | } | |
178 | ||
4e5359cd SF |
179 | static int i915_gem_pageflip_info(struct seq_file *m, void *data) |
180 | { | |
181 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
182 | struct drm_device *dev = node->minor->dev; | |
183 | unsigned long flags; | |
184 | struct intel_crtc *crtc; | |
185 | ||
186 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) { | |
187 | const char *pipe = crtc->pipe ? "B" : "A"; | |
188 | const char *plane = crtc->plane ? "B" : "A"; | |
189 | struct intel_unpin_work *work; | |
190 | ||
191 | spin_lock_irqsave(&dev->event_lock, flags); | |
192 | work = crtc->unpin_work; | |
193 | if (work == NULL) { | |
194 | seq_printf(m, "No flip due on pipe %s (plane %s)\n", | |
195 | pipe, plane); | |
196 | } else { | |
197 | if (!work->pending) { | |
198 | seq_printf(m, "Flip queued on pipe %s (plane %s)\n", | |
199 | pipe, plane); | |
200 | } else { | |
201 | seq_printf(m, "Flip pending (waiting for vsync) on pipe %s (plane %s)\n", | |
202 | pipe, plane); | |
203 | } | |
204 | if (work->enable_stall_check) | |
205 | seq_printf(m, "Stall check enabled, "); | |
206 | else | |
207 | seq_printf(m, "Stall check waiting for page flip ioctl, "); | |
208 | seq_printf(m, "%d prepares\n", work->pending); | |
209 | ||
210 | if (work->old_fb_obj) { | |
211 | struct drm_i915_gem_object *obj_priv = to_intel_bo(work->old_fb_obj); | |
212 | if(obj_priv) | |
213 | seq_printf(m, "Old framebuffer gtt_offset 0x%08x\n", obj_priv->gtt_offset ); | |
214 | } | |
215 | if (work->pending_flip_obj) { | |
216 | struct drm_i915_gem_object *obj_priv = to_intel_bo(work->pending_flip_obj); | |
217 | if(obj_priv) | |
218 | seq_printf(m, "New framebuffer gtt_offset 0x%08x\n", obj_priv->gtt_offset ); | |
219 | } | |
220 | } | |
221 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
222 | } | |
223 | ||
224 | return 0; | |
225 | } | |
226 | ||
2017263e BG |
227 | static int i915_gem_request_info(struct seq_file *m, void *data) |
228 | { | |
229 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
230 | struct drm_device *dev = node->minor->dev; | |
231 | drm_i915_private_t *dev_priv = dev->dev_private; | |
232 | struct drm_i915_gem_request *gem_request; | |
de227ef0 CW |
233 | int ret; |
234 | ||
235 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
236 | if (ret) | |
237 | return ret; | |
2017263e BG |
238 | |
239 | seq_printf(m, "Request:\n"); | |
852835f3 ZN |
240 | list_for_each_entry(gem_request, &dev_priv->render_ring.request_list, |
241 | list) { | |
2017263e BG |
242 | seq_printf(m, " %d @ %d\n", |
243 | gem_request->seqno, | |
244 | (int) (jiffies - gem_request->emitted_jiffies)); | |
245 | } | |
de227ef0 CW |
246 | mutex_unlock(&dev->struct_mutex); |
247 | ||
2017263e BG |
248 | return 0; |
249 | } | |
250 | ||
251 | static int i915_gem_seqno_info(struct seq_file *m, void *data) | |
252 | { | |
253 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
254 | struct drm_device *dev = node->minor->dev; | |
255 | drm_i915_private_t *dev_priv = dev->dev_private; | |
de227ef0 CW |
256 | int ret; |
257 | ||
258 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
259 | if (ret) | |
260 | return ret; | |
2017263e | 261 | |
e20f9c64 | 262 | if (dev_priv->render_ring.status_page.page_addr != NULL) { |
2017263e | 263 | seq_printf(m, "Current sequence: %d\n", |
f787a5f5 | 264 | dev_priv->render_ring.get_seqno(dev, &dev_priv->render_ring)); |
2017263e BG |
265 | } else { |
266 | seq_printf(m, "Current sequence: hws uninitialized\n"); | |
267 | } | |
268 | seq_printf(m, "Waiter sequence: %d\n", | |
269 | dev_priv->mm.waiting_gem_seqno); | |
270 | seq_printf(m, "IRQ sequence: %d\n", dev_priv->mm.irq_gem_seqno); | |
de227ef0 CW |
271 | |
272 | mutex_unlock(&dev->struct_mutex); | |
273 | ||
2017263e BG |
274 | return 0; |
275 | } | |
276 | ||
277 | ||
278 | static int i915_interrupt_info(struct seq_file *m, void *data) | |
279 | { | |
280 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
281 | struct drm_device *dev = node->minor->dev; | |
282 | drm_i915_private_t *dev_priv = dev->dev_private; | |
de227ef0 CW |
283 | int ret; |
284 | ||
285 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
286 | if (ret) | |
287 | return ret; | |
2017263e | 288 | |
bad720ff | 289 | if (!HAS_PCH_SPLIT(dev)) { |
5f6a1695 ZW |
290 | seq_printf(m, "Interrupt enable: %08x\n", |
291 | I915_READ(IER)); | |
292 | seq_printf(m, "Interrupt identity: %08x\n", | |
293 | I915_READ(IIR)); | |
294 | seq_printf(m, "Interrupt mask: %08x\n", | |
295 | I915_READ(IMR)); | |
296 | seq_printf(m, "Pipe A stat: %08x\n", | |
297 | I915_READ(PIPEASTAT)); | |
298 | seq_printf(m, "Pipe B stat: %08x\n", | |
299 | I915_READ(PIPEBSTAT)); | |
300 | } else { | |
301 | seq_printf(m, "North Display Interrupt enable: %08x\n", | |
302 | I915_READ(DEIER)); | |
303 | seq_printf(m, "North Display Interrupt identity: %08x\n", | |
304 | I915_READ(DEIIR)); | |
305 | seq_printf(m, "North Display Interrupt mask: %08x\n", | |
306 | I915_READ(DEIMR)); | |
307 | seq_printf(m, "South Display Interrupt enable: %08x\n", | |
308 | I915_READ(SDEIER)); | |
309 | seq_printf(m, "South Display Interrupt identity: %08x\n", | |
310 | I915_READ(SDEIIR)); | |
311 | seq_printf(m, "South Display Interrupt mask: %08x\n", | |
312 | I915_READ(SDEIMR)); | |
313 | seq_printf(m, "Graphics Interrupt enable: %08x\n", | |
314 | I915_READ(GTIER)); | |
315 | seq_printf(m, "Graphics Interrupt identity: %08x\n", | |
316 | I915_READ(GTIIR)); | |
317 | seq_printf(m, "Graphics Interrupt mask: %08x\n", | |
318 | I915_READ(GTIMR)); | |
319 | } | |
2017263e BG |
320 | seq_printf(m, "Interrupts received: %d\n", |
321 | atomic_read(&dev_priv->irq_received)); | |
e20f9c64 | 322 | if (dev_priv->render_ring.status_page.page_addr != NULL) { |
2017263e | 323 | seq_printf(m, "Current sequence: %d\n", |
f787a5f5 | 324 | dev_priv->render_ring.get_seqno(dev, &dev_priv->render_ring)); |
2017263e BG |
325 | } else { |
326 | seq_printf(m, "Current sequence: hws uninitialized\n"); | |
327 | } | |
328 | seq_printf(m, "Waiter sequence: %d\n", | |
329 | dev_priv->mm.waiting_gem_seqno); | |
330 | seq_printf(m, "IRQ sequence: %d\n", | |
331 | dev_priv->mm.irq_gem_seqno); | |
de227ef0 CW |
332 | mutex_unlock(&dev->struct_mutex); |
333 | ||
2017263e BG |
334 | return 0; |
335 | } | |
336 | ||
a6172a80 CW |
337 | static int i915_gem_fence_regs_info(struct seq_file *m, void *data) |
338 | { | |
339 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
340 | struct drm_device *dev = node->minor->dev; | |
341 | drm_i915_private_t *dev_priv = dev->dev_private; | |
de227ef0 CW |
342 | int i, ret; |
343 | ||
344 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
345 | if (ret) | |
346 | return ret; | |
a6172a80 CW |
347 | |
348 | seq_printf(m, "Reserved fences = %d\n", dev_priv->fence_reg_start); | |
349 | seq_printf(m, "Total fences = %d\n", dev_priv->num_fence_regs); | |
350 | for (i = 0; i < dev_priv->num_fence_regs; i++) { | |
351 | struct drm_gem_object *obj = dev_priv->fence_regs[i].obj; | |
352 | ||
353 | if (obj == NULL) { | |
354 | seq_printf(m, "Fenced object[%2d] = unused\n", i); | |
355 | } else { | |
356 | struct drm_i915_gem_object *obj_priv; | |
357 | ||
23010e43 | 358 | obj_priv = to_intel_bo(obj); |
a6172a80 | 359 | seq_printf(m, "Fenced object[%2d] = %p: %s " |
0b4d569d | 360 | "%08x %08zx %08x %s %08x %08x %d", |
a6172a80 CW |
361 | i, obj, get_pin_flag(obj_priv), |
362 | obj_priv->gtt_offset, | |
363 | obj->size, obj_priv->stride, | |
364 | get_tiling_flag(obj_priv), | |
365 | obj->read_domains, obj->write_domain, | |
366 | obj_priv->last_rendering_seqno); | |
367 | if (obj->name) | |
368 | seq_printf(m, " (name: %d)", obj->name); | |
369 | seq_printf(m, "\n"); | |
370 | } | |
371 | } | |
de227ef0 | 372 | mutex_unlock(&dev->struct_mutex); |
a6172a80 CW |
373 | |
374 | return 0; | |
375 | } | |
376 | ||
2017263e BG |
377 | static int i915_hws_info(struct seq_file *m, void *data) |
378 | { | |
379 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
380 | struct drm_device *dev = node->minor->dev; | |
381 | drm_i915_private_t *dev_priv = dev->dev_private; | |
382 | int i; | |
383 | volatile u32 *hws; | |
384 | ||
e20f9c64 | 385 | hws = (volatile u32 *)dev_priv->render_ring.status_page.page_addr; |
2017263e BG |
386 | if (hws == NULL) |
387 | return 0; | |
388 | ||
389 | for (i = 0; i < 4096 / sizeof(u32) / 4; i += 4) { | |
390 | seq_printf(m, "0x%08x: 0x%08x 0x%08x 0x%08x 0x%08x\n", | |
391 | i * 4, | |
392 | hws[i], hws[i + 1], hws[i + 2], hws[i + 3]); | |
393 | } | |
394 | return 0; | |
395 | } | |
396 | ||
6911a9b8 BG |
397 | static void i915_dump_pages(struct seq_file *m, struct page **pages, int page_count) |
398 | { | |
399 | int page, i; | |
400 | uint32_t *mem; | |
401 | ||
402 | for (page = 0; page < page_count; page++) { | |
de227ef0 | 403 | mem = kmap(pages[page]); |
6911a9b8 BG |
404 | for (i = 0; i < PAGE_SIZE; i += 4) |
405 | seq_printf(m, "%08x : %08x\n", i, mem[i / 4]); | |
de227ef0 | 406 | kunmap(pages[page]); |
6911a9b8 BG |
407 | } |
408 | } | |
409 | ||
410 | static int i915_batchbuffer_info(struct seq_file *m, void *data) | |
411 | { | |
412 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
413 | struct drm_device *dev = node->minor->dev; | |
414 | drm_i915_private_t *dev_priv = dev->dev_private; | |
415 | struct drm_gem_object *obj; | |
416 | struct drm_i915_gem_object *obj_priv; | |
417 | int ret; | |
418 | ||
de227ef0 CW |
419 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
420 | if (ret) | |
421 | return ret; | |
6911a9b8 | 422 | |
852835f3 ZN |
423 | list_for_each_entry(obj_priv, &dev_priv->render_ring.active_list, |
424 | list) { | |
a8089e84 | 425 | obj = &obj_priv->base; |
6911a9b8 | 426 | if (obj->read_domains & I915_GEM_DOMAIN_COMMAND) { |
4bdadb97 | 427 | ret = i915_gem_object_get_pages(obj, 0); |
6911a9b8 | 428 | if (ret) { |
de227ef0 | 429 | mutex_unlock(&dev->struct_mutex); |
6911a9b8 BG |
430 | return ret; |
431 | } | |
432 | ||
433 | seq_printf(m, "--- gtt_offset = 0x%08x\n", obj_priv->gtt_offset); | |
434 | i915_dump_pages(m, obj_priv->pages, obj->size / PAGE_SIZE); | |
435 | ||
436 | i915_gem_object_put_pages(obj); | |
437 | } | |
438 | } | |
439 | ||
de227ef0 | 440 | mutex_unlock(&dev->struct_mutex); |
6911a9b8 BG |
441 | |
442 | return 0; | |
443 | } | |
444 | ||
445 | static int i915_ringbuffer_data(struct seq_file *m, void *data) | |
446 | { | |
447 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
448 | struct drm_device *dev = node->minor->dev; | |
449 | drm_i915_private_t *dev_priv = dev->dev_private; | |
de227ef0 CW |
450 | int ret; |
451 | ||
452 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
453 | if (ret) | |
454 | return ret; | |
6911a9b8 | 455 | |
8187a2b7 | 456 | if (!dev_priv->render_ring.gem_object) { |
6911a9b8 | 457 | seq_printf(m, "No ringbuffer setup\n"); |
de227ef0 CW |
458 | } else { |
459 | u8 *virt = dev_priv->render_ring.virtual_start; | |
460 | uint32_t off; | |
6911a9b8 | 461 | |
de227ef0 CW |
462 | for (off = 0; off < dev_priv->render_ring.size; off += 4) { |
463 | uint32_t *ptr = (uint32_t *)(virt + off); | |
464 | seq_printf(m, "%08x : %08x\n", off, *ptr); | |
465 | } | |
6911a9b8 | 466 | } |
de227ef0 | 467 | mutex_unlock(&dev->struct_mutex); |
6911a9b8 BG |
468 | |
469 | return 0; | |
470 | } | |
471 | ||
472 | static int i915_ringbuffer_info(struct seq_file *m, void *data) | |
473 | { | |
474 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
475 | struct drm_device *dev = node->minor->dev; | |
476 | drm_i915_private_t *dev_priv = dev->dev_private; | |
0ef82af7 | 477 | unsigned int head, tail; |
6911a9b8 BG |
478 | |
479 | head = I915_READ(PRB0_HEAD) & HEAD_ADDR; | |
480 | tail = I915_READ(PRB0_TAIL) & TAIL_ADDR; | |
6911a9b8 BG |
481 | |
482 | seq_printf(m, "RingHead : %08x\n", head); | |
483 | seq_printf(m, "RingTail : %08x\n", tail); | |
8187a2b7 | 484 | seq_printf(m, "RingSize : %08lx\n", dev_priv->render_ring.size); |
a6c45cf0 | 485 | seq_printf(m, "Acthd : %08x\n", I915_READ(INTEL_INFO(dev)->gen >= 4 ? ACTHD_I965 : ACTHD)); |
6911a9b8 BG |
486 | |
487 | return 0; | |
488 | } | |
489 | ||
9df30794 CW |
490 | static const char *pin_flag(int pinned) |
491 | { | |
492 | if (pinned > 0) | |
493 | return " P"; | |
494 | else if (pinned < 0) | |
495 | return " p"; | |
496 | else | |
497 | return ""; | |
498 | } | |
499 | ||
500 | static const char *tiling_flag(int tiling) | |
501 | { | |
502 | switch (tiling) { | |
503 | default: | |
504 | case I915_TILING_NONE: return ""; | |
505 | case I915_TILING_X: return " X"; | |
506 | case I915_TILING_Y: return " Y"; | |
507 | } | |
508 | } | |
509 | ||
510 | static const char *dirty_flag(int dirty) | |
511 | { | |
512 | return dirty ? " dirty" : ""; | |
513 | } | |
514 | ||
515 | static const char *purgeable_flag(int purgeable) | |
516 | { | |
517 | return purgeable ? " purgeable" : ""; | |
518 | } | |
519 | ||
63eeaf38 JB |
520 | static int i915_error_state(struct seq_file *m, void *unused) |
521 | { | |
522 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
523 | struct drm_device *dev = node->minor->dev; | |
524 | drm_i915_private_t *dev_priv = dev->dev_private; | |
525 | struct drm_i915_error_state *error; | |
526 | unsigned long flags; | |
9df30794 | 527 | int i, page, offset, elt; |
63eeaf38 JB |
528 | |
529 | spin_lock_irqsave(&dev_priv->error_lock, flags); | |
530 | if (!dev_priv->first_error) { | |
531 | seq_printf(m, "no error state collected\n"); | |
532 | goto out; | |
533 | } | |
534 | ||
535 | error = dev_priv->first_error; | |
536 | ||
8a905236 JB |
537 | seq_printf(m, "Time: %ld s %ld us\n", error->time.tv_sec, |
538 | error->time.tv_usec); | |
9df30794 | 539 | seq_printf(m, "PCI ID: 0x%04x\n", dev->pci_device); |
63eeaf38 JB |
540 | seq_printf(m, "EIR: 0x%08x\n", error->eir); |
541 | seq_printf(m, " PGTBL_ER: 0x%08x\n", error->pgtbl_er); | |
542 | seq_printf(m, " INSTPM: 0x%08x\n", error->instpm); | |
543 | seq_printf(m, " IPEIR: 0x%08x\n", error->ipeir); | |
544 | seq_printf(m, " IPEHR: 0x%08x\n", error->ipehr); | |
545 | seq_printf(m, " INSTDONE: 0x%08x\n", error->instdone); | |
546 | seq_printf(m, " ACTHD: 0x%08x\n", error->acthd); | |
a6c45cf0 | 547 | if (INTEL_INFO(dev)->gen >= 4) { |
63eeaf38 JB |
548 | seq_printf(m, " INSTPS: 0x%08x\n", error->instps); |
549 | seq_printf(m, " INSTDONE1: 0x%08x\n", error->instdone1); | |
550 | } | |
9df30794 CW |
551 | seq_printf(m, "seqno: 0x%08x\n", error->seqno); |
552 | ||
553 | if (error->active_bo_count) { | |
554 | seq_printf(m, "Buffers [%d]:\n", error->active_bo_count); | |
555 | ||
556 | for (i = 0; i < error->active_bo_count; i++) { | |
557 | seq_printf(m, " %08x %8zd %08x %08x %08x%s%s%s%s", | |
558 | error->active_bo[i].gtt_offset, | |
559 | error->active_bo[i].size, | |
560 | error->active_bo[i].read_domains, | |
561 | error->active_bo[i].write_domain, | |
562 | error->active_bo[i].seqno, | |
563 | pin_flag(error->active_bo[i].pinned), | |
564 | tiling_flag(error->active_bo[i].tiling), | |
565 | dirty_flag(error->active_bo[i].dirty), | |
566 | purgeable_flag(error->active_bo[i].purgeable)); | |
567 | ||
568 | if (error->active_bo[i].name) | |
569 | seq_printf(m, " (name: %d)", error->active_bo[i].name); | |
570 | if (error->active_bo[i].fence_reg != I915_FENCE_REG_NONE) | |
571 | seq_printf(m, " (fence: %d)", error->active_bo[i].fence_reg); | |
572 | ||
573 | seq_printf(m, "\n"); | |
574 | } | |
575 | } | |
576 | ||
577 | for (i = 0; i < ARRAY_SIZE(error->batchbuffer); i++) { | |
578 | if (error->batchbuffer[i]) { | |
579 | struct drm_i915_error_object *obj = error->batchbuffer[i]; | |
580 | ||
581 | seq_printf(m, "--- gtt_offset = 0x%08x\n", obj->gtt_offset); | |
582 | offset = 0; | |
583 | for (page = 0; page < obj->page_count; page++) { | |
584 | for (elt = 0; elt < PAGE_SIZE/4; elt++) { | |
585 | seq_printf(m, "%08x : %08x\n", offset, obj->pages[page][elt]); | |
586 | offset += 4; | |
587 | } | |
588 | } | |
589 | } | |
590 | } | |
591 | ||
592 | if (error->ringbuffer) { | |
593 | struct drm_i915_error_object *obj = error->ringbuffer; | |
594 | ||
595 | seq_printf(m, "--- ringbuffer = 0x%08x\n", obj->gtt_offset); | |
596 | offset = 0; | |
597 | for (page = 0; page < obj->page_count; page++) { | |
598 | for (elt = 0; elt < PAGE_SIZE/4; elt++) { | |
599 | seq_printf(m, "%08x : %08x\n", offset, obj->pages[page][elt]); | |
600 | offset += 4; | |
601 | } | |
602 | } | |
603 | } | |
63eeaf38 | 604 | |
6ef3d427 CW |
605 | if (error->overlay) |
606 | intel_overlay_print_error_state(m, error->overlay); | |
607 | ||
63eeaf38 JB |
608 | out: |
609 | spin_unlock_irqrestore(&dev_priv->error_lock, flags); | |
610 | ||
611 | return 0; | |
612 | } | |
6911a9b8 | 613 | |
f97108d1 JB |
614 | static int i915_rstdby_delays(struct seq_file *m, void *unused) |
615 | { | |
616 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
617 | struct drm_device *dev = node->minor->dev; | |
618 | drm_i915_private_t *dev_priv = dev->dev_private; | |
619 | u16 crstanddelay = I915_READ16(CRSTANDVID); | |
620 | ||
621 | seq_printf(m, "w/ctx: %d, w/o ctx: %d\n", (crstanddelay >> 8) & 0x3f, (crstanddelay & 0x3f)); | |
622 | ||
623 | return 0; | |
624 | } | |
625 | ||
626 | static int i915_cur_delayinfo(struct seq_file *m, void *unused) | |
627 | { | |
628 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
629 | struct drm_device *dev = node->minor->dev; | |
630 | drm_i915_private_t *dev_priv = dev->dev_private; | |
631 | u16 rgvswctl = I915_READ16(MEMSWCTL); | |
7648fa99 | 632 | u16 rgvstat = I915_READ16(MEMSTAT_ILK); |
f97108d1 | 633 | |
7648fa99 JB |
634 | seq_printf(m, "Requested P-state: %d\n", (rgvswctl >> 8) & 0xf); |
635 | seq_printf(m, "Requested VID: %d\n", rgvswctl & 0x3f); | |
636 | seq_printf(m, "Current VID: %d\n", (rgvstat & MEMSTAT_VID_MASK) >> | |
637 | MEMSTAT_VID_SHIFT); | |
638 | seq_printf(m, "Current P-state: %d\n", | |
639 | (rgvstat & MEMSTAT_PSTATE_MASK) >> MEMSTAT_PSTATE_SHIFT); | |
f97108d1 JB |
640 | |
641 | return 0; | |
642 | } | |
643 | ||
644 | static int i915_delayfreq_table(struct seq_file *m, void *unused) | |
645 | { | |
646 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
647 | struct drm_device *dev = node->minor->dev; | |
648 | drm_i915_private_t *dev_priv = dev->dev_private; | |
649 | u32 delayfreq; | |
650 | int i; | |
651 | ||
652 | for (i = 0; i < 16; i++) { | |
653 | delayfreq = I915_READ(PXVFREQ_BASE + i * 4); | |
7648fa99 JB |
654 | seq_printf(m, "P%02dVIDFREQ: 0x%08x (VID: %d)\n", i, delayfreq, |
655 | (delayfreq & PXVFREQ_PX_MASK) >> PXVFREQ_PX_SHIFT); | |
f97108d1 JB |
656 | } |
657 | ||
658 | return 0; | |
659 | } | |
660 | ||
661 | static inline int MAP_TO_MV(int map) | |
662 | { | |
663 | return 1250 - (map * 25); | |
664 | } | |
665 | ||
666 | static int i915_inttoext_table(struct seq_file *m, void *unused) | |
667 | { | |
668 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
669 | struct drm_device *dev = node->minor->dev; | |
670 | drm_i915_private_t *dev_priv = dev->dev_private; | |
671 | u32 inttoext; | |
672 | int i; | |
673 | ||
674 | for (i = 1; i <= 32; i++) { | |
675 | inttoext = I915_READ(INTTOEXT_BASE_ILK + i * 4); | |
676 | seq_printf(m, "INTTOEXT%02d: 0x%08x\n", i, inttoext); | |
677 | } | |
678 | ||
679 | return 0; | |
680 | } | |
681 | ||
682 | static int i915_drpc_info(struct seq_file *m, void *unused) | |
683 | { | |
684 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
685 | struct drm_device *dev = node->minor->dev; | |
686 | drm_i915_private_t *dev_priv = dev->dev_private; | |
687 | u32 rgvmodectl = I915_READ(MEMMODECTL); | |
7648fa99 JB |
688 | u32 rstdbyctl = I915_READ(MCHBAR_RENDER_STANDBY); |
689 | u16 crstandvid = I915_READ16(CRSTANDVID); | |
f97108d1 JB |
690 | |
691 | seq_printf(m, "HD boost: %s\n", (rgvmodectl & MEMMODE_BOOST_EN) ? | |
692 | "yes" : "no"); | |
693 | seq_printf(m, "Boost freq: %d\n", | |
694 | (rgvmodectl & MEMMODE_BOOST_FREQ_MASK) >> | |
695 | MEMMODE_BOOST_FREQ_SHIFT); | |
696 | seq_printf(m, "HW control enabled: %s\n", | |
697 | rgvmodectl & MEMMODE_HWIDLE_EN ? "yes" : "no"); | |
698 | seq_printf(m, "SW control enabled: %s\n", | |
699 | rgvmodectl & MEMMODE_SWMODE_EN ? "yes" : "no"); | |
700 | seq_printf(m, "Gated voltage change: %s\n", | |
701 | rgvmodectl & MEMMODE_RCLK_GATE ? "yes" : "no"); | |
702 | seq_printf(m, "Starting frequency: P%d\n", | |
703 | (rgvmodectl & MEMMODE_FSTART_MASK) >> MEMMODE_FSTART_SHIFT); | |
7648fa99 | 704 | seq_printf(m, "Max P-state: P%d\n", |
f97108d1 | 705 | (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT); |
7648fa99 JB |
706 | seq_printf(m, "Min P-state: P%d\n", (rgvmodectl & MEMMODE_FMIN_MASK)); |
707 | seq_printf(m, "RS1 VID: %d\n", (crstandvid & 0x3f)); | |
708 | seq_printf(m, "RS2 VID: %d\n", ((crstandvid >> 8) & 0x3f)); | |
709 | seq_printf(m, "Render standby enabled: %s\n", | |
710 | (rstdbyctl & RCX_SW_EXIT) ? "no" : "yes"); | |
f97108d1 JB |
711 | |
712 | return 0; | |
713 | } | |
714 | ||
b5e50c3f JB |
715 | static int i915_fbc_status(struct seq_file *m, void *unused) |
716 | { | |
717 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
718 | struct drm_device *dev = node->minor->dev; | |
b5e50c3f | 719 | drm_i915_private_t *dev_priv = dev->dev_private; |
b5e50c3f | 720 | |
ee5382ae | 721 | if (!I915_HAS_FBC(dev)) { |
b5e50c3f JB |
722 | seq_printf(m, "FBC unsupported on this chipset\n"); |
723 | return 0; | |
724 | } | |
725 | ||
ee5382ae | 726 | if (intel_fbc_enabled(dev)) { |
b5e50c3f JB |
727 | seq_printf(m, "FBC enabled\n"); |
728 | } else { | |
729 | seq_printf(m, "FBC disabled: "); | |
730 | switch (dev_priv->no_fbc_reason) { | |
bed4a673 CW |
731 | case FBC_NO_OUTPUT: |
732 | seq_printf(m, "no outputs"); | |
733 | break; | |
b5e50c3f JB |
734 | case FBC_STOLEN_TOO_SMALL: |
735 | seq_printf(m, "not enough stolen memory"); | |
736 | break; | |
737 | case FBC_UNSUPPORTED_MODE: | |
738 | seq_printf(m, "mode not supported"); | |
739 | break; | |
740 | case FBC_MODE_TOO_LARGE: | |
741 | seq_printf(m, "mode too large"); | |
742 | break; | |
743 | case FBC_BAD_PLANE: | |
744 | seq_printf(m, "FBC unsupported on plane"); | |
745 | break; | |
746 | case FBC_NOT_TILED: | |
747 | seq_printf(m, "scanout buffer not tiled"); | |
748 | break; | |
9c928d16 JB |
749 | case FBC_MULTIPLE_PIPES: |
750 | seq_printf(m, "multiple pipes are enabled"); | |
751 | break; | |
b5e50c3f JB |
752 | default: |
753 | seq_printf(m, "unknown reason"); | |
754 | } | |
755 | seq_printf(m, "\n"); | |
756 | } | |
757 | return 0; | |
758 | } | |
759 | ||
4a9bef37 JB |
760 | static int i915_sr_status(struct seq_file *m, void *unused) |
761 | { | |
762 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
763 | struct drm_device *dev = node->minor->dev; | |
764 | drm_i915_private_t *dev_priv = dev->dev_private; | |
765 | bool sr_enabled = false; | |
766 | ||
5ba2aaaa CW |
767 | if (IS_IRONLAKE(dev)) |
768 | sr_enabled = I915_READ(WM1_LP_ILK) & WM1_LP_SR_EN; | |
a6c45cf0 | 769 | else if (IS_CRESTLINE(dev) || IS_I945G(dev) || IS_I945GM(dev)) |
4a9bef37 JB |
770 | sr_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN; |
771 | else if (IS_I915GM(dev)) | |
772 | sr_enabled = I915_READ(INSTPM) & INSTPM_SELF_EN; | |
773 | else if (IS_PINEVIEW(dev)) | |
774 | sr_enabled = I915_READ(DSPFW3) & PINEVIEW_SELF_REFRESH_EN; | |
775 | ||
5ba2aaaa CW |
776 | seq_printf(m, "self-refresh: %s\n", |
777 | sr_enabled ? "enabled" : "disabled"); | |
4a9bef37 JB |
778 | |
779 | return 0; | |
780 | } | |
781 | ||
7648fa99 JB |
782 | static int i915_emon_status(struct seq_file *m, void *unused) |
783 | { | |
784 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
785 | struct drm_device *dev = node->minor->dev; | |
786 | drm_i915_private_t *dev_priv = dev->dev_private; | |
787 | unsigned long temp, chipset, gfx; | |
de227ef0 CW |
788 | int ret; |
789 | ||
790 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
791 | if (ret) | |
792 | return ret; | |
7648fa99 JB |
793 | |
794 | temp = i915_mch_val(dev_priv); | |
795 | chipset = i915_chipset_val(dev_priv); | |
796 | gfx = i915_gfx_val(dev_priv); | |
de227ef0 | 797 | mutex_unlock(&dev->struct_mutex); |
7648fa99 JB |
798 | |
799 | seq_printf(m, "GMCH temp: %ld\n", temp); | |
800 | seq_printf(m, "Chipset power: %ld\n", chipset); | |
801 | seq_printf(m, "GFX power: %ld\n", gfx); | |
802 | seq_printf(m, "Total power: %ld\n", chipset + gfx); | |
803 | ||
804 | return 0; | |
805 | } | |
806 | ||
807 | static int i915_gfxec(struct seq_file *m, void *unused) | |
808 | { | |
809 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
810 | struct drm_device *dev = node->minor->dev; | |
811 | drm_i915_private_t *dev_priv = dev->dev_private; | |
812 | ||
813 | seq_printf(m, "GFXEC: %ld\n", (unsigned long)I915_READ(0x112f4)); | |
814 | ||
815 | return 0; | |
816 | } | |
817 | ||
44834a67 CW |
818 | static int i915_opregion(struct seq_file *m, void *unused) |
819 | { | |
820 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
821 | struct drm_device *dev = node->minor->dev; | |
822 | drm_i915_private_t *dev_priv = dev->dev_private; | |
823 | struct intel_opregion *opregion = &dev_priv->opregion; | |
824 | int ret; | |
825 | ||
826 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
827 | if (ret) | |
828 | return ret; | |
829 | ||
830 | if (opregion->header) | |
831 | seq_write(m, opregion->header, OPREGION_SIZE); | |
832 | ||
833 | mutex_unlock(&dev->struct_mutex); | |
834 | ||
835 | return 0; | |
836 | } | |
837 | ||
37811fcc CW |
838 | static int i915_gem_framebuffer_info(struct seq_file *m, void *data) |
839 | { | |
840 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
841 | struct drm_device *dev = node->minor->dev; | |
842 | drm_i915_private_t *dev_priv = dev->dev_private; | |
843 | struct intel_fbdev *ifbdev; | |
844 | struct intel_framebuffer *fb; | |
845 | int ret; | |
846 | ||
847 | ret = mutex_lock_interruptible(&dev->mode_config.mutex); | |
848 | if (ret) | |
849 | return ret; | |
850 | ||
851 | ifbdev = dev_priv->fbdev; | |
852 | fb = to_intel_framebuffer(ifbdev->helper.fb); | |
853 | ||
854 | seq_printf(m, "fbcon size: %d x %d, depth %d, %d bpp, obj ", | |
855 | fb->base.width, | |
856 | fb->base.height, | |
857 | fb->base.depth, | |
858 | fb->base.bits_per_pixel); | |
859 | describe_obj(m, to_intel_bo(fb->obj)); | |
860 | seq_printf(m, "\n"); | |
861 | ||
862 | list_for_each_entry(fb, &dev->mode_config.fb_list, base.head) { | |
863 | if (&fb->base == ifbdev->helper.fb) | |
864 | continue; | |
865 | ||
866 | seq_printf(m, "user size: %d x %d, depth %d, %d bpp, obj ", | |
867 | fb->base.width, | |
868 | fb->base.height, | |
869 | fb->base.depth, | |
870 | fb->base.bits_per_pixel); | |
871 | describe_obj(m, to_intel_bo(fb->obj)); | |
872 | seq_printf(m, "\n"); | |
873 | } | |
874 | ||
875 | mutex_unlock(&dev->mode_config.mutex); | |
876 | ||
877 | return 0; | |
878 | } | |
879 | ||
f3cd474b CW |
880 | static int |
881 | i915_wedged_open(struct inode *inode, | |
882 | struct file *filp) | |
883 | { | |
884 | filp->private_data = inode->i_private; | |
885 | return 0; | |
886 | } | |
887 | ||
888 | static ssize_t | |
889 | i915_wedged_read(struct file *filp, | |
890 | char __user *ubuf, | |
891 | size_t max, | |
892 | loff_t *ppos) | |
893 | { | |
894 | struct drm_device *dev = filp->private_data; | |
895 | drm_i915_private_t *dev_priv = dev->dev_private; | |
896 | char buf[80]; | |
897 | int len; | |
898 | ||
899 | len = snprintf(buf, sizeof (buf), | |
900 | "wedged : %d\n", | |
901 | atomic_read(&dev_priv->mm.wedged)); | |
902 | ||
f4433a8d DC |
903 | if (len > sizeof (buf)) |
904 | len = sizeof (buf); | |
905 | ||
f3cd474b CW |
906 | return simple_read_from_buffer(ubuf, max, ppos, buf, len); |
907 | } | |
908 | ||
909 | static ssize_t | |
910 | i915_wedged_write(struct file *filp, | |
911 | const char __user *ubuf, | |
912 | size_t cnt, | |
913 | loff_t *ppos) | |
914 | { | |
915 | struct drm_device *dev = filp->private_data; | |
916 | drm_i915_private_t *dev_priv = dev->dev_private; | |
917 | char buf[20]; | |
918 | int val = 1; | |
919 | ||
920 | if (cnt > 0) { | |
921 | if (cnt > sizeof (buf) - 1) | |
922 | return -EINVAL; | |
923 | ||
924 | if (copy_from_user(buf, ubuf, cnt)) | |
925 | return -EFAULT; | |
926 | buf[cnt] = 0; | |
927 | ||
928 | val = simple_strtoul(buf, NULL, 0); | |
929 | } | |
930 | ||
931 | DRM_INFO("Manually setting wedged to %d\n", val); | |
932 | ||
933 | atomic_set(&dev_priv->mm.wedged, val); | |
934 | if (val) { | |
f787a5f5 | 935 | wake_up_all(&dev_priv->irq_queue); |
f3cd474b CW |
936 | queue_work(dev_priv->wq, &dev_priv->error_work); |
937 | } | |
938 | ||
939 | return cnt; | |
940 | } | |
941 | ||
942 | static const struct file_operations i915_wedged_fops = { | |
943 | .owner = THIS_MODULE, | |
944 | .open = i915_wedged_open, | |
945 | .read = i915_wedged_read, | |
946 | .write = i915_wedged_write, | |
947 | }; | |
948 | ||
949 | /* As the drm_debugfs_init() routines are called before dev->dev_private is | |
950 | * allocated we need to hook into the minor for release. */ | |
951 | static int | |
952 | drm_add_fake_info_node(struct drm_minor *minor, | |
953 | struct dentry *ent, | |
954 | const void *key) | |
955 | { | |
956 | struct drm_info_node *node; | |
957 | ||
958 | node = kmalloc(sizeof(struct drm_info_node), GFP_KERNEL); | |
959 | if (node == NULL) { | |
960 | debugfs_remove(ent); | |
961 | return -ENOMEM; | |
962 | } | |
963 | ||
964 | node->minor = minor; | |
965 | node->dent = ent; | |
966 | node->info_ent = (void *) key; | |
967 | list_add(&node->list, &minor->debugfs_nodes.list); | |
968 | ||
969 | return 0; | |
970 | } | |
971 | ||
972 | static int i915_wedged_create(struct dentry *root, struct drm_minor *minor) | |
973 | { | |
974 | struct drm_device *dev = minor->dev; | |
975 | struct dentry *ent; | |
976 | ||
977 | ent = debugfs_create_file("i915_wedged", | |
978 | S_IRUGO | S_IWUSR, | |
979 | root, dev, | |
980 | &i915_wedged_fops); | |
981 | if (IS_ERR(ent)) | |
982 | return PTR_ERR(ent); | |
983 | ||
984 | return drm_add_fake_info_node(minor, ent, &i915_wedged_fops); | |
985 | } | |
9e3a6d15 | 986 | |
27c202ad | 987 | static struct drm_info_list i915_debugfs_list[] = { |
70d39fe4 | 988 | {"i915_capabilities", i915_capabilities, 0, 0}, |
82690bba CW |
989 | {"i915_gem_render_active", i915_gem_object_list_info, 0, (void *) RENDER_LIST}, |
990 | {"i915_gem_bsd_active", i915_gem_object_list_info, 0, (void *) BSD_LIST}, | |
433e12f7 BG |
991 | {"i915_gem_flushing", i915_gem_object_list_info, 0, (void *) FLUSHING_LIST}, |
992 | {"i915_gem_inactive", i915_gem_object_list_info, 0, (void *) INACTIVE_LIST}, | |
f13d3f73 | 993 | {"i915_gem_pinned", i915_gem_object_list_info, 0, (void *) PINNED_LIST}, |
4e5359cd | 994 | {"i915_gem_pageflip", i915_gem_pageflip_info, 0}, |
2017263e BG |
995 | {"i915_gem_request", i915_gem_request_info, 0}, |
996 | {"i915_gem_seqno", i915_gem_seqno_info, 0}, | |
a6172a80 | 997 | {"i915_gem_fence_regs", i915_gem_fence_regs_info, 0}, |
2017263e BG |
998 | {"i915_gem_interrupt", i915_interrupt_info, 0}, |
999 | {"i915_gem_hws", i915_hws_info, 0}, | |
6911a9b8 BG |
1000 | {"i915_ringbuffer_data", i915_ringbuffer_data, 0}, |
1001 | {"i915_ringbuffer_info", i915_ringbuffer_info, 0}, | |
1002 | {"i915_batchbuffers", i915_batchbuffer_info, 0}, | |
63eeaf38 | 1003 | {"i915_error_state", i915_error_state, 0}, |
f97108d1 JB |
1004 | {"i915_rstdby_delays", i915_rstdby_delays, 0}, |
1005 | {"i915_cur_delayinfo", i915_cur_delayinfo, 0}, | |
1006 | {"i915_delayfreq_table", i915_delayfreq_table, 0}, | |
1007 | {"i915_inttoext_table", i915_inttoext_table, 0}, | |
1008 | {"i915_drpc_info", i915_drpc_info, 0}, | |
7648fa99 JB |
1009 | {"i915_emon_status", i915_emon_status, 0}, |
1010 | {"i915_gfxec", i915_gfxec, 0}, | |
b5e50c3f | 1011 | {"i915_fbc_status", i915_fbc_status, 0}, |
4a9bef37 | 1012 | {"i915_sr_status", i915_sr_status, 0}, |
44834a67 | 1013 | {"i915_opregion", i915_opregion, 0}, |
37811fcc | 1014 | {"i915_gem_framebuffer", i915_gem_framebuffer_info, 0}, |
2017263e | 1015 | }; |
27c202ad | 1016 | #define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list) |
2017263e | 1017 | |
27c202ad | 1018 | int i915_debugfs_init(struct drm_minor *minor) |
2017263e | 1019 | { |
f3cd474b CW |
1020 | int ret; |
1021 | ||
1022 | ret = i915_wedged_create(minor->debugfs_root, minor); | |
1023 | if (ret) | |
1024 | return ret; | |
1025 | ||
27c202ad BG |
1026 | return drm_debugfs_create_files(i915_debugfs_list, |
1027 | I915_DEBUGFS_ENTRIES, | |
2017263e BG |
1028 | minor->debugfs_root, minor); |
1029 | } | |
1030 | ||
27c202ad | 1031 | void i915_debugfs_cleanup(struct drm_minor *minor) |
2017263e | 1032 | { |
27c202ad BG |
1033 | drm_debugfs_remove_files(i915_debugfs_list, |
1034 | I915_DEBUGFS_ENTRIES, minor); | |
33db679b KH |
1035 | drm_debugfs_remove_files((struct drm_info_list *) &i915_wedged_fops, |
1036 | 1, minor); | |
2017263e BG |
1037 | } |
1038 | ||
1039 | #endif /* CONFIG_DEBUG_FS */ |