Commit | Line | Data |
---|---|---|
2017263e BG |
1 | /* |
2 | * Copyright © 2008 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | * Keith Packard <keithp@keithp.com> | |
26 | * | |
27 | */ | |
28 | ||
29 | #include <linux/seq_file.h> | |
b2c88f5b | 30 | #include <linux/circ_buf.h> |
926321d5 | 31 | #include <linux/ctype.h> |
f3cd474b | 32 | #include <linux/debugfs.h> |
5a0e3ad6 | 33 | #include <linux/slab.h> |
2d1a8a48 | 34 | #include <linux/export.h> |
6d2b8885 | 35 | #include <linux/list_sort.h> |
ec013e7f | 36 | #include <asm/msr-index.h> |
760285e7 | 37 | #include <drm/drmP.h> |
4e5359cd | 38 | #include "intel_drv.h" |
e5c65260 | 39 | #include "intel_ringbuffer.h" |
760285e7 | 40 | #include <drm/i915_drm.h> |
2017263e BG |
41 | #include "i915_drv.h" |
42 | ||
f13d3f73 | 43 | enum { |
69dc4987 | 44 | ACTIVE_LIST, |
f13d3f73 | 45 | INACTIVE_LIST, |
d21d5975 | 46 | PINNED_LIST, |
f13d3f73 | 47 | }; |
2017263e | 48 | |
70d39fe4 CW |
49 | static const char *yesno(int v) |
50 | { | |
51 | return v ? "yes" : "no"; | |
52 | } | |
53 | ||
497666d8 DL |
54 | /* As the drm_debugfs_init() routines are called before dev->dev_private is |
55 | * allocated we need to hook into the minor for release. */ | |
56 | static int | |
57 | drm_add_fake_info_node(struct drm_minor *minor, | |
58 | struct dentry *ent, | |
59 | const void *key) | |
60 | { | |
61 | struct drm_info_node *node; | |
62 | ||
63 | node = kmalloc(sizeof(*node), GFP_KERNEL); | |
64 | if (node == NULL) { | |
65 | debugfs_remove(ent); | |
66 | return -ENOMEM; | |
67 | } | |
68 | ||
69 | node->minor = minor; | |
70 | node->dent = ent; | |
71 | node->info_ent = (void *) key; | |
72 | ||
73 | mutex_lock(&minor->debugfs_lock); | |
74 | list_add(&node->list, &minor->debugfs_list); | |
75 | mutex_unlock(&minor->debugfs_lock); | |
76 | ||
77 | return 0; | |
78 | } | |
79 | ||
70d39fe4 CW |
80 | static int i915_capabilities(struct seq_file *m, void *data) |
81 | { | |
9f25d007 | 82 | struct drm_info_node *node = m->private; |
70d39fe4 CW |
83 | struct drm_device *dev = node->minor->dev; |
84 | const struct intel_device_info *info = INTEL_INFO(dev); | |
85 | ||
86 | seq_printf(m, "gen: %d\n", info->gen); | |
03d00ac5 | 87 | seq_printf(m, "pch: %d\n", INTEL_PCH_TYPE(dev)); |
79fc46df DL |
88 | #define PRINT_FLAG(x) seq_printf(m, #x ": %s\n", yesno(info->x)) |
89 | #define SEP_SEMICOLON ; | |
90 | DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG, SEP_SEMICOLON); | |
91 | #undef PRINT_FLAG | |
92 | #undef SEP_SEMICOLON | |
70d39fe4 CW |
93 | |
94 | return 0; | |
95 | } | |
2017263e | 96 | |
05394f39 | 97 | static const char *get_pin_flag(struct drm_i915_gem_object *obj) |
a6172a80 | 98 | { |
05394f39 | 99 | if (obj->user_pin_count > 0) |
a6172a80 | 100 | return "P"; |
d7f46fc4 | 101 | else if (i915_gem_obj_is_pinned(obj)) |
a6172a80 CW |
102 | return "p"; |
103 | else | |
104 | return " "; | |
105 | } | |
106 | ||
05394f39 | 107 | static const char *get_tiling_flag(struct drm_i915_gem_object *obj) |
a6172a80 | 108 | { |
0206e353 AJ |
109 | switch (obj->tiling_mode) { |
110 | default: | |
111 | case I915_TILING_NONE: return " "; | |
112 | case I915_TILING_X: return "X"; | |
113 | case I915_TILING_Y: return "Y"; | |
114 | } | |
a6172a80 CW |
115 | } |
116 | ||
1d693bcc BW |
117 | static inline const char *get_global_flag(struct drm_i915_gem_object *obj) |
118 | { | |
119 | return obj->has_global_gtt_mapping ? "g" : " "; | |
120 | } | |
121 | ||
37811fcc CW |
122 | static void |
123 | describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj) | |
124 | { | |
1d693bcc | 125 | struct i915_vma *vma; |
d7f46fc4 BW |
126 | int pin_count = 0; |
127 | ||
fb1ae911 | 128 | seq_printf(m, "%pK: %s%s%s %8zdKiB %02x %02x %u %u %u%s%s%s", |
37811fcc CW |
129 | &obj->base, |
130 | get_pin_flag(obj), | |
131 | get_tiling_flag(obj), | |
1d693bcc | 132 | get_global_flag(obj), |
a05a5862 | 133 | obj->base.size / 1024, |
37811fcc CW |
134 | obj->base.read_domains, |
135 | obj->base.write_domain, | |
0201f1ec CW |
136 | obj->last_read_seqno, |
137 | obj->last_write_seqno, | |
caea7476 | 138 | obj->last_fenced_seqno, |
84734a04 | 139 | i915_cache_level_str(obj->cache_level), |
37811fcc CW |
140 | obj->dirty ? " dirty" : "", |
141 | obj->madv == I915_MADV_DONTNEED ? " purgeable" : ""); | |
142 | if (obj->base.name) | |
143 | seq_printf(m, " (name: %d)", obj->base.name); | |
d7f46fc4 BW |
144 | list_for_each_entry(vma, &obj->vma_list, vma_link) |
145 | if (vma->pin_count > 0) | |
146 | pin_count++; | |
147 | seq_printf(m, " (pinned x %d)", pin_count); | |
cc98b413 CW |
148 | if (obj->pin_display) |
149 | seq_printf(m, " (display)"); | |
37811fcc CW |
150 | if (obj->fence_reg != I915_FENCE_REG_NONE) |
151 | seq_printf(m, " (fence: %d)", obj->fence_reg); | |
1d693bcc BW |
152 | list_for_each_entry(vma, &obj->vma_list, vma_link) { |
153 | if (!i915_is_ggtt(vma->vm)) | |
154 | seq_puts(m, " (pp"); | |
155 | else | |
156 | seq_puts(m, " (g"); | |
157 | seq_printf(m, "gtt offset: %08lx, size: %08lx)", | |
158 | vma->node.start, vma->node.size); | |
159 | } | |
c1ad11fc CW |
160 | if (obj->stolen) |
161 | seq_printf(m, " (stolen: %08lx)", obj->stolen->start); | |
6299f992 CW |
162 | if (obj->pin_mappable || obj->fault_mappable) { |
163 | char s[3], *t = s; | |
164 | if (obj->pin_mappable) | |
165 | *t++ = 'p'; | |
166 | if (obj->fault_mappable) | |
167 | *t++ = 'f'; | |
168 | *t = '\0'; | |
169 | seq_printf(m, " (%s mappable)", s); | |
170 | } | |
69dc4987 CW |
171 | if (obj->ring != NULL) |
172 | seq_printf(m, " (%s)", obj->ring->name); | |
d5a81ef1 DV |
173 | if (obj->frontbuffer_bits) |
174 | seq_printf(m, " (frontbuffer: 0x%03x)", obj->frontbuffer_bits); | |
37811fcc CW |
175 | } |
176 | ||
273497e5 | 177 | static void describe_ctx(struct seq_file *m, struct intel_context *ctx) |
3ccfd19d | 178 | { |
ea0c76f8 | 179 | seq_putc(m, ctx->legacy_hw_ctx.initialized ? 'I' : 'i'); |
3ccfd19d BW |
180 | seq_putc(m, ctx->remap_slice ? 'R' : 'r'); |
181 | seq_putc(m, ' '); | |
182 | } | |
183 | ||
433e12f7 | 184 | static int i915_gem_object_list_info(struct seq_file *m, void *data) |
2017263e | 185 | { |
9f25d007 | 186 | struct drm_info_node *node = m->private; |
433e12f7 BG |
187 | uintptr_t list = (uintptr_t) node->info_ent->data; |
188 | struct list_head *head; | |
2017263e | 189 | struct drm_device *dev = node->minor->dev; |
5cef07e1 BW |
190 | struct drm_i915_private *dev_priv = dev->dev_private; |
191 | struct i915_address_space *vm = &dev_priv->gtt.base; | |
ca191b13 | 192 | struct i915_vma *vma; |
8f2480fb CW |
193 | size_t total_obj_size, total_gtt_size; |
194 | int count, ret; | |
de227ef0 CW |
195 | |
196 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
197 | if (ret) | |
198 | return ret; | |
2017263e | 199 | |
ca191b13 | 200 | /* FIXME: the user of this interface might want more than just GGTT */ |
433e12f7 BG |
201 | switch (list) { |
202 | case ACTIVE_LIST: | |
267f0c90 | 203 | seq_puts(m, "Active:\n"); |
5cef07e1 | 204 | head = &vm->active_list; |
433e12f7 BG |
205 | break; |
206 | case INACTIVE_LIST: | |
267f0c90 | 207 | seq_puts(m, "Inactive:\n"); |
5cef07e1 | 208 | head = &vm->inactive_list; |
433e12f7 | 209 | break; |
433e12f7 | 210 | default: |
de227ef0 CW |
211 | mutex_unlock(&dev->struct_mutex); |
212 | return -EINVAL; | |
2017263e | 213 | } |
2017263e | 214 | |
8f2480fb | 215 | total_obj_size = total_gtt_size = count = 0; |
ca191b13 BW |
216 | list_for_each_entry(vma, head, mm_list) { |
217 | seq_printf(m, " "); | |
218 | describe_obj(m, vma->obj); | |
219 | seq_printf(m, "\n"); | |
220 | total_obj_size += vma->obj->base.size; | |
221 | total_gtt_size += vma->node.size; | |
8f2480fb | 222 | count++; |
2017263e | 223 | } |
de227ef0 | 224 | mutex_unlock(&dev->struct_mutex); |
5e118f41 | 225 | |
8f2480fb CW |
226 | seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n", |
227 | count, total_obj_size, total_gtt_size); | |
2017263e BG |
228 | return 0; |
229 | } | |
230 | ||
6d2b8885 CW |
231 | static int obj_rank_by_stolen(void *priv, |
232 | struct list_head *A, struct list_head *B) | |
233 | { | |
234 | struct drm_i915_gem_object *a = | |
b25cb2f8 | 235 | container_of(A, struct drm_i915_gem_object, obj_exec_link); |
6d2b8885 | 236 | struct drm_i915_gem_object *b = |
b25cb2f8 | 237 | container_of(B, struct drm_i915_gem_object, obj_exec_link); |
6d2b8885 CW |
238 | |
239 | return a->stolen->start - b->stolen->start; | |
240 | } | |
241 | ||
242 | static int i915_gem_stolen_list_info(struct seq_file *m, void *data) | |
243 | { | |
9f25d007 | 244 | struct drm_info_node *node = m->private; |
6d2b8885 CW |
245 | struct drm_device *dev = node->minor->dev; |
246 | struct drm_i915_private *dev_priv = dev->dev_private; | |
247 | struct drm_i915_gem_object *obj; | |
248 | size_t total_obj_size, total_gtt_size; | |
249 | LIST_HEAD(stolen); | |
250 | int count, ret; | |
251 | ||
252 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
253 | if (ret) | |
254 | return ret; | |
255 | ||
256 | total_obj_size = total_gtt_size = count = 0; | |
257 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) { | |
258 | if (obj->stolen == NULL) | |
259 | continue; | |
260 | ||
b25cb2f8 | 261 | list_add(&obj->obj_exec_link, &stolen); |
6d2b8885 CW |
262 | |
263 | total_obj_size += obj->base.size; | |
264 | total_gtt_size += i915_gem_obj_ggtt_size(obj); | |
265 | count++; | |
266 | } | |
267 | list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) { | |
268 | if (obj->stolen == NULL) | |
269 | continue; | |
270 | ||
b25cb2f8 | 271 | list_add(&obj->obj_exec_link, &stolen); |
6d2b8885 CW |
272 | |
273 | total_obj_size += obj->base.size; | |
274 | count++; | |
275 | } | |
276 | list_sort(NULL, &stolen, obj_rank_by_stolen); | |
277 | seq_puts(m, "Stolen:\n"); | |
278 | while (!list_empty(&stolen)) { | |
b25cb2f8 | 279 | obj = list_first_entry(&stolen, typeof(*obj), obj_exec_link); |
6d2b8885 CW |
280 | seq_puts(m, " "); |
281 | describe_obj(m, obj); | |
282 | seq_putc(m, '\n'); | |
b25cb2f8 | 283 | list_del_init(&obj->obj_exec_link); |
6d2b8885 CW |
284 | } |
285 | mutex_unlock(&dev->struct_mutex); | |
286 | ||
287 | seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n", | |
288 | count, total_obj_size, total_gtt_size); | |
289 | return 0; | |
290 | } | |
291 | ||
6299f992 CW |
292 | #define count_objects(list, member) do { \ |
293 | list_for_each_entry(obj, list, member) { \ | |
f343c5f6 | 294 | size += i915_gem_obj_ggtt_size(obj); \ |
6299f992 CW |
295 | ++count; \ |
296 | if (obj->map_and_fenceable) { \ | |
f343c5f6 | 297 | mappable_size += i915_gem_obj_ggtt_size(obj); \ |
6299f992 CW |
298 | ++mappable_count; \ |
299 | } \ | |
300 | } \ | |
0206e353 | 301 | } while (0) |
6299f992 | 302 | |
2db8e9d6 | 303 | struct file_stats { |
6313c204 | 304 | struct drm_i915_file_private *file_priv; |
2db8e9d6 | 305 | int count; |
c67a17e9 CW |
306 | size_t total, unbound; |
307 | size_t global, shared; | |
308 | size_t active, inactive; | |
2db8e9d6 CW |
309 | }; |
310 | ||
311 | static int per_file_stats(int id, void *ptr, void *data) | |
312 | { | |
313 | struct drm_i915_gem_object *obj = ptr; | |
314 | struct file_stats *stats = data; | |
6313c204 | 315 | struct i915_vma *vma; |
2db8e9d6 CW |
316 | |
317 | stats->count++; | |
318 | stats->total += obj->base.size; | |
319 | ||
c67a17e9 CW |
320 | if (obj->base.name || obj->base.dma_buf) |
321 | stats->shared += obj->base.size; | |
322 | ||
6313c204 CW |
323 | if (USES_FULL_PPGTT(obj->base.dev)) { |
324 | list_for_each_entry(vma, &obj->vma_list, vma_link) { | |
325 | struct i915_hw_ppgtt *ppgtt; | |
326 | ||
327 | if (!drm_mm_node_allocated(&vma->node)) | |
328 | continue; | |
329 | ||
330 | if (i915_is_ggtt(vma->vm)) { | |
331 | stats->global += obj->base.size; | |
332 | continue; | |
333 | } | |
334 | ||
335 | ppgtt = container_of(vma->vm, struct i915_hw_ppgtt, base); | |
336 | if (ppgtt->ctx && ppgtt->ctx->file_priv != stats->file_priv) | |
337 | continue; | |
338 | ||
339 | if (obj->ring) /* XXX per-vma statistic */ | |
340 | stats->active += obj->base.size; | |
341 | else | |
342 | stats->inactive += obj->base.size; | |
343 | ||
344 | return 0; | |
345 | } | |
2db8e9d6 | 346 | } else { |
6313c204 CW |
347 | if (i915_gem_obj_ggtt_bound(obj)) { |
348 | stats->global += obj->base.size; | |
349 | if (obj->ring) | |
350 | stats->active += obj->base.size; | |
351 | else | |
352 | stats->inactive += obj->base.size; | |
353 | return 0; | |
354 | } | |
2db8e9d6 CW |
355 | } |
356 | ||
6313c204 CW |
357 | if (!list_empty(&obj->global_list)) |
358 | stats->unbound += obj->base.size; | |
359 | ||
2db8e9d6 CW |
360 | return 0; |
361 | } | |
362 | ||
ca191b13 BW |
363 | #define count_vmas(list, member) do { \ |
364 | list_for_each_entry(vma, list, member) { \ | |
365 | size += i915_gem_obj_ggtt_size(vma->obj); \ | |
366 | ++count; \ | |
367 | if (vma->obj->map_and_fenceable) { \ | |
368 | mappable_size += i915_gem_obj_ggtt_size(vma->obj); \ | |
369 | ++mappable_count; \ | |
370 | } \ | |
371 | } \ | |
372 | } while (0) | |
373 | ||
374 | static int i915_gem_object_info(struct seq_file *m, void* data) | |
73aa808f | 375 | { |
9f25d007 | 376 | struct drm_info_node *node = m->private; |
73aa808f CW |
377 | struct drm_device *dev = node->minor->dev; |
378 | struct drm_i915_private *dev_priv = dev->dev_private; | |
b7abb714 CW |
379 | u32 count, mappable_count, purgeable_count; |
380 | size_t size, mappable_size, purgeable_size; | |
6299f992 | 381 | struct drm_i915_gem_object *obj; |
5cef07e1 | 382 | struct i915_address_space *vm = &dev_priv->gtt.base; |
2db8e9d6 | 383 | struct drm_file *file; |
ca191b13 | 384 | struct i915_vma *vma; |
73aa808f CW |
385 | int ret; |
386 | ||
387 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
388 | if (ret) | |
389 | return ret; | |
390 | ||
6299f992 CW |
391 | seq_printf(m, "%u objects, %zu bytes\n", |
392 | dev_priv->mm.object_count, | |
393 | dev_priv->mm.object_memory); | |
394 | ||
395 | size = count = mappable_size = mappable_count = 0; | |
35c20a60 | 396 | count_objects(&dev_priv->mm.bound_list, global_list); |
6299f992 CW |
397 | seq_printf(m, "%u [%u] objects, %zu [%zu] bytes in gtt\n", |
398 | count, mappable_count, size, mappable_size); | |
399 | ||
400 | size = count = mappable_size = mappable_count = 0; | |
ca191b13 | 401 | count_vmas(&vm->active_list, mm_list); |
6299f992 CW |
402 | seq_printf(m, " %u [%u] active objects, %zu [%zu] bytes\n", |
403 | count, mappable_count, size, mappable_size); | |
404 | ||
6299f992 | 405 | size = count = mappable_size = mappable_count = 0; |
ca191b13 | 406 | count_vmas(&vm->inactive_list, mm_list); |
6299f992 CW |
407 | seq_printf(m, " %u [%u] inactive objects, %zu [%zu] bytes\n", |
408 | count, mappable_count, size, mappable_size); | |
409 | ||
b7abb714 | 410 | size = count = purgeable_size = purgeable_count = 0; |
35c20a60 | 411 | list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) { |
6c085a72 | 412 | size += obj->base.size, ++count; |
b7abb714 CW |
413 | if (obj->madv == I915_MADV_DONTNEED) |
414 | purgeable_size += obj->base.size, ++purgeable_count; | |
415 | } | |
6c085a72 CW |
416 | seq_printf(m, "%u unbound objects, %zu bytes\n", count, size); |
417 | ||
6299f992 | 418 | size = count = mappable_size = mappable_count = 0; |
35c20a60 | 419 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) { |
6299f992 | 420 | if (obj->fault_mappable) { |
f343c5f6 | 421 | size += i915_gem_obj_ggtt_size(obj); |
6299f992 CW |
422 | ++count; |
423 | } | |
424 | if (obj->pin_mappable) { | |
f343c5f6 | 425 | mappable_size += i915_gem_obj_ggtt_size(obj); |
6299f992 CW |
426 | ++mappable_count; |
427 | } | |
b7abb714 CW |
428 | if (obj->madv == I915_MADV_DONTNEED) { |
429 | purgeable_size += obj->base.size; | |
430 | ++purgeable_count; | |
431 | } | |
6299f992 | 432 | } |
b7abb714 CW |
433 | seq_printf(m, "%u purgeable objects, %zu bytes\n", |
434 | purgeable_count, purgeable_size); | |
6299f992 CW |
435 | seq_printf(m, "%u pinned mappable objects, %zu bytes\n", |
436 | mappable_count, mappable_size); | |
437 | seq_printf(m, "%u fault mappable objects, %zu bytes\n", | |
438 | count, size); | |
439 | ||
93d18799 | 440 | seq_printf(m, "%zu [%lu] gtt total\n", |
853ba5d2 BW |
441 | dev_priv->gtt.base.total, |
442 | dev_priv->gtt.mappable_end - dev_priv->gtt.base.start); | |
73aa808f | 443 | |
267f0c90 | 444 | seq_putc(m, '\n'); |
2db8e9d6 CW |
445 | list_for_each_entry_reverse(file, &dev->filelist, lhead) { |
446 | struct file_stats stats; | |
3ec2f427 | 447 | struct task_struct *task; |
2db8e9d6 CW |
448 | |
449 | memset(&stats, 0, sizeof(stats)); | |
6313c204 | 450 | stats.file_priv = file->driver_priv; |
5b5ffff0 | 451 | spin_lock(&file->table_lock); |
2db8e9d6 | 452 | idr_for_each(&file->object_idr, per_file_stats, &stats); |
5b5ffff0 | 453 | spin_unlock(&file->table_lock); |
3ec2f427 TH |
454 | /* |
455 | * Although we have a valid reference on file->pid, that does | |
456 | * not guarantee that the task_struct who called get_pid() is | |
457 | * still alive (e.g. get_pid(current) => fork() => exit()). | |
458 | * Therefore, we need to protect this ->comm access using RCU. | |
459 | */ | |
460 | rcu_read_lock(); | |
461 | task = pid_task(file->pid, PIDTYPE_PID); | |
c67a17e9 | 462 | seq_printf(m, "%s: %u objects, %zu bytes (%zu active, %zu inactive, %zu global, %zu shared, %zu unbound)\n", |
3ec2f427 | 463 | task ? task->comm : "<unknown>", |
2db8e9d6 CW |
464 | stats.count, |
465 | stats.total, | |
466 | stats.active, | |
467 | stats.inactive, | |
6313c204 | 468 | stats.global, |
c67a17e9 | 469 | stats.shared, |
2db8e9d6 | 470 | stats.unbound); |
3ec2f427 | 471 | rcu_read_unlock(); |
2db8e9d6 CW |
472 | } |
473 | ||
73aa808f CW |
474 | mutex_unlock(&dev->struct_mutex); |
475 | ||
476 | return 0; | |
477 | } | |
478 | ||
aee56cff | 479 | static int i915_gem_gtt_info(struct seq_file *m, void *data) |
08c18323 | 480 | { |
9f25d007 | 481 | struct drm_info_node *node = m->private; |
08c18323 | 482 | struct drm_device *dev = node->minor->dev; |
1b50247a | 483 | uintptr_t list = (uintptr_t) node->info_ent->data; |
08c18323 CW |
484 | struct drm_i915_private *dev_priv = dev->dev_private; |
485 | struct drm_i915_gem_object *obj; | |
486 | size_t total_obj_size, total_gtt_size; | |
487 | int count, ret; | |
488 | ||
489 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
490 | if (ret) | |
491 | return ret; | |
492 | ||
493 | total_obj_size = total_gtt_size = count = 0; | |
35c20a60 | 494 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) { |
d7f46fc4 | 495 | if (list == PINNED_LIST && !i915_gem_obj_is_pinned(obj)) |
1b50247a CW |
496 | continue; |
497 | ||
267f0c90 | 498 | seq_puts(m, " "); |
08c18323 | 499 | describe_obj(m, obj); |
267f0c90 | 500 | seq_putc(m, '\n'); |
08c18323 | 501 | total_obj_size += obj->base.size; |
f343c5f6 | 502 | total_gtt_size += i915_gem_obj_ggtt_size(obj); |
08c18323 CW |
503 | count++; |
504 | } | |
505 | ||
506 | mutex_unlock(&dev->struct_mutex); | |
507 | ||
508 | seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n", | |
509 | count, total_obj_size, total_gtt_size); | |
510 | ||
511 | return 0; | |
512 | } | |
513 | ||
4e5359cd SF |
514 | static int i915_gem_pageflip_info(struct seq_file *m, void *data) |
515 | { | |
9f25d007 | 516 | struct drm_info_node *node = m->private; |
4e5359cd SF |
517 | struct drm_device *dev = node->minor->dev; |
518 | unsigned long flags; | |
519 | struct intel_crtc *crtc; | |
8a270ebf DV |
520 | int ret; |
521 | ||
522 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
523 | if (ret) | |
524 | return ret; | |
4e5359cd | 525 | |
d3fcc808 | 526 | for_each_intel_crtc(dev, crtc) { |
9db4a9c7 JB |
527 | const char pipe = pipe_name(crtc->pipe); |
528 | const char plane = plane_name(crtc->plane); | |
4e5359cd SF |
529 | struct intel_unpin_work *work; |
530 | ||
531 | spin_lock_irqsave(&dev->event_lock, flags); | |
532 | work = crtc->unpin_work; | |
533 | if (work == NULL) { | |
9db4a9c7 | 534 | seq_printf(m, "No flip due on pipe %c (plane %c)\n", |
4e5359cd SF |
535 | pipe, plane); |
536 | } else { | |
e7d841ca | 537 | if (atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) { |
9db4a9c7 | 538 | seq_printf(m, "Flip queued on pipe %c (plane %c)\n", |
4e5359cd SF |
539 | pipe, plane); |
540 | } else { | |
9db4a9c7 | 541 | seq_printf(m, "Flip pending (waiting for vsync) on pipe %c (plane %c)\n", |
4e5359cd SF |
542 | pipe, plane); |
543 | } | |
544 | if (work->enable_stall_check) | |
267f0c90 | 545 | seq_puts(m, "Stall check enabled, "); |
4e5359cd | 546 | else |
267f0c90 | 547 | seq_puts(m, "Stall check waiting for page flip ioctl, "); |
e7d841ca | 548 | seq_printf(m, "%d prepares\n", atomic_read(&work->pending)); |
4e5359cd SF |
549 | |
550 | if (work->old_fb_obj) { | |
05394f39 CW |
551 | struct drm_i915_gem_object *obj = work->old_fb_obj; |
552 | if (obj) | |
f343c5f6 BW |
553 | seq_printf(m, "Old framebuffer gtt_offset 0x%08lx\n", |
554 | i915_gem_obj_ggtt_offset(obj)); | |
4e5359cd SF |
555 | } |
556 | if (work->pending_flip_obj) { | |
05394f39 CW |
557 | struct drm_i915_gem_object *obj = work->pending_flip_obj; |
558 | if (obj) | |
f343c5f6 BW |
559 | seq_printf(m, "New framebuffer gtt_offset 0x%08lx\n", |
560 | i915_gem_obj_ggtt_offset(obj)); | |
4e5359cd SF |
561 | } |
562 | } | |
563 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
564 | } | |
565 | ||
8a270ebf DV |
566 | mutex_unlock(&dev->struct_mutex); |
567 | ||
4e5359cd SF |
568 | return 0; |
569 | } | |
570 | ||
2017263e BG |
571 | static int i915_gem_request_info(struct seq_file *m, void *data) |
572 | { | |
9f25d007 | 573 | struct drm_info_node *node = m->private; |
2017263e | 574 | struct drm_device *dev = node->minor->dev; |
e277a1f8 | 575 | struct drm_i915_private *dev_priv = dev->dev_private; |
a4872ba6 | 576 | struct intel_engine_cs *ring; |
2017263e | 577 | struct drm_i915_gem_request *gem_request; |
a2c7f6fd | 578 | int ret, count, i; |
de227ef0 CW |
579 | |
580 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
581 | if (ret) | |
582 | return ret; | |
2017263e | 583 | |
c2c347a9 | 584 | count = 0; |
a2c7f6fd CW |
585 | for_each_ring(ring, dev_priv, i) { |
586 | if (list_empty(&ring->request_list)) | |
587 | continue; | |
588 | ||
589 | seq_printf(m, "%s requests:\n", ring->name); | |
c2c347a9 | 590 | list_for_each_entry(gem_request, |
a2c7f6fd | 591 | &ring->request_list, |
c2c347a9 CW |
592 | list) { |
593 | seq_printf(m, " %d @ %d\n", | |
594 | gem_request->seqno, | |
595 | (int) (jiffies - gem_request->emitted_jiffies)); | |
596 | } | |
597 | count++; | |
2017263e | 598 | } |
de227ef0 CW |
599 | mutex_unlock(&dev->struct_mutex); |
600 | ||
c2c347a9 | 601 | if (count == 0) |
267f0c90 | 602 | seq_puts(m, "No requests\n"); |
c2c347a9 | 603 | |
2017263e BG |
604 | return 0; |
605 | } | |
606 | ||
b2223497 | 607 | static void i915_ring_seqno_info(struct seq_file *m, |
a4872ba6 | 608 | struct intel_engine_cs *ring) |
b2223497 CW |
609 | { |
610 | if (ring->get_seqno) { | |
43a7b924 | 611 | seq_printf(m, "Current sequence (%s): %u\n", |
b2eadbc8 | 612 | ring->name, ring->get_seqno(ring, false)); |
b2223497 CW |
613 | } |
614 | } | |
615 | ||
2017263e BG |
616 | static int i915_gem_seqno_info(struct seq_file *m, void *data) |
617 | { | |
9f25d007 | 618 | struct drm_info_node *node = m->private; |
2017263e | 619 | struct drm_device *dev = node->minor->dev; |
e277a1f8 | 620 | struct drm_i915_private *dev_priv = dev->dev_private; |
a4872ba6 | 621 | struct intel_engine_cs *ring; |
1ec14ad3 | 622 | int ret, i; |
de227ef0 CW |
623 | |
624 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
625 | if (ret) | |
626 | return ret; | |
c8c8fb33 | 627 | intel_runtime_pm_get(dev_priv); |
2017263e | 628 | |
a2c7f6fd CW |
629 | for_each_ring(ring, dev_priv, i) |
630 | i915_ring_seqno_info(m, ring); | |
de227ef0 | 631 | |
c8c8fb33 | 632 | intel_runtime_pm_put(dev_priv); |
de227ef0 CW |
633 | mutex_unlock(&dev->struct_mutex); |
634 | ||
2017263e BG |
635 | return 0; |
636 | } | |
637 | ||
638 | ||
639 | static int i915_interrupt_info(struct seq_file *m, void *data) | |
640 | { | |
9f25d007 | 641 | struct drm_info_node *node = m->private; |
2017263e | 642 | struct drm_device *dev = node->minor->dev; |
e277a1f8 | 643 | struct drm_i915_private *dev_priv = dev->dev_private; |
a4872ba6 | 644 | struct intel_engine_cs *ring; |
9db4a9c7 | 645 | int ret, i, pipe; |
de227ef0 CW |
646 | |
647 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
648 | if (ret) | |
649 | return ret; | |
c8c8fb33 | 650 | intel_runtime_pm_get(dev_priv); |
2017263e | 651 | |
74e1ca8c VS |
652 | if (IS_CHERRYVIEW(dev)) { |
653 | int i; | |
654 | seq_printf(m, "Master Interrupt Control:\t%08x\n", | |
655 | I915_READ(GEN8_MASTER_IRQ)); | |
656 | ||
657 | seq_printf(m, "Display IER:\t%08x\n", | |
658 | I915_READ(VLV_IER)); | |
659 | seq_printf(m, "Display IIR:\t%08x\n", | |
660 | I915_READ(VLV_IIR)); | |
661 | seq_printf(m, "Display IIR_RW:\t%08x\n", | |
662 | I915_READ(VLV_IIR_RW)); | |
663 | seq_printf(m, "Display IMR:\t%08x\n", | |
664 | I915_READ(VLV_IMR)); | |
665 | for_each_pipe(pipe) | |
666 | seq_printf(m, "Pipe %c stat:\t%08x\n", | |
667 | pipe_name(pipe), | |
668 | I915_READ(PIPESTAT(pipe))); | |
669 | ||
670 | seq_printf(m, "Port hotplug:\t%08x\n", | |
671 | I915_READ(PORT_HOTPLUG_EN)); | |
672 | seq_printf(m, "DPFLIPSTAT:\t%08x\n", | |
673 | I915_READ(VLV_DPFLIPSTAT)); | |
674 | seq_printf(m, "DPINVGTT:\t%08x\n", | |
675 | I915_READ(DPINVGTT)); | |
676 | ||
677 | for (i = 0; i < 4; i++) { | |
678 | seq_printf(m, "GT Interrupt IMR %d:\t%08x\n", | |
679 | i, I915_READ(GEN8_GT_IMR(i))); | |
680 | seq_printf(m, "GT Interrupt IIR %d:\t%08x\n", | |
681 | i, I915_READ(GEN8_GT_IIR(i))); | |
682 | seq_printf(m, "GT Interrupt IER %d:\t%08x\n", | |
683 | i, I915_READ(GEN8_GT_IER(i))); | |
684 | } | |
685 | ||
686 | seq_printf(m, "PCU interrupt mask:\t%08x\n", | |
687 | I915_READ(GEN8_PCU_IMR)); | |
688 | seq_printf(m, "PCU interrupt identity:\t%08x\n", | |
689 | I915_READ(GEN8_PCU_IIR)); | |
690 | seq_printf(m, "PCU interrupt enable:\t%08x\n", | |
691 | I915_READ(GEN8_PCU_IER)); | |
692 | } else if (INTEL_INFO(dev)->gen >= 8) { | |
a123f157 BW |
693 | seq_printf(m, "Master Interrupt Control:\t%08x\n", |
694 | I915_READ(GEN8_MASTER_IRQ)); | |
695 | ||
696 | for (i = 0; i < 4; i++) { | |
697 | seq_printf(m, "GT Interrupt IMR %d:\t%08x\n", | |
698 | i, I915_READ(GEN8_GT_IMR(i))); | |
699 | seq_printf(m, "GT Interrupt IIR %d:\t%08x\n", | |
700 | i, I915_READ(GEN8_GT_IIR(i))); | |
701 | seq_printf(m, "GT Interrupt IER %d:\t%08x\n", | |
702 | i, I915_READ(GEN8_GT_IER(i))); | |
703 | } | |
704 | ||
07d27e20 | 705 | for_each_pipe(pipe) { |
a123f157 | 706 | seq_printf(m, "Pipe %c IMR:\t%08x\n", |
07d27e20 DL |
707 | pipe_name(pipe), |
708 | I915_READ(GEN8_DE_PIPE_IMR(pipe))); | |
a123f157 | 709 | seq_printf(m, "Pipe %c IIR:\t%08x\n", |
07d27e20 DL |
710 | pipe_name(pipe), |
711 | I915_READ(GEN8_DE_PIPE_IIR(pipe))); | |
a123f157 | 712 | seq_printf(m, "Pipe %c IER:\t%08x\n", |
07d27e20 DL |
713 | pipe_name(pipe), |
714 | I915_READ(GEN8_DE_PIPE_IER(pipe))); | |
a123f157 BW |
715 | } |
716 | ||
717 | seq_printf(m, "Display Engine port interrupt mask:\t%08x\n", | |
718 | I915_READ(GEN8_DE_PORT_IMR)); | |
719 | seq_printf(m, "Display Engine port interrupt identity:\t%08x\n", | |
720 | I915_READ(GEN8_DE_PORT_IIR)); | |
721 | seq_printf(m, "Display Engine port interrupt enable:\t%08x\n", | |
722 | I915_READ(GEN8_DE_PORT_IER)); | |
723 | ||
724 | seq_printf(m, "Display Engine misc interrupt mask:\t%08x\n", | |
725 | I915_READ(GEN8_DE_MISC_IMR)); | |
726 | seq_printf(m, "Display Engine misc interrupt identity:\t%08x\n", | |
727 | I915_READ(GEN8_DE_MISC_IIR)); | |
728 | seq_printf(m, "Display Engine misc interrupt enable:\t%08x\n", | |
729 | I915_READ(GEN8_DE_MISC_IER)); | |
730 | ||
731 | seq_printf(m, "PCU interrupt mask:\t%08x\n", | |
732 | I915_READ(GEN8_PCU_IMR)); | |
733 | seq_printf(m, "PCU interrupt identity:\t%08x\n", | |
734 | I915_READ(GEN8_PCU_IIR)); | |
735 | seq_printf(m, "PCU interrupt enable:\t%08x\n", | |
736 | I915_READ(GEN8_PCU_IER)); | |
737 | } else if (IS_VALLEYVIEW(dev)) { | |
7e231dbe JB |
738 | seq_printf(m, "Display IER:\t%08x\n", |
739 | I915_READ(VLV_IER)); | |
740 | seq_printf(m, "Display IIR:\t%08x\n", | |
741 | I915_READ(VLV_IIR)); | |
742 | seq_printf(m, "Display IIR_RW:\t%08x\n", | |
743 | I915_READ(VLV_IIR_RW)); | |
744 | seq_printf(m, "Display IMR:\t%08x\n", | |
745 | I915_READ(VLV_IMR)); | |
746 | for_each_pipe(pipe) | |
747 | seq_printf(m, "Pipe %c stat:\t%08x\n", | |
748 | pipe_name(pipe), | |
749 | I915_READ(PIPESTAT(pipe))); | |
750 | ||
751 | seq_printf(m, "Master IER:\t%08x\n", | |
752 | I915_READ(VLV_MASTER_IER)); | |
753 | ||
754 | seq_printf(m, "Render IER:\t%08x\n", | |
755 | I915_READ(GTIER)); | |
756 | seq_printf(m, "Render IIR:\t%08x\n", | |
757 | I915_READ(GTIIR)); | |
758 | seq_printf(m, "Render IMR:\t%08x\n", | |
759 | I915_READ(GTIMR)); | |
760 | ||
761 | seq_printf(m, "PM IER:\t\t%08x\n", | |
762 | I915_READ(GEN6_PMIER)); | |
763 | seq_printf(m, "PM IIR:\t\t%08x\n", | |
764 | I915_READ(GEN6_PMIIR)); | |
765 | seq_printf(m, "PM IMR:\t\t%08x\n", | |
766 | I915_READ(GEN6_PMIMR)); | |
767 | ||
768 | seq_printf(m, "Port hotplug:\t%08x\n", | |
769 | I915_READ(PORT_HOTPLUG_EN)); | |
770 | seq_printf(m, "DPFLIPSTAT:\t%08x\n", | |
771 | I915_READ(VLV_DPFLIPSTAT)); | |
772 | seq_printf(m, "DPINVGTT:\t%08x\n", | |
773 | I915_READ(DPINVGTT)); | |
774 | ||
775 | } else if (!HAS_PCH_SPLIT(dev)) { | |
5f6a1695 ZW |
776 | seq_printf(m, "Interrupt enable: %08x\n", |
777 | I915_READ(IER)); | |
778 | seq_printf(m, "Interrupt identity: %08x\n", | |
779 | I915_READ(IIR)); | |
780 | seq_printf(m, "Interrupt mask: %08x\n", | |
781 | I915_READ(IMR)); | |
9db4a9c7 JB |
782 | for_each_pipe(pipe) |
783 | seq_printf(m, "Pipe %c stat: %08x\n", | |
784 | pipe_name(pipe), | |
785 | I915_READ(PIPESTAT(pipe))); | |
5f6a1695 ZW |
786 | } else { |
787 | seq_printf(m, "North Display Interrupt enable: %08x\n", | |
788 | I915_READ(DEIER)); | |
789 | seq_printf(m, "North Display Interrupt identity: %08x\n", | |
790 | I915_READ(DEIIR)); | |
791 | seq_printf(m, "North Display Interrupt mask: %08x\n", | |
792 | I915_READ(DEIMR)); | |
793 | seq_printf(m, "South Display Interrupt enable: %08x\n", | |
794 | I915_READ(SDEIER)); | |
795 | seq_printf(m, "South Display Interrupt identity: %08x\n", | |
796 | I915_READ(SDEIIR)); | |
797 | seq_printf(m, "South Display Interrupt mask: %08x\n", | |
798 | I915_READ(SDEIMR)); | |
799 | seq_printf(m, "Graphics Interrupt enable: %08x\n", | |
800 | I915_READ(GTIER)); | |
801 | seq_printf(m, "Graphics Interrupt identity: %08x\n", | |
802 | I915_READ(GTIIR)); | |
803 | seq_printf(m, "Graphics Interrupt mask: %08x\n", | |
804 | I915_READ(GTIMR)); | |
805 | } | |
a2c7f6fd | 806 | for_each_ring(ring, dev_priv, i) { |
a123f157 | 807 | if (INTEL_INFO(dev)->gen >= 6) { |
a2c7f6fd CW |
808 | seq_printf(m, |
809 | "Graphics Interrupt mask (%s): %08x\n", | |
810 | ring->name, I915_READ_IMR(ring)); | |
9862e600 | 811 | } |
a2c7f6fd | 812 | i915_ring_seqno_info(m, ring); |
9862e600 | 813 | } |
c8c8fb33 | 814 | intel_runtime_pm_put(dev_priv); |
de227ef0 CW |
815 | mutex_unlock(&dev->struct_mutex); |
816 | ||
2017263e BG |
817 | return 0; |
818 | } | |
819 | ||
a6172a80 CW |
820 | static int i915_gem_fence_regs_info(struct seq_file *m, void *data) |
821 | { | |
9f25d007 | 822 | struct drm_info_node *node = m->private; |
a6172a80 | 823 | struct drm_device *dev = node->minor->dev; |
e277a1f8 | 824 | struct drm_i915_private *dev_priv = dev->dev_private; |
de227ef0 CW |
825 | int i, ret; |
826 | ||
827 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
828 | if (ret) | |
829 | return ret; | |
a6172a80 CW |
830 | |
831 | seq_printf(m, "Reserved fences = %d\n", dev_priv->fence_reg_start); | |
832 | seq_printf(m, "Total fences = %d\n", dev_priv->num_fence_regs); | |
833 | for (i = 0; i < dev_priv->num_fence_regs; i++) { | |
05394f39 | 834 | struct drm_i915_gem_object *obj = dev_priv->fence_regs[i].obj; |
a6172a80 | 835 | |
6c085a72 CW |
836 | seq_printf(m, "Fence %d, pin count = %d, object = ", |
837 | i, dev_priv->fence_regs[i].pin_count); | |
c2c347a9 | 838 | if (obj == NULL) |
267f0c90 | 839 | seq_puts(m, "unused"); |
c2c347a9 | 840 | else |
05394f39 | 841 | describe_obj(m, obj); |
267f0c90 | 842 | seq_putc(m, '\n'); |
a6172a80 CW |
843 | } |
844 | ||
05394f39 | 845 | mutex_unlock(&dev->struct_mutex); |
a6172a80 CW |
846 | return 0; |
847 | } | |
848 | ||
2017263e BG |
849 | static int i915_hws_info(struct seq_file *m, void *data) |
850 | { | |
9f25d007 | 851 | struct drm_info_node *node = m->private; |
2017263e | 852 | struct drm_device *dev = node->minor->dev; |
e277a1f8 | 853 | struct drm_i915_private *dev_priv = dev->dev_private; |
a4872ba6 | 854 | struct intel_engine_cs *ring; |
1a240d4d | 855 | const u32 *hws; |
4066c0ae CW |
856 | int i; |
857 | ||
1ec14ad3 | 858 | ring = &dev_priv->ring[(uintptr_t)node->info_ent->data]; |
1a240d4d | 859 | hws = ring->status_page.page_addr; |
2017263e BG |
860 | if (hws == NULL) |
861 | return 0; | |
862 | ||
863 | for (i = 0; i < 4096 / sizeof(u32) / 4; i += 4) { | |
864 | seq_printf(m, "0x%08x: 0x%08x 0x%08x 0x%08x 0x%08x\n", | |
865 | i * 4, | |
866 | hws[i], hws[i + 1], hws[i + 2], hws[i + 3]); | |
867 | } | |
868 | return 0; | |
869 | } | |
870 | ||
d5442303 DV |
871 | static ssize_t |
872 | i915_error_state_write(struct file *filp, | |
873 | const char __user *ubuf, | |
874 | size_t cnt, | |
875 | loff_t *ppos) | |
876 | { | |
edc3d884 | 877 | struct i915_error_state_file_priv *error_priv = filp->private_data; |
d5442303 | 878 | struct drm_device *dev = error_priv->dev; |
22bcfc6a | 879 | int ret; |
d5442303 DV |
880 | |
881 | DRM_DEBUG_DRIVER("Resetting error state\n"); | |
882 | ||
22bcfc6a DV |
883 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
884 | if (ret) | |
885 | return ret; | |
886 | ||
d5442303 DV |
887 | i915_destroy_error_state(dev); |
888 | mutex_unlock(&dev->struct_mutex); | |
889 | ||
890 | return cnt; | |
891 | } | |
892 | ||
893 | static int i915_error_state_open(struct inode *inode, struct file *file) | |
894 | { | |
895 | struct drm_device *dev = inode->i_private; | |
d5442303 | 896 | struct i915_error_state_file_priv *error_priv; |
d5442303 DV |
897 | |
898 | error_priv = kzalloc(sizeof(*error_priv), GFP_KERNEL); | |
899 | if (!error_priv) | |
900 | return -ENOMEM; | |
901 | ||
902 | error_priv->dev = dev; | |
903 | ||
95d5bfb3 | 904 | i915_error_state_get(dev, error_priv); |
d5442303 | 905 | |
edc3d884 MK |
906 | file->private_data = error_priv; |
907 | ||
908 | return 0; | |
d5442303 DV |
909 | } |
910 | ||
911 | static int i915_error_state_release(struct inode *inode, struct file *file) | |
912 | { | |
edc3d884 | 913 | struct i915_error_state_file_priv *error_priv = file->private_data; |
d5442303 | 914 | |
95d5bfb3 | 915 | i915_error_state_put(error_priv); |
d5442303 DV |
916 | kfree(error_priv); |
917 | ||
edc3d884 MK |
918 | return 0; |
919 | } | |
920 | ||
4dc955f7 MK |
921 | static ssize_t i915_error_state_read(struct file *file, char __user *userbuf, |
922 | size_t count, loff_t *pos) | |
923 | { | |
924 | struct i915_error_state_file_priv *error_priv = file->private_data; | |
925 | struct drm_i915_error_state_buf error_str; | |
926 | loff_t tmp_pos = 0; | |
927 | ssize_t ret_count = 0; | |
928 | int ret; | |
929 | ||
930 | ret = i915_error_state_buf_init(&error_str, count, *pos); | |
931 | if (ret) | |
932 | return ret; | |
edc3d884 | 933 | |
fc16b48b | 934 | ret = i915_error_state_to_str(&error_str, error_priv); |
edc3d884 MK |
935 | if (ret) |
936 | goto out; | |
937 | ||
edc3d884 MK |
938 | ret_count = simple_read_from_buffer(userbuf, count, &tmp_pos, |
939 | error_str.buf, | |
940 | error_str.bytes); | |
941 | ||
942 | if (ret_count < 0) | |
943 | ret = ret_count; | |
944 | else | |
945 | *pos = error_str.start + ret_count; | |
946 | out: | |
4dc955f7 | 947 | i915_error_state_buf_release(&error_str); |
edc3d884 | 948 | return ret ?: ret_count; |
d5442303 DV |
949 | } |
950 | ||
951 | static const struct file_operations i915_error_state_fops = { | |
952 | .owner = THIS_MODULE, | |
953 | .open = i915_error_state_open, | |
edc3d884 | 954 | .read = i915_error_state_read, |
d5442303 DV |
955 | .write = i915_error_state_write, |
956 | .llseek = default_llseek, | |
957 | .release = i915_error_state_release, | |
958 | }; | |
959 | ||
647416f9 KC |
960 | static int |
961 | i915_next_seqno_get(void *data, u64 *val) | |
40633219 | 962 | { |
647416f9 | 963 | struct drm_device *dev = data; |
e277a1f8 | 964 | struct drm_i915_private *dev_priv = dev->dev_private; |
40633219 MK |
965 | int ret; |
966 | ||
967 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
968 | if (ret) | |
969 | return ret; | |
970 | ||
647416f9 | 971 | *val = dev_priv->next_seqno; |
40633219 MK |
972 | mutex_unlock(&dev->struct_mutex); |
973 | ||
647416f9 | 974 | return 0; |
40633219 MK |
975 | } |
976 | ||
647416f9 KC |
977 | static int |
978 | i915_next_seqno_set(void *data, u64 val) | |
979 | { | |
980 | struct drm_device *dev = data; | |
40633219 MK |
981 | int ret; |
982 | ||
40633219 MK |
983 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
984 | if (ret) | |
985 | return ret; | |
986 | ||
e94fbaa8 | 987 | ret = i915_gem_set_seqno(dev, val); |
40633219 MK |
988 | mutex_unlock(&dev->struct_mutex); |
989 | ||
647416f9 | 990 | return ret; |
40633219 MK |
991 | } |
992 | ||
647416f9 KC |
993 | DEFINE_SIMPLE_ATTRIBUTE(i915_next_seqno_fops, |
994 | i915_next_seqno_get, i915_next_seqno_set, | |
3a3b4f98 | 995 | "0x%llx\n"); |
40633219 | 996 | |
adb4bd12 | 997 | static int i915_frequency_info(struct seq_file *m, void *unused) |
f97108d1 | 998 | { |
9f25d007 | 999 | struct drm_info_node *node = m->private; |
f97108d1 | 1000 | struct drm_device *dev = node->minor->dev; |
e277a1f8 | 1001 | struct drm_i915_private *dev_priv = dev->dev_private; |
c8c8fb33 PZ |
1002 | int ret = 0; |
1003 | ||
1004 | intel_runtime_pm_get(dev_priv); | |
3b8d8d91 | 1005 | |
5c9669ce TR |
1006 | flush_delayed_work(&dev_priv->rps.delayed_resume_work); |
1007 | ||
3b8d8d91 JB |
1008 | if (IS_GEN5(dev)) { |
1009 | u16 rgvswctl = I915_READ16(MEMSWCTL); | |
1010 | u16 rgvstat = I915_READ16(MEMSTAT_ILK); | |
1011 | ||
1012 | seq_printf(m, "Requested P-state: %d\n", (rgvswctl >> 8) & 0xf); | |
1013 | seq_printf(m, "Requested VID: %d\n", rgvswctl & 0x3f); | |
1014 | seq_printf(m, "Current VID: %d\n", (rgvstat & MEMSTAT_VID_MASK) >> | |
1015 | MEMSTAT_VID_SHIFT); | |
1016 | seq_printf(m, "Current P-state: %d\n", | |
1017 | (rgvstat & MEMSTAT_PSTATE_MASK) >> MEMSTAT_PSTATE_SHIFT); | |
daa3afb2 TR |
1018 | } else if (IS_GEN6(dev) || (IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) || |
1019 | IS_BROADWELL(dev)) { | |
3b8d8d91 JB |
1020 | u32 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS); |
1021 | u32 rp_state_limits = I915_READ(GEN6_RP_STATE_LIMITS); | |
1022 | u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP); | |
0d8f9491 | 1023 | u32 rpmodectl, rpinclimit, rpdeclimit; |
8e8c06cd | 1024 | u32 rpstat, cagf, reqf; |
ccab5c82 JB |
1025 | u32 rpupei, rpcurup, rpprevup; |
1026 | u32 rpdownei, rpcurdown, rpprevdown; | |
3b8d8d91 JB |
1027 | int max_freq; |
1028 | ||
1029 | /* RPSTAT1 is in the GT power well */ | |
d1ebd816 BW |
1030 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
1031 | if (ret) | |
c8c8fb33 | 1032 | goto out; |
d1ebd816 | 1033 | |
c8d9a590 | 1034 | gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL); |
3b8d8d91 | 1035 | |
8e8c06cd CW |
1036 | reqf = I915_READ(GEN6_RPNSWREQ); |
1037 | reqf &= ~GEN6_TURBO_DISABLE; | |
daa3afb2 | 1038 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
8e8c06cd CW |
1039 | reqf >>= 24; |
1040 | else | |
1041 | reqf >>= 25; | |
1042 | reqf *= GT_FREQUENCY_MULTIPLIER; | |
1043 | ||
0d8f9491 CW |
1044 | rpmodectl = I915_READ(GEN6_RP_CONTROL); |
1045 | rpinclimit = I915_READ(GEN6_RP_UP_THRESHOLD); | |
1046 | rpdeclimit = I915_READ(GEN6_RP_DOWN_THRESHOLD); | |
1047 | ||
ccab5c82 JB |
1048 | rpstat = I915_READ(GEN6_RPSTAT1); |
1049 | rpupei = I915_READ(GEN6_RP_CUR_UP_EI); | |
1050 | rpcurup = I915_READ(GEN6_RP_CUR_UP); | |
1051 | rpprevup = I915_READ(GEN6_RP_PREV_UP); | |
1052 | rpdownei = I915_READ(GEN6_RP_CUR_DOWN_EI); | |
1053 | rpcurdown = I915_READ(GEN6_RP_CUR_DOWN); | |
1054 | rpprevdown = I915_READ(GEN6_RP_PREV_DOWN); | |
daa3afb2 | 1055 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
f82855d3 BW |
1056 | cagf = (rpstat & HSW_CAGF_MASK) >> HSW_CAGF_SHIFT; |
1057 | else | |
1058 | cagf = (rpstat & GEN6_CAGF_MASK) >> GEN6_CAGF_SHIFT; | |
1059 | cagf *= GT_FREQUENCY_MULTIPLIER; | |
ccab5c82 | 1060 | |
c8d9a590 | 1061 | gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL); |
d1ebd816 BW |
1062 | mutex_unlock(&dev->struct_mutex); |
1063 | ||
0d8f9491 CW |
1064 | seq_printf(m, "PM IER=0x%08x IMR=0x%08x ISR=0x%08x IIR=0x%08x, MASK=0x%08x\n", |
1065 | I915_READ(GEN6_PMIER), | |
1066 | I915_READ(GEN6_PMIMR), | |
1067 | I915_READ(GEN6_PMISR), | |
1068 | I915_READ(GEN6_PMIIR), | |
1069 | I915_READ(GEN6_PMINTRMSK)); | |
3b8d8d91 | 1070 | seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status); |
3b8d8d91 JB |
1071 | seq_printf(m, "Render p-state ratio: %d\n", |
1072 | (gt_perf_status & 0xff00) >> 8); | |
1073 | seq_printf(m, "Render p-state VID: %d\n", | |
1074 | gt_perf_status & 0xff); | |
1075 | seq_printf(m, "Render p-state limit: %d\n", | |
1076 | rp_state_limits & 0xff); | |
0d8f9491 CW |
1077 | seq_printf(m, "RPSTAT1: 0x%08x\n", rpstat); |
1078 | seq_printf(m, "RPMODECTL: 0x%08x\n", rpmodectl); | |
1079 | seq_printf(m, "RPINCLIMIT: 0x%08x\n", rpinclimit); | |
1080 | seq_printf(m, "RPDECLIMIT: 0x%08x\n", rpdeclimit); | |
8e8c06cd | 1081 | seq_printf(m, "RPNSWREQ: %dMHz\n", reqf); |
f82855d3 | 1082 | seq_printf(m, "CAGF: %dMHz\n", cagf); |
ccab5c82 JB |
1083 | seq_printf(m, "RP CUR UP EI: %dus\n", rpupei & |
1084 | GEN6_CURICONT_MASK); | |
1085 | seq_printf(m, "RP CUR UP: %dus\n", rpcurup & | |
1086 | GEN6_CURBSYTAVG_MASK); | |
1087 | seq_printf(m, "RP PREV UP: %dus\n", rpprevup & | |
1088 | GEN6_CURBSYTAVG_MASK); | |
1089 | seq_printf(m, "RP CUR DOWN EI: %dus\n", rpdownei & | |
1090 | GEN6_CURIAVG_MASK); | |
1091 | seq_printf(m, "RP CUR DOWN: %dus\n", rpcurdown & | |
1092 | GEN6_CURBSYTAVG_MASK); | |
1093 | seq_printf(m, "RP PREV DOWN: %dus\n", rpprevdown & | |
1094 | GEN6_CURBSYTAVG_MASK); | |
3b8d8d91 JB |
1095 | |
1096 | max_freq = (rp_state_cap & 0xff0000) >> 16; | |
1097 | seq_printf(m, "Lowest (RPN) frequency: %dMHz\n", | |
c8735b0c | 1098 | max_freq * GT_FREQUENCY_MULTIPLIER); |
3b8d8d91 JB |
1099 | |
1100 | max_freq = (rp_state_cap & 0xff00) >> 8; | |
1101 | seq_printf(m, "Nominal (RP1) frequency: %dMHz\n", | |
c8735b0c | 1102 | max_freq * GT_FREQUENCY_MULTIPLIER); |
3b8d8d91 JB |
1103 | |
1104 | max_freq = rp_state_cap & 0xff; | |
1105 | seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n", | |
c8735b0c | 1106 | max_freq * GT_FREQUENCY_MULTIPLIER); |
31c77388 BW |
1107 | |
1108 | seq_printf(m, "Max overclocked frequency: %dMHz\n", | |
b39fb297 | 1109 | dev_priv->rps.max_freq * GT_FREQUENCY_MULTIPLIER); |
0a073b84 | 1110 | } else if (IS_VALLEYVIEW(dev)) { |
03af2045 | 1111 | u32 freq_sts; |
0a073b84 | 1112 | |
259bd5d4 | 1113 | mutex_lock(&dev_priv->rps.hw_lock); |
64936258 | 1114 | freq_sts = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS); |
0a073b84 JB |
1115 | seq_printf(m, "PUNIT_REG_GPU_FREQ_STS: 0x%08x\n", freq_sts); |
1116 | seq_printf(m, "DDR freq: %d MHz\n", dev_priv->mem_freq); | |
1117 | ||
0a073b84 | 1118 | seq_printf(m, "max GPU freq: %d MHz\n", |
b2435c94 | 1119 | vlv_gpu_freq(dev_priv, dev_priv->rps.max_freq)); |
0a073b84 | 1120 | |
0a073b84 | 1121 | seq_printf(m, "min GPU freq: %d MHz\n", |
b2435c94 | 1122 | vlv_gpu_freq(dev_priv, dev_priv->rps.min_freq)); |
03af2045 VS |
1123 | |
1124 | seq_printf(m, "efficient (RPe) frequency: %d MHz\n", | |
b2435c94 | 1125 | vlv_gpu_freq(dev_priv, dev_priv->rps.efficient_freq)); |
0a073b84 JB |
1126 | |
1127 | seq_printf(m, "current GPU freq: %d MHz\n", | |
2ec3815f | 1128 | vlv_gpu_freq(dev_priv, (freq_sts >> 8) & 0xff)); |
259bd5d4 | 1129 | mutex_unlock(&dev_priv->rps.hw_lock); |
3b8d8d91 | 1130 | } else { |
267f0c90 | 1131 | seq_puts(m, "no P-state info available\n"); |
3b8d8d91 | 1132 | } |
f97108d1 | 1133 | |
c8c8fb33 PZ |
1134 | out: |
1135 | intel_runtime_pm_put(dev_priv); | |
1136 | return ret; | |
f97108d1 JB |
1137 | } |
1138 | ||
4d85529d | 1139 | static int ironlake_drpc_info(struct seq_file *m) |
f97108d1 | 1140 | { |
9f25d007 | 1141 | struct drm_info_node *node = m->private; |
f97108d1 | 1142 | struct drm_device *dev = node->minor->dev; |
e277a1f8 | 1143 | struct drm_i915_private *dev_priv = dev->dev_private; |
616fdb5a BW |
1144 | u32 rgvmodectl, rstdbyctl; |
1145 | u16 crstandvid; | |
1146 | int ret; | |
1147 | ||
1148 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
1149 | if (ret) | |
1150 | return ret; | |
c8c8fb33 | 1151 | intel_runtime_pm_get(dev_priv); |
616fdb5a BW |
1152 | |
1153 | rgvmodectl = I915_READ(MEMMODECTL); | |
1154 | rstdbyctl = I915_READ(RSTDBYCTL); | |
1155 | crstandvid = I915_READ16(CRSTANDVID); | |
1156 | ||
c8c8fb33 | 1157 | intel_runtime_pm_put(dev_priv); |
616fdb5a | 1158 | mutex_unlock(&dev->struct_mutex); |
f97108d1 JB |
1159 | |
1160 | seq_printf(m, "HD boost: %s\n", (rgvmodectl & MEMMODE_BOOST_EN) ? | |
1161 | "yes" : "no"); | |
1162 | seq_printf(m, "Boost freq: %d\n", | |
1163 | (rgvmodectl & MEMMODE_BOOST_FREQ_MASK) >> | |
1164 | MEMMODE_BOOST_FREQ_SHIFT); | |
1165 | seq_printf(m, "HW control enabled: %s\n", | |
1166 | rgvmodectl & MEMMODE_HWIDLE_EN ? "yes" : "no"); | |
1167 | seq_printf(m, "SW control enabled: %s\n", | |
1168 | rgvmodectl & MEMMODE_SWMODE_EN ? "yes" : "no"); | |
1169 | seq_printf(m, "Gated voltage change: %s\n", | |
1170 | rgvmodectl & MEMMODE_RCLK_GATE ? "yes" : "no"); | |
1171 | seq_printf(m, "Starting frequency: P%d\n", | |
1172 | (rgvmodectl & MEMMODE_FSTART_MASK) >> MEMMODE_FSTART_SHIFT); | |
7648fa99 | 1173 | seq_printf(m, "Max P-state: P%d\n", |
f97108d1 | 1174 | (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT); |
7648fa99 JB |
1175 | seq_printf(m, "Min P-state: P%d\n", (rgvmodectl & MEMMODE_FMIN_MASK)); |
1176 | seq_printf(m, "RS1 VID: %d\n", (crstandvid & 0x3f)); | |
1177 | seq_printf(m, "RS2 VID: %d\n", ((crstandvid >> 8) & 0x3f)); | |
1178 | seq_printf(m, "Render standby enabled: %s\n", | |
1179 | (rstdbyctl & RCX_SW_EXIT) ? "no" : "yes"); | |
267f0c90 | 1180 | seq_puts(m, "Current RS state: "); |
88271da3 JB |
1181 | switch (rstdbyctl & RSX_STATUS_MASK) { |
1182 | case RSX_STATUS_ON: | |
267f0c90 | 1183 | seq_puts(m, "on\n"); |
88271da3 JB |
1184 | break; |
1185 | case RSX_STATUS_RC1: | |
267f0c90 | 1186 | seq_puts(m, "RC1\n"); |
88271da3 JB |
1187 | break; |
1188 | case RSX_STATUS_RC1E: | |
267f0c90 | 1189 | seq_puts(m, "RC1E\n"); |
88271da3 JB |
1190 | break; |
1191 | case RSX_STATUS_RS1: | |
267f0c90 | 1192 | seq_puts(m, "RS1\n"); |
88271da3 JB |
1193 | break; |
1194 | case RSX_STATUS_RS2: | |
267f0c90 | 1195 | seq_puts(m, "RS2 (RC6)\n"); |
88271da3 JB |
1196 | break; |
1197 | case RSX_STATUS_RS3: | |
267f0c90 | 1198 | seq_puts(m, "RC3 (RC6+)\n"); |
88271da3 JB |
1199 | break; |
1200 | default: | |
267f0c90 | 1201 | seq_puts(m, "unknown\n"); |
88271da3 JB |
1202 | break; |
1203 | } | |
f97108d1 JB |
1204 | |
1205 | return 0; | |
1206 | } | |
1207 | ||
669ab5aa D |
1208 | static int vlv_drpc_info(struct seq_file *m) |
1209 | { | |
1210 | ||
9f25d007 | 1211 | struct drm_info_node *node = m->private; |
669ab5aa D |
1212 | struct drm_device *dev = node->minor->dev; |
1213 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1214 | u32 rpmodectl1, rcctl1; | |
1215 | unsigned fw_rendercount = 0, fw_mediacount = 0; | |
1216 | ||
d46c0517 ID |
1217 | intel_runtime_pm_get(dev_priv); |
1218 | ||
669ab5aa D |
1219 | rpmodectl1 = I915_READ(GEN6_RP_CONTROL); |
1220 | rcctl1 = I915_READ(GEN6_RC_CONTROL); | |
1221 | ||
d46c0517 ID |
1222 | intel_runtime_pm_put(dev_priv); |
1223 | ||
669ab5aa D |
1224 | seq_printf(m, "Video Turbo Mode: %s\n", |
1225 | yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO)); | |
1226 | seq_printf(m, "Turbo enabled: %s\n", | |
1227 | yesno(rpmodectl1 & GEN6_RP_ENABLE)); | |
1228 | seq_printf(m, "HW control enabled: %s\n", | |
1229 | yesno(rpmodectl1 & GEN6_RP_ENABLE)); | |
1230 | seq_printf(m, "SW control enabled: %s\n", | |
1231 | yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) == | |
1232 | GEN6_RP_MEDIA_SW_MODE)); | |
1233 | seq_printf(m, "RC6 Enabled: %s\n", | |
1234 | yesno(rcctl1 & (GEN7_RC_CTL_TO_MODE | | |
1235 | GEN6_RC_CTL_EI_MODE(1)))); | |
1236 | seq_printf(m, "Render Power Well: %s\n", | |
1237 | (I915_READ(VLV_GTLC_PW_STATUS) & | |
1238 | VLV_GTLC_PW_RENDER_STATUS_MASK) ? "Up" : "Down"); | |
1239 | seq_printf(m, "Media Power Well: %s\n", | |
1240 | (I915_READ(VLV_GTLC_PW_STATUS) & | |
1241 | VLV_GTLC_PW_MEDIA_STATUS_MASK) ? "Up" : "Down"); | |
1242 | ||
9cc19be5 ID |
1243 | seq_printf(m, "Render RC6 residency since boot: %u\n", |
1244 | I915_READ(VLV_GT_RENDER_RC6)); | |
1245 | seq_printf(m, "Media RC6 residency since boot: %u\n", | |
1246 | I915_READ(VLV_GT_MEDIA_RC6)); | |
1247 | ||
669ab5aa D |
1248 | spin_lock_irq(&dev_priv->uncore.lock); |
1249 | fw_rendercount = dev_priv->uncore.fw_rendercount; | |
1250 | fw_mediacount = dev_priv->uncore.fw_mediacount; | |
1251 | spin_unlock_irq(&dev_priv->uncore.lock); | |
1252 | ||
1253 | seq_printf(m, "Forcewake Render Count = %u\n", fw_rendercount); | |
1254 | seq_printf(m, "Forcewake Media Count = %u\n", fw_mediacount); | |
1255 | ||
1256 | ||
1257 | return 0; | |
1258 | } | |
1259 | ||
1260 | ||
4d85529d BW |
1261 | static int gen6_drpc_info(struct seq_file *m) |
1262 | { | |
1263 | ||
9f25d007 | 1264 | struct drm_info_node *node = m->private; |
4d85529d BW |
1265 | struct drm_device *dev = node->minor->dev; |
1266 | struct drm_i915_private *dev_priv = dev->dev_private; | |
ecd8faea | 1267 | u32 rpmodectl1, gt_core_status, rcctl1, rc6vids = 0; |
93b525dc | 1268 | unsigned forcewake_count; |
aee56cff | 1269 | int count = 0, ret; |
4d85529d BW |
1270 | |
1271 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
1272 | if (ret) | |
1273 | return ret; | |
c8c8fb33 | 1274 | intel_runtime_pm_get(dev_priv); |
4d85529d | 1275 | |
907b28c5 CW |
1276 | spin_lock_irq(&dev_priv->uncore.lock); |
1277 | forcewake_count = dev_priv->uncore.forcewake_count; | |
1278 | spin_unlock_irq(&dev_priv->uncore.lock); | |
93b525dc DV |
1279 | |
1280 | if (forcewake_count) { | |
267f0c90 DL |
1281 | seq_puts(m, "RC information inaccurate because somebody " |
1282 | "holds a forcewake reference \n"); | |
4d85529d BW |
1283 | } else { |
1284 | /* NB: we cannot use forcewake, else we read the wrong values */ | |
1285 | while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1)) | |
1286 | udelay(10); | |
1287 | seq_printf(m, "RC information accurate: %s\n", yesno(count < 51)); | |
1288 | } | |
1289 | ||
1290 | gt_core_status = readl(dev_priv->regs + GEN6_GT_CORE_STATUS); | |
ed71f1b4 | 1291 | trace_i915_reg_rw(false, GEN6_GT_CORE_STATUS, gt_core_status, 4, true); |
4d85529d BW |
1292 | |
1293 | rpmodectl1 = I915_READ(GEN6_RP_CONTROL); | |
1294 | rcctl1 = I915_READ(GEN6_RC_CONTROL); | |
1295 | mutex_unlock(&dev->struct_mutex); | |
44cbd338 BW |
1296 | mutex_lock(&dev_priv->rps.hw_lock); |
1297 | sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids); | |
1298 | mutex_unlock(&dev_priv->rps.hw_lock); | |
4d85529d | 1299 | |
c8c8fb33 PZ |
1300 | intel_runtime_pm_put(dev_priv); |
1301 | ||
4d85529d BW |
1302 | seq_printf(m, "Video Turbo Mode: %s\n", |
1303 | yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO)); | |
1304 | seq_printf(m, "HW control enabled: %s\n", | |
1305 | yesno(rpmodectl1 & GEN6_RP_ENABLE)); | |
1306 | seq_printf(m, "SW control enabled: %s\n", | |
1307 | yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) == | |
1308 | GEN6_RP_MEDIA_SW_MODE)); | |
fff24e21 | 1309 | seq_printf(m, "RC1e Enabled: %s\n", |
4d85529d BW |
1310 | yesno(rcctl1 & GEN6_RC_CTL_RC1e_ENABLE)); |
1311 | seq_printf(m, "RC6 Enabled: %s\n", | |
1312 | yesno(rcctl1 & GEN6_RC_CTL_RC6_ENABLE)); | |
1313 | seq_printf(m, "Deep RC6 Enabled: %s\n", | |
1314 | yesno(rcctl1 & GEN6_RC_CTL_RC6p_ENABLE)); | |
1315 | seq_printf(m, "Deepest RC6 Enabled: %s\n", | |
1316 | yesno(rcctl1 & GEN6_RC_CTL_RC6pp_ENABLE)); | |
267f0c90 | 1317 | seq_puts(m, "Current RC state: "); |
4d85529d BW |
1318 | switch (gt_core_status & GEN6_RCn_MASK) { |
1319 | case GEN6_RC0: | |
1320 | if (gt_core_status & GEN6_CORE_CPD_STATE_MASK) | |
267f0c90 | 1321 | seq_puts(m, "Core Power Down\n"); |
4d85529d | 1322 | else |
267f0c90 | 1323 | seq_puts(m, "on\n"); |
4d85529d BW |
1324 | break; |
1325 | case GEN6_RC3: | |
267f0c90 | 1326 | seq_puts(m, "RC3\n"); |
4d85529d BW |
1327 | break; |
1328 | case GEN6_RC6: | |
267f0c90 | 1329 | seq_puts(m, "RC6\n"); |
4d85529d BW |
1330 | break; |
1331 | case GEN6_RC7: | |
267f0c90 | 1332 | seq_puts(m, "RC7\n"); |
4d85529d BW |
1333 | break; |
1334 | default: | |
267f0c90 | 1335 | seq_puts(m, "Unknown\n"); |
4d85529d BW |
1336 | break; |
1337 | } | |
1338 | ||
1339 | seq_printf(m, "Core Power Down: %s\n", | |
1340 | yesno(gt_core_status & GEN6_CORE_CPD_STATE_MASK)); | |
cce66a28 BW |
1341 | |
1342 | /* Not exactly sure what this is */ | |
1343 | seq_printf(m, "RC6 \"Locked to RPn\" residency since boot: %u\n", | |
1344 | I915_READ(GEN6_GT_GFX_RC6_LOCKED)); | |
1345 | seq_printf(m, "RC6 residency since boot: %u\n", | |
1346 | I915_READ(GEN6_GT_GFX_RC6)); | |
1347 | seq_printf(m, "RC6+ residency since boot: %u\n", | |
1348 | I915_READ(GEN6_GT_GFX_RC6p)); | |
1349 | seq_printf(m, "RC6++ residency since boot: %u\n", | |
1350 | I915_READ(GEN6_GT_GFX_RC6pp)); | |
1351 | ||
ecd8faea BW |
1352 | seq_printf(m, "RC6 voltage: %dmV\n", |
1353 | GEN6_DECODE_RC6_VID(((rc6vids >> 0) & 0xff))); | |
1354 | seq_printf(m, "RC6+ voltage: %dmV\n", | |
1355 | GEN6_DECODE_RC6_VID(((rc6vids >> 8) & 0xff))); | |
1356 | seq_printf(m, "RC6++ voltage: %dmV\n", | |
1357 | GEN6_DECODE_RC6_VID(((rc6vids >> 16) & 0xff))); | |
4d85529d BW |
1358 | return 0; |
1359 | } | |
1360 | ||
1361 | static int i915_drpc_info(struct seq_file *m, void *unused) | |
1362 | { | |
9f25d007 | 1363 | struct drm_info_node *node = m->private; |
4d85529d BW |
1364 | struct drm_device *dev = node->minor->dev; |
1365 | ||
669ab5aa D |
1366 | if (IS_VALLEYVIEW(dev)) |
1367 | return vlv_drpc_info(m); | |
1368 | else if (IS_GEN6(dev) || IS_GEN7(dev)) | |
4d85529d BW |
1369 | return gen6_drpc_info(m); |
1370 | else | |
1371 | return ironlake_drpc_info(m); | |
1372 | } | |
1373 | ||
b5e50c3f JB |
1374 | static int i915_fbc_status(struct seq_file *m, void *unused) |
1375 | { | |
9f25d007 | 1376 | struct drm_info_node *node = m->private; |
b5e50c3f | 1377 | struct drm_device *dev = node->minor->dev; |
e277a1f8 | 1378 | struct drm_i915_private *dev_priv = dev->dev_private; |
b5e50c3f | 1379 | |
3a77c4c4 | 1380 | if (!HAS_FBC(dev)) { |
267f0c90 | 1381 | seq_puts(m, "FBC unsupported on this chipset\n"); |
b5e50c3f JB |
1382 | return 0; |
1383 | } | |
1384 | ||
36623ef8 PZ |
1385 | intel_runtime_pm_get(dev_priv); |
1386 | ||
ee5382ae | 1387 | if (intel_fbc_enabled(dev)) { |
267f0c90 | 1388 | seq_puts(m, "FBC enabled\n"); |
b5e50c3f | 1389 | } else { |
267f0c90 | 1390 | seq_puts(m, "FBC disabled: "); |
5c3fe8b0 | 1391 | switch (dev_priv->fbc.no_fbc_reason) { |
29ebf90f CW |
1392 | case FBC_OK: |
1393 | seq_puts(m, "FBC actived, but currently disabled in hardware"); | |
1394 | break; | |
1395 | case FBC_UNSUPPORTED: | |
1396 | seq_puts(m, "unsupported by this chipset"); | |
1397 | break; | |
bed4a673 | 1398 | case FBC_NO_OUTPUT: |
267f0c90 | 1399 | seq_puts(m, "no outputs"); |
bed4a673 | 1400 | break; |
b5e50c3f | 1401 | case FBC_STOLEN_TOO_SMALL: |
267f0c90 | 1402 | seq_puts(m, "not enough stolen memory"); |
b5e50c3f JB |
1403 | break; |
1404 | case FBC_UNSUPPORTED_MODE: | |
267f0c90 | 1405 | seq_puts(m, "mode not supported"); |
b5e50c3f JB |
1406 | break; |
1407 | case FBC_MODE_TOO_LARGE: | |
267f0c90 | 1408 | seq_puts(m, "mode too large"); |
b5e50c3f JB |
1409 | break; |
1410 | case FBC_BAD_PLANE: | |
267f0c90 | 1411 | seq_puts(m, "FBC unsupported on plane"); |
b5e50c3f JB |
1412 | break; |
1413 | case FBC_NOT_TILED: | |
267f0c90 | 1414 | seq_puts(m, "scanout buffer not tiled"); |
b5e50c3f | 1415 | break; |
9c928d16 | 1416 | case FBC_MULTIPLE_PIPES: |
267f0c90 | 1417 | seq_puts(m, "multiple pipes are enabled"); |
9c928d16 | 1418 | break; |
c1a9f047 | 1419 | case FBC_MODULE_PARAM: |
267f0c90 | 1420 | seq_puts(m, "disabled per module param (default off)"); |
c1a9f047 | 1421 | break; |
8a5729a3 | 1422 | case FBC_CHIP_DEFAULT: |
267f0c90 | 1423 | seq_puts(m, "disabled per chip default"); |
8a5729a3 | 1424 | break; |
b5e50c3f | 1425 | default: |
267f0c90 | 1426 | seq_puts(m, "unknown reason"); |
b5e50c3f | 1427 | } |
267f0c90 | 1428 | seq_putc(m, '\n'); |
b5e50c3f | 1429 | } |
36623ef8 PZ |
1430 | |
1431 | intel_runtime_pm_put(dev_priv); | |
1432 | ||
b5e50c3f JB |
1433 | return 0; |
1434 | } | |
1435 | ||
da46f936 RV |
1436 | static int i915_fbc_fc_get(void *data, u64 *val) |
1437 | { | |
1438 | struct drm_device *dev = data; | |
1439 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1440 | ||
1441 | if (INTEL_INFO(dev)->gen < 7 || !HAS_FBC(dev)) | |
1442 | return -ENODEV; | |
1443 | ||
1444 | drm_modeset_lock_all(dev); | |
1445 | *val = dev_priv->fbc.false_color; | |
1446 | drm_modeset_unlock_all(dev); | |
1447 | ||
1448 | return 0; | |
1449 | } | |
1450 | ||
1451 | static int i915_fbc_fc_set(void *data, u64 val) | |
1452 | { | |
1453 | struct drm_device *dev = data; | |
1454 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1455 | u32 reg; | |
1456 | ||
1457 | if (INTEL_INFO(dev)->gen < 7 || !HAS_FBC(dev)) | |
1458 | return -ENODEV; | |
1459 | ||
1460 | drm_modeset_lock_all(dev); | |
1461 | ||
1462 | reg = I915_READ(ILK_DPFC_CONTROL); | |
1463 | dev_priv->fbc.false_color = val; | |
1464 | ||
1465 | I915_WRITE(ILK_DPFC_CONTROL, val ? | |
1466 | (reg | FBC_CTL_FALSE_COLOR) : | |
1467 | (reg & ~FBC_CTL_FALSE_COLOR)); | |
1468 | ||
1469 | drm_modeset_unlock_all(dev); | |
1470 | return 0; | |
1471 | } | |
1472 | ||
1473 | DEFINE_SIMPLE_ATTRIBUTE(i915_fbc_fc_fops, | |
1474 | i915_fbc_fc_get, i915_fbc_fc_set, | |
1475 | "%llu\n"); | |
1476 | ||
92d44621 PZ |
1477 | static int i915_ips_status(struct seq_file *m, void *unused) |
1478 | { | |
9f25d007 | 1479 | struct drm_info_node *node = m->private; |
92d44621 PZ |
1480 | struct drm_device *dev = node->minor->dev; |
1481 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1482 | ||
f5adf94e | 1483 | if (!HAS_IPS(dev)) { |
92d44621 PZ |
1484 | seq_puts(m, "not supported\n"); |
1485 | return 0; | |
1486 | } | |
1487 | ||
36623ef8 PZ |
1488 | intel_runtime_pm_get(dev_priv); |
1489 | ||
0eaa53f0 RV |
1490 | seq_printf(m, "Enabled by kernel parameter: %s\n", |
1491 | yesno(i915.enable_ips)); | |
1492 | ||
1493 | if (INTEL_INFO(dev)->gen >= 8) { | |
1494 | seq_puts(m, "Currently: unknown\n"); | |
1495 | } else { | |
1496 | if (I915_READ(IPS_CTL) & IPS_ENABLE) | |
1497 | seq_puts(m, "Currently: enabled\n"); | |
1498 | else | |
1499 | seq_puts(m, "Currently: disabled\n"); | |
1500 | } | |
92d44621 | 1501 | |
36623ef8 PZ |
1502 | intel_runtime_pm_put(dev_priv); |
1503 | ||
92d44621 PZ |
1504 | return 0; |
1505 | } | |
1506 | ||
4a9bef37 JB |
1507 | static int i915_sr_status(struct seq_file *m, void *unused) |
1508 | { | |
9f25d007 | 1509 | struct drm_info_node *node = m->private; |
4a9bef37 | 1510 | struct drm_device *dev = node->minor->dev; |
e277a1f8 | 1511 | struct drm_i915_private *dev_priv = dev->dev_private; |
4a9bef37 JB |
1512 | bool sr_enabled = false; |
1513 | ||
36623ef8 PZ |
1514 | intel_runtime_pm_get(dev_priv); |
1515 | ||
1398261a | 1516 | if (HAS_PCH_SPLIT(dev)) |
5ba2aaaa | 1517 | sr_enabled = I915_READ(WM1_LP_ILK) & WM1_LP_SR_EN; |
a6c45cf0 | 1518 | else if (IS_CRESTLINE(dev) || IS_I945G(dev) || IS_I945GM(dev)) |
4a9bef37 JB |
1519 | sr_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN; |
1520 | else if (IS_I915GM(dev)) | |
1521 | sr_enabled = I915_READ(INSTPM) & INSTPM_SELF_EN; | |
1522 | else if (IS_PINEVIEW(dev)) | |
1523 | sr_enabled = I915_READ(DSPFW3) & PINEVIEW_SELF_REFRESH_EN; | |
1524 | ||
36623ef8 PZ |
1525 | intel_runtime_pm_put(dev_priv); |
1526 | ||
5ba2aaaa CW |
1527 | seq_printf(m, "self-refresh: %s\n", |
1528 | sr_enabled ? "enabled" : "disabled"); | |
4a9bef37 JB |
1529 | |
1530 | return 0; | |
1531 | } | |
1532 | ||
7648fa99 JB |
1533 | static int i915_emon_status(struct seq_file *m, void *unused) |
1534 | { | |
9f25d007 | 1535 | struct drm_info_node *node = m->private; |
7648fa99 | 1536 | struct drm_device *dev = node->minor->dev; |
e277a1f8 | 1537 | struct drm_i915_private *dev_priv = dev->dev_private; |
7648fa99 | 1538 | unsigned long temp, chipset, gfx; |
de227ef0 CW |
1539 | int ret; |
1540 | ||
582be6b4 CW |
1541 | if (!IS_GEN5(dev)) |
1542 | return -ENODEV; | |
1543 | ||
de227ef0 CW |
1544 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
1545 | if (ret) | |
1546 | return ret; | |
7648fa99 JB |
1547 | |
1548 | temp = i915_mch_val(dev_priv); | |
1549 | chipset = i915_chipset_val(dev_priv); | |
1550 | gfx = i915_gfx_val(dev_priv); | |
de227ef0 | 1551 | mutex_unlock(&dev->struct_mutex); |
7648fa99 JB |
1552 | |
1553 | seq_printf(m, "GMCH temp: %ld\n", temp); | |
1554 | seq_printf(m, "Chipset power: %ld\n", chipset); | |
1555 | seq_printf(m, "GFX power: %ld\n", gfx); | |
1556 | seq_printf(m, "Total power: %ld\n", chipset + gfx); | |
1557 | ||
1558 | return 0; | |
1559 | } | |
1560 | ||
23b2f8bb JB |
1561 | static int i915_ring_freq_table(struct seq_file *m, void *unused) |
1562 | { | |
9f25d007 | 1563 | struct drm_info_node *node = m->private; |
23b2f8bb | 1564 | struct drm_device *dev = node->minor->dev; |
e277a1f8 | 1565 | struct drm_i915_private *dev_priv = dev->dev_private; |
5bfa0199 | 1566 | int ret = 0; |
23b2f8bb JB |
1567 | int gpu_freq, ia_freq; |
1568 | ||
1c70c0ce | 1569 | if (!(IS_GEN6(dev) || IS_GEN7(dev))) { |
267f0c90 | 1570 | seq_puts(m, "unsupported on this chipset\n"); |
23b2f8bb JB |
1571 | return 0; |
1572 | } | |
1573 | ||
5bfa0199 PZ |
1574 | intel_runtime_pm_get(dev_priv); |
1575 | ||
5c9669ce TR |
1576 | flush_delayed_work(&dev_priv->rps.delayed_resume_work); |
1577 | ||
4fc688ce | 1578 | ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock); |
23b2f8bb | 1579 | if (ret) |
5bfa0199 | 1580 | goto out; |
23b2f8bb | 1581 | |
267f0c90 | 1582 | seq_puts(m, "GPU freq (MHz)\tEffective CPU freq (MHz)\tEffective Ring freq (MHz)\n"); |
23b2f8bb | 1583 | |
b39fb297 BW |
1584 | for (gpu_freq = dev_priv->rps.min_freq_softlimit; |
1585 | gpu_freq <= dev_priv->rps.max_freq_softlimit; | |
23b2f8bb | 1586 | gpu_freq++) { |
42c0526c BW |
1587 | ia_freq = gpu_freq; |
1588 | sandybridge_pcode_read(dev_priv, | |
1589 | GEN6_PCODE_READ_MIN_FREQ_TABLE, | |
1590 | &ia_freq); | |
3ebecd07 CW |
1591 | seq_printf(m, "%d\t\t%d\t\t\t\t%d\n", |
1592 | gpu_freq * GT_FREQUENCY_MULTIPLIER, | |
1593 | ((ia_freq >> 0) & 0xff) * 100, | |
1594 | ((ia_freq >> 8) & 0xff) * 100); | |
23b2f8bb JB |
1595 | } |
1596 | ||
4fc688ce | 1597 | mutex_unlock(&dev_priv->rps.hw_lock); |
23b2f8bb | 1598 | |
5bfa0199 PZ |
1599 | out: |
1600 | intel_runtime_pm_put(dev_priv); | |
1601 | return ret; | |
23b2f8bb JB |
1602 | } |
1603 | ||
44834a67 CW |
1604 | static int i915_opregion(struct seq_file *m, void *unused) |
1605 | { | |
9f25d007 | 1606 | struct drm_info_node *node = m->private; |
44834a67 | 1607 | struct drm_device *dev = node->minor->dev; |
e277a1f8 | 1608 | struct drm_i915_private *dev_priv = dev->dev_private; |
44834a67 | 1609 | struct intel_opregion *opregion = &dev_priv->opregion; |
0d38f009 | 1610 | void *data = kmalloc(OPREGION_SIZE, GFP_KERNEL); |
44834a67 CW |
1611 | int ret; |
1612 | ||
0d38f009 DV |
1613 | if (data == NULL) |
1614 | return -ENOMEM; | |
1615 | ||
44834a67 CW |
1616 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
1617 | if (ret) | |
0d38f009 | 1618 | goto out; |
44834a67 | 1619 | |
0d38f009 DV |
1620 | if (opregion->header) { |
1621 | memcpy_fromio(data, opregion->header, OPREGION_SIZE); | |
1622 | seq_write(m, data, OPREGION_SIZE); | |
1623 | } | |
44834a67 CW |
1624 | |
1625 | mutex_unlock(&dev->struct_mutex); | |
1626 | ||
0d38f009 DV |
1627 | out: |
1628 | kfree(data); | |
44834a67 CW |
1629 | return 0; |
1630 | } | |
1631 | ||
37811fcc CW |
1632 | static int i915_gem_framebuffer_info(struct seq_file *m, void *data) |
1633 | { | |
9f25d007 | 1634 | struct drm_info_node *node = m->private; |
37811fcc | 1635 | struct drm_device *dev = node->minor->dev; |
4520f53a | 1636 | struct intel_fbdev *ifbdev = NULL; |
37811fcc | 1637 | struct intel_framebuffer *fb; |
37811fcc | 1638 | |
4520f53a DV |
1639 | #ifdef CONFIG_DRM_I915_FBDEV |
1640 | struct drm_i915_private *dev_priv = dev->dev_private; | |
37811fcc CW |
1641 | |
1642 | ifbdev = dev_priv->fbdev; | |
1643 | fb = to_intel_framebuffer(ifbdev->helper.fb); | |
1644 | ||
623f9783 | 1645 | seq_printf(m, "fbcon size: %d x %d, depth %d, %d bpp, refcount %d, obj ", |
37811fcc CW |
1646 | fb->base.width, |
1647 | fb->base.height, | |
1648 | fb->base.depth, | |
623f9783 DV |
1649 | fb->base.bits_per_pixel, |
1650 | atomic_read(&fb->base.refcount.refcount)); | |
05394f39 | 1651 | describe_obj(m, fb->obj); |
267f0c90 | 1652 | seq_putc(m, '\n'); |
4520f53a | 1653 | #endif |
37811fcc | 1654 | |
4b096ac1 | 1655 | mutex_lock(&dev->mode_config.fb_lock); |
37811fcc | 1656 | list_for_each_entry(fb, &dev->mode_config.fb_list, base.head) { |
131a56dc | 1657 | if (ifbdev && &fb->base == ifbdev->helper.fb) |
37811fcc CW |
1658 | continue; |
1659 | ||
623f9783 | 1660 | seq_printf(m, "user size: %d x %d, depth %d, %d bpp, refcount %d, obj ", |
37811fcc CW |
1661 | fb->base.width, |
1662 | fb->base.height, | |
1663 | fb->base.depth, | |
623f9783 DV |
1664 | fb->base.bits_per_pixel, |
1665 | atomic_read(&fb->base.refcount.refcount)); | |
05394f39 | 1666 | describe_obj(m, fb->obj); |
267f0c90 | 1667 | seq_putc(m, '\n'); |
37811fcc | 1668 | } |
4b096ac1 | 1669 | mutex_unlock(&dev->mode_config.fb_lock); |
37811fcc CW |
1670 | |
1671 | return 0; | |
1672 | } | |
1673 | ||
e76d3630 BW |
1674 | static int i915_context_status(struct seq_file *m, void *unused) |
1675 | { | |
9f25d007 | 1676 | struct drm_info_node *node = m->private; |
e76d3630 | 1677 | struct drm_device *dev = node->minor->dev; |
e277a1f8 | 1678 | struct drm_i915_private *dev_priv = dev->dev_private; |
a4872ba6 | 1679 | struct intel_engine_cs *ring; |
273497e5 | 1680 | struct intel_context *ctx; |
a168c293 | 1681 | int ret, i; |
e76d3630 | 1682 | |
f3d28878 | 1683 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
e76d3630 BW |
1684 | if (ret) |
1685 | return ret; | |
1686 | ||
3e373948 | 1687 | if (dev_priv->ips.pwrctx) { |
267f0c90 | 1688 | seq_puts(m, "power context "); |
3e373948 | 1689 | describe_obj(m, dev_priv->ips.pwrctx); |
267f0c90 | 1690 | seq_putc(m, '\n'); |
dc501fbc | 1691 | } |
e76d3630 | 1692 | |
3e373948 | 1693 | if (dev_priv->ips.renderctx) { |
267f0c90 | 1694 | seq_puts(m, "render context "); |
3e373948 | 1695 | describe_obj(m, dev_priv->ips.renderctx); |
267f0c90 | 1696 | seq_putc(m, '\n'); |
dc501fbc | 1697 | } |
e76d3630 | 1698 | |
a33afea5 | 1699 | list_for_each_entry(ctx, &dev_priv->context_list, link) { |
ea0c76f8 | 1700 | if (ctx->legacy_hw_ctx.rcs_state == NULL) |
b77f6997 CW |
1701 | continue; |
1702 | ||
a33afea5 | 1703 | seq_puts(m, "HW context "); |
3ccfd19d | 1704 | describe_ctx(m, ctx); |
a33afea5 BW |
1705 | for_each_ring(ring, dev_priv, i) |
1706 | if (ring->default_context == ctx) | |
1707 | seq_printf(m, "(default context %s) ", ring->name); | |
1708 | ||
ea0c76f8 | 1709 | describe_obj(m, ctx->legacy_hw_ctx.rcs_state); |
a33afea5 | 1710 | seq_putc(m, '\n'); |
a168c293 BW |
1711 | } |
1712 | ||
f3d28878 | 1713 | mutex_unlock(&dev->struct_mutex); |
e76d3630 BW |
1714 | |
1715 | return 0; | |
1716 | } | |
1717 | ||
6d794d42 BW |
1718 | static int i915_gen6_forcewake_count_info(struct seq_file *m, void *data) |
1719 | { | |
9f25d007 | 1720 | struct drm_info_node *node = m->private; |
6d794d42 BW |
1721 | struct drm_device *dev = node->minor->dev; |
1722 | struct drm_i915_private *dev_priv = dev->dev_private; | |
43709ba0 | 1723 | unsigned forcewake_count = 0, fw_rendercount = 0, fw_mediacount = 0; |
6d794d42 | 1724 | |
907b28c5 | 1725 | spin_lock_irq(&dev_priv->uncore.lock); |
43709ba0 D |
1726 | if (IS_VALLEYVIEW(dev)) { |
1727 | fw_rendercount = dev_priv->uncore.fw_rendercount; | |
1728 | fw_mediacount = dev_priv->uncore.fw_mediacount; | |
1729 | } else | |
1730 | forcewake_count = dev_priv->uncore.forcewake_count; | |
907b28c5 | 1731 | spin_unlock_irq(&dev_priv->uncore.lock); |
6d794d42 | 1732 | |
43709ba0 D |
1733 | if (IS_VALLEYVIEW(dev)) { |
1734 | seq_printf(m, "fw_rendercount = %u\n", fw_rendercount); | |
1735 | seq_printf(m, "fw_mediacount = %u\n", fw_mediacount); | |
1736 | } else | |
1737 | seq_printf(m, "forcewake count = %u\n", forcewake_count); | |
6d794d42 BW |
1738 | |
1739 | return 0; | |
1740 | } | |
1741 | ||
ea16a3cd DV |
1742 | static const char *swizzle_string(unsigned swizzle) |
1743 | { | |
aee56cff | 1744 | switch (swizzle) { |
ea16a3cd DV |
1745 | case I915_BIT_6_SWIZZLE_NONE: |
1746 | return "none"; | |
1747 | case I915_BIT_6_SWIZZLE_9: | |
1748 | return "bit9"; | |
1749 | case I915_BIT_6_SWIZZLE_9_10: | |
1750 | return "bit9/bit10"; | |
1751 | case I915_BIT_6_SWIZZLE_9_11: | |
1752 | return "bit9/bit11"; | |
1753 | case I915_BIT_6_SWIZZLE_9_10_11: | |
1754 | return "bit9/bit10/bit11"; | |
1755 | case I915_BIT_6_SWIZZLE_9_17: | |
1756 | return "bit9/bit17"; | |
1757 | case I915_BIT_6_SWIZZLE_9_10_17: | |
1758 | return "bit9/bit10/bit17"; | |
1759 | case I915_BIT_6_SWIZZLE_UNKNOWN: | |
8a168ca7 | 1760 | return "unknown"; |
ea16a3cd DV |
1761 | } |
1762 | ||
1763 | return "bug"; | |
1764 | } | |
1765 | ||
1766 | static int i915_swizzle_info(struct seq_file *m, void *data) | |
1767 | { | |
9f25d007 | 1768 | struct drm_info_node *node = m->private; |
ea16a3cd DV |
1769 | struct drm_device *dev = node->minor->dev; |
1770 | struct drm_i915_private *dev_priv = dev->dev_private; | |
22bcfc6a DV |
1771 | int ret; |
1772 | ||
1773 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
1774 | if (ret) | |
1775 | return ret; | |
c8c8fb33 | 1776 | intel_runtime_pm_get(dev_priv); |
ea16a3cd | 1777 | |
ea16a3cd DV |
1778 | seq_printf(m, "bit6 swizzle for X-tiling = %s\n", |
1779 | swizzle_string(dev_priv->mm.bit_6_swizzle_x)); | |
1780 | seq_printf(m, "bit6 swizzle for Y-tiling = %s\n", | |
1781 | swizzle_string(dev_priv->mm.bit_6_swizzle_y)); | |
1782 | ||
1783 | if (IS_GEN3(dev) || IS_GEN4(dev)) { | |
1784 | seq_printf(m, "DDC = 0x%08x\n", | |
1785 | I915_READ(DCC)); | |
1786 | seq_printf(m, "C0DRB3 = 0x%04x\n", | |
1787 | I915_READ16(C0DRB3)); | |
1788 | seq_printf(m, "C1DRB3 = 0x%04x\n", | |
1789 | I915_READ16(C1DRB3)); | |
9d3203e1 | 1790 | } else if (INTEL_INFO(dev)->gen >= 6) { |
3fa7d235 DV |
1791 | seq_printf(m, "MAD_DIMM_C0 = 0x%08x\n", |
1792 | I915_READ(MAD_DIMM_C0)); | |
1793 | seq_printf(m, "MAD_DIMM_C1 = 0x%08x\n", | |
1794 | I915_READ(MAD_DIMM_C1)); | |
1795 | seq_printf(m, "MAD_DIMM_C2 = 0x%08x\n", | |
1796 | I915_READ(MAD_DIMM_C2)); | |
1797 | seq_printf(m, "TILECTL = 0x%08x\n", | |
1798 | I915_READ(TILECTL)); | |
9d3203e1 BW |
1799 | if (IS_GEN8(dev)) |
1800 | seq_printf(m, "GAMTARBMODE = 0x%08x\n", | |
1801 | I915_READ(GAMTARBMODE)); | |
1802 | else | |
1803 | seq_printf(m, "ARB_MODE = 0x%08x\n", | |
1804 | I915_READ(ARB_MODE)); | |
3fa7d235 DV |
1805 | seq_printf(m, "DISP_ARB_CTL = 0x%08x\n", |
1806 | I915_READ(DISP_ARB_CTL)); | |
ea16a3cd | 1807 | } |
c8c8fb33 | 1808 | intel_runtime_pm_put(dev_priv); |
ea16a3cd DV |
1809 | mutex_unlock(&dev->struct_mutex); |
1810 | ||
1811 | return 0; | |
1812 | } | |
1813 | ||
1c60fef5 BW |
1814 | static int per_file_ctx(int id, void *ptr, void *data) |
1815 | { | |
273497e5 | 1816 | struct intel_context *ctx = ptr; |
1c60fef5 BW |
1817 | struct seq_file *m = data; |
1818 | struct i915_hw_ppgtt *ppgtt = ctx_to_ppgtt(ctx); | |
1819 | ||
f83d6518 OM |
1820 | if (i915_gem_context_is_default(ctx)) |
1821 | seq_puts(m, " default context:\n"); | |
1822 | else | |
821d66dd | 1823 | seq_printf(m, " context %d:\n", ctx->user_handle); |
1c60fef5 BW |
1824 | ppgtt->debug_dump(ppgtt, m); |
1825 | ||
1826 | return 0; | |
1827 | } | |
1828 | ||
77df6772 | 1829 | static void gen8_ppgtt_info(struct seq_file *m, struct drm_device *dev) |
3cf17fc5 | 1830 | { |
3cf17fc5 | 1831 | struct drm_i915_private *dev_priv = dev->dev_private; |
a4872ba6 | 1832 | struct intel_engine_cs *ring; |
77df6772 BW |
1833 | struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt; |
1834 | int unused, i; | |
3cf17fc5 | 1835 | |
77df6772 BW |
1836 | if (!ppgtt) |
1837 | return; | |
1838 | ||
1839 | seq_printf(m, "Page directories: %d\n", ppgtt->num_pd_pages); | |
5abbcca3 | 1840 | seq_printf(m, "Page tables: %d\n", ppgtt->num_pd_entries); |
77df6772 BW |
1841 | for_each_ring(ring, dev_priv, unused) { |
1842 | seq_printf(m, "%s\n", ring->name); | |
1843 | for (i = 0; i < 4; i++) { | |
1844 | u32 offset = 0x270 + i * 8; | |
1845 | u64 pdp = I915_READ(ring->mmio_base + offset + 4); | |
1846 | pdp <<= 32; | |
1847 | pdp |= I915_READ(ring->mmio_base + offset); | |
a2a5b15c | 1848 | seq_printf(m, "\tPDP%d 0x%016llx\n", i, pdp); |
77df6772 BW |
1849 | } |
1850 | } | |
1851 | } | |
1852 | ||
1853 | static void gen6_ppgtt_info(struct seq_file *m, struct drm_device *dev) | |
1854 | { | |
1855 | struct drm_i915_private *dev_priv = dev->dev_private; | |
a4872ba6 | 1856 | struct intel_engine_cs *ring; |
1c60fef5 | 1857 | struct drm_file *file; |
77df6772 | 1858 | int i; |
3cf17fc5 | 1859 | |
3cf17fc5 DV |
1860 | if (INTEL_INFO(dev)->gen == 6) |
1861 | seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(GFX_MODE)); | |
1862 | ||
a2c7f6fd | 1863 | for_each_ring(ring, dev_priv, i) { |
3cf17fc5 DV |
1864 | seq_printf(m, "%s\n", ring->name); |
1865 | if (INTEL_INFO(dev)->gen == 7) | |
1866 | seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(RING_MODE_GEN7(ring))); | |
1867 | seq_printf(m, "PP_DIR_BASE: 0x%08x\n", I915_READ(RING_PP_DIR_BASE(ring))); | |
1868 | seq_printf(m, "PP_DIR_BASE_READ: 0x%08x\n", I915_READ(RING_PP_DIR_BASE_READ(ring))); | |
1869 | seq_printf(m, "PP_DIR_DCLV: 0x%08x\n", I915_READ(RING_PP_DIR_DCLV(ring))); | |
1870 | } | |
1871 | if (dev_priv->mm.aliasing_ppgtt) { | |
1872 | struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt; | |
1873 | ||
267f0c90 | 1874 | seq_puts(m, "aliasing PPGTT:\n"); |
3cf17fc5 | 1875 | seq_printf(m, "pd gtt offset: 0x%08x\n", ppgtt->pd_offset); |
1c60fef5 | 1876 | |
87d60b63 | 1877 | ppgtt->debug_dump(ppgtt, m); |
1c60fef5 BW |
1878 | } else |
1879 | return; | |
1880 | ||
1881 | list_for_each_entry_reverse(file, &dev->filelist, lhead) { | |
1882 | struct drm_i915_file_private *file_priv = file->driver_priv; | |
1c60fef5 | 1883 | |
1c60fef5 BW |
1884 | seq_printf(m, "proc: %s\n", |
1885 | get_pid_task(file->pid, PIDTYPE_PID)->comm); | |
1c60fef5 | 1886 | idr_for_each(&file_priv->context_idr, per_file_ctx, m); |
3cf17fc5 DV |
1887 | } |
1888 | seq_printf(m, "ECOCHK: 0x%08x\n", I915_READ(GAM_ECOCHK)); | |
77df6772 BW |
1889 | } |
1890 | ||
1891 | static int i915_ppgtt_info(struct seq_file *m, void *data) | |
1892 | { | |
9f25d007 | 1893 | struct drm_info_node *node = m->private; |
77df6772 | 1894 | struct drm_device *dev = node->minor->dev; |
c8c8fb33 | 1895 | struct drm_i915_private *dev_priv = dev->dev_private; |
77df6772 BW |
1896 | |
1897 | int ret = mutex_lock_interruptible(&dev->struct_mutex); | |
1898 | if (ret) | |
1899 | return ret; | |
c8c8fb33 | 1900 | intel_runtime_pm_get(dev_priv); |
77df6772 BW |
1901 | |
1902 | if (INTEL_INFO(dev)->gen >= 8) | |
1903 | gen8_ppgtt_info(m, dev); | |
1904 | else if (INTEL_INFO(dev)->gen >= 6) | |
1905 | gen6_ppgtt_info(m, dev); | |
1906 | ||
c8c8fb33 | 1907 | intel_runtime_pm_put(dev_priv); |
3cf17fc5 DV |
1908 | mutex_unlock(&dev->struct_mutex); |
1909 | ||
1910 | return 0; | |
1911 | } | |
1912 | ||
63573eb7 BW |
1913 | static int i915_llc(struct seq_file *m, void *data) |
1914 | { | |
9f25d007 | 1915 | struct drm_info_node *node = m->private; |
63573eb7 BW |
1916 | struct drm_device *dev = node->minor->dev; |
1917 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1918 | ||
1919 | /* Size calculation for LLC is a bit of a pain. Ignore for now. */ | |
1920 | seq_printf(m, "LLC: %s\n", yesno(HAS_LLC(dev))); | |
1921 | seq_printf(m, "eLLC: %zuMB\n", dev_priv->ellc_size); | |
1922 | ||
1923 | return 0; | |
1924 | } | |
1925 | ||
e91fd8c6 RV |
1926 | static int i915_edp_psr_status(struct seq_file *m, void *data) |
1927 | { | |
1928 | struct drm_info_node *node = m->private; | |
1929 | struct drm_device *dev = node->minor->dev; | |
1930 | struct drm_i915_private *dev_priv = dev->dev_private; | |
a031d709 RV |
1931 | u32 psrperf = 0; |
1932 | bool enabled = false; | |
e91fd8c6 | 1933 | |
c8c8fb33 PZ |
1934 | intel_runtime_pm_get(dev_priv); |
1935 | ||
fa128fa6 | 1936 | mutex_lock(&dev_priv->psr.lock); |
a031d709 RV |
1937 | seq_printf(m, "Sink_Support: %s\n", yesno(dev_priv->psr.sink_support)); |
1938 | seq_printf(m, "Source_OK: %s\n", yesno(dev_priv->psr.source_ok)); | |
2807cf69 | 1939 | seq_printf(m, "Enabled: %s\n", yesno((bool)dev_priv->psr.enabled)); |
5755c78f | 1940 | seq_printf(m, "Active: %s\n", yesno(dev_priv->psr.active)); |
fa128fa6 DV |
1941 | seq_printf(m, "Busy frontbuffer bits: 0x%03x\n", |
1942 | dev_priv->psr.busy_frontbuffer_bits); | |
1943 | seq_printf(m, "Re-enable work scheduled: %s\n", | |
1944 | yesno(work_busy(&dev_priv->psr.work.work))); | |
e91fd8c6 | 1945 | |
a031d709 RV |
1946 | enabled = HAS_PSR(dev) && |
1947 | I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE; | |
5755c78f | 1948 | seq_printf(m, "HW Enabled & Active bit: %s\n", yesno(enabled)); |
e91fd8c6 | 1949 | |
a031d709 RV |
1950 | if (HAS_PSR(dev)) |
1951 | psrperf = I915_READ(EDP_PSR_PERF_CNT(dev)) & | |
1952 | EDP_PSR_PERF_CNT_MASK; | |
1953 | seq_printf(m, "Performance_Counter: %u\n", psrperf); | |
fa128fa6 | 1954 | mutex_unlock(&dev_priv->psr.lock); |
e91fd8c6 | 1955 | |
c8c8fb33 | 1956 | intel_runtime_pm_put(dev_priv); |
e91fd8c6 RV |
1957 | return 0; |
1958 | } | |
1959 | ||
d2e216d0 RV |
1960 | static int i915_sink_crc(struct seq_file *m, void *data) |
1961 | { | |
1962 | struct drm_info_node *node = m->private; | |
1963 | struct drm_device *dev = node->minor->dev; | |
1964 | struct intel_encoder *encoder; | |
1965 | struct intel_connector *connector; | |
1966 | struct intel_dp *intel_dp = NULL; | |
1967 | int ret; | |
1968 | u8 crc[6]; | |
1969 | ||
1970 | drm_modeset_lock_all(dev); | |
1971 | list_for_each_entry(connector, &dev->mode_config.connector_list, | |
1972 | base.head) { | |
1973 | ||
1974 | if (connector->base.dpms != DRM_MODE_DPMS_ON) | |
1975 | continue; | |
1976 | ||
b6ae3c7c PZ |
1977 | if (!connector->base.encoder) |
1978 | continue; | |
1979 | ||
d2e216d0 RV |
1980 | encoder = to_intel_encoder(connector->base.encoder); |
1981 | if (encoder->type != INTEL_OUTPUT_EDP) | |
1982 | continue; | |
1983 | ||
1984 | intel_dp = enc_to_intel_dp(&encoder->base); | |
1985 | ||
1986 | ret = intel_dp_sink_crc(intel_dp, crc); | |
1987 | if (ret) | |
1988 | goto out; | |
1989 | ||
1990 | seq_printf(m, "%02x%02x%02x%02x%02x%02x\n", | |
1991 | crc[0], crc[1], crc[2], | |
1992 | crc[3], crc[4], crc[5]); | |
1993 | goto out; | |
1994 | } | |
1995 | ret = -ENODEV; | |
1996 | out: | |
1997 | drm_modeset_unlock_all(dev); | |
1998 | return ret; | |
1999 | } | |
2000 | ||
ec013e7f JB |
2001 | static int i915_energy_uJ(struct seq_file *m, void *data) |
2002 | { | |
2003 | struct drm_info_node *node = m->private; | |
2004 | struct drm_device *dev = node->minor->dev; | |
2005 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2006 | u64 power; | |
2007 | u32 units; | |
2008 | ||
2009 | if (INTEL_INFO(dev)->gen < 6) | |
2010 | return -ENODEV; | |
2011 | ||
36623ef8 PZ |
2012 | intel_runtime_pm_get(dev_priv); |
2013 | ||
ec013e7f JB |
2014 | rdmsrl(MSR_RAPL_POWER_UNIT, power); |
2015 | power = (power & 0x1f00) >> 8; | |
2016 | units = 1000000 / (1 << power); /* convert to uJ */ | |
2017 | power = I915_READ(MCH_SECP_NRG_STTS); | |
2018 | power *= units; | |
2019 | ||
36623ef8 PZ |
2020 | intel_runtime_pm_put(dev_priv); |
2021 | ||
ec013e7f | 2022 | seq_printf(m, "%llu", (long long unsigned)power); |
371db66a PZ |
2023 | |
2024 | return 0; | |
2025 | } | |
2026 | ||
2027 | static int i915_pc8_status(struct seq_file *m, void *unused) | |
2028 | { | |
9f25d007 | 2029 | struct drm_info_node *node = m->private; |
371db66a PZ |
2030 | struct drm_device *dev = node->minor->dev; |
2031 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2032 | ||
85b8d5c2 | 2033 | if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) { |
371db66a PZ |
2034 | seq_puts(m, "not supported\n"); |
2035 | return 0; | |
2036 | } | |
2037 | ||
86c4ec0d | 2038 | seq_printf(m, "GPU idle: %s\n", yesno(!dev_priv->mm.busy)); |
371db66a | 2039 | seq_printf(m, "IRQs disabled: %s\n", |
9df7575f | 2040 | yesno(!intel_irqs_enabled(dev_priv))); |
371db66a | 2041 | |
ec013e7f JB |
2042 | return 0; |
2043 | } | |
2044 | ||
1da51581 ID |
2045 | static const char *power_domain_str(enum intel_display_power_domain domain) |
2046 | { | |
2047 | switch (domain) { | |
2048 | case POWER_DOMAIN_PIPE_A: | |
2049 | return "PIPE_A"; | |
2050 | case POWER_DOMAIN_PIPE_B: | |
2051 | return "PIPE_B"; | |
2052 | case POWER_DOMAIN_PIPE_C: | |
2053 | return "PIPE_C"; | |
2054 | case POWER_DOMAIN_PIPE_A_PANEL_FITTER: | |
2055 | return "PIPE_A_PANEL_FITTER"; | |
2056 | case POWER_DOMAIN_PIPE_B_PANEL_FITTER: | |
2057 | return "PIPE_B_PANEL_FITTER"; | |
2058 | case POWER_DOMAIN_PIPE_C_PANEL_FITTER: | |
2059 | return "PIPE_C_PANEL_FITTER"; | |
2060 | case POWER_DOMAIN_TRANSCODER_A: | |
2061 | return "TRANSCODER_A"; | |
2062 | case POWER_DOMAIN_TRANSCODER_B: | |
2063 | return "TRANSCODER_B"; | |
2064 | case POWER_DOMAIN_TRANSCODER_C: | |
2065 | return "TRANSCODER_C"; | |
2066 | case POWER_DOMAIN_TRANSCODER_EDP: | |
2067 | return "TRANSCODER_EDP"; | |
319be8ae ID |
2068 | case POWER_DOMAIN_PORT_DDI_A_2_LANES: |
2069 | return "PORT_DDI_A_2_LANES"; | |
2070 | case POWER_DOMAIN_PORT_DDI_A_4_LANES: | |
2071 | return "PORT_DDI_A_4_LANES"; | |
2072 | case POWER_DOMAIN_PORT_DDI_B_2_LANES: | |
2073 | return "PORT_DDI_B_2_LANES"; | |
2074 | case POWER_DOMAIN_PORT_DDI_B_4_LANES: | |
2075 | return "PORT_DDI_B_4_LANES"; | |
2076 | case POWER_DOMAIN_PORT_DDI_C_2_LANES: | |
2077 | return "PORT_DDI_C_2_LANES"; | |
2078 | case POWER_DOMAIN_PORT_DDI_C_4_LANES: | |
2079 | return "PORT_DDI_C_4_LANES"; | |
2080 | case POWER_DOMAIN_PORT_DDI_D_2_LANES: | |
2081 | return "PORT_DDI_D_2_LANES"; | |
2082 | case POWER_DOMAIN_PORT_DDI_D_4_LANES: | |
2083 | return "PORT_DDI_D_4_LANES"; | |
2084 | case POWER_DOMAIN_PORT_DSI: | |
2085 | return "PORT_DSI"; | |
2086 | case POWER_DOMAIN_PORT_CRT: | |
2087 | return "PORT_CRT"; | |
2088 | case POWER_DOMAIN_PORT_OTHER: | |
2089 | return "PORT_OTHER"; | |
1da51581 ID |
2090 | case POWER_DOMAIN_VGA: |
2091 | return "VGA"; | |
2092 | case POWER_DOMAIN_AUDIO: | |
2093 | return "AUDIO"; | |
bd2bb1b9 PZ |
2094 | case POWER_DOMAIN_PLLS: |
2095 | return "PLLS"; | |
1da51581 ID |
2096 | case POWER_DOMAIN_INIT: |
2097 | return "INIT"; | |
2098 | default: | |
2099 | WARN_ON(1); | |
2100 | return "?"; | |
2101 | } | |
2102 | } | |
2103 | ||
2104 | static int i915_power_domain_info(struct seq_file *m, void *unused) | |
2105 | { | |
9f25d007 | 2106 | struct drm_info_node *node = m->private; |
1da51581 ID |
2107 | struct drm_device *dev = node->minor->dev; |
2108 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2109 | struct i915_power_domains *power_domains = &dev_priv->power_domains; | |
2110 | int i; | |
2111 | ||
2112 | mutex_lock(&power_domains->lock); | |
2113 | ||
2114 | seq_printf(m, "%-25s %s\n", "Power well/domain", "Use count"); | |
2115 | for (i = 0; i < power_domains->power_well_count; i++) { | |
2116 | struct i915_power_well *power_well; | |
2117 | enum intel_display_power_domain power_domain; | |
2118 | ||
2119 | power_well = &power_domains->power_wells[i]; | |
2120 | seq_printf(m, "%-25s %d\n", power_well->name, | |
2121 | power_well->count); | |
2122 | ||
2123 | for (power_domain = 0; power_domain < POWER_DOMAIN_NUM; | |
2124 | power_domain++) { | |
2125 | if (!(BIT(power_domain) & power_well->domains)) | |
2126 | continue; | |
2127 | ||
2128 | seq_printf(m, " %-23s %d\n", | |
2129 | power_domain_str(power_domain), | |
2130 | power_domains->domain_use_count[power_domain]); | |
2131 | } | |
2132 | } | |
2133 | ||
2134 | mutex_unlock(&power_domains->lock); | |
2135 | ||
2136 | return 0; | |
2137 | } | |
2138 | ||
53f5e3ca JB |
2139 | static void intel_seq_print_mode(struct seq_file *m, int tabs, |
2140 | struct drm_display_mode *mode) | |
2141 | { | |
2142 | int i; | |
2143 | ||
2144 | for (i = 0; i < tabs; i++) | |
2145 | seq_putc(m, '\t'); | |
2146 | ||
2147 | seq_printf(m, "id %d:\"%s\" freq %d clock %d hdisp %d hss %d hse %d htot %d vdisp %d vss %d vse %d vtot %d type 0x%x flags 0x%x\n", | |
2148 | mode->base.id, mode->name, | |
2149 | mode->vrefresh, mode->clock, | |
2150 | mode->hdisplay, mode->hsync_start, | |
2151 | mode->hsync_end, mode->htotal, | |
2152 | mode->vdisplay, mode->vsync_start, | |
2153 | mode->vsync_end, mode->vtotal, | |
2154 | mode->type, mode->flags); | |
2155 | } | |
2156 | ||
2157 | static void intel_encoder_info(struct seq_file *m, | |
2158 | struct intel_crtc *intel_crtc, | |
2159 | struct intel_encoder *intel_encoder) | |
2160 | { | |
9f25d007 | 2161 | struct drm_info_node *node = m->private; |
53f5e3ca JB |
2162 | struct drm_device *dev = node->minor->dev; |
2163 | struct drm_crtc *crtc = &intel_crtc->base; | |
2164 | struct intel_connector *intel_connector; | |
2165 | struct drm_encoder *encoder; | |
2166 | ||
2167 | encoder = &intel_encoder->base; | |
2168 | seq_printf(m, "\tencoder %d: type: %s, connectors:\n", | |
8e329a03 | 2169 | encoder->base.id, encoder->name); |
53f5e3ca JB |
2170 | for_each_connector_on_encoder(dev, encoder, intel_connector) { |
2171 | struct drm_connector *connector = &intel_connector->base; | |
2172 | seq_printf(m, "\t\tconnector %d: type: %s, status: %s", | |
2173 | connector->base.id, | |
c23cc417 | 2174 | connector->name, |
53f5e3ca JB |
2175 | drm_get_connector_status_name(connector->status)); |
2176 | if (connector->status == connector_status_connected) { | |
2177 | struct drm_display_mode *mode = &crtc->mode; | |
2178 | seq_printf(m, ", mode:\n"); | |
2179 | intel_seq_print_mode(m, 2, mode); | |
2180 | } else { | |
2181 | seq_putc(m, '\n'); | |
2182 | } | |
2183 | } | |
2184 | } | |
2185 | ||
2186 | static void intel_crtc_info(struct seq_file *m, struct intel_crtc *intel_crtc) | |
2187 | { | |
9f25d007 | 2188 | struct drm_info_node *node = m->private; |
53f5e3ca JB |
2189 | struct drm_device *dev = node->minor->dev; |
2190 | struct drm_crtc *crtc = &intel_crtc->base; | |
2191 | struct intel_encoder *intel_encoder; | |
2192 | ||
5aa8a937 MR |
2193 | if (crtc->primary->fb) |
2194 | seq_printf(m, "\tfb: %d, pos: %dx%d, size: %dx%d\n", | |
2195 | crtc->primary->fb->base.id, crtc->x, crtc->y, | |
2196 | crtc->primary->fb->width, crtc->primary->fb->height); | |
2197 | else | |
2198 | seq_puts(m, "\tprimary plane disabled\n"); | |
53f5e3ca JB |
2199 | for_each_encoder_on_crtc(dev, crtc, intel_encoder) |
2200 | intel_encoder_info(m, intel_crtc, intel_encoder); | |
2201 | } | |
2202 | ||
2203 | static void intel_panel_info(struct seq_file *m, struct intel_panel *panel) | |
2204 | { | |
2205 | struct drm_display_mode *mode = panel->fixed_mode; | |
2206 | ||
2207 | seq_printf(m, "\tfixed mode:\n"); | |
2208 | intel_seq_print_mode(m, 2, mode); | |
2209 | } | |
2210 | ||
2211 | static void intel_dp_info(struct seq_file *m, | |
2212 | struct intel_connector *intel_connector) | |
2213 | { | |
2214 | struct intel_encoder *intel_encoder = intel_connector->encoder; | |
2215 | struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base); | |
2216 | ||
2217 | seq_printf(m, "\tDPCD rev: %x\n", intel_dp->dpcd[DP_DPCD_REV]); | |
2218 | seq_printf(m, "\taudio support: %s\n", intel_dp->has_audio ? "yes" : | |
2219 | "no"); | |
2220 | if (intel_encoder->type == INTEL_OUTPUT_EDP) | |
2221 | intel_panel_info(m, &intel_connector->panel); | |
2222 | } | |
2223 | ||
2224 | static void intel_hdmi_info(struct seq_file *m, | |
2225 | struct intel_connector *intel_connector) | |
2226 | { | |
2227 | struct intel_encoder *intel_encoder = intel_connector->encoder; | |
2228 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&intel_encoder->base); | |
2229 | ||
2230 | seq_printf(m, "\taudio support: %s\n", intel_hdmi->has_audio ? "yes" : | |
2231 | "no"); | |
2232 | } | |
2233 | ||
2234 | static void intel_lvds_info(struct seq_file *m, | |
2235 | struct intel_connector *intel_connector) | |
2236 | { | |
2237 | intel_panel_info(m, &intel_connector->panel); | |
2238 | } | |
2239 | ||
2240 | static void intel_connector_info(struct seq_file *m, | |
2241 | struct drm_connector *connector) | |
2242 | { | |
2243 | struct intel_connector *intel_connector = to_intel_connector(connector); | |
2244 | struct intel_encoder *intel_encoder = intel_connector->encoder; | |
f103fc7d | 2245 | struct drm_display_mode *mode; |
53f5e3ca JB |
2246 | |
2247 | seq_printf(m, "connector %d: type %s, status: %s\n", | |
c23cc417 | 2248 | connector->base.id, connector->name, |
53f5e3ca JB |
2249 | drm_get_connector_status_name(connector->status)); |
2250 | if (connector->status == connector_status_connected) { | |
2251 | seq_printf(m, "\tname: %s\n", connector->display_info.name); | |
2252 | seq_printf(m, "\tphysical dimensions: %dx%dmm\n", | |
2253 | connector->display_info.width_mm, | |
2254 | connector->display_info.height_mm); | |
2255 | seq_printf(m, "\tsubpixel order: %s\n", | |
2256 | drm_get_subpixel_order_name(connector->display_info.subpixel_order)); | |
2257 | seq_printf(m, "\tCEA rev: %d\n", | |
2258 | connector->display_info.cea_rev); | |
2259 | } | |
36cd7444 DA |
2260 | if (intel_encoder) { |
2261 | if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT || | |
2262 | intel_encoder->type == INTEL_OUTPUT_EDP) | |
2263 | intel_dp_info(m, intel_connector); | |
2264 | else if (intel_encoder->type == INTEL_OUTPUT_HDMI) | |
2265 | intel_hdmi_info(m, intel_connector); | |
2266 | else if (intel_encoder->type == INTEL_OUTPUT_LVDS) | |
2267 | intel_lvds_info(m, intel_connector); | |
2268 | } | |
53f5e3ca | 2269 | |
f103fc7d JB |
2270 | seq_printf(m, "\tmodes:\n"); |
2271 | list_for_each_entry(mode, &connector->modes, head) | |
2272 | intel_seq_print_mode(m, 2, mode); | |
53f5e3ca JB |
2273 | } |
2274 | ||
065f2ec2 CW |
2275 | static bool cursor_active(struct drm_device *dev, int pipe) |
2276 | { | |
2277 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2278 | u32 state; | |
2279 | ||
2280 | if (IS_845G(dev) || IS_I865G(dev)) | |
2281 | state = I915_READ(_CURACNTR) & CURSOR_ENABLE; | |
065f2ec2 | 2282 | else |
5efb3e28 | 2283 | state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE; |
065f2ec2 CW |
2284 | |
2285 | return state; | |
2286 | } | |
2287 | ||
2288 | static bool cursor_position(struct drm_device *dev, int pipe, int *x, int *y) | |
2289 | { | |
2290 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2291 | u32 pos; | |
2292 | ||
5efb3e28 | 2293 | pos = I915_READ(CURPOS(pipe)); |
065f2ec2 CW |
2294 | |
2295 | *x = (pos >> CURSOR_X_SHIFT) & CURSOR_POS_MASK; | |
2296 | if (pos & (CURSOR_POS_SIGN << CURSOR_X_SHIFT)) | |
2297 | *x = -*x; | |
2298 | ||
2299 | *y = (pos >> CURSOR_Y_SHIFT) & CURSOR_POS_MASK; | |
2300 | if (pos & (CURSOR_POS_SIGN << CURSOR_Y_SHIFT)) | |
2301 | *y = -*y; | |
2302 | ||
2303 | return cursor_active(dev, pipe); | |
2304 | } | |
2305 | ||
53f5e3ca JB |
2306 | static int i915_display_info(struct seq_file *m, void *unused) |
2307 | { | |
9f25d007 | 2308 | struct drm_info_node *node = m->private; |
53f5e3ca | 2309 | struct drm_device *dev = node->minor->dev; |
b0e5ddf3 | 2310 | struct drm_i915_private *dev_priv = dev->dev_private; |
065f2ec2 | 2311 | struct intel_crtc *crtc; |
53f5e3ca JB |
2312 | struct drm_connector *connector; |
2313 | ||
b0e5ddf3 | 2314 | intel_runtime_pm_get(dev_priv); |
53f5e3ca JB |
2315 | drm_modeset_lock_all(dev); |
2316 | seq_printf(m, "CRTC info\n"); | |
2317 | seq_printf(m, "---------\n"); | |
d3fcc808 | 2318 | for_each_intel_crtc(dev, crtc) { |
065f2ec2 CW |
2319 | bool active; |
2320 | int x, y; | |
53f5e3ca | 2321 | |
57127efa | 2322 | seq_printf(m, "CRTC %d: pipe: %c, active=%s (size=%dx%d)\n", |
065f2ec2 | 2323 | crtc->base.base.id, pipe_name(crtc->pipe), |
57127efa | 2324 | yesno(crtc->active), crtc->config.pipe_src_w, crtc->config.pipe_src_h); |
a23dc658 | 2325 | if (crtc->active) { |
065f2ec2 CW |
2326 | intel_crtc_info(m, crtc); |
2327 | ||
a23dc658 | 2328 | active = cursor_position(dev, crtc->pipe, &x, &y); |
57127efa | 2329 | seq_printf(m, "\tcursor visible? %s, position (%d, %d), size %dx%d, addr 0x%08x, active? %s\n", |
4b0e333e | 2330 | yesno(crtc->cursor_base), |
57127efa CW |
2331 | x, y, crtc->cursor_width, crtc->cursor_height, |
2332 | crtc->cursor_addr, yesno(active)); | |
a23dc658 | 2333 | } |
cace841c DV |
2334 | |
2335 | seq_printf(m, "\tunderrun reporting: cpu=%s pch=%s \n", | |
2336 | yesno(!crtc->cpu_fifo_underrun_disabled), | |
2337 | yesno(!crtc->pch_fifo_underrun_disabled)); | |
53f5e3ca JB |
2338 | } |
2339 | ||
2340 | seq_printf(m, "\n"); | |
2341 | seq_printf(m, "Connector info\n"); | |
2342 | seq_printf(m, "--------------\n"); | |
2343 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { | |
2344 | intel_connector_info(m, connector); | |
2345 | } | |
2346 | drm_modeset_unlock_all(dev); | |
b0e5ddf3 | 2347 | intel_runtime_pm_put(dev_priv); |
53f5e3ca JB |
2348 | |
2349 | return 0; | |
2350 | } | |
2351 | ||
e04934cf BW |
2352 | static int i915_semaphore_status(struct seq_file *m, void *unused) |
2353 | { | |
2354 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
2355 | struct drm_device *dev = node->minor->dev; | |
2356 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2357 | struct intel_engine_cs *ring; | |
2358 | int num_rings = hweight32(INTEL_INFO(dev)->ring_mask); | |
2359 | int i, j, ret; | |
2360 | ||
2361 | if (!i915_semaphore_is_enabled(dev)) { | |
2362 | seq_puts(m, "Semaphores are disabled\n"); | |
2363 | return 0; | |
2364 | } | |
2365 | ||
2366 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
2367 | if (ret) | |
2368 | return ret; | |
03872064 | 2369 | intel_runtime_pm_get(dev_priv); |
e04934cf BW |
2370 | |
2371 | if (IS_BROADWELL(dev)) { | |
2372 | struct page *page; | |
2373 | uint64_t *seqno; | |
2374 | ||
2375 | page = i915_gem_object_get_page(dev_priv->semaphore_obj, 0); | |
2376 | ||
2377 | seqno = (uint64_t *)kmap_atomic(page); | |
2378 | for_each_ring(ring, dev_priv, i) { | |
2379 | uint64_t offset; | |
2380 | ||
2381 | seq_printf(m, "%s\n", ring->name); | |
2382 | ||
2383 | seq_puts(m, " Last signal:"); | |
2384 | for (j = 0; j < num_rings; j++) { | |
2385 | offset = i * I915_NUM_RINGS + j; | |
2386 | seq_printf(m, "0x%08llx (0x%02llx) ", | |
2387 | seqno[offset], offset * 8); | |
2388 | } | |
2389 | seq_putc(m, '\n'); | |
2390 | ||
2391 | seq_puts(m, " Last wait: "); | |
2392 | for (j = 0; j < num_rings; j++) { | |
2393 | offset = i + (j * I915_NUM_RINGS); | |
2394 | seq_printf(m, "0x%08llx (0x%02llx) ", | |
2395 | seqno[offset], offset * 8); | |
2396 | } | |
2397 | seq_putc(m, '\n'); | |
2398 | ||
2399 | } | |
2400 | kunmap_atomic(seqno); | |
2401 | } else { | |
2402 | seq_puts(m, " Last signal:"); | |
2403 | for_each_ring(ring, dev_priv, i) | |
2404 | for (j = 0; j < num_rings; j++) | |
2405 | seq_printf(m, "0x%08x\n", | |
2406 | I915_READ(ring->semaphore.mbox.signal[j])); | |
2407 | seq_putc(m, '\n'); | |
2408 | } | |
2409 | ||
2410 | seq_puts(m, "\nSync seqno:\n"); | |
2411 | for_each_ring(ring, dev_priv, i) { | |
2412 | for (j = 0; j < num_rings; j++) { | |
2413 | seq_printf(m, " 0x%08x ", ring->semaphore.sync_seqno[j]); | |
2414 | } | |
2415 | seq_putc(m, '\n'); | |
2416 | } | |
2417 | seq_putc(m, '\n'); | |
2418 | ||
03872064 | 2419 | intel_runtime_pm_put(dev_priv); |
e04934cf BW |
2420 | mutex_unlock(&dev->struct_mutex); |
2421 | return 0; | |
2422 | } | |
2423 | ||
728e29d7 DV |
2424 | static int i915_shared_dplls_info(struct seq_file *m, void *unused) |
2425 | { | |
2426 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
2427 | struct drm_device *dev = node->minor->dev; | |
2428 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2429 | int i; | |
2430 | ||
2431 | drm_modeset_lock_all(dev); | |
2432 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { | |
2433 | struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; | |
2434 | ||
2435 | seq_printf(m, "DPLL%i: %s, id: %i\n", i, pll->name, pll->id); | |
2436 | seq_printf(m, " refcount: %i, active: %i, on: %s\n", pll->refcount, | |
2437 | pll->active, yesno(pll->on)); | |
2438 | seq_printf(m, " tracked hardware state:\n"); | |
2439 | seq_printf(m, " dpll: 0x%08x\n", pll->hw_state.dpll); | |
2440 | seq_printf(m, " dpll_md: 0x%08x\n", pll->hw_state.dpll_md); | |
2441 | seq_printf(m, " fp0: 0x%08x\n", pll->hw_state.fp0); | |
2442 | seq_printf(m, " fp1: 0x%08x\n", pll->hw_state.fp1); | |
d452c5b6 | 2443 | seq_printf(m, " wrpll: 0x%08x\n", pll->hw_state.wrpll); |
728e29d7 DV |
2444 | } |
2445 | drm_modeset_unlock_all(dev); | |
2446 | ||
2447 | return 0; | |
2448 | } | |
2449 | ||
07144428 DL |
2450 | struct pipe_crc_info { |
2451 | const char *name; | |
2452 | struct drm_device *dev; | |
2453 | enum pipe pipe; | |
2454 | }; | |
2455 | ||
11bed958 DA |
2456 | static int i915_dp_mst_info(struct seq_file *m, void *unused) |
2457 | { | |
2458 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
2459 | struct drm_device *dev = node->minor->dev; | |
2460 | struct drm_encoder *encoder; | |
2461 | struct intel_encoder *intel_encoder; | |
2462 | struct intel_digital_port *intel_dig_port; | |
2463 | drm_modeset_lock_all(dev); | |
2464 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { | |
2465 | intel_encoder = to_intel_encoder(encoder); | |
2466 | if (intel_encoder->type != INTEL_OUTPUT_DISPLAYPORT) | |
2467 | continue; | |
2468 | intel_dig_port = enc_to_dig_port(encoder); | |
2469 | if (!intel_dig_port->dp.can_mst) | |
2470 | continue; | |
2471 | ||
2472 | drm_dp_mst_dump_topology(m, &intel_dig_port->dp.mst_mgr); | |
2473 | } | |
2474 | drm_modeset_unlock_all(dev); | |
2475 | return 0; | |
2476 | } | |
2477 | ||
07144428 DL |
2478 | static int i915_pipe_crc_open(struct inode *inode, struct file *filep) |
2479 | { | |
be5c7a90 DL |
2480 | struct pipe_crc_info *info = inode->i_private; |
2481 | struct drm_i915_private *dev_priv = info->dev->dev_private; | |
2482 | struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe]; | |
2483 | ||
7eb1c496 DV |
2484 | if (info->pipe >= INTEL_INFO(info->dev)->num_pipes) |
2485 | return -ENODEV; | |
2486 | ||
d538bbdf DL |
2487 | spin_lock_irq(&pipe_crc->lock); |
2488 | ||
2489 | if (pipe_crc->opened) { | |
2490 | spin_unlock_irq(&pipe_crc->lock); | |
be5c7a90 DL |
2491 | return -EBUSY; /* already open */ |
2492 | } | |
2493 | ||
d538bbdf | 2494 | pipe_crc->opened = true; |
07144428 DL |
2495 | filep->private_data = inode->i_private; |
2496 | ||
d538bbdf DL |
2497 | spin_unlock_irq(&pipe_crc->lock); |
2498 | ||
07144428 DL |
2499 | return 0; |
2500 | } | |
2501 | ||
2502 | static int i915_pipe_crc_release(struct inode *inode, struct file *filep) | |
2503 | { | |
be5c7a90 DL |
2504 | struct pipe_crc_info *info = inode->i_private; |
2505 | struct drm_i915_private *dev_priv = info->dev->dev_private; | |
2506 | struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe]; | |
2507 | ||
d538bbdf DL |
2508 | spin_lock_irq(&pipe_crc->lock); |
2509 | pipe_crc->opened = false; | |
2510 | spin_unlock_irq(&pipe_crc->lock); | |
be5c7a90 | 2511 | |
07144428 DL |
2512 | return 0; |
2513 | } | |
2514 | ||
2515 | /* (6 fields, 8 chars each, space separated (5) + '\n') */ | |
2516 | #define PIPE_CRC_LINE_LEN (6 * 8 + 5 + 1) | |
2517 | /* account for \'0' */ | |
2518 | #define PIPE_CRC_BUFFER_LEN (PIPE_CRC_LINE_LEN + 1) | |
2519 | ||
2520 | static int pipe_crc_data_count(struct intel_pipe_crc *pipe_crc) | |
8bf1e9f1 | 2521 | { |
d538bbdf DL |
2522 | assert_spin_locked(&pipe_crc->lock); |
2523 | return CIRC_CNT(pipe_crc->head, pipe_crc->tail, | |
2524 | INTEL_PIPE_CRC_ENTRIES_NR); | |
07144428 DL |
2525 | } |
2526 | ||
2527 | static ssize_t | |
2528 | i915_pipe_crc_read(struct file *filep, char __user *user_buf, size_t count, | |
2529 | loff_t *pos) | |
2530 | { | |
2531 | struct pipe_crc_info *info = filep->private_data; | |
2532 | struct drm_device *dev = info->dev; | |
2533 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2534 | struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe]; | |
2535 | char buf[PIPE_CRC_BUFFER_LEN]; | |
2536 | int head, tail, n_entries, n; | |
2537 | ssize_t bytes_read; | |
2538 | ||
2539 | /* | |
2540 | * Don't allow user space to provide buffers not big enough to hold | |
2541 | * a line of data. | |
2542 | */ | |
2543 | if (count < PIPE_CRC_LINE_LEN) | |
2544 | return -EINVAL; | |
2545 | ||
2546 | if (pipe_crc->source == INTEL_PIPE_CRC_SOURCE_NONE) | |
8bf1e9f1 | 2547 | return 0; |
07144428 DL |
2548 | |
2549 | /* nothing to read */ | |
d538bbdf | 2550 | spin_lock_irq(&pipe_crc->lock); |
07144428 | 2551 | while (pipe_crc_data_count(pipe_crc) == 0) { |
d538bbdf DL |
2552 | int ret; |
2553 | ||
2554 | if (filep->f_flags & O_NONBLOCK) { | |
2555 | spin_unlock_irq(&pipe_crc->lock); | |
07144428 | 2556 | return -EAGAIN; |
d538bbdf | 2557 | } |
07144428 | 2558 | |
d538bbdf DL |
2559 | ret = wait_event_interruptible_lock_irq(pipe_crc->wq, |
2560 | pipe_crc_data_count(pipe_crc), pipe_crc->lock); | |
2561 | if (ret) { | |
2562 | spin_unlock_irq(&pipe_crc->lock); | |
2563 | return ret; | |
2564 | } | |
8bf1e9f1 SH |
2565 | } |
2566 | ||
07144428 | 2567 | /* We now have one or more entries to read */ |
d538bbdf DL |
2568 | head = pipe_crc->head; |
2569 | tail = pipe_crc->tail; | |
07144428 DL |
2570 | n_entries = min((size_t)CIRC_CNT(head, tail, INTEL_PIPE_CRC_ENTRIES_NR), |
2571 | count / PIPE_CRC_LINE_LEN); | |
d538bbdf DL |
2572 | spin_unlock_irq(&pipe_crc->lock); |
2573 | ||
07144428 DL |
2574 | bytes_read = 0; |
2575 | n = 0; | |
2576 | do { | |
b2c88f5b | 2577 | struct intel_pipe_crc_entry *entry = &pipe_crc->entries[tail]; |
07144428 | 2578 | int ret; |
8bf1e9f1 | 2579 | |
07144428 DL |
2580 | bytes_read += snprintf(buf, PIPE_CRC_BUFFER_LEN, |
2581 | "%8u %8x %8x %8x %8x %8x\n", | |
2582 | entry->frame, entry->crc[0], | |
2583 | entry->crc[1], entry->crc[2], | |
2584 | entry->crc[3], entry->crc[4]); | |
2585 | ||
2586 | ret = copy_to_user(user_buf + n * PIPE_CRC_LINE_LEN, | |
2587 | buf, PIPE_CRC_LINE_LEN); | |
2588 | if (ret == PIPE_CRC_LINE_LEN) | |
2589 | return -EFAULT; | |
b2c88f5b DL |
2590 | |
2591 | BUILD_BUG_ON_NOT_POWER_OF_2(INTEL_PIPE_CRC_ENTRIES_NR); | |
2592 | tail = (tail + 1) & (INTEL_PIPE_CRC_ENTRIES_NR - 1); | |
07144428 DL |
2593 | n++; |
2594 | } while (--n_entries); | |
8bf1e9f1 | 2595 | |
d538bbdf DL |
2596 | spin_lock_irq(&pipe_crc->lock); |
2597 | pipe_crc->tail = tail; | |
2598 | spin_unlock_irq(&pipe_crc->lock); | |
2599 | ||
07144428 DL |
2600 | return bytes_read; |
2601 | } | |
2602 | ||
2603 | static const struct file_operations i915_pipe_crc_fops = { | |
2604 | .owner = THIS_MODULE, | |
2605 | .open = i915_pipe_crc_open, | |
2606 | .read = i915_pipe_crc_read, | |
2607 | .release = i915_pipe_crc_release, | |
2608 | }; | |
2609 | ||
2610 | static struct pipe_crc_info i915_pipe_crc_data[I915_MAX_PIPES] = { | |
2611 | { | |
2612 | .name = "i915_pipe_A_crc", | |
2613 | .pipe = PIPE_A, | |
2614 | }, | |
2615 | { | |
2616 | .name = "i915_pipe_B_crc", | |
2617 | .pipe = PIPE_B, | |
2618 | }, | |
2619 | { | |
2620 | .name = "i915_pipe_C_crc", | |
2621 | .pipe = PIPE_C, | |
2622 | }, | |
2623 | }; | |
2624 | ||
2625 | static int i915_pipe_crc_create(struct dentry *root, struct drm_minor *minor, | |
2626 | enum pipe pipe) | |
2627 | { | |
2628 | struct drm_device *dev = minor->dev; | |
2629 | struct dentry *ent; | |
2630 | struct pipe_crc_info *info = &i915_pipe_crc_data[pipe]; | |
2631 | ||
2632 | info->dev = dev; | |
2633 | ent = debugfs_create_file(info->name, S_IRUGO, root, info, | |
2634 | &i915_pipe_crc_fops); | |
f3c5fe97 WY |
2635 | if (!ent) |
2636 | return -ENOMEM; | |
07144428 DL |
2637 | |
2638 | return drm_add_fake_info_node(minor, ent, info); | |
8bf1e9f1 SH |
2639 | } |
2640 | ||
e8dfcf78 | 2641 | static const char * const pipe_crc_sources[] = { |
926321d5 DV |
2642 | "none", |
2643 | "plane1", | |
2644 | "plane2", | |
2645 | "pf", | |
5b3a856b | 2646 | "pipe", |
3d099a05 DV |
2647 | "TV", |
2648 | "DP-B", | |
2649 | "DP-C", | |
2650 | "DP-D", | |
46a19188 | 2651 | "auto", |
926321d5 DV |
2652 | }; |
2653 | ||
2654 | static const char *pipe_crc_source_name(enum intel_pipe_crc_source source) | |
2655 | { | |
2656 | BUILD_BUG_ON(ARRAY_SIZE(pipe_crc_sources) != INTEL_PIPE_CRC_SOURCE_MAX); | |
2657 | return pipe_crc_sources[source]; | |
2658 | } | |
2659 | ||
bd9db02f | 2660 | static int display_crc_ctl_show(struct seq_file *m, void *data) |
926321d5 DV |
2661 | { |
2662 | struct drm_device *dev = m->private; | |
2663 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2664 | int i; | |
2665 | ||
2666 | for (i = 0; i < I915_MAX_PIPES; i++) | |
2667 | seq_printf(m, "%c %s\n", pipe_name(i), | |
2668 | pipe_crc_source_name(dev_priv->pipe_crc[i].source)); | |
2669 | ||
2670 | return 0; | |
2671 | } | |
2672 | ||
bd9db02f | 2673 | static int display_crc_ctl_open(struct inode *inode, struct file *file) |
926321d5 DV |
2674 | { |
2675 | struct drm_device *dev = inode->i_private; | |
2676 | ||
bd9db02f | 2677 | return single_open(file, display_crc_ctl_show, dev); |
926321d5 DV |
2678 | } |
2679 | ||
46a19188 | 2680 | static int i8xx_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source, |
52f843f6 DV |
2681 | uint32_t *val) |
2682 | { | |
46a19188 DV |
2683 | if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) |
2684 | *source = INTEL_PIPE_CRC_SOURCE_PIPE; | |
2685 | ||
2686 | switch (*source) { | |
52f843f6 DV |
2687 | case INTEL_PIPE_CRC_SOURCE_PIPE: |
2688 | *val = PIPE_CRC_ENABLE | PIPE_CRC_INCLUDE_BORDER_I8XX; | |
2689 | break; | |
2690 | case INTEL_PIPE_CRC_SOURCE_NONE: | |
2691 | *val = 0; | |
2692 | break; | |
2693 | default: | |
2694 | return -EINVAL; | |
2695 | } | |
2696 | ||
2697 | return 0; | |
2698 | } | |
2699 | ||
46a19188 DV |
2700 | static int i9xx_pipe_crc_auto_source(struct drm_device *dev, enum pipe pipe, |
2701 | enum intel_pipe_crc_source *source) | |
2702 | { | |
2703 | struct intel_encoder *encoder; | |
2704 | struct intel_crtc *crtc; | |
26756809 | 2705 | struct intel_digital_port *dig_port; |
46a19188 DV |
2706 | int ret = 0; |
2707 | ||
2708 | *source = INTEL_PIPE_CRC_SOURCE_PIPE; | |
2709 | ||
6e9f798d | 2710 | drm_modeset_lock_all(dev); |
46a19188 DV |
2711 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, |
2712 | base.head) { | |
2713 | if (!encoder->base.crtc) | |
2714 | continue; | |
2715 | ||
2716 | crtc = to_intel_crtc(encoder->base.crtc); | |
2717 | ||
2718 | if (crtc->pipe != pipe) | |
2719 | continue; | |
2720 | ||
2721 | switch (encoder->type) { | |
2722 | case INTEL_OUTPUT_TVOUT: | |
2723 | *source = INTEL_PIPE_CRC_SOURCE_TV; | |
2724 | break; | |
2725 | case INTEL_OUTPUT_DISPLAYPORT: | |
2726 | case INTEL_OUTPUT_EDP: | |
26756809 DV |
2727 | dig_port = enc_to_dig_port(&encoder->base); |
2728 | switch (dig_port->port) { | |
2729 | case PORT_B: | |
2730 | *source = INTEL_PIPE_CRC_SOURCE_DP_B; | |
2731 | break; | |
2732 | case PORT_C: | |
2733 | *source = INTEL_PIPE_CRC_SOURCE_DP_C; | |
2734 | break; | |
2735 | case PORT_D: | |
2736 | *source = INTEL_PIPE_CRC_SOURCE_DP_D; | |
2737 | break; | |
2738 | default: | |
2739 | WARN(1, "nonexisting DP port %c\n", | |
2740 | port_name(dig_port->port)); | |
2741 | break; | |
2742 | } | |
46a19188 DV |
2743 | break; |
2744 | } | |
2745 | } | |
6e9f798d | 2746 | drm_modeset_unlock_all(dev); |
46a19188 DV |
2747 | |
2748 | return ret; | |
2749 | } | |
2750 | ||
2751 | static int vlv_pipe_crc_ctl_reg(struct drm_device *dev, | |
2752 | enum pipe pipe, | |
2753 | enum intel_pipe_crc_source *source, | |
7ac0129b DV |
2754 | uint32_t *val) |
2755 | { | |
8d2f24ca DV |
2756 | struct drm_i915_private *dev_priv = dev->dev_private; |
2757 | bool need_stable_symbols = false; | |
2758 | ||
46a19188 DV |
2759 | if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) { |
2760 | int ret = i9xx_pipe_crc_auto_source(dev, pipe, source); | |
2761 | if (ret) | |
2762 | return ret; | |
2763 | } | |
2764 | ||
2765 | switch (*source) { | |
7ac0129b DV |
2766 | case INTEL_PIPE_CRC_SOURCE_PIPE: |
2767 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_VLV; | |
2768 | break; | |
2769 | case INTEL_PIPE_CRC_SOURCE_DP_B: | |
2770 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_VLV; | |
8d2f24ca | 2771 | need_stable_symbols = true; |
7ac0129b DV |
2772 | break; |
2773 | case INTEL_PIPE_CRC_SOURCE_DP_C: | |
2774 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_VLV; | |
8d2f24ca | 2775 | need_stable_symbols = true; |
7ac0129b DV |
2776 | break; |
2777 | case INTEL_PIPE_CRC_SOURCE_NONE: | |
2778 | *val = 0; | |
2779 | break; | |
2780 | default: | |
2781 | return -EINVAL; | |
2782 | } | |
2783 | ||
8d2f24ca DV |
2784 | /* |
2785 | * When the pipe CRC tap point is after the transcoders we need | |
2786 | * to tweak symbol-level features to produce a deterministic series of | |
2787 | * symbols for a given frame. We need to reset those features only once | |
2788 | * a frame (instead of every nth symbol): | |
2789 | * - DC-balance: used to ensure a better clock recovery from the data | |
2790 | * link (SDVO) | |
2791 | * - DisplayPort scrambling: used for EMI reduction | |
2792 | */ | |
2793 | if (need_stable_symbols) { | |
2794 | uint32_t tmp = I915_READ(PORT_DFT2_G4X); | |
2795 | ||
8d2f24ca DV |
2796 | tmp |= DC_BALANCE_RESET_VLV; |
2797 | if (pipe == PIPE_A) | |
2798 | tmp |= PIPE_A_SCRAMBLE_RESET; | |
2799 | else | |
2800 | tmp |= PIPE_B_SCRAMBLE_RESET; | |
2801 | ||
2802 | I915_WRITE(PORT_DFT2_G4X, tmp); | |
2803 | } | |
2804 | ||
7ac0129b DV |
2805 | return 0; |
2806 | } | |
2807 | ||
4b79ebf7 | 2808 | static int i9xx_pipe_crc_ctl_reg(struct drm_device *dev, |
46a19188 DV |
2809 | enum pipe pipe, |
2810 | enum intel_pipe_crc_source *source, | |
4b79ebf7 DV |
2811 | uint32_t *val) |
2812 | { | |
84093603 DV |
2813 | struct drm_i915_private *dev_priv = dev->dev_private; |
2814 | bool need_stable_symbols = false; | |
2815 | ||
46a19188 DV |
2816 | if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) { |
2817 | int ret = i9xx_pipe_crc_auto_source(dev, pipe, source); | |
2818 | if (ret) | |
2819 | return ret; | |
2820 | } | |
2821 | ||
2822 | switch (*source) { | |
4b79ebf7 DV |
2823 | case INTEL_PIPE_CRC_SOURCE_PIPE: |
2824 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_I9XX; | |
2825 | break; | |
2826 | case INTEL_PIPE_CRC_SOURCE_TV: | |
2827 | if (!SUPPORTS_TV(dev)) | |
2828 | return -EINVAL; | |
2829 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_TV_PRE; | |
2830 | break; | |
2831 | case INTEL_PIPE_CRC_SOURCE_DP_B: | |
2832 | if (!IS_G4X(dev)) | |
2833 | return -EINVAL; | |
2834 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_G4X; | |
84093603 | 2835 | need_stable_symbols = true; |
4b79ebf7 DV |
2836 | break; |
2837 | case INTEL_PIPE_CRC_SOURCE_DP_C: | |
2838 | if (!IS_G4X(dev)) | |
2839 | return -EINVAL; | |
2840 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_G4X; | |
84093603 | 2841 | need_stable_symbols = true; |
4b79ebf7 DV |
2842 | break; |
2843 | case INTEL_PIPE_CRC_SOURCE_DP_D: | |
2844 | if (!IS_G4X(dev)) | |
2845 | return -EINVAL; | |
2846 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_D_G4X; | |
84093603 | 2847 | need_stable_symbols = true; |
4b79ebf7 DV |
2848 | break; |
2849 | case INTEL_PIPE_CRC_SOURCE_NONE: | |
2850 | *val = 0; | |
2851 | break; | |
2852 | default: | |
2853 | return -EINVAL; | |
2854 | } | |
2855 | ||
84093603 DV |
2856 | /* |
2857 | * When the pipe CRC tap point is after the transcoders we need | |
2858 | * to tweak symbol-level features to produce a deterministic series of | |
2859 | * symbols for a given frame. We need to reset those features only once | |
2860 | * a frame (instead of every nth symbol): | |
2861 | * - DC-balance: used to ensure a better clock recovery from the data | |
2862 | * link (SDVO) | |
2863 | * - DisplayPort scrambling: used for EMI reduction | |
2864 | */ | |
2865 | if (need_stable_symbols) { | |
2866 | uint32_t tmp = I915_READ(PORT_DFT2_G4X); | |
2867 | ||
2868 | WARN_ON(!IS_G4X(dev)); | |
2869 | ||
2870 | I915_WRITE(PORT_DFT_I9XX, | |
2871 | I915_READ(PORT_DFT_I9XX) | DC_BALANCE_RESET); | |
2872 | ||
2873 | if (pipe == PIPE_A) | |
2874 | tmp |= PIPE_A_SCRAMBLE_RESET; | |
2875 | else | |
2876 | tmp |= PIPE_B_SCRAMBLE_RESET; | |
2877 | ||
2878 | I915_WRITE(PORT_DFT2_G4X, tmp); | |
2879 | } | |
2880 | ||
4b79ebf7 DV |
2881 | return 0; |
2882 | } | |
2883 | ||
8d2f24ca DV |
2884 | static void vlv_undo_pipe_scramble_reset(struct drm_device *dev, |
2885 | enum pipe pipe) | |
2886 | { | |
2887 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2888 | uint32_t tmp = I915_READ(PORT_DFT2_G4X); | |
2889 | ||
2890 | if (pipe == PIPE_A) | |
2891 | tmp &= ~PIPE_A_SCRAMBLE_RESET; | |
2892 | else | |
2893 | tmp &= ~PIPE_B_SCRAMBLE_RESET; | |
2894 | if (!(tmp & PIPE_SCRAMBLE_RESET_MASK)) | |
2895 | tmp &= ~DC_BALANCE_RESET_VLV; | |
2896 | I915_WRITE(PORT_DFT2_G4X, tmp); | |
2897 | ||
2898 | } | |
2899 | ||
84093603 DV |
2900 | static void g4x_undo_pipe_scramble_reset(struct drm_device *dev, |
2901 | enum pipe pipe) | |
2902 | { | |
2903 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2904 | uint32_t tmp = I915_READ(PORT_DFT2_G4X); | |
2905 | ||
2906 | if (pipe == PIPE_A) | |
2907 | tmp &= ~PIPE_A_SCRAMBLE_RESET; | |
2908 | else | |
2909 | tmp &= ~PIPE_B_SCRAMBLE_RESET; | |
2910 | I915_WRITE(PORT_DFT2_G4X, tmp); | |
2911 | ||
2912 | if (!(tmp & PIPE_SCRAMBLE_RESET_MASK)) { | |
2913 | I915_WRITE(PORT_DFT_I9XX, | |
2914 | I915_READ(PORT_DFT_I9XX) & ~DC_BALANCE_RESET); | |
2915 | } | |
2916 | } | |
2917 | ||
46a19188 | 2918 | static int ilk_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source, |
5b3a856b DV |
2919 | uint32_t *val) |
2920 | { | |
46a19188 DV |
2921 | if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) |
2922 | *source = INTEL_PIPE_CRC_SOURCE_PIPE; | |
2923 | ||
2924 | switch (*source) { | |
5b3a856b DV |
2925 | case INTEL_PIPE_CRC_SOURCE_PLANE1: |
2926 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_ILK; | |
2927 | break; | |
2928 | case INTEL_PIPE_CRC_SOURCE_PLANE2: | |
2929 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_ILK; | |
2930 | break; | |
5b3a856b DV |
2931 | case INTEL_PIPE_CRC_SOURCE_PIPE: |
2932 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_ILK; | |
2933 | break; | |
3d099a05 | 2934 | case INTEL_PIPE_CRC_SOURCE_NONE: |
5b3a856b DV |
2935 | *val = 0; |
2936 | break; | |
3d099a05 DV |
2937 | default: |
2938 | return -EINVAL; | |
5b3a856b DV |
2939 | } |
2940 | ||
2941 | return 0; | |
2942 | } | |
2943 | ||
fabf6e51 DV |
2944 | static void hsw_trans_edp_pipe_A_crc_wa(struct drm_device *dev) |
2945 | { | |
2946 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2947 | struct intel_crtc *crtc = | |
2948 | to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_A]); | |
2949 | ||
2950 | drm_modeset_lock_all(dev); | |
2951 | /* | |
2952 | * If we use the eDP transcoder we need to make sure that we don't | |
2953 | * bypass the pfit, since otherwise the pipe CRC source won't work. Only | |
2954 | * relevant on hsw with pipe A when using the always-on power well | |
2955 | * routing. | |
2956 | */ | |
2957 | if (crtc->config.cpu_transcoder == TRANSCODER_EDP && | |
2958 | !crtc->config.pch_pfit.enabled) { | |
2959 | crtc->config.pch_pfit.force_thru = true; | |
2960 | ||
2961 | intel_display_power_get(dev_priv, | |
2962 | POWER_DOMAIN_PIPE_PANEL_FITTER(PIPE_A)); | |
2963 | ||
2964 | dev_priv->display.crtc_disable(&crtc->base); | |
2965 | dev_priv->display.crtc_enable(&crtc->base); | |
2966 | } | |
2967 | drm_modeset_unlock_all(dev); | |
2968 | } | |
2969 | ||
2970 | static void hsw_undo_trans_edp_pipe_A_crc_wa(struct drm_device *dev) | |
2971 | { | |
2972 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2973 | struct intel_crtc *crtc = | |
2974 | to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_A]); | |
2975 | ||
2976 | drm_modeset_lock_all(dev); | |
2977 | /* | |
2978 | * If we use the eDP transcoder we need to make sure that we don't | |
2979 | * bypass the pfit, since otherwise the pipe CRC source won't work. Only | |
2980 | * relevant on hsw with pipe A when using the always-on power well | |
2981 | * routing. | |
2982 | */ | |
2983 | if (crtc->config.pch_pfit.force_thru) { | |
2984 | crtc->config.pch_pfit.force_thru = false; | |
2985 | ||
2986 | dev_priv->display.crtc_disable(&crtc->base); | |
2987 | dev_priv->display.crtc_enable(&crtc->base); | |
2988 | ||
2989 | intel_display_power_put(dev_priv, | |
2990 | POWER_DOMAIN_PIPE_PANEL_FITTER(PIPE_A)); | |
2991 | } | |
2992 | drm_modeset_unlock_all(dev); | |
2993 | } | |
2994 | ||
2995 | static int ivb_pipe_crc_ctl_reg(struct drm_device *dev, | |
2996 | enum pipe pipe, | |
2997 | enum intel_pipe_crc_source *source, | |
5b3a856b DV |
2998 | uint32_t *val) |
2999 | { | |
46a19188 DV |
3000 | if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) |
3001 | *source = INTEL_PIPE_CRC_SOURCE_PF; | |
3002 | ||
3003 | switch (*source) { | |
5b3a856b DV |
3004 | case INTEL_PIPE_CRC_SOURCE_PLANE1: |
3005 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_IVB; | |
3006 | break; | |
3007 | case INTEL_PIPE_CRC_SOURCE_PLANE2: | |
3008 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_IVB; | |
3009 | break; | |
3010 | case INTEL_PIPE_CRC_SOURCE_PF: | |
fabf6e51 DV |
3011 | if (IS_HASWELL(dev) && pipe == PIPE_A) |
3012 | hsw_trans_edp_pipe_A_crc_wa(dev); | |
3013 | ||
5b3a856b DV |
3014 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PF_IVB; |
3015 | break; | |
3d099a05 | 3016 | case INTEL_PIPE_CRC_SOURCE_NONE: |
5b3a856b DV |
3017 | *val = 0; |
3018 | break; | |
3d099a05 DV |
3019 | default: |
3020 | return -EINVAL; | |
5b3a856b DV |
3021 | } |
3022 | ||
3023 | return 0; | |
3024 | } | |
3025 | ||
926321d5 DV |
3026 | static int pipe_crc_set_source(struct drm_device *dev, enum pipe pipe, |
3027 | enum intel_pipe_crc_source source) | |
3028 | { | |
3029 | struct drm_i915_private *dev_priv = dev->dev_private; | |
cc3da175 | 3030 | struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe]; |
432f3342 | 3031 | u32 val = 0; /* shut up gcc */ |
5b3a856b | 3032 | int ret; |
926321d5 | 3033 | |
cc3da175 DL |
3034 | if (pipe_crc->source == source) |
3035 | return 0; | |
3036 | ||
ae676fcd DL |
3037 | /* forbid changing the source without going back to 'none' */ |
3038 | if (pipe_crc->source && source) | |
3039 | return -EINVAL; | |
3040 | ||
52f843f6 | 3041 | if (IS_GEN2(dev)) |
46a19188 | 3042 | ret = i8xx_pipe_crc_ctl_reg(&source, &val); |
52f843f6 | 3043 | else if (INTEL_INFO(dev)->gen < 5) |
46a19188 | 3044 | ret = i9xx_pipe_crc_ctl_reg(dev, pipe, &source, &val); |
7ac0129b | 3045 | else if (IS_VALLEYVIEW(dev)) |
fabf6e51 | 3046 | ret = vlv_pipe_crc_ctl_reg(dev, pipe, &source, &val); |
4b79ebf7 | 3047 | else if (IS_GEN5(dev) || IS_GEN6(dev)) |
46a19188 | 3048 | ret = ilk_pipe_crc_ctl_reg(&source, &val); |
5b3a856b | 3049 | else |
fabf6e51 | 3050 | ret = ivb_pipe_crc_ctl_reg(dev, pipe, &source, &val); |
5b3a856b DV |
3051 | |
3052 | if (ret != 0) | |
3053 | return ret; | |
3054 | ||
4b584369 DL |
3055 | /* none -> real source transition */ |
3056 | if (source) { | |
7cd6ccff DL |
3057 | DRM_DEBUG_DRIVER("collecting CRCs for pipe %c, %s\n", |
3058 | pipe_name(pipe), pipe_crc_source_name(source)); | |
3059 | ||
e5f75aca DL |
3060 | pipe_crc->entries = kzalloc(sizeof(*pipe_crc->entries) * |
3061 | INTEL_PIPE_CRC_ENTRIES_NR, | |
3062 | GFP_KERNEL); | |
3063 | if (!pipe_crc->entries) | |
3064 | return -ENOMEM; | |
3065 | ||
d538bbdf DL |
3066 | spin_lock_irq(&pipe_crc->lock); |
3067 | pipe_crc->head = 0; | |
3068 | pipe_crc->tail = 0; | |
3069 | spin_unlock_irq(&pipe_crc->lock); | |
4b584369 DL |
3070 | } |
3071 | ||
cc3da175 | 3072 | pipe_crc->source = source; |
926321d5 | 3073 | |
926321d5 DV |
3074 | I915_WRITE(PIPE_CRC_CTL(pipe), val); |
3075 | POSTING_READ(PIPE_CRC_CTL(pipe)); | |
3076 | ||
e5f75aca DL |
3077 | /* real source -> none transition */ |
3078 | if (source == INTEL_PIPE_CRC_SOURCE_NONE) { | |
d538bbdf | 3079 | struct intel_pipe_crc_entry *entries; |
a33d7105 DV |
3080 | struct intel_crtc *crtc = |
3081 | to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); | |
d538bbdf | 3082 | |
7cd6ccff DL |
3083 | DRM_DEBUG_DRIVER("stopping CRCs for pipe %c\n", |
3084 | pipe_name(pipe)); | |
3085 | ||
a33d7105 DV |
3086 | drm_modeset_lock(&crtc->base.mutex, NULL); |
3087 | if (crtc->active) | |
3088 | intel_wait_for_vblank(dev, pipe); | |
3089 | drm_modeset_unlock(&crtc->base.mutex); | |
bcf17ab2 | 3090 | |
d538bbdf DL |
3091 | spin_lock_irq(&pipe_crc->lock); |
3092 | entries = pipe_crc->entries; | |
e5f75aca | 3093 | pipe_crc->entries = NULL; |
d538bbdf DL |
3094 | spin_unlock_irq(&pipe_crc->lock); |
3095 | ||
3096 | kfree(entries); | |
84093603 DV |
3097 | |
3098 | if (IS_G4X(dev)) | |
3099 | g4x_undo_pipe_scramble_reset(dev, pipe); | |
8d2f24ca DV |
3100 | else if (IS_VALLEYVIEW(dev)) |
3101 | vlv_undo_pipe_scramble_reset(dev, pipe); | |
fabf6e51 DV |
3102 | else if (IS_HASWELL(dev) && pipe == PIPE_A) |
3103 | hsw_undo_trans_edp_pipe_A_crc_wa(dev); | |
e5f75aca DL |
3104 | } |
3105 | ||
926321d5 DV |
3106 | return 0; |
3107 | } | |
3108 | ||
3109 | /* | |
3110 | * Parse pipe CRC command strings: | |
b94dec87 DL |
3111 | * command: wsp* object wsp+ name wsp+ source wsp* |
3112 | * object: 'pipe' | |
3113 | * name: (A | B | C) | |
926321d5 DV |
3114 | * source: (none | plane1 | plane2 | pf) |
3115 | * wsp: (#0x20 | #0x9 | #0xA)+ | |
3116 | * | |
3117 | * eg.: | |
b94dec87 DL |
3118 | * "pipe A plane1" -> Start CRC computations on plane1 of pipe A |
3119 | * "pipe A none" -> Stop CRC | |
926321d5 | 3120 | */ |
bd9db02f | 3121 | static int display_crc_ctl_tokenize(char *buf, char *words[], int max_words) |
926321d5 DV |
3122 | { |
3123 | int n_words = 0; | |
3124 | ||
3125 | while (*buf) { | |
3126 | char *end; | |
3127 | ||
3128 | /* skip leading white space */ | |
3129 | buf = skip_spaces(buf); | |
3130 | if (!*buf) | |
3131 | break; /* end of buffer */ | |
3132 | ||
3133 | /* find end of word */ | |
3134 | for (end = buf; *end && !isspace(*end); end++) | |
3135 | ; | |
3136 | ||
3137 | if (n_words == max_words) { | |
3138 | DRM_DEBUG_DRIVER("too many words, allowed <= %d\n", | |
3139 | max_words); | |
3140 | return -EINVAL; /* ran out of words[] before bytes */ | |
3141 | } | |
3142 | ||
3143 | if (*end) | |
3144 | *end++ = '\0'; | |
3145 | words[n_words++] = buf; | |
3146 | buf = end; | |
3147 | } | |
3148 | ||
3149 | return n_words; | |
3150 | } | |
3151 | ||
b94dec87 DL |
3152 | enum intel_pipe_crc_object { |
3153 | PIPE_CRC_OBJECT_PIPE, | |
3154 | }; | |
3155 | ||
e8dfcf78 | 3156 | static const char * const pipe_crc_objects[] = { |
b94dec87 DL |
3157 | "pipe", |
3158 | }; | |
3159 | ||
3160 | static int | |
bd9db02f | 3161 | display_crc_ctl_parse_object(const char *buf, enum intel_pipe_crc_object *o) |
b94dec87 DL |
3162 | { |
3163 | int i; | |
3164 | ||
3165 | for (i = 0; i < ARRAY_SIZE(pipe_crc_objects); i++) | |
3166 | if (!strcmp(buf, pipe_crc_objects[i])) { | |
bd9db02f | 3167 | *o = i; |
b94dec87 DL |
3168 | return 0; |
3169 | } | |
3170 | ||
3171 | return -EINVAL; | |
3172 | } | |
3173 | ||
bd9db02f | 3174 | static int display_crc_ctl_parse_pipe(const char *buf, enum pipe *pipe) |
926321d5 DV |
3175 | { |
3176 | const char name = buf[0]; | |
3177 | ||
3178 | if (name < 'A' || name >= pipe_name(I915_MAX_PIPES)) | |
3179 | return -EINVAL; | |
3180 | ||
3181 | *pipe = name - 'A'; | |
3182 | ||
3183 | return 0; | |
3184 | } | |
3185 | ||
3186 | static int | |
bd9db02f | 3187 | display_crc_ctl_parse_source(const char *buf, enum intel_pipe_crc_source *s) |
926321d5 DV |
3188 | { |
3189 | int i; | |
3190 | ||
3191 | for (i = 0; i < ARRAY_SIZE(pipe_crc_sources); i++) | |
3192 | if (!strcmp(buf, pipe_crc_sources[i])) { | |
bd9db02f | 3193 | *s = i; |
926321d5 DV |
3194 | return 0; |
3195 | } | |
3196 | ||
3197 | return -EINVAL; | |
3198 | } | |
3199 | ||
bd9db02f | 3200 | static int display_crc_ctl_parse(struct drm_device *dev, char *buf, size_t len) |
926321d5 | 3201 | { |
b94dec87 | 3202 | #define N_WORDS 3 |
926321d5 | 3203 | int n_words; |
b94dec87 | 3204 | char *words[N_WORDS]; |
926321d5 | 3205 | enum pipe pipe; |
b94dec87 | 3206 | enum intel_pipe_crc_object object; |
926321d5 DV |
3207 | enum intel_pipe_crc_source source; |
3208 | ||
bd9db02f | 3209 | n_words = display_crc_ctl_tokenize(buf, words, N_WORDS); |
b94dec87 DL |
3210 | if (n_words != N_WORDS) { |
3211 | DRM_DEBUG_DRIVER("tokenize failed, a command is %d words\n", | |
3212 | N_WORDS); | |
3213 | return -EINVAL; | |
3214 | } | |
3215 | ||
bd9db02f | 3216 | if (display_crc_ctl_parse_object(words[0], &object) < 0) { |
b94dec87 | 3217 | DRM_DEBUG_DRIVER("unknown object %s\n", words[0]); |
926321d5 DV |
3218 | return -EINVAL; |
3219 | } | |
3220 | ||
bd9db02f | 3221 | if (display_crc_ctl_parse_pipe(words[1], &pipe) < 0) { |
b94dec87 | 3222 | DRM_DEBUG_DRIVER("unknown pipe %s\n", words[1]); |
926321d5 DV |
3223 | return -EINVAL; |
3224 | } | |
3225 | ||
bd9db02f | 3226 | if (display_crc_ctl_parse_source(words[2], &source) < 0) { |
b94dec87 | 3227 | DRM_DEBUG_DRIVER("unknown source %s\n", words[2]); |
926321d5 DV |
3228 | return -EINVAL; |
3229 | } | |
3230 | ||
3231 | return pipe_crc_set_source(dev, pipe, source); | |
3232 | } | |
3233 | ||
bd9db02f DL |
3234 | static ssize_t display_crc_ctl_write(struct file *file, const char __user *ubuf, |
3235 | size_t len, loff_t *offp) | |
926321d5 DV |
3236 | { |
3237 | struct seq_file *m = file->private_data; | |
3238 | struct drm_device *dev = m->private; | |
3239 | char *tmpbuf; | |
3240 | int ret; | |
3241 | ||
3242 | if (len == 0) | |
3243 | return 0; | |
3244 | ||
3245 | if (len > PAGE_SIZE - 1) { | |
3246 | DRM_DEBUG_DRIVER("expected <%lu bytes into pipe crc control\n", | |
3247 | PAGE_SIZE); | |
3248 | return -E2BIG; | |
3249 | } | |
3250 | ||
3251 | tmpbuf = kmalloc(len + 1, GFP_KERNEL); | |
3252 | if (!tmpbuf) | |
3253 | return -ENOMEM; | |
3254 | ||
3255 | if (copy_from_user(tmpbuf, ubuf, len)) { | |
3256 | ret = -EFAULT; | |
3257 | goto out; | |
3258 | } | |
3259 | tmpbuf[len] = '\0'; | |
3260 | ||
bd9db02f | 3261 | ret = display_crc_ctl_parse(dev, tmpbuf, len); |
926321d5 DV |
3262 | |
3263 | out: | |
3264 | kfree(tmpbuf); | |
3265 | if (ret < 0) | |
3266 | return ret; | |
3267 | ||
3268 | *offp += len; | |
3269 | return len; | |
3270 | } | |
3271 | ||
bd9db02f | 3272 | static const struct file_operations i915_display_crc_ctl_fops = { |
926321d5 | 3273 | .owner = THIS_MODULE, |
bd9db02f | 3274 | .open = display_crc_ctl_open, |
926321d5 DV |
3275 | .read = seq_read, |
3276 | .llseek = seq_lseek, | |
3277 | .release = single_release, | |
bd9db02f | 3278 | .write = display_crc_ctl_write |
926321d5 DV |
3279 | }; |
3280 | ||
369a1342 VS |
3281 | static void wm_latency_show(struct seq_file *m, const uint16_t wm[5]) |
3282 | { | |
3283 | struct drm_device *dev = m->private; | |
546c81fd | 3284 | int num_levels = ilk_wm_max_level(dev) + 1; |
369a1342 VS |
3285 | int level; |
3286 | ||
3287 | drm_modeset_lock_all(dev); | |
3288 | ||
3289 | for (level = 0; level < num_levels; level++) { | |
3290 | unsigned int latency = wm[level]; | |
3291 | ||
3292 | /* WM1+ latency values in 0.5us units */ | |
3293 | if (level > 0) | |
3294 | latency *= 5; | |
3295 | ||
3296 | seq_printf(m, "WM%d %u (%u.%u usec)\n", | |
3297 | level, wm[level], | |
3298 | latency / 10, latency % 10); | |
3299 | } | |
3300 | ||
3301 | drm_modeset_unlock_all(dev); | |
3302 | } | |
3303 | ||
3304 | static int pri_wm_latency_show(struct seq_file *m, void *data) | |
3305 | { | |
3306 | struct drm_device *dev = m->private; | |
3307 | ||
3308 | wm_latency_show(m, to_i915(dev)->wm.pri_latency); | |
3309 | ||
3310 | return 0; | |
3311 | } | |
3312 | ||
3313 | static int spr_wm_latency_show(struct seq_file *m, void *data) | |
3314 | { | |
3315 | struct drm_device *dev = m->private; | |
3316 | ||
3317 | wm_latency_show(m, to_i915(dev)->wm.spr_latency); | |
3318 | ||
3319 | return 0; | |
3320 | } | |
3321 | ||
3322 | static int cur_wm_latency_show(struct seq_file *m, void *data) | |
3323 | { | |
3324 | struct drm_device *dev = m->private; | |
3325 | ||
3326 | wm_latency_show(m, to_i915(dev)->wm.cur_latency); | |
3327 | ||
3328 | return 0; | |
3329 | } | |
3330 | ||
3331 | static int pri_wm_latency_open(struct inode *inode, struct file *file) | |
3332 | { | |
3333 | struct drm_device *dev = inode->i_private; | |
3334 | ||
9ad0257c | 3335 | if (HAS_GMCH_DISPLAY(dev)) |
369a1342 VS |
3336 | return -ENODEV; |
3337 | ||
3338 | return single_open(file, pri_wm_latency_show, dev); | |
3339 | } | |
3340 | ||
3341 | static int spr_wm_latency_open(struct inode *inode, struct file *file) | |
3342 | { | |
3343 | struct drm_device *dev = inode->i_private; | |
3344 | ||
9ad0257c | 3345 | if (HAS_GMCH_DISPLAY(dev)) |
369a1342 VS |
3346 | return -ENODEV; |
3347 | ||
3348 | return single_open(file, spr_wm_latency_show, dev); | |
3349 | } | |
3350 | ||
3351 | static int cur_wm_latency_open(struct inode *inode, struct file *file) | |
3352 | { | |
3353 | struct drm_device *dev = inode->i_private; | |
3354 | ||
9ad0257c | 3355 | if (HAS_GMCH_DISPLAY(dev)) |
369a1342 VS |
3356 | return -ENODEV; |
3357 | ||
3358 | return single_open(file, cur_wm_latency_show, dev); | |
3359 | } | |
3360 | ||
3361 | static ssize_t wm_latency_write(struct file *file, const char __user *ubuf, | |
3362 | size_t len, loff_t *offp, uint16_t wm[5]) | |
3363 | { | |
3364 | struct seq_file *m = file->private_data; | |
3365 | struct drm_device *dev = m->private; | |
3366 | uint16_t new[5] = { 0 }; | |
546c81fd | 3367 | int num_levels = ilk_wm_max_level(dev) + 1; |
369a1342 VS |
3368 | int level; |
3369 | int ret; | |
3370 | char tmp[32]; | |
3371 | ||
3372 | if (len >= sizeof(tmp)) | |
3373 | return -EINVAL; | |
3374 | ||
3375 | if (copy_from_user(tmp, ubuf, len)) | |
3376 | return -EFAULT; | |
3377 | ||
3378 | tmp[len] = '\0'; | |
3379 | ||
3380 | ret = sscanf(tmp, "%hu %hu %hu %hu %hu", &new[0], &new[1], &new[2], &new[3], &new[4]); | |
3381 | if (ret != num_levels) | |
3382 | return -EINVAL; | |
3383 | ||
3384 | drm_modeset_lock_all(dev); | |
3385 | ||
3386 | for (level = 0; level < num_levels; level++) | |
3387 | wm[level] = new[level]; | |
3388 | ||
3389 | drm_modeset_unlock_all(dev); | |
3390 | ||
3391 | return len; | |
3392 | } | |
3393 | ||
3394 | ||
3395 | static ssize_t pri_wm_latency_write(struct file *file, const char __user *ubuf, | |
3396 | size_t len, loff_t *offp) | |
3397 | { | |
3398 | struct seq_file *m = file->private_data; | |
3399 | struct drm_device *dev = m->private; | |
3400 | ||
3401 | return wm_latency_write(file, ubuf, len, offp, to_i915(dev)->wm.pri_latency); | |
3402 | } | |
3403 | ||
3404 | static ssize_t spr_wm_latency_write(struct file *file, const char __user *ubuf, | |
3405 | size_t len, loff_t *offp) | |
3406 | { | |
3407 | struct seq_file *m = file->private_data; | |
3408 | struct drm_device *dev = m->private; | |
3409 | ||
3410 | return wm_latency_write(file, ubuf, len, offp, to_i915(dev)->wm.spr_latency); | |
3411 | } | |
3412 | ||
3413 | static ssize_t cur_wm_latency_write(struct file *file, const char __user *ubuf, | |
3414 | size_t len, loff_t *offp) | |
3415 | { | |
3416 | struct seq_file *m = file->private_data; | |
3417 | struct drm_device *dev = m->private; | |
3418 | ||
3419 | return wm_latency_write(file, ubuf, len, offp, to_i915(dev)->wm.cur_latency); | |
3420 | } | |
3421 | ||
3422 | static const struct file_operations i915_pri_wm_latency_fops = { | |
3423 | .owner = THIS_MODULE, | |
3424 | .open = pri_wm_latency_open, | |
3425 | .read = seq_read, | |
3426 | .llseek = seq_lseek, | |
3427 | .release = single_release, | |
3428 | .write = pri_wm_latency_write | |
3429 | }; | |
3430 | ||
3431 | static const struct file_operations i915_spr_wm_latency_fops = { | |
3432 | .owner = THIS_MODULE, | |
3433 | .open = spr_wm_latency_open, | |
3434 | .read = seq_read, | |
3435 | .llseek = seq_lseek, | |
3436 | .release = single_release, | |
3437 | .write = spr_wm_latency_write | |
3438 | }; | |
3439 | ||
3440 | static const struct file_operations i915_cur_wm_latency_fops = { | |
3441 | .owner = THIS_MODULE, | |
3442 | .open = cur_wm_latency_open, | |
3443 | .read = seq_read, | |
3444 | .llseek = seq_lseek, | |
3445 | .release = single_release, | |
3446 | .write = cur_wm_latency_write | |
3447 | }; | |
3448 | ||
647416f9 KC |
3449 | static int |
3450 | i915_wedged_get(void *data, u64 *val) | |
f3cd474b | 3451 | { |
647416f9 | 3452 | struct drm_device *dev = data; |
e277a1f8 | 3453 | struct drm_i915_private *dev_priv = dev->dev_private; |
f3cd474b | 3454 | |
647416f9 | 3455 | *val = atomic_read(&dev_priv->gpu_error.reset_counter); |
f3cd474b | 3456 | |
647416f9 | 3457 | return 0; |
f3cd474b CW |
3458 | } |
3459 | ||
647416f9 KC |
3460 | static int |
3461 | i915_wedged_set(void *data, u64 val) | |
f3cd474b | 3462 | { |
647416f9 | 3463 | struct drm_device *dev = data; |
d46c0517 ID |
3464 | struct drm_i915_private *dev_priv = dev->dev_private; |
3465 | ||
3466 | intel_runtime_pm_get(dev_priv); | |
f3cd474b | 3467 | |
58174462 MK |
3468 | i915_handle_error(dev, val, |
3469 | "Manually setting wedged to %llu", val); | |
d46c0517 ID |
3470 | |
3471 | intel_runtime_pm_put(dev_priv); | |
3472 | ||
647416f9 | 3473 | return 0; |
f3cd474b CW |
3474 | } |
3475 | ||
647416f9 KC |
3476 | DEFINE_SIMPLE_ATTRIBUTE(i915_wedged_fops, |
3477 | i915_wedged_get, i915_wedged_set, | |
3a3b4f98 | 3478 | "%llu\n"); |
f3cd474b | 3479 | |
647416f9 KC |
3480 | static int |
3481 | i915_ring_stop_get(void *data, u64 *val) | |
e5eb3d63 | 3482 | { |
647416f9 | 3483 | struct drm_device *dev = data; |
e277a1f8 | 3484 | struct drm_i915_private *dev_priv = dev->dev_private; |
e5eb3d63 | 3485 | |
647416f9 | 3486 | *val = dev_priv->gpu_error.stop_rings; |
e5eb3d63 | 3487 | |
647416f9 | 3488 | return 0; |
e5eb3d63 DV |
3489 | } |
3490 | ||
647416f9 KC |
3491 | static int |
3492 | i915_ring_stop_set(void *data, u64 val) | |
e5eb3d63 | 3493 | { |
647416f9 | 3494 | struct drm_device *dev = data; |
e5eb3d63 | 3495 | struct drm_i915_private *dev_priv = dev->dev_private; |
647416f9 | 3496 | int ret; |
e5eb3d63 | 3497 | |
647416f9 | 3498 | DRM_DEBUG_DRIVER("Stopping rings 0x%08llx\n", val); |
e5eb3d63 | 3499 | |
22bcfc6a DV |
3500 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
3501 | if (ret) | |
3502 | return ret; | |
3503 | ||
99584db3 | 3504 | dev_priv->gpu_error.stop_rings = val; |
e5eb3d63 DV |
3505 | mutex_unlock(&dev->struct_mutex); |
3506 | ||
647416f9 | 3507 | return 0; |
e5eb3d63 DV |
3508 | } |
3509 | ||
647416f9 KC |
3510 | DEFINE_SIMPLE_ATTRIBUTE(i915_ring_stop_fops, |
3511 | i915_ring_stop_get, i915_ring_stop_set, | |
3512 | "0x%08llx\n"); | |
d5442303 | 3513 | |
094f9a54 CW |
3514 | static int |
3515 | i915_ring_missed_irq_get(void *data, u64 *val) | |
3516 | { | |
3517 | struct drm_device *dev = data; | |
3518 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3519 | ||
3520 | *val = dev_priv->gpu_error.missed_irq_rings; | |
3521 | return 0; | |
3522 | } | |
3523 | ||
3524 | static int | |
3525 | i915_ring_missed_irq_set(void *data, u64 val) | |
3526 | { | |
3527 | struct drm_device *dev = data; | |
3528 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3529 | int ret; | |
3530 | ||
3531 | /* Lock against concurrent debugfs callers */ | |
3532 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
3533 | if (ret) | |
3534 | return ret; | |
3535 | dev_priv->gpu_error.missed_irq_rings = val; | |
3536 | mutex_unlock(&dev->struct_mutex); | |
3537 | ||
3538 | return 0; | |
3539 | } | |
3540 | ||
3541 | DEFINE_SIMPLE_ATTRIBUTE(i915_ring_missed_irq_fops, | |
3542 | i915_ring_missed_irq_get, i915_ring_missed_irq_set, | |
3543 | "0x%08llx\n"); | |
3544 | ||
3545 | static int | |
3546 | i915_ring_test_irq_get(void *data, u64 *val) | |
3547 | { | |
3548 | struct drm_device *dev = data; | |
3549 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3550 | ||
3551 | *val = dev_priv->gpu_error.test_irq_rings; | |
3552 | ||
3553 | return 0; | |
3554 | } | |
3555 | ||
3556 | static int | |
3557 | i915_ring_test_irq_set(void *data, u64 val) | |
3558 | { | |
3559 | struct drm_device *dev = data; | |
3560 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3561 | int ret; | |
3562 | ||
3563 | DRM_DEBUG_DRIVER("Masking interrupts on rings 0x%08llx\n", val); | |
3564 | ||
3565 | /* Lock against concurrent debugfs callers */ | |
3566 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
3567 | if (ret) | |
3568 | return ret; | |
3569 | ||
3570 | dev_priv->gpu_error.test_irq_rings = val; | |
3571 | mutex_unlock(&dev->struct_mutex); | |
3572 | ||
3573 | return 0; | |
3574 | } | |
3575 | ||
3576 | DEFINE_SIMPLE_ATTRIBUTE(i915_ring_test_irq_fops, | |
3577 | i915_ring_test_irq_get, i915_ring_test_irq_set, | |
3578 | "0x%08llx\n"); | |
3579 | ||
dd624afd CW |
3580 | #define DROP_UNBOUND 0x1 |
3581 | #define DROP_BOUND 0x2 | |
3582 | #define DROP_RETIRE 0x4 | |
3583 | #define DROP_ACTIVE 0x8 | |
3584 | #define DROP_ALL (DROP_UNBOUND | \ | |
3585 | DROP_BOUND | \ | |
3586 | DROP_RETIRE | \ | |
3587 | DROP_ACTIVE) | |
647416f9 KC |
3588 | static int |
3589 | i915_drop_caches_get(void *data, u64 *val) | |
dd624afd | 3590 | { |
647416f9 | 3591 | *val = DROP_ALL; |
dd624afd | 3592 | |
647416f9 | 3593 | return 0; |
dd624afd CW |
3594 | } |
3595 | ||
647416f9 KC |
3596 | static int |
3597 | i915_drop_caches_set(void *data, u64 val) | |
dd624afd | 3598 | { |
647416f9 | 3599 | struct drm_device *dev = data; |
dd624afd CW |
3600 | struct drm_i915_private *dev_priv = dev->dev_private; |
3601 | struct drm_i915_gem_object *obj, *next; | |
ca191b13 BW |
3602 | struct i915_address_space *vm; |
3603 | struct i915_vma *vma, *x; | |
647416f9 | 3604 | int ret; |
dd624afd | 3605 | |
2f9fe5ff | 3606 | DRM_DEBUG("Dropping caches: 0x%08llx\n", val); |
dd624afd CW |
3607 | |
3608 | /* No need to check and wait for gpu resets, only libdrm auto-restarts | |
3609 | * on ioctls on -EAGAIN. */ | |
3610 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
3611 | if (ret) | |
3612 | return ret; | |
3613 | ||
3614 | if (val & DROP_ACTIVE) { | |
3615 | ret = i915_gpu_idle(dev); | |
3616 | if (ret) | |
3617 | goto unlock; | |
3618 | } | |
3619 | ||
3620 | if (val & (DROP_RETIRE | DROP_ACTIVE)) | |
3621 | i915_gem_retire_requests(dev); | |
3622 | ||
3623 | if (val & DROP_BOUND) { | |
ca191b13 BW |
3624 | list_for_each_entry(vm, &dev_priv->vm_list, global_link) { |
3625 | list_for_each_entry_safe(vma, x, &vm->inactive_list, | |
3626 | mm_list) { | |
d7f46fc4 | 3627 | if (vma->pin_count) |
ca191b13 BW |
3628 | continue; |
3629 | ||
3630 | ret = i915_vma_unbind(vma); | |
3631 | if (ret) | |
3632 | goto unlock; | |
3633 | } | |
31a46c9c | 3634 | } |
dd624afd CW |
3635 | } |
3636 | ||
3637 | if (val & DROP_UNBOUND) { | |
35c20a60 BW |
3638 | list_for_each_entry_safe(obj, next, &dev_priv->mm.unbound_list, |
3639 | global_list) | |
dd624afd CW |
3640 | if (obj->pages_pin_count == 0) { |
3641 | ret = i915_gem_object_put_pages(obj); | |
3642 | if (ret) | |
3643 | goto unlock; | |
3644 | } | |
3645 | } | |
3646 | ||
3647 | unlock: | |
3648 | mutex_unlock(&dev->struct_mutex); | |
3649 | ||
647416f9 | 3650 | return ret; |
dd624afd CW |
3651 | } |
3652 | ||
647416f9 KC |
3653 | DEFINE_SIMPLE_ATTRIBUTE(i915_drop_caches_fops, |
3654 | i915_drop_caches_get, i915_drop_caches_set, | |
3655 | "0x%08llx\n"); | |
dd624afd | 3656 | |
647416f9 KC |
3657 | static int |
3658 | i915_max_freq_get(void *data, u64 *val) | |
358733e9 | 3659 | { |
647416f9 | 3660 | struct drm_device *dev = data; |
e277a1f8 | 3661 | struct drm_i915_private *dev_priv = dev->dev_private; |
647416f9 | 3662 | int ret; |
004777cb | 3663 | |
daa3afb2 | 3664 | if (INTEL_INFO(dev)->gen < 6) |
004777cb DV |
3665 | return -ENODEV; |
3666 | ||
5c9669ce TR |
3667 | flush_delayed_work(&dev_priv->rps.delayed_resume_work); |
3668 | ||
4fc688ce | 3669 | ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock); |
004777cb DV |
3670 | if (ret) |
3671 | return ret; | |
358733e9 | 3672 | |
0a073b84 | 3673 | if (IS_VALLEYVIEW(dev)) |
b39fb297 | 3674 | *val = vlv_gpu_freq(dev_priv, dev_priv->rps.max_freq_softlimit); |
0a073b84 | 3675 | else |
b39fb297 | 3676 | *val = dev_priv->rps.max_freq_softlimit * GT_FREQUENCY_MULTIPLIER; |
4fc688ce | 3677 | mutex_unlock(&dev_priv->rps.hw_lock); |
358733e9 | 3678 | |
647416f9 | 3679 | return 0; |
358733e9 JB |
3680 | } |
3681 | ||
647416f9 KC |
3682 | static int |
3683 | i915_max_freq_set(void *data, u64 val) | |
358733e9 | 3684 | { |
647416f9 | 3685 | struct drm_device *dev = data; |
358733e9 | 3686 | struct drm_i915_private *dev_priv = dev->dev_private; |
dd0a1aa1 | 3687 | u32 rp_state_cap, hw_max, hw_min; |
647416f9 | 3688 | int ret; |
004777cb | 3689 | |
daa3afb2 | 3690 | if (INTEL_INFO(dev)->gen < 6) |
004777cb | 3691 | return -ENODEV; |
358733e9 | 3692 | |
5c9669ce TR |
3693 | flush_delayed_work(&dev_priv->rps.delayed_resume_work); |
3694 | ||
647416f9 | 3695 | DRM_DEBUG_DRIVER("Manually setting max freq to %llu\n", val); |
358733e9 | 3696 | |
4fc688ce | 3697 | ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock); |
004777cb DV |
3698 | if (ret) |
3699 | return ret; | |
3700 | ||
358733e9 JB |
3701 | /* |
3702 | * Turbo will still be enabled, but won't go above the set value. | |
3703 | */ | |
0a073b84 | 3704 | if (IS_VALLEYVIEW(dev)) { |
2ec3815f | 3705 | val = vlv_freq_opcode(dev_priv, val); |
dd0a1aa1 | 3706 | |
03af2045 VS |
3707 | hw_max = dev_priv->rps.max_freq; |
3708 | hw_min = dev_priv->rps.min_freq; | |
0a073b84 JB |
3709 | } else { |
3710 | do_div(val, GT_FREQUENCY_MULTIPLIER); | |
dd0a1aa1 JM |
3711 | |
3712 | rp_state_cap = I915_READ(GEN6_RP_STATE_CAP); | |
b39fb297 | 3713 | hw_max = dev_priv->rps.max_freq; |
dd0a1aa1 JM |
3714 | hw_min = (rp_state_cap >> 16) & 0xff; |
3715 | } | |
3716 | ||
b39fb297 | 3717 | if (val < hw_min || val > hw_max || val < dev_priv->rps.min_freq_softlimit) { |
dd0a1aa1 JM |
3718 | mutex_unlock(&dev_priv->rps.hw_lock); |
3719 | return -EINVAL; | |
0a073b84 JB |
3720 | } |
3721 | ||
b39fb297 | 3722 | dev_priv->rps.max_freq_softlimit = val; |
dd0a1aa1 JM |
3723 | |
3724 | if (IS_VALLEYVIEW(dev)) | |
3725 | valleyview_set_rps(dev, val); | |
3726 | else | |
3727 | gen6_set_rps(dev, val); | |
3728 | ||
4fc688ce | 3729 | mutex_unlock(&dev_priv->rps.hw_lock); |
358733e9 | 3730 | |
647416f9 | 3731 | return 0; |
358733e9 JB |
3732 | } |
3733 | ||
647416f9 KC |
3734 | DEFINE_SIMPLE_ATTRIBUTE(i915_max_freq_fops, |
3735 | i915_max_freq_get, i915_max_freq_set, | |
3a3b4f98 | 3736 | "%llu\n"); |
358733e9 | 3737 | |
647416f9 KC |
3738 | static int |
3739 | i915_min_freq_get(void *data, u64 *val) | |
1523c310 | 3740 | { |
647416f9 | 3741 | struct drm_device *dev = data; |
e277a1f8 | 3742 | struct drm_i915_private *dev_priv = dev->dev_private; |
647416f9 | 3743 | int ret; |
004777cb | 3744 | |
daa3afb2 | 3745 | if (INTEL_INFO(dev)->gen < 6) |
004777cb DV |
3746 | return -ENODEV; |
3747 | ||
5c9669ce TR |
3748 | flush_delayed_work(&dev_priv->rps.delayed_resume_work); |
3749 | ||
4fc688ce | 3750 | ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock); |
004777cb DV |
3751 | if (ret) |
3752 | return ret; | |
1523c310 | 3753 | |
0a073b84 | 3754 | if (IS_VALLEYVIEW(dev)) |
b39fb297 | 3755 | *val = vlv_gpu_freq(dev_priv, dev_priv->rps.min_freq_softlimit); |
0a073b84 | 3756 | else |
b39fb297 | 3757 | *val = dev_priv->rps.min_freq_softlimit * GT_FREQUENCY_MULTIPLIER; |
4fc688ce | 3758 | mutex_unlock(&dev_priv->rps.hw_lock); |
1523c310 | 3759 | |
647416f9 | 3760 | return 0; |
1523c310 JB |
3761 | } |
3762 | ||
647416f9 KC |
3763 | static int |
3764 | i915_min_freq_set(void *data, u64 val) | |
1523c310 | 3765 | { |
647416f9 | 3766 | struct drm_device *dev = data; |
1523c310 | 3767 | struct drm_i915_private *dev_priv = dev->dev_private; |
dd0a1aa1 | 3768 | u32 rp_state_cap, hw_max, hw_min; |
647416f9 | 3769 | int ret; |
004777cb | 3770 | |
daa3afb2 | 3771 | if (INTEL_INFO(dev)->gen < 6) |
004777cb | 3772 | return -ENODEV; |
1523c310 | 3773 | |
5c9669ce TR |
3774 | flush_delayed_work(&dev_priv->rps.delayed_resume_work); |
3775 | ||
647416f9 | 3776 | DRM_DEBUG_DRIVER("Manually setting min freq to %llu\n", val); |
1523c310 | 3777 | |
4fc688ce | 3778 | ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock); |
004777cb DV |
3779 | if (ret) |
3780 | return ret; | |
3781 | ||
1523c310 JB |
3782 | /* |
3783 | * Turbo will still be enabled, but won't go below the set value. | |
3784 | */ | |
0a073b84 | 3785 | if (IS_VALLEYVIEW(dev)) { |
2ec3815f | 3786 | val = vlv_freq_opcode(dev_priv, val); |
dd0a1aa1 | 3787 | |
03af2045 VS |
3788 | hw_max = dev_priv->rps.max_freq; |
3789 | hw_min = dev_priv->rps.min_freq; | |
0a073b84 JB |
3790 | } else { |
3791 | do_div(val, GT_FREQUENCY_MULTIPLIER); | |
dd0a1aa1 JM |
3792 | |
3793 | rp_state_cap = I915_READ(GEN6_RP_STATE_CAP); | |
b39fb297 | 3794 | hw_max = dev_priv->rps.max_freq; |
dd0a1aa1 JM |
3795 | hw_min = (rp_state_cap >> 16) & 0xff; |
3796 | } | |
3797 | ||
b39fb297 | 3798 | if (val < hw_min || val > hw_max || val > dev_priv->rps.max_freq_softlimit) { |
dd0a1aa1 JM |
3799 | mutex_unlock(&dev_priv->rps.hw_lock); |
3800 | return -EINVAL; | |
0a073b84 | 3801 | } |
dd0a1aa1 | 3802 | |
b39fb297 | 3803 | dev_priv->rps.min_freq_softlimit = val; |
dd0a1aa1 JM |
3804 | |
3805 | if (IS_VALLEYVIEW(dev)) | |
3806 | valleyview_set_rps(dev, val); | |
3807 | else | |
3808 | gen6_set_rps(dev, val); | |
3809 | ||
4fc688ce | 3810 | mutex_unlock(&dev_priv->rps.hw_lock); |
1523c310 | 3811 | |
647416f9 | 3812 | return 0; |
1523c310 JB |
3813 | } |
3814 | ||
647416f9 KC |
3815 | DEFINE_SIMPLE_ATTRIBUTE(i915_min_freq_fops, |
3816 | i915_min_freq_get, i915_min_freq_set, | |
3a3b4f98 | 3817 | "%llu\n"); |
1523c310 | 3818 | |
647416f9 KC |
3819 | static int |
3820 | i915_cache_sharing_get(void *data, u64 *val) | |
07b7ddd9 | 3821 | { |
647416f9 | 3822 | struct drm_device *dev = data; |
e277a1f8 | 3823 | struct drm_i915_private *dev_priv = dev->dev_private; |
07b7ddd9 | 3824 | u32 snpcr; |
647416f9 | 3825 | int ret; |
07b7ddd9 | 3826 | |
004777cb DV |
3827 | if (!(IS_GEN6(dev) || IS_GEN7(dev))) |
3828 | return -ENODEV; | |
3829 | ||
22bcfc6a DV |
3830 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
3831 | if (ret) | |
3832 | return ret; | |
c8c8fb33 | 3833 | intel_runtime_pm_get(dev_priv); |
22bcfc6a | 3834 | |
07b7ddd9 | 3835 | snpcr = I915_READ(GEN6_MBCUNIT_SNPCR); |
c8c8fb33 PZ |
3836 | |
3837 | intel_runtime_pm_put(dev_priv); | |
07b7ddd9 JB |
3838 | mutex_unlock(&dev_priv->dev->struct_mutex); |
3839 | ||
647416f9 | 3840 | *val = (snpcr & GEN6_MBC_SNPCR_MASK) >> GEN6_MBC_SNPCR_SHIFT; |
07b7ddd9 | 3841 | |
647416f9 | 3842 | return 0; |
07b7ddd9 JB |
3843 | } |
3844 | ||
647416f9 KC |
3845 | static int |
3846 | i915_cache_sharing_set(void *data, u64 val) | |
07b7ddd9 | 3847 | { |
647416f9 | 3848 | struct drm_device *dev = data; |
07b7ddd9 | 3849 | struct drm_i915_private *dev_priv = dev->dev_private; |
07b7ddd9 | 3850 | u32 snpcr; |
07b7ddd9 | 3851 | |
004777cb DV |
3852 | if (!(IS_GEN6(dev) || IS_GEN7(dev))) |
3853 | return -ENODEV; | |
3854 | ||
647416f9 | 3855 | if (val > 3) |
07b7ddd9 JB |
3856 | return -EINVAL; |
3857 | ||
c8c8fb33 | 3858 | intel_runtime_pm_get(dev_priv); |
647416f9 | 3859 | DRM_DEBUG_DRIVER("Manually setting uncore sharing to %llu\n", val); |
07b7ddd9 JB |
3860 | |
3861 | /* Update the cache sharing policy here as well */ | |
3862 | snpcr = I915_READ(GEN6_MBCUNIT_SNPCR); | |
3863 | snpcr &= ~GEN6_MBC_SNPCR_MASK; | |
3864 | snpcr |= (val << GEN6_MBC_SNPCR_SHIFT); | |
3865 | I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr); | |
3866 | ||
c8c8fb33 | 3867 | intel_runtime_pm_put(dev_priv); |
647416f9 | 3868 | return 0; |
07b7ddd9 JB |
3869 | } |
3870 | ||
647416f9 KC |
3871 | DEFINE_SIMPLE_ATTRIBUTE(i915_cache_sharing_fops, |
3872 | i915_cache_sharing_get, i915_cache_sharing_set, | |
3873 | "%llu\n"); | |
07b7ddd9 | 3874 | |
6d794d42 BW |
3875 | static int i915_forcewake_open(struct inode *inode, struct file *file) |
3876 | { | |
3877 | struct drm_device *dev = inode->i_private; | |
3878 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6d794d42 | 3879 | |
075edca4 | 3880 | if (INTEL_INFO(dev)->gen < 6) |
6d794d42 BW |
3881 | return 0; |
3882 | ||
c8d9a590 | 3883 | gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL); |
6d794d42 BW |
3884 | |
3885 | return 0; | |
3886 | } | |
3887 | ||
c43b5634 | 3888 | static int i915_forcewake_release(struct inode *inode, struct file *file) |
6d794d42 BW |
3889 | { |
3890 | struct drm_device *dev = inode->i_private; | |
3891 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3892 | ||
075edca4 | 3893 | if (INTEL_INFO(dev)->gen < 6) |
6d794d42 BW |
3894 | return 0; |
3895 | ||
c8d9a590 | 3896 | gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL); |
6d794d42 BW |
3897 | |
3898 | return 0; | |
3899 | } | |
3900 | ||
3901 | static const struct file_operations i915_forcewake_fops = { | |
3902 | .owner = THIS_MODULE, | |
3903 | .open = i915_forcewake_open, | |
3904 | .release = i915_forcewake_release, | |
3905 | }; | |
3906 | ||
3907 | static int i915_forcewake_create(struct dentry *root, struct drm_minor *minor) | |
3908 | { | |
3909 | struct drm_device *dev = minor->dev; | |
3910 | struct dentry *ent; | |
3911 | ||
3912 | ent = debugfs_create_file("i915_forcewake_user", | |
8eb57294 | 3913 | S_IRUSR, |
6d794d42 BW |
3914 | root, dev, |
3915 | &i915_forcewake_fops); | |
f3c5fe97 WY |
3916 | if (!ent) |
3917 | return -ENOMEM; | |
6d794d42 | 3918 | |
8eb57294 | 3919 | return drm_add_fake_info_node(minor, ent, &i915_forcewake_fops); |
6d794d42 BW |
3920 | } |
3921 | ||
6a9c308d DV |
3922 | static int i915_debugfs_create(struct dentry *root, |
3923 | struct drm_minor *minor, | |
3924 | const char *name, | |
3925 | const struct file_operations *fops) | |
07b7ddd9 JB |
3926 | { |
3927 | struct drm_device *dev = minor->dev; | |
3928 | struct dentry *ent; | |
3929 | ||
6a9c308d | 3930 | ent = debugfs_create_file(name, |
07b7ddd9 JB |
3931 | S_IRUGO | S_IWUSR, |
3932 | root, dev, | |
6a9c308d | 3933 | fops); |
f3c5fe97 WY |
3934 | if (!ent) |
3935 | return -ENOMEM; | |
07b7ddd9 | 3936 | |
6a9c308d | 3937 | return drm_add_fake_info_node(minor, ent, fops); |
07b7ddd9 JB |
3938 | } |
3939 | ||
06c5bf8c | 3940 | static const struct drm_info_list i915_debugfs_list[] = { |
311bd68e | 3941 | {"i915_capabilities", i915_capabilities, 0}, |
73aa808f | 3942 | {"i915_gem_objects", i915_gem_object_info, 0}, |
08c18323 | 3943 | {"i915_gem_gtt", i915_gem_gtt_info, 0}, |
1b50247a | 3944 | {"i915_gem_pinned", i915_gem_gtt_info, 0, (void *) PINNED_LIST}, |
433e12f7 | 3945 | {"i915_gem_active", i915_gem_object_list_info, 0, (void *) ACTIVE_LIST}, |
433e12f7 | 3946 | {"i915_gem_inactive", i915_gem_object_list_info, 0, (void *) INACTIVE_LIST}, |
6d2b8885 | 3947 | {"i915_gem_stolen", i915_gem_stolen_list_info }, |
4e5359cd | 3948 | {"i915_gem_pageflip", i915_gem_pageflip_info, 0}, |
2017263e BG |
3949 | {"i915_gem_request", i915_gem_request_info, 0}, |
3950 | {"i915_gem_seqno", i915_gem_seqno_info, 0}, | |
a6172a80 | 3951 | {"i915_gem_fence_regs", i915_gem_fence_regs_info, 0}, |
2017263e | 3952 | {"i915_gem_interrupt", i915_interrupt_info, 0}, |
1ec14ad3 CW |
3953 | {"i915_gem_hws", i915_hws_info, 0, (void *)RCS}, |
3954 | {"i915_gem_hws_blt", i915_hws_info, 0, (void *)BCS}, | |
3955 | {"i915_gem_hws_bsd", i915_hws_info, 0, (void *)VCS}, | |
9010ebfd | 3956 | {"i915_gem_hws_vebox", i915_hws_info, 0, (void *)VECS}, |
adb4bd12 | 3957 | {"i915_frequency_info", i915_frequency_info, 0}, |
f97108d1 | 3958 | {"i915_drpc_info", i915_drpc_info, 0}, |
7648fa99 | 3959 | {"i915_emon_status", i915_emon_status, 0}, |
23b2f8bb | 3960 | {"i915_ring_freq_table", i915_ring_freq_table, 0}, |
b5e50c3f | 3961 | {"i915_fbc_status", i915_fbc_status, 0}, |
92d44621 | 3962 | {"i915_ips_status", i915_ips_status, 0}, |
4a9bef37 | 3963 | {"i915_sr_status", i915_sr_status, 0}, |
44834a67 | 3964 | {"i915_opregion", i915_opregion, 0}, |
37811fcc | 3965 | {"i915_gem_framebuffer", i915_gem_framebuffer_info, 0}, |
e76d3630 | 3966 | {"i915_context_status", i915_context_status, 0}, |
6d794d42 | 3967 | {"i915_gen6_forcewake_count", i915_gen6_forcewake_count_info, 0}, |
ea16a3cd | 3968 | {"i915_swizzle_info", i915_swizzle_info, 0}, |
3cf17fc5 | 3969 | {"i915_ppgtt_info", i915_ppgtt_info, 0}, |
63573eb7 | 3970 | {"i915_llc", i915_llc, 0}, |
e91fd8c6 | 3971 | {"i915_edp_psr_status", i915_edp_psr_status, 0}, |
d2e216d0 | 3972 | {"i915_sink_crc_eDP1", i915_sink_crc, 0}, |
ec013e7f | 3973 | {"i915_energy_uJ", i915_energy_uJ, 0}, |
371db66a | 3974 | {"i915_pc8_status", i915_pc8_status, 0}, |
1da51581 | 3975 | {"i915_power_domain_info", i915_power_domain_info, 0}, |
53f5e3ca | 3976 | {"i915_display_info", i915_display_info, 0}, |
e04934cf | 3977 | {"i915_semaphore_status", i915_semaphore_status, 0}, |
728e29d7 | 3978 | {"i915_shared_dplls_info", i915_shared_dplls_info, 0}, |
11bed958 | 3979 | {"i915_dp_mst_info", i915_dp_mst_info, 0}, |
2017263e | 3980 | }; |
27c202ad | 3981 | #define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list) |
2017263e | 3982 | |
06c5bf8c | 3983 | static const struct i915_debugfs_files { |
34b9674c DV |
3984 | const char *name; |
3985 | const struct file_operations *fops; | |
3986 | } i915_debugfs_files[] = { | |
3987 | {"i915_wedged", &i915_wedged_fops}, | |
3988 | {"i915_max_freq", &i915_max_freq_fops}, | |
3989 | {"i915_min_freq", &i915_min_freq_fops}, | |
3990 | {"i915_cache_sharing", &i915_cache_sharing_fops}, | |
3991 | {"i915_ring_stop", &i915_ring_stop_fops}, | |
094f9a54 CW |
3992 | {"i915_ring_missed_irq", &i915_ring_missed_irq_fops}, |
3993 | {"i915_ring_test_irq", &i915_ring_test_irq_fops}, | |
34b9674c DV |
3994 | {"i915_gem_drop_caches", &i915_drop_caches_fops}, |
3995 | {"i915_error_state", &i915_error_state_fops}, | |
3996 | {"i915_next_seqno", &i915_next_seqno_fops}, | |
bd9db02f | 3997 | {"i915_display_crc_ctl", &i915_display_crc_ctl_fops}, |
369a1342 VS |
3998 | {"i915_pri_wm_latency", &i915_pri_wm_latency_fops}, |
3999 | {"i915_spr_wm_latency", &i915_spr_wm_latency_fops}, | |
4000 | {"i915_cur_wm_latency", &i915_cur_wm_latency_fops}, | |
da46f936 | 4001 | {"i915_fbc_false_color", &i915_fbc_fc_fops}, |
34b9674c DV |
4002 | }; |
4003 | ||
07144428 DL |
4004 | void intel_display_crc_init(struct drm_device *dev) |
4005 | { | |
4006 | struct drm_i915_private *dev_priv = dev->dev_private; | |
b378360e | 4007 | enum pipe pipe; |
07144428 | 4008 | |
b378360e DV |
4009 | for_each_pipe(pipe) { |
4010 | struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe]; | |
07144428 | 4011 | |
d538bbdf DL |
4012 | pipe_crc->opened = false; |
4013 | spin_lock_init(&pipe_crc->lock); | |
07144428 DL |
4014 | init_waitqueue_head(&pipe_crc->wq); |
4015 | } | |
4016 | } | |
4017 | ||
27c202ad | 4018 | int i915_debugfs_init(struct drm_minor *minor) |
2017263e | 4019 | { |
34b9674c | 4020 | int ret, i; |
f3cd474b | 4021 | |
6d794d42 | 4022 | ret = i915_forcewake_create(minor->debugfs_root, minor); |
358733e9 JB |
4023 | if (ret) |
4024 | return ret; | |
6a9c308d | 4025 | |
07144428 DL |
4026 | for (i = 0; i < ARRAY_SIZE(i915_pipe_crc_data); i++) { |
4027 | ret = i915_pipe_crc_create(minor->debugfs_root, minor, i); | |
4028 | if (ret) | |
4029 | return ret; | |
4030 | } | |
4031 | ||
34b9674c DV |
4032 | for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) { |
4033 | ret = i915_debugfs_create(minor->debugfs_root, minor, | |
4034 | i915_debugfs_files[i].name, | |
4035 | i915_debugfs_files[i].fops); | |
4036 | if (ret) | |
4037 | return ret; | |
4038 | } | |
40633219 | 4039 | |
27c202ad BG |
4040 | return drm_debugfs_create_files(i915_debugfs_list, |
4041 | I915_DEBUGFS_ENTRIES, | |
2017263e BG |
4042 | minor->debugfs_root, minor); |
4043 | } | |
4044 | ||
27c202ad | 4045 | void i915_debugfs_cleanup(struct drm_minor *minor) |
2017263e | 4046 | { |
34b9674c DV |
4047 | int i; |
4048 | ||
27c202ad BG |
4049 | drm_debugfs_remove_files(i915_debugfs_list, |
4050 | I915_DEBUGFS_ENTRIES, minor); | |
07144428 | 4051 | |
6d794d42 BW |
4052 | drm_debugfs_remove_files((struct drm_info_list *) &i915_forcewake_fops, |
4053 | 1, minor); | |
07144428 | 4054 | |
e309a997 | 4055 | for (i = 0; i < ARRAY_SIZE(i915_pipe_crc_data); i++) { |
07144428 DL |
4056 | struct drm_info_list *info_list = |
4057 | (struct drm_info_list *)&i915_pipe_crc_data[i]; | |
4058 | ||
4059 | drm_debugfs_remove_files(info_list, 1, minor); | |
4060 | } | |
4061 | ||
34b9674c DV |
4062 | for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) { |
4063 | struct drm_info_list *info_list = | |
4064 | (struct drm_info_list *) i915_debugfs_files[i].fops; | |
4065 | ||
4066 | drm_debugfs_remove_files(info_list, 1, minor); | |
4067 | } | |
2017263e | 4068 | } |