Commit | Line | Data |
---|---|---|
2017263e BG |
1 | /* |
2 | * Copyright © 2008 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | * Keith Packard <keithp@keithp.com> | |
26 | * | |
27 | */ | |
28 | ||
29 | #include <linux/seq_file.h> | |
f3cd474b | 30 | #include <linux/debugfs.h> |
5a0e3ad6 | 31 | #include <linux/slab.h> |
2d1a8a48 | 32 | #include <linux/export.h> |
4518f611 | 33 | #include <generated/utsrelease.h> |
760285e7 | 34 | #include <drm/drmP.h> |
4e5359cd | 35 | #include "intel_drv.h" |
e5c65260 | 36 | #include "intel_ringbuffer.h" |
760285e7 | 37 | #include <drm/i915_drm.h> |
2017263e BG |
38 | #include "i915_drv.h" |
39 | ||
40 | #define DRM_I915_RING_DEBUG 1 | |
41 | ||
42 | ||
43 | #if defined(CONFIG_DEBUG_FS) | |
44 | ||
f13d3f73 | 45 | enum { |
69dc4987 | 46 | ACTIVE_LIST, |
f13d3f73 | 47 | INACTIVE_LIST, |
d21d5975 | 48 | PINNED_LIST, |
f13d3f73 | 49 | }; |
2017263e | 50 | |
70d39fe4 CW |
51 | static const char *yesno(int v) |
52 | { | |
53 | return v ? "yes" : "no"; | |
54 | } | |
55 | ||
56 | static int i915_capabilities(struct seq_file *m, void *data) | |
57 | { | |
58 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
59 | struct drm_device *dev = node->minor->dev; | |
60 | const struct intel_device_info *info = INTEL_INFO(dev); | |
61 | ||
62 | seq_printf(m, "gen: %d\n", info->gen); | |
03d00ac5 | 63 | seq_printf(m, "pch: %d\n", INTEL_PCH_TYPE(dev)); |
c96ea64e DV |
64 | #define DEV_INFO_FLAG(x) seq_printf(m, #x ": %s\n", yesno(info->x)) |
65 | #define DEV_INFO_SEP ; | |
66 | DEV_INFO_FLAGS; | |
67 | #undef DEV_INFO_FLAG | |
68 | #undef DEV_INFO_SEP | |
70d39fe4 CW |
69 | |
70 | return 0; | |
71 | } | |
2017263e | 72 | |
05394f39 | 73 | static const char *get_pin_flag(struct drm_i915_gem_object *obj) |
a6172a80 | 74 | { |
05394f39 | 75 | if (obj->user_pin_count > 0) |
a6172a80 | 76 | return "P"; |
05394f39 | 77 | else if (obj->pin_count > 0) |
a6172a80 CW |
78 | return "p"; |
79 | else | |
80 | return " "; | |
81 | } | |
82 | ||
05394f39 | 83 | static const char *get_tiling_flag(struct drm_i915_gem_object *obj) |
a6172a80 | 84 | { |
0206e353 AJ |
85 | switch (obj->tiling_mode) { |
86 | default: | |
87 | case I915_TILING_NONE: return " "; | |
88 | case I915_TILING_X: return "X"; | |
89 | case I915_TILING_Y: return "Y"; | |
90 | } | |
a6172a80 CW |
91 | } |
92 | ||
93dfb40c | 93 | static const char *cache_level_str(int type) |
08c18323 CW |
94 | { |
95 | switch (type) { | |
93dfb40c CW |
96 | case I915_CACHE_NONE: return " uncached"; |
97 | case I915_CACHE_LLC: return " snooped (LLC)"; | |
98 | case I915_CACHE_LLC_MLC: return " snooped (LLC+MLC)"; | |
08c18323 CW |
99 | default: return ""; |
100 | } | |
101 | } | |
102 | ||
37811fcc CW |
103 | static void |
104 | describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj) | |
105 | { | |
04b97b34 | 106 | seq_printf(m, "%p: %s%s %8zdKiB %02x %02x %d %d %d%s%s%s", |
37811fcc CW |
107 | &obj->base, |
108 | get_pin_flag(obj), | |
109 | get_tiling_flag(obj), | |
a05a5862 | 110 | obj->base.size / 1024, |
37811fcc CW |
111 | obj->base.read_domains, |
112 | obj->base.write_domain, | |
0201f1ec CW |
113 | obj->last_read_seqno, |
114 | obj->last_write_seqno, | |
caea7476 | 115 | obj->last_fenced_seqno, |
93dfb40c | 116 | cache_level_str(obj->cache_level), |
37811fcc CW |
117 | obj->dirty ? " dirty" : "", |
118 | obj->madv == I915_MADV_DONTNEED ? " purgeable" : ""); | |
119 | if (obj->base.name) | |
120 | seq_printf(m, " (name: %d)", obj->base.name); | |
c110a6d7 CW |
121 | if (obj->pin_count) |
122 | seq_printf(m, " (pinned x %d)", obj->pin_count); | |
37811fcc CW |
123 | if (obj->fence_reg != I915_FENCE_REG_NONE) |
124 | seq_printf(m, " (fence: %d)", obj->fence_reg); | |
125 | if (obj->gtt_space != NULL) | |
a00b10c3 CW |
126 | seq_printf(m, " (gtt offset: %08x, size: %08x)", |
127 | obj->gtt_offset, (unsigned int)obj->gtt_space->size); | |
c1ad11fc CW |
128 | if (obj->stolen) |
129 | seq_printf(m, " (stolen: %08lx)", obj->stolen->start); | |
6299f992 CW |
130 | if (obj->pin_mappable || obj->fault_mappable) { |
131 | char s[3], *t = s; | |
132 | if (obj->pin_mappable) | |
133 | *t++ = 'p'; | |
134 | if (obj->fault_mappable) | |
135 | *t++ = 'f'; | |
136 | *t = '\0'; | |
137 | seq_printf(m, " (%s mappable)", s); | |
138 | } | |
69dc4987 CW |
139 | if (obj->ring != NULL) |
140 | seq_printf(m, " (%s)", obj->ring->name); | |
37811fcc CW |
141 | } |
142 | ||
433e12f7 | 143 | static int i915_gem_object_list_info(struct seq_file *m, void *data) |
2017263e BG |
144 | { |
145 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
433e12f7 BG |
146 | uintptr_t list = (uintptr_t) node->info_ent->data; |
147 | struct list_head *head; | |
2017263e BG |
148 | struct drm_device *dev = node->minor->dev; |
149 | drm_i915_private_t *dev_priv = dev->dev_private; | |
05394f39 | 150 | struct drm_i915_gem_object *obj; |
8f2480fb CW |
151 | size_t total_obj_size, total_gtt_size; |
152 | int count, ret; | |
de227ef0 CW |
153 | |
154 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
155 | if (ret) | |
156 | return ret; | |
2017263e | 157 | |
433e12f7 BG |
158 | switch (list) { |
159 | case ACTIVE_LIST: | |
160 | seq_printf(m, "Active:\n"); | |
69dc4987 | 161 | head = &dev_priv->mm.active_list; |
433e12f7 BG |
162 | break; |
163 | case INACTIVE_LIST: | |
a17458fc | 164 | seq_printf(m, "Inactive:\n"); |
433e12f7 BG |
165 | head = &dev_priv->mm.inactive_list; |
166 | break; | |
433e12f7 | 167 | default: |
de227ef0 CW |
168 | mutex_unlock(&dev->struct_mutex); |
169 | return -EINVAL; | |
2017263e | 170 | } |
2017263e | 171 | |
8f2480fb | 172 | total_obj_size = total_gtt_size = count = 0; |
05394f39 | 173 | list_for_each_entry(obj, head, mm_list) { |
37811fcc | 174 | seq_printf(m, " "); |
05394f39 | 175 | describe_obj(m, obj); |
f4ceda89 | 176 | seq_printf(m, "\n"); |
05394f39 CW |
177 | total_obj_size += obj->base.size; |
178 | total_gtt_size += obj->gtt_space->size; | |
8f2480fb | 179 | count++; |
2017263e | 180 | } |
de227ef0 | 181 | mutex_unlock(&dev->struct_mutex); |
5e118f41 | 182 | |
8f2480fb CW |
183 | seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n", |
184 | count, total_obj_size, total_gtt_size); | |
2017263e BG |
185 | return 0; |
186 | } | |
187 | ||
6299f992 CW |
188 | #define count_objects(list, member) do { \ |
189 | list_for_each_entry(obj, list, member) { \ | |
190 | size += obj->gtt_space->size; \ | |
191 | ++count; \ | |
192 | if (obj->map_and_fenceable) { \ | |
193 | mappable_size += obj->gtt_space->size; \ | |
194 | ++mappable_count; \ | |
195 | } \ | |
196 | } \ | |
0206e353 | 197 | } while (0) |
6299f992 | 198 | |
73aa808f CW |
199 | static int i915_gem_object_info(struct seq_file *m, void* data) |
200 | { | |
201 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
202 | struct drm_device *dev = node->minor->dev; | |
203 | struct drm_i915_private *dev_priv = dev->dev_private; | |
b7abb714 CW |
204 | u32 count, mappable_count, purgeable_count; |
205 | size_t size, mappable_size, purgeable_size; | |
6299f992 | 206 | struct drm_i915_gem_object *obj; |
73aa808f CW |
207 | int ret; |
208 | ||
209 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
210 | if (ret) | |
211 | return ret; | |
212 | ||
6299f992 CW |
213 | seq_printf(m, "%u objects, %zu bytes\n", |
214 | dev_priv->mm.object_count, | |
215 | dev_priv->mm.object_memory); | |
216 | ||
217 | size = count = mappable_size = mappable_count = 0; | |
6c085a72 | 218 | count_objects(&dev_priv->mm.bound_list, gtt_list); |
6299f992 CW |
219 | seq_printf(m, "%u [%u] objects, %zu [%zu] bytes in gtt\n", |
220 | count, mappable_count, size, mappable_size); | |
221 | ||
222 | size = count = mappable_size = mappable_count = 0; | |
223 | count_objects(&dev_priv->mm.active_list, mm_list); | |
6299f992 CW |
224 | seq_printf(m, " %u [%u] active objects, %zu [%zu] bytes\n", |
225 | count, mappable_count, size, mappable_size); | |
226 | ||
6299f992 CW |
227 | size = count = mappable_size = mappable_count = 0; |
228 | count_objects(&dev_priv->mm.inactive_list, mm_list); | |
229 | seq_printf(m, " %u [%u] inactive objects, %zu [%zu] bytes\n", | |
230 | count, mappable_count, size, mappable_size); | |
231 | ||
b7abb714 CW |
232 | size = count = purgeable_size = purgeable_count = 0; |
233 | list_for_each_entry(obj, &dev_priv->mm.unbound_list, gtt_list) { | |
6c085a72 | 234 | size += obj->base.size, ++count; |
b7abb714 CW |
235 | if (obj->madv == I915_MADV_DONTNEED) |
236 | purgeable_size += obj->base.size, ++purgeable_count; | |
237 | } | |
6c085a72 CW |
238 | seq_printf(m, "%u unbound objects, %zu bytes\n", count, size); |
239 | ||
6299f992 | 240 | size = count = mappable_size = mappable_count = 0; |
6c085a72 | 241 | list_for_each_entry(obj, &dev_priv->mm.bound_list, gtt_list) { |
6299f992 CW |
242 | if (obj->fault_mappable) { |
243 | size += obj->gtt_space->size; | |
244 | ++count; | |
245 | } | |
246 | if (obj->pin_mappable) { | |
247 | mappable_size += obj->gtt_space->size; | |
248 | ++mappable_count; | |
249 | } | |
b7abb714 CW |
250 | if (obj->madv == I915_MADV_DONTNEED) { |
251 | purgeable_size += obj->base.size; | |
252 | ++purgeable_count; | |
253 | } | |
6299f992 | 254 | } |
b7abb714 CW |
255 | seq_printf(m, "%u purgeable objects, %zu bytes\n", |
256 | purgeable_count, purgeable_size); | |
6299f992 CW |
257 | seq_printf(m, "%u pinned mappable objects, %zu bytes\n", |
258 | mappable_count, mappable_size); | |
259 | seq_printf(m, "%u fault mappable objects, %zu bytes\n", | |
260 | count, size); | |
261 | ||
93d18799 | 262 | seq_printf(m, "%zu [%lu] gtt total\n", |
5d4545ae BW |
263 | dev_priv->gtt.total, |
264 | dev_priv->gtt.mappable_end - dev_priv->gtt.start); | |
73aa808f CW |
265 | |
266 | mutex_unlock(&dev->struct_mutex); | |
267 | ||
268 | return 0; | |
269 | } | |
270 | ||
08c18323 CW |
271 | static int i915_gem_gtt_info(struct seq_file *m, void* data) |
272 | { | |
273 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
274 | struct drm_device *dev = node->minor->dev; | |
1b50247a | 275 | uintptr_t list = (uintptr_t) node->info_ent->data; |
08c18323 CW |
276 | struct drm_i915_private *dev_priv = dev->dev_private; |
277 | struct drm_i915_gem_object *obj; | |
278 | size_t total_obj_size, total_gtt_size; | |
279 | int count, ret; | |
280 | ||
281 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
282 | if (ret) | |
283 | return ret; | |
284 | ||
285 | total_obj_size = total_gtt_size = count = 0; | |
6c085a72 | 286 | list_for_each_entry(obj, &dev_priv->mm.bound_list, gtt_list) { |
1b50247a CW |
287 | if (list == PINNED_LIST && obj->pin_count == 0) |
288 | continue; | |
289 | ||
08c18323 CW |
290 | seq_printf(m, " "); |
291 | describe_obj(m, obj); | |
292 | seq_printf(m, "\n"); | |
293 | total_obj_size += obj->base.size; | |
294 | total_gtt_size += obj->gtt_space->size; | |
295 | count++; | |
296 | } | |
297 | ||
298 | mutex_unlock(&dev->struct_mutex); | |
299 | ||
300 | seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n", | |
301 | count, total_obj_size, total_gtt_size); | |
302 | ||
303 | return 0; | |
304 | } | |
305 | ||
4e5359cd SF |
306 | static int i915_gem_pageflip_info(struct seq_file *m, void *data) |
307 | { | |
308 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
309 | struct drm_device *dev = node->minor->dev; | |
310 | unsigned long flags; | |
311 | struct intel_crtc *crtc; | |
312 | ||
313 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) { | |
9db4a9c7 JB |
314 | const char pipe = pipe_name(crtc->pipe); |
315 | const char plane = plane_name(crtc->plane); | |
4e5359cd SF |
316 | struct intel_unpin_work *work; |
317 | ||
318 | spin_lock_irqsave(&dev->event_lock, flags); | |
319 | work = crtc->unpin_work; | |
320 | if (work == NULL) { | |
9db4a9c7 | 321 | seq_printf(m, "No flip due on pipe %c (plane %c)\n", |
4e5359cd SF |
322 | pipe, plane); |
323 | } else { | |
e7d841ca | 324 | if (atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) { |
9db4a9c7 | 325 | seq_printf(m, "Flip queued on pipe %c (plane %c)\n", |
4e5359cd SF |
326 | pipe, plane); |
327 | } else { | |
9db4a9c7 | 328 | seq_printf(m, "Flip pending (waiting for vsync) on pipe %c (plane %c)\n", |
4e5359cd SF |
329 | pipe, plane); |
330 | } | |
331 | if (work->enable_stall_check) | |
332 | seq_printf(m, "Stall check enabled, "); | |
333 | else | |
334 | seq_printf(m, "Stall check waiting for page flip ioctl, "); | |
e7d841ca | 335 | seq_printf(m, "%d prepares\n", atomic_read(&work->pending)); |
4e5359cd SF |
336 | |
337 | if (work->old_fb_obj) { | |
05394f39 CW |
338 | struct drm_i915_gem_object *obj = work->old_fb_obj; |
339 | if (obj) | |
340 | seq_printf(m, "Old framebuffer gtt_offset 0x%08x\n", obj->gtt_offset); | |
4e5359cd SF |
341 | } |
342 | if (work->pending_flip_obj) { | |
05394f39 CW |
343 | struct drm_i915_gem_object *obj = work->pending_flip_obj; |
344 | if (obj) | |
345 | seq_printf(m, "New framebuffer gtt_offset 0x%08x\n", obj->gtt_offset); | |
4e5359cd SF |
346 | } |
347 | } | |
348 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
349 | } | |
350 | ||
351 | return 0; | |
352 | } | |
353 | ||
2017263e BG |
354 | static int i915_gem_request_info(struct seq_file *m, void *data) |
355 | { | |
356 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
357 | struct drm_device *dev = node->minor->dev; | |
358 | drm_i915_private_t *dev_priv = dev->dev_private; | |
a2c7f6fd | 359 | struct intel_ring_buffer *ring; |
2017263e | 360 | struct drm_i915_gem_request *gem_request; |
a2c7f6fd | 361 | int ret, count, i; |
de227ef0 CW |
362 | |
363 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
364 | if (ret) | |
365 | return ret; | |
2017263e | 366 | |
c2c347a9 | 367 | count = 0; |
a2c7f6fd CW |
368 | for_each_ring(ring, dev_priv, i) { |
369 | if (list_empty(&ring->request_list)) | |
370 | continue; | |
371 | ||
372 | seq_printf(m, "%s requests:\n", ring->name); | |
c2c347a9 | 373 | list_for_each_entry(gem_request, |
a2c7f6fd | 374 | &ring->request_list, |
c2c347a9 CW |
375 | list) { |
376 | seq_printf(m, " %d @ %d\n", | |
377 | gem_request->seqno, | |
378 | (int) (jiffies - gem_request->emitted_jiffies)); | |
379 | } | |
380 | count++; | |
2017263e | 381 | } |
de227ef0 CW |
382 | mutex_unlock(&dev->struct_mutex); |
383 | ||
c2c347a9 CW |
384 | if (count == 0) |
385 | seq_printf(m, "No requests\n"); | |
386 | ||
2017263e BG |
387 | return 0; |
388 | } | |
389 | ||
b2223497 CW |
390 | static void i915_ring_seqno_info(struct seq_file *m, |
391 | struct intel_ring_buffer *ring) | |
392 | { | |
393 | if (ring->get_seqno) { | |
43a7b924 | 394 | seq_printf(m, "Current sequence (%s): %u\n", |
b2eadbc8 | 395 | ring->name, ring->get_seqno(ring, false)); |
b2223497 CW |
396 | } |
397 | } | |
398 | ||
2017263e BG |
399 | static int i915_gem_seqno_info(struct seq_file *m, void *data) |
400 | { | |
401 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
402 | struct drm_device *dev = node->minor->dev; | |
403 | drm_i915_private_t *dev_priv = dev->dev_private; | |
a2c7f6fd | 404 | struct intel_ring_buffer *ring; |
1ec14ad3 | 405 | int ret, i; |
de227ef0 CW |
406 | |
407 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
408 | if (ret) | |
409 | return ret; | |
2017263e | 410 | |
a2c7f6fd CW |
411 | for_each_ring(ring, dev_priv, i) |
412 | i915_ring_seqno_info(m, ring); | |
de227ef0 CW |
413 | |
414 | mutex_unlock(&dev->struct_mutex); | |
415 | ||
2017263e BG |
416 | return 0; |
417 | } | |
418 | ||
419 | ||
420 | static int i915_interrupt_info(struct seq_file *m, void *data) | |
421 | { | |
422 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
423 | struct drm_device *dev = node->minor->dev; | |
424 | drm_i915_private_t *dev_priv = dev->dev_private; | |
a2c7f6fd | 425 | struct intel_ring_buffer *ring; |
9db4a9c7 | 426 | int ret, i, pipe; |
de227ef0 CW |
427 | |
428 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
429 | if (ret) | |
430 | return ret; | |
2017263e | 431 | |
7e231dbe JB |
432 | if (IS_VALLEYVIEW(dev)) { |
433 | seq_printf(m, "Display IER:\t%08x\n", | |
434 | I915_READ(VLV_IER)); | |
435 | seq_printf(m, "Display IIR:\t%08x\n", | |
436 | I915_READ(VLV_IIR)); | |
437 | seq_printf(m, "Display IIR_RW:\t%08x\n", | |
438 | I915_READ(VLV_IIR_RW)); | |
439 | seq_printf(m, "Display IMR:\t%08x\n", | |
440 | I915_READ(VLV_IMR)); | |
441 | for_each_pipe(pipe) | |
442 | seq_printf(m, "Pipe %c stat:\t%08x\n", | |
443 | pipe_name(pipe), | |
444 | I915_READ(PIPESTAT(pipe))); | |
445 | ||
446 | seq_printf(m, "Master IER:\t%08x\n", | |
447 | I915_READ(VLV_MASTER_IER)); | |
448 | ||
449 | seq_printf(m, "Render IER:\t%08x\n", | |
450 | I915_READ(GTIER)); | |
451 | seq_printf(m, "Render IIR:\t%08x\n", | |
452 | I915_READ(GTIIR)); | |
453 | seq_printf(m, "Render IMR:\t%08x\n", | |
454 | I915_READ(GTIMR)); | |
455 | ||
456 | seq_printf(m, "PM IER:\t\t%08x\n", | |
457 | I915_READ(GEN6_PMIER)); | |
458 | seq_printf(m, "PM IIR:\t\t%08x\n", | |
459 | I915_READ(GEN6_PMIIR)); | |
460 | seq_printf(m, "PM IMR:\t\t%08x\n", | |
461 | I915_READ(GEN6_PMIMR)); | |
462 | ||
463 | seq_printf(m, "Port hotplug:\t%08x\n", | |
464 | I915_READ(PORT_HOTPLUG_EN)); | |
465 | seq_printf(m, "DPFLIPSTAT:\t%08x\n", | |
466 | I915_READ(VLV_DPFLIPSTAT)); | |
467 | seq_printf(m, "DPINVGTT:\t%08x\n", | |
468 | I915_READ(DPINVGTT)); | |
469 | ||
470 | } else if (!HAS_PCH_SPLIT(dev)) { | |
5f6a1695 ZW |
471 | seq_printf(m, "Interrupt enable: %08x\n", |
472 | I915_READ(IER)); | |
473 | seq_printf(m, "Interrupt identity: %08x\n", | |
474 | I915_READ(IIR)); | |
475 | seq_printf(m, "Interrupt mask: %08x\n", | |
476 | I915_READ(IMR)); | |
9db4a9c7 JB |
477 | for_each_pipe(pipe) |
478 | seq_printf(m, "Pipe %c stat: %08x\n", | |
479 | pipe_name(pipe), | |
480 | I915_READ(PIPESTAT(pipe))); | |
5f6a1695 ZW |
481 | } else { |
482 | seq_printf(m, "North Display Interrupt enable: %08x\n", | |
483 | I915_READ(DEIER)); | |
484 | seq_printf(m, "North Display Interrupt identity: %08x\n", | |
485 | I915_READ(DEIIR)); | |
486 | seq_printf(m, "North Display Interrupt mask: %08x\n", | |
487 | I915_READ(DEIMR)); | |
488 | seq_printf(m, "South Display Interrupt enable: %08x\n", | |
489 | I915_READ(SDEIER)); | |
490 | seq_printf(m, "South Display Interrupt identity: %08x\n", | |
491 | I915_READ(SDEIIR)); | |
492 | seq_printf(m, "South Display Interrupt mask: %08x\n", | |
493 | I915_READ(SDEIMR)); | |
494 | seq_printf(m, "Graphics Interrupt enable: %08x\n", | |
495 | I915_READ(GTIER)); | |
496 | seq_printf(m, "Graphics Interrupt identity: %08x\n", | |
497 | I915_READ(GTIIR)); | |
498 | seq_printf(m, "Graphics Interrupt mask: %08x\n", | |
499 | I915_READ(GTIMR)); | |
500 | } | |
2017263e BG |
501 | seq_printf(m, "Interrupts received: %d\n", |
502 | atomic_read(&dev_priv->irq_received)); | |
a2c7f6fd | 503 | for_each_ring(ring, dev_priv, i) { |
da64c6fc | 504 | if (IS_GEN6(dev) || IS_GEN7(dev)) { |
a2c7f6fd CW |
505 | seq_printf(m, |
506 | "Graphics Interrupt mask (%s): %08x\n", | |
507 | ring->name, I915_READ_IMR(ring)); | |
9862e600 | 508 | } |
a2c7f6fd | 509 | i915_ring_seqno_info(m, ring); |
9862e600 | 510 | } |
de227ef0 CW |
511 | mutex_unlock(&dev->struct_mutex); |
512 | ||
2017263e BG |
513 | return 0; |
514 | } | |
515 | ||
a6172a80 CW |
516 | static int i915_gem_fence_regs_info(struct seq_file *m, void *data) |
517 | { | |
518 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
519 | struct drm_device *dev = node->minor->dev; | |
520 | drm_i915_private_t *dev_priv = dev->dev_private; | |
de227ef0 CW |
521 | int i, ret; |
522 | ||
523 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
524 | if (ret) | |
525 | return ret; | |
a6172a80 CW |
526 | |
527 | seq_printf(m, "Reserved fences = %d\n", dev_priv->fence_reg_start); | |
528 | seq_printf(m, "Total fences = %d\n", dev_priv->num_fence_regs); | |
529 | for (i = 0; i < dev_priv->num_fence_regs; i++) { | |
05394f39 | 530 | struct drm_i915_gem_object *obj = dev_priv->fence_regs[i].obj; |
a6172a80 | 531 | |
6c085a72 CW |
532 | seq_printf(m, "Fence %d, pin count = %d, object = ", |
533 | i, dev_priv->fence_regs[i].pin_count); | |
c2c347a9 CW |
534 | if (obj == NULL) |
535 | seq_printf(m, "unused"); | |
536 | else | |
05394f39 | 537 | describe_obj(m, obj); |
c2c347a9 | 538 | seq_printf(m, "\n"); |
a6172a80 CW |
539 | } |
540 | ||
05394f39 | 541 | mutex_unlock(&dev->struct_mutex); |
a6172a80 CW |
542 | return 0; |
543 | } | |
544 | ||
2017263e BG |
545 | static int i915_hws_info(struct seq_file *m, void *data) |
546 | { | |
547 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
548 | struct drm_device *dev = node->minor->dev; | |
549 | drm_i915_private_t *dev_priv = dev->dev_private; | |
4066c0ae | 550 | struct intel_ring_buffer *ring; |
1a240d4d | 551 | const u32 *hws; |
4066c0ae CW |
552 | int i; |
553 | ||
1ec14ad3 | 554 | ring = &dev_priv->ring[(uintptr_t)node->info_ent->data]; |
1a240d4d | 555 | hws = ring->status_page.page_addr; |
2017263e BG |
556 | if (hws == NULL) |
557 | return 0; | |
558 | ||
559 | for (i = 0; i < 4096 / sizeof(u32) / 4; i += 4) { | |
560 | seq_printf(m, "0x%08x: 0x%08x 0x%08x 0x%08x 0x%08x\n", | |
561 | i * 4, | |
562 | hws[i], hws[i + 1], hws[i + 2], hws[i + 3]); | |
563 | } | |
564 | return 0; | |
565 | } | |
566 | ||
e5c65260 CW |
567 | static const char *ring_str(int ring) |
568 | { | |
569 | switch (ring) { | |
96154f2f DV |
570 | case RCS: return "render"; |
571 | case VCS: return "bsd"; | |
572 | case BCS: return "blt"; | |
e5c65260 CW |
573 | default: return ""; |
574 | } | |
575 | } | |
576 | ||
9df30794 CW |
577 | static const char *pin_flag(int pinned) |
578 | { | |
579 | if (pinned > 0) | |
580 | return " P"; | |
581 | else if (pinned < 0) | |
582 | return " p"; | |
583 | else | |
584 | return ""; | |
585 | } | |
586 | ||
587 | static const char *tiling_flag(int tiling) | |
588 | { | |
589 | switch (tiling) { | |
590 | default: | |
591 | case I915_TILING_NONE: return ""; | |
592 | case I915_TILING_X: return " X"; | |
593 | case I915_TILING_Y: return " Y"; | |
594 | } | |
595 | } | |
596 | ||
597 | static const char *dirty_flag(int dirty) | |
598 | { | |
599 | return dirty ? " dirty" : ""; | |
600 | } | |
601 | ||
602 | static const char *purgeable_flag(int purgeable) | |
603 | { | |
604 | return purgeable ? " purgeable" : ""; | |
605 | } | |
606 | ||
c724e8a9 CW |
607 | static void print_error_buffers(struct seq_file *m, |
608 | const char *name, | |
609 | struct drm_i915_error_buffer *err, | |
610 | int count) | |
611 | { | |
612 | seq_printf(m, "%s [%d]:\n", name, count); | |
613 | ||
614 | while (count--) { | |
04b97b34 | 615 | seq_printf(m, " %08x %8u %02x %02x %x %x%s%s%s%s%s%s%s", |
c724e8a9 CW |
616 | err->gtt_offset, |
617 | err->size, | |
618 | err->read_domains, | |
619 | err->write_domain, | |
0201f1ec | 620 | err->rseqno, err->wseqno, |
c724e8a9 CW |
621 | pin_flag(err->pinned), |
622 | tiling_flag(err->tiling), | |
623 | dirty_flag(err->dirty), | |
624 | purgeable_flag(err->purgeable), | |
96154f2f | 625 | err->ring != -1 ? " " : "", |
a779e5ab | 626 | ring_str(err->ring), |
93dfb40c | 627 | cache_level_str(err->cache_level)); |
c724e8a9 CW |
628 | |
629 | if (err->name) | |
630 | seq_printf(m, " (name: %d)", err->name); | |
631 | if (err->fence_reg != I915_FENCE_REG_NONE) | |
632 | seq_printf(m, " (fence: %d)", err->fence_reg); | |
633 | ||
634 | seq_printf(m, "\n"); | |
635 | err++; | |
636 | } | |
637 | } | |
638 | ||
d27b1e0e DV |
639 | static void i915_ring_error_state(struct seq_file *m, |
640 | struct drm_device *dev, | |
641 | struct drm_i915_error_state *error, | |
642 | unsigned ring) | |
643 | { | |
ec34a01d | 644 | BUG_ON(ring >= I915_NUM_RINGS); /* shut up confused gcc */ |
d27b1e0e | 645 | seq_printf(m, "%s command stream:\n", ring_str(ring)); |
c1cd90ed DV |
646 | seq_printf(m, " HEAD: 0x%08x\n", error->head[ring]); |
647 | seq_printf(m, " TAIL: 0x%08x\n", error->tail[ring]); | |
0f3b6849 | 648 | seq_printf(m, " CTL: 0x%08x\n", error->ctl[ring]); |
d27b1e0e DV |
649 | seq_printf(m, " ACTHD: 0x%08x\n", error->acthd[ring]); |
650 | seq_printf(m, " IPEIR: 0x%08x\n", error->ipeir[ring]); | |
651 | seq_printf(m, " IPEHR: 0x%08x\n", error->ipehr[ring]); | |
652 | seq_printf(m, " INSTDONE: 0x%08x\n", error->instdone[ring]); | |
050ee91f | 653 | if (ring == RCS && INTEL_INFO(dev)->gen >= 4) |
c1cd90ed | 654 | seq_printf(m, " BBADDR: 0x%08llx\n", error->bbaddr); |
050ee91f | 655 | |
c1cd90ed DV |
656 | if (INTEL_INFO(dev)->gen >= 4) |
657 | seq_printf(m, " INSTPS: 0x%08x\n", error->instps[ring]); | |
658 | seq_printf(m, " INSTPM: 0x%08x\n", error->instpm[ring]); | |
9d2f41fa | 659 | seq_printf(m, " FADDR: 0x%08x\n", error->faddr[ring]); |
33f3f518 | 660 | if (INTEL_INFO(dev)->gen >= 6) { |
12f55818 | 661 | seq_printf(m, " RC PSMI: 0x%08x\n", error->rc_psmi[ring]); |
33f3f518 | 662 | seq_printf(m, " FAULT_REG: 0x%08x\n", error->fault_reg[ring]); |
df2b23d9 CW |
663 | seq_printf(m, " SYNC_0: 0x%08x [last synced 0x%08x]\n", |
664 | error->semaphore_mboxes[ring][0], | |
665 | error->semaphore_seqno[ring][0]); | |
666 | seq_printf(m, " SYNC_1: 0x%08x [last synced 0x%08x]\n", | |
667 | error->semaphore_mboxes[ring][1], | |
668 | error->semaphore_seqno[ring][1]); | |
33f3f518 | 669 | } |
d27b1e0e | 670 | seq_printf(m, " seqno: 0x%08x\n", error->seqno[ring]); |
9574b3fe | 671 | seq_printf(m, " waiting: %s\n", yesno(error->waiting[ring])); |
7e3b8737 DV |
672 | seq_printf(m, " ring->head: 0x%08x\n", error->cpu_ring_head[ring]); |
673 | seq_printf(m, " ring->tail: 0x%08x\n", error->cpu_ring_tail[ring]); | |
d27b1e0e DV |
674 | } |
675 | ||
d5442303 DV |
676 | struct i915_error_state_file_priv { |
677 | struct drm_device *dev; | |
678 | struct drm_i915_error_state *error; | |
679 | }; | |
680 | ||
63eeaf38 JB |
681 | static int i915_error_state(struct seq_file *m, void *unused) |
682 | { | |
d5442303 DV |
683 | struct i915_error_state_file_priv *error_priv = m->private; |
684 | struct drm_device *dev = error_priv->dev; | |
63eeaf38 | 685 | drm_i915_private_t *dev_priv = dev->dev_private; |
d5442303 | 686 | struct drm_i915_error_state *error = error_priv->error; |
b4519513 | 687 | struct intel_ring_buffer *ring; |
52d39a21 | 688 | int i, j, page, offset, elt; |
63eeaf38 | 689 | |
742cbee8 | 690 | if (!error) { |
63eeaf38 | 691 | seq_printf(m, "no error state collected\n"); |
742cbee8 | 692 | return 0; |
63eeaf38 JB |
693 | } |
694 | ||
8a905236 JB |
695 | seq_printf(m, "Time: %ld s %ld us\n", error->time.tv_sec, |
696 | error->time.tv_usec); | |
fdfa175d | 697 | seq_printf(m, "Kernel: " UTS_RELEASE "\n"); |
9df30794 | 698 | seq_printf(m, "PCI ID: 0x%04x\n", dev->pci_device); |
1d8f38f4 | 699 | seq_printf(m, "EIR: 0x%08x\n", error->eir); |
be998e2e | 700 | seq_printf(m, "IER: 0x%08x\n", error->ier); |
1d8f38f4 | 701 | seq_printf(m, "PGTBL_ER: 0x%08x\n", error->pgtbl_er); |
0f3b6849 CW |
702 | seq_printf(m, "FORCEWAKE: 0x%08x\n", error->forcewake); |
703 | seq_printf(m, "DERRMR: 0x%08x\n", error->derrmr); | |
b9a3906b | 704 | seq_printf(m, "CCID: 0x%08x\n", error->ccid); |
9df30794 | 705 | |
bf3301ab | 706 | for (i = 0; i < dev_priv->num_fence_regs; i++) |
748ebc60 CW |
707 | seq_printf(m, " fence[%d] = %08llx\n", i, error->fence[i]); |
708 | ||
050ee91f BW |
709 | for (i = 0; i < ARRAY_SIZE(error->extra_instdone); i++) |
710 | seq_printf(m, " INSTDONE_%d: 0x%08x\n", i, error->extra_instdone[i]); | |
711 | ||
33f3f518 | 712 | if (INTEL_INFO(dev)->gen >= 6) { |
d27b1e0e | 713 | seq_printf(m, "ERROR: 0x%08x\n", error->error); |
33f3f518 DV |
714 | seq_printf(m, "DONE_REG: 0x%08x\n", error->done_reg); |
715 | } | |
d27b1e0e | 716 | |
71e172e8 BW |
717 | if (INTEL_INFO(dev)->gen == 7) |
718 | seq_printf(m, "ERR_INT: 0x%08x\n", error->err_int); | |
719 | ||
b4519513 CW |
720 | for_each_ring(ring, dev_priv, i) |
721 | i915_ring_error_state(m, dev, error, i); | |
d27b1e0e | 722 | |
c724e8a9 CW |
723 | if (error->active_bo) |
724 | print_error_buffers(m, "Active", | |
725 | error->active_bo, | |
726 | error->active_bo_count); | |
727 | ||
728 | if (error->pinned_bo) | |
729 | print_error_buffers(m, "Pinned", | |
730 | error->pinned_bo, | |
731 | error->pinned_bo_count); | |
9df30794 | 732 | |
52d39a21 CW |
733 | for (i = 0; i < ARRAY_SIZE(error->ring); i++) { |
734 | struct drm_i915_error_object *obj; | |
9df30794 | 735 | |
52d39a21 | 736 | if ((obj = error->ring[i].batchbuffer)) { |
bcfb2e28 CW |
737 | seq_printf(m, "%s --- gtt_offset = 0x%08x\n", |
738 | dev_priv->ring[i].name, | |
739 | obj->gtt_offset); | |
9df30794 CW |
740 | offset = 0; |
741 | for (page = 0; page < obj->page_count; page++) { | |
742 | for (elt = 0; elt < PAGE_SIZE/4; elt++) { | |
743 | seq_printf(m, "%08x : %08x\n", offset, obj->pages[page][elt]); | |
744 | offset += 4; | |
745 | } | |
746 | } | |
747 | } | |
9df30794 | 748 | |
52d39a21 CW |
749 | if (error->ring[i].num_requests) { |
750 | seq_printf(m, "%s --- %d requests\n", | |
751 | dev_priv->ring[i].name, | |
752 | error->ring[i].num_requests); | |
753 | for (j = 0; j < error->ring[i].num_requests; j++) { | |
ee4f42b1 | 754 | seq_printf(m, " seqno 0x%08x, emitted %ld, tail 0x%08x\n", |
52d39a21 | 755 | error->ring[i].requests[j].seqno, |
ee4f42b1 CW |
756 | error->ring[i].requests[j].jiffies, |
757 | error->ring[i].requests[j].tail); | |
52d39a21 CW |
758 | } |
759 | } | |
760 | ||
761 | if ((obj = error->ring[i].ringbuffer)) { | |
e2f973d5 CW |
762 | seq_printf(m, "%s --- ringbuffer = 0x%08x\n", |
763 | dev_priv->ring[i].name, | |
764 | obj->gtt_offset); | |
765 | offset = 0; | |
766 | for (page = 0; page < obj->page_count; page++) { | |
767 | for (elt = 0; elt < PAGE_SIZE/4; elt++) { | |
768 | seq_printf(m, "%08x : %08x\n", | |
769 | offset, | |
770 | obj->pages[page][elt]); | |
771 | offset += 4; | |
772 | } | |
9df30794 CW |
773 | } |
774 | } | |
8c123e54 BW |
775 | |
776 | obj = error->ring[i].ctx; | |
777 | if (obj) { | |
778 | seq_printf(m, "%s --- HW Context = 0x%08x\n", | |
779 | dev_priv->ring[i].name, | |
780 | obj->gtt_offset); | |
781 | offset = 0; | |
782 | for (elt = 0; elt < PAGE_SIZE/16; elt += 4) { | |
783 | seq_printf(m, "[%04x] %08x %08x %08x %08x\n", | |
784 | offset, | |
785 | obj->pages[0][elt], | |
786 | obj->pages[0][elt+1], | |
787 | obj->pages[0][elt+2], | |
788 | obj->pages[0][elt+3]); | |
789 | offset += 16; | |
790 | } | |
791 | } | |
9df30794 | 792 | } |
63eeaf38 | 793 | |
6ef3d427 CW |
794 | if (error->overlay) |
795 | intel_overlay_print_error_state(m, error->overlay); | |
796 | ||
c4a1d9e4 CW |
797 | if (error->display) |
798 | intel_display_print_error_state(m, dev, error->display); | |
799 | ||
63eeaf38 JB |
800 | return 0; |
801 | } | |
6911a9b8 | 802 | |
d5442303 DV |
803 | static ssize_t |
804 | i915_error_state_write(struct file *filp, | |
805 | const char __user *ubuf, | |
806 | size_t cnt, | |
807 | loff_t *ppos) | |
808 | { | |
809 | struct seq_file *m = filp->private_data; | |
810 | struct i915_error_state_file_priv *error_priv = m->private; | |
811 | struct drm_device *dev = error_priv->dev; | |
22bcfc6a | 812 | int ret; |
d5442303 DV |
813 | |
814 | DRM_DEBUG_DRIVER("Resetting error state\n"); | |
815 | ||
22bcfc6a DV |
816 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
817 | if (ret) | |
818 | return ret; | |
819 | ||
d5442303 DV |
820 | i915_destroy_error_state(dev); |
821 | mutex_unlock(&dev->struct_mutex); | |
822 | ||
823 | return cnt; | |
824 | } | |
825 | ||
826 | static int i915_error_state_open(struct inode *inode, struct file *file) | |
827 | { | |
828 | struct drm_device *dev = inode->i_private; | |
829 | drm_i915_private_t *dev_priv = dev->dev_private; | |
830 | struct i915_error_state_file_priv *error_priv; | |
831 | unsigned long flags; | |
832 | ||
833 | error_priv = kzalloc(sizeof(*error_priv), GFP_KERNEL); | |
834 | if (!error_priv) | |
835 | return -ENOMEM; | |
836 | ||
837 | error_priv->dev = dev; | |
838 | ||
99584db3 DV |
839 | spin_lock_irqsave(&dev_priv->gpu_error.lock, flags); |
840 | error_priv->error = dev_priv->gpu_error.first_error; | |
d5442303 DV |
841 | if (error_priv->error) |
842 | kref_get(&error_priv->error->ref); | |
99584db3 | 843 | spin_unlock_irqrestore(&dev_priv->gpu_error.lock, flags); |
d5442303 DV |
844 | |
845 | return single_open(file, i915_error_state, error_priv); | |
846 | } | |
847 | ||
848 | static int i915_error_state_release(struct inode *inode, struct file *file) | |
849 | { | |
850 | struct seq_file *m = file->private_data; | |
851 | struct i915_error_state_file_priv *error_priv = m->private; | |
852 | ||
853 | if (error_priv->error) | |
854 | kref_put(&error_priv->error->ref, i915_error_state_free); | |
855 | kfree(error_priv); | |
856 | ||
857 | return single_release(inode, file); | |
858 | } | |
859 | ||
860 | static const struct file_operations i915_error_state_fops = { | |
861 | .owner = THIS_MODULE, | |
862 | .open = i915_error_state_open, | |
863 | .read = seq_read, | |
864 | .write = i915_error_state_write, | |
865 | .llseek = default_llseek, | |
866 | .release = i915_error_state_release, | |
867 | }; | |
868 | ||
40633219 MK |
869 | static ssize_t |
870 | i915_next_seqno_read(struct file *filp, | |
871 | char __user *ubuf, | |
872 | size_t max, | |
873 | loff_t *ppos) | |
874 | { | |
875 | struct drm_device *dev = filp->private_data; | |
876 | drm_i915_private_t *dev_priv = dev->dev_private; | |
877 | char buf[80]; | |
878 | int len; | |
879 | int ret; | |
880 | ||
881 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
882 | if (ret) | |
883 | return ret; | |
884 | ||
885 | len = snprintf(buf, sizeof(buf), | |
886 | "next_seqno : 0x%x\n", | |
887 | dev_priv->next_seqno); | |
888 | ||
889 | mutex_unlock(&dev->struct_mutex); | |
890 | ||
891 | if (len > sizeof(buf)) | |
892 | len = sizeof(buf); | |
893 | ||
894 | return simple_read_from_buffer(ubuf, max, ppos, buf, len); | |
895 | } | |
896 | ||
897 | static ssize_t | |
898 | i915_next_seqno_write(struct file *filp, | |
899 | const char __user *ubuf, | |
900 | size_t cnt, | |
901 | loff_t *ppos) | |
902 | { | |
903 | struct drm_device *dev = filp->private_data; | |
40633219 MK |
904 | char buf[20]; |
905 | u32 val = 1; | |
906 | int ret; | |
907 | ||
908 | if (cnt > 0) { | |
909 | if (cnt > sizeof(buf) - 1) | |
910 | return -EINVAL; | |
911 | ||
912 | if (copy_from_user(buf, ubuf, cnt)) | |
913 | return -EFAULT; | |
914 | buf[cnt] = 0; | |
915 | ||
916 | ret = kstrtouint(buf, 0, &val); | |
917 | if (ret < 0) | |
918 | return ret; | |
919 | } | |
920 | ||
40633219 MK |
921 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
922 | if (ret) | |
923 | return ret; | |
924 | ||
e94fbaa8 | 925 | ret = i915_gem_set_seqno(dev, val); |
40633219 MK |
926 | |
927 | mutex_unlock(&dev->struct_mutex); | |
928 | ||
929 | return ret ?: cnt; | |
930 | } | |
931 | ||
932 | static const struct file_operations i915_next_seqno_fops = { | |
933 | .owner = THIS_MODULE, | |
934 | .open = simple_open, | |
935 | .read = i915_next_seqno_read, | |
936 | .write = i915_next_seqno_write, | |
937 | .llseek = default_llseek, | |
938 | }; | |
939 | ||
f97108d1 JB |
940 | static int i915_rstdby_delays(struct seq_file *m, void *unused) |
941 | { | |
942 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
943 | struct drm_device *dev = node->minor->dev; | |
944 | drm_i915_private_t *dev_priv = dev->dev_private; | |
616fdb5a BW |
945 | u16 crstanddelay; |
946 | int ret; | |
947 | ||
948 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
949 | if (ret) | |
950 | return ret; | |
951 | ||
952 | crstanddelay = I915_READ16(CRSTANDVID); | |
953 | ||
954 | mutex_unlock(&dev->struct_mutex); | |
f97108d1 JB |
955 | |
956 | seq_printf(m, "w/ctx: %d, w/o ctx: %d\n", (crstanddelay >> 8) & 0x3f, (crstanddelay & 0x3f)); | |
957 | ||
958 | return 0; | |
959 | } | |
960 | ||
961 | static int i915_cur_delayinfo(struct seq_file *m, void *unused) | |
962 | { | |
963 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
964 | struct drm_device *dev = node->minor->dev; | |
965 | drm_i915_private_t *dev_priv = dev->dev_private; | |
d1ebd816 | 966 | int ret; |
3b8d8d91 JB |
967 | |
968 | if (IS_GEN5(dev)) { | |
969 | u16 rgvswctl = I915_READ16(MEMSWCTL); | |
970 | u16 rgvstat = I915_READ16(MEMSTAT_ILK); | |
971 | ||
972 | seq_printf(m, "Requested P-state: %d\n", (rgvswctl >> 8) & 0xf); | |
973 | seq_printf(m, "Requested VID: %d\n", rgvswctl & 0x3f); | |
974 | seq_printf(m, "Current VID: %d\n", (rgvstat & MEMSTAT_VID_MASK) >> | |
975 | MEMSTAT_VID_SHIFT); | |
976 | seq_printf(m, "Current P-state: %d\n", | |
977 | (rgvstat & MEMSTAT_PSTATE_MASK) >> MEMSTAT_PSTATE_SHIFT); | |
1c70c0ce | 978 | } else if (IS_GEN6(dev) || IS_GEN7(dev)) { |
3b8d8d91 JB |
979 | u32 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS); |
980 | u32 rp_state_limits = I915_READ(GEN6_RP_STATE_LIMITS); | |
981 | u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP); | |
f82855d3 | 982 | u32 rpstat, cagf; |
ccab5c82 JB |
983 | u32 rpupei, rpcurup, rpprevup; |
984 | u32 rpdownei, rpcurdown, rpprevdown; | |
3b8d8d91 JB |
985 | int max_freq; |
986 | ||
987 | /* RPSTAT1 is in the GT power well */ | |
d1ebd816 BW |
988 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
989 | if (ret) | |
990 | return ret; | |
991 | ||
fcca7926 | 992 | gen6_gt_force_wake_get(dev_priv); |
3b8d8d91 | 993 | |
ccab5c82 JB |
994 | rpstat = I915_READ(GEN6_RPSTAT1); |
995 | rpupei = I915_READ(GEN6_RP_CUR_UP_EI); | |
996 | rpcurup = I915_READ(GEN6_RP_CUR_UP); | |
997 | rpprevup = I915_READ(GEN6_RP_PREV_UP); | |
998 | rpdownei = I915_READ(GEN6_RP_CUR_DOWN_EI); | |
999 | rpcurdown = I915_READ(GEN6_RP_CUR_DOWN); | |
1000 | rpprevdown = I915_READ(GEN6_RP_PREV_DOWN); | |
f82855d3 BW |
1001 | if (IS_HASWELL(dev)) |
1002 | cagf = (rpstat & HSW_CAGF_MASK) >> HSW_CAGF_SHIFT; | |
1003 | else | |
1004 | cagf = (rpstat & GEN6_CAGF_MASK) >> GEN6_CAGF_SHIFT; | |
1005 | cagf *= GT_FREQUENCY_MULTIPLIER; | |
ccab5c82 | 1006 | |
d1ebd816 BW |
1007 | gen6_gt_force_wake_put(dev_priv); |
1008 | mutex_unlock(&dev->struct_mutex); | |
1009 | ||
3b8d8d91 | 1010 | seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status); |
ccab5c82 | 1011 | seq_printf(m, "RPSTAT1: 0x%08x\n", rpstat); |
3b8d8d91 JB |
1012 | seq_printf(m, "Render p-state ratio: %d\n", |
1013 | (gt_perf_status & 0xff00) >> 8); | |
1014 | seq_printf(m, "Render p-state VID: %d\n", | |
1015 | gt_perf_status & 0xff); | |
1016 | seq_printf(m, "Render p-state limit: %d\n", | |
1017 | rp_state_limits & 0xff); | |
f82855d3 | 1018 | seq_printf(m, "CAGF: %dMHz\n", cagf); |
ccab5c82 JB |
1019 | seq_printf(m, "RP CUR UP EI: %dus\n", rpupei & |
1020 | GEN6_CURICONT_MASK); | |
1021 | seq_printf(m, "RP CUR UP: %dus\n", rpcurup & | |
1022 | GEN6_CURBSYTAVG_MASK); | |
1023 | seq_printf(m, "RP PREV UP: %dus\n", rpprevup & | |
1024 | GEN6_CURBSYTAVG_MASK); | |
1025 | seq_printf(m, "RP CUR DOWN EI: %dus\n", rpdownei & | |
1026 | GEN6_CURIAVG_MASK); | |
1027 | seq_printf(m, "RP CUR DOWN: %dus\n", rpcurdown & | |
1028 | GEN6_CURBSYTAVG_MASK); | |
1029 | seq_printf(m, "RP PREV DOWN: %dus\n", rpprevdown & | |
1030 | GEN6_CURBSYTAVG_MASK); | |
3b8d8d91 JB |
1031 | |
1032 | max_freq = (rp_state_cap & 0xff0000) >> 16; | |
1033 | seq_printf(m, "Lowest (RPN) frequency: %dMHz\n", | |
c8735b0c | 1034 | max_freq * GT_FREQUENCY_MULTIPLIER); |
3b8d8d91 JB |
1035 | |
1036 | max_freq = (rp_state_cap & 0xff00) >> 8; | |
1037 | seq_printf(m, "Nominal (RP1) frequency: %dMHz\n", | |
c8735b0c | 1038 | max_freq * GT_FREQUENCY_MULTIPLIER); |
3b8d8d91 JB |
1039 | |
1040 | max_freq = rp_state_cap & 0xff; | |
1041 | seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n", | |
c8735b0c | 1042 | max_freq * GT_FREQUENCY_MULTIPLIER); |
3b8d8d91 JB |
1043 | } else { |
1044 | seq_printf(m, "no P-state info available\n"); | |
1045 | } | |
f97108d1 JB |
1046 | |
1047 | return 0; | |
1048 | } | |
1049 | ||
1050 | static int i915_delayfreq_table(struct seq_file *m, void *unused) | |
1051 | { | |
1052 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1053 | struct drm_device *dev = node->minor->dev; | |
1054 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1055 | u32 delayfreq; | |
616fdb5a BW |
1056 | int ret, i; |
1057 | ||
1058 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
1059 | if (ret) | |
1060 | return ret; | |
f97108d1 JB |
1061 | |
1062 | for (i = 0; i < 16; i++) { | |
1063 | delayfreq = I915_READ(PXVFREQ_BASE + i * 4); | |
7648fa99 JB |
1064 | seq_printf(m, "P%02dVIDFREQ: 0x%08x (VID: %d)\n", i, delayfreq, |
1065 | (delayfreq & PXVFREQ_PX_MASK) >> PXVFREQ_PX_SHIFT); | |
f97108d1 JB |
1066 | } |
1067 | ||
616fdb5a BW |
1068 | mutex_unlock(&dev->struct_mutex); |
1069 | ||
f97108d1 JB |
1070 | return 0; |
1071 | } | |
1072 | ||
1073 | static inline int MAP_TO_MV(int map) | |
1074 | { | |
1075 | return 1250 - (map * 25); | |
1076 | } | |
1077 | ||
1078 | static int i915_inttoext_table(struct seq_file *m, void *unused) | |
1079 | { | |
1080 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1081 | struct drm_device *dev = node->minor->dev; | |
1082 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1083 | u32 inttoext; | |
616fdb5a BW |
1084 | int ret, i; |
1085 | ||
1086 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
1087 | if (ret) | |
1088 | return ret; | |
f97108d1 JB |
1089 | |
1090 | for (i = 1; i <= 32; i++) { | |
1091 | inttoext = I915_READ(INTTOEXT_BASE_ILK + i * 4); | |
1092 | seq_printf(m, "INTTOEXT%02d: 0x%08x\n", i, inttoext); | |
1093 | } | |
1094 | ||
616fdb5a BW |
1095 | mutex_unlock(&dev->struct_mutex); |
1096 | ||
f97108d1 JB |
1097 | return 0; |
1098 | } | |
1099 | ||
4d85529d | 1100 | static int ironlake_drpc_info(struct seq_file *m) |
f97108d1 JB |
1101 | { |
1102 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1103 | struct drm_device *dev = node->minor->dev; | |
1104 | drm_i915_private_t *dev_priv = dev->dev_private; | |
616fdb5a BW |
1105 | u32 rgvmodectl, rstdbyctl; |
1106 | u16 crstandvid; | |
1107 | int ret; | |
1108 | ||
1109 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
1110 | if (ret) | |
1111 | return ret; | |
1112 | ||
1113 | rgvmodectl = I915_READ(MEMMODECTL); | |
1114 | rstdbyctl = I915_READ(RSTDBYCTL); | |
1115 | crstandvid = I915_READ16(CRSTANDVID); | |
1116 | ||
1117 | mutex_unlock(&dev->struct_mutex); | |
f97108d1 JB |
1118 | |
1119 | seq_printf(m, "HD boost: %s\n", (rgvmodectl & MEMMODE_BOOST_EN) ? | |
1120 | "yes" : "no"); | |
1121 | seq_printf(m, "Boost freq: %d\n", | |
1122 | (rgvmodectl & MEMMODE_BOOST_FREQ_MASK) >> | |
1123 | MEMMODE_BOOST_FREQ_SHIFT); | |
1124 | seq_printf(m, "HW control enabled: %s\n", | |
1125 | rgvmodectl & MEMMODE_HWIDLE_EN ? "yes" : "no"); | |
1126 | seq_printf(m, "SW control enabled: %s\n", | |
1127 | rgvmodectl & MEMMODE_SWMODE_EN ? "yes" : "no"); | |
1128 | seq_printf(m, "Gated voltage change: %s\n", | |
1129 | rgvmodectl & MEMMODE_RCLK_GATE ? "yes" : "no"); | |
1130 | seq_printf(m, "Starting frequency: P%d\n", | |
1131 | (rgvmodectl & MEMMODE_FSTART_MASK) >> MEMMODE_FSTART_SHIFT); | |
7648fa99 | 1132 | seq_printf(m, "Max P-state: P%d\n", |
f97108d1 | 1133 | (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT); |
7648fa99 JB |
1134 | seq_printf(m, "Min P-state: P%d\n", (rgvmodectl & MEMMODE_FMIN_MASK)); |
1135 | seq_printf(m, "RS1 VID: %d\n", (crstandvid & 0x3f)); | |
1136 | seq_printf(m, "RS2 VID: %d\n", ((crstandvid >> 8) & 0x3f)); | |
1137 | seq_printf(m, "Render standby enabled: %s\n", | |
1138 | (rstdbyctl & RCX_SW_EXIT) ? "no" : "yes"); | |
88271da3 JB |
1139 | seq_printf(m, "Current RS state: "); |
1140 | switch (rstdbyctl & RSX_STATUS_MASK) { | |
1141 | case RSX_STATUS_ON: | |
1142 | seq_printf(m, "on\n"); | |
1143 | break; | |
1144 | case RSX_STATUS_RC1: | |
1145 | seq_printf(m, "RC1\n"); | |
1146 | break; | |
1147 | case RSX_STATUS_RC1E: | |
1148 | seq_printf(m, "RC1E\n"); | |
1149 | break; | |
1150 | case RSX_STATUS_RS1: | |
1151 | seq_printf(m, "RS1\n"); | |
1152 | break; | |
1153 | case RSX_STATUS_RS2: | |
1154 | seq_printf(m, "RS2 (RC6)\n"); | |
1155 | break; | |
1156 | case RSX_STATUS_RS3: | |
1157 | seq_printf(m, "RC3 (RC6+)\n"); | |
1158 | break; | |
1159 | default: | |
1160 | seq_printf(m, "unknown\n"); | |
1161 | break; | |
1162 | } | |
f97108d1 JB |
1163 | |
1164 | return 0; | |
1165 | } | |
1166 | ||
4d85529d BW |
1167 | static int gen6_drpc_info(struct seq_file *m) |
1168 | { | |
1169 | ||
1170 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1171 | struct drm_device *dev = node->minor->dev; | |
1172 | struct drm_i915_private *dev_priv = dev->dev_private; | |
ecd8faea | 1173 | u32 rpmodectl1, gt_core_status, rcctl1, rc6vids = 0; |
93b525dc | 1174 | unsigned forcewake_count; |
4d85529d BW |
1175 | int count=0, ret; |
1176 | ||
1177 | ||
1178 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
1179 | if (ret) | |
1180 | return ret; | |
1181 | ||
93b525dc DV |
1182 | spin_lock_irq(&dev_priv->gt_lock); |
1183 | forcewake_count = dev_priv->forcewake_count; | |
1184 | spin_unlock_irq(&dev_priv->gt_lock); | |
1185 | ||
1186 | if (forcewake_count) { | |
1187 | seq_printf(m, "RC information inaccurate because somebody " | |
1188 | "holds a forcewake reference \n"); | |
4d85529d BW |
1189 | } else { |
1190 | /* NB: we cannot use forcewake, else we read the wrong values */ | |
1191 | while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1)) | |
1192 | udelay(10); | |
1193 | seq_printf(m, "RC information accurate: %s\n", yesno(count < 51)); | |
1194 | } | |
1195 | ||
1196 | gt_core_status = readl(dev_priv->regs + GEN6_GT_CORE_STATUS); | |
1197 | trace_i915_reg_rw(false, GEN6_GT_CORE_STATUS, gt_core_status, 4); | |
1198 | ||
1199 | rpmodectl1 = I915_READ(GEN6_RP_CONTROL); | |
1200 | rcctl1 = I915_READ(GEN6_RC_CONTROL); | |
1201 | mutex_unlock(&dev->struct_mutex); | |
44cbd338 BW |
1202 | mutex_lock(&dev_priv->rps.hw_lock); |
1203 | sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids); | |
1204 | mutex_unlock(&dev_priv->rps.hw_lock); | |
4d85529d BW |
1205 | |
1206 | seq_printf(m, "Video Turbo Mode: %s\n", | |
1207 | yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO)); | |
1208 | seq_printf(m, "HW control enabled: %s\n", | |
1209 | yesno(rpmodectl1 & GEN6_RP_ENABLE)); | |
1210 | seq_printf(m, "SW control enabled: %s\n", | |
1211 | yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) == | |
1212 | GEN6_RP_MEDIA_SW_MODE)); | |
fff24e21 | 1213 | seq_printf(m, "RC1e Enabled: %s\n", |
4d85529d BW |
1214 | yesno(rcctl1 & GEN6_RC_CTL_RC1e_ENABLE)); |
1215 | seq_printf(m, "RC6 Enabled: %s\n", | |
1216 | yesno(rcctl1 & GEN6_RC_CTL_RC6_ENABLE)); | |
1217 | seq_printf(m, "Deep RC6 Enabled: %s\n", | |
1218 | yesno(rcctl1 & GEN6_RC_CTL_RC6p_ENABLE)); | |
1219 | seq_printf(m, "Deepest RC6 Enabled: %s\n", | |
1220 | yesno(rcctl1 & GEN6_RC_CTL_RC6pp_ENABLE)); | |
1221 | seq_printf(m, "Current RC state: "); | |
1222 | switch (gt_core_status & GEN6_RCn_MASK) { | |
1223 | case GEN6_RC0: | |
1224 | if (gt_core_status & GEN6_CORE_CPD_STATE_MASK) | |
1225 | seq_printf(m, "Core Power Down\n"); | |
1226 | else | |
1227 | seq_printf(m, "on\n"); | |
1228 | break; | |
1229 | case GEN6_RC3: | |
1230 | seq_printf(m, "RC3\n"); | |
1231 | break; | |
1232 | case GEN6_RC6: | |
1233 | seq_printf(m, "RC6\n"); | |
1234 | break; | |
1235 | case GEN6_RC7: | |
1236 | seq_printf(m, "RC7\n"); | |
1237 | break; | |
1238 | default: | |
1239 | seq_printf(m, "Unknown\n"); | |
1240 | break; | |
1241 | } | |
1242 | ||
1243 | seq_printf(m, "Core Power Down: %s\n", | |
1244 | yesno(gt_core_status & GEN6_CORE_CPD_STATE_MASK)); | |
cce66a28 BW |
1245 | |
1246 | /* Not exactly sure what this is */ | |
1247 | seq_printf(m, "RC6 \"Locked to RPn\" residency since boot: %u\n", | |
1248 | I915_READ(GEN6_GT_GFX_RC6_LOCKED)); | |
1249 | seq_printf(m, "RC6 residency since boot: %u\n", | |
1250 | I915_READ(GEN6_GT_GFX_RC6)); | |
1251 | seq_printf(m, "RC6+ residency since boot: %u\n", | |
1252 | I915_READ(GEN6_GT_GFX_RC6p)); | |
1253 | seq_printf(m, "RC6++ residency since boot: %u\n", | |
1254 | I915_READ(GEN6_GT_GFX_RC6pp)); | |
1255 | ||
ecd8faea BW |
1256 | seq_printf(m, "RC6 voltage: %dmV\n", |
1257 | GEN6_DECODE_RC6_VID(((rc6vids >> 0) & 0xff))); | |
1258 | seq_printf(m, "RC6+ voltage: %dmV\n", | |
1259 | GEN6_DECODE_RC6_VID(((rc6vids >> 8) & 0xff))); | |
1260 | seq_printf(m, "RC6++ voltage: %dmV\n", | |
1261 | GEN6_DECODE_RC6_VID(((rc6vids >> 16) & 0xff))); | |
4d85529d BW |
1262 | return 0; |
1263 | } | |
1264 | ||
1265 | static int i915_drpc_info(struct seq_file *m, void *unused) | |
1266 | { | |
1267 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1268 | struct drm_device *dev = node->minor->dev; | |
1269 | ||
1270 | if (IS_GEN6(dev) || IS_GEN7(dev)) | |
1271 | return gen6_drpc_info(m); | |
1272 | else | |
1273 | return ironlake_drpc_info(m); | |
1274 | } | |
1275 | ||
b5e50c3f JB |
1276 | static int i915_fbc_status(struct seq_file *m, void *unused) |
1277 | { | |
1278 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1279 | struct drm_device *dev = node->minor->dev; | |
b5e50c3f | 1280 | drm_i915_private_t *dev_priv = dev->dev_private; |
b5e50c3f | 1281 | |
ee5382ae | 1282 | if (!I915_HAS_FBC(dev)) { |
b5e50c3f JB |
1283 | seq_printf(m, "FBC unsupported on this chipset\n"); |
1284 | return 0; | |
1285 | } | |
1286 | ||
ee5382ae | 1287 | if (intel_fbc_enabled(dev)) { |
b5e50c3f JB |
1288 | seq_printf(m, "FBC enabled\n"); |
1289 | } else { | |
1290 | seq_printf(m, "FBC disabled: "); | |
1291 | switch (dev_priv->no_fbc_reason) { | |
bed4a673 CW |
1292 | case FBC_NO_OUTPUT: |
1293 | seq_printf(m, "no outputs"); | |
1294 | break; | |
b5e50c3f JB |
1295 | case FBC_STOLEN_TOO_SMALL: |
1296 | seq_printf(m, "not enough stolen memory"); | |
1297 | break; | |
1298 | case FBC_UNSUPPORTED_MODE: | |
1299 | seq_printf(m, "mode not supported"); | |
1300 | break; | |
1301 | case FBC_MODE_TOO_LARGE: | |
1302 | seq_printf(m, "mode too large"); | |
1303 | break; | |
1304 | case FBC_BAD_PLANE: | |
1305 | seq_printf(m, "FBC unsupported on plane"); | |
1306 | break; | |
1307 | case FBC_NOT_TILED: | |
1308 | seq_printf(m, "scanout buffer not tiled"); | |
1309 | break; | |
9c928d16 JB |
1310 | case FBC_MULTIPLE_PIPES: |
1311 | seq_printf(m, "multiple pipes are enabled"); | |
1312 | break; | |
c1a9f047 JB |
1313 | case FBC_MODULE_PARAM: |
1314 | seq_printf(m, "disabled per module param (default off)"); | |
1315 | break; | |
b5e50c3f JB |
1316 | default: |
1317 | seq_printf(m, "unknown reason"); | |
1318 | } | |
1319 | seq_printf(m, "\n"); | |
1320 | } | |
1321 | return 0; | |
1322 | } | |
1323 | ||
4a9bef37 JB |
1324 | static int i915_sr_status(struct seq_file *m, void *unused) |
1325 | { | |
1326 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1327 | struct drm_device *dev = node->minor->dev; | |
1328 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1329 | bool sr_enabled = false; | |
1330 | ||
1398261a | 1331 | if (HAS_PCH_SPLIT(dev)) |
5ba2aaaa | 1332 | sr_enabled = I915_READ(WM1_LP_ILK) & WM1_LP_SR_EN; |
a6c45cf0 | 1333 | else if (IS_CRESTLINE(dev) || IS_I945G(dev) || IS_I945GM(dev)) |
4a9bef37 JB |
1334 | sr_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN; |
1335 | else if (IS_I915GM(dev)) | |
1336 | sr_enabled = I915_READ(INSTPM) & INSTPM_SELF_EN; | |
1337 | else if (IS_PINEVIEW(dev)) | |
1338 | sr_enabled = I915_READ(DSPFW3) & PINEVIEW_SELF_REFRESH_EN; | |
1339 | ||
5ba2aaaa CW |
1340 | seq_printf(m, "self-refresh: %s\n", |
1341 | sr_enabled ? "enabled" : "disabled"); | |
4a9bef37 JB |
1342 | |
1343 | return 0; | |
1344 | } | |
1345 | ||
7648fa99 JB |
1346 | static int i915_emon_status(struct seq_file *m, void *unused) |
1347 | { | |
1348 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1349 | struct drm_device *dev = node->minor->dev; | |
1350 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1351 | unsigned long temp, chipset, gfx; | |
de227ef0 CW |
1352 | int ret; |
1353 | ||
582be6b4 CW |
1354 | if (!IS_GEN5(dev)) |
1355 | return -ENODEV; | |
1356 | ||
de227ef0 CW |
1357 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
1358 | if (ret) | |
1359 | return ret; | |
7648fa99 JB |
1360 | |
1361 | temp = i915_mch_val(dev_priv); | |
1362 | chipset = i915_chipset_val(dev_priv); | |
1363 | gfx = i915_gfx_val(dev_priv); | |
de227ef0 | 1364 | mutex_unlock(&dev->struct_mutex); |
7648fa99 JB |
1365 | |
1366 | seq_printf(m, "GMCH temp: %ld\n", temp); | |
1367 | seq_printf(m, "Chipset power: %ld\n", chipset); | |
1368 | seq_printf(m, "GFX power: %ld\n", gfx); | |
1369 | seq_printf(m, "Total power: %ld\n", chipset + gfx); | |
1370 | ||
1371 | return 0; | |
1372 | } | |
1373 | ||
23b2f8bb JB |
1374 | static int i915_ring_freq_table(struct seq_file *m, void *unused) |
1375 | { | |
1376 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1377 | struct drm_device *dev = node->minor->dev; | |
1378 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1379 | int ret; | |
1380 | int gpu_freq, ia_freq; | |
1381 | ||
1c70c0ce | 1382 | if (!(IS_GEN6(dev) || IS_GEN7(dev))) { |
23b2f8bb JB |
1383 | seq_printf(m, "unsupported on this chipset\n"); |
1384 | return 0; | |
1385 | } | |
1386 | ||
4fc688ce | 1387 | ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock); |
23b2f8bb JB |
1388 | if (ret) |
1389 | return ret; | |
1390 | ||
1391 | seq_printf(m, "GPU freq (MHz)\tEffective CPU freq (MHz)\n"); | |
1392 | ||
c6a828d3 DV |
1393 | for (gpu_freq = dev_priv->rps.min_delay; |
1394 | gpu_freq <= dev_priv->rps.max_delay; | |
23b2f8bb | 1395 | gpu_freq++) { |
42c0526c BW |
1396 | ia_freq = gpu_freq; |
1397 | sandybridge_pcode_read(dev_priv, | |
1398 | GEN6_PCODE_READ_MIN_FREQ_TABLE, | |
1399 | &ia_freq); | |
c8735b0c | 1400 | seq_printf(m, "%d\t\t%d\n", gpu_freq * GT_FREQUENCY_MULTIPLIER, ia_freq * 100); |
23b2f8bb JB |
1401 | } |
1402 | ||
4fc688ce | 1403 | mutex_unlock(&dev_priv->rps.hw_lock); |
23b2f8bb JB |
1404 | |
1405 | return 0; | |
1406 | } | |
1407 | ||
7648fa99 JB |
1408 | static int i915_gfxec(struct seq_file *m, void *unused) |
1409 | { | |
1410 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1411 | struct drm_device *dev = node->minor->dev; | |
1412 | drm_i915_private_t *dev_priv = dev->dev_private; | |
616fdb5a BW |
1413 | int ret; |
1414 | ||
1415 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
1416 | if (ret) | |
1417 | return ret; | |
7648fa99 JB |
1418 | |
1419 | seq_printf(m, "GFXEC: %ld\n", (unsigned long)I915_READ(0x112f4)); | |
1420 | ||
616fdb5a BW |
1421 | mutex_unlock(&dev->struct_mutex); |
1422 | ||
7648fa99 JB |
1423 | return 0; |
1424 | } | |
1425 | ||
44834a67 CW |
1426 | static int i915_opregion(struct seq_file *m, void *unused) |
1427 | { | |
1428 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1429 | struct drm_device *dev = node->minor->dev; | |
1430 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1431 | struct intel_opregion *opregion = &dev_priv->opregion; | |
0d38f009 | 1432 | void *data = kmalloc(OPREGION_SIZE, GFP_KERNEL); |
44834a67 CW |
1433 | int ret; |
1434 | ||
0d38f009 DV |
1435 | if (data == NULL) |
1436 | return -ENOMEM; | |
1437 | ||
44834a67 CW |
1438 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
1439 | if (ret) | |
0d38f009 | 1440 | goto out; |
44834a67 | 1441 | |
0d38f009 DV |
1442 | if (opregion->header) { |
1443 | memcpy_fromio(data, opregion->header, OPREGION_SIZE); | |
1444 | seq_write(m, data, OPREGION_SIZE); | |
1445 | } | |
44834a67 CW |
1446 | |
1447 | mutex_unlock(&dev->struct_mutex); | |
1448 | ||
0d38f009 DV |
1449 | out: |
1450 | kfree(data); | |
44834a67 CW |
1451 | return 0; |
1452 | } | |
1453 | ||
37811fcc CW |
1454 | static int i915_gem_framebuffer_info(struct seq_file *m, void *data) |
1455 | { | |
1456 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1457 | struct drm_device *dev = node->minor->dev; | |
1458 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1459 | struct intel_fbdev *ifbdev; | |
1460 | struct intel_framebuffer *fb; | |
1461 | int ret; | |
1462 | ||
1463 | ret = mutex_lock_interruptible(&dev->mode_config.mutex); | |
1464 | if (ret) | |
1465 | return ret; | |
1466 | ||
1467 | ifbdev = dev_priv->fbdev; | |
1468 | fb = to_intel_framebuffer(ifbdev->helper.fb); | |
1469 | ||
623f9783 | 1470 | seq_printf(m, "fbcon size: %d x %d, depth %d, %d bpp, refcount %d, obj ", |
37811fcc CW |
1471 | fb->base.width, |
1472 | fb->base.height, | |
1473 | fb->base.depth, | |
623f9783 DV |
1474 | fb->base.bits_per_pixel, |
1475 | atomic_read(&fb->base.refcount.refcount)); | |
05394f39 | 1476 | describe_obj(m, fb->obj); |
37811fcc | 1477 | seq_printf(m, "\n"); |
4b096ac1 | 1478 | mutex_unlock(&dev->mode_config.mutex); |
37811fcc | 1479 | |
4b096ac1 | 1480 | mutex_lock(&dev->mode_config.fb_lock); |
37811fcc CW |
1481 | list_for_each_entry(fb, &dev->mode_config.fb_list, base.head) { |
1482 | if (&fb->base == ifbdev->helper.fb) | |
1483 | continue; | |
1484 | ||
623f9783 | 1485 | seq_printf(m, "user size: %d x %d, depth %d, %d bpp, refcount %d, obj ", |
37811fcc CW |
1486 | fb->base.width, |
1487 | fb->base.height, | |
1488 | fb->base.depth, | |
623f9783 DV |
1489 | fb->base.bits_per_pixel, |
1490 | atomic_read(&fb->base.refcount.refcount)); | |
05394f39 | 1491 | describe_obj(m, fb->obj); |
37811fcc CW |
1492 | seq_printf(m, "\n"); |
1493 | } | |
4b096ac1 | 1494 | mutex_unlock(&dev->mode_config.fb_lock); |
37811fcc CW |
1495 | |
1496 | return 0; | |
1497 | } | |
1498 | ||
e76d3630 BW |
1499 | static int i915_context_status(struct seq_file *m, void *unused) |
1500 | { | |
1501 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1502 | struct drm_device *dev = node->minor->dev; | |
1503 | drm_i915_private_t *dev_priv = dev->dev_private; | |
a168c293 BW |
1504 | struct intel_ring_buffer *ring; |
1505 | int ret, i; | |
e76d3630 BW |
1506 | |
1507 | ret = mutex_lock_interruptible(&dev->mode_config.mutex); | |
1508 | if (ret) | |
1509 | return ret; | |
1510 | ||
3e373948 | 1511 | if (dev_priv->ips.pwrctx) { |
dc501fbc | 1512 | seq_printf(m, "power context "); |
3e373948 | 1513 | describe_obj(m, dev_priv->ips.pwrctx); |
dc501fbc BW |
1514 | seq_printf(m, "\n"); |
1515 | } | |
e76d3630 | 1516 | |
3e373948 | 1517 | if (dev_priv->ips.renderctx) { |
dc501fbc | 1518 | seq_printf(m, "render context "); |
3e373948 | 1519 | describe_obj(m, dev_priv->ips.renderctx); |
dc501fbc BW |
1520 | seq_printf(m, "\n"); |
1521 | } | |
e76d3630 | 1522 | |
a168c293 BW |
1523 | for_each_ring(ring, dev_priv, i) { |
1524 | if (ring->default_context) { | |
1525 | seq_printf(m, "HW default context %s ring ", ring->name); | |
1526 | describe_obj(m, ring->default_context->obj); | |
1527 | seq_printf(m, "\n"); | |
1528 | } | |
1529 | } | |
1530 | ||
e76d3630 BW |
1531 | mutex_unlock(&dev->mode_config.mutex); |
1532 | ||
1533 | return 0; | |
1534 | } | |
1535 | ||
6d794d42 BW |
1536 | static int i915_gen6_forcewake_count_info(struct seq_file *m, void *data) |
1537 | { | |
1538 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1539 | struct drm_device *dev = node->minor->dev; | |
1540 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9f1f46a4 | 1541 | unsigned forcewake_count; |
6d794d42 | 1542 | |
9f1f46a4 DV |
1543 | spin_lock_irq(&dev_priv->gt_lock); |
1544 | forcewake_count = dev_priv->forcewake_count; | |
1545 | spin_unlock_irq(&dev_priv->gt_lock); | |
6d794d42 | 1546 | |
9f1f46a4 | 1547 | seq_printf(m, "forcewake count = %u\n", forcewake_count); |
6d794d42 BW |
1548 | |
1549 | return 0; | |
1550 | } | |
1551 | ||
ea16a3cd DV |
1552 | static const char *swizzle_string(unsigned swizzle) |
1553 | { | |
1554 | switch(swizzle) { | |
1555 | case I915_BIT_6_SWIZZLE_NONE: | |
1556 | return "none"; | |
1557 | case I915_BIT_6_SWIZZLE_9: | |
1558 | return "bit9"; | |
1559 | case I915_BIT_6_SWIZZLE_9_10: | |
1560 | return "bit9/bit10"; | |
1561 | case I915_BIT_6_SWIZZLE_9_11: | |
1562 | return "bit9/bit11"; | |
1563 | case I915_BIT_6_SWIZZLE_9_10_11: | |
1564 | return "bit9/bit10/bit11"; | |
1565 | case I915_BIT_6_SWIZZLE_9_17: | |
1566 | return "bit9/bit17"; | |
1567 | case I915_BIT_6_SWIZZLE_9_10_17: | |
1568 | return "bit9/bit10/bit17"; | |
1569 | case I915_BIT_6_SWIZZLE_UNKNOWN: | |
1570 | return "unkown"; | |
1571 | } | |
1572 | ||
1573 | return "bug"; | |
1574 | } | |
1575 | ||
1576 | static int i915_swizzle_info(struct seq_file *m, void *data) | |
1577 | { | |
1578 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1579 | struct drm_device *dev = node->minor->dev; | |
1580 | struct drm_i915_private *dev_priv = dev->dev_private; | |
22bcfc6a DV |
1581 | int ret; |
1582 | ||
1583 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
1584 | if (ret) | |
1585 | return ret; | |
ea16a3cd | 1586 | |
ea16a3cd DV |
1587 | seq_printf(m, "bit6 swizzle for X-tiling = %s\n", |
1588 | swizzle_string(dev_priv->mm.bit_6_swizzle_x)); | |
1589 | seq_printf(m, "bit6 swizzle for Y-tiling = %s\n", | |
1590 | swizzle_string(dev_priv->mm.bit_6_swizzle_y)); | |
1591 | ||
1592 | if (IS_GEN3(dev) || IS_GEN4(dev)) { | |
1593 | seq_printf(m, "DDC = 0x%08x\n", | |
1594 | I915_READ(DCC)); | |
1595 | seq_printf(m, "C0DRB3 = 0x%04x\n", | |
1596 | I915_READ16(C0DRB3)); | |
1597 | seq_printf(m, "C1DRB3 = 0x%04x\n", | |
1598 | I915_READ16(C1DRB3)); | |
3fa7d235 DV |
1599 | } else if (IS_GEN6(dev) || IS_GEN7(dev)) { |
1600 | seq_printf(m, "MAD_DIMM_C0 = 0x%08x\n", | |
1601 | I915_READ(MAD_DIMM_C0)); | |
1602 | seq_printf(m, "MAD_DIMM_C1 = 0x%08x\n", | |
1603 | I915_READ(MAD_DIMM_C1)); | |
1604 | seq_printf(m, "MAD_DIMM_C2 = 0x%08x\n", | |
1605 | I915_READ(MAD_DIMM_C2)); | |
1606 | seq_printf(m, "TILECTL = 0x%08x\n", | |
1607 | I915_READ(TILECTL)); | |
1608 | seq_printf(m, "ARB_MODE = 0x%08x\n", | |
1609 | I915_READ(ARB_MODE)); | |
1610 | seq_printf(m, "DISP_ARB_CTL = 0x%08x\n", | |
1611 | I915_READ(DISP_ARB_CTL)); | |
ea16a3cd DV |
1612 | } |
1613 | mutex_unlock(&dev->struct_mutex); | |
1614 | ||
1615 | return 0; | |
1616 | } | |
1617 | ||
3cf17fc5 DV |
1618 | static int i915_ppgtt_info(struct seq_file *m, void *data) |
1619 | { | |
1620 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1621 | struct drm_device *dev = node->minor->dev; | |
1622 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1623 | struct intel_ring_buffer *ring; | |
1624 | int i, ret; | |
1625 | ||
1626 | ||
1627 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
1628 | if (ret) | |
1629 | return ret; | |
1630 | if (INTEL_INFO(dev)->gen == 6) | |
1631 | seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(GFX_MODE)); | |
1632 | ||
a2c7f6fd | 1633 | for_each_ring(ring, dev_priv, i) { |
3cf17fc5 DV |
1634 | seq_printf(m, "%s\n", ring->name); |
1635 | if (INTEL_INFO(dev)->gen == 7) | |
1636 | seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(RING_MODE_GEN7(ring))); | |
1637 | seq_printf(m, "PP_DIR_BASE: 0x%08x\n", I915_READ(RING_PP_DIR_BASE(ring))); | |
1638 | seq_printf(m, "PP_DIR_BASE_READ: 0x%08x\n", I915_READ(RING_PP_DIR_BASE_READ(ring))); | |
1639 | seq_printf(m, "PP_DIR_DCLV: 0x%08x\n", I915_READ(RING_PP_DIR_DCLV(ring))); | |
1640 | } | |
1641 | if (dev_priv->mm.aliasing_ppgtt) { | |
1642 | struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt; | |
1643 | ||
1644 | seq_printf(m, "aliasing PPGTT:\n"); | |
1645 | seq_printf(m, "pd gtt offset: 0x%08x\n", ppgtt->pd_offset); | |
1646 | } | |
1647 | seq_printf(m, "ECOCHK: 0x%08x\n", I915_READ(GAM_ECOCHK)); | |
1648 | mutex_unlock(&dev->struct_mutex); | |
1649 | ||
1650 | return 0; | |
1651 | } | |
1652 | ||
57f350b6 JB |
1653 | static int i915_dpio_info(struct seq_file *m, void *data) |
1654 | { | |
1655 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1656 | struct drm_device *dev = node->minor->dev; | |
1657 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1658 | int ret; | |
1659 | ||
1660 | ||
1661 | if (!IS_VALLEYVIEW(dev)) { | |
1662 | seq_printf(m, "unsupported\n"); | |
1663 | return 0; | |
1664 | } | |
1665 | ||
09153000 | 1666 | ret = mutex_lock_interruptible(&dev_priv->dpio_lock); |
57f350b6 JB |
1667 | if (ret) |
1668 | return ret; | |
1669 | ||
1670 | seq_printf(m, "DPIO_CTL: 0x%08x\n", I915_READ(DPIO_CTL)); | |
1671 | ||
1672 | seq_printf(m, "DPIO_DIV_A: 0x%08x\n", | |
1673 | intel_dpio_read(dev_priv, _DPIO_DIV_A)); | |
1674 | seq_printf(m, "DPIO_DIV_B: 0x%08x\n", | |
1675 | intel_dpio_read(dev_priv, _DPIO_DIV_B)); | |
1676 | ||
1677 | seq_printf(m, "DPIO_REFSFR_A: 0x%08x\n", | |
1678 | intel_dpio_read(dev_priv, _DPIO_REFSFR_A)); | |
1679 | seq_printf(m, "DPIO_REFSFR_B: 0x%08x\n", | |
1680 | intel_dpio_read(dev_priv, _DPIO_REFSFR_B)); | |
1681 | ||
1682 | seq_printf(m, "DPIO_CORE_CLK_A: 0x%08x\n", | |
1683 | intel_dpio_read(dev_priv, _DPIO_CORE_CLK_A)); | |
1684 | seq_printf(m, "DPIO_CORE_CLK_B: 0x%08x\n", | |
1685 | intel_dpio_read(dev_priv, _DPIO_CORE_CLK_B)); | |
1686 | ||
1687 | seq_printf(m, "DPIO_LFP_COEFF_A: 0x%08x\n", | |
1688 | intel_dpio_read(dev_priv, _DPIO_LFP_COEFF_A)); | |
1689 | seq_printf(m, "DPIO_LFP_COEFF_B: 0x%08x\n", | |
1690 | intel_dpio_read(dev_priv, _DPIO_LFP_COEFF_B)); | |
1691 | ||
1692 | seq_printf(m, "DPIO_FASTCLK_DISABLE: 0x%08x\n", | |
1693 | intel_dpio_read(dev_priv, DPIO_FASTCLK_DISABLE)); | |
1694 | ||
09153000 | 1695 | mutex_unlock(&dev_priv->dpio_lock); |
57f350b6 JB |
1696 | |
1697 | return 0; | |
1698 | } | |
1699 | ||
f3cd474b CW |
1700 | static ssize_t |
1701 | i915_wedged_read(struct file *filp, | |
1702 | char __user *ubuf, | |
1703 | size_t max, | |
1704 | loff_t *ppos) | |
1705 | { | |
1706 | struct drm_device *dev = filp->private_data; | |
1707 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1708 | char buf[80]; | |
1709 | int len; | |
1710 | ||
0206e353 | 1711 | len = snprintf(buf, sizeof(buf), |
f3cd474b | 1712 | "wedged : %d\n", |
1f83fee0 | 1713 | atomic_read(&dev_priv->gpu_error.reset_counter)); |
f3cd474b | 1714 | |
0206e353 AJ |
1715 | if (len > sizeof(buf)) |
1716 | len = sizeof(buf); | |
f4433a8d | 1717 | |
f3cd474b CW |
1718 | return simple_read_from_buffer(ubuf, max, ppos, buf, len); |
1719 | } | |
1720 | ||
1721 | static ssize_t | |
1722 | i915_wedged_write(struct file *filp, | |
1723 | const char __user *ubuf, | |
1724 | size_t cnt, | |
1725 | loff_t *ppos) | |
1726 | { | |
1727 | struct drm_device *dev = filp->private_data; | |
f3cd474b CW |
1728 | char buf[20]; |
1729 | int val = 1; | |
1730 | ||
1731 | if (cnt > 0) { | |
0206e353 | 1732 | if (cnt > sizeof(buf) - 1) |
f3cd474b CW |
1733 | return -EINVAL; |
1734 | ||
1735 | if (copy_from_user(buf, ubuf, cnt)) | |
1736 | return -EFAULT; | |
1737 | buf[cnt] = 0; | |
1738 | ||
1739 | val = simple_strtoul(buf, NULL, 0); | |
1740 | } | |
1741 | ||
1742 | DRM_INFO("Manually setting wedged to %d\n", val); | |
527f9e90 | 1743 | i915_handle_error(dev, val); |
f3cd474b CW |
1744 | |
1745 | return cnt; | |
1746 | } | |
1747 | ||
1748 | static const struct file_operations i915_wedged_fops = { | |
1749 | .owner = THIS_MODULE, | |
234e3405 | 1750 | .open = simple_open, |
f3cd474b CW |
1751 | .read = i915_wedged_read, |
1752 | .write = i915_wedged_write, | |
6038f373 | 1753 | .llseek = default_llseek, |
f3cd474b CW |
1754 | }; |
1755 | ||
e5eb3d63 DV |
1756 | static ssize_t |
1757 | i915_ring_stop_read(struct file *filp, | |
1758 | char __user *ubuf, | |
1759 | size_t max, | |
1760 | loff_t *ppos) | |
1761 | { | |
1762 | struct drm_device *dev = filp->private_data; | |
1763 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1764 | char buf[20]; | |
1765 | int len; | |
1766 | ||
1767 | len = snprintf(buf, sizeof(buf), | |
99584db3 | 1768 | "0x%08x\n", dev_priv->gpu_error.stop_rings); |
e5eb3d63 DV |
1769 | |
1770 | if (len > sizeof(buf)) | |
1771 | len = sizeof(buf); | |
1772 | ||
1773 | return simple_read_from_buffer(ubuf, max, ppos, buf, len); | |
1774 | } | |
1775 | ||
1776 | static ssize_t | |
1777 | i915_ring_stop_write(struct file *filp, | |
1778 | const char __user *ubuf, | |
1779 | size_t cnt, | |
1780 | loff_t *ppos) | |
1781 | { | |
1782 | struct drm_device *dev = filp->private_data; | |
1783 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1784 | char buf[20]; | |
22bcfc6a | 1785 | int val = 0, ret; |
e5eb3d63 DV |
1786 | |
1787 | if (cnt > 0) { | |
1788 | if (cnt > sizeof(buf) - 1) | |
1789 | return -EINVAL; | |
1790 | ||
1791 | if (copy_from_user(buf, ubuf, cnt)) | |
1792 | return -EFAULT; | |
1793 | buf[cnt] = 0; | |
1794 | ||
1795 | val = simple_strtoul(buf, NULL, 0); | |
1796 | } | |
1797 | ||
1798 | DRM_DEBUG_DRIVER("Stopping rings 0x%08x\n", val); | |
1799 | ||
22bcfc6a DV |
1800 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
1801 | if (ret) | |
1802 | return ret; | |
1803 | ||
99584db3 | 1804 | dev_priv->gpu_error.stop_rings = val; |
e5eb3d63 DV |
1805 | mutex_unlock(&dev->struct_mutex); |
1806 | ||
1807 | return cnt; | |
1808 | } | |
1809 | ||
1810 | static const struct file_operations i915_ring_stop_fops = { | |
1811 | .owner = THIS_MODULE, | |
1812 | .open = simple_open, | |
1813 | .read = i915_ring_stop_read, | |
1814 | .write = i915_ring_stop_write, | |
1815 | .llseek = default_llseek, | |
1816 | }; | |
d5442303 | 1817 | |
dd624afd CW |
1818 | #define DROP_UNBOUND 0x1 |
1819 | #define DROP_BOUND 0x2 | |
1820 | #define DROP_RETIRE 0x4 | |
1821 | #define DROP_ACTIVE 0x8 | |
1822 | #define DROP_ALL (DROP_UNBOUND | \ | |
1823 | DROP_BOUND | \ | |
1824 | DROP_RETIRE | \ | |
1825 | DROP_ACTIVE) | |
1826 | static ssize_t | |
1827 | i915_drop_caches_read(struct file *filp, | |
1828 | char __user *ubuf, | |
1829 | size_t max, | |
1830 | loff_t *ppos) | |
1831 | { | |
1832 | char buf[20]; | |
1833 | int len; | |
1834 | ||
1835 | len = snprintf(buf, sizeof(buf), "0x%08x\n", DROP_ALL); | |
1836 | if (len > sizeof(buf)) | |
1837 | len = sizeof(buf); | |
1838 | ||
1839 | return simple_read_from_buffer(ubuf, max, ppos, buf, len); | |
1840 | } | |
1841 | ||
1842 | static ssize_t | |
1843 | i915_drop_caches_write(struct file *filp, | |
1844 | const char __user *ubuf, | |
1845 | size_t cnt, | |
1846 | loff_t *ppos) | |
1847 | { | |
1848 | struct drm_device *dev = filp->private_data; | |
1849 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1850 | struct drm_i915_gem_object *obj, *next; | |
1851 | char buf[20]; | |
1852 | int val = 0, ret; | |
1853 | ||
1854 | if (cnt > 0) { | |
1855 | if (cnt > sizeof(buf) - 1) | |
1856 | return -EINVAL; | |
1857 | ||
1858 | if (copy_from_user(buf, ubuf, cnt)) | |
1859 | return -EFAULT; | |
1860 | buf[cnt] = 0; | |
1861 | ||
1862 | val = simple_strtoul(buf, NULL, 0); | |
1863 | } | |
1864 | ||
1865 | DRM_DEBUG_DRIVER("Dropping caches: 0x%08x\n", val); | |
1866 | ||
1867 | /* No need to check and wait for gpu resets, only libdrm auto-restarts | |
1868 | * on ioctls on -EAGAIN. */ | |
1869 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
1870 | if (ret) | |
1871 | return ret; | |
1872 | ||
1873 | if (val & DROP_ACTIVE) { | |
1874 | ret = i915_gpu_idle(dev); | |
1875 | if (ret) | |
1876 | goto unlock; | |
1877 | } | |
1878 | ||
1879 | if (val & (DROP_RETIRE | DROP_ACTIVE)) | |
1880 | i915_gem_retire_requests(dev); | |
1881 | ||
1882 | if (val & DROP_BOUND) { | |
1883 | list_for_each_entry_safe(obj, next, &dev_priv->mm.inactive_list, mm_list) | |
1884 | if (obj->pin_count == 0) { | |
1885 | ret = i915_gem_object_unbind(obj); | |
1886 | if (ret) | |
1887 | goto unlock; | |
1888 | } | |
1889 | } | |
1890 | ||
1891 | if (val & DROP_UNBOUND) { | |
1892 | list_for_each_entry_safe(obj, next, &dev_priv->mm.unbound_list, gtt_list) | |
1893 | if (obj->pages_pin_count == 0) { | |
1894 | ret = i915_gem_object_put_pages(obj); | |
1895 | if (ret) | |
1896 | goto unlock; | |
1897 | } | |
1898 | } | |
1899 | ||
1900 | unlock: | |
1901 | mutex_unlock(&dev->struct_mutex); | |
1902 | ||
1903 | return ret ?: cnt; | |
1904 | } | |
1905 | ||
1906 | static const struct file_operations i915_drop_caches_fops = { | |
1907 | .owner = THIS_MODULE, | |
1908 | .open = simple_open, | |
1909 | .read = i915_drop_caches_read, | |
1910 | .write = i915_drop_caches_write, | |
1911 | .llseek = default_llseek, | |
1912 | }; | |
1913 | ||
358733e9 JB |
1914 | static ssize_t |
1915 | i915_max_freq_read(struct file *filp, | |
1916 | char __user *ubuf, | |
1917 | size_t max, | |
1918 | loff_t *ppos) | |
1919 | { | |
1920 | struct drm_device *dev = filp->private_data; | |
1921 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1922 | char buf[80]; | |
004777cb DV |
1923 | int len, ret; |
1924 | ||
1925 | if (!(IS_GEN6(dev) || IS_GEN7(dev))) | |
1926 | return -ENODEV; | |
1927 | ||
4fc688ce | 1928 | ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock); |
004777cb DV |
1929 | if (ret) |
1930 | return ret; | |
358733e9 | 1931 | |
0206e353 | 1932 | len = snprintf(buf, sizeof(buf), |
c8735b0c | 1933 | "max freq: %d\n", dev_priv->rps.max_delay * GT_FREQUENCY_MULTIPLIER); |
4fc688ce | 1934 | mutex_unlock(&dev_priv->rps.hw_lock); |
358733e9 | 1935 | |
0206e353 AJ |
1936 | if (len > sizeof(buf)) |
1937 | len = sizeof(buf); | |
358733e9 JB |
1938 | |
1939 | return simple_read_from_buffer(ubuf, max, ppos, buf, len); | |
1940 | } | |
1941 | ||
1942 | static ssize_t | |
1943 | i915_max_freq_write(struct file *filp, | |
1944 | const char __user *ubuf, | |
1945 | size_t cnt, | |
1946 | loff_t *ppos) | |
1947 | { | |
1948 | struct drm_device *dev = filp->private_data; | |
1949 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1950 | char buf[20]; | |
004777cb DV |
1951 | int val = 1, ret; |
1952 | ||
1953 | if (!(IS_GEN6(dev) || IS_GEN7(dev))) | |
1954 | return -ENODEV; | |
358733e9 JB |
1955 | |
1956 | if (cnt > 0) { | |
0206e353 | 1957 | if (cnt > sizeof(buf) - 1) |
358733e9 JB |
1958 | return -EINVAL; |
1959 | ||
1960 | if (copy_from_user(buf, ubuf, cnt)) | |
1961 | return -EFAULT; | |
1962 | buf[cnt] = 0; | |
1963 | ||
1964 | val = simple_strtoul(buf, NULL, 0); | |
1965 | } | |
1966 | ||
1967 | DRM_DEBUG_DRIVER("Manually setting max freq to %d\n", val); | |
1968 | ||
4fc688ce | 1969 | ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock); |
004777cb DV |
1970 | if (ret) |
1971 | return ret; | |
1972 | ||
358733e9 JB |
1973 | /* |
1974 | * Turbo will still be enabled, but won't go above the set value. | |
1975 | */ | |
c8735b0c | 1976 | dev_priv->rps.max_delay = val / GT_FREQUENCY_MULTIPLIER; |
358733e9 | 1977 | |
c8735b0c | 1978 | gen6_set_rps(dev, val / GT_FREQUENCY_MULTIPLIER); |
4fc688ce | 1979 | mutex_unlock(&dev_priv->rps.hw_lock); |
358733e9 JB |
1980 | |
1981 | return cnt; | |
1982 | } | |
1983 | ||
1984 | static const struct file_operations i915_max_freq_fops = { | |
1985 | .owner = THIS_MODULE, | |
234e3405 | 1986 | .open = simple_open, |
358733e9 JB |
1987 | .read = i915_max_freq_read, |
1988 | .write = i915_max_freq_write, | |
1989 | .llseek = default_llseek, | |
1990 | }; | |
1991 | ||
1523c310 JB |
1992 | static ssize_t |
1993 | i915_min_freq_read(struct file *filp, char __user *ubuf, size_t max, | |
1994 | loff_t *ppos) | |
1995 | { | |
1996 | struct drm_device *dev = filp->private_data; | |
1997 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1998 | char buf[80]; | |
004777cb DV |
1999 | int len, ret; |
2000 | ||
2001 | if (!(IS_GEN6(dev) || IS_GEN7(dev))) | |
2002 | return -ENODEV; | |
2003 | ||
4fc688ce | 2004 | ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock); |
004777cb DV |
2005 | if (ret) |
2006 | return ret; | |
1523c310 JB |
2007 | |
2008 | len = snprintf(buf, sizeof(buf), | |
c8735b0c | 2009 | "min freq: %d\n", dev_priv->rps.min_delay * GT_FREQUENCY_MULTIPLIER); |
4fc688ce | 2010 | mutex_unlock(&dev_priv->rps.hw_lock); |
1523c310 JB |
2011 | |
2012 | if (len > sizeof(buf)) | |
2013 | len = sizeof(buf); | |
2014 | ||
2015 | return simple_read_from_buffer(ubuf, max, ppos, buf, len); | |
2016 | } | |
2017 | ||
2018 | static ssize_t | |
2019 | i915_min_freq_write(struct file *filp, const char __user *ubuf, size_t cnt, | |
2020 | loff_t *ppos) | |
2021 | { | |
2022 | struct drm_device *dev = filp->private_data; | |
2023 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2024 | char buf[20]; | |
004777cb DV |
2025 | int val = 1, ret; |
2026 | ||
2027 | if (!(IS_GEN6(dev) || IS_GEN7(dev))) | |
2028 | return -ENODEV; | |
1523c310 JB |
2029 | |
2030 | if (cnt > 0) { | |
2031 | if (cnt > sizeof(buf) - 1) | |
2032 | return -EINVAL; | |
2033 | ||
2034 | if (copy_from_user(buf, ubuf, cnt)) | |
2035 | return -EFAULT; | |
2036 | buf[cnt] = 0; | |
2037 | ||
2038 | val = simple_strtoul(buf, NULL, 0); | |
2039 | } | |
2040 | ||
2041 | DRM_DEBUG_DRIVER("Manually setting min freq to %d\n", val); | |
2042 | ||
4fc688ce | 2043 | ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock); |
004777cb DV |
2044 | if (ret) |
2045 | return ret; | |
2046 | ||
1523c310 JB |
2047 | /* |
2048 | * Turbo will still be enabled, but won't go below the set value. | |
2049 | */ | |
c8735b0c | 2050 | dev_priv->rps.min_delay = val / GT_FREQUENCY_MULTIPLIER; |
1523c310 | 2051 | |
c8735b0c | 2052 | gen6_set_rps(dev, val / GT_FREQUENCY_MULTIPLIER); |
4fc688ce | 2053 | mutex_unlock(&dev_priv->rps.hw_lock); |
1523c310 JB |
2054 | |
2055 | return cnt; | |
2056 | } | |
2057 | ||
2058 | static const struct file_operations i915_min_freq_fops = { | |
2059 | .owner = THIS_MODULE, | |
2060 | .open = simple_open, | |
2061 | .read = i915_min_freq_read, | |
2062 | .write = i915_min_freq_write, | |
2063 | .llseek = default_llseek, | |
2064 | }; | |
2065 | ||
07b7ddd9 JB |
2066 | static ssize_t |
2067 | i915_cache_sharing_read(struct file *filp, | |
2068 | char __user *ubuf, | |
2069 | size_t max, | |
2070 | loff_t *ppos) | |
2071 | { | |
2072 | struct drm_device *dev = filp->private_data; | |
2073 | drm_i915_private_t *dev_priv = dev->dev_private; | |
2074 | char buf[80]; | |
2075 | u32 snpcr; | |
22bcfc6a | 2076 | int len, ret; |
07b7ddd9 | 2077 | |
004777cb DV |
2078 | if (!(IS_GEN6(dev) || IS_GEN7(dev))) |
2079 | return -ENODEV; | |
2080 | ||
22bcfc6a DV |
2081 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
2082 | if (ret) | |
2083 | return ret; | |
2084 | ||
07b7ddd9 JB |
2085 | snpcr = I915_READ(GEN6_MBCUNIT_SNPCR); |
2086 | mutex_unlock(&dev_priv->dev->struct_mutex); | |
2087 | ||
0206e353 | 2088 | len = snprintf(buf, sizeof(buf), |
07b7ddd9 JB |
2089 | "%d\n", (snpcr & GEN6_MBC_SNPCR_MASK) >> |
2090 | GEN6_MBC_SNPCR_SHIFT); | |
2091 | ||
0206e353 AJ |
2092 | if (len > sizeof(buf)) |
2093 | len = sizeof(buf); | |
07b7ddd9 JB |
2094 | |
2095 | return simple_read_from_buffer(ubuf, max, ppos, buf, len); | |
2096 | } | |
2097 | ||
2098 | static ssize_t | |
2099 | i915_cache_sharing_write(struct file *filp, | |
2100 | const char __user *ubuf, | |
2101 | size_t cnt, | |
2102 | loff_t *ppos) | |
2103 | { | |
2104 | struct drm_device *dev = filp->private_data; | |
2105 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2106 | char buf[20]; | |
2107 | u32 snpcr; | |
2108 | int val = 1; | |
2109 | ||
004777cb DV |
2110 | if (!(IS_GEN6(dev) || IS_GEN7(dev))) |
2111 | return -ENODEV; | |
2112 | ||
07b7ddd9 | 2113 | if (cnt > 0) { |
0206e353 | 2114 | if (cnt > sizeof(buf) - 1) |
07b7ddd9 JB |
2115 | return -EINVAL; |
2116 | ||
2117 | if (copy_from_user(buf, ubuf, cnt)) | |
2118 | return -EFAULT; | |
2119 | buf[cnt] = 0; | |
2120 | ||
2121 | val = simple_strtoul(buf, NULL, 0); | |
2122 | } | |
2123 | ||
2124 | if (val < 0 || val > 3) | |
2125 | return -EINVAL; | |
2126 | ||
2127 | DRM_DEBUG_DRIVER("Manually setting uncore sharing to %d\n", val); | |
2128 | ||
2129 | /* Update the cache sharing policy here as well */ | |
2130 | snpcr = I915_READ(GEN6_MBCUNIT_SNPCR); | |
2131 | snpcr &= ~GEN6_MBC_SNPCR_MASK; | |
2132 | snpcr |= (val << GEN6_MBC_SNPCR_SHIFT); | |
2133 | I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr); | |
2134 | ||
2135 | return cnt; | |
2136 | } | |
2137 | ||
2138 | static const struct file_operations i915_cache_sharing_fops = { | |
2139 | .owner = THIS_MODULE, | |
234e3405 | 2140 | .open = simple_open, |
07b7ddd9 JB |
2141 | .read = i915_cache_sharing_read, |
2142 | .write = i915_cache_sharing_write, | |
2143 | .llseek = default_llseek, | |
2144 | }; | |
2145 | ||
f3cd474b CW |
2146 | /* As the drm_debugfs_init() routines are called before dev->dev_private is |
2147 | * allocated we need to hook into the minor for release. */ | |
2148 | static int | |
2149 | drm_add_fake_info_node(struct drm_minor *minor, | |
2150 | struct dentry *ent, | |
2151 | const void *key) | |
2152 | { | |
2153 | struct drm_info_node *node; | |
2154 | ||
2155 | node = kmalloc(sizeof(struct drm_info_node), GFP_KERNEL); | |
2156 | if (node == NULL) { | |
2157 | debugfs_remove(ent); | |
2158 | return -ENOMEM; | |
2159 | } | |
2160 | ||
2161 | node->minor = minor; | |
2162 | node->dent = ent; | |
2163 | node->info_ent = (void *) key; | |
b3e067c0 MS |
2164 | |
2165 | mutex_lock(&minor->debugfs_lock); | |
2166 | list_add(&node->list, &minor->debugfs_list); | |
2167 | mutex_unlock(&minor->debugfs_lock); | |
f3cd474b CW |
2168 | |
2169 | return 0; | |
2170 | } | |
2171 | ||
6d794d42 BW |
2172 | static int i915_forcewake_open(struct inode *inode, struct file *file) |
2173 | { | |
2174 | struct drm_device *dev = inode->i_private; | |
2175 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6d794d42 | 2176 | |
075edca4 | 2177 | if (INTEL_INFO(dev)->gen < 6) |
6d794d42 BW |
2178 | return 0; |
2179 | ||
6d794d42 | 2180 | gen6_gt_force_wake_get(dev_priv); |
6d794d42 BW |
2181 | |
2182 | return 0; | |
2183 | } | |
2184 | ||
c43b5634 | 2185 | static int i915_forcewake_release(struct inode *inode, struct file *file) |
6d794d42 BW |
2186 | { |
2187 | struct drm_device *dev = inode->i_private; | |
2188 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2189 | ||
075edca4 | 2190 | if (INTEL_INFO(dev)->gen < 6) |
6d794d42 BW |
2191 | return 0; |
2192 | ||
6d794d42 | 2193 | gen6_gt_force_wake_put(dev_priv); |
6d794d42 BW |
2194 | |
2195 | return 0; | |
2196 | } | |
2197 | ||
2198 | static const struct file_operations i915_forcewake_fops = { | |
2199 | .owner = THIS_MODULE, | |
2200 | .open = i915_forcewake_open, | |
2201 | .release = i915_forcewake_release, | |
2202 | }; | |
2203 | ||
2204 | static int i915_forcewake_create(struct dentry *root, struct drm_minor *minor) | |
2205 | { | |
2206 | struct drm_device *dev = minor->dev; | |
2207 | struct dentry *ent; | |
2208 | ||
2209 | ent = debugfs_create_file("i915_forcewake_user", | |
8eb57294 | 2210 | S_IRUSR, |
6d794d42 BW |
2211 | root, dev, |
2212 | &i915_forcewake_fops); | |
2213 | if (IS_ERR(ent)) | |
2214 | return PTR_ERR(ent); | |
2215 | ||
8eb57294 | 2216 | return drm_add_fake_info_node(minor, ent, &i915_forcewake_fops); |
6d794d42 BW |
2217 | } |
2218 | ||
6a9c308d DV |
2219 | static int i915_debugfs_create(struct dentry *root, |
2220 | struct drm_minor *minor, | |
2221 | const char *name, | |
2222 | const struct file_operations *fops) | |
07b7ddd9 JB |
2223 | { |
2224 | struct drm_device *dev = minor->dev; | |
2225 | struct dentry *ent; | |
2226 | ||
6a9c308d | 2227 | ent = debugfs_create_file(name, |
07b7ddd9 JB |
2228 | S_IRUGO | S_IWUSR, |
2229 | root, dev, | |
6a9c308d | 2230 | fops); |
07b7ddd9 JB |
2231 | if (IS_ERR(ent)) |
2232 | return PTR_ERR(ent); | |
2233 | ||
6a9c308d | 2234 | return drm_add_fake_info_node(minor, ent, fops); |
07b7ddd9 JB |
2235 | } |
2236 | ||
27c202ad | 2237 | static struct drm_info_list i915_debugfs_list[] = { |
311bd68e | 2238 | {"i915_capabilities", i915_capabilities, 0}, |
73aa808f | 2239 | {"i915_gem_objects", i915_gem_object_info, 0}, |
08c18323 | 2240 | {"i915_gem_gtt", i915_gem_gtt_info, 0}, |
1b50247a | 2241 | {"i915_gem_pinned", i915_gem_gtt_info, 0, (void *) PINNED_LIST}, |
433e12f7 | 2242 | {"i915_gem_active", i915_gem_object_list_info, 0, (void *) ACTIVE_LIST}, |
433e12f7 | 2243 | {"i915_gem_inactive", i915_gem_object_list_info, 0, (void *) INACTIVE_LIST}, |
4e5359cd | 2244 | {"i915_gem_pageflip", i915_gem_pageflip_info, 0}, |
2017263e BG |
2245 | {"i915_gem_request", i915_gem_request_info, 0}, |
2246 | {"i915_gem_seqno", i915_gem_seqno_info, 0}, | |
a6172a80 | 2247 | {"i915_gem_fence_regs", i915_gem_fence_regs_info, 0}, |
2017263e | 2248 | {"i915_gem_interrupt", i915_interrupt_info, 0}, |
1ec14ad3 CW |
2249 | {"i915_gem_hws", i915_hws_info, 0, (void *)RCS}, |
2250 | {"i915_gem_hws_blt", i915_hws_info, 0, (void *)BCS}, | |
2251 | {"i915_gem_hws_bsd", i915_hws_info, 0, (void *)VCS}, | |
f97108d1 JB |
2252 | {"i915_rstdby_delays", i915_rstdby_delays, 0}, |
2253 | {"i915_cur_delayinfo", i915_cur_delayinfo, 0}, | |
2254 | {"i915_delayfreq_table", i915_delayfreq_table, 0}, | |
2255 | {"i915_inttoext_table", i915_inttoext_table, 0}, | |
2256 | {"i915_drpc_info", i915_drpc_info, 0}, | |
7648fa99 | 2257 | {"i915_emon_status", i915_emon_status, 0}, |
23b2f8bb | 2258 | {"i915_ring_freq_table", i915_ring_freq_table, 0}, |
7648fa99 | 2259 | {"i915_gfxec", i915_gfxec, 0}, |
b5e50c3f | 2260 | {"i915_fbc_status", i915_fbc_status, 0}, |
4a9bef37 | 2261 | {"i915_sr_status", i915_sr_status, 0}, |
44834a67 | 2262 | {"i915_opregion", i915_opregion, 0}, |
37811fcc | 2263 | {"i915_gem_framebuffer", i915_gem_framebuffer_info, 0}, |
e76d3630 | 2264 | {"i915_context_status", i915_context_status, 0}, |
6d794d42 | 2265 | {"i915_gen6_forcewake_count", i915_gen6_forcewake_count_info, 0}, |
ea16a3cd | 2266 | {"i915_swizzle_info", i915_swizzle_info, 0}, |
3cf17fc5 | 2267 | {"i915_ppgtt_info", i915_ppgtt_info, 0}, |
57f350b6 | 2268 | {"i915_dpio", i915_dpio_info, 0}, |
2017263e | 2269 | }; |
27c202ad | 2270 | #define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list) |
2017263e | 2271 | |
27c202ad | 2272 | int i915_debugfs_init(struct drm_minor *minor) |
2017263e | 2273 | { |
f3cd474b CW |
2274 | int ret; |
2275 | ||
6a9c308d DV |
2276 | ret = i915_debugfs_create(minor->debugfs_root, minor, |
2277 | "i915_wedged", | |
2278 | &i915_wedged_fops); | |
f3cd474b CW |
2279 | if (ret) |
2280 | return ret; | |
2281 | ||
6d794d42 | 2282 | ret = i915_forcewake_create(minor->debugfs_root, minor); |
358733e9 JB |
2283 | if (ret) |
2284 | return ret; | |
6a9c308d DV |
2285 | |
2286 | ret = i915_debugfs_create(minor->debugfs_root, minor, | |
2287 | "i915_max_freq", | |
2288 | &i915_max_freq_fops); | |
07b7ddd9 JB |
2289 | if (ret) |
2290 | return ret; | |
6a9c308d | 2291 | |
1523c310 JB |
2292 | ret = i915_debugfs_create(minor->debugfs_root, minor, |
2293 | "i915_min_freq", | |
2294 | &i915_min_freq_fops); | |
2295 | if (ret) | |
2296 | return ret; | |
2297 | ||
6a9c308d DV |
2298 | ret = i915_debugfs_create(minor->debugfs_root, minor, |
2299 | "i915_cache_sharing", | |
2300 | &i915_cache_sharing_fops); | |
6d794d42 BW |
2301 | if (ret) |
2302 | return ret; | |
004777cb | 2303 | |
e5eb3d63 DV |
2304 | ret = i915_debugfs_create(minor->debugfs_root, minor, |
2305 | "i915_ring_stop", | |
2306 | &i915_ring_stop_fops); | |
2307 | if (ret) | |
2308 | return ret; | |
6d794d42 | 2309 | |
dd624afd CW |
2310 | ret = i915_debugfs_create(minor->debugfs_root, minor, |
2311 | "i915_gem_drop_caches", | |
2312 | &i915_drop_caches_fops); | |
2313 | if (ret) | |
2314 | return ret; | |
2315 | ||
d5442303 DV |
2316 | ret = i915_debugfs_create(minor->debugfs_root, minor, |
2317 | "i915_error_state", | |
2318 | &i915_error_state_fops); | |
2319 | if (ret) | |
2320 | return ret; | |
2321 | ||
40633219 MK |
2322 | ret = i915_debugfs_create(minor->debugfs_root, minor, |
2323 | "i915_next_seqno", | |
2324 | &i915_next_seqno_fops); | |
2325 | if (ret) | |
2326 | return ret; | |
2327 | ||
27c202ad BG |
2328 | return drm_debugfs_create_files(i915_debugfs_list, |
2329 | I915_DEBUGFS_ENTRIES, | |
2017263e BG |
2330 | minor->debugfs_root, minor); |
2331 | } | |
2332 | ||
27c202ad | 2333 | void i915_debugfs_cleanup(struct drm_minor *minor) |
2017263e | 2334 | { |
27c202ad BG |
2335 | drm_debugfs_remove_files(i915_debugfs_list, |
2336 | I915_DEBUGFS_ENTRIES, minor); | |
6d794d42 BW |
2337 | drm_debugfs_remove_files((struct drm_info_list *) &i915_forcewake_fops, |
2338 | 1, minor); | |
33db679b KH |
2339 | drm_debugfs_remove_files((struct drm_info_list *) &i915_wedged_fops, |
2340 | 1, minor); | |
358733e9 JB |
2341 | drm_debugfs_remove_files((struct drm_info_list *) &i915_max_freq_fops, |
2342 | 1, minor); | |
1523c310 JB |
2343 | drm_debugfs_remove_files((struct drm_info_list *) &i915_min_freq_fops, |
2344 | 1, minor); | |
07b7ddd9 JB |
2345 | drm_debugfs_remove_files((struct drm_info_list *) &i915_cache_sharing_fops, |
2346 | 1, minor); | |
dd624afd CW |
2347 | drm_debugfs_remove_files((struct drm_info_list *) &i915_drop_caches_fops, |
2348 | 1, minor); | |
e5eb3d63 DV |
2349 | drm_debugfs_remove_files((struct drm_info_list *) &i915_ring_stop_fops, |
2350 | 1, minor); | |
6bd459df DV |
2351 | drm_debugfs_remove_files((struct drm_info_list *) &i915_error_state_fops, |
2352 | 1, minor); | |
40633219 MK |
2353 | drm_debugfs_remove_files((struct drm_info_list *) &i915_next_seqno_fops, |
2354 | 1, minor); | |
2017263e BG |
2355 | } |
2356 | ||
2357 | #endif /* CONFIG_DEBUG_FS */ |