Commit | Line | Data |
---|---|---|
2017263e BG |
1 | /* |
2 | * Copyright © 2008 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | * Keith Packard <keithp@keithp.com> | |
26 | * | |
27 | */ | |
28 | ||
29 | #include <linux/seq_file.h> | |
f3cd474b | 30 | #include <linux/debugfs.h> |
5a0e3ad6 | 31 | #include <linux/slab.h> |
2d1a8a48 | 32 | #include <linux/export.h> |
2017263e BG |
33 | #include "drmP.h" |
34 | #include "drm.h" | |
4e5359cd | 35 | #include "intel_drv.h" |
e5c65260 | 36 | #include "intel_ringbuffer.h" |
2017263e BG |
37 | #include "i915_drm.h" |
38 | #include "i915_drv.h" | |
39 | ||
40 | #define DRM_I915_RING_DEBUG 1 | |
41 | ||
42 | ||
43 | #if defined(CONFIG_DEBUG_FS) | |
44 | ||
f13d3f73 | 45 | enum { |
69dc4987 | 46 | ACTIVE_LIST, |
f13d3f73 CW |
47 | FLUSHING_LIST, |
48 | INACTIVE_LIST, | |
d21d5975 CW |
49 | PINNED_LIST, |
50 | DEFERRED_FREE_LIST, | |
f13d3f73 | 51 | }; |
2017263e | 52 | |
70d39fe4 CW |
53 | static const char *yesno(int v) |
54 | { | |
55 | return v ? "yes" : "no"; | |
56 | } | |
57 | ||
58 | static int i915_capabilities(struct seq_file *m, void *data) | |
59 | { | |
60 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
61 | struct drm_device *dev = node->minor->dev; | |
62 | const struct intel_device_info *info = INTEL_INFO(dev); | |
63 | ||
64 | seq_printf(m, "gen: %d\n", info->gen); | |
03d00ac5 | 65 | seq_printf(m, "pch: %d\n", INTEL_PCH_TYPE(dev)); |
70d39fe4 CW |
66 | #define B(x) seq_printf(m, #x ": %s\n", yesno(info->x)) |
67 | B(is_mobile); | |
70d39fe4 CW |
68 | B(is_i85x); |
69 | B(is_i915g); | |
70d39fe4 | 70 | B(is_i945gm); |
70d39fe4 CW |
71 | B(is_g33); |
72 | B(need_gfx_hws); | |
73 | B(is_g4x); | |
74 | B(is_pineview); | |
75 | B(is_broadwater); | |
76 | B(is_crestline); | |
70d39fe4 | 77 | B(has_fbc); |
70d39fe4 CW |
78 | B(has_pipe_cxsr); |
79 | B(has_hotplug); | |
80 | B(cursor_needs_physical); | |
81 | B(has_overlay); | |
82 | B(overlay_needs_physical); | |
a6c45cf0 | 83 | B(supports_tv); |
549f7365 CW |
84 | B(has_bsd_ring); |
85 | B(has_blt_ring); | |
3d29b842 | 86 | B(has_llc); |
70d39fe4 CW |
87 | #undef B |
88 | ||
89 | return 0; | |
90 | } | |
2017263e | 91 | |
05394f39 | 92 | static const char *get_pin_flag(struct drm_i915_gem_object *obj) |
a6172a80 | 93 | { |
05394f39 | 94 | if (obj->user_pin_count > 0) |
a6172a80 | 95 | return "P"; |
05394f39 | 96 | else if (obj->pin_count > 0) |
a6172a80 CW |
97 | return "p"; |
98 | else | |
99 | return " "; | |
100 | } | |
101 | ||
05394f39 | 102 | static const char *get_tiling_flag(struct drm_i915_gem_object *obj) |
a6172a80 | 103 | { |
0206e353 AJ |
104 | switch (obj->tiling_mode) { |
105 | default: | |
106 | case I915_TILING_NONE: return " "; | |
107 | case I915_TILING_X: return "X"; | |
108 | case I915_TILING_Y: return "Y"; | |
109 | } | |
a6172a80 CW |
110 | } |
111 | ||
93dfb40c | 112 | static const char *cache_level_str(int type) |
08c18323 CW |
113 | { |
114 | switch (type) { | |
93dfb40c CW |
115 | case I915_CACHE_NONE: return " uncached"; |
116 | case I915_CACHE_LLC: return " snooped (LLC)"; | |
117 | case I915_CACHE_LLC_MLC: return " snooped (LLC+MLC)"; | |
08c18323 CW |
118 | default: return ""; |
119 | } | |
120 | } | |
121 | ||
37811fcc CW |
122 | static void |
123 | describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj) | |
124 | { | |
a05a5862 | 125 | seq_printf(m, "%p: %s%s %8zdKiB %04x %04x %d %d%s%s%s", |
37811fcc CW |
126 | &obj->base, |
127 | get_pin_flag(obj), | |
128 | get_tiling_flag(obj), | |
a05a5862 | 129 | obj->base.size / 1024, |
37811fcc CW |
130 | obj->base.read_domains, |
131 | obj->base.write_domain, | |
132 | obj->last_rendering_seqno, | |
caea7476 | 133 | obj->last_fenced_seqno, |
93dfb40c | 134 | cache_level_str(obj->cache_level), |
37811fcc CW |
135 | obj->dirty ? " dirty" : "", |
136 | obj->madv == I915_MADV_DONTNEED ? " purgeable" : ""); | |
137 | if (obj->base.name) | |
138 | seq_printf(m, " (name: %d)", obj->base.name); | |
139 | if (obj->fence_reg != I915_FENCE_REG_NONE) | |
140 | seq_printf(m, " (fence: %d)", obj->fence_reg); | |
141 | if (obj->gtt_space != NULL) | |
a00b10c3 CW |
142 | seq_printf(m, " (gtt offset: %08x, size: %08x)", |
143 | obj->gtt_offset, (unsigned int)obj->gtt_space->size); | |
6299f992 CW |
144 | if (obj->pin_mappable || obj->fault_mappable) { |
145 | char s[3], *t = s; | |
146 | if (obj->pin_mappable) | |
147 | *t++ = 'p'; | |
148 | if (obj->fault_mappable) | |
149 | *t++ = 'f'; | |
150 | *t = '\0'; | |
151 | seq_printf(m, " (%s mappable)", s); | |
152 | } | |
69dc4987 CW |
153 | if (obj->ring != NULL) |
154 | seq_printf(m, " (%s)", obj->ring->name); | |
37811fcc CW |
155 | } |
156 | ||
433e12f7 | 157 | static int i915_gem_object_list_info(struct seq_file *m, void *data) |
2017263e BG |
158 | { |
159 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
433e12f7 BG |
160 | uintptr_t list = (uintptr_t) node->info_ent->data; |
161 | struct list_head *head; | |
2017263e BG |
162 | struct drm_device *dev = node->minor->dev; |
163 | drm_i915_private_t *dev_priv = dev->dev_private; | |
05394f39 | 164 | struct drm_i915_gem_object *obj; |
8f2480fb CW |
165 | size_t total_obj_size, total_gtt_size; |
166 | int count, ret; | |
de227ef0 CW |
167 | |
168 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
169 | if (ret) | |
170 | return ret; | |
2017263e | 171 | |
433e12f7 BG |
172 | switch (list) { |
173 | case ACTIVE_LIST: | |
174 | seq_printf(m, "Active:\n"); | |
69dc4987 | 175 | head = &dev_priv->mm.active_list; |
433e12f7 BG |
176 | break; |
177 | case INACTIVE_LIST: | |
a17458fc | 178 | seq_printf(m, "Inactive:\n"); |
433e12f7 BG |
179 | head = &dev_priv->mm.inactive_list; |
180 | break; | |
f13d3f73 CW |
181 | case PINNED_LIST: |
182 | seq_printf(m, "Pinned:\n"); | |
183 | head = &dev_priv->mm.pinned_list; | |
184 | break; | |
433e12f7 BG |
185 | case FLUSHING_LIST: |
186 | seq_printf(m, "Flushing:\n"); | |
187 | head = &dev_priv->mm.flushing_list; | |
188 | break; | |
d21d5975 CW |
189 | case DEFERRED_FREE_LIST: |
190 | seq_printf(m, "Deferred free:\n"); | |
191 | head = &dev_priv->mm.deferred_free_list; | |
192 | break; | |
433e12f7 | 193 | default: |
de227ef0 CW |
194 | mutex_unlock(&dev->struct_mutex); |
195 | return -EINVAL; | |
2017263e | 196 | } |
2017263e | 197 | |
8f2480fb | 198 | total_obj_size = total_gtt_size = count = 0; |
05394f39 | 199 | list_for_each_entry(obj, head, mm_list) { |
37811fcc | 200 | seq_printf(m, " "); |
05394f39 | 201 | describe_obj(m, obj); |
f4ceda89 | 202 | seq_printf(m, "\n"); |
05394f39 CW |
203 | total_obj_size += obj->base.size; |
204 | total_gtt_size += obj->gtt_space->size; | |
8f2480fb | 205 | count++; |
2017263e | 206 | } |
de227ef0 | 207 | mutex_unlock(&dev->struct_mutex); |
5e118f41 | 208 | |
8f2480fb CW |
209 | seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n", |
210 | count, total_obj_size, total_gtt_size); | |
2017263e BG |
211 | return 0; |
212 | } | |
213 | ||
6299f992 CW |
214 | #define count_objects(list, member) do { \ |
215 | list_for_each_entry(obj, list, member) { \ | |
216 | size += obj->gtt_space->size; \ | |
217 | ++count; \ | |
218 | if (obj->map_and_fenceable) { \ | |
219 | mappable_size += obj->gtt_space->size; \ | |
220 | ++mappable_count; \ | |
221 | } \ | |
222 | } \ | |
0206e353 | 223 | } while (0) |
6299f992 | 224 | |
73aa808f CW |
225 | static int i915_gem_object_info(struct seq_file *m, void* data) |
226 | { | |
227 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
228 | struct drm_device *dev = node->minor->dev; | |
229 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6299f992 CW |
230 | u32 count, mappable_count; |
231 | size_t size, mappable_size; | |
232 | struct drm_i915_gem_object *obj; | |
73aa808f CW |
233 | int ret; |
234 | ||
235 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
236 | if (ret) | |
237 | return ret; | |
238 | ||
6299f992 CW |
239 | seq_printf(m, "%u objects, %zu bytes\n", |
240 | dev_priv->mm.object_count, | |
241 | dev_priv->mm.object_memory); | |
242 | ||
243 | size = count = mappable_size = mappable_count = 0; | |
244 | count_objects(&dev_priv->mm.gtt_list, gtt_list); | |
245 | seq_printf(m, "%u [%u] objects, %zu [%zu] bytes in gtt\n", | |
246 | count, mappable_count, size, mappable_size); | |
247 | ||
248 | size = count = mappable_size = mappable_count = 0; | |
249 | count_objects(&dev_priv->mm.active_list, mm_list); | |
250 | count_objects(&dev_priv->mm.flushing_list, mm_list); | |
251 | seq_printf(m, " %u [%u] active objects, %zu [%zu] bytes\n", | |
252 | count, mappable_count, size, mappable_size); | |
253 | ||
254 | size = count = mappable_size = mappable_count = 0; | |
255 | count_objects(&dev_priv->mm.pinned_list, mm_list); | |
256 | seq_printf(m, " %u [%u] pinned objects, %zu [%zu] bytes\n", | |
257 | count, mappable_count, size, mappable_size); | |
258 | ||
259 | size = count = mappable_size = mappable_count = 0; | |
260 | count_objects(&dev_priv->mm.inactive_list, mm_list); | |
261 | seq_printf(m, " %u [%u] inactive objects, %zu [%zu] bytes\n", | |
262 | count, mappable_count, size, mappable_size); | |
263 | ||
264 | size = count = mappable_size = mappable_count = 0; | |
265 | count_objects(&dev_priv->mm.deferred_free_list, mm_list); | |
266 | seq_printf(m, " %u [%u] freed objects, %zu [%zu] bytes\n", | |
267 | count, mappable_count, size, mappable_size); | |
268 | ||
269 | size = count = mappable_size = mappable_count = 0; | |
270 | list_for_each_entry(obj, &dev_priv->mm.gtt_list, gtt_list) { | |
271 | if (obj->fault_mappable) { | |
272 | size += obj->gtt_space->size; | |
273 | ++count; | |
274 | } | |
275 | if (obj->pin_mappable) { | |
276 | mappable_size += obj->gtt_space->size; | |
277 | ++mappable_count; | |
278 | } | |
279 | } | |
280 | seq_printf(m, "%u pinned mappable objects, %zu bytes\n", | |
281 | mappable_count, mappable_size); | |
282 | seq_printf(m, "%u fault mappable objects, %zu bytes\n", | |
283 | count, size); | |
284 | ||
285 | seq_printf(m, "%zu [%zu] gtt total\n", | |
286 | dev_priv->mm.gtt_total, dev_priv->mm.mappable_gtt_total); | |
73aa808f CW |
287 | |
288 | mutex_unlock(&dev->struct_mutex); | |
289 | ||
290 | return 0; | |
291 | } | |
292 | ||
08c18323 CW |
293 | static int i915_gem_gtt_info(struct seq_file *m, void* data) |
294 | { | |
295 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
296 | struct drm_device *dev = node->minor->dev; | |
297 | struct drm_i915_private *dev_priv = dev->dev_private; | |
298 | struct drm_i915_gem_object *obj; | |
299 | size_t total_obj_size, total_gtt_size; | |
300 | int count, ret; | |
301 | ||
302 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
303 | if (ret) | |
304 | return ret; | |
305 | ||
306 | total_obj_size = total_gtt_size = count = 0; | |
307 | list_for_each_entry(obj, &dev_priv->mm.gtt_list, gtt_list) { | |
308 | seq_printf(m, " "); | |
309 | describe_obj(m, obj); | |
310 | seq_printf(m, "\n"); | |
311 | total_obj_size += obj->base.size; | |
312 | total_gtt_size += obj->gtt_space->size; | |
313 | count++; | |
314 | } | |
315 | ||
316 | mutex_unlock(&dev->struct_mutex); | |
317 | ||
318 | seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n", | |
319 | count, total_obj_size, total_gtt_size); | |
320 | ||
321 | return 0; | |
322 | } | |
323 | ||
73aa808f | 324 | |
4e5359cd SF |
325 | static int i915_gem_pageflip_info(struct seq_file *m, void *data) |
326 | { | |
327 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
328 | struct drm_device *dev = node->minor->dev; | |
329 | unsigned long flags; | |
330 | struct intel_crtc *crtc; | |
331 | ||
332 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) { | |
9db4a9c7 JB |
333 | const char pipe = pipe_name(crtc->pipe); |
334 | const char plane = plane_name(crtc->plane); | |
4e5359cd SF |
335 | struct intel_unpin_work *work; |
336 | ||
337 | spin_lock_irqsave(&dev->event_lock, flags); | |
338 | work = crtc->unpin_work; | |
339 | if (work == NULL) { | |
9db4a9c7 | 340 | seq_printf(m, "No flip due on pipe %c (plane %c)\n", |
4e5359cd SF |
341 | pipe, plane); |
342 | } else { | |
343 | if (!work->pending) { | |
9db4a9c7 | 344 | seq_printf(m, "Flip queued on pipe %c (plane %c)\n", |
4e5359cd SF |
345 | pipe, plane); |
346 | } else { | |
9db4a9c7 | 347 | seq_printf(m, "Flip pending (waiting for vsync) on pipe %c (plane %c)\n", |
4e5359cd SF |
348 | pipe, plane); |
349 | } | |
350 | if (work->enable_stall_check) | |
351 | seq_printf(m, "Stall check enabled, "); | |
352 | else | |
353 | seq_printf(m, "Stall check waiting for page flip ioctl, "); | |
354 | seq_printf(m, "%d prepares\n", work->pending); | |
355 | ||
356 | if (work->old_fb_obj) { | |
05394f39 CW |
357 | struct drm_i915_gem_object *obj = work->old_fb_obj; |
358 | if (obj) | |
359 | seq_printf(m, "Old framebuffer gtt_offset 0x%08x\n", obj->gtt_offset); | |
4e5359cd SF |
360 | } |
361 | if (work->pending_flip_obj) { | |
05394f39 CW |
362 | struct drm_i915_gem_object *obj = work->pending_flip_obj; |
363 | if (obj) | |
364 | seq_printf(m, "New framebuffer gtt_offset 0x%08x\n", obj->gtt_offset); | |
4e5359cd SF |
365 | } |
366 | } | |
367 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
368 | } | |
369 | ||
370 | return 0; | |
371 | } | |
372 | ||
2017263e BG |
373 | static int i915_gem_request_info(struct seq_file *m, void *data) |
374 | { | |
375 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
376 | struct drm_device *dev = node->minor->dev; | |
377 | drm_i915_private_t *dev_priv = dev->dev_private; | |
378 | struct drm_i915_gem_request *gem_request; | |
c2c347a9 | 379 | int ret, count; |
de227ef0 CW |
380 | |
381 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
382 | if (ret) | |
383 | return ret; | |
2017263e | 384 | |
c2c347a9 | 385 | count = 0; |
1ec14ad3 | 386 | if (!list_empty(&dev_priv->ring[RCS].request_list)) { |
c2c347a9 CW |
387 | seq_printf(m, "Render requests:\n"); |
388 | list_for_each_entry(gem_request, | |
1ec14ad3 | 389 | &dev_priv->ring[RCS].request_list, |
c2c347a9 CW |
390 | list) { |
391 | seq_printf(m, " %d @ %d\n", | |
392 | gem_request->seqno, | |
393 | (int) (jiffies - gem_request->emitted_jiffies)); | |
394 | } | |
395 | count++; | |
396 | } | |
1ec14ad3 | 397 | if (!list_empty(&dev_priv->ring[VCS].request_list)) { |
c2c347a9 CW |
398 | seq_printf(m, "BSD requests:\n"); |
399 | list_for_each_entry(gem_request, | |
1ec14ad3 | 400 | &dev_priv->ring[VCS].request_list, |
c2c347a9 CW |
401 | list) { |
402 | seq_printf(m, " %d @ %d\n", | |
403 | gem_request->seqno, | |
404 | (int) (jiffies - gem_request->emitted_jiffies)); | |
405 | } | |
406 | count++; | |
407 | } | |
1ec14ad3 | 408 | if (!list_empty(&dev_priv->ring[BCS].request_list)) { |
c2c347a9 CW |
409 | seq_printf(m, "BLT requests:\n"); |
410 | list_for_each_entry(gem_request, | |
1ec14ad3 | 411 | &dev_priv->ring[BCS].request_list, |
c2c347a9 CW |
412 | list) { |
413 | seq_printf(m, " %d @ %d\n", | |
414 | gem_request->seqno, | |
415 | (int) (jiffies - gem_request->emitted_jiffies)); | |
416 | } | |
417 | count++; | |
2017263e | 418 | } |
de227ef0 CW |
419 | mutex_unlock(&dev->struct_mutex); |
420 | ||
c2c347a9 CW |
421 | if (count == 0) |
422 | seq_printf(m, "No requests\n"); | |
423 | ||
2017263e BG |
424 | return 0; |
425 | } | |
426 | ||
b2223497 CW |
427 | static void i915_ring_seqno_info(struct seq_file *m, |
428 | struct intel_ring_buffer *ring) | |
429 | { | |
430 | if (ring->get_seqno) { | |
431 | seq_printf(m, "Current sequence (%s): %d\n", | |
432 | ring->name, ring->get_seqno(ring)); | |
433 | seq_printf(m, "Waiter sequence (%s): %d\n", | |
434 | ring->name, ring->waiting_seqno); | |
435 | seq_printf(m, "IRQ sequence (%s): %d\n", | |
436 | ring->name, ring->irq_seqno); | |
437 | } | |
438 | } | |
439 | ||
2017263e BG |
440 | static int i915_gem_seqno_info(struct seq_file *m, void *data) |
441 | { | |
442 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
443 | struct drm_device *dev = node->minor->dev; | |
444 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1ec14ad3 | 445 | int ret, i; |
de227ef0 CW |
446 | |
447 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
448 | if (ret) | |
449 | return ret; | |
2017263e | 450 | |
1ec14ad3 CW |
451 | for (i = 0; i < I915_NUM_RINGS; i++) |
452 | i915_ring_seqno_info(m, &dev_priv->ring[i]); | |
de227ef0 CW |
453 | |
454 | mutex_unlock(&dev->struct_mutex); | |
455 | ||
2017263e BG |
456 | return 0; |
457 | } | |
458 | ||
459 | ||
460 | static int i915_interrupt_info(struct seq_file *m, void *data) | |
461 | { | |
462 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
463 | struct drm_device *dev = node->minor->dev; | |
464 | drm_i915_private_t *dev_priv = dev->dev_private; | |
9db4a9c7 | 465 | int ret, i, pipe; |
de227ef0 CW |
466 | |
467 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
468 | if (ret) | |
469 | return ret; | |
2017263e | 470 | |
7e231dbe JB |
471 | if (IS_VALLEYVIEW(dev)) { |
472 | seq_printf(m, "Display IER:\t%08x\n", | |
473 | I915_READ(VLV_IER)); | |
474 | seq_printf(m, "Display IIR:\t%08x\n", | |
475 | I915_READ(VLV_IIR)); | |
476 | seq_printf(m, "Display IIR_RW:\t%08x\n", | |
477 | I915_READ(VLV_IIR_RW)); | |
478 | seq_printf(m, "Display IMR:\t%08x\n", | |
479 | I915_READ(VLV_IMR)); | |
480 | for_each_pipe(pipe) | |
481 | seq_printf(m, "Pipe %c stat:\t%08x\n", | |
482 | pipe_name(pipe), | |
483 | I915_READ(PIPESTAT(pipe))); | |
484 | ||
485 | seq_printf(m, "Master IER:\t%08x\n", | |
486 | I915_READ(VLV_MASTER_IER)); | |
487 | ||
488 | seq_printf(m, "Render IER:\t%08x\n", | |
489 | I915_READ(GTIER)); | |
490 | seq_printf(m, "Render IIR:\t%08x\n", | |
491 | I915_READ(GTIIR)); | |
492 | seq_printf(m, "Render IMR:\t%08x\n", | |
493 | I915_READ(GTIMR)); | |
494 | ||
495 | seq_printf(m, "PM IER:\t\t%08x\n", | |
496 | I915_READ(GEN6_PMIER)); | |
497 | seq_printf(m, "PM IIR:\t\t%08x\n", | |
498 | I915_READ(GEN6_PMIIR)); | |
499 | seq_printf(m, "PM IMR:\t\t%08x\n", | |
500 | I915_READ(GEN6_PMIMR)); | |
501 | ||
502 | seq_printf(m, "Port hotplug:\t%08x\n", | |
503 | I915_READ(PORT_HOTPLUG_EN)); | |
504 | seq_printf(m, "DPFLIPSTAT:\t%08x\n", | |
505 | I915_READ(VLV_DPFLIPSTAT)); | |
506 | seq_printf(m, "DPINVGTT:\t%08x\n", | |
507 | I915_READ(DPINVGTT)); | |
508 | ||
509 | } else if (!HAS_PCH_SPLIT(dev)) { | |
5f6a1695 ZW |
510 | seq_printf(m, "Interrupt enable: %08x\n", |
511 | I915_READ(IER)); | |
512 | seq_printf(m, "Interrupt identity: %08x\n", | |
513 | I915_READ(IIR)); | |
514 | seq_printf(m, "Interrupt mask: %08x\n", | |
515 | I915_READ(IMR)); | |
9db4a9c7 JB |
516 | for_each_pipe(pipe) |
517 | seq_printf(m, "Pipe %c stat: %08x\n", | |
518 | pipe_name(pipe), | |
519 | I915_READ(PIPESTAT(pipe))); | |
5f6a1695 ZW |
520 | } else { |
521 | seq_printf(m, "North Display Interrupt enable: %08x\n", | |
522 | I915_READ(DEIER)); | |
523 | seq_printf(m, "North Display Interrupt identity: %08x\n", | |
524 | I915_READ(DEIIR)); | |
525 | seq_printf(m, "North Display Interrupt mask: %08x\n", | |
526 | I915_READ(DEIMR)); | |
527 | seq_printf(m, "South Display Interrupt enable: %08x\n", | |
528 | I915_READ(SDEIER)); | |
529 | seq_printf(m, "South Display Interrupt identity: %08x\n", | |
530 | I915_READ(SDEIIR)); | |
531 | seq_printf(m, "South Display Interrupt mask: %08x\n", | |
532 | I915_READ(SDEIMR)); | |
533 | seq_printf(m, "Graphics Interrupt enable: %08x\n", | |
534 | I915_READ(GTIER)); | |
535 | seq_printf(m, "Graphics Interrupt identity: %08x\n", | |
536 | I915_READ(GTIIR)); | |
537 | seq_printf(m, "Graphics Interrupt mask: %08x\n", | |
538 | I915_READ(GTIMR)); | |
539 | } | |
2017263e BG |
540 | seq_printf(m, "Interrupts received: %d\n", |
541 | atomic_read(&dev_priv->irq_received)); | |
9862e600 | 542 | for (i = 0; i < I915_NUM_RINGS; i++) { |
da64c6fc | 543 | if (IS_GEN6(dev) || IS_GEN7(dev)) { |
9862e600 CW |
544 | seq_printf(m, "Graphics Interrupt mask (%s): %08x\n", |
545 | dev_priv->ring[i].name, | |
546 | I915_READ_IMR(&dev_priv->ring[i])); | |
547 | } | |
1ec14ad3 | 548 | i915_ring_seqno_info(m, &dev_priv->ring[i]); |
9862e600 | 549 | } |
de227ef0 CW |
550 | mutex_unlock(&dev->struct_mutex); |
551 | ||
2017263e BG |
552 | return 0; |
553 | } | |
554 | ||
a6172a80 CW |
555 | static int i915_gem_fence_regs_info(struct seq_file *m, void *data) |
556 | { | |
557 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
558 | struct drm_device *dev = node->minor->dev; | |
559 | drm_i915_private_t *dev_priv = dev->dev_private; | |
de227ef0 CW |
560 | int i, ret; |
561 | ||
562 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
563 | if (ret) | |
564 | return ret; | |
a6172a80 CW |
565 | |
566 | seq_printf(m, "Reserved fences = %d\n", dev_priv->fence_reg_start); | |
567 | seq_printf(m, "Total fences = %d\n", dev_priv->num_fence_regs); | |
568 | for (i = 0; i < dev_priv->num_fence_regs; i++) { | |
05394f39 | 569 | struct drm_i915_gem_object *obj = dev_priv->fence_regs[i].obj; |
a6172a80 | 570 | |
c2c347a9 CW |
571 | seq_printf(m, "Fenced object[%2d] = ", i); |
572 | if (obj == NULL) | |
573 | seq_printf(m, "unused"); | |
574 | else | |
05394f39 | 575 | describe_obj(m, obj); |
c2c347a9 | 576 | seq_printf(m, "\n"); |
a6172a80 CW |
577 | } |
578 | ||
05394f39 | 579 | mutex_unlock(&dev->struct_mutex); |
a6172a80 CW |
580 | return 0; |
581 | } | |
582 | ||
2017263e BG |
583 | static int i915_hws_info(struct seq_file *m, void *data) |
584 | { | |
585 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
586 | struct drm_device *dev = node->minor->dev; | |
587 | drm_i915_private_t *dev_priv = dev->dev_private; | |
4066c0ae | 588 | struct intel_ring_buffer *ring; |
311bd68e | 589 | const volatile u32 __iomem *hws; |
4066c0ae CW |
590 | int i; |
591 | ||
1ec14ad3 | 592 | ring = &dev_priv->ring[(uintptr_t)node->info_ent->data]; |
311bd68e | 593 | hws = (volatile u32 __iomem *)ring->status_page.page_addr; |
2017263e BG |
594 | if (hws == NULL) |
595 | return 0; | |
596 | ||
597 | for (i = 0; i < 4096 / sizeof(u32) / 4; i += 4) { | |
598 | seq_printf(m, "0x%08x: 0x%08x 0x%08x 0x%08x 0x%08x\n", | |
599 | i * 4, | |
600 | hws[i], hws[i + 1], hws[i + 2], hws[i + 3]); | |
601 | } | |
602 | return 0; | |
603 | } | |
604 | ||
e5c65260 CW |
605 | static const char *ring_str(int ring) |
606 | { | |
607 | switch (ring) { | |
96154f2f DV |
608 | case RCS: return "render"; |
609 | case VCS: return "bsd"; | |
610 | case BCS: return "blt"; | |
e5c65260 CW |
611 | default: return ""; |
612 | } | |
613 | } | |
614 | ||
9df30794 CW |
615 | static const char *pin_flag(int pinned) |
616 | { | |
617 | if (pinned > 0) | |
618 | return " P"; | |
619 | else if (pinned < 0) | |
620 | return " p"; | |
621 | else | |
622 | return ""; | |
623 | } | |
624 | ||
625 | static const char *tiling_flag(int tiling) | |
626 | { | |
627 | switch (tiling) { | |
628 | default: | |
629 | case I915_TILING_NONE: return ""; | |
630 | case I915_TILING_X: return " X"; | |
631 | case I915_TILING_Y: return " Y"; | |
632 | } | |
633 | } | |
634 | ||
635 | static const char *dirty_flag(int dirty) | |
636 | { | |
637 | return dirty ? " dirty" : ""; | |
638 | } | |
639 | ||
640 | static const char *purgeable_flag(int purgeable) | |
641 | { | |
642 | return purgeable ? " purgeable" : ""; | |
643 | } | |
644 | ||
c724e8a9 CW |
645 | static void print_error_buffers(struct seq_file *m, |
646 | const char *name, | |
647 | struct drm_i915_error_buffer *err, | |
648 | int count) | |
649 | { | |
650 | seq_printf(m, "%s [%d]:\n", name, count); | |
651 | ||
652 | while (count--) { | |
96154f2f | 653 | seq_printf(m, " %08x %8u %04x %04x %08x%s%s%s%s%s%s%s", |
c724e8a9 CW |
654 | err->gtt_offset, |
655 | err->size, | |
656 | err->read_domains, | |
657 | err->write_domain, | |
658 | err->seqno, | |
659 | pin_flag(err->pinned), | |
660 | tiling_flag(err->tiling), | |
661 | dirty_flag(err->dirty), | |
662 | purgeable_flag(err->purgeable), | |
96154f2f | 663 | err->ring != -1 ? " " : "", |
a779e5ab | 664 | ring_str(err->ring), |
93dfb40c | 665 | cache_level_str(err->cache_level)); |
c724e8a9 CW |
666 | |
667 | if (err->name) | |
668 | seq_printf(m, " (name: %d)", err->name); | |
669 | if (err->fence_reg != I915_FENCE_REG_NONE) | |
670 | seq_printf(m, " (fence: %d)", err->fence_reg); | |
671 | ||
672 | seq_printf(m, "\n"); | |
673 | err++; | |
674 | } | |
675 | } | |
676 | ||
d27b1e0e DV |
677 | static void i915_ring_error_state(struct seq_file *m, |
678 | struct drm_device *dev, | |
679 | struct drm_i915_error_state *error, | |
680 | unsigned ring) | |
681 | { | |
ec34a01d | 682 | BUG_ON(ring >= I915_NUM_RINGS); /* shut up confused gcc */ |
d27b1e0e | 683 | seq_printf(m, "%s command stream:\n", ring_str(ring)); |
c1cd90ed DV |
684 | seq_printf(m, " HEAD: 0x%08x\n", error->head[ring]); |
685 | seq_printf(m, " TAIL: 0x%08x\n", error->tail[ring]); | |
d27b1e0e DV |
686 | seq_printf(m, " ACTHD: 0x%08x\n", error->acthd[ring]); |
687 | seq_printf(m, " IPEIR: 0x%08x\n", error->ipeir[ring]); | |
688 | seq_printf(m, " IPEHR: 0x%08x\n", error->ipehr[ring]); | |
689 | seq_printf(m, " INSTDONE: 0x%08x\n", error->instdone[ring]); | |
c1cd90ed DV |
690 | if (ring == RCS && INTEL_INFO(dev)->gen >= 4) { |
691 | seq_printf(m, " INSTDONE1: 0x%08x\n", error->instdone1); | |
692 | seq_printf(m, " BBADDR: 0x%08llx\n", error->bbaddr); | |
d27b1e0e | 693 | } |
c1cd90ed DV |
694 | if (INTEL_INFO(dev)->gen >= 4) |
695 | seq_printf(m, " INSTPS: 0x%08x\n", error->instps[ring]); | |
696 | seq_printf(m, " INSTPM: 0x%08x\n", error->instpm[ring]); | |
9d2f41fa | 697 | seq_printf(m, " FADDR: 0x%08x\n", error->faddr[ring]); |
33f3f518 | 698 | if (INTEL_INFO(dev)->gen >= 6) { |
33f3f518 | 699 | seq_printf(m, " FAULT_REG: 0x%08x\n", error->fault_reg[ring]); |
7e3b8737 DV |
700 | seq_printf(m, " SYNC_0: 0x%08x\n", |
701 | error->semaphore_mboxes[ring][0]); | |
702 | seq_printf(m, " SYNC_1: 0x%08x\n", | |
703 | error->semaphore_mboxes[ring][1]); | |
33f3f518 | 704 | } |
d27b1e0e | 705 | seq_printf(m, " seqno: 0x%08x\n", error->seqno[ring]); |
7e3b8737 DV |
706 | seq_printf(m, " ring->head: 0x%08x\n", error->cpu_ring_head[ring]); |
707 | seq_printf(m, " ring->tail: 0x%08x\n", error->cpu_ring_tail[ring]); | |
d27b1e0e DV |
708 | } |
709 | ||
63eeaf38 JB |
710 | static int i915_error_state(struct seq_file *m, void *unused) |
711 | { | |
712 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
713 | struct drm_device *dev = node->minor->dev; | |
714 | drm_i915_private_t *dev_priv = dev->dev_private; | |
715 | struct drm_i915_error_state *error; | |
716 | unsigned long flags; | |
52d39a21 | 717 | int i, j, page, offset, elt; |
63eeaf38 JB |
718 | |
719 | spin_lock_irqsave(&dev_priv->error_lock, flags); | |
720 | if (!dev_priv->first_error) { | |
721 | seq_printf(m, "no error state collected\n"); | |
722 | goto out; | |
723 | } | |
724 | ||
725 | error = dev_priv->first_error; | |
726 | ||
8a905236 JB |
727 | seq_printf(m, "Time: %ld s %ld us\n", error->time.tv_sec, |
728 | error->time.tv_usec); | |
9df30794 | 729 | seq_printf(m, "PCI ID: 0x%04x\n", dev->pci_device); |
1d8f38f4 CW |
730 | seq_printf(m, "EIR: 0x%08x\n", error->eir); |
731 | seq_printf(m, "PGTBL_ER: 0x%08x\n", error->pgtbl_er); | |
9df30794 | 732 | |
bf3301ab | 733 | for (i = 0; i < dev_priv->num_fence_regs; i++) |
748ebc60 CW |
734 | seq_printf(m, " fence[%d] = %08llx\n", i, error->fence[i]); |
735 | ||
33f3f518 | 736 | if (INTEL_INFO(dev)->gen >= 6) { |
d27b1e0e | 737 | seq_printf(m, "ERROR: 0x%08x\n", error->error); |
33f3f518 DV |
738 | seq_printf(m, "DONE_REG: 0x%08x\n", error->done_reg); |
739 | } | |
d27b1e0e DV |
740 | |
741 | i915_ring_error_state(m, dev, error, RCS); | |
742 | if (HAS_BLT(dev)) | |
743 | i915_ring_error_state(m, dev, error, BCS); | |
744 | if (HAS_BSD(dev)) | |
745 | i915_ring_error_state(m, dev, error, VCS); | |
746 | ||
c724e8a9 CW |
747 | if (error->active_bo) |
748 | print_error_buffers(m, "Active", | |
749 | error->active_bo, | |
750 | error->active_bo_count); | |
751 | ||
752 | if (error->pinned_bo) | |
753 | print_error_buffers(m, "Pinned", | |
754 | error->pinned_bo, | |
755 | error->pinned_bo_count); | |
9df30794 | 756 | |
52d39a21 CW |
757 | for (i = 0; i < ARRAY_SIZE(error->ring); i++) { |
758 | struct drm_i915_error_object *obj; | |
9df30794 | 759 | |
52d39a21 | 760 | if ((obj = error->ring[i].batchbuffer)) { |
bcfb2e28 CW |
761 | seq_printf(m, "%s --- gtt_offset = 0x%08x\n", |
762 | dev_priv->ring[i].name, | |
763 | obj->gtt_offset); | |
9df30794 CW |
764 | offset = 0; |
765 | for (page = 0; page < obj->page_count; page++) { | |
766 | for (elt = 0; elt < PAGE_SIZE/4; elt++) { | |
767 | seq_printf(m, "%08x : %08x\n", offset, obj->pages[page][elt]); | |
768 | offset += 4; | |
769 | } | |
770 | } | |
771 | } | |
9df30794 | 772 | |
52d39a21 CW |
773 | if (error->ring[i].num_requests) { |
774 | seq_printf(m, "%s --- %d requests\n", | |
775 | dev_priv->ring[i].name, | |
776 | error->ring[i].num_requests); | |
777 | for (j = 0; j < error->ring[i].num_requests; j++) { | |
ee4f42b1 | 778 | seq_printf(m, " seqno 0x%08x, emitted %ld, tail 0x%08x\n", |
52d39a21 | 779 | error->ring[i].requests[j].seqno, |
ee4f42b1 CW |
780 | error->ring[i].requests[j].jiffies, |
781 | error->ring[i].requests[j].tail); | |
52d39a21 CW |
782 | } |
783 | } | |
784 | ||
785 | if ((obj = error->ring[i].ringbuffer)) { | |
e2f973d5 CW |
786 | seq_printf(m, "%s --- ringbuffer = 0x%08x\n", |
787 | dev_priv->ring[i].name, | |
788 | obj->gtt_offset); | |
789 | offset = 0; | |
790 | for (page = 0; page < obj->page_count; page++) { | |
791 | for (elt = 0; elt < PAGE_SIZE/4; elt++) { | |
792 | seq_printf(m, "%08x : %08x\n", | |
793 | offset, | |
794 | obj->pages[page][elt]); | |
795 | offset += 4; | |
796 | } | |
9df30794 CW |
797 | } |
798 | } | |
799 | } | |
63eeaf38 | 800 | |
6ef3d427 CW |
801 | if (error->overlay) |
802 | intel_overlay_print_error_state(m, error->overlay); | |
803 | ||
c4a1d9e4 CW |
804 | if (error->display) |
805 | intel_display_print_error_state(m, dev, error->display); | |
806 | ||
63eeaf38 JB |
807 | out: |
808 | spin_unlock_irqrestore(&dev_priv->error_lock, flags); | |
809 | ||
810 | return 0; | |
811 | } | |
6911a9b8 | 812 | |
f97108d1 JB |
813 | static int i915_rstdby_delays(struct seq_file *m, void *unused) |
814 | { | |
815 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
816 | struct drm_device *dev = node->minor->dev; | |
817 | drm_i915_private_t *dev_priv = dev->dev_private; | |
616fdb5a BW |
818 | u16 crstanddelay; |
819 | int ret; | |
820 | ||
821 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
822 | if (ret) | |
823 | return ret; | |
824 | ||
825 | crstanddelay = I915_READ16(CRSTANDVID); | |
826 | ||
827 | mutex_unlock(&dev->struct_mutex); | |
f97108d1 JB |
828 | |
829 | seq_printf(m, "w/ctx: %d, w/o ctx: %d\n", (crstanddelay >> 8) & 0x3f, (crstanddelay & 0x3f)); | |
830 | ||
831 | return 0; | |
832 | } | |
833 | ||
834 | static int i915_cur_delayinfo(struct seq_file *m, void *unused) | |
835 | { | |
836 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
837 | struct drm_device *dev = node->minor->dev; | |
838 | drm_i915_private_t *dev_priv = dev->dev_private; | |
d1ebd816 | 839 | int ret; |
3b8d8d91 JB |
840 | |
841 | if (IS_GEN5(dev)) { | |
842 | u16 rgvswctl = I915_READ16(MEMSWCTL); | |
843 | u16 rgvstat = I915_READ16(MEMSTAT_ILK); | |
844 | ||
845 | seq_printf(m, "Requested P-state: %d\n", (rgvswctl >> 8) & 0xf); | |
846 | seq_printf(m, "Requested VID: %d\n", rgvswctl & 0x3f); | |
847 | seq_printf(m, "Current VID: %d\n", (rgvstat & MEMSTAT_VID_MASK) >> | |
848 | MEMSTAT_VID_SHIFT); | |
849 | seq_printf(m, "Current P-state: %d\n", | |
850 | (rgvstat & MEMSTAT_PSTATE_MASK) >> MEMSTAT_PSTATE_SHIFT); | |
1c70c0ce | 851 | } else if (IS_GEN6(dev) || IS_GEN7(dev)) { |
3b8d8d91 JB |
852 | u32 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS); |
853 | u32 rp_state_limits = I915_READ(GEN6_RP_STATE_LIMITS); | |
854 | u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP); | |
ccab5c82 JB |
855 | u32 rpstat; |
856 | u32 rpupei, rpcurup, rpprevup; | |
857 | u32 rpdownei, rpcurdown, rpprevdown; | |
3b8d8d91 JB |
858 | int max_freq; |
859 | ||
860 | /* RPSTAT1 is in the GT power well */ | |
d1ebd816 BW |
861 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
862 | if (ret) | |
863 | return ret; | |
864 | ||
fcca7926 | 865 | gen6_gt_force_wake_get(dev_priv); |
3b8d8d91 | 866 | |
ccab5c82 JB |
867 | rpstat = I915_READ(GEN6_RPSTAT1); |
868 | rpupei = I915_READ(GEN6_RP_CUR_UP_EI); | |
869 | rpcurup = I915_READ(GEN6_RP_CUR_UP); | |
870 | rpprevup = I915_READ(GEN6_RP_PREV_UP); | |
871 | rpdownei = I915_READ(GEN6_RP_CUR_DOWN_EI); | |
872 | rpcurdown = I915_READ(GEN6_RP_CUR_DOWN); | |
873 | rpprevdown = I915_READ(GEN6_RP_PREV_DOWN); | |
874 | ||
d1ebd816 BW |
875 | gen6_gt_force_wake_put(dev_priv); |
876 | mutex_unlock(&dev->struct_mutex); | |
877 | ||
3b8d8d91 | 878 | seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status); |
ccab5c82 | 879 | seq_printf(m, "RPSTAT1: 0x%08x\n", rpstat); |
3b8d8d91 JB |
880 | seq_printf(m, "Render p-state ratio: %d\n", |
881 | (gt_perf_status & 0xff00) >> 8); | |
882 | seq_printf(m, "Render p-state VID: %d\n", | |
883 | gt_perf_status & 0xff); | |
884 | seq_printf(m, "Render p-state limit: %d\n", | |
885 | rp_state_limits & 0xff); | |
ccab5c82 | 886 | seq_printf(m, "CAGF: %dMHz\n", ((rpstat & GEN6_CAGF_MASK) >> |
e281fcaa | 887 | GEN6_CAGF_SHIFT) * 50); |
ccab5c82 JB |
888 | seq_printf(m, "RP CUR UP EI: %dus\n", rpupei & |
889 | GEN6_CURICONT_MASK); | |
890 | seq_printf(m, "RP CUR UP: %dus\n", rpcurup & | |
891 | GEN6_CURBSYTAVG_MASK); | |
892 | seq_printf(m, "RP PREV UP: %dus\n", rpprevup & | |
893 | GEN6_CURBSYTAVG_MASK); | |
894 | seq_printf(m, "RP CUR DOWN EI: %dus\n", rpdownei & | |
895 | GEN6_CURIAVG_MASK); | |
896 | seq_printf(m, "RP CUR DOWN: %dus\n", rpcurdown & | |
897 | GEN6_CURBSYTAVG_MASK); | |
898 | seq_printf(m, "RP PREV DOWN: %dus\n", rpprevdown & | |
899 | GEN6_CURBSYTAVG_MASK); | |
3b8d8d91 JB |
900 | |
901 | max_freq = (rp_state_cap & 0xff0000) >> 16; | |
902 | seq_printf(m, "Lowest (RPN) frequency: %dMHz\n", | |
e281fcaa | 903 | max_freq * 50); |
3b8d8d91 JB |
904 | |
905 | max_freq = (rp_state_cap & 0xff00) >> 8; | |
906 | seq_printf(m, "Nominal (RP1) frequency: %dMHz\n", | |
e281fcaa | 907 | max_freq * 50); |
3b8d8d91 JB |
908 | |
909 | max_freq = rp_state_cap & 0xff; | |
910 | seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n", | |
e281fcaa | 911 | max_freq * 50); |
3b8d8d91 JB |
912 | } else { |
913 | seq_printf(m, "no P-state info available\n"); | |
914 | } | |
f97108d1 JB |
915 | |
916 | return 0; | |
917 | } | |
918 | ||
919 | static int i915_delayfreq_table(struct seq_file *m, void *unused) | |
920 | { | |
921 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
922 | struct drm_device *dev = node->minor->dev; | |
923 | drm_i915_private_t *dev_priv = dev->dev_private; | |
924 | u32 delayfreq; | |
616fdb5a BW |
925 | int ret, i; |
926 | ||
927 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
928 | if (ret) | |
929 | return ret; | |
f97108d1 JB |
930 | |
931 | for (i = 0; i < 16; i++) { | |
932 | delayfreq = I915_READ(PXVFREQ_BASE + i * 4); | |
7648fa99 JB |
933 | seq_printf(m, "P%02dVIDFREQ: 0x%08x (VID: %d)\n", i, delayfreq, |
934 | (delayfreq & PXVFREQ_PX_MASK) >> PXVFREQ_PX_SHIFT); | |
f97108d1 JB |
935 | } |
936 | ||
616fdb5a BW |
937 | mutex_unlock(&dev->struct_mutex); |
938 | ||
f97108d1 JB |
939 | return 0; |
940 | } | |
941 | ||
942 | static inline int MAP_TO_MV(int map) | |
943 | { | |
944 | return 1250 - (map * 25); | |
945 | } | |
946 | ||
947 | static int i915_inttoext_table(struct seq_file *m, void *unused) | |
948 | { | |
949 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
950 | struct drm_device *dev = node->minor->dev; | |
951 | drm_i915_private_t *dev_priv = dev->dev_private; | |
952 | u32 inttoext; | |
616fdb5a BW |
953 | int ret, i; |
954 | ||
955 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
956 | if (ret) | |
957 | return ret; | |
f97108d1 JB |
958 | |
959 | for (i = 1; i <= 32; i++) { | |
960 | inttoext = I915_READ(INTTOEXT_BASE_ILK + i * 4); | |
961 | seq_printf(m, "INTTOEXT%02d: 0x%08x\n", i, inttoext); | |
962 | } | |
963 | ||
616fdb5a BW |
964 | mutex_unlock(&dev->struct_mutex); |
965 | ||
f97108d1 JB |
966 | return 0; |
967 | } | |
968 | ||
4d85529d | 969 | static int ironlake_drpc_info(struct seq_file *m) |
f97108d1 JB |
970 | { |
971 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
972 | struct drm_device *dev = node->minor->dev; | |
973 | drm_i915_private_t *dev_priv = dev->dev_private; | |
616fdb5a BW |
974 | u32 rgvmodectl, rstdbyctl; |
975 | u16 crstandvid; | |
976 | int ret; | |
977 | ||
978 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
979 | if (ret) | |
980 | return ret; | |
981 | ||
982 | rgvmodectl = I915_READ(MEMMODECTL); | |
983 | rstdbyctl = I915_READ(RSTDBYCTL); | |
984 | crstandvid = I915_READ16(CRSTANDVID); | |
985 | ||
986 | mutex_unlock(&dev->struct_mutex); | |
f97108d1 JB |
987 | |
988 | seq_printf(m, "HD boost: %s\n", (rgvmodectl & MEMMODE_BOOST_EN) ? | |
989 | "yes" : "no"); | |
990 | seq_printf(m, "Boost freq: %d\n", | |
991 | (rgvmodectl & MEMMODE_BOOST_FREQ_MASK) >> | |
992 | MEMMODE_BOOST_FREQ_SHIFT); | |
993 | seq_printf(m, "HW control enabled: %s\n", | |
994 | rgvmodectl & MEMMODE_HWIDLE_EN ? "yes" : "no"); | |
995 | seq_printf(m, "SW control enabled: %s\n", | |
996 | rgvmodectl & MEMMODE_SWMODE_EN ? "yes" : "no"); | |
997 | seq_printf(m, "Gated voltage change: %s\n", | |
998 | rgvmodectl & MEMMODE_RCLK_GATE ? "yes" : "no"); | |
999 | seq_printf(m, "Starting frequency: P%d\n", | |
1000 | (rgvmodectl & MEMMODE_FSTART_MASK) >> MEMMODE_FSTART_SHIFT); | |
7648fa99 | 1001 | seq_printf(m, "Max P-state: P%d\n", |
f97108d1 | 1002 | (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT); |
7648fa99 JB |
1003 | seq_printf(m, "Min P-state: P%d\n", (rgvmodectl & MEMMODE_FMIN_MASK)); |
1004 | seq_printf(m, "RS1 VID: %d\n", (crstandvid & 0x3f)); | |
1005 | seq_printf(m, "RS2 VID: %d\n", ((crstandvid >> 8) & 0x3f)); | |
1006 | seq_printf(m, "Render standby enabled: %s\n", | |
1007 | (rstdbyctl & RCX_SW_EXIT) ? "no" : "yes"); | |
88271da3 JB |
1008 | seq_printf(m, "Current RS state: "); |
1009 | switch (rstdbyctl & RSX_STATUS_MASK) { | |
1010 | case RSX_STATUS_ON: | |
1011 | seq_printf(m, "on\n"); | |
1012 | break; | |
1013 | case RSX_STATUS_RC1: | |
1014 | seq_printf(m, "RC1\n"); | |
1015 | break; | |
1016 | case RSX_STATUS_RC1E: | |
1017 | seq_printf(m, "RC1E\n"); | |
1018 | break; | |
1019 | case RSX_STATUS_RS1: | |
1020 | seq_printf(m, "RS1\n"); | |
1021 | break; | |
1022 | case RSX_STATUS_RS2: | |
1023 | seq_printf(m, "RS2 (RC6)\n"); | |
1024 | break; | |
1025 | case RSX_STATUS_RS3: | |
1026 | seq_printf(m, "RC3 (RC6+)\n"); | |
1027 | break; | |
1028 | default: | |
1029 | seq_printf(m, "unknown\n"); | |
1030 | break; | |
1031 | } | |
f97108d1 JB |
1032 | |
1033 | return 0; | |
1034 | } | |
1035 | ||
4d85529d BW |
1036 | static int gen6_drpc_info(struct seq_file *m) |
1037 | { | |
1038 | ||
1039 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1040 | struct drm_device *dev = node->minor->dev; | |
1041 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1042 | u32 rpmodectl1, gt_core_status, rcctl1; | |
93b525dc | 1043 | unsigned forcewake_count; |
4d85529d BW |
1044 | int count=0, ret; |
1045 | ||
1046 | ||
1047 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
1048 | if (ret) | |
1049 | return ret; | |
1050 | ||
93b525dc DV |
1051 | spin_lock_irq(&dev_priv->gt_lock); |
1052 | forcewake_count = dev_priv->forcewake_count; | |
1053 | spin_unlock_irq(&dev_priv->gt_lock); | |
1054 | ||
1055 | if (forcewake_count) { | |
1056 | seq_printf(m, "RC information inaccurate because somebody " | |
1057 | "holds a forcewake reference \n"); | |
4d85529d BW |
1058 | } else { |
1059 | /* NB: we cannot use forcewake, else we read the wrong values */ | |
1060 | while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1)) | |
1061 | udelay(10); | |
1062 | seq_printf(m, "RC information accurate: %s\n", yesno(count < 51)); | |
1063 | } | |
1064 | ||
1065 | gt_core_status = readl(dev_priv->regs + GEN6_GT_CORE_STATUS); | |
1066 | trace_i915_reg_rw(false, GEN6_GT_CORE_STATUS, gt_core_status, 4); | |
1067 | ||
1068 | rpmodectl1 = I915_READ(GEN6_RP_CONTROL); | |
1069 | rcctl1 = I915_READ(GEN6_RC_CONTROL); | |
1070 | mutex_unlock(&dev->struct_mutex); | |
1071 | ||
1072 | seq_printf(m, "Video Turbo Mode: %s\n", | |
1073 | yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO)); | |
1074 | seq_printf(m, "HW control enabled: %s\n", | |
1075 | yesno(rpmodectl1 & GEN6_RP_ENABLE)); | |
1076 | seq_printf(m, "SW control enabled: %s\n", | |
1077 | yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) == | |
1078 | GEN6_RP_MEDIA_SW_MODE)); | |
fff24e21 | 1079 | seq_printf(m, "RC1e Enabled: %s\n", |
4d85529d BW |
1080 | yesno(rcctl1 & GEN6_RC_CTL_RC1e_ENABLE)); |
1081 | seq_printf(m, "RC6 Enabled: %s\n", | |
1082 | yesno(rcctl1 & GEN6_RC_CTL_RC6_ENABLE)); | |
1083 | seq_printf(m, "Deep RC6 Enabled: %s\n", | |
1084 | yesno(rcctl1 & GEN6_RC_CTL_RC6p_ENABLE)); | |
1085 | seq_printf(m, "Deepest RC6 Enabled: %s\n", | |
1086 | yesno(rcctl1 & GEN6_RC_CTL_RC6pp_ENABLE)); | |
1087 | seq_printf(m, "Current RC state: "); | |
1088 | switch (gt_core_status & GEN6_RCn_MASK) { | |
1089 | case GEN6_RC0: | |
1090 | if (gt_core_status & GEN6_CORE_CPD_STATE_MASK) | |
1091 | seq_printf(m, "Core Power Down\n"); | |
1092 | else | |
1093 | seq_printf(m, "on\n"); | |
1094 | break; | |
1095 | case GEN6_RC3: | |
1096 | seq_printf(m, "RC3\n"); | |
1097 | break; | |
1098 | case GEN6_RC6: | |
1099 | seq_printf(m, "RC6\n"); | |
1100 | break; | |
1101 | case GEN6_RC7: | |
1102 | seq_printf(m, "RC7\n"); | |
1103 | break; | |
1104 | default: | |
1105 | seq_printf(m, "Unknown\n"); | |
1106 | break; | |
1107 | } | |
1108 | ||
1109 | seq_printf(m, "Core Power Down: %s\n", | |
1110 | yesno(gt_core_status & GEN6_CORE_CPD_STATE_MASK)); | |
cce66a28 BW |
1111 | |
1112 | /* Not exactly sure what this is */ | |
1113 | seq_printf(m, "RC6 \"Locked to RPn\" residency since boot: %u\n", | |
1114 | I915_READ(GEN6_GT_GFX_RC6_LOCKED)); | |
1115 | seq_printf(m, "RC6 residency since boot: %u\n", | |
1116 | I915_READ(GEN6_GT_GFX_RC6)); | |
1117 | seq_printf(m, "RC6+ residency since boot: %u\n", | |
1118 | I915_READ(GEN6_GT_GFX_RC6p)); | |
1119 | seq_printf(m, "RC6++ residency since boot: %u\n", | |
1120 | I915_READ(GEN6_GT_GFX_RC6pp)); | |
1121 | ||
4d85529d BW |
1122 | return 0; |
1123 | } | |
1124 | ||
1125 | static int i915_drpc_info(struct seq_file *m, void *unused) | |
1126 | { | |
1127 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1128 | struct drm_device *dev = node->minor->dev; | |
1129 | ||
1130 | if (IS_GEN6(dev) || IS_GEN7(dev)) | |
1131 | return gen6_drpc_info(m); | |
1132 | else | |
1133 | return ironlake_drpc_info(m); | |
1134 | } | |
1135 | ||
b5e50c3f JB |
1136 | static int i915_fbc_status(struct seq_file *m, void *unused) |
1137 | { | |
1138 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1139 | struct drm_device *dev = node->minor->dev; | |
b5e50c3f | 1140 | drm_i915_private_t *dev_priv = dev->dev_private; |
b5e50c3f | 1141 | |
ee5382ae | 1142 | if (!I915_HAS_FBC(dev)) { |
b5e50c3f JB |
1143 | seq_printf(m, "FBC unsupported on this chipset\n"); |
1144 | return 0; | |
1145 | } | |
1146 | ||
ee5382ae | 1147 | if (intel_fbc_enabled(dev)) { |
b5e50c3f JB |
1148 | seq_printf(m, "FBC enabled\n"); |
1149 | } else { | |
1150 | seq_printf(m, "FBC disabled: "); | |
1151 | switch (dev_priv->no_fbc_reason) { | |
bed4a673 CW |
1152 | case FBC_NO_OUTPUT: |
1153 | seq_printf(m, "no outputs"); | |
1154 | break; | |
b5e50c3f JB |
1155 | case FBC_STOLEN_TOO_SMALL: |
1156 | seq_printf(m, "not enough stolen memory"); | |
1157 | break; | |
1158 | case FBC_UNSUPPORTED_MODE: | |
1159 | seq_printf(m, "mode not supported"); | |
1160 | break; | |
1161 | case FBC_MODE_TOO_LARGE: | |
1162 | seq_printf(m, "mode too large"); | |
1163 | break; | |
1164 | case FBC_BAD_PLANE: | |
1165 | seq_printf(m, "FBC unsupported on plane"); | |
1166 | break; | |
1167 | case FBC_NOT_TILED: | |
1168 | seq_printf(m, "scanout buffer not tiled"); | |
1169 | break; | |
9c928d16 JB |
1170 | case FBC_MULTIPLE_PIPES: |
1171 | seq_printf(m, "multiple pipes are enabled"); | |
1172 | break; | |
c1a9f047 JB |
1173 | case FBC_MODULE_PARAM: |
1174 | seq_printf(m, "disabled per module param (default off)"); | |
1175 | break; | |
b5e50c3f JB |
1176 | default: |
1177 | seq_printf(m, "unknown reason"); | |
1178 | } | |
1179 | seq_printf(m, "\n"); | |
1180 | } | |
1181 | return 0; | |
1182 | } | |
1183 | ||
4a9bef37 JB |
1184 | static int i915_sr_status(struct seq_file *m, void *unused) |
1185 | { | |
1186 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1187 | struct drm_device *dev = node->minor->dev; | |
1188 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1189 | bool sr_enabled = false; | |
1190 | ||
1398261a | 1191 | if (HAS_PCH_SPLIT(dev)) |
5ba2aaaa | 1192 | sr_enabled = I915_READ(WM1_LP_ILK) & WM1_LP_SR_EN; |
a6c45cf0 | 1193 | else if (IS_CRESTLINE(dev) || IS_I945G(dev) || IS_I945GM(dev)) |
4a9bef37 JB |
1194 | sr_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN; |
1195 | else if (IS_I915GM(dev)) | |
1196 | sr_enabled = I915_READ(INSTPM) & INSTPM_SELF_EN; | |
1197 | else if (IS_PINEVIEW(dev)) | |
1198 | sr_enabled = I915_READ(DSPFW3) & PINEVIEW_SELF_REFRESH_EN; | |
1199 | ||
5ba2aaaa CW |
1200 | seq_printf(m, "self-refresh: %s\n", |
1201 | sr_enabled ? "enabled" : "disabled"); | |
4a9bef37 JB |
1202 | |
1203 | return 0; | |
1204 | } | |
1205 | ||
7648fa99 JB |
1206 | static int i915_emon_status(struct seq_file *m, void *unused) |
1207 | { | |
1208 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1209 | struct drm_device *dev = node->minor->dev; | |
1210 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1211 | unsigned long temp, chipset, gfx; | |
de227ef0 CW |
1212 | int ret; |
1213 | ||
1214 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
1215 | if (ret) | |
1216 | return ret; | |
7648fa99 JB |
1217 | |
1218 | temp = i915_mch_val(dev_priv); | |
1219 | chipset = i915_chipset_val(dev_priv); | |
1220 | gfx = i915_gfx_val(dev_priv); | |
de227ef0 | 1221 | mutex_unlock(&dev->struct_mutex); |
7648fa99 JB |
1222 | |
1223 | seq_printf(m, "GMCH temp: %ld\n", temp); | |
1224 | seq_printf(m, "Chipset power: %ld\n", chipset); | |
1225 | seq_printf(m, "GFX power: %ld\n", gfx); | |
1226 | seq_printf(m, "Total power: %ld\n", chipset + gfx); | |
1227 | ||
1228 | return 0; | |
1229 | } | |
1230 | ||
23b2f8bb JB |
1231 | static int i915_ring_freq_table(struct seq_file *m, void *unused) |
1232 | { | |
1233 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1234 | struct drm_device *dev = node->minor->dev; | |
1235 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1236 | int ret; | |
1237 | int gpu_freq, ia_freq; | |
1238 | ||
1c70c0ce | 1239 | if (!(IS_GEN6(dev) || IS_GEN7(dev))) { |
23b2f8bb JB |
1240 | seq_printf(m, "unsupported on this chipset\n"); |
1241 | return 0; | |
1242 | } | |
1243 | ||
1244 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
1245 | if (ret) | |
1246 | return ret; | |
1247 | ||
1248 | seq_printf(m, "GPU freq (MHz)\tEffective CPU freq (MHz)\n"); | |
1249 | ||
1250 | for (gpu_freq = dev_priv->min_delay; gpu_freq <= dev_priv->max_delay; | |
1251 | gpu_freq++) { | |
1252 | I915_WRITE(GEN6_PCODE_DATA, gpu_freq); | |
1253 | I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | | |
1254 | GEN6_PCODE_READ_MIN_FREQ_TABLE); | |
1255 | if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & | |
1256 | GEN6_PCODE_READY) == 0, 10)) { | |
1257 | DRM_ERROR("pcode read of freq table timed out\n"); | |
1258 | continue; | |
1259 | } | |
1260 | ia_freq = I915_READ(GEN6_PCODE_DATA); | |
1261 | seq_printf(m, "%d\t\t%d\n", gpu_freq * 50, ia_freq * 100); | |
1262 | } | |
1263 | ||
1264 | mutex_unlock(&dev->struct_mutex); | |
1265 | ||
1266 | return 0; | |
1267 | } | |
1268 | ||
7648fa99 JB |
1269 | static int i915_gfxec(struct seq_file *m, void *unused) |
1270 | { | |
1271 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1272 | struct drm_device *dev = node->minor->dev; | |
1273 | drm_i915_private_t *dev_priv = dev->dev_private; | |
616fdb5a BW |
1274 | int ret; |
1275 | ||
1276 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
1277 | if (ret) | |
1278 | return ret; | |
7648fa99 JB |
1279 | |
1280 | seq_printf(m, "GFXEC: %ld\n", (unsigned long)I915_READ(0x112f4)); | |
1281 | ||
616fdb5a BW |
1282 | mutex_unlock(&dev->struct_mutex); |
1283 | ||
7648fa99 JB |
1284 | return 0; |
1285 | } | |
1286 | ||
44834a67 CW |
1287 | static int i915_opregion(struct seq_file *m, void *unused) |
1288 | { | |
1289 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1290 | struct drm_device *dev = node->minor->dev; | |
1291 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1292 | struct intel_opregion *opregion = &dev_priv->opregion; | |
1293 | int ret; | |
1294 | ||
1295 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
1296 | if (ret) | |
1297 | return ret; | |
1298 | ||
1299 | if (opregion->header) | |
1300 | seq_write(m, opregion->header, OPREGION_SIZE); | |
1301 | ||
1302 | mutex_unlock(&dev->struct_mutex); | |
1303 | ||
1304 | return 0; | |
1305 | } | |
1306 | ||
37811fcc CW |
1307 | static int i915_gem_framebuffer_info(struct seq_file *m, void *data) |
1308 | { | |
1309 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1310 | struct drm_device *dev = node->minor->dev; | |
1311 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1312 | struct intel_fbdev *ifbdev; | |
1313 | struct intel_framebuffer *fb; | |
1314 | int ret; | |
1315 | ||
1316 | ret = mutex_lock_interruptible(&dev->mode_config.mutex); | |
1317 | if (ret) | |
1318 | return ret; | |
1319 | ||
1320 | ifbdev = dev_priv->fbdev; | |
1321 | fb = to_intel_framebuffer(ifbdev->helper.fb); | |
1322 | ||
1323 | seq_printf(m, "fbcon size: %d x %d, depth %d, %d bpp, obj ", | |
1324 | fb->base.width, | |
1325 | fb->base.height, | |
1326 | fb->base.depth, | |
1327 | fb->base.bits_per_pixel); | |
05394f39 | 1328 | describe_obj(m, fb->obj); |
37811fcc CW |
1329 | seq_printf(m, "\n"); |
1330 | ||
1331 | list_for_each_entry(fb, &dev->mode_config.fb_list, base.head) { | |
1332 | if (&fb->base == ifbdev->helper.fb) | |
1333 | continue; | |
1334 | ||
1335 | seq_printf(m, "user size: %d x %d, depth %d, %d bpp, obj ", | |
1336 | fb->base.width, | |
1337 | fb->base.height, | |
1338 | fb->base.depth, | |
1339 | fb->base.bits_per_pixel); | |
05394f39 | 1340 | describe_obj(m, fb->obj); |
37811fcc CW |
1341 | seq_printf(m, "\n"); |
1342 | } | |
1343 | ||
1344 | mutex_unlock(&dev->mode_config.mutex); | |
1345 | ||
1346 | return 0; | |
1347 | } | |
1348 | ||
e76d3630 BW |
1349 | static int i915_context_status(struct seq_file *m, void *unused) |
1350 | { | |
1351 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1352 | struct drm_device *dev = node->minor->dev; | |
1353 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1354 | int ret; | |
1355 | ||
1356 | ret = mutex_lock_interruptible(&dev->mode_config.mutex); | |
1357 | if (ret) | |
1358 | return ret; | |
1359 | ||
dc501fbc BW |
1360 | if (dev_priv->pwrctx) { |
1361 | seq_printf(m, "power context "); | |
1362 | describe_obj(m, dev_priv->pwrctx); | |
1363 | seq_printf(m, "\n"); | |
1364 | } | |
e76d3630 | 1365 | |
dc501fbc BW |
1366 | if (dev_priv->renderctx) { |
1367 | seq_printf(m, "render context "); | |
1368 | describe_obj(m, dev_priv->renderctx); | |
1369 | seq_printf(m, "\n"); | |
1370 | } | |
e76d3630 BW |
1371 | |
1372 | mutex_unlock(&dev->mode_config.mutex); | |
1373 | ||
1374 | return 0; | |
1375 | } | |
1376 | ||
6d794d42 BW |
1377 | static int i915_gen6_forcewake_count_info(struct seq_file *m, void *data) |
1378 | { | |
1379 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1380 | struct drm_device *dev = node->minor->dev; | |
1381 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9f1f46a4 | 1382 | unsigned forcewake_count; |
6d794d42 | 1383 | |
9f1f46a4 DV |
1384 | spin_lock_irq(&dev_priv->gt_lock); |
1385 | forcewake_count = dev_priv->forcewake_count; | |
1386 | spin_unlock_irq(&dev_priv->gt_lock); | |
6d794d42 | 1387 | |
9f1f46a4 | 1388 | seq_printf(m, "forcewake count = %u\n", forcewake_count); |
6d794d42 BW |
1389 | |
1390 | return 0; | |
1391 | } | |
1392 | ||
ea16a3cd DV |
1393 | static const char *swizzle_string(unsigned swizzle) |
1394 | { | |
1395 | switch(swizzle) { | |
1396 | case I915_BIT_6_SWIZZLE_NONE: | |
1397 | return "none"; | |
1398 | case I915_BIT_6_SWIZZLE_9: | |
1399 | return "bit9"; | |
1400 | case I915_BIT_6_SWIZZLE_9_10: | |
1401 | return "bit9/bit10"; | |
1402 | case I915_BIT_6_SWIZZLE_9_11: | |
1403 | return "bit9/bit11"; | |
1404 | case I915_BIT_6_SWIZZLE_9_10_11: | |
1405 | return "bit9/bit10/bit11"; | |
1406 | case I915_BIT_6_SWIZZLE_9_17: | |
1407 | return "bit9/bit17"; | |
1408 | case I915_BIT_6_SWIZZLE_9_10_17: | |
1409 | return "bit9/bit10/bit17"; | |
1410 | case I915_BIT_6_SWIZZLE_UNKNOWN: | |
1411 | return "unkown"; | |
1412 | } | |
1413 | ||
1414 | return "bug"; | |
1415 | } | |
1416 | ||
1417 | static int i915_swizzle_info(struct seq_file *m, void *data) | |
1418 | { | |
1419 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1420 | struct drm_device *dev = node->minor->dev; | |
1421 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1422 | ||
1423 | mutex_lock(&dev->struct_mutex); | |
1424 | seq_printf(m, "bit6 swizzle for X-tiling = %s\n", | |
1425 | swizzle_string(dev_priv->mm.bit_6_swizzle_x)); | |
1426 | seq_printf(m, "bit6 swizzle for Y-tiling = %s\n", | |
1427 | swizzle_string(dev_priv->mm.bit_6_swizzle_y)); | |
1428 | ||
1429 | if (IS_GEN3(dev) || IS_GEN4(dev)) { | |
1430 | seq_printf(m, "DDC = 0x%08x\n", | |
1431 | I915_READ(DCC)); | |
1432 | seq_printf(m, "C0DRB3 = 0x%04x\n", | |
1433 | I915_READ16(C0DRB3)); | |
1434 | seq_printf(m, "C1DRB3 = 0x%04x\n", | |
1435 | I915_READ16(C1DRB3)); | |
3fa7d235 DV |
1436 | } else if (IS_GEN6(dev) || IS_GEN7(dev)) { |
1437 | seq_printf(m, "MAD_DIMM_C0 = 0x%08x\n", | |
1438 | I915_READ(MAD_DIMM_C0)); | |
1439 | seq_printf(m, "MAD_DIMM_C1 = 0x%08x\n", | |
1440 | I915_READ(MAD_DIMM_C1)); | |
1441 | seq_printf(m, "MAD_DIMM_C2 = 0x%08x\n", | |
1442 | I915_READ(MAD_DIMM_C2)); | |
1443 | seq_printf(m, "TILECTL = 0x%08x\n", | |
1444 | I915_READ(TILECTL)); | |
1445 | seq_printf(m, "ARB_MODE = 0x%08x\n", | |
1446 | I915_READ(ARB_MODE)); | |
1447 | seq_printf(m, "DISP_ARB_CTL = 0x%08x\n", | |
1448 | I915_READ(DISP_ARB_CTL)); | |
ea16a3cd DV |
1449 | } |
1450 | mutex_unlock(&dev->struct_mutex); | |
1451 | ||
1452 | return 0; | |
1453 | } | |
1454 | ||
3cf17fc5 DV |
1455 | static int i915_ppgtt_info(struct seq_file *m, void *data) |
1456 | { | |
1457 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1458 | struct drm_device *dev = node->minor->dev; | |
1459 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1460 | struct intel_ring_buffer *ring; | |
1461 | int i, ret; | |
1462 | ||
1463 | ||
1464 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
1465 | if (ret) | |
1466 | return ret; | |
1467 | if (INTEL_INFO(dev)->gen == 6) | |
1468 | seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(GFX_MODE)); | |
1469 | ||
1470 | for (i = 0; i < I915_NUM_RINGS; i++) { | |
1471 | ring = &dev_priv->ring[i]; | |
1472 | ||
1473 | seq_printf(m, "%s\n", ring->name); | |
1474 | if (INTEL_INFO(dev)->gen == 7) | |
1475 | seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(RING_MODE_GEN7(ring))); | |
1476 | seq_printf(m, "PP_DIR_BASE: 0x%08x\n", I915_READ(RING_PP_DIR_BASE(ring))); | |
1477 | seq_printf(m, "PP_DIR_BASE_READ: 0x%08x\n", I915_READ(RING_PP_DIR_BASE_READ(ring))); | |
1478 | seq_printf(m, "PP_DIR_DCLV: 0x%08x\n", I915_READ(RING_PP_DIR_DCLV(ring))); | |
1479 | } | |
1480 | if (dev_priv->mm.aliasing_ppgtt) { | |
1481 | struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt; | |
1482 | ||
1483 | seq_printf(m, "aliasing PPGTT:\n"); | |
1484 | seq_printf(m, "pd gtt offset: 0x%08x\n", ppgtt->pd_offset); | |
1485 | } | |
1486 | seq_printf(m, "ECOCHK: 0x%08x\n", I915_READ(GAM_ECOCHK)); | |
1487 | mutex_unlock(&dev->struct_mutex); | |
1488 | ||
1489 | return 0; | |
1490 | } | |
1491 | ||
57f350b6 JB |
1492 | static int i915_dpio_info(struct seq_file *m, void *data) |
1493 | { | |
1494 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1495 | struct drm_device *dev = node->minor->dev; | |
1496 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1497 | int ret; | |
1498 | ||
1499 | ||
1500 | if (!IS_VALLEYVIEW(dev)) { | |
1501 | seq_printf(m, "unsupported\n"); | |
1502 | return 0; | |
1503 | } | |
1504 | ||
1505 | ret = mutex_lock_interruptible(&dev->mode_config.mutex); | |
1506 | if (ret) | |
1507 | return ret; | |
1508 | ||
1509 | seq_printf(m, "DPIO_CTL: 0x%08x\n", I915_READ(DPIO_CTL)); | |
1510 | ||
1511 | seq_printf(m, "DPIO_DIV_A: 0x%08x\n", | |
1512 | intel_dpio_read(dev_priv, _DPIO_DIV_A)); | |
1513 | seq_printf(m, "DPIO_DIV_B: 0x%08x\n", | |
1514 | intel_dpio_read(dev_priv, _DPIO_DIV_B)); | |
1515 | ||
1516 | seq_printf(m, "DPIO_REFSFR_A: 0x%08x\n", | |
1517 | intel_dpio_read(dev_priv, _DPIO_REFSFR_A)); | |
1518 | seq_printf(m, "DPIO_REFSFR_B: 0x%08x\n", | |
1519 | intel_dpio_read(dev_priv, _DPIO_REFSFR_B)); | |
1520 | ||
1521 | seq_printf(m, "DPIO_CORE_CLK_A: 0x%08x\n", | |
1522 | intel_dpio_read(dev_priv, _DPIO_CORE_CLK_A)); | |
1523 | seq_printf(m, "DPIO_CORE_CLK_B: 0x%08x\n", | |
1524 | intel_dpio_read(dev_priv, _DPIO_CORE_CLK_B)); | |
1525 | ||
1526 | seq_printf(m, "DPIO_LFP_COEFF_A: 0x%08x\n", | |
1527 | intel_dpio_read(dev_priv, _DPIO_LFP_COEFF_A)); | |
1528 | seq_printf(m, "DPIO_LFP_COEFF_B: 0x%08x\n", | |
1529 | intel_dpio_read(dev_priv, _DPIO_LFP_COEFF_B)); | |
1530 | ||
1531 | seq_printf(m, "DPIO_FASTCLK_DISABLE: 0x%08x\n", | |
1532 | intel_dpio_read(dev_priv, DPIO_FASTCLK_DISABLE)); | |
1533 | ||
1534 | mutex_unlock(&dev->mode_config.mutex); | |
1535 | ||
1536 | return 0; | |
1537 | } | |
1538 | ||
f3cd474b CW |
1539 | static ssize_t |
1540 | i915_wedged_read(struct file *filp, | |
1541 | char __user *ubuf, | |
1542 | size_t max, | |
1543 | loff_t *ppos) | |
1544 | { | |
1545 | struct drm_device *dev = filp->private_data; | |
1546 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1547 | char buf[80]; | |
1548 | int len; | |
1549 | ||
0206e353 | 1550 | len = snprintf(buf, sizeof(buf), |
f3cd474b CW |
1551 | "wedged : %d\n", |
1552 | atomic_read(&dev_priv->mm.wedged)); | |
1553 | ||
0206e353 AJ |
1554 | if (len > sizeof(buf)) |
1555 | len = sizeof(buf); | |
f4433a8d | 1556 | |
f3cd474b CW |
1557 | return simple_read_from_buffer(ubuf, max, ppos, buf, len); |
1558 | } | |
1559 | ||
1560 | static ssize_t | |
1561 | i915_wedged_write(struct file *filp, | |
1562 | const char __user *ubuf, | |
1563 | size_t cnt, | |
1564 | loff_t *ppos) | |
1565 | { | |
1566 | struct drm_device *dev = filp->private_data; | |
f3cd474b CW |
1567 | char buf[20]; |
1568 | int val = 1; | |
1569 | ||
1570 | if (cnt > 0) { | |
0206e353 | 1571 | if (cnt > sizeof(buf) - 1) |
f3cd474b CW |
1572 | return -EINVAL; |
1573 | ||
1574 | if (copy_from_user(buf, ubuf, cnt)) | |
1575 | return -EFAULT; | |
1576 | buf[cnt] = 0; | |
1577 | ||
1578 | val = simple_strtoul(buf, NULL, 0); | |
1579 | } | |
1580 | ||
1581 | DRM_INFO("Manually setting wedged to %d\n", val); | |
527f9e90 | 1582 | i915_handle_error(dev, val); |
f3cd474b CW |
1583 | |
1584 | return cnt; | |
1585 | } | |
1586 | ||
1587 | static const struct file_operations i915_wedged_fops = { | |
1588 | .owner = THIS_MODULE, | |
234e3405 | 1589 | .open = simple_open, |
f3cd474b CW |
1590 | .read = i915_wedged_read, |
1591 | .write = i915_wedged_write, | |
6038f373 | 1592 | .llseek = default_llseek, |
f3cd474b CW |
1593 | }; |
1594 | ||
358733e9 JB |
1595 | static ssize_t |
1596 | i915_max_freq_read(struct file *filp, | |
1597 | char __user *ubuf, | |
1598 | size_t max, | |
1599 | loff_t *ppos) | |
1600 | { | |
1601 | struct drm_device *dev = filp->private_data; | |
1602 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1603 | char buf[80]; | |
1604 | int len; | |
1605 | ||
0206e353 | 1606 | len = snprintf(buf, sizeof(buf), |
358733e9 JB |
1607 | "max freq: %d\n", dev_priv->max_delay * 50); |
1608 | ||
0206e353 AJ |
1609 | if (len > sizeof(buf)) |
1610 | len = sizeof(buf); | |
358733e9 JB |
1611 | |
1612 | return simple_read_from_buffer(ubuf, max, ppos, buf, len); | |
1613 | } | |
1614 | ||
1615 | static ssize_t | |
1616 | i915_max_freq_write(struct file *filp, | |
1617 | const char __user *ubuf, | |
1618 | size_t cnt, | |
1619 | loff_t *ppos) | |
1620 | { | |
1621 | struct drm_device *dev = filp->private_data; | |
1622 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1623 | char buf[20]; | |
1624 | int val = 1; | |
1625 | ||
1626 | if (cnt > 0) { | |
0206e353 | 1627 | if (cnt > sizeof(buf) - 1) |
358733e9 JB |
1628 | return -EINVAL; |
1629 | ||
1630 | if (copy_from_user(buf, ubuf, cnt)) | |
1631 | return -EFAULT; | |
1632 | buf[cnt] = 0; | |
1633 | ||
1634 | val = simple_strtoul(buf, NULL, 0); | |
1635 | } | |
1636 | ||
1637 | DRM_DEBUG_DRIVER("Manually setting max freq to %d\n", val); | |
1638 | ||
1639 | /* | |
1640 | * Turbo will still be enabled, but won't go above the set value. | |
1641 | */ | |
1642 | dev_priv->max_delay = val / 50; | |
1643 | ||
1644 | gen6_set_rps(dev, val / 50); | |
1645 | ||
1646 | return cnt; | |
1647 | } | |
1648 | ||
1649 | static const struct file_operations i915_max_freq_fops = { | |
1650 | .owner = THIS_MODULE, | |
234e3405 | 1651 | .open = simple_open, |
358733e9 JB |
1652 | .read = i915_max_freq_read, |
1653 | .write = i915_max_freq_write, | |
1654 | .llseek = default_llseek, | |
1655 | }; | |
1656 | ||
07b7ddd9 JB |
1657 | static ssize_t |
1658 | i915_cache_sharing_read(struct file *filp, | |
1659 | char __user *ubuf, | |
1660 | size_t max, | |
1661 | loff_t *ppos) | |
1662 | { | |
1663 | struct drm_device *dev = filp->private_data; | |
1664 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1665 | char buf[80]; | |
1666 | u32 snpcr; | |
1667 | int len; | |
1668 | ||
1669 | mutex_lock(&dev_priv->dev->struct_mutex); | |
1670 | snpcr = I915_READ(GEN6_MBCUNIT_SNPCR); | |
1671 | mutex_unlock(&dev_priv->dev->struct_mutex); | |
1672 | ||
0206e353 | 1673 | len = snprintf(buf, sizeof(buf), |
07b7ddd9 JB |
1674 | "%d\n", (snpcr & GEN6_MBC_SNPCR_MASK) >> |
1675 | GEN6_MBC_SNPCR_SHIFT); | |
1676 | ||
0206e353 AJ |
1677 | if (len > sizeof(buf)) |
1678 | len = sizeof(buf); | |
07b7ddd9 JB |
1679 | |
1680 | return simple_read_from_buffer(ubuf, max, ppos, buf, len); | |
1681 | } | |
1682 | ||
1683 | static ssize_t | |
1684 | i915_cache_sharing_write(struct file *filp, | |
1685 | const char __user *ubuf, | |
1686 | size_t cnt, | |
1687 | loff_t *ppos) | |
1688 | { | |
1689 | struct drm_device *dev = filp->private_data; | |
1690 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1691 | char buf[20]; | |
1692 | u32 snpcr; | |
1693 | int val = 1; | |
1694 | ||
1695 | if (cnt > 0) { | |
0206e353 | 1696 | if (cnt > sizeof(buf) - 1) |
07b7ddd9 JB |
1697 | return -EINVAL; |
1698 | ||
1699 | if (copy_from_user(buf, ubuf, cnt)) | |
1700 | return -EFAULT; | |
1701 | buf[cnt] = 0; | |
1702 | ||
1703 | val = simple_strtoul(buf, NULL, 0); | |
1704 | } | |
1705 | ||
1706 | if (val < 0 || val > 3) | |
1707 | return -EINVAL; | |
1708 | ||
1709 | DRM_DEBUG_DRIVER("Manually setting uncore sharing to %d\n", val); | |
1710 | ||
1711 | /* Update the cache sharing policy here as well */ | |
1712 | snpcr = I915_READ(GEN6_MBCUNIT_SNPCR); | |
1713 | snpcr &= ~GEN6_MBC_SNPCR_MASK; | |
1714 | snpcr |= (val << GEN6_MBC_SNPCR_SHIFT); | |
1715 | I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr); | |
1716 | ||
1717 | return cnt; | |
1718 | } | |
1719 | ||
1720 | static const struct file_operations i915_cache_sharing_fops = { | |
1721 | .owner = THIS_MODULE, | |
234e3405 | 1722 | .open = simple_open, |
07b7ddd9 JB |
1723 | .read = i915_cache_sharing_read, |
1724 | .write = i915_cache_sharing_write, | |
1725 | .llseek = default_llseek, | |
1726 | }; | |
1727 | ||
f3cd474b CW |
1728 | /* As the drm_debugfs_init() routines are called before dev->dev_private is |
1729 | * allocated we need to hook into the minor for release. */ | |
1730 | static int | |
1731 | drm_add_fake_info_node(struct drm_minor *minor, | |
1732 | struct dentry *ent, | |
1733 | const void *key) | |
1734 | { | |
1735 | struct drm_info_node *node; | |
1736 | ||
1737 | node = kmalloc(sizeof(struct drm_info_node), GFP_KERNEL); | |
1738 | if (node == NULL) { | |
1739 | debugfs_remove(ent); | |
1740 | return -ENOMEM; | |
1741 | } | |
1742 | ||
1743 | node->minor = minor; | |
1744 | node->dent = ent; | |
1745 | node->info_ent = (void *) key; | |
b3e067c0 MS |
1746 | |
1747 | mutex_lock(&minor->debugfs_lock); | |
1748 | list_add(&node->list, &minor->debugfs_list); | |
1749 | mutex_unlock(&minor->debugfs_lock); | |
f3cd474b CW |
1750 | |
1751 | return 0; | |
1752 | } | |
1753 | ||
6d794d42 BW |
1754 | static int i915_forcewake_open(struct inode *inode, struct file *file) |
1755 | { | |
1756 | struct drm_device *dev = inode->i_private; | |
1757 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1758 | int ret; | |
1759 | ||
075edca4 | 1760 | if (INTEL_INFO(dev)->gen < 6) |
6d794d42 BW |
1761 | return 0; |
1762 | ||
1763 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
1764 | if (ret) | |
1765 | return ret; | |
1766 | gen6_gt_force_wake_get(dev_priv); | |
1767 | mutex_unlock(&dev->struct_mutex); | |
1768 | ||
1769 | return 0; | |
1770 | } | |
1771 | ||
c43b5634 | 1772 | static int i915_forcewake_release(struct inode *inode, struct file *file) |
6d794d42 BW |
1773 | { |
1774 | struct drm_device *dev = inode->i_private; | |
1775 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1776 | ||
075edca4 | 1777 | if (INTEL_INFO(dev)->gen < 6) |
6d794d42 BW |
1778 | return 0; |
1779 | ||
1780 | /* | |
1781 | * It's bad that we can potentially hang userspace if struct_mutex gets | |
1782 | * forever stuck. However, if we cannot acquire this lock it means that | |
1783 | * almost certainly the driver has hung, is not unload-able. Therefore | |
1784 | * hanging here is probably a minor inconvenience not to be seen my | |
1785 | * almost every user. | |
1786 | */ | |
1787 | mutex_lock(&dev->struct_mutex); | |
1788 | gen6_gt_force_wake_put(dev_priv); | |
1789 | mutex_unlock(&dev->struct_mutex); | |
1790 | ||
1791 | return 0; | |
1792 | } | |
1793 | ||
1794 | static const struct file_operations i915_forcewake_fops = { | |
1795 | .owner = THIS_MODULE, | |
1796 | .open = i915_forcewake_open, | |
1797 | .release = i915_forcewake_release, | |
1798 | }; | |
1799 | ||
1800 | static int i915_forcewake_create(struct dentry *root, struct drm_minor *minor) | |
1801 | { | |
1802 | struct drm_device *dev = minor->dev; | |
1803 | struct dentry *ent; | |
1804 | ||
1805 | ent = debugfs_create_file("i915_forcewake_user", | |
8eb57294 | 1806 | S_IRUSR, |
6d794d42 BW |
1807 | root, dev, |
1808 | &i915_forcewake_fops); | |
1809 | if (IS_ERR(ent)) | |
1810 | return PTR_ERR(ent); | |
1811 | ||
8eb57294 | 1812 | return drm_add_fake_info_node(minor, ent, &i915_forcewake_fops); |
6d794d42 BW |
1813 | } |
1814 | ||
6a9c308d DV |
1815 | static int i915_debugfs_create(struct dentry *root, |
1816 | struct drm_minor *minor, | |
1817 | const char *name, | |
1818 | const struct file_operations *fops) | |
07b7ddd9 JB |
1819 | { |
1820 | struct drm_device *dev = minor->dev; | |
1821 | struct dentry *ent; | |
1822 | ||
6a9c308d | 1823 | ent = debugfs_create_file(name, |
07b7ddd9 JB |
1824 | S_IRUGO | S_IWUSR, |
1825 | root, dev, | |
6a9c308d | 1826 | fops); |
07b7ddd9 JB |
1827 | if (IS_ERR(ent)) |
1828 | return PTR_ERR(ent); | |
1829 | ||
6a9c308d | 1830 | return drm_add_fake_info_node(minor, ent, fops); |
07b7ddd9 JB |
1831 | } |
1832 | ||
27c202ad | 1833 | static struct drm_info_list i915_debugfs_list[] = { |
311bd68e | 1834 | {"i915_capabilities", i915_capabilities, 0}, |
73aa808f | 1835 | {"i915_gem_objects", i915_gem_object_info, 0}, |
08c18323 | 1836 | {"i915_gem_gtt", i915_gem_gtt_info, 0}, |
433e12f7 BG |
1837 | {"i915_gem_active", i915_gem_object_list_info, 0, (void *) ACTIVE_LIST}, |
1838 | {"i915_gem_flushing", i915_gem_object_list_info, 0, (void *) FLUSHING_LIST}, | |
1839 | {"i915_gem_inactive", i915_gem_object_list_info, 0, (void *) INACTIVE_LIST}, | |
f13d3f73 | 1840 | {"i915_gem_pinned", i915_gem_object_list_info, 0, (void *) PINNED_LIST}, |
d21d5975 | 1841 | {"i915_gem_deferred_free", i915_gem_object_list_info, 0, (void *) DEFERRED_FREE_LIST}, |
4e5359cd | 1842 | {"i915_gem_pageflip", i915_gem_pageflip_info, 0}, |
2017263e BG |
1843 | {"i915_gem_request", i915_gem_request_info, 0}, |
1844 | {"i915_gem_seqno", i915_gem_seqno_info, 0}, | |
a6172a80 | 1845 | {"i915_gem_fence_regs", i915_gem_fence_regs_info, 0}, |
2017263e | 1846 | {"i915_gem_interrupt", i915_interrupt_info, 0}, |
1ec14ad3 CW |
1847 | {"i915_gem_hws", i915_hws_info, 0, (void *)RCS}, |
1848 | {"i915_gem_hws_blt", i915_hws_info, 0, (void *)BCS}, | |
1849 | {"i915_gem_hws_bsd", i915_hws_info, 0, (void *)VCS}, | |
63eeaf38 | 1850 | {"i915_error_state", i915_error_state, 0}, |
f97108d1 JB |
1851 | {"i915_rstdby_delays", i915_rstdby_delays, 0}, |
1852 | {"i915_cur_delayinfo", i915_cur_delayinfo, 0}, | |
1853 | {"i915_delayfreq_table", i915_delayfreq_table, 0}, | |
1854 | {"i915_inttoext_table", i915_inttoext_table, 0}, | |
1855 | {"i915_drpc_info", i915_drpc_info, 0}, | |
7648fa99 | 1856 | {"i915_emon_status", i915_emon_status, 0}, |
23b2f8bb | 1857 | {"i915_ring_freq_table", i915_ring_freq_table, 0}, |
7648fa99 | 1858 | {"i915_gfxec", i915_gfxec, 0}, |
b5e50c3f | 1859 | {"i915_fbc_status", i915_fbc_status, 0}, |
4a9bef37 | 1860 | {"i915_sr_status", i915_sr_status, 0}, |
44834a67 | 1861 | {"i915_opregion", i915_opregion, 0}, |
37811fcc | 1862 | {"i915_gem_framebuffer", i915_gem_framebuffer_info, 0}, |
e76d3630 | 1863 | {"i915_context_status", i915_context_status, 0}, |
6d794d42 | 1864 | {"i915_gen6_forcewake_count", i915_gen6_forcewake_count_info, 0}, |
ea16a3cd | 1865 | {"i915_swizzle_info", i915_swizzle_info, 0}, |
3cf17fc5 | 1866 | {"i915_ppgtt_info", i915_ppgtt_info, 0}, |
57f350b6 | 1867 | {"i915_dpio", i915_dpio_info, 0}, |
2017263e | 1868 | }; |
27c202ad | 1869 | #define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list) |
2017263e | 1870 | |
27c202ad | 1871 | int i915_debugfs_init(struct drm_minor *minor) |
2017263e | 1872 | { |
f3cd474b CW |
1873 | int ret; |
1874 | ||
6a9c308d DV |
1875 | ret = i915_debugfs_create(minor->debugfs_root, minor, |
1876 | "i915_wedged", | |
1877 | &i915_wedged_fops); | |
f3cd474b CW |
1878 | if (ret) |
1879 | return ret; | |
1880 | ||
6d794d42 | 1881 | ret = i915_forcewake_create(minor->debugfs_root, minor); |
358733e9 JB |
1882 | if (ret) |
1883 | return ret; | |
6a9c308d DV |
1884 | |
1885 | ret = i915_debugfs_create(minor->debugfs_root, minor, | |
1886 | "i915_max_freq", | |
1887 | &i915_max_freq_fops); | |
07b7ddd9 JB |
1888 | if (ret) |
1889 | return ret; | |
6a9c308d DV |
1890 | |
1891 | ret = i915_debugfs_create(minor->debugfs_root, minor, | |
1892 | "i915_cache_sharing", | |
1893 | &i915_cache_sharing_fops); | |
6d794d42 BW |
1894 | if (ret) |
1895 | return ret; | |
1896 | ||
27c202ad BG |
1897 | return drm_debugfs_create_files(i915_debugfs_list, |
1898 | I915_DEBUGFS_ENTRIES, | |
2017263e BG |
1899 | minor->debugfs_root, minor); |
1900 | } | |
1901 | ||
27c202ad | 1902 | void i915_debugfs_cleanup(struct drm_minor *minor) |
2017263e | 1903 | { |
27c202ad BG |
1904 | drm_debugfs_remove_files(i915_debugfs_list, |
1905 | I915_DEBUGFS_ENTRIES, minor); | |
6d794d42 BW |
1906 | drm_debugfs_remove_files((struct drm_info_list *) &i915_forcewake_fops, |
1907 | 1, minor); | |
33db679b KH |
1908 | drm_debugfs_remove_files((struct drm_info_list *) &i915_wedged_fops, |
1909 | 1, minor); | |
358733e9 JB |
1910 | drm_debugfs_remove_files((struct drm_info_list *) &i915_max_freq_fops, |
1911 | 1, minor); | |
07b7ddd9 JB |
1912 | drm_debugfs_remove_files((struct drm_info_list *) &i915_cache_sharing_fops, |
1913 | 1, minor); | |
2017263e BG |
1914 | } |
1915 | ||
1916 | #endif /* CONFIG_DEBUG_FS */ |