Commit | Line | Data |
---|---|---|
2017263e BG |
1 | /* |
2 | * Copyright © 2008 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | * Keith Packard <keithp@keithp.com> | |
26 | * | |
27 | */ | |
28 | ||
29 | #include <linux/seq_file.h> | |
b2c88f5b | 30 | #include <linux/circ_buf.h> |
926321d5 | 31 | #include <linux/ctype.h> |
f3cd474b | 32 | #include <linux/debugfs.h> |
5a0e3ad6 | 33 | #include <linux/slab.h> |
2d1a8a48 | 34 | #include <linux/export.h> |
6d2b8885 | 35 | #include <linux/list_sort.h> |
ec013e7f | 36 | #include <asm/msr-index.h> |
760285e7 | 37 | #include <drm/drmP.h> |
4e5359cd | 38 | #include "intel_drv.h" |
e5c65260 | 39 | #include "intel_ringbuffer.h" |
760285e7 | 40 | #include <drm/i915_drm.h> |
2017263e BG |
41 | #include "i915_drv.h" |
42 | ||
f13d3f73 | 43 | enum { |
69dc4987 | 44 | ACTIVE_LIST, |
f13d3f73 | 45 | INACTIVE_LIST, |
d21d5975 | 46 | PINNED_LIST, |
f13d3f73 | 47 | }; |
2017263e | 48 | |
70d39fe4 CW |
49 | static const char *yesno(int v) |
50 | { | |
51 | return v ? "yes" : "no"; | |
52 | } | |
53 | ||
497666d8 DL |
54 | /* As the drm_debugfs_init() routines are called before dev->dev_private is |
55 | * allocated we need to hook into the minor for release. */ | |
56 | static int | |
57 | drm_add_fake_info_node(struct drm_minor *minor, | |
58 | struct dentry *ent, | |
59 | const void *key) | |
60 | { | |
61 | struct drm_info_node *node; | |
62 | ||
63 | node = kmalloc(sizeof(*node), GFP_KERNEL); | |
64 | if (node == NULL) { | |
65 | debugfs_remove(ent); | |
66 | return -ENOMEM; | |
67 | } | |
68 | ||
69 | node->minor = minor; | |
70 | node->dent = ent; | |
71 | node->info_ent = (void *) key; | |
72 | ||
73 | mutex_lock(&minor->debugfs_lock); | |
74 | list_add(&node->list, &minor->debugfs_list); | |
75 | mutex_unlock(&minor->debugfs_lock); | |
76 | ||
77 | return 0; | |
78 | } | |
79 | ||
70d39fe4 CW |
80 | static int i915_capabilities(struct seq_file *m, void *data) |
81 | { | |
9f25d007 | 82 | struct drm_info_node *node = m->private; |
70d39fe4 CW |
83 | struct drm_device *dev = node->minor->dev; |
84 | const struct intel_device_info *info = INTEL_INFO(dev); | |
85 | ||
86 | seq_printf(m, "gen: %d\n", info->gen); | |
03d00ac5 | 87 | seq_printf(m, "pch: %d\n", INTEL_PCH_TYPE(dev)); |
79fc46df DL |
88 | #define PRINT_FLAG(x) seq_printf(m, #x ": %s\n", yesno(info->x)) |
89 | #define SEP_SEMICOLON ; | |
90 | DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG, SEP_SEMICOLON); | |
91 | #undef PRINT_FLAG | |
92 | #undef SEP_SEMICOLON | |
70d39fe4 CW |
93 | |
94 | return 0; | |
95 | } | |
2017263e | 96 | |
05394f39 | 97 | static const char *get_pin_flag(struct drm_i915_gem_object *obj) |
a6172a80 | 98 | { |
4feb7659 | 99 | if (i915_gem_obj_is_pinned(obj)) |
a6172a80 CW |
100 | return "p"; |
101 | else | |
102 | return " "; | |
103 | } | |
104 | ||
05394f39 | 105 | static const char *get_tiling_flag(struct drm_i915_gem_object *obj) |
a6172a80 | 106 | { |
0206e353 AJ |
107 | switch (obj->tiling_mode) { |
108 | default: | |
109 | case I915_TILING_NONE: return " "; | |
110 | case I915_TILING_X: return "X"; | |
111 | case I915_TILING_Y: return "Y"; | |
112 | } | |
a6172a80 CW |
113 | } |
114 | ||
1d693bcc BW |
115 | static inline const char *get_global_flag(struct drm_i915_gem_object *obj) |
116 | { | |
aff43766 | 117 | return i915_gem_obj_to_ggtt(obj) ? "g" : " "; |
1d693bcc BW |
118 | } |
119 | ||
37811fcc CW |
120 | static void |
121 | describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj) | |
122 | { | |
1d693bcc | 123 | struct i915_vma *vma; |
d7f46fc4 BW |
124 | int pin_count = 0; |
125 | ||
20e28fba | 126 | seq_printf(m, "%pK: %s%s%s %8zdKiB %02x %02x %x %x %x%s%s%s", |
37811fcc CW |
127 | &obj->base, |
128 | get_pin_flag(obj), | |
129 | get_tiling_flag(obj), | |
1d693bcc | 130 | get_global_flag(obj), |
a05a5862 | 131 | obj->base.size / 1024, |
37811fcc CW |
132 | obj->base.read_domains, |
133 | obj->base.write_domain, | |
97b2a6a1 JH |
134 | i915_gem_request_get_seqno(obj->last_read_req), |
135 | i915_gem_request_get_seqno(obj->last_write_req), | |
136 | i915_gem_request_get_seqno(obj->last_fenced_req), | |
0a4cd7c8 | 137 | i915_cache_level_str(to_i915(obj->base.dev), obj->cache_level), |
37811fcc CW |
138 | obj->dirty ? " dirty" : "", |
139 | obj->madv == I915_MADV_DONTNEED ? " purgeable" : ""); | |
140 | if (obj->base.name) | |
141 | seq_printf(m, " (name: %d)", obj->base.name); | |
ba0635ff | 142 | list_for_each_entry(vma, &obj->vma_list, vma_link) { |
d7f46fc4 BW |
143 | if (vma->pin_count > 0) |
144 | pin_count++; | |
ba0635ff DC |
145 | } |
146 | seq_printf(m, " (pinned x %d)", pin_count); | |
cc98b413 CW |
147 | if (obj->pin_display) |
148 | seq_printf(m, " (display)"); | |
37811fcc CW |
149 | if (obj->fence_reg != I915_FENCE_REG_NONE) |
150 | seq_printf(m, " (fence: %d)", obj->fence_reg); | |
1d693bcc BW |
151 | list_for_each_entry(vma, &obj->vma_list, vma_link) { |
152 | if (!i915_is_ggtt(vma->vm)) | |
153 | seq_puts(m, " (pp"); | |
154 | else | |
155 | seq_puts(m, " (g"); | |
440fd528 | 156 | seq_printf(m, "gtt offset: %08llx, size: %08llx, type: %u)", |
fe14d5f4 TU |
157 | vma->node.start, vma->node.size, |
158 | vma->ggtt_view.type); | |
1d693bcc | 159 | } |
c1ad11fc | 160 | if (obj->stolen) |
440fd528 | 161 | seq_printf(m, " (stolen: %08llx)", obj->stolen->start); |
6299f992 CW |
162 | if (obj->pin_mappable || obj->fault_mappable) { |
163 | char s[3], *t = s; | |
164 | if (obj->pin_mappable) | |
165 | *t++ = 'p'; | |
166 | if (obj->fault_mappable) | |
167 | *t++ = 'f'; | |
168 | *t = '\0'; | |
169 | seq_printf(m, " (%s mappable)", s); | |
170 | } | |
41c52415 JH |
171 | if (obj->last_read_req != NULL) |
172 | seq_printf(m, " (%s)", | |
173 | i915_gem_request_get_ring(obj->last_read_req)->name); | |
d5a81ef1 DV |
174 | if (obj->frontbuffer_bits) |
175 | seq_printf(m, " (frontbuffer: 0x%03x)", obj->frontbuffer_bits); | |
37811fcc CW |
176 | } |
177 | ||
273497e5 | 178 | static void describe_ctx(struct seq_file *m, struct intel_context *ctx) |
3ccfd19d | 179 | { |
ea0c76f8 | 180 | seq_putc(m, ctx->legacy_hw_ctx.initialized ? 'I' : 'i'); |
3ccfd19d BW |
181 | seq_putc(m, ctx->remap_slice ? 'R' : 'r'); |
182 | seq_putc(m, ' '); | |
183 | } | |
184 | ||
433e12f7 | 185 | static int i915_gem_object_list_info(struct seq_file *m, void *data) |
2017263e | 186 | { |
9f25d007 | 187 | struct drm_info_node *node = m->private; |
433e12f7 BG |
188 | uintptr_t list = (uintptr_t) node->info_ent->data; |
189 | struct list_head *head; | |
2017263e | 190 | struct drm_device *dev = node->minor->dev; |
5cef07e1 BW |
191 | struct drm_i915_private *dev_priv = dev->dev_private; |
192 | struct i915_address_space *vm = &dev_priv->gtt.base; | |
ca191b13 | 193 | struct i915_vma *vma; |
8f2480fb CW |
194 | size_t total_obj_size, total_gtt_size; |
195 | int count, ret; | |
de227ef0 CW |
196 | |
197 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
198 | if (ret) | |
199 | return ret; | |
2017263e | 200 | |
ca191b13 | 201 | /* FIXME: the user of this interface might want more than just GGTT */ |
433e12f7 BG |
202 | switch (list) { |
203 | case ACTIVE_LIST: | |
267f0c90 | 204 | seq_puts(m, "Active:\n"); |
5cef07e1 | 205 | head = &vm->active_list; |
433e12f7 BG |
206 | break; |
207 | case INACTIVE_LIST: | |
267f0c90 | 208 | seq_puts(m, "Inactive:\n"); |
5cef07e1 | 209 | head = &vm->inactive_list; |
433e12f7 | 210 | break; |
433e12f7 | 211 | default: |
de227ef0 CW |
212 | mutex_unlock(&dev->struct_mutex); |
213 | return -EINVAL; | |
2017263e | 214 | } |
2017263e | 215 | |
8f2480fb | 216 | total_obj_size = total_gtt_size = count = 0; |
ca191b13 BW |
217 | list_for_each_entry(vma, head, mm_list) { |
218 | seq_printf(m, " "); | |
219 | describe_obj(m, vma->obj); | |
220 | seq_printf(m, "\n"); | |
221 | total_obj_size += vma->obj->base.size; | |
222 | total_gtt_size += vma->node.size; | |
8f2480fb | 223 | count++; |
2017263e | 224 | } |
de227ef0 | 225 | mutex_unlock(&dev->struct_mutex); |
5e118f41 | 226 | |
8f2480fb CW |
227 | seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n", |
228 | count, total_obj_size, total_gtt_size); | |
2017263e BG |
229 | return 0; |
230 | } | |
231 | ||
6d2b8885 CW |
232 | static int obj_rank_by_stolen(void *priv, |
233 | struct list_head *A, struct list_head *B) | |
234 | { | |
235 | struct drm_i915_gem_object *a = | |
b25cb2f8 | 236 | container_of(A, struct drm_i915_gem_object, obj_exec_link); |
6d2b8885 | 237 | struct drm_i915_gem_object *b = |
b25cb2f8 | 238 | container_of(B, struct drm_i915_gem_object, obj_exec_link); |
6d2b8885 CW |
239 | |
240 | return a->stolen->start - b->stolen->start; | |
241 | } | |
242 | ||
243 | static int i915_gem_stolen_list_info(struct seq_file *m, void *data) | |
244 | { | |
9f25d007 | 245 | struct drm_info_node *node = m->private; |
6d2b8885 CW |
246 | struct drm_device *dev = node->minor->dev; |
247 | struct drm_i915_private *dev_priv = dev->dev_private; | |
248 | struct drm_i915_gem_object *obj; | |
249 | size_t total_obj_size, total_gtt_size; | |
250 | LIST_HEAD(stolen); | |
251 | int count, ret; | |
252 | ||
253 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
254 | if (ret) | |
255 | return ret; | |
256 | ||
257 | total_obj_size = total_gtt_size = count = 0; | |
258 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) { | |
259 | if (obj->stolen == NULL) | |
260 | continue; | |
261 | ||
b25cb2f8 | 262 | list_add(&obj->obj_exec_link, &stolen); |
6d2b8885 CW |
263 | |
264 | total_obj_size += obj->base.size; | |
265 | total_gtt_size += i915_gem_obj_ggtt_size(obj); | |
266 | count++; | |
267 | } | |
268 | list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) { | |
269 | if (obj->stolen == NULL) | |
270 | continue; | |
271 | ||
b25cb2f8 | 272 | list_add(&obj->obj_exec_link, &stolen); |
6d2b8885 CW |
273 | |
274 | total_obj_size += obj->base.size; | |
275 | count++; | |
276 | } | |
277 | list_sort(NULL, &stolen, obj_rank_by_stolen); | |
278 | seq_puts(m, "Stolen:\n"); | |
279 | while (!list_empty(&stolen)) { | |
b25cb2f8 | 280 | obj = list_first_entry(&stolen, typeof(*obj), obj_exec_link); |
6d2b8885 CW |
281 | seq_puts(m, " "); |
282 | describe_obj(m, obj); | |
283 | seq_putc(m, '\n'); | |
b25cb2f8 | 284 | list_del_init(&obj->obj_exec_link); |
6d2b8885 CW |
285 | } |
286 | mutex_unlock(&dev->struct_mutex); | |
287 | ||
288 | seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n", | |
289 | count, total_obj_size, total_gtt_size); | |
290 | return 0; | |
291 | } | |
292 | ||
6299f992 CW |
293 | #define count_objects(list, member) do { \ |
294 | list_for_each_entry(obj, list, member) { \ | |
f343c5f6 | 295 | size += i915_gem_obj_ggtt_size(obj); \ |
6299f992 CW |
296 | ++count; \ |
297 | if (obj->map_and_fenceable) { \ | |
f343c5f6 | 298 | mappable_size += i915_gem_obj_ggtt_size(obj); \ |
6299f992 CW |
299 | ++mappable_count; \ |
300 | } \ | |
301 | } \ | |
0206e353 | 302 | } while (0) |
6299f992 | 303 | |
2db8e9d6 | 304 | struct file_stats { |
6313c204 | 305 | struct drm_i915_file_private *file_priv; |
2db8e9d6 | 306 | int count; |
c67a17e9 CW |
307 | size_t total, unbound; |
308 | size_t global, shared; | |
309 | size_t active, inactive; | |
2db8e9d6 CW |
310 | }; |
311 | ||
312 | static int per_file_stats(int id, void *ptr, void *data) | |
313 | { | |
314 | struct drm_i915_gem_object *obj = ptr; | |
315 | struct file_stats *stats = data; | |
6313c204 | 316 | struct i915_vma *vma; |
2db8e9d6 CW |
317 | |
318 | stats->count++; | |
319 | stats->total += obj->base.size; | |
320 | ||
c67a17e9 CW |
321 | if (obj->base.name || obj->base.dma_buf) |
322 | stats->shared += obj->base.size; | |
323 | ||
6313c204 CW |
324 | if (USES_FULL_PPGTT(obj->base.dev)) { |
325 | list_for_each_entry(vma, &obj->vma_list, vma_link) { | |
326 | struct i915_hw_ppgtt *ppgtt; | |
327 | ||
328 | if (!drm_mm_node_allocated(&vma->node)) | |
329 | continue; | |
330 | ||
331 | if (i915_is_ggtt(vma->vm)) { | |
332 | stats->global += obj->base.size; | |
333 | continue; | |
334 | } | |
335 | ||
336 | ppgtt = container_of(vma->vm, struct i915_hw_ppgtt, base); | |
4d884705 | 337 | if (ppgtt->file_priv != stats->file_priv) |
6313c204 CW |
338 | continue; |
339 | ||
41c52415 | 340 | if (obj->active) /* XXX per-vma statistic */ |
6313c204 CW |
341 | stats->active += obj->base.size; |
342 | else | |
343 | stats->inactive += obj->base.size; | |
344 | ||
345 | return 0; | |
346 | } | |
2db8e9d6 | 347 | } else { |
6313c204 CW |
348 | if (i915_gem_obj_ggtt_bound(obj)) { |
349 | stats->global += obj->base.size; | |
41c52415 | 350 | if (obj->active) |
6313c204 CW |
351 | stats->active += obj->base.size; |
352 | else | |
353 | stats->inactive += obj->base.size; | |
354 | return 0; | |
355 | } | |
2db8e9d6 CW |
356 | } |
357 | ||
6313c204 CW |
358 | if (!list_empty(&obj->global_list)) |
359 | stats->unbound += obj->base.size; | |
360 | ||
2db8e9d6 CW |
361 | return 0; |
362 | } | |
363 | ||
493018dc BV |
364 | #define print_file_stats(m, name, stats) \ |
365 | seq_printf(m, "%s: %u objects, %zu bytes (%zu active, %zu inactive, %zu global, %zu shared, %zu unbound)\n", \ | |
366 | name, \ | |
367 | stats.count, \ | |
368 | stats.total, \ | |
369 | stats.active, \ | |
370 | stats.inactive, \ | |
371 | stats.global, \ | |
372 | stats.shared, \ | |
373 | stats.unbound) | |
374 | ||
375 | static void print_batch_pool_stats(struct seq_file *m, | |
376 | struct drm_i915_private *dev_priv) | |
377 | { | |
378 | struct drm_i915_gem_object *obj; | |
379 | struct file_stats stats; | |
380 | ||
381 | memset(&stats, 0, sizeof(stats)); | |
382 | ||
383 | list_for_each_entry(obj, | |
384 | &dev_priv->mm.batch_pool.cache_list, | |
385 | batch_pool_list) | |
386 | per_file_stats(0, obj, &stats); | |
387 | ||
388 | print_file_stats(m, "batch pool", stats); | |
389 | } | |
390 | ||
ca191b13 BW |
391 | #define count_vmas(list, member) do { \ |
392 | list_for_each_entry(vma, list, member) { \ | |
393 | size += i915_gem_obj_ggtt_size(vma->obj); \ | |
394 | ++count; \ | |
395 | if (vma->obj->map_and_fenceable) { \ | |
396 | mappable_size += i915_gem_obj_ggtt_size(vma->obj); \ | |
397 | ++mappable_count; \ | |
398 | } \ | |
399 | } \ | |
400 | } while (0) | |
401 | ||
402 | static int i915_gem_object_info(struct seq_file *m, void* data) | |
73aa808f | 403 | { |
9f25d007 | 404 | struct drm_info_node *node = m->private; |
73aa808f CW |
405 | struct drm_device *dev = node->minor->dev; |
406 | struct drm_i915_private *dev_priv = dev->dev_private; | |
b7abb714 CW |
407 | u32 count, mappable_count, purgeable_count; |
408 | size_t size, mappable_size, purgeable_size; | |
6299f992 | 409 | struct drm_i915_gem_object *obj; |
5cef07e1 | 410 | struct i915_address_space *vm = &dev_priv->gtt.base; |
2db8e9d6 | 411 | struct drm_file *file; |
ca191b13 | 412 | struct i915_vma *vma; |
73aa808f CW |
413 | int ret; |
414 | ||
415 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
416 | if (ret) | |
417 | return ret; | |
418 | ||
6299f992 CW |
419 | seq_printf(m, "%u objects, %zu bytes\n", |
420 | dev_priv->mm.object_count, | |
421 | dev_priv->mm.object_memory); | |
422 | ||
423 | size = count = mappable_size = mappable_count = 0; | |
35c20a60 | 424 | count_objects(&dev_priv->mm.bound_list, global_list); |
6299f992 CW |
425 | seq_printf(m, "%u [%u] objects, %zu [%zu] bytes in gtt\n", |
426 | count, mappable_count, size, mappable_size); | |
427 | ||
428 | size = count = mappable_size = mappable_count = 0; | |
ca191b13 | 429 | count_vmas(&vm->active_list, mm_list); |
6299f992 CW |
430 | seq_printf(m, " %u [%u] active objects, %zu [%zu] bytes\n", |
431 | count, mappable_count, size, mappable_size); | |
432 | ||
6299f992 | 433 | size = count = mappable_size = mappable_count = 0; |
ca191b13 | 434 | count_vmas(&vm->inactive_list, mm_list); |
6299f992 CW |
435 | seq_printf(m, " %u [%u] inactive objects, %zu [%zu] bytes\n", |
436 | count, mappable_count, size, mappable_size); | |
437 | ||
b7abb714 | 438 | size = count = purgeable_size = purgeable_count = 0; |
35c20a60 | 439 | list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) { |
6c085a72 | 440 | size += obj->base.size, ++count; |
b7abb714 CW |
441 | if (obj->madv == I915_MADV_DONTNEED) |
442 | purgeable_size += obj->base.size, ++purgeable_count; | |
443 | } | |
6c085a72 CW |
444 | seq_printf(m, "%u unbound objects, %zu bytes\n", count, size); |
445 | ||
6299f992 | 446 | size = count = mappable_size = mappable_count = 0; |
35c20a60 | 447 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) { |
6299f992 | 448 | if (obj->fault_mappable) { |
f343c5f6 | 449 | size += i915_gem_obj_ggtt_size(obj); |
6299f992 CW |
450 | ++count; |
451 | } | |
452 | if (obj->pin_mappable) { | |
f343c5f6 | 453 | mappable_size += i915_gem_obj_ggtt_size(obj); |
6299f992 CW |
454 | ++mappable_count; |
455 | } | |
b7abb714 CW |
456 | if (obj->madv == I915_MADV_DONTNEED) { |
457 | purgeable_size += obj->base.size; | |
458 | ++purgeable_count; | |
459 | } | |
6299f992 | 460 | } |
b7abb714 CW |
461 | seq_printf(m, "%u purgeable objects, %zu bytes\n", |
462 | purgeable_count, purgeable_size); | |
6299f992 CW |
463 | seq_printf(m, "%u pinned mappable objects, %zu bytes\n", |
464 | mappable_count, mappable_size); | |
465 | seq_printf(m, "%u fault mappable objects, %zu bytes\n", | |
466 | count, size); | |
467 | ||
93d18799 | 468 | seq_printf(m, "%zu [%lu] gtt total\n", |
853ba5d2 BW |
469 | dev_priv->gtt.base.total, |
470 | dev_priv->gtt.mappable_end - dev_priv->gtt.base.start); | |
73aa808f | 471 | |
493018dc BV |
472 | seq_putc(m, '\n'); |
473 | print_batch_pool_stats(m, dev_priv); | |
474 | ||
267f0c90 | 475 | seq_putc(m, '\n'); |
2db8e9d6 CW |
476 | list_for_each_entry_reverse(file, &dev->filelist, lhead) { |
477 | struct file_stats stats; | |
3ec2f427 | 478 | struct task_struct *task; |
2db8e9d6 CW |
479 | |
480 | memset(&stats, 0, sizeof(stats)); | |
6313c204 | 481 | stats.file_priv = file->driver_priv; |
5b5ffff0 | 482 | spin_lock(&file->table_lock); |
2db8e9d6 | 483 | idr_for_each(&file->object_idr, per_file_stats, &stats); |
5b5ffff0 | 484 | spin_unlock(&file->table_lock); |
3ec2f427 TH |
485 | /* |
486 | * Although we have a valid reference on file->pid, that does | |
487 | * not guarantee that the task_struct who called get_pid() is | |
488 | * still alive (e.g. get_pid(current) => fork() => exit()). | |
489 | * Therefore, we need to protect this ->comm access using RCU. | |
490 | */ | |
491 | rcu_read_lock(); | |
492 | task = pid_task(file->pid, PIDTYPE_PID); | |
493018dc | 493 | print_file_stats(m, task ? task->comm : "<unknown>", stats); |
3ec2f427 | 494 | rcu_read_unlock(); |
2db8e9d6 CW |
495 | } |
496 | ||
73aa808f CW |
497 | mutex_unlock(&dev->struct_mutex); |
498 | ||
499 | return 0; | |
500 | } | |
501 | ||
aee56cff | 502 | static int i915_gem_gtt_info(struct seq_file *m, void *data) |
08c18323 | 503 | { |
9f25d007 | 504 | struct drm_info_node *node = m->private; |
08c18323 | 505 | struct drm_device *dev = node->minor->dev; |
1b50247a | 506 | uintptr_t list = (uintptr_t) node->info_ent->data; |
08c18323 CW |
507 | struct drm_i915_private *dev_priv = dev->dev_private; |
508 | struct drm_i915_gem_object *obj; | |
509 | size_t total_obj_size, total_gtt_size; | |
510 | int count, ret; | |
511 | ||
512 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
513 | if (ret) | |
514 | return ret; | |
515 | ||
516 | total_obj_size = total_gtt_size = count = 0; | |
35c20a60 | 517 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) { |
d7f46fc4 | 518 | if (list == PINNED_LIST && !i915_gem_obj_is_pinned(obj)) |
1b50247a CW |
519 | continue; |
520 | ||
267f0c90 | 521 | seq_puts(m, " "); |
08c18323 | 522 | describe_obj(m, obj); |
267f0c90 | 523 | seq_putc(m, '\n'); |
08c18323 | 524 | total_obj_size += obj->base.size; |
f343c5f6 | 525 | total_gtt_size += i915_gem_obj_ggtt_size(obj); |
08c18323 CW |
526 | count++; |
527 | } | |
528 | ||
529 | mutex_unlock(&dev->struct_mutex); | |
530 | ||
531 | seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n", | |
532 | count, total_obj_size, total_gtt_size); | |
533 | ||
534 | return 0; | |
535 | } | |
536 | ||
4e5359cd SF |
537 | static int i915_gem_pageflip_info(struct seq_file *m, void *data) |
538 | { | |
9f25d007 | 539 | struct drm_info_node *node = m->private; |
4e5359cd | 540 | struct drm_device *dev = node->minor->dev; |
d6bbafa1 | 541 | struct drm_i915_private *dev_priv = dev->dev_private; |
4e5359cd | 542 | struct intel_crtc *crtc; |
8a270ebf DV |
543 | int ret; |
544 | ||
545 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
546 | if (ret) | |
547 | return ret; | |
4e5359cd | 548 | |
d3fcc808 | 549 | for_each_intel_crtc(dev, crtc) { |
9db4a9c7 JB |
550 | const char pipe = pipe_name(crtc->pipe); |
551 | const char plane = plane_name(crtc->plane); | |
4e5359cd SF |
552 | struct intel_unpin_work *work; |
553 | ||
5e2d7afc | 554 | spin_lock_irq(&dev->event_lock); |
4e5359cd SF |
555 | work = crtc->unpin_work; |
556 | if (work == NULL) { | |
9db4a9c7 | 557 | seq_printf(m, "No flip due on pipe %c (plane %c)\n", |
4e5359cd SF |
558 | pipe, plane); |
559 | } else { | |
d6bbafa1 CW |
560 | u32 addr; |
561 | ||
e7d841ca | 562 | if (atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) { |
9db4a9c7 | 563 | seq_printf(m, "Flip queued on pipe %c (plane %c)\n", |
4e5359cd SF |
564 | pipe, plane); |
565 | } else { | |
9db4a9c7 | 566 | seq_printf(m, "Flip pending (waiting for vsync) on pipe %c (plane %c)\n", |
4e5359cd SF |
567 | pipe, plane); |
568 | } | |
3a8a946e DV |
569 | if (work->flip_queued_req) { |
570 | struct intel_engine_cs *ring = | |
571 | i915_gem_request_get_ring(work->flip_queued_req); | |
572 | ||
20e28fba | 573 | seq_printf(m, "Flip queued on %s at seqno %x, next seqno %x [current breadcrumb %x], completed? %d\n", |
3a8a946e | 574 | ring->name, |
f06cc1b9 | 575 | i915_gem_request_get_seqno(work->flip_queued_req), |
d6bbafa1 | 576 | dev_priv->next_seqno, |
3a8a946e | 577 | ring->get_seqno(ring, true), |
1b5a433a | 578 | i915_gem_request_completed(work->flip_queued_req, true)); |
d6bbafa1 CW |
579 | } else |
580 | seq_printf(m, "Flip not associated with any ring\n"); | |
581 | seq_printf(m, "Flip queued on frame %d, (was ready on frame %d), now %d\n", | |
582 | work->flip_queued_vblank, | |
583 | work->flip_ready_vblank, | |
1e3feefd | 584 | drm_crtc_vblank_count(&crtc->base)); |
4e5359cd | 585 | if (work->enable_stall_check) |
267f0c90 | 586 | seq_puts(m, "Stall check enabled, "); |
4e5359cd | 587 | else |
267f0c90 | 588 | seq_puts(m, "Stall check waiting for page flip ioctl, "); |
e7d841ca | 589 | seq_printf(m, "%d prepares\n", atomic_read(&work->pending)); |
4e5359cd | 590 | |
d6bbafa1 CW |
591 | if (INTEL_INFO(dev)->gen >= 4) |
592 | addr = I915_HI_DISPBASE(I915_READ(DSPSURF(crtc->plane))); | |
593 | else | |
594 | addr = I915_READ(DSPADDR(crtc->plane)); | |
595 | seq_printf(m, "Current scanout address 0x%08x\n", addr); | |
596 | ||
4e5359cd | 597 | if (work->pending_flip_obj) { |
d6bbafa1 CW |
598 | seq_printf(m, "New framebuffer address 0x%08lx\n", (long)work->gtt_offset); |
599 | seq_printf(m, "MMIO update completed? %d\n", addr == work->gtt_offset); | |
4e5359cd SF |
600 | } |
601 | } | |
5e2d7afc | 602 | spin_unlock_irq(&dev->event_lock); |
4e5359cd SF |
603 | } |
604 | ||
8a270ebf DV |
605 | mutex_unlock(&dev->struct_mutex); |
606 | ||
4e5359cd SF |
607 | return 0; |
608 | } | |
609 | ||
493018dc BV |
610 | static int i915_gem_batch_pool_info(struct seq_file *m, void *data) |
611 | { | |
612 | struct drm_info_node *node = m->private; | |
613 | struct drm_device *dev = node->minor->dev; | |
614 | struct drm_i915_private *dev_priv = dev->dev_private; | |
615 | struct drm_i915_gem_object *obj; | |
616 | int count = 0; | |
617 | int ret; | |
618 | ||
619 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
620 | if (ret) | |
621 | return ret; | |
622 | ||
623 | seq_puts(m, "cache:\n"); | |
624 | list_for_each_entry(obj, | |
625 | &dev_priv->mm.batch_pool.cache_list, | |
626 | batch_pool_list) { | |
627 | seq_puts(m, " "); | |
628 | describe_obj(m, obj); | |
629 | seq_putc(m, '\n'); | |
630 | count++; | |
631 | } | |
632 | ||
633 | seq_printf(m, "total: %d\n", count); | |
634 | ||
635 | mutex_unlock(&dev->struct_mutex); | |
636 | ||
637 | return 0; | |
638 | } | |
639 | ||
2017263e BG |
640 | static int i915_gem_request_info(struct seq_file *m, void *data) |
641 | { | |
9f25d007 | 642 | struct drm_info_node *node = m->private; |
2017263e | 643 | struct drm_device *dev = node->minor->dev; |
e277a1f8 | 644 | struct drm_i915_private *dev_priv = dev->dev_private; |
a4872ba6 | 645 | struct intel_engine_cs *ring; |
2017263e | 646 | struct drm_i915_gem_request *gem_request; |
a2c7f6fd | 647 | int ret, count, i; |
de227ef0 CW |
648 | |
649 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
650 | if (ret) | |
651 | return ret; | |
2017263e | 652 | |
c2c347a9 | 653 | count = 0; |
a2c7f6fd CW |
654 | for_each_ring(ring, dev_priv, i) { |
655 | if (list_empty(&ring->request_list)) | |
656 | continue; | |
657 | ||
658 | seq_printf(m, "%s requests:\n", ring->name); | |
c2c347a9 | 659 | list_for_each_entry(gem_request, |
a2c7f6fd | 660 | &ring->request_list, |
c2c347a9 | 661 | list) { |
20e28fba | 662 | seq_printf(m, " %x @ %d\n", |
c2c347a9 CW |
663 | gem_request->seqno, |
664 | (int) (jiffies - gem_request->emitted_jiffies)); | |
665 | } | |
666 | count++; | |
2017263e | 667 | } |
de227ef0 CW |
668 | mutex_unlock(&dev->struct_mutex); |
669 | ||
c2c347a9 | 670 | if (count == 0) |
267f0c90 | 671 | seq_puts(m, "No requests\n"); |
c2c347a9 | 672 | |
2017263e BG |
673 | return 0; |
674 | } | |
675 | ||
b2223497 | 676 | static void i915_ring_seqno_info(struct seq_file *m, |
a4872ba6 | 677 | struct intel_engine_cs *ring) |
b2223497 CW |
678 | { |
679 | if (ring->get_seqno) { | |
20e28fba | 680 | seq_printf(m, "Current sequence (%s): %x\n", |
b2eadbc8 | 681 | ring->name, ring->get_seqno(ring, false)); |
b2223497 CW |
682 | } |
683 | } | |
684 | ||
2017263e BG |
685 | static int i915_gem_seqno_info(struct seq_file *m, void *data) |
686 | { | |
9f25d007 | 687 | struct drm_info_node *node = m->private; |
2017263e | 688 | struct drm_device *dev = node->minor->dev; |
e277a1f8 | 689 | struct drm_i915_private *dev_priv = dev->dev_private; |
a4872ba6 | 690 | struct intel_engine_cs *ring; |
1ec14ad3 | 691 | int ret, i; |
de227ef0 CW |
692 | |
693 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
694 | if (ret) | |
695 | return ret; | |
c8c8fb33 | 696 | intel_runtime_pm_get(dev_priv); |
2017263e | 697 | |
a2c7f6fd CW |
698 | for_each_ring(ring, dev_priv, i) |
699 | i915_ring_seqno_info(m, ring); | |
de227ef0 | 700 | |
c8c8fb33 | 701 | intel_runtime_pm_put(dev_priv); |
de227ef0 CW |
702 | mutex_unlock(&dev->struct_mutex); |
703 | ||
2017263e BG |
704 | return 0; |
705 | } | |
706 | ||
707 | ||
708 | static int i915_interrupt_info(struct seq_file *m, void *data) | |
709 | { | |
9f25d007 | 710 | struct drm_info_node *node = m->private; |
2017263e | 711 | struct drm_device *dev = node->minor->dev; |
e277a1f8 | 712 | struct drm_i915_private *dev_priv = dev->dev_private; |
a4872ba6 | 713 | struct intel_engine_cs *ring; |
9db4a9c7 | 714 | int ret, i, pipe; |
de227ef0 CW |
715 | |
716 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
717 | if (ret) | |
718 | return ret; | |
c8c8fb33 | 719 | intel_runtime_pm_get(dev_priv); |
2017263e | 720 | |
74e1ca8c | 721 | if (IS_CHERRYVIEW(dev)) { |
74e1ca8c VS |
722 | seq_printf(m, "Master Interrupt Control:\t%08x\n", |
723 | I915_READ(GEN8_MASTER_IRQ)); | |
724 | ||
725 | seq_printf(m, "Display IER:\t%08x\n", | |
726 | I915_READ(VLV_IER)); | |
727 | seq_printf(m, "Display IIR:\t%08x\n", | |
728 | I915_READ(VLV_IIR)); | |
729 | seq_printf(m, "Display IIR_RW:\t%08x\n", | |
730 | I915_READ(VLV_IIR_RW)); | |
731 | seq_printf(m, "Display IMR:\t%08x\n", | |
732 | I915_READ(VLV_IMR)); | |
055e393f | 733 | for_each_pipe(dev_priv, pipe) |
74e1ca8c VS |
734 | seq_printf(m, "Pipe %c stat:\t%08x\n", |
735 | pipe_name(pipe), | |
736 | I915_READ(PIPESTAT(pipe))); | |
737 | ||
738 | seq_printf(m, "Port hotplug:\t%08x\n", | |
739 | I915_READ(PORT_HOTPLUG_EN)); | |
740 | seq_printf(m, "DPFLIPSTAT:\t%08x\n", | |
741 | I915_READ(VLV_DPFLIPSTAT)); | |
742 | seq_printf(m, "DPINVGTT:\t%08x\n", | |
743 | I915_READ(DPINVGTT)); | |
744 | ||
745 | for (i = 0; i < 4; i++) { | |
746 | seq_printf(m, "GT Interrupt IMR %d:\t%08x\n", | |
747 | i, I915_READ(GEN8_GT_IMR(i))); | |
748 | seq_printf(m, "GT Interrupt IIR %d:\t%08x\n", | |
749 | i, I915_READ(GEN8_GT_IIR(i))); | |
750 | seq_printf(m, "GT Interrupt IER %d:\t%08x\n", | |
751 | i, I915_READ(GEN8_GT_IER(i))); | |
752 | } | |
753 | ||
754 | seq_printf(m, "PCU interrupt mask:\t%08x\n", | |
755 | I915_READ(GEN8_PCU_IMR)); | |
756 | seq_printf(m, "PCU interrupt identity:\t%08x\n", | |
757 | I915_READ(GEN8_PCU_IIR)); | |
758 | seq_printf(m, "PCU interrupt enable:\t%08x\n", | |
759 | I915_READ(GEN8_PCU_IER)); | |
760 | } else if (INTEL_INFO(dev)->gen >= 8) { | |
a123f157 BW |
761 | seq_printf(m, "Master Interrupt Control:\t%08x\n", |
762 | I915_READ(GEN8_MASTER_IRQ)); | |
763 | ||
764 | for (i = 0; i < 4; i++) { | |
765 | seq_printf(m, "GT Interrupt IMR %d:\t%08x\n", | |
766 | i, I915_READ(GEN8_GT_IMR(i))); | |
767 | seq_printf(m, "GT Interrupt IIR %d:\t%08x\n", | |
768 | i, I915_READ(GEN8_GT_IIR(i))); | |
769 | seq_printf(m, "GT Interrupt IER %d:\t%08x\n", | |
770 | i, I915_READ(GEN8_GT_IER(i))); | |
771 | } | |
772 | ||
055e393f | 773 | for_each_pipe(dev_priv, pipe) { |
f458ebbc | 774 | if (!intel_display_power_is_enabled(dev_priv, |
22c59960 PZ |
775 | POWER_DOMAIN_PIPE(pipe))) { |
776 | seq_printf(m, "Pipe %c power disabled\n", | |
777 | pipe_name(pipe)); | |
778 | continue; | |
779 | } | |
a123f157 | 780 | seq_printf(m, "Pipe %c IMR:\t%08x\n", |
07d27e20 DL |
781 | pipe_name(pipe), |
782 | I915_READ(GEN8_DE_PIPE_IMR(pipe))); | |
a123f157 | 783 | seq_printf(m, "Pipe %c IIR:\t%08x\n", |
07d27e20 DL |
784 | pipe_name(pipe), |
785 | I915_READ(GEN8_DE_PIPE_IIR(pipe))); | |
a123f157 | 786 | seq_printf(m, "Pipe %c IER:\t%08x\n", |
07d27e20 DL |
787 | pipe_name(pipe), |
788 | I915_READ(GEN8_DE_PIPE_IER(pipe))); | |
a123f157 BW |
789 | } |
790 | ||
791 | seq_printf(m, "Display Engine port interrupt mask:\t%08x\n", | |
792 | I915_READ(GEN8_DE_PORT_IMR)); | |
793 | seq_printf(m, "Display Engine port interrupt identity:\t%08x\n", | |
794 | I915_READ(GEN8_DE_PORT_IIR)); | |
795 | seq_printf(m, "Display Engine port interrupt enable:\t%08x\n", | |
796 | I915_READ(GEN8_DE_PORT_IER)); | |
797 | ||
798 | seq_printf(m, "Display Engine misc interrupt mask:\t%08x\n", | |
799 | I915_READ(GEN8_DE_MISC_IMR)); | |
800 | seq_printf(m, "Display Engine misc interrupt identity:\t%08x\n", | |
801 | I915_READ(GEN8_DE_MISC_IIR)); | |
802 | seq_printf(m, "Display Engine misc interrupt enable:\t%08x\n", | |
803 | I915_READ(GEN8_DE_MISC_IER)); | |
804 | ||
805 | seq_printf(m, "PCU interrupt mask:\t%08x\n", | |
806 | I915_READ(GEN8_PCU_IMR)); | |
807 | seq_printf(m, "PCU interrupt identity:\t%08x\n", | |
808 | I915_READ(GEN8_PCU_IIR)); | |
809 | seq_printf(m, "PCU interrupt enable:\t%08x\n", | |
810 | I915_READ(GEN8_PCU_IER)); | |
811 | } else if (IS_VALLEYVIEW(dev)) { | |
7e231dbe JB |
812 | seq_printf(m, "Display IER:\t%08x\n", |
813 | I915_READ(VLV_IER)); | |
814 | seq_printf(m, "Display IIR:\t%08x\n", | |
815 | I915_READ(VLV_IIR)); | |
816 | seq_printf(m, "Display IIR_RW:\t%08x\n", | |
817 | I915_READ(VLV_IIR_RW)); | |
818 | seq_printf(m, "Display IMR:\t%08x\n", | |
819 | I915_READ(VLV_IMR)); | |
055e393f | 820 | for_each_pipe(dev_priv, pipe) |
7e231dbe JB |
821 | seq_printf(m, "Pipe %c stat:\t%08x\n", |
822 | pipe_name(pipe), | |
823 | I915_READ(PIPESTAT(pipe))); | |
824 | ||
825 | seq_printf(m, "Master IER:\t%08x\n", | |
826 | I915_READ(VLV_MASTER_IER)); | |
827 | ||
828 | seq_printf(m, "Render IER:\t%08x\n", | |
829 | I915_READ(GTIER)); | |
830 | seq_printf(m, "Render IIR:\t%08x\n", | |
831 | I915_READ(GTIIR)); | |
832 | seq_printf(m, "Render IMR:\t%08x\n", | |
833 | I915_READ(GTIMR)); | |
834 | ||
835 | seq_printf(m, "PM IER:\t\t%08x\n", | |
836 | I915_READ(GEN6_PMIER)); | |
837 | seq_printf(m, "PM IIR:\t\t%08x\n", | |
838 | I915_READ(GEN6_PMIIR)); | |
839 | seq_printf(m, "PM IMR:\t\t%08x\n", | |
840 | I915_READ(GEN6_PMIMR)); | |
841 | ||
842 | seq_printf(m, "Port hotplug:\t%08x\n", | |
843 | I915_READ(PORT_HOTPLUG_EN)); | |
844 | seq_printf(m, "DPFLIPSTAT:\t%08x\n", | |
845 | I915_READ(VLV_DPFLIPSTAT)); | |
846 | seq_printf(m, "DPINVGTT:\t%08x\n", | |
847 | I915_READ(DPINVGTT)); | |
848 | ||
849 | } else if (!HAS_PCH_SPLIT(dev)) { | |
5f6a1695 ZW |
850 | seq_printf(m, "Interrupt enable: %08x\n", |
851 | I915_READ(IER)); | |
852 | seq_printf(m, "Interrupt identity: %08x\n", | |
853 | I915_READ(IIR)); | |
854 | seq_printf(m, "Interrupt mask: %08x\n", | |
855 | I915_READ(IMR)); | |
055e393f | 856 | for_each_pipe(dev_priv, pipe) |
9db4a9c7 JB |
857 | seq_printf(m, "Pipe %c stat: %08x\n", |
858 | pipe_name(pipe), | |
859 | I915_READ(PIPESTAT(pipe))); | |
5f6a1695 ZW |
860 | } else { |
861 | seq_printf(m, "North Display Interrupt enable: %08x\n", | |
862 | I915_READ(DEIER)); | |
863 | seq_printf(m, "North Display Interrupt identity: %08x\n", | |
864 | I915_READ(DEIIR)); | |
865 | seq_printf(m, "North Display Interrupt mask: %08x\n", | |
866 | I915_READ(DEIMR)); | |
867 | seq_printf(m, "South Display Interrupt enable: %08x\n", | |
868 | I915_READ(SDEIER)); | |
869 | seq_printf(m, "South Display Interrupt identity: %08x\n", | |
870 | I915_READ(SDEIIR)); | |
871 | seq_printf(m, "South Display Interrupt mask: %08x\n", | |
872 | I915_READ(SDEIMR)); | |
873 | seq_printf(m, "Graphics Interrupt enable: %08x\n", | |
874 | I915_READ(GTIER)); | |
875 | seq_printf(m, "Graphics Interrupt identity: %08x\n", | |
876 | I915_READ(GTIIR)); | |
877 | seq_printf(m, "Graphics Interrupt mask: %08x\n", | |
878 | I915_READ(GTIMR)); | |
879 | } | |
a2c7f6fd | 880 | for_each_ring(ring, dev_priv, i) { |
a123f157 | 881 | if (INTEL_INFO(dev)->gen >= 6) { |
a2c7f6fd CW |
882 | seq_printf(m, |
883 | "Graphics Interrupt mask (%s): %08x\n", | |
884 | ring->name, I915_READ_IMR(ring)); | |
9862e600 | 885 | } |
a2c7f6fd | 886 | i915_ring_seqno_info(m, ring); |
9862e600 | 887 | } |
c8c8fb33 | 888 | intel_runtime_pm_put(dev_priv); |
de227ef0 CW |
889 | mutex_unlock(&dev->struct_mutex); |
890 | ||
2017263e BG |
891 | return 0; |
892 | } | |
893 | ||
a6172a80 CW |
894 | static int i915_gem_fence_regs_info(struct seq_file *m, void *data) |
895 | { | |
9f25d007 | 896 | struct drm_info_node *node = m->private; |
a6172a80 | 897 | struct drm_device *dev = node->minor->dev; |
e277a1f8 | 898 | struct drm_i915_private *dev_priv = dev->dev_private; |
de227ef0 CW |
899 | int i, ret; |
900 | ||
901 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
902 | if (ret) | |
903 | return ret; | |
a6172a80 CW |
904 | |
905 | seq_printf(m, "Reserved fences = %d\n", dev_priv->fence_reg_start); | |
906 | seq_printf(m, "Total fences = %d\n", dev_priv->num_fence_regs); | |
907 | for (i = 0; i < dev_priv->num_fence_regs; i++) { | |
05394f39 | 908 | struct drm_i915_gem_object *obj = dev_priv->fence_regs[i].obj; |
a6172a80 | 909 | |
6c085a72 CW |
910 | seq_printf(m, "Fence %d, pin count = %d, object = ", |
911 | i, dev_priv->fence_regs[i].pin_count); | |
c2c347a9 | 912 | if (obj == NULL) |
267f0c90 | 913 | seq_puts(m, "unused"); |
c2c347a9 | 914 | else |
05394f39 | 915 | describe_obj(m, obj); |
267f0c90 | 916 | seq_putc(m, '\n'); |
a6172a80 CW |
917 | } |
918 | ||
05394f39 | 919 | mutex_unlock(&dev->struct_mutex); |
a6172a80 CW |
920 | return 0; |
921 | } | |
922 | ||
2017263e BG |
923 | static int i915_hws_info(struct seq_file *m, void *data) |
924 | { | |
9f25d007 | 925 | struct drm_info_node *node = m->private; |
2017263e | 926 | struct drm_device *dev = node->minor->dev; |
e277a1f8 | 927 | struct drm_i915_private *dev_priv = dev->dev_private; |
a4872ba6 | 928 | struct intel_engine_cs *ring; |
1a240d4d | 929 | const u32 *hws; |
4066c0ae CW |
930 | int i; |
931 | ||
1ec14ad3 | 932 | ring = &dev_priv->ring[(uintptr_t)node->info_ent->data]; |
1a240d4d | 933 | hws = ring->status_page.page_addr; |
2017263e BG |
934 | if (hws == NULL) |
935 | return 0; | |
936 | ||
937 | for (i = 0; i < 4096 / sizeof(u32) / 4; i += 4) { | |
938 | seq_printf(m, "0x%08x: 0x%08x 0x%08x 0x%08x 0x%08x\n", | |
939 | i * 4, | |
940 | hws[i], hws[i + 1], hws[i + 2], hws[i + 3]); | |
941 | } | |
942 | return 0; | |
943 | } | |
944 | ||
d5442303 DV |
945 | static ssize_t |
946 | i915_error_state_write(struct file *filp, | |
947 | const char __user *ubuf, | |
948 | size_t cnt, | |
949 | loff_t *ppos) | |
950 | { | |
edc3d884 | 951 | struct i915_error_state_file_priv *error_priv = filp->private_data; |
d5442303 | 952 | struct drm_device *dev = error_priv->dev; |
22bcfc6a | 953 | int ret; |
d5442303 DV |
954 | |
955 | DRM_DEBUG_DRIVER("Resetting error state\n"); | |
956 | ||
22bcfc6a DV |
957 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
958 | if (ret) | |
959 | return ret; | |
960 | ||
d5442303 DV |
961 | i915_destroy_error_state(dev); |
962 | mutex_unlock(&dev->struct_mutex); | |
963 | ||
964 | return cnt; | |
965 | } | |
966 | ||
967 | static int i915_error_state_open(struct inode *inode, struct file *file) | |
968 | { | |
969 | struct drm_device *dev = inode->i_private; | |
d5442303 | 970 | struct i915_error_state_file_priv *error_priv; |
d5442303 DV |
971 | |
972 | error_priv = kzalloc(sizeof(*error_priv), GFP_KERNEL); | |
973 | if (!error_priv) | |
974 | return -ENOMEM; | |
975 | ||
976 | error_priv->dev = dev; | |
977 | ||
95d5bfb3 | 978 | i915_error_state_get(dev, error_priv); |
d5442303 | 979 | |
edc3d884 MK |
980 | file->private_data = error_priv; |
981 | ||
982 | return 0; | |
d5442303 DV |
983 | } |
984 | ||
985 | static int i915_error_state_release(struct inode *inode, struct file *file) | |
986 | { | |
edc3d884 | 987 | struct i915_error_state_file_priv *error_priv = file->private_data; |
d5442303 | 988 | |
95d5bfb3 | 989 | i915_error_state_put(error_priv); |
d5442303 DV |
990 | kfree(error_priv); |
991 | ||
edc3d884 MK |
992 | return 0; |
993 | } | |
994 | ||
4dc955f7 MK |
995 | static ssize_t i915_error_state_read(struct file *file, char __user *userbuf, |
996 | size_t count, loff_t *pos) | |
997 | { | |
998 | struct i915_error_state_file_priv *error_priv = file->private_data; | |
999 | struct drm_i915_error_state_buf error_str; | |
1000 | loff_t tmp_pos = 0; | |
1001 | ssize_t ret_count = 0; | |
1002 | int ret; | |
1003 | ||
0a4cd7c8 | 1004 | ret = i915_error_state_buf_init(&error_str, to_i915(error_priv->dev), count, *pos); |
4dc955f7 MK |
1005 | if (ret) |
1006 | return ret; | |
edc3d884 | 1007 | |
fc16b48b | 1008 | ret = i915_error_state_to_str(&error_str, error_priv); |
edc3d884 MK |
1009 | if (ret) |
1010 | goto out; | |
1011 | ||
edc3d884 MK |
1012 | ret_count = simple_read_from_buffer(userbuf, count, &tmp_pos, |
1013 | error_str.buf, | |
1014 | error_str.bytes); | |
1015 | ||
1016 | if (ret_count < 0) | |
1017 | ret = ret_count; | |
1018 | else | |
1019 | *pos = error_str.start + ret_count; | |
1020 | out: | |
4dc955f7 | 1021 | i915_error_state_buf_release(&error_str); |
edc3d884 | 1022 | return ret ?: ret_count; |
d5442303 DV |
1023 | } |
1024 | ||
1025 | static const struct file_operations i915_error_state_fops = { | |
1026 | .owner = THIS_MODULE, | |
1027 | .open = i915_error_state_open, | |
edc3d884 | 1028 | .read = i915_error_state_read, |
d5442303 DV |
1029 | .write = i915_error_state_write, |
1030 | .llseek = default_llseek, | |
1031 | .release = i915_error_state_release, | |
1032 | }; | |
1033 | ||
647416f9 KC |
1034 | static int |
1035 | i915_next_seqno_get(void *data, u64 *val) | |
40633219 | 1036 | { |
647416f9 | 1037 | struct drm_device *dev = data; |
e277a1f8 | 1038 | struct drm_i915_private *dev_priv = dev->dev_private; |
40633219 MK |
1039 | int ret; |
1040 | ||
1041 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
1042 | if (ret) | |
1043 | return ret; | |
1044 | ||
647416f9 | 1045 | *val = dev_priv->next_seqno; |
40633219 MK |
1046 | mutex_unlock(&dev->struct_mutex); |
1047 | ||
647416f9 | 1048 | return 0; |
40633219 MK |
1049 | } |
1050 | ||
647416f9 KC |
1051 | static int |
1052 | i915_next_seqno_set(void *data, u64 val) | |
1053 | { | |
1054 | struct drm_device *dev = data; | |
40633219 MK |
1055 | int ret; |
1056 | ||
40633219 MK |
1057 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
1058 | if (ret) | |
1059 | return ret; | |
1060 | ||
e94fbaa8 | 1061 | ret = i915_gem_set_seqno(dev, val); |
40633219 MK |
1062 | mutex_unlock(&dev->struct_mutex); |
1063 | ||
647416f9 | 1064 | return ret; |
40633219 MK |
1065 | } |
1066 | ||
647416f9 KC |
1067 | DEFINE_SIMPLE_ATTRIBUTE(i915_next_seqno_fops, |
1068 | i915_next_seqno_get, i915_next_seqno_set, | |
3a3b4f98 | 1069 | "0x%llx\n"); |
40633219 | 1070 | |
adb4bd12 | 1071 | static int i915_frequency_info(struct seq_file *m, void *unused) |
f97108d1 | 1072 | { |
9f25d007 | 1073 | struct drm_info_node *node = m->private; |
f97108d1 | 1074 | struct drm_device *dev = node->minor->dev; |
e277a1f8 | 1075 | struct drm_i915_private *dev_priv = dev->dev_private; |
c8c8fb33 PZ |
1076 | int ret = 0; |
1077 | ||
1078 | intel_runtime_pm_get(dev_priv); | |
3b8d8d91 | 1079 | |
5c9669ce TR |
1080 | flush_delayed_work(&dev_priv->rps.delayed_resume_work); |
1081 | ||
3b8d8d91 JB |
1082 | if (IS_GEN5(dev)) { |
1083 | u16 rgvswctl = I915_READ16(MEMSWCTL); | |
1084 | u16 rgvstat = I915_READ16(MEMSTAT_ILK); | |
1085 | ||
1086 | seq_printf(m, "Requested P-state: %d\n", (rgvswctl >> 8) & 0xf); | |
1087 | seq_printf(m, "Requested VID: %d\n", rgvswctl & 0x3f); | |
1088 | seq_printf(m, "Current VID: %d\n", (rgvstat & MEMSTAT_VID_MASK) >> | |
1089 | MEMSTAT_VID_SHIFT); | |
1090 | seq_printf(m, "Current P-state: %d\n", | |
1091 | (rgvstat & MEMSTAT_PSTATE_MASK) >> MEMSTAT_PSTATE_SHIFT); | |
daa3afb2 | 1092 | } else if (IS_GEN6(dev) || (IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) || |
60260a5b | 1093 | IS_BROADWELL(dev) || IS_GEN9(dev)) { |
3b8d8d91 JB |
1094 | u32 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS); |
1095 | u32 rp_state_limits = I915_READ(GEN6_RP_STATE_LIMITS); | |
1096 | u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP); | |
0d8f9491 | 1097 | u32 rpmodectl, rpinclimit, rpdeclimit; |
8e8c06cd | 1098 | u32 rpstat, cagf, reqf; |
ccab5c82 JB |
1099 | u32 rpupei, rpcurup, rpprevup; |
1100 | u32 rpdownei, rpcurdown, rpprevdown; | |
9dd3c605 | 1101 | u32 pm_ier, pm_imr, pm_isr, pm_iir, pm_mask; |
3b8d8d91 JB |
1102 | int max_freq; |
1103 | ||
1104 | /* RPSTAT1 is in the GT power well */ | |
d1ebd816 BW |
1105 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
1106 | if (ret) | |
c8c8fb33 | 1107 | goto out; |
d1ebd816 | 1108 | |
59bad947 | 1109 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); |
3b8d8d91 | 1110 | |
8e8c06cd | 1111 | reqf = I915_READ(GEN6_RPNSWREQ); |
60260a5b AG |
1112 | if (IS_GEN9(dev)) |
1113 | reqf >>= 23; | |
1114 | else { | |
1115 | reqf &= ~GEN6_TURBO_DISABLE; | |
1116 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) | |
1117 | reqf >>= 24; | |
1118 | else | |
1119 | reqf >>= 25; | |
1120 | } | |
7c59a9c1 | 1121 | reqf = intel_gpu_freq(dev_priv, reqf); |
8e8c06cd | 1122 | |
0d8f9491 CW |
1123 | rpmodectl = I915_READ(GEN6_RP_CONTROL); |
1124 | rpinclimit = I915_READ(GEN6_RP_UP_THRESHOLD); | |
1125 | rpdeclimit = I915_READ(GEN6_RP_DOWN_THRESHOLD); | |
1126 | ||
ccab5c82 JB |
1127 | rpstat = I915_READ(GEN6_RPSTAT1); |
1128 | rpupei = I915_READ(GEN6_RP_CUR_UP_EI); | |
1129 | rpcurup = I915_READ(GEN6_RP_CUR_UP); | |
1130 | rpprevup = I915_READ(GEN6_RP_PREV_UP); | |
1131 | rpdownei = I915_READ(GEN6_RP_CUR_DOWN_EI); | |
1132 | rpcurdown = I915_READ(GEN6_RP_CUR_DOWN); | |
1133 | rpprevdown = I915_READ(GEN6_RP_PREV_DOWN); | |
60260a5b AG |
1134 | if (IS_GEN9(dev)) |
1135 | cagf = (rpstat & GEN9_CAGF_MASK) >> GEN9_CAGF_SHIFT; | |
1136 | else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) | |
f82855d3 BW |
1137 | cagf = (rpstat & HSW_CAGF_MASK) >> HSW_CAGF_SHIFT; |
1138 | else | |
1139 | cagf = (rpstat & GEN6_CAGF_MASK) >> GEN6_CAGF_SHIFT; | |
7c59a9c1 | 1140 | cagf = intel_gpu_freq(dev_priv, cagf); |
ccab5c82 | 1141 | |
59bad947 | 1142 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); |
d1ebd816 BW |
1143 | mutex_unlock(&dev->struct_mutex); |
1144 | ||
9dd3c605 PZ |
1145 | if (IS_GEN6(dev) || IS_GEN7(dev)) { |
1146 | pm_ier = I915_READ(GEN6_PMIER); | |
1147 | pm_imr = I915_READ(GEN6_PMIMR); | |
1148 | pm_isr = I915_READ(GEN6_PMISR); | |
1149 | pm_iir = I915_READ(GEN6_PMIIR); | |
1150 | pm_mask = I915_READ(GEN6_PMINTRMSK); | |
1151 | } else { | |
1152 | pm_ier = I915_READ(GEN8_GT_IER(2)); | |
1153 | pm_imr = I915_READ(GEN8_GT_IMR(2)); | |
1154 | pm_isr = I915_READ(GEN8_GT_ISR(2)); | |
1155 | pm_iir = I915_READ(GEN8_GT_IIR(2)); | |
1156 | pm_mask = I915_READ(GEN6_PMINTRMSK); | |
1157 | } | |
0d8f9491 | 1158 | seq_printf(m, "PM IER=0x%08x IMR=0x%08x ISR=0x%08x IIR=0x%08x, MASK=0x%08x\n", |
9dd3c605 | 1159 | pm_ier, pm_imr, pm_isr, pm_iir, pm_mask); |
3b8d8d91 | 1160 | seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status); |
3b8d8d91 | 1161 | seq_printf(m, "Render p-state ratio: %d\n", |
60260a5b | 1162 | (gt_perf_status & (IS_GEN9(dev) ? 0x1ff00 : 0xff00)) >> 8); |
3b8d8d91 JB |
1163 | seq_printf(m, "Render p-state VID: %d\n", |
1164 | gt_perf_status & 0xff); | |
1165 | seq_printf(m, "Render p-state limit: %d\n", | |
1166 | rp_state_limits & 0xff); | |
0d8f9491 CW |
1167 | seq_printf(m, "RPSTAT1: 0x%08x\n", rpstat); |
1168 | seq_printf(m, "RPMODECTL: 0x%08x\n", rpmodectl); | |
1169 | seq_printf(m, "RPINCLIMIT: 0x%08x\n", rpinclimit); | |
1170 | seq_printf(m, "RPDECLIMIT: 0x%08x\n", rpdeclimit); | |
8e8c06cd | 1171 | seq_printf(m, "RPNSWREQ: %dMHz\n", reqf); |
f82855d3 | 1172 | seq_printf(m, "CAGF: %dMHz\n", cagf); |
ccab5c82 JB |
1173 | seq_printf(m, "RP CUR UP EI: %dus\n", rpupei & |
1174 | GEN6_CURICONT_MASK); | |
1175 | seq_printf(m, "RP CUR UP: %dus\n", rpcurup & | |
1176 | GEN6_CURBSYTAVG_MASK); | |
1177 | seq_printf(m, "RP PREV UP: %dus\n", rpprevup & | |
1178 | GEN6_CURBSYTAVG_MASK); | |
1179 | seq_printf(m, "RP CUR DOWN EI: %dus\n", rpdownei & | |
1180 | GEN6_CURIAVG_MASK); | |
1181 | seq_printf(m, "RP CUR DOWN: %dus\n", rpcurdown & | |
1182 | GEN6_CURBSYTAVG_MASK); | |
1183 | seq_printf(m, "RP PREV DOWN: %dus\n", rpprevdown & | |
1184 | GEN6_CURBSYTAVG_MASK); | |
3b8d8d91 JB |
1185 | |
1186 | max_freq = (rp_state_cap & 0xff0000) >> 16; | |
60260a5b | 1187 | max_freq *= (IS_SKYLAKE(dev) ? GEN9_FREQ_SCALER : 1); |
3b8d8d91 | 1188 | seq_printf(m, "Lowest (RPN) frequency: %dMHz\n", |
7c59a9c1 | 1189 | intel_gpu_freq(dev_priv, max_freq)); |
3b8d8d91 JB |
1190 | |
1191 | max_freq = (rp_state_cap & 0xff00) >> 8; | |
60260a5b | 1192 | max_freq *= (IS_SKYLAKE(dev) ? GEN9_FREQ_SCALER : 1); |
3b8d8d91 | 1193 | seq_printf(m, "Nominal (RP1) frequency: %dMHz\n", |
7c59a9c1 | 1194 | intel_gpu_freq(dev_priv, max_freq)); |
3b8d8d91 JB |
1195 | |
1196 | max_freq = rp_state_cap & 0xff; | |
60260a5b | 1197 | max_freq *= (IS_SKYLAKE(dev) ? GEN9_FREQ_SCALER : 1); |
3b8d8d91 | 1198 | seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n", |
7c59a9c1 | 1199 | intel_gpu_freq(dev_priv, max_freq)); |
31c77388 BW |
1200 | |
1201 | seq_printf(m, "Max overclocked frequency: %dMHz\n", | |
7c59a9c1 | 1202 | intel_gpu_freq(dev_priv, dev_priv->rps.max_freq)); |
0a073b84 | 1203 | } else if (IS_VALLEYVIEW(dev)) { |
03af2045 | 1204 | u32 freq_sts; |
0a073b84 | 1205 | |
259bd5d4 | 1206 | mutex_lock(&dev_priv->rps.hw_lock); |
64936258 | 1207 | freq_sts = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS); |
0a073b84 JB |
1208 | seq_printf(m, "PUNIT_REG_GPU_FREQ_STS: 0x%08x\n", freq_sts); |
1209 | seq_printf(m, "DDR freq: %d MHz\n", dev_priv->mem_freq); | |
1210 | ||
0a073b84 | 1211 | seq_printf(m, "max GPU freq: %d MHz\n", |
7c59a9c1 | 1212 | intel_gpu_freq(dev_priv, dev_priv->rps.max_freq)); |
0a073b84 | 1213 | |
0a073b84 | 1214 | seq_printf(m, "min GPU freq: %d MHz\n", |
7c59a9c1 | 1215 | intel_gpu_freq(dev_priv, dev_priv->rps.min_freq)); |
03af2045 | 1216 | |
7c59a9c1 VS |
1217 | seq_printf(m, |
1218 | "efficient (RPe) frequency: %d MHz\n", | |
1219 | intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq)); | |
0a073b84 JB |
1220 | |
1221 | seq_printf(m, "current GPU freq: %d MHz\n", | |
7c59a9c1 | 1222 | intel_gpu_freq(dev_priv, (freq_sts >> 8) & 0xff)); |
259bd5d4 | 1223 | mutex_unlock(&dev_priv->rps.hw_lock); |
3b8d8d91 | 1224 | } else { |
267f0c90 | 1225 | seq_puts(m, "no P-state info available\n"); |
3b8d8d91 | 1226 | } |
f97108d1 | 1227 | |
c8c8fb33 PZ |
1228 | out: |
1229 | intel_runtime_pm_put(dev_priv); | |
1230 | return ret; | |
f97108d1 JB |
1231 | } |
1232 | ||
f654449a CW |
1233 | static int i915_hangcheck_info(struct seq_file *m, void *unused) |
1234 | { | |
1235 | struct drm_info_node *node = m->private; | |
ebbc7546 MK |
1236 | struct drm_device *dev = node->minor->dev; |
1237 | struct drm_i915_private *dev_priv = dev->dev_private; | |
f654449a | 1238 | struct intel_engine_cs *ring; |
ebbc7546 MK |
1239 | u64 acthd[I915_NUM_RINGS]; |
1240 | u32 seqno[I915_NUM_RINGS]; | |
f654449a CW |
1241 | int i; |
1242 | ||
1243 | if (!i915.enable_hangcheck) { | |
1244 | seq_printf(m, "Hangcheck disabled\n"); | |
1245 | return 0; | |
1246 | } | |
1247 | ||
ebbc7546 MK |
1248 | intel_runtime_pm_get(dev_priv); |
1249 | ||
1250 | for_each_ring(ring, dev_priv, i) { | |
1251 | seqno[i] = ring->get_seqno(ring, false); | |
1252 | acthd[i] = intel_ring_get_active_head(ring); | |
1253 | } | |
1254 | ||
1255 | intel_runtime_pm_put(dev_priv); | |
1256 | ||
f654449a CW |
1257 | if (delayed_work_pending(&dev_priv->gpu_error.hangcheck_work)) { |
1258 | seq_printf(m, "Hangcheck active, fires in %dms\n", | |
1259 | jiffies_to_msecs(dev_priv->gpu_error.hangcheck_work.timer.expires - | |
1260 | jiffies)); | |
1261 | } else | |
1262 | seq_printf(m, "Hangcheck inactive\n"); | |
1263 | ||
1264 | for_each_ring(ring, dev_priv, i) { | |
1265 | seq_printf(m, "%s:\n", ring->name); | |
1266 | seq_printf(m, "\tseqno = %x [current %x]\n", | |
ebbc7546 | 1267 | ring->hangcheck.seqno, seqno[i]); |
f654449a CW |
1268 | seq_printf(m, "\tACTHD = 0x%08llx [current 0x%08llx]\n", |
1269 | (long long)ring->hangcheck.acthd, | |
ebbc7546 | 1270 | (long long)acthd[i]); |
f654449a CW |
1271 | seq_printf(m, "\tmax ACTHD = 0x%08llx\n", |
1272 | (long long)ring->hangcheck.max_acthd); | |
ebbc7546 MK |
1273 | seq_printf(m, "\tscore = %d\n", ring->hangcheck.score); |
1274 | seq_printf(m, "\taction = %d\n", ring->hangcheck.action); | |
f654449a CW |
1275 | } |
1276 | ||
1277 | return 0; | |
1278 | } | |
1279 | ||
4d85529d | 1280 | static int ironlake_drpc_info(struct seq_file *m) |
f97108d1 | 1281 | { |
9f25d007 | 1282 | struct drm_info_node *node = m->private; |
f97108d1 | 1283 | struct drm_device *dev = node->minor->dev; |
e277a1f8 | 1284 | struct drm_i915_private *dev_priv = dev->dev_private; |
616fdb5a BW |
1285 | u32 rgvmodectl, rstdbyctl; |
1286 | u16 crstandvid; | |
1287 | int ret; | |
1288 | ||
1289 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
1290 | if (ret) | |
1291 | return ret; | |
c8c8fb33 | 1292 | intel_runtime_pm_get(dev_priv); |
616fdb5a BW |
1293 | |
1294 | rgvmodectl = I915_READ(MEMMODECTL); | |
1295 | rstdbyctl = I915_READ(RSTDBYCTL); | |
1296 | crstandvid = I915_READ16(CRSTANDVID); | |
1297 | ||
c8c8fb33 | 1298 | intel_runtime_pm_put(dev_priv); |
616fdb5a | 1299 | mutex_unlock(&dev->struct_mutex); |
f97108d1 JB |
1300 | |
1301 | seq_printf(m, "HD boost: %s\n", (rgvmodectl & MEMMODE_BOOST_EN) ? | |
1302 | "yes" : "no"); | |
1303 | seq_printf(m, "Boost freq: %d\n", | |
1304 | (rgvmodectl & MEMMODE_BOOST_FREQ_MASK) >> | |
1305 | MEMMODE_BOOST_FREQ_SHIFT); | |
1306 | seq_printf(m, "HW control enabled: %s\n", | |
1307 | rgvmodectl & MEMMODE_HWIDLE_EN ? "yes" : "no"); | |
1308 | seq_printf(m, "SW control enabled: %s\n", | |
1309 | rgvmodectl & MEMMODE_SWMODE_EN ? "yes" : "no"); | |
1310 | seq_printf(m, "Gated voltage change: %s\n", | |
1311 | rgvmodectl & MEMMODE_RCLK_GATE ? "yes" : "no"); | |
1312 | seq_printf(m, "Starting frequency: P%d\n", | |
1313 | (rgvmodectl & MEMMODE_FSTART_MASK) >> MEMMODE_FSTART_SHIFT); | |
7648fa99 | 1314 | seq_printf(m, "Max P-state: P%d\n", |
f97108d1 | 1315 | (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT); |
7648fa99 JB |
1316 | seq_printf(m, "Min P-state: P%d\n", (rgvmodectl & MEMMODE_FMIN_MASK)); |
1317 | seq_printf(m, "RS1 VID: %d\n", (crstandvid & 0x3f)); | |
1318 | seq_printf(m, "RS2 VID: %d\n", ((crstandvid >> 8) & 0x3f)); | |
1319 | seq_printf(m, "Render standby enabled: %s\n", | |
1320 | (rstdbyctl & RCX_SW_EXIT) ? "no" : "yes"); | |
267f0c90 | 1321 | seq_puts(m, "Current RS state: "); |
88271da3 JB |
1322 | switch (rstdbyctl & RSX_STATUS_MASK) { |
1323 | case RSX_STATUS_ON: | |
267f0c90 | 1324 | seq_puts(m, "on\n"); |
88271da3 JB |
1325 | break; |
1326 | case RSX_STATUS_RC1: | |
267f0c90 | 1327 | seq_puts(m, "RC1\n"); |
88271da3 JB |
1328 | break; |
1329 | case RSX_STATUS_RC1E: | |
267f0c90 | 1330 | seq_puts(m, "RC1E\n"); |
88271da3 JB |
1331 | break; |
1332 | case RSX_STATUS_RS1: | |
267f0c90 | 1333 | seq_puts(m, "RS1\n"); |
88271da3 JB |
1334 | break; |
1335 | case RSX_STATUS_RS2: | |
267f0c90 | 1336 | seq_puts(m, "RS2 (RC6)\n"); |
88271da3 JB |
1337 | break; |
1338 | case RSX_STATUS_RS3: | |
267f0c90 | 1339 | seq_puts(m, "RC3 (RC6+)\n"); |
88271da3 JB |
1340 | break; |
1341 | default: | |
267f0c90 | 1342 | seq_puts(m, "unknown\n"); |
88271da3 JB |
1343 | break; |
1344 | } | |
f97108d1 JB |
1345 | |
1346 | return 0; | |
1347 | } | |
1348 | ||
f65367b5 | 1349 | static int i915_forcewake_domains(struct seq_file *m, void *data) |
669ab5aa | 1350 | { |
b2cff0db CW |
1351 | struct drm_info_node *node = m->private; |
1352 | struct drm_device *dev = node->minor->dev; | |
1353 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1354 | struct intel_uncore_forcewake_domain *fw_domain; | |
b2cff0db CW |
1355 | int i; |
1356 | ||
1357 | spin_lock_irq(&dev_priv->uncore.lock); | |
1358 | for_each_fw_domain(fw_domain, dev_priv, i) { | |
1359 | seq_printf(m, "%s.wake_count = %u\n", | |
05a2fb15 | 1360 | intel_uncore_forcewake_domain_to_str(i), |
b2cff0db CW |
1361 | fw_domain->wake_count); |
1362 | } | |
1363 | spin_unlock_irq(&dev_priv->uncore.lock); | |
669ab5aa | 1364 | |
b2cff0db CW |
1365 | return 0; |
1366 | } | |
1367 | ||
1368 | static int vlv_drpc_info(struct seq_file *m) | |
1369 | { | |
9f25d007 | 1370 | struct drm_info_node *node = m->private; |
669ab5aa D |
1371 | struct drm_device *dev = node->minor->dev; |
1372 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6b312cd3 | 1373 | u32 rpmodectl1, rcctl1, pw_status; |
669ab5aa | 1374 | |
d46c0517 ID |
1375 | intel_runtime_pm_get(dev_priv); |
1376 | ||
6b312cd3 | 1377 | pw_status = I915_READ(VLV_GTLC_PW_STATUS); |
669ab5aa D |
1378 | rpmodectl1 = I915_READ(GEN6_RP_CONTROL); |
1379 | rcctl1 = I915_READ(GEN6_RC_CONTROL); | |
1380 | ||
d46c0517 ID |
1381 | intel_runtime_pm_put(dev_priv); |
1382 | ||
669ab5aa D |
1383 | seq_printf(m, "Video Turbo Mode: %s\n", |
1384 | yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO)); | |
1385 | seq_printf(m, "Turbo enabled: %s\n", | |
1386 | yesno(rpmodectl1 & GEN6_RP_ENABLE)); | |
1387 | seq_printf(m, "HW control enabled: %s\n", | |
1388 | yesno(rpmodectl1 & GEN6_RP_ENABLE)); | |
1389 | seq_printf(m, "SW control enabled: %s\n", | |
1390 | yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) == | |
1391 | GEN6_RP_MEDIA_SW_MODE)); | |
1392 | seq_printf(m, "RC6 Enabled: %s\n", | |
1393 | yesno(rcctl1 & (GEN7_RC_CTL_TO_MODE | | |
1394 | GEN6_RC_CTL_EI_MODE(1)))); | |
1395 | seq_printf(m, "Render Power Well: %s\n", | |
6b312cd3 | 1396 | (pw_status & VLV_GTLC_PW_RENDER_STATUS_MASK) ? "Up" : "Down"); |
669ab5aa | 1397 | seq_printf(m, "Media Power Well: %s\n", |
6b312cd3 | 1398 | (pw_status & VLV_GTLC_PW_MEDIA_STATUS_MASK) ? "Up" : "Down"); |
669ab5aa | 1399 | |
9cc19be5 ID |
1400 | seq_printf(m, "Render RC6 residency since boot: %u\n", |
1401 | I915_READ(VLV_GT_RENDER_RC6)); | |
1402 | seq_printf(m, "Media RC6 residency since boot: %u\n", | |
1403 | I915_READ(VLV_GT_MEDIA_RC6)); | |
1404 | ||
f65367b5 | 1405 | return i915_forcewake_domains(m, NULL); |
669ab5aa D |
1406 | } |
1407 | ||
4d85529d BW |
1408 | static int gen6_drpc_info(struct seq_file *m) |
1409 | { | |
9f25d007 | 1410 | struct drm_info_node *node = m->private; |
4d85529d BW |
1411 | struct drm_device *dev = node->minor->dev; |
1412 | struct drm_i915_private *dev_priv = dev->dev_private; | |
ecd8faea | 1413 | u32 rpmodectl1, gt_core_status, rcctl1, rc6vids = 0; |
93b525dc | 1414 | unsigned forcewake_count; |
aee56cff | 1415 | int count = 0, ret; |
4d85529d BW |
1416 | |
1417 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
1418 | if (ret) | |
1419 | return ret; | |
c8c8fb33 | 1420 | intel_runtime_pm_get(dev_priv); |
4d85529d | 1421 | |
907b28c5 | 1422 | spin_lock_irq(&dev_priv->uncore.lock); |
b2cff0db | 1423 | forcewake_count = dev_priv->uncore.fw_domain[FW_DOMAIN_ID_RENDER].wake_count; |
907b28c5 | 1424 | spin_unlock_irq(&dev_priv->uncore.lock); |
93b525dc DV |
1425 | |
1426 | if (forcewake_count) { | |
267f0c90 DL |
1427 | seq_puts(m, "RC information inaccurate because somebody " |
1428 | "holds a forcewake reference \n"); | |
4d85529d BW |
1429 | } else { |
1430 | /* NB: we cannot use forcewake, else we read the wrong values */ | |
1431 | while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1)) | |
1432 | udelay(10); | |
1433 | seq_printf(m, "RC information accurate: %s\n", yesno(count < 51)); | |
1434 | } | |
1435 | ||
1436 | gt_core_status = readl(dev_priv->regs + GEN6_GT_CORE_STATUS); | |
ed71f1b4 | 1437 | trace_i915_reg_rw(false, GEN6_GT_CORE_STATUS, gt_core_status, 4, true); |
4d85529d BW |
1438 | |
1439 | rpmodectl1 = I915_READ(GEN6_RP_CONTROL); | |
1440 | rcctl1 = I915_READ(GEN6_RC_CONTROL); | |
1441 | mutex_unlock(&dev->struct_mutex); | |
44cbd338 BW |
1442 | mutex_lock(&dev_priv->rps.hw_lock); |
1443 | sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids); | |
1444 | mutex_unlock(&dev_priv->rps.hw_lock); | |
4d85529d | 1445 | |
c8c8fb33 PZ |
1446 | intel_runtime_pm_put(dev_priv); |
1447 | ||
4d85529d BW |
1448 | seq_printf(m, "Video Turbo Mode: %s\n", |
1449 | yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO)); | |
1450 | seq_printf(m, "HW control enabled: %s\n", | |
1451 | yesno(rpmodectl1 & GEN6_RP_ENABLE)); | |
1452 | seq_printf(m, "SW control enabled: %s\n", | |
1453 | yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) == | |
1454 | GEN6_RP_MEDIA_SW_MODE)); | |
fff24e21 | 1455 | seq_printf(m, "RC1e Enabled: %s\n", |
4d85529d BW |
1456 | yesno(rcctl1 & GEN6_RC_CTL_RC1e_ENABLE)); |
1457 | seq_printf(m, "RC6 Enabled: %s\n", | |
1458 | yesno(rcctl1 & GEN6_RC_CTL_RC6_ENABLE)); | |
1459 | seq_printf(m, "Deep RC6 Enabled: %s\n", | |
1460 | yesno(rcctl1 & GEN6_RC_CTL_RC6p_ENABLE)); | |
1461 | seq_printf(m, "Deepest RC6 Enabled: %s\n", | |
1462 | yesno(rcctl1 & GEN6_RC_CTL_RC6pp_ENABLE)); | |
267f0c90 | 1463 | seq_puts(m, "Current RC state: "); |
4d85529d BW |
1464 | switch (gt_core_status & GEN6_RCn_MASK) { |
1465 | case GEN6_RC0: | |
1466 | if (gt_core_status & GEN6_CORE_CPD_STATE_MASK) | |
267f0c90 | 1467 | seq_puts(m, "Core Power Down\n"); |
4d85529d | 1468 | else |
267f0c90 | 1469 | seq_puts(m, "on\n"); |
4d85529d BW |
1470 | break; |
1471 | case GEN6_RC3: | |
267f0c90 | 1472 | seq_puts(m, "RC3\n"); |
4d85529d BW |
1473 | break; |
1474 | case GEN6_RC6: | |
267f0c90 | 1475 | seq_puts(m, "RC6\n"); |
4d85529d BW |
1476 | break; |
1477 | case GEN6_RC7: | |
267f0c90 | 1478 | seq_puts(m, "RC7\n"); |
4d85529d BW |
1479 | break; |
1480 | default: | |
267f0c90 | 1481 | seq_puts(m, "Unknown\n"); |
4d85529d BW |
1482 | break; |
1483 | } | |
1484 | ||
1485 | seq_printf(m, "Core Power Down: %s\n", | |
1486 | yesno(gt_core_status & GEN6_CORE_CPD_STATE_MASK)); | |
cce66a28 BW |
1487 | |
1488 | /* Not exactly sure what this is */ | |
1489 | seq_printf(m, "RC6 \"Locked to RPn\" residency since boot: %u\n", | |
1490 | I915_READ(GEN6_GT_GFX_RC6_LOCKED)); | |
1491 | seq_printf(m, "RC6 residency since boot: %u\n", | |
1492 | I915_READ(GEN6_GT_GFX_RC6)); | |
1493 | seq_printf(m, "RC6+ residency since boot: %u\n", | |
1494 | I915_READ(GEN6_GT_GFX_RC6p)); | |
1495 | seq_printf(m, "RC6++ residency since boot: %u\n", | |
1496 | I915_READ(GEN6_GT_GFX_RC6pp)); | |
1497 | ||
ecd8faea BW |
1498 | seq_printf(m, "RC6 voltage: %dmV\n", |
1499 | GEN6_DECODE_RC6_VID(((rc6vids >> 0) & 0xff))); | |
1500 | seq_printf(m, "RC6+ voltage: %dmV\n", | |
1501 | GEN6_DECODE_RC6_VID(((rc6vids >> 8) & 0xff))); | |
1502 | seq_printf(m, "RC6++ voltage: %dmV\n", | |
1503 | GEN6_DECODE_RC6_VID(((rc6vids >> 16) & 0xff))); | |
4d85529d BW |
1504 | return 0; |
1505 | } | |
1506 | ||
1507 | static int i915_drpc_info(struct seq_file *m, void *unused) | |
1508 | { | |
9f25d007 | 1509 | struct drm_info_node *node = m->private; |
4d85529d BW |
1510 | struct drm_device *dev = node->minor->dev; |
1511 | ||
669ab5aa D |
1512 | if (IS_VALLEYVIEW(dev)) |
1513 | return vlv_drpc_info(m); | |
ac66cf4b | 1514 | else if (INTEL_INFO(dev)->gen >= 6) |
4d85529d BW |
1515 | return gen6_drpc_info(m); |
1516 | else | |
1517 | return ironlake_drpc_info(m); | |
1518 | } | |
1519 | ||
b5e50c3f JB |
1520 | static int i915_fbc_status(struct seq_file *m, void *unused) |
1521 | { | |
9f25d007 | 1522 | struct drm_info_node *node = m->private; |
b5e50c3f | 1523 | struct drm_device *dev = node->minor->dev; |
e277a1f8 | 1524 | struct drm_i915_private *dev_priv = dev->dev_private; |
b5e50c3f | 1525 | |
3a77c4c4 | 1526 | if (!HAS_FBC(dev)) { |
267f0c90 | 1527 | seq_puts(m, "FBC unsupported on this chipset\n"); |
b5e50c3f JB |
1528 | return 0; |
1529 | } | |
1530 | ||
36623ef8 PZ |
1531 | intel_runtime_pm_get(dev_priv); |
1532 | ||
ee5382ae | 1533 | if (intel_fbc_enabled(dev)) { |
267f0c90 | 1534 | seq_puts(m, "FBC enabled\n"); |
b5e50c3f | 1535 | } else { |
267f0c90 | 1536 | seq_puts(m, "FBC disabled: "); |
5c3fe8b0 | 1537 | switch (dev_priv->fbc.no_fbc_reason) { |
29ebf90f CW |
1538 | case FBC_OK: |
1539 | seq_puts(m, "FBC actived, but currently disabled in hardware"); | |
1540 | break; | |
1541 | case FBC_UNSUPPORTED: | |
1542 | seq_puts(m, "unsupported by this chipset"); | |
1543 | break; | |
bed4a673 | 1544 | case FBC_NO_OUTPUT: |
267f0c90 | 1545 | seq_puts(m, "no outputs"); |
bed4a673 | 1546 | break; |
b5e50c3f | 1547 | case FBC_STOLEN_TOO_SMALL: |
267f0c90 | 1548 | seq_puts(m, "not enough stolen memory"); |
b5e50c3f JB |
1549 | break; |
1550 | case FBC_UNSUPPORTED_MODE: | |
267f0c90 | 1551 | seq_puts(m, "mode not supported"); |
b5e50c3f JB |
1552 | break; |
1553 | case FBC_MODE_TOO_LARGE: | |
267f0c90 | 1554 | seq_puts(m, "mode too large"); |
b5e50c3f JB |
1555 | break; |
1556 | case FBC_BAD_PLANE: | |
267f0c90 | 1557 | seq_puts(m, "FBC unsupported on plane"); |
b5e50c3f JB |
1558 | break; |
1559 | case FBC_NOT_TILED: | |
267f0c90 | 1560 | seq_puts(m, "scanout buffer not tiled"); |
b5e50c3f | 1561 | break; |
9c928d16 | 1562 | case FBC_MULTIPLE_PIPES: |
267f0c90 | 1563 | seq_puts(m, "multiple pipes are enabled"); |
9c928d16 | 1564 | break; |
c1a9f047 | 1565 | case FBC_MODULE_PARAM: |
267f0c90 | 1566 | seq_puts(m, "disabled per module param (default off)"); |
c1a9f047 | 1567 | break; |
8a5729a3 | 1568 | case FBC_CHIP_DEFAULT: |
267f0c90 | 1569 | seq_puts(m, "disabled per chip default"); |
8a5729a3 | 1570 | break; |
b5e50c3f | 1571 | default: |
267f0c90 | 1572 | seq_puts(m, "unknown reason"); |
b5e50c3f | 1573 | } |
267f0c90 | 1574 | seq_putc(m, '\n'); |
b5e50c3f | 1575 | } |
36623ef8 PZ |
1576 | |
1577 | intel_runtime_pm_put(dev_priv); | |
1578 | ||
b5e50c3f JB |
1579 | return 0; |
1580 | } | |
1581 | ||
da46f936 RV |
1582 | static int i915_fbc_fc_get(void *data, u64 *val) |
1583 | { | |
1584 | struct drm_device *dev = data; | |
1585 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1586 | ||
1587 | if (INTEL_INFO(dev)->gen < 7 || !HAS_FBC(dev)) | |
1588 | return -ENODEV; | |
1589 | ||
1590 | drm_modeset_lock_all(dev); | |
1591 | *val = dev_priv->fbc.false_color; | |
1592 | drm_modeset_unlock_all(dev); | |
1593 | ||
1594 | return 0; | |
1595 | } | |
1596 | ||
1597 | static int i915_fbc_fc_set(void *data, u64 val) | |
1598 | { | |
1599 | struct drm_device *dev = data; | |
1600 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1601 | u32 reg; | |
1602 | ||
1603 | if (INTEL_INFO(dev)->gen < 7 || !HAS_FBC(dev)) | |
1604 | return -ENODEV; | |
1605 | ||
1606 | drm_modeset_lock_all(dev); | |
1607 | ||
1608 | reg = I915_READ(ILK_DPFC_CONTROL); | |
1609 | dev_priv->fbc.false_color = val; | |
1610 | ||
1611 | I915_WRITE(ILK_DPFC_CONTROL, val ? | |
1612 | (reg | FBC_CTL_FALSE_COLOR) : | |
1613 | (reg & ~FBC_CTL_FALSE_COLOR)); | |
1614 | ||
1615 | drm_modeset_unlock_all(dev); | |
1616 | return 0; | |
1617 | } | |
1618 | ||
1619 | DEFINE_SIMPLE_ATTRIBUTE(i915_fbc_fc_fops, | |
1620 | i915_fbc_fc_get, i915_fbc_fc_set, | |
1621 | "%llu\n"); | |
1622 | ||
92d44621 PZ |
1623 | static int i915_ips_status(struct seq_file *m, void *unused) |
1624 | { | |
9f25d007 | 1625 | struct drm_info_node *node = m->private; |
92d44621 PZ |
1626 | struct drm_device *dev = node->minor->dev; |
1627 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1628 | ||
f5adf94e | 1629 | if (!HAS_IPS(dev)) { |
92d44621 PZ |
1630 | seq_puts(m, "not supported\n"); |
1631 | return 0; | |
1632 | } | |
1633 | ||
36623ef8 PZ |
1634 | intel_runtime_pm_get(dev_priv); |
1635 | ||
0eaa53f0 RV |
1636 | seq_printf(m, "Enabled by kernel parameter: %s\n", |
1637 | yesno(i915.enable_ips)); | |
1638 | ||
1639 | if (INTEL_INFO(dev)->gen >= 8) { | |
1640 | seq_puts(m, "Currently: unknown\n"); | |
1641 | } else { | |
1642 | if (I915_READ(IPS_CTL) & IPS_ENABLE) | |
1643 | seq_puts(m, "Currently: enabled\n"); | |
1644 | else | |
1645 | seq_puts(m, "Currently: disabled\n"); | |
1646 | } | |
92d44621 | 1647 | |
36623ef8 PZ |
1648 | intel_runtime_pm_put(dev_priv); |
1649 | ||
92d44621 PZ |
1650 | return 0; |
1651 | } | |
1652 | ||
4a9bef37 JB |
1653 | static int i915_sr_status(struct seq_file *m, void *unused) |
1654 | { | |
9f25d007 | 1655 | struct drm_info_node *node = m->private; |
4a9bef37 | 1656 | struct drm_device *dev = node->minor->dev; |
e277a1f8 | 1657 | struct drm_i915_private *dev_priv = dev->dev_private; |
4a9bef37 JB |
1658 | bool sr_enabled = false; |
1659 | ||
36623ef8 PZ |
1660 | intel_runtime_pm_get(dev_priv); |
1661 | ||
1398261a | 1662 | if (HAS_PCH_SPLIT(dev)) |
5ba2aaaa | 1663 | sr_enabled = I915_READ(WM1_LP_ILK) & WM1_LP_SR_EN; |
a6c45cf0 | 1664 | else if (IS_CRESTLINE(dev) || IS_I945G(dev) || IS_I945GM(dev)) |
4a9bef37 JB |
1665 | sr_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN; |
1666 | else if (IS_I915GM(dev)) | |
1667 | sr_enabled = I915_READ(INSTPM) & INSTPM_SELF_EN; | |
1668 | else if (IS_PINEVIEW(dev)) | |
1669 | sr_enabled = I915_READ(DSPFW3) & PINEVIEW_SELF_REFRESH_EN; | |
1670 | ||
36623ef8 PZ |
1671 | intel_runtime_pm_put(dev_priv); |
1672 | ||
5ba2aaaa CW |
1673 | seq_printf(m, "self-refresh: %s\n", |
1674 | sr_enabled ? "enabled" : "disabled"); | |
4a9bef37 JB |
1675 | |
1676 | return 0; | |
1677 | } | |
1678 | ||
7648fa99 JB |
1679 | static int i915_emon_status(struct seq_file *m, void *unused) |
1680 | { | |
9f25d007 | 1681 | struct drm_info_node *node = m->private; |
7648fa99 | 1682 | struct drm_device *dev = node->minor->dev; |
e277a1f8 | 1683 | struct drm_i915_private *dev_priv = dev->dev_private; |
7648fa99 | 1684 | unsigned long temp, chipset, gfx; |
de227ef0 CW |
1685 | int ret; |
1686 | ||
582be6b4 CW |
1687 | if (!IS_GEN5(dev)) |
1688 | return -ENODEV; | |
1689 | ||
de227ef0 CW |
1690 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
1691 | if (ret) | |
1692 | return ret; | |
7648fa99 JB |
1693 | |
1694 | temp = i915_mch_val(dev_priv); | |
1695 | chipset = i915_chipset_val(dev_priv); | |
1696 | gfx = i915_gfx_val(dev_priv); | |
de227ef0 | 1697 | mutex_unlock(&dev->struct_mutex); |
7648fa99 JB |
1698 | |
1699 | seq_printf(m, "GMCH temp: %ld\n", temp); | |
1700 | seq_printf(m, "Chipset power: %ld\n", chipset); | |
1701 | seq_printf(m, "GFX power: %ld\n", gfx); | |
1702 | seq_printf(m, "Total power: %ld\n", chipset + gfx); | |
1703 | ||
1704 | return 0; | |
1705 | } | |
1706 | ||
23b2f8bb JB |
1707 | static int i915_ring_freq_table(struct seq_file *m, void *unused) |
1708 | { | |
9f25d007 | 1709 | struct drm_info_node *node = m->private; |
23b2f8bb | 1710 | struct drm_device *dev = node->minor->dev; |
e277a1f8 | 1711 | struct drm_i915_private *dev_priv = dev->dev_private; |
5bfa0199 | 1712 | int ret = 0; |
23b2f8bb JB |
1713 | int gpu_freq, ia_freq; |
1714 | ||
1c70c0ce | 1715 | if (!(IS_GEN6(dev) || IS_GEN7(dev))) { |
267f0c90 | 1716 | seq_puts(m, "unsupported on this chipset\n"); |
23b2f8bb JB |
1717 | return 0; |
1718 | } | |
1719 | ||
5bfa0199 PZ |
1720 | intel_runtime_pm_get(dev_priv); |
1721 | ||
5c9669ce TR |
1722 | flush_delayed_work(&dev_priv->rps.delayed_resume_work); |
1723 | ||
4fc688ce | 1724 | ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock); |
23b2f8bb | 1725 | if (ret) |
5bfa0199 | 1726 | goto out; |
23b2f8bb | 1727 | |
267f0c90 | 1728 | seq_puts(m, "GPU freq (MHz)\tEffective CPU freq (MHz)\tEffective Ring freq (MHz)\n"); |
23b2f8bb | 1729 | |
b39fb297 BW |
1730 | for (gpu_freq = dev_priv->rps.min_freq_softlimit; |
1731 | gpu_freq <= dev_priv->rps.max_freq_softlimit; | |
23b2f8bb | 1732 | gpu_freq++) { |
42c0526c BW |
1733 | ia_freq = gpu_freq; |
1734 | sandybridge_pcode_read(dev_priv, | |
1735 | GEN6_PCODE_READ_MIN_FREQ_TABLE, | |
1736 | &ia_freq); | |
3ebecd07 | 1737 | seq_printf(m, "%d\t\t%d\t\t\t\t%d\n", |
7c59a9c1 | 1738 | intel_gpu_freq(dev_priv, gpu_freq), |
3ebecd07 CW |
1739 | ((ia_freq >> 0) & 0xff) * 100, |
1740 | ((ia_freq >> 8) & 0xff) * 100); | |
23b2f8bb JB |
1741 | } |
1742 | ||
4fc688ce | 1743 | mutex_unlock(&dev_priv->rps.hw_lock); |
23b2f8bb | 1744 | |
5bfa0199 PZ |
1745 | out: |
1746 | intel_runtime_pm_put(dev_priv); | |
1747 | return ret; | |
23b2f8bb JB |
1748 | } |
1749 | ||
44834a67 CW |
1750 | static int i915_opregion(struct seq_file *m, void *unused) |
1751 | { | |
9f25d007 | 1752 | struct drm_info_node *node = m->private; |
44834a67 | 1753 | struct drm_device *dev = node->minor->dev; |
e277a1f8 | 1754 | struct drm_i915_private *dev_priv = dev->dev_private; |
44834a67 | 1755 | struct intel_opregion *opregion = &dev_priv->opregion; |
0d38f009 | 1756 | void *data = kmalloc(OPREGION_SIZE, GFP_KERNEL); |
44834a67 CW |
1757 | int ret; |
1758 | ||
0d38f009 DV |
1759 | if (data == NULL) |
1760 | return -ENOMEM; | |
1761 | ||
44834a67 CW |
1762 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
1763 | if (ret) | |
0d38f009 | 1764 | goto out; |
44834a67 | 1765 | |
0d38f009 DV |
1766 | if (opregion->header) { |
1767 | memcpy_fromio(data, opregion->header, OPREGION_SIZE); | |
1768 | seq_write(m, data, OPREGION_SIZE); | |
1769 | } | |
44834a67 CW |
1770 | |
1771 | mutex_unlock(&dev->struct_mutex); | |
1772 | ||
0d38f009 DV |
1773 | out: |
1774 | kfree(data); | |
44834a67 CW |
1775 | return 0; |
1776 | } | |
1777 | ||
37811fcc CW |
1778 | static int i915_gem_framebuffer_info(struct seq_file *m, void *data) |
1779 | { | |
9f25d007 | 1780 | struct drm_info_node *node = m->private; |
37811fcc | 1781 | struct drm_device *dev = node->minor->dev; |
4520f53a | 1782 | struct intel_fbdev *ifbdev = NULL; |
37811fcc | 1783 | struct intel_framebuffer *fb; |
37811fcc | 1784 | |
4520f53a DV |
1785 | #ifdef CONFIG_DRM_I915_FBDEV |
1786 | struct drm_i915_private *dev_priv = dev->dev_private; | |
37811fcc CW |
1787 | |
1788 | ifbdev = dev_priv->fbdev; | |
1789 | fb = to_intel_framebuffer(ifbdev->helper.fb); | |
1790 | ||
c1ca506d | 1791 | seq_printf(m, "fbcon size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj ", |
37811fcc CW |
1792 | fb->base.width, |
1793 | fb->base.height, | |
1794 | fb->base.depth, | |
623f9783 | 1795 | fb->base.bits_per_pixel, |
c1ca506d | 1796 | fb->base.modifier[0], |
623f9783 | 1797 | atomic_read(&fb->base.refcount.refcount)); |
05394f39 | 1798 | describe_obj(m, fb->obj); |
267f0c90 | 1799 | seq_putc(m, '\n'); |
4520f53a | 1800 | #endif |
37811fcc | 1801 | |
4b096ac1 | 1802 | mutex_lock(&dev->mode_config.fb_lock); |
37811fcc | 1803 | list_for_each_entry(fb, &dev->mode_config.fb_list, base.head) { |
131a56dc | 1804 | if (ifbdev && &fb->base == ifbdev->helper.fb) |
37811fcc CW |
1805 | continue; |
1806 | ||
c1ca506d | 1807 | seq_printf(m, "user size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj ", |
37811fcc CW |
1808 | fb->base.width, |
1809 | fb->base.height, | |
1810 | fb->base.depth, | |
623f9783 | 1811 | fb->base.bits_per_pixel, |
c1ca506d | 1812 | fb->base.modifier[0], |
623f9783 | 1813 | atomic_read(&fb->base.refcount.refcount)); |
05394f39 | 1814 | describe_obj(m, fb->obj); |
267f0c90 | 1815 | seq_putc(m, '\n'); |
37811fcc | 1816 | } |
4b096ac1 | 1817 | mutex_unlock(&dev->mode_config.fb_lock); |
37811fcc CW |
1818 | |
1819 | return 0; | |
1820 | } | |
1821 | ||
c9fe99bd OM |
1822 | static void describe_ctx_ringbuf(struct seq_file *m, |
1823 | struct intel_ringbuffer *ringbuf) | |
1824 | { | |
1825 | seq_printf(m, " (ringbuffer, space: %d, head: %u, tail: %u, last head: %d)", | |
1826 | ringbuf->space, ringbuf->head, ringbuf->tail, | |
1827 | ringbuf->last_retired_head); | |
1828 | } | |
1829 | ||
e76d3630 BW |
1830 | static int i915_context_status(struct seq_file *m, void *unused) |
1831 | { | |
9f25d007 | 1832 | struct drm_info_node *node = m->private; |
e76d3630 | 1833 | struct drm_device *dev = node->minor->dev; |
e277a1f8 | 1834 | struct drm_i915_private *dev_priv = dev->dev_private; |
a4872ba6 | 1835 | struct intel_engine_cs *ring; |
273497e5 | 1836 | struct intel_context *ctx; |
a168c293 | 1837 | int ret, i; |
e76d3630 | 1838 | |
f3d28878 | 1839 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
e76d3630 BW |
1840 | if (ret) |
1841 | return ret; | |
1842 | ||
a33afea5 | 1843 | list_for_each_entry(ctx, &dev_priv->context_list, link) { |
c9fe99bd OM |
1844 | if (!i915.enable_execlists && |
1845 | ctx->legacy_hw_ctx.rcs_state == NULL) | |
b77f6997 CW |
1846 | continue; |
1847 | ||
a33afea5 | 1848 | seq_puts(m, "HW context "); |
3ccfd19d | 1849 | describe_ctx(m, ctx); |
c9fe99bd | 1850 | for_each_ring(ring, dev_priv, i) { |
a33afea5 | 1851 | if (ring->default_context == ctx) |
c9fe99bd OM |
1852 | seq_printf(m, "(default context %s) ", |
1853 | ring->name); | |
1854 | } | |
1855 | ||
1856 | if (i915.enable_execlists) { | |
1857 | seq_putc(m, '\n'); | |
1858 | for_each_ring(ring, dev_priv, i) { | |
1859 | struct drm_i915_gem_object *ctx_obj = | |
1860 | ctx->engine[i].state; | |
1861 | struct intel_ringbuffer *ringbuf = | |
1862 | ctx->engine[i].ringbuf; | |
1863 | ||
1864 | seq_printf(m, "%s: ", ring->name); | |
1865 | if (ctx_obj) | |
1866 | describe_obj(m, ctx_obj); | |
1867 | if (ringbuf) | |
1868 | describe_ctx_ringbuf(m, ringbuf); | |
1869 | seq_putc(m, '\n'); | |
1870 | } | |
1871 | } else { | |
1872 | describe_obj(m, ctx->legacy_hw_ctx.rcs_state); | |
1873 | } | |
a33afea5 | 1874 | |
a33afea5 | 1875 | seq_putc(m, '\n'); |
a168c293 BW |
1876 | } |
1877 | ||
f3d28878 | 1878 | mutex_unlock(&dev->struct_mutex); |
e76d3630 BW |
1879 | |
1880 | return 0; | |
1881 | } | |
1882 | ||
064ca1d2 TD |
1883 | static void i915_dump_lrc_obj(struct seq_file *m, |
1884 | struct intel_engine_cs *ring, | |
1885 | struct drm_i915_gem_object *ctx_obj) | |
1886 | { | |
1887 | struct page *page; | |
1888 | uint32_t *reg_state; | |
1889 | int j; | |
1890 | unsigned long ggtt_offset = 0; | |
1891 | ||
1892 | if (ctx_obj == NULL) { | |
1893 | seq_printf(m, "Context on %s with no gem object\n", | |
1894 | ring->name); | |
1895 | return; | |
1896 | } | |
1897 | ||
1898 | seq_printf(m, "CONTEXT: %s %u\n", ring->name, | |
1899 | intel_execlists_ctx_id(ctx_obj)); | |
1900 | ||
1901 | if (!i915_gem_obj_ggtt_bound(ctx_obj)) | |
1902 | seq_puts(m, "\tNot bound in GGTT\n"); | |
1903 | else | |
1904 | ggtt_offset = i915_gem_obj_ggtt_offset(ctx_obj); | |
1905 | ||
1906 | if (i915_gem_object_get_pages(ctx_obj)) { | |
1907 | seq_puts(m, "\tFailed to get pages for context object\n"); | |
1908 | return; | |
1909 | } | |
1910 | ||
1911 | page = i915_gem_object_get_page(ctx_obj, 1); | |
1912 | if (!WARN_ON(page == NULL)) { | |
1913 | reg_state = kmap_atomic(page); | |
1914 | ||
1915 | for (j = 0; j < 0x600 / sizeof(u32) / 4; j += 4) { | |
1916 | seq_printf(m, "\t[0x%08lx] 0x%08x 0x%08x 0x%08x 0x%08x\n", | |
1917 | ggtt_offset + 4096 + (j * 4), | |
1918 | reg_state[j], reg_state[j + 1], | |
1919 | reg_state[j + 2], reg_state[j + 3]); | |
1920 | } | |
1921 | kunmap_atomic(reg_state); | |
1922 | } | |
1923 | ||
1924 | seq_putc(m, '\n'); | |
1925 | } | |
1926 | ||
c0ab1ae9 BW |
1927 | static int i915_dump_lrc(struct seq_file *m, void *unused) |
1928 | { | |
1929 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1930 | struct drm_device *dev = node->minor->dev; | |
1931 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1932 | struct intel_engine_cs *ring; | |
1933 | struct intel_context *ctx; | |
1934 | int ret, i; | |
1935 | ||
1936 | if (!i915.enable_execlists) { | |
1937 | seq_printf(m, "Logical Ring Contexts are disabled\n"); | |
1938 | return 0; | |
1939 | } | |
1940 | ||
1941 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
1942 | if (ret) | |
1943 | return ret; | |
1944 | ||
1945 | list_for_each_entry(ctx, &dev_priv->context_list, link) { | |
1946 | for_each_ring(ring, dev_priv, i) { | |
064ca1d2 TD |
1947 | if (ring->default_context != ctx) |
1948 | i915_dump_lrc_obj(m, ring, | |
1949 | ctx->engine[i].state); | |
c0ab1ae9 BW |
1950 | } |
1951 | } | |
1952 | ||
1953 | mutex_unlock(&dev->struct_mutex); | |
1954 | ||
1955 | return 0; | |
1956 | } | |
1957 | ||
4ba70e44 OM |
1958 | static int i915_execlists(struct seq_file *m, void *data) |
1959 | { | |
1960 | struct drm_info_node *node = (struct drm_info_node *)m->private; | |
1961 | struct drm_device *dev = node->minor->dev; | |
1962 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1963 | struct intel_engine_cs *ring; | |
1964 | u32 status_pointer; | |
1965 | u8 read_pointer; | |
1966 | u8 write_pointer; | |
1967 | u32 status; | |
1968 | u32 ctx_id; | |
1969 | struct list_head *cursor; | |
1970 | int ring_id, i; | |
1971 | int ret; | |
1972 | ||
1973 | if (!i915.enable_execlists) { | |
1974 | seq_puts(m, "Logical Ring Contexts are disabled\n"); | |
1975 | return 0; | |
1976 | } | |
1977 | ||
1978 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
1979 | if (ret) | |
1980 | return ret; | |
1981 | ||
fc0412ec MT |
1982 | intel_runtime_pm_get(dev_priv); |
1983 | ||
4ba70e44 | 1984 | for_each_ring(ring, dev_priv, ring_id) { |
6d3d8274 | 1985 | struct drm_i915_gem_request *head_req = NULL; |
4ba70e44 OM |
1986 | int count = 0; |
1987 | unsigned long flags; | |
1988 | ||
1989 | seq_printf(m, "%s\n", ring->name); | |
1990 | ||
1991 | status = I915_READ(RING_EXECLIST_STATUS(ring)); | |
1992 | ctx_id = I915_READ(RING_EXECLIST_STATUS(ring) + 4); | |
1993 | seq_printf(m, "\tExeclist status: 0x%08X, context: %u\n", | |
1994 | status, ctx_id); | |
1995 | ||
1996 | status_pointer = I915_READ(RING_CONTEXT_STATUS_PTR(ring)); | |
1997 | seq_printf(m, "\tStatus pointer: 0x%08X\n", status_pointer); | |
1998 | ||
1999 | read_pointer = ring->next_context_status_buffer; | |
2000 | write_pointer = status_pointer & 0x07; | |
2001 | if (read_pointer > write_pointer) | |
2002 | write_pointer += 6; | |
2003 | seq_printf(m, "\tRead pointer: 0x%08X, write pointer 0x%08X\n", | |
2004 | read_pointer, write_pointer); | |
2005 | ||
2006 | for (i = 0; i < 6; i++) { | |
2007 | status = I915_READ(RING_CONTEXT_STATUS_BUF(ring) + 8*i); | |
2008 | ctx_id = I915_READ(RING_CONTEXT_STATUS_BUF(ring) + 8*i + 4); | |
2009 | ||
2010 | seq_printf(m, "\tStatus buffer %d: 0x%08X, context: %u\n", | |
2011 | i, status, ctx_id); | |
2012 | } | |
2013 | ||
2014 | spin_lock_irqsave(&ring->execlist_lock, flags); | |
2015 | list_for_each(cursor, &ring->execlist_queue) | |
2016 | count++; | |
2017 | head_req = list_first_entry_or_null(&ring->execlist_queue, | |
6d3d8274 | 2018 | struct drm_i915_gem_request, execlist_link); |
4ba70e44 OM |
2019 | spin_unlock_irqrestore(&ring->execlist_lock, flags); |
2020 | ||
2021 | seq_printf(m, "\t%d requests in queue\n", count); | |
2022 | if (head_req) { | |
2023 | struct drm_i915_gem_object *ctx_obj; | |
2024 | ||
6d3d8274 | 2025 | ctx_obj = head_req->ctx->engine[ring_id].state; |
4ba70e44 OM |
2026 | seq_printf(m, "\tHead request id: %u\n", |
2027 | intel_execlists_ctx_id(ctx_obj)); | |
2028 | seq_printf(m, "\tHead request tail: %u\n", | |
6d3d8274 | 2029 | head_req->tail); |
4ba70e44 OM |
2030 | } |
2031 | ||
2032 | seq_putc(m, '\n'); | |
2033 | } | |
2034 | ||
fc0412ec | 2035 | intel_runtime_pm_put(dev_priv); |
4ba70e44 OM |
2036 | mutex_unlock(&dev->struct_mutex); |
2037 | ||
2038 | return 0; | |
2039 | } | |
2040 | ||
ea16a3cd DV |
2041 | static const char *swizzle_string(unsigned swizzle) |
2042 | { | |
aee56cff | 2043 | switch (swizzle) { |
ea16a3cd DV |
2044 | case I915_BIT_6_SWIZZLE_NONE: |
2045 | return "none"; | |
2046 | case I915_BIT_6_SWIZZLE_9: | |
2047 | return "bit9"; | |
2048 | case I915_BIT_6_SWIZZLE_9_10: | |
2049 | return "bit9/bit10"; | |
2050 | case I915_BIT_6_SWIZZLE_9_11: | |
2051 | return "bit9/bit11"; | |
2052 | case I915_BIT_6_SWIZZLE_9_10_11: | |
2053 | return "bit9/bit10/bit11"; | |
2054 | case I915_BIT_6_SWIZZLE_9_17: | |
2055 | return "bit9/bit17"; | |
2056 | case I915_BIT_6_SWIZZLE_9_10_17: | |
2057 | return "bit9/bit10/bit17"; | |
2058 | case I915_BIT_6_SWIZZLE_UNKNOWN: | |
8a168ca7 | 2059 | return "unknown"; |
ea16a3cd DV |
2060 | } |
2061 | ||
2062 | return "bug"; | |
2063 | } | |
2064 | ||
2065 | static int i915_swizzle_info(struct seq_file *m, void *data) | |
2066 | { | |
9f25d007 | 2067 | struct drm_info_node *node = m->private; |
ea16a3cd DV |
2068 | struct drm_device *dev = node->minor->dev; |
2069 | struct drm_i915_private *dev_priv = dev->dev_private; | |
22bcfc6a DV |
2070 | int ret; |
2071 | ||
2072 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
2073 | if (ret) | |
2074 | return ret; | |
c8c8fb33 | 2075 | intel_runtime_pm_get(dev_priv); |
ea16a3cd | 2076 | |
ea16a3cd DV |
2077 | seq_printf(m, "bit6 swizzle for X-tiling = %s\n", |
2078 | swizzle_string(dev_priv->mm.bit_6_swizzle_x)); | |
2079 | seq_printf(m, "bit6 swizzle for Y-tiling = %s\n", | |
2080 | swizzle_string(dev_priv->mm.bit_6_swizzle_y)); | |
2081 | ||
2082 | if (IS_GEN3(dev) || IS_GEN4(dev)) { | |
2083 | seq_printf(m, "DDC = 0x%08x\n", | |
2084 | I915_READ(DCC)); | |
656bfa3a DV |
2085 | seq_printf(m, "DDC2 = 0x%08x\n", |
2086 | I915_READ(DCC2)); | |
ea16a3cd DV |
2087 | seq_printf(m, "C0DRB3 = 0x%04x\n", |
2088 | I915_READ16(C0DRB3)); | |
2089 | seq_printf(m, "C1DRB3 = 0x%04x\n", | |
2090 | I915_READ16(C1DRB3)); | |
9d3203e1 | 2091 | } else if (INTEL_INFO(dev)->gen >= 6) { |
3fa7d235 DV |
2092 | seq_printf(m, "MAD_DIMM_C0 = 0x%08x\n", |
2093 | I915_READ(MAD_DIMM_C0)); | |
2094 | seq_printf(m, "MAD_DIMM_C1 = 0x%08x\n", | |
2095 | I915_READ(MAD_DIMM_C1)); | |
2096 | seq_printf(m, "MAD_DIMM_C2 = 0x%08x\n", | |
2097 | I915_READ(MAD_DIMM_C2)); | |
2098 | seq_printf(m, "TILECTL = 0x%08x\n", | |
2099 | I915_READ(TILECTL)); | |
5907f5fb | 2100 | if (INTEL_INFO(dev)->gen >= 8) |
9d3203e1 BW |
2101 | seq_printf(m, "GAMTARBMODE = 0x%08x\n", |
2102 | I915_READ(GAMTARBMODE)); | |
2103 | else | |
2104 | seq_printf(m, "ARB_MODE = 0x%08x\n", | |
2105 | I915_READ(ARB_MODE)); | |
3fa7d235 DV |
2106 | seq_printf(m, "DISP_ARB_CTL = 0x%08x\n", |
2107 | I915_READ(DISP_ARB_CTL)); | |
ea16a3cd | 2108 | } |
656bfa3a DV |
2109 | |
2110 | if (dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES) | |
2111 | seq_puts(m, "L-shaped memory detected\n"); | |
2112 | ||
c8c8fb33 | 2113 | intel_runtime_pm_put(dev_priv); |
ea16a3cd DV |
2114 | mutex_unlock(&dev->struct_mutex); |
2115 | ||
2116 | return 0; | |
2117 | } | |
2118 | ||
1c60fef5 BW |
2119 | static int per_file_ctx(int id, void *ptr, void *data) |
2120 | { | |
273497e5 | 2121 | struct intel_context *ctx = ptr; |
1c60fef5 | 2122 | struct seq_file *m = data; |
ae6c4806 DV |
2123 | struct i915_hw_ppgtt *ppgtt = ctx->ppgtt; |
2124 | ||
2125 | if (!ppgtt) { | |
2126 | seq_printf(m, " no ppgtt for context %d\n", | |
2127 | ctx->user_handle); | |
2128 | return 0; | |
2129 | } | |
1c60fef5 | 2130 | |
f83d6518 OM |
2131 | if (i915_gem_context_is_default(ctx)) |
2132 | seq_puts(m, " default context:\n"); | |
2133 | else | |
821d66dd | 2134 | seq_printf(m, " context %d:\n", ctx->user_handle); |
1c60fef5 BW |
2135 | ppgtt->debug_dump(ppgtt, m); |
2136 | ||
2137 | return 0; | |
2138 | } | |
2139 | ||
77df6772 | 2140 | static void gen8_ppgtt_info(struct seq_file *m, struct drm_device *dev) |
3cf17fc5 | 2141 | { |
3cf17fc5 | 2142 | struct drm_i915_private *dev_priv = dev->dev_private; |
a4872ba6 | 2143 | struct intel_engine_cs *ring; |
77df6772 BW |
2144 | struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt; |
2145 | int unused, i; | |
3cf17fc5 | 2146 | |
77df6772 BW |
2147 | if (!ppgtt) |
2148 | return; | |
2149 | ||
2150 | seq_printf(m, "Page directories: %d\n", ppgtt->num_pd_pages); | |
5abbcca3 | 2151 | seq_printf(m, "Page tables: %d\n", ppgtt->num_pd_entries); |
77df6772 BW |
2152 | for_each_ring(ring, dev_priv, unused) { |
2153 | seq_printf(m, "%s\n", ring->name); | |
2154 | for (i = 0; i < 4; i++) { | |
2155 | u32 offset = 0x270 + i * 8; | |
2156 | u64 pdp = I915_READ(ring->mmio_base + offset + 4); | |
2157 | pdp <<= 32; | |
2158 | pdp |= I915_READ(ring->mmio_base + offset); | |
a2a5b15c | 2159 | seq_printf(m, "\tPDP%d 0x%016llx\n", i, pdp); |
77df6772 BW |
2160 | } |
2161 | } | |
2162 | } | |
2163 | ||
2164 | static void gen6_ppgtt_info(struct seq_file *m, struct drm_device *dev) | |
2165 | { | |
2166 | struct drm_i915_private *dev_priv = dev->dev_private; | |
a4872ba6 | 2167 | struct intel_engine_cs *ring; |
1c60fef5 | 2168 | struct drm_file *file; |
77df6772 | 2169 | int i; |
3cf17fc5 | 2170 | |
3cf17fc5 DV |
2171 | if (INTEL_INFO(dev)->gen == 6) |
2172 | seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(GFX_MODE)); | |
2173 | ||
a2c7f6fd | 2174 | for_each_ring(ring, dev_priv, i) { |
3cf17fc5 DV |
2175 | seq_printf(m, "%s\n", ring->name); |
2176 | if (INTEL_INFO(dev)->gen == 7) | |
2177 | seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(RING_MODE_GEN7(ring))); | |
2178 | seq_printf(m, "PP_DIR_BASE: 0x%08x\n", I915_READ(RING_PP_DIR_BASE(ring))); | |
2179 | seq_printf(m, "PP_DIR_BASE_READ: 0x%08x\n", I915_READ(RING_PP_DIR_BASE_READ(ring))); | |
2180 | seq_printf(m, "PP_DIR_DCLV: 0x%08x\n", I915_READ(RING_PP_DIR_DCLV(ring))); | |
2181 | } | |
2182 | if (dev_priv->mm.aliasing_ppgtt) { | |
2183 | struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt; | |
2184 | ||
267f0c90 | 2185 | seq_puts(m, "aliasing PPGTT:\n"); |
7324cc04 | 2186 | seq_printf(m, "pd gtt offset: 0x%08x\n", ppgtt->pd.pd_offset); |
1c60fef5 | 2187 | |
87d60b63 | 2188 | ppgtt->debug_dump(ppgtt, m); |
ae6c4806 | 2189 | } |
1c60fef5 BW |
2190 | |
2191 | list_for_each_entry_reverse(file, &dev->filelist, lhead) { | |
2192 | struct drm_i915_file_private *file_priv = file->driver_priv; | |
1c60fef5 | 2193 | |
1c60fef5 BW |
2194 | seq_printf(m, "proc: %s\n", |
2195 | get_pid_task(file->pid, PIDTYPE_PID)->comm); | |
1c60fef5 | 2196 | idr_for_each(&file_priv->context_idr, per_file_ctx, m); |
3cf17fc5 DV |
2197 | } |
2198 | seq_printf(m, "ECOCHK: 0x%08x\n", I915_READ(GAM_ECOCHK)); | |
77df6772 BW |
2199 | } |
2200 | ||
2201 | static int i915_ppgtt_info(struct seq_file *m, void *data) | |
2202 | { | |
9f25d007 | 2203 | struct drm_info_node *node = m->private; |
77df6772 | 2204 | struct drm_device *dev = node->minor->dev; |
c8c8fb33 | 2205 | struct drm_i915_private *dev_priv = dev->dev_private; |
77df6772 BW |
2206 | |
2207 | int ret = mutex_lock_interruptible(&dev->struct_mutex); | |
2208 | if (ret) | |
2209 | return ret; | |
c8c8fb33 | 2210 | intel_runtime_pm_get(dev_priv); |
77df6772 BW |
2211 | |
2212 | if (INTEL_INFO(dev)->gen >= 8) | |
2213 | gen8_ppgtt_info(m, dev); | |
2214 | else if (INTEL_INFO(dev)->gen >= 6) | |
2215 | gen6_ppgtt_info(m, dev); | |
2216 | ||
c8c8fb33 | 2217 | intel_runtime_pm_put(dev_priv); |
3cf17fc5 DV |
2218 | mutex_unlock(&dev->struct_mutex); |
2219 | ||
2220 | return 0; | |
2221 | } | |
2222 | ||
63573eb7 BW |
2223 | static int i915_llc(struct seq_file *m, void *data) |
2224 | { | |
9f25d007 | 2225 | struct drm_info_node *node = m->private; |
63573eb7 BW |
2226 | struct drm_device *dev = node->minor->dev; |
2227 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2228 | ||
2229 | /* Size calculation for LLC is a bit of a pain. Ignore for now. */ | |
2230 | seq_printf(m, "LLC: %s\n", yesno(HAS_LLC(dev))); | |
2231 | seq_printf(m, "eLLC: %zuMB\n", dev_priv->ellc_size); | |
2232 | ||
2233 | return 0; | |
2234 | } | |
2235 | ||
e91fd8c6 RV |
2236 | static int i915_edp_psr_status(struct seq_file *m, void *data) |
2237 | { | |
2238 | struct drm_info_node *node = m->private; | |
2239 | struct drm_device *dev = node->minor->dev; | |
2240 | struct drm_i915_private *dev_priv = dev->dev_private; | |
a031d709 | 2241 | u32 psrperf = 0; |
a6cbdb8e RV |
2242 | u32 stat[3]; |
2243 | enum pipe pipe; | |
a031d709 | 2244 | bool enabled = false; |
e91fd8c6 | 2245 | |
3553a8ea DL |
2246 | if (!HAS_PSR(dev)) { |
2247 | seq_puts(m, "PSR not supported\n"); | |
2248 | return 0; | |
2249 | } | |
2250 | ||
c8c8fb33 PZ |
2251 | intel_runtime_pm_get(dev_priv); |
2252 | ||
fa128fa6 | 2253 | mutex_lock(&dev_priv->psr.lock); |
a031d709 RV |
2254 | seq_printf(m, "Sink_Support: %s\n", yesno(dev_priv->psr.sink_support)); |
2255 | seq_printf(m, "Source_OK: %s\n", yesno(dev_priv->psr.source_ok)); | |
2807cf69 | 2256 | seq_printf(m, "Enabled: %s\n", yesno((bool)dev_priv->psr.enabled)); |
5755c78f | 2257 | seq_printf(m, "Active: %s\n", yesno(dev_priv->psr.active)); |
fa128fa6 DV |
2258 | seq_printf(m, "Busy frontbuffer bits: 0x%03x\n", |
2259 | dev_priv->psr.busy_frontbuffer_bits); | |
2260 | seq_printf(m, "Re-enable work scheduled: %s\n", | |
2261 | yesno(work_busy(&dev_priv->psr.work.work))); | |
e91fd8c6 | 2262 | |
3553a8ea DL |
2263 | if (HAS_DDI(dev)) |
2264 | enabled = I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE; | |
2265 | else { | |
2266 | for_each_pipe(dev_priv, pipe) { | |
2267 | stat[pipe] = I915_READ(VLV_PSRSTAT(pipe)) & | |
2268 | VLV_EDP_PSR_CURR_STATE_MASK; | |
2269 | if ((stat[pipe] == VLV_EDP_PSR_ACTIVE_NORFB_UP) || | |
2270 | (stat[pipe] == VLV_EDP_PSR_ACTIVE_SF_UPDATE)) | |
2271 | enabled = true; | |
a6cbdb8e RV |
2272 | } |
2273 | } | |
2274 | seq_printf(m, "HW Enabled & Active bit: %s", yesno(enabled)); | |
2275 | ||
2276 | if (!HAS_DDI(dev)) | |
2277 | for_each_pipe(dev_priv, pipe) { | |
2278 | if ((stat[pipe] == VLV_EDP_PSR_ACTIVE_NORFB_UP) || | |
2279 | (stat[pipe] == VLV_EDP_PSR_ACTIVE_SF_UPDATE)) | |
2280 | seq_printf(m, " pipe %c", pipe_name(pipe)); | |
2281 | } | |
2282 | seq_puts(m, "\n"); | |
e91fd8c6 | 2283 | |
fb495814 RV |
2284 | seq_printf(m, "Link standby: %s\n", |
2285 | yesno((bool)dev_priv->psr.link_standby)); | |
2286 | ||
a6cbdb8e | 2287 | /* CHV PSR has no kind of performance counter */ |
3553a8ea | 2288 | if (HAS_DDI(dev)) { |
a031d709 RV |
2289 | psrperf = I915_READ(EDP_PSR_PERF_CNT(dev)) & |
2290 | EDP_PSR_PERF_CNT_MASK; | |
a6cbdb8e RV |
2291 | |
2292 | seq_printf(m, "Performance_Counter: %u\n", psrperf); | |
2293 | } | |
fa128fa6 | 2294 | mutex_unlock(&dev_priv->psr.lock); |
e91fd8c6 | 2295 | |
c8c8fb33 | 2296 | intel_runtime_pm_put(dev_priv); |
e91fd8c6 RV |
2297 | return 0; |
2298 | } | |
2299 | ||
d2e216d0 RV |
2300 | static int i915_sink_crc(struct seq_file *m, void *data) |
2301 | { | |
2302 | struct drm_info_node *node = m->private; | |
2303 | struct drm_device *dev = node->minor->dev; | |
2304 | struct intel_encoder *encoder; | |
2305 | struct intel_connector *connector; | |
2306 | struct intel_dp *intel_dp = NULL; | |
2307 | int ret; | |
2308 | u8 crc[6]; | |
2309 | ||
2310 | drm_modeset_lock_all(dev); | |
aca5e361 | 2311 | for_each_intel_connector(dev, connector) { |
d2e216d0 RV |
2312 | |
2313 | if (connector->base.dpms != DRM_MODE_DPMS_ON) | |
2314 | continue; | |
2315 | ||
b6ae3c7c PZ |
2316 | if (!connector->base.encoder) |
2317 | continue; | |
2318 | ||
d2e216d0 RV |
2319 | encoder = to_intel_encoder(connector->base.encoder); |
2320 | if (encoder->type != INTEL_OUTPUT_EDP) | |
2321 | continue; | |
2322 | ||
2323 | intel_dp = enc_to_intel_dp(&encoder->base); | |
2324 | ||
2325 | ret = intel_dp_sink_crc(intel_dp, crc); | |
2326 | if (ret) | |
2327 | goto out; | |
2328 | ||
2329 | seq_printf(m, "%02x%02x%02x%02x%02x%02x\n", | |
2330 | crc[0], crc[1], crc[2], | |
2331 | crc[3], crc[4], crc[5]); | |
2332 | goto out; | |
2333 | } | |
2334 | ret = -ENODEV; | |
2335 | out: | |
2336 | drm_modeset_unlock_all(dev); | |
2337 | return ret; | |
2338 | } | |
2339 | ||
ec013e7f JB |
2340 | static int i915_energy_uJ(struct seq_file *m, void *data) |
2341 | { | |
2342 | struct drm_info_node *node = m->private; | |
2343 | struct drm_device *dev = node->minor->dev; | |
2344 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2345 | u64 power; | |
2346 | u32 units; | |
2347 | ||
2348 | if (INTEL_INFO(dev)->gen < 6) | |
2349 | return -ENODEV; | |
2350 | ||
36623ef8 PZ |
2351 | intel_runtime_pm_get(dev_priv); |
2352 | ||
ec013e7f JB |
2353 | rdmsrl(MSR_RAPL_POWER_UNIT, power); |
2354 | power = (power & 0x1f00) >> 8; | |
2355 | units = 1000000 / (1 << power); /* convert to uJ */ | |
2356 | power = I915_READ(MCH_SECP_NRG_STTS); | |
2357 | power *= units; | |
2358 | ||
36623ef8 PZ |
2359 | intel_runtime_pm_put(dev_priv); |
2360 | ||
ec013e7f | 2361 | seq_printf(m, "%llu", (long long unsigned)power); |
371db66a PZ |
2362 | |
2363 | return 0; | |
2364 | } | |
2365 | ||
2366 | static int i915_pc8_status(struct seq_file *m, void *unused) | |
2367 | { | |
9f25d007 | 2368 | struct drm_info_node *node = m->private; |
371db66a PZ |
2369 | struct drm_device *dev = node->minor->dev; |
2370 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2371 | ||
85b8d5c2 | 2372 | if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) { |
371db66a PZ |
2373 | seq_puts(m, "not supported\n"); |
2374 | return 0; | |
2375 | } | |
2376 | ||
86c4ec0d | 2377 | seq_printf(m, "GPU idle: %s\n", yesno(!dev_priv->mm.busy)); |
371db66a | 2378 | seq_printf(m, "IRQs disabled: %s\n", |
9df7575f | 2379 | yesno(!intel_irqs_enabled(dev_priv))); |
371db66a | 2380 | |
ec013e7f JB |
2381 | return 0; |
2382 | } | |
2383 | ||
1da51581 ID |
2384 | static const char *power_domain_str(enum intel_display_power_domain domain) |
2385 | { | |
2386 | switch (domain) { | |
2387 | case POWER_DOMAIN_PIPE_A: | |
2388 | return "PIPE_A"; | |
2389 | case POWER_DOMAIN_PIPE_B: | |
2390 | return "PIPE_B"; | |
2391 | case POWER_DOMAIN_PIPE_C: | |
2392 | return "PIPE_C"; | |
2393 | case POWER_DOMAIN_PIPE_A_PANEL_FITTER: | |
2394 | return "PIPE_A_PANEL_FITTER"; | |
2395 | case POWER_DOMAIN_PIPE_B_PANEL_FITTER: | |
2396 | return "PIPE_B_PANEL_FITTER"; | |
2397 | case POWER_DOMAIN_PIPE_C_PANEL_FITTER: | |
2398 | return "PIPE_C_PANEL_FITTER"; | |
2399 | case POWER_DOMAIN_TRANSCODER_A: | |
2400 | return "TRANSCODER_A"; | |
2401 | case POWER_DOMAIN_TRANSCODER_B: | |
2402 | return "TRANSCODER_B"; | |
2403 | case POWER_DOMAIN_TRANSCODER_C: | |
2404 | return "TRANSCODER_C"; | |
2405 | case POWER_DOMAIN_TRANSCODER_EDP: | |
2406 | return "TRANSCODER_EDP"; | |
319be8ae ID |
2407 | case POWER_DOMAIN_PORT_DDI_A_2_LANES: |
2408 | return "PORT_DDI_A_2_LANES"; | |
2409 | case POWER_DOMAIN_PORT_DDI_A_4_LANES: | |
2410 | return "PORT_DDI_A_4_LANES"; | |
2411 | case POWER_DOMAIN_PORT_DDI_B_2_LANES: | |
2412 | return "PORT_DDI_B_2_LANES"; | |
2413 | case POWER_DOMAIN_PORT_DDI_B_4_LANES: | |
2414 | return "PORT_DDI_B_4_LANES"; | |
2415 | case POWER_DOMAIN_PORT_DDI_C_2_LANES: | |
2416 | return "PORT_DDI_C_2_LANES"; | |
2417 | case POWER_DOMAIN_PORT_DDI_C_4_LANES: | |
2418 | return "PORT_DDI_C_4_LANES"; | |
2419 | case POWER_DOMAIN_PORT_DDI_D_2_LANES: | |
2420 | return "PORT_DDI_D_2_LANES"; | |
2421 | case POWER_DOMAIN_PORT_DDI_D_4_LANES: | |
2422 | return "PORT_DDI_D_4_LANES"; | |
2423 | case POWER_DOMAIN_PORT_DSI: | |
2424 | return "PORT_DSI"; | |
2425 | case POWER_DOMAIN_PORT_CRT: | |
2426 | return "PORT_CRT"; | |
2427 | case POWER_DOMAIN_PORT_OTHER: | |
2428 | return "PORT_OTHER"; | |
1da51581 ID |
2429 | case POWER_DOMAIN_VGA: |
2430 | return "VGA"; | |
2431 | case POWER_DOMAIN_AUDIO: | |
2432 | return "AUDIO"; | |
bd2bb1b9 PZ |
2433 | case POWER_DOMAIN_PLLS: |
2434 | return "PLLS"; | |
1407121a S |
2435 | case POWER_DOMAIN_AUX_A: |
2436 | return "AUX_A"; | |
2437 | case POWER_DOMAIN_AUX_B: | |
2438 | return "AUX_B"; | |
2439 | case POWER_DOMAIN_AUX_C: | |
2440 | return "AUX_C"; | |
2441 | case POWER_DOMAIN_AUX_D: | |
2442 | return "AUX_D"; | |
1da51581 ID |
2443 | case POWER_DOMAIN_INIT: |
2444 | return "INIT"; | |
2445 | default: | |
5f77eeb0 | 2446 | MISSING_CASE(domain); |
1da51581 ID |
2447 | return "?"; |
2448 | } | |
2449 | } | |
2450 | ||
2451 | static int i915_power_domain_info(struct seq_file *m, void *unused) | |
2452 | { | |
9f25d007 | 2453 | struct drm_info_node *node = m->private; |
1da51581 ID |
2454 | struct drm_device *dev = node->minor->dev; |
2455 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2456 | struct i915_power_domains *power_domains = &dev_priv->power_domains; | |
2457 | int i; | |
2458 | ||
2459 | mutex_lock(&power_domains->lock); | |
2460 | ||
2461 | seq_printf(m, "%-25s %s\n", "Power well/domain", "Use count"); | |
2462 | for (i = 0; i < power_domains->power_well_count; i++) { | |
2463 | struct i915_power_well *power_well; | |
2464 | enum intel_display_power_domain power_domain; | |
2465 | ||
2466 | power_well = &power_domains->power_wells[i]; | |
2467 | seq_printf(m, "%-25s %d\n", power_well->name, | |
2468 | power_well->count); | |
2469 | ||
2470 | for (power_domain = 0; power_domain < POWER_DOMAIN_NUM; | |
2471 | power_domain++) { | |
2472 | if (!(BIT(power_domain) & power_well->domains)) | |
2473 | continue; | |
2474 | ||
2475 | seq_printf(m, " %-23s %d\n", | |
2476 | power_domain_str(power_domain), | |
2477 | power_domains->domain_use_count[power_domain]); | |
2478 | } | |
2479 | } | |
2480 | ||
2481 | mutex_unlock(&power_domains->lock); | |
2482 | ||
2483 | return 0; | |
2484 | } | |
2485 | ||
53f5e3ca JB |
2486 | static void intel_seq_print_mode(struct seq_file *m, int tabs, |
2487 | struct drm_display_mode *mode) | |
2488 | { | |
2489 | int i; | |
2490 | ||
2491 | for (i = 0; i < tabs; i++) | |
2492 | seq_putc(m, '\t'); | |
2493 | ||
2494 | seq_printf(m, "id %d:\"%s\" freq %d clock %d hdisp %d hss %d hse %d htot %d vdisp %d vss %d vse %d vtot %d type 0x%x flags 0x%x\n", | |
2495 | mode->base.id, mode->name, | |
2496 | mode->vrefresh, mode->clock, | |
2497 | mode->hdisplay, mode->hsync_start, | |
2498 | mode->hsync_end, mode->htotal, | |
2499 | mode->vdisplay, mode->vsync_start, | |
2500 | mode->vsync_end, mode->vtotal, | |
2501 | mode->type, mode->flags); | |
2502 | } | |
2503 | ||
2504 | static void intel_encoder_info(struct seq_file *m, | |
2505 | struct intel_crtc *intel_crtc, | |
2506 | struct intel_encoder *intel_encoder) | |
2507 | { | |
9f25d007 | 2508 | struct drm_info_node *node = m->private; |
53f5e3ca JB |
2509 | struct drm_device *dev = node->minor->dev; |
2510 | struct drm_crtc *crtc = &intel_crtc->base; | |
2511 | struct intel_connector *intel_connector; | |
2512 | struct drm_encoder *encoder; | |
2513 | ||
2514 | encoder = &intel_encoder->base; | |
2515 | seq_printf(m, "\tencoder %d: type: %s, connectors:\n", | |
8e329a03 | 2516 | encoder->base.id, encoder->name); |
53f5e3ca JB |
2517 | for_each_connector_on_encoder(dev, encoder, intel_connector) { |
2518 | struct drm_connector *connector = &intel_connector->base; | |
2519 | seq_printf(m, "\t\tconnector %d: type: %s, status: %s", | |
2520 | connector->base.id, | |
c23cc417 | 2521 | connector->name, |
53f5e3ca JB |
2522 | drm_get_connector_status_name(connector->status)); |
2523 | if (connector->status == connector_status_connected) { | |
2524 | struct drm_display_mode *mode = &crtc->mode; | |
2525 | seq_printf(m, ", mode:\n"); | |
2526 | intel_seq_print_mode(m, 2, mode); | |
2527 | } else { | |
2528 | seq_putc(m, '\n'); | |
2529 | } | |
2530 | } | |
2531 | } | |
2532 | ||
2533 | static void intel_crtc_info(struct seq_file *m, struct intel_crtc *intel_crtc) | |
2534 | { | |
9f25d007 | 2535 | struct drm_info_node *node = m->private; |
53f5e3ca JB |
2536 | struct drm_device *dev = node->minor->dev; |
2537 | struct drm_crtc *crtc = &intel_crtc->base; | |
2538 | struct intel_encoder *intel_encoder; | |
2539 | ||
5aa8a937 MR |
2540 | if (crtc->primary->fb) |
2541 | seq_printf(m, "\tfb: %d, pos: %dx%d, size: %dx%d\n", | |
2542 | crtc->primary->fb->base.id, crtc->x, crtc->y, | |
2543 | crtc->primary->fb->width, crtc->primary->fb->height); | |
2544 | else | |
2545 | seq_puts(m, "\tprimary plane disabled\n"); | |
53f5e3ca JB |
2546 | for_each_encoder_on_crtc(dev, crtc, intel_encoder) |
2547 | intel_encoder_info(m, intel_crtc, intel_encoder); | |
2548 | } | |
2549 | ||
2550 | static void intel_panel_info(struct seq_file *m, struct intel_panel *panel) | |
2551 | { | |
2552 | struct drm_display_mode *mode = panel->fixed_mode; | |
2553 | ||
2554 | seq_printf(m, "\tfixed mode:\n"); | |
2555 | intel_seq_print_mode(m, 2, mode); | |
2556 | } | |
2557 | ||
2558 | static void intel_dp_info(struct seq_file *m, | |
2559 | struct intel_connector *intel_connector) | |
2560 | { | |
2561 | struct intel_encoder *intel_encoder = intel_connector->encoder; | |
2562 | struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base); | |
2563 | ||
2564 | seq_printf(m, "\tDPCD rev: %x\n", intel_dp->dpcd[DP_DPCD_REV]); | |
2565 | seq_printf(m, "\taudio support: %s\n", intel_dp->has_audio ? "yes" : | |
2566 | "no"); | |
2567 | if (intel_encoder->type == INTEL_OUTPUT_EDP) | |
2568 | intel_panel_info(m, &intel_connector->panel); | |
2569 | } | |
2570 | ||
2571 | static void intel_hdmi_info(struct seq_file *m, | |
2572 | struct intel_connector *intel_connector) | |
2573 | { | |
2574 | struct intel_encoder *intel_encoder = intel_connector->encoder; | |
2575 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&intel_encoder->base); | |
2576 | ||
2577 | seq_printf(m, "\taudio support: %s\n", intel_hdmi->has_audio ? "yes" : | |
2578 | "no"); | |
2579 | } | |
2580 | ||
2581 | static void intel_lvds_info(struct seq_file *m, | |
2582 | struct intel_connector *intel_connector) | |
2583 | { | |
2584 | intel_panel_info(m, &intel_connector->panel); | |
2585 | } | |
2586 | ||
2587 | static void intel_connector_info(struct seq_file *m, | |
2588 | struct drm_connector *connector) | |
2589 | { | |
2590 | struct intel_connector *intel_connector = to_intel_connector(connector); | |
2591 | struct intel_encoder *intel_encoder = intel_connector->encoder; | |
f103fc7d | 2592 | struct drm_display_mode *mode; |
53f5e3ca JB |
2593 | |
2594 | seq_printf(m, "connector %d: type %s, status: %s\n", | |
c23cc417 | 2595 | connector->base.id, connector->name, |
53f5e3ca JB |
2596 | drm_get_connector_status_name(connector->status)); |
2597 | if (connector->status == connector_status_connected) { | |
2598 | seq_printf(m, "\tname: %s\n", connector->display_info.name); | |
2599 | seq_printf(m, "\tphysical dimensions: %dx%dmm\n", | |
2600 | connector->display_info.width_mm, | |
2601 | connector->display_info.height_mm); | |
2602 | seq_printf(m, "\tsubpixel order: %s\n", | |
2603 | drm_get_subpixel_order_name(connector->display_info.subpixel_order)); | |
2604 | seq_printf(m, "\tCEA rev: %d\n", | |
2605 | connector->display_info.cea_rev); | |
2606 | } | |
36cd7444 DA |
2607 | if (intel_encoder) { |
2608 | if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT || | |
2609 | intel_encoder->type == INTEL_OUTPUT_EDP) | |
2610 | intel_dp_info(m, intel_connector); | |
2611 | else if (intel_encoder->type == INTEL_OUTPUT_HDMI) | |
2612 | intel_hdmi_info(m, intel_connector); | |
2613 | else if (intel_encoder->type == INTEL_OUTPUT_LVDS) | |
2614 | intel_lvds_info(m, intel_connector); | |
2615 | } | |
53f5e3ca | 2616 | |
f103fc7d JB |
2617 | seq_printf(m, "\tmodes:\n"); |
2618 | list_for_each_entry(mode, &connector->modes, head) | |
2619 | intel_seq_print_mode(m, 2, mode); | |
53f5e3ca JB |
2620 | } |
2621 | ||
065f2ec2 CW |
2622 | static bool cursor_active(struct drm_device *dev, int pipe) |
2623 | { | |
2624 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2625 | u32 state; | |
2626 | ||
2627 | if (IS_845G(dev) || IS_I865G(dev)) | |
2628 | state = I915_READ(_CURACNTR) & CURSOR_ENABLE; | |
065f2ec2 | 2629 | else |
5efb3e28 | 2630 | state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE; |
065f2ec2 CW |
2631 | |
2632 | return state; | |
2633 | } | |
2634 | ||
2635 | static bool cursor_position(struct drm_device *dev, int pipe, int *x, int *y) | |
2636 | { | |
2637 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2638 | u32 pos; | |
2639 | ||
5efb3e28 | 2640 | pos = I915_READ(CURPOS(pipe)); |
065f2ec2 CW |
2641 | |
2642 | *x = (pos >> CURSOR_X_SHIFT) & CURSOR_POS_MASK; | |
2643 | if (pos & (CURSOR_POS_SIGN << CURSOR_X_SHIFT)) | |
2644 | *x = -*x; | |
2645 | ||
2646 | *y = (pos >> CURSOR_Y_SHIFT) & CURSOR_POS_MASK; | |
2647 | if (pos & (CURSOR_POS_SIGN << CURSOR_Y_SHIFT)) | |
2648 | *y = -*y; | |
2649 | ||
2650 | return cursor_active(dev, pipe); | |
2651 | } | |
2652 | ||
53f5e3ca JB |
2653 | static int i915_display_info(struct seq_file *m, void *unused) |
2654 | { | |
9f25d007 | 2655 | struct drm_info_node *node = m->private; |
53f5e3ca | 2656 | struct drm_device *dev = node->minor->dev; |
b0e5ddf3 | 2657 | struct drm_i915_private *dev_priv = dev->dev_private; |
065f2ec2 | 2658 | struct intel_crtc *crtc; |
53f5e3ca JB |
2659 | struct drm_connector *connector; |
2660 | ||
b0e5ddf3 | 2661 | intel_runtime_pm_get(dev_priv); |
53f5e3ca JB |
2662 | drm_modeset_lock_all(dev); |
2663 | seq_printf(m, "CRTC info\n"); | |
2664 | seq_printf(m, "---------\n"); | |
d3fcc808 | 2665 | for_each_intel_crtc(dev, crtc) { |
065f2ec2 CW |
2666 | bool active; |
2667 | int x, y; | |
53f5e3ca | 2668 | |
57127efa | 2669 | seq_printf(m, "CRTC %d: pipe: %c, active=%s (size=%dx%d)\n", |
065f2ec2 | 2670 | crtc->base.base.id, pipe_name(crtc->pipe), |
6e3c9717 ACO |
2671 | yesno(crtc->active), crtc->config->pipe_src_w, |
2672 | crtc->config->pipe_src_h); | |
a23dc658 | 2673 | if (crtc->active) { |
065f2ec2 CW |
2674 | intel_crtc_info(m, crtc); |
2675 | ||
a23dc658 | 2676 | active = cursor_position(dev, crtc->pipe, &x, &y); |
57127efa | 2677 | seq_printf(m, "\tcursor visible? %s, position (%d, %d), size %dx%d, addr 0x%08x, active? %s\n", |
4b0e333e | 2678 | yesno(crtc->cursor_base), |
3dd512fb MR |
2679 | x, y, crtc->base.cursor->state->crtc_w, |
2680 | crtc->base.cursor->state->crtc_h, | |
57127efa | 2681 | crtc->cursor_addr, yesno(active)); |
a23dc658 | 2682 | } |
cace841c DV |
2683 | |
2684 | seq_printf(m, "\tunderrun reporting: cpu=%s pch=%s \n", | |
2685 | yesno(!crtc->cpu_fifo_underrun_disabled), | |
2686 | yesno(!crtc->pch_fifo_underrun_disabled)); | |
53f5e3ca JB |
2687 | } |
2688 | ||
2689 | seq_printf(m, "\n"); | |
2690 | seq_printf(m, "Connector info\n"); | |
2691 | seq_printf(m, "--------------\n"); | |
2692 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { | |
2693 | intel_connector_info(m, connector); | |
2694 | } | |
2695 | drm_modeset_unlock_all(dev); | |
b0e5ddf3 | 2696 | intel_runtime_pm_put(dev_priv); |
53f5e3ca JB |
2697 | |
2698 | return 0; | |
2699 | } | |
2700 | ||
e04934cf BW |
2701 | static int i915_semaphore_status(struct seq_file *m, void *unused) |
2702 | { | |
2703 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
2704 | struct drm_device *dev = node->minor->dev; | |
2705 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2706 | struct intel_engine_cs *ring; | |
2707 | int num_rings = hweight32(INTEL_INFO(dev)->ring_mask); | |
2708 | int i, j, ret; | |
2709 | ||
2710 | if (!i915_semaphore_is_enabled(dev)) { | |
2711 | seq_puts(m, "Semaphores are disabled\n"); | |
2712 | return 0; | |
2713 | } | |
2714 | ||
2715 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
2716 | if (ret) | |
2717 | return ret; | |
03872064 | 2718 | intel_runtime_pm_get(dev_priv); |
e04934cf BW |
2719 | |
2720 | if (IS_BROADWELL(dev)) { | |
2721 | struct page *page; | |
2722 | uint64_t *seqno; | |
2723 | ||
2724 | page = i915_gem_object_get_page(dev_priv->semaphore_obj, 0); | |
2725 | ||
2726 | seqno = (uint64_t *)kmap_atomic(page); | |
2727 | for_each_ring(ring, dev_priv, i) { | |
2728 | uint64_t offset; | |
2729 | ||
2730 | seq_printf(m, "%s\n", ring->name); | |
2731 | ||
2732 | seq_puts(m, " Last signal:"); | |
2733 | for (j = 0; j < num_rings; j++) { | |
2734 | offset = i * I915_NUM_RINGS + j; | |
2735 | seq_printf(m, "0x%08llx (0x%02llx) ", | |
2736 | seqno[offset], offset * 8); | |
2737 | } | |
2738 | seq_putc(m, '\n'); | |
2739 | ||
2740 | seq_puts(m, " Last wait: "); | |
2741 | for (j = 0; j < num_rings; j++) { | |
2742 | offset = i + (j * I915_NUM_RINGS); | |
2743 | seq_printf(m, "0x%08llx (0x%02llx) ", | |
2744 | seqno[offset], offset * 8); | |
2745 | } | |
2746 | seq_putc(m, '\n'); | |
2747 | ||
2748 | } | |
2749 | kunmap_atomic(seqno); | |
2750 | } else { | |
2751 | seq_puts(m, " Last signal:"); | |
2752 | for_each_ring(ring, dev_priv, i) | |
2753 | for (j = 0; j < num_rings; j++) | |
2754 | seq_printf(m, "0x%08x\n", | |
2755 | I915_READ(ring->semaphore.mbox.signal[j])); | |
2756 | seq_putc(m, '\n'); | |
2757 | } | |
2758 | ||
2759 | seq_puts(m, "\nSync seqno:\n"); | |
2760 | for_each_ring(ring, dev_priv, i) { | |
2761 | for (j = 0; j < num_rings; j++) { | |
2762 | seq_printf(m, " 0x%08x ", ring->semaphore.sync_seqno[j]); | |
2763 | } | |
2764 | seq_putc(m, '\n'); | |
2765 | } | |
2766 | seq_putc(m, '\n'); | |
2767 | ||
03872064 | 2768 | intel_runtime_pm_put(dev_priv); |
e04934cf BW |
2769 | mutex_unlock(&dev->struct_mutex); |
2770 | return 0; | |
2771 | } | |
2772 | ||
728e29d7 DV |
2773 | static int i915_shared_dplls_info(struct seq_file *m, void *unused) |
2774 | { | |
2775 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
2776 | struct drm_device *dev = node->minor->dev; | |
2777 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2778 | int i; | |
2779 | ||
2780 | drm_modeset_lock_all(dev); | |
2781 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { | |
2782 | struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; | |
2783 | ||
2784 | seq_printf(m, "DPLL%i: %s, id: %i\n", i, pll->name, pll->id); | |
1e6f2ddc | 2785 | seq_printf(m, " crtc_mask: 0x%08x, active: %d, on: %s\n", |
3e369b76 | 2786 | pll->config.crtc_mask, pll->active, yesno(pll->on)); |
728e29d7 | 2787 | seq_printf(m, " tracked hardware state:\n"); |
3e369b76 ACO |
2788 | seq_printf(m, " dpll: 0x%08x\n", pll->config.hw_state.dpll); |
2789 | seq_printf(m, " dpll_md: 0x%08x\n", | |
2790 | pll->config.hw_state.dpll_md); | |
2791 | seq_printf(m, " fp0: 0x%08x\n", pll->config.hw_state.fp0); | |
2792 | seq_printf(m, " fp1: 0x%08x\n", pll->config.hw_state.fp1); | |
2793 | seq_printf(m, " wrpll: 0x%08x\n", pll->config.hw_state.wrpll); | |
728e29d7 DV |
2794 | } |
2795 | drm_modeset_unlock_all(dev); | |
2796 | ||
2797 | return 0; | |
2798 | } | |
2799 | ||
1ed1ef9d | 2800 | static int i915_wa_registers(struct seq_file *m, void *unused) |
888b5995 AS |
2801 | { |
2802 | int i; | |
2803 | int ret; | |
2804 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
2805 | struct drm_device *dev = node->minor->dev; | |
2806 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2807 | ||
888b5995 AS |
2808 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
2809 | if (ret) | |
2810 | return ret; | |
2811 | ||
2812 | intel_runtime_pm_get(dev_priv); | |
2813 | ||
7225342a MK |
2814 | seq_printf(m, "Workarounds applied: %d\n", dev_priv->workarounds.count); |
2815 | for (i = 0; i < dev_priv->workarounds.count; ++i) { | |
2fa60f6d MK |
2816 | u32 addr, mask, value, read; |
2817 | bool ok; | |
888b5995 | 2818 | |
7225342a MK |
2819 | addr = dev_priv->workarounds.reg[i].addr; |
2820 | mask = dev_priv->workarounds.reg[i].mask; | |
2fa60f6d MK |
2821 | value = dev_priv->workarounds.reg[i].value; |
2822 | read = I915_READ(addr); | |
2823 | ok = (value & mask) == (read & mask); | |
2824 | seq_printf(m, "0x%X: 0x%08X, mask: 0x%08X, read: 0x%08x, status: %s\n", | |
2825 | addr, value, mask, read, ok ? "OK" : "FAIL"); | |
888b5995 AS |
2826 | } |
2827 | ||
2828 | intel_runtime_pm_put(dev_priv); | |
2829 | mutex_unlock(&dev->struct_mutex); | |
2830 | ||
2831 | return 0; | |
2832 | } | |
2833 | ||
c5511e44 DL |
2834 | static int i915_ddb_info(struct seq_file *m, void *unused) |
2835 | { | |
2836 | struct drm_info_node *node = m->private; | |
2837 | struct drm_device *dev = node->minor->dev; | |
2838 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2839 | struct skl_ddb_allocation *ddb; | |
2840 | struct skl_ddb_entry *entry; | |
2841 | enum pipe pipe; | |
2842 | int plane; | |
2843 | ||
2fcffe19 DL |
2844 | if (INTEL_INFO(dev)->gen < 9) |
2845 | return 0; | |
2846 | ||
c5511e44 DL |
2847 | drm_modeset_lock_all(dev); |
2848 | ||
2849 | ddb = &dev_priv->wm.skl_hw.ddb; | |
2850 | ||
2851 | seq_printf(m, "%-15s%8s%8s%8s\n", "", "Start", "End", "Size"); | |
2852 | ||
2853 | for_each_pipe(dev_priv, pipe) { | |
2854 | seq_printf(m, "Pipe %c\n", pipe_name(pipe)); | |
2855 | ||
dd740780 | 2856 | for_each_plane(dev_priv, pipe, plane) { |
c5511e44 DL |
2857 | entry = &ddb->plane[pipe][plane]; |
2858 | seq_printf(m, " Plane%-8d%8u%8u%8u\n", plane + 1, | |
2859 | entry->start, entry->end, | |
2860 | skl_ddb_entry_size(entry)); | |
2861 | } | |
2862 | ||
2863 | entry = &ddb->cursor[pipe]; | |
2864 | seq_printf(m, " %-13s%8u%8u%8u\n", "Cursor", entry->start, | |
2865 | entry->end, skl_ddb_entry_size(entry)); | |
2866 | } | |
2867 | ||
2868 | drm_modeset_unlock_all(dev); | |
2869 | ||
2870 | return 0; | |
2871 | } | |
2872 | ||
a54746e3 VK |
2873 | static void drrs_status_per_crtc(struct seq_file *m, |
2874 | struct drm_device *dev, struct intel_crtc *intel_crtc) | |
2875 | { | |
2876 | struct intel_encoder *intel_encoder; | |
2877 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2878 | struct i915_drrs *drrs = &dev_priv->drrs; | |
2879 | int vrefresh = 0; | |
2880 | ||
2881 | for_each_encoder_on_crtc(dev, &intel_crtc->base, intel_encoder) { | |
2882 | /* Encoder connected on this CRTC */ | |
2883 | switch (intel_encoder->type) { | |
2884 | case INTEL_OUTPUT_EDP: | |
2885 | seq_puts(m, "eDP:\n"); | |
2886 | break; | |
2887 | case INTEL_OUTPUT_DSI: | |
2888 | seq_puts(m, "DSI:\n"); | |
2889 | break; | |
2890 | case INTEL_OUTPUT_HDMI: | |
2891 | seq_puts(m, "HDMI:\n"); | |
2892 | break; | |
2893 | case INTEL_OUTPUT_DISPLAYPORT: | |
2894 | seq_puts(m, "DP:\n"); | |
2895 | break; | |
2896 | default: | |
2897 | seq_printf(m, "Other encoder (id=%d).\n", | |
2898 | intel_encoder->type); | |
2899 | return; | |
2900 | } | |
2901 | } | |
2902 | ||
2903 | if (dev_priv->vbt.drrs_type == STATIC_DRRS_SUPPORT) | |
2904 | seq_puts(m, "\tVBT: DRRS_type: Static"); | |
2905 | else if (dev_priv->vbt.drrs_type == SEAMLESS_DRRS_SUPPORT) | |
2906 | seq_puts(m, "\tVBT: DRRS_type: Seamless"); | |
2907 | else if (dev_priv->vbt.drrs_type == DRRS_NOT_SUPPORTED) | |
2908 | seq_puts(m, "\tVBT: DRRS_type: None"); | |
2909 | else | |
2910 | seq_puts(m, "\tVBT: DRRS_type: FIXME: Unrecognized Value"); | |
2911 | ||
2912 | seq_puts(m, "\n\n"); | |
2913 | ||
2914 | if (intel_crtc->config->has_drrs) { | |
2915 | struct intel_panel *panel; | |
2916 | ||
2917 | mutex_lock(&drrs->mutex); | |
2918 | /* DRRS Supported */ | |
2919 | seq_puts(m, "\tDRRS Supported: Yes\n"); | |
2920 | ||
2921 | /* disable_drrs() will make drrs->dp NULL */ | |
2922 | if (!drrs->dp) { | |
2923 | seq_puts(m, "Idleness DRRS: Disabled"); | |
2924 | mutex_unlock(&drrs->mutex); | |
2925 | return; | |
2926 | } | |
2927 | ||
2928 | panel = &drrs->dp->attached_connector->panel; | |
2929 | seq_printf(m, "\t\tBusy_frontbuffer_bits: 0x%X", | |
2930 | drrs->busy_frontbuffer_bits); | |
2931 | ||
2932 | seq_puts(m, "\n\t\t"); | |
2933 | if (drrs->refresh_rate_type == DRRS_HIGH_RR) { | |
2934 | seq_puts(m, "DRRS_State: DRRS_HIGH_RR\n"); | |
2935 | vrefresh = panel->fixed_mode->vrefresh; | |
2936 | } else if (drrs->refresh_rate_type == DRRS_LOW_RR) { | |
2937 | seq_puts(m, "DRRS_State: DRRS_LOW_RR\n"); | |
2938 | vrefresh = panel->downclock_mode->vrefresh; | |
2939 | } else { | |
2940 | seq_printf(m, "DRRS_State: Unknown(%d)\n", | |
2941 | drrs->refresh_rate_type); | |
2942 | mutex_unlock(&drrs->mutex); | |
2943 | return; | |
2944 | } | |
2945 | seq_printf(m, "\t\tVrefresh: %d", vrefresh); | |
2946 | ||
2947 | seq_puts(m, "\n\t\t"); | |
2948 | mutex_unlock(&drrs->mutex); | |
2949 | } else { | |
2950 | /* DRRS not supported. Print the VBT parameter*/ | |
2951 | seq_puts(m, "\tDRRS Supported : No"); | |
2952 | } | |
2953 | seq_puts(m, "\n"); | |
2954 | } | |
2955 | ||
2956 | static int i915_drrs_status(struct seq_file *m, void *unused) | |
2957 | { | |
2958 | struct drm_info_node *node = m->private; | |
2959 | struct drm_device *dev = node->minor->dev; | |
2960 | struct intel_crtc *intel_crtc; | |
2961 | int active_crtc_cnt = 0; | |
2962 | ||
2963 | for_each_intel_crtc(dev, intel_crtc) { | |
2964 | drm_modeset_lock(&intel_crtc->base.mutex, NULL); | |
2965 | ||
2966 | if (intel_crtc->active) { | |
2967 | active_crtc_cnt++; | |
2968 | seq_printf(m, "\nCRTC %d: ", active_crtc_cnt); | |
2969 | ||
2970 | drrs_status_per_crtc(m, dev, intel_crtc); | |
2971 | } | |
2972 | ||
2973 | drm_modeset_unlock(&intel_crtc->base.mutex); | |
2974 | } | |
2975 | ||
2976 | if (!active_crtc_cnt) | |
2977 | seq_puts(m, "No active crtc found\n"); | |
2978 | ||
2979 | return 0; | |
2980 | } | |
2981 | ||
07144428 DL |
2982 | struct pipe_crc_info { |
2983 | const char *name; | |
2984 | struct drm_device *dev; | |
2985 | enum pipe pipe; | |
2986 | }; | |
2987 | ||
11bed958 DA |
2988 | static int i915_dp_mst_info(struct seq_file *m, void *unused) |
2989 | { | |
2990 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
2991 | struct drm_device *dev = node->minor->dev; | |
2992 | struct drm_encoder *encoder; | |
2993 | struct intel_encoder *intel_encoder; | |
2994 | struct intel_digital_port *intel_dig_port; | |
2995 | drm_modeset_lock_all(dev); | |
2996 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { | |
2997 | intel_encoder = to_intel_encoder(encoder); | |
2998 | if (intel_encoder->type != INTEL_OUTPUT_DISPLAYPORT) | |
2999 | continue; | |
3000 | intel_dig_port = enc_to_dig_port(encoder); | |
3001 | if (!intel_dig_port->dp.can_mst) | |
3002 | continue; | |
3003 | ||
3004 | drm_dp_mst_dump_topology(m, &intel_dig_port->dp.mst_mgr); | |
3005 | } | |
3006 | drm_modeset_unlock_all(dev); | |
3007 | return 0; | |
3008 | } | |
3009 | ||
07144428 DL |
3010 | static int i915_pipe_crc_open(struct inode *inode, struct file *filep) |
3011 | { | |
be5c7a90 DL |
3012 | struct pipe_crc_info *info = inode->i_private; |
3013 | struct drm_i915_private *dev_priv = info->dev->dev_private; | |
3014 | struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe]; | |
3015 | ||
7eb1c496 DV |
3016 | if (info->pipe >= INTEL_INFO(info->dev)->num_pipes) |
3017 | return -ENODEV; | |
3018 | ||
d538bbdf DL |
3019 | spin_lock_irq(&pipe_crc->lock); |
3020 | ||
3021 | if (pipe_crc->opened) { | |
3022 | spin_unlock_irq(&pipe_crc->lock); | |
be5c7a90 DL |
3023 | return -EBUSY; /* already open */ |
3024 | } | |
3025 | ||
d538bbdf | 3026 | pipe_crc->opened = true; |
07144428 DL |
3027 | filep->private_data = inode->i_private; |
3028 | ||
d538bbdf DL |
3029 | spin_unlock_irq(&pipe_crc->lock); |
3030 | ||
07144428 DL |
3031 | return 0; |
3032 | } | |
3033 | ||
3034 | static int i915_pipe_crc_release(struct inode *inode, struct file *filep) | |
3035 | { | |
be5c7a90 DL |
3036 | struct pipe_crc_info *info = inode->i_private; |
3037 | struct drm_i915_private *dev_priv = info->dev->dev_private; | |
3038 | struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe]; | |
3039 | ||
d538bbdf DL |
3040 | spin_lock_irq(&pipe_crc->lock); |
3041 | pipe_crc->opened = false; | |
3042 | spin_unlock_irq(&pipe_crc->lock); | |
be5c7a90 | 3043 | |
07144428 DL |
3044 | return 0; |
3045 | } | |
3046 | ||
3047 | /* (6 fields, 8 chars each, space separated (5) + '\n') */ | |
3048 | #define PIPE_CRC_LINE_LEN (6 * 8 + 5 + 1) | |
3049 | /* account for \'0' */ | |
3050 | #define PIPE_CRC_BUFFER_LEN (PIPE_CRC_LINE_LEN + 1) | |
3051 | ||
3052 | static int pipe_crc_data_count(struct intel_pipe_crc *pipe_crc) | |
8bf1e9f1 | 3053 | { |
d538bbdf DL |
3054 | assert_spin_locked(&pipe_crc->lock); |
3055 | return CIRC_CNT(pipe_crc->head, pipe_crc->tail, | |
3056 | INTEL_PIPE_CRC_ENTRIES_NR); | |
07144428 DL |
3057 | } |
3058 | ||
3059 | static ssize_t | |
3060 | i915_pipe_crc_read(struct file *filep, char __user *user_buf, size_t count, | |
3061 | loff_t *pos) | |
3062 | { | |
3063 | struct pipe_crc_info *info = filep->private_data; | |
3064 | struct drm_device *dev = info->dev; | |
3065 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3066 | struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe]; | |
3067 | char buf[PIPE_CRC_BUFFER_LEN]; | |
9ad6d99f | 3068 | int n_entries; |
07144428 DL |
3069 | ssize_t bytes_read; |
3070 | ||
3071 | /* | |
3072 | * Don't allow user space to provide buffers not big enough to hold | |
3073 | * a line of data. | |
3074 | */ | |
3075 | if (count < PIPE_CRC_LINE_LEN) | |
3076 | return -EINVAL; | |
3077 | ||
3078 | if (pipe_crc->source == INTEL_PIPE_CRC_SOURCE_NONE) | |
8bf1e9f1 | 3079 | return 0; |
07144428 DL |
3080 | |
3081 | /* nothing to read */ | |
d538bbdf | 3082 | spin_lock_irq(&pipe_crc->lock); |
07144428 | 3083 | while (pipe_crc_data_count(pipe_crc) == 0) { |
d538bbdf DL |
3084 | int ret; |
3085 | ||
3086 | if (filep->f_flags & O_NONBLOCK) { | |
3087 | spin_unlock_irq(&pipe_crc->lock); | |
07144428 | 3088 | return -EAGAIN; |
d538bbdf | 3089 | } |
07144428 | 3090 | |
d538bbdf DL |
3091 | ret = wait_event_interruptible_lock_irq(pipe_crc->wq, |
3092 | pipe_crc_data_count(pipe_crc), pipe_crc->lock); | |
3093 | if (ret) { | |
3094 | spin_unlock_irq(&pipe_crc->lock); | |
3095 | return ret; | |
3096 | } | |
8bf1e9f1 SH |
3097 | } |
3098 | ||
07144428 | 3099 | /* We now have one or more entries to read */ |
9ad6d99f | 3100 | n_entries = count / PIPE_CRC_LINE_LEN; |
d538bbdf | 3101 | |
07144428 | 3102 | bytes_read = 0; |
9ad6d99f VS |
3103 | while (n_entries > 0) { |
3104 | struct intel_pipe_crc_entry *entry = | |
3105 | &pipe_crc->entries[pipe_crc->tail]; | |
07144428 | 3106 | int ret; |
8bf1e9f1 | 3107 | |
9ad6d99f VS |
3108 | if (CIRC_CNT(pipe_crc->head, pipe_crc->tail, |
3109 | INTEL_PIPE_CRC_ENTRIES_NR) < 1) | |
3110 | break; | |
3111 | ||
3112 | BUILD_BUG_ON_NOT_POWER_OF_2(INTEL_PIPE_CRC_ENTRIES_NR); | |
3113 | pipe_crc->tail = (pipe_crc->tail + 1) & (INTEL_PIPE_CRC_ENTRIES_NR - 1); | |
3114 | ||
07144428 DL |
3115 | bytes_read += snprintf(buf, PIPE_CRC_BUFFER_LEN, |
3116 | "%8u %8x %8x %8x %8x %8x\n", | |
3117 | entry->frame, entry->crc[0], | |
3118 | entry->crc[1], entry->crc[2], | |
3119 | entry->crc[3], entry->crc[4]); | |
3120 | ||
9ad6d99f VS |
3121 | spin_unlock_irq(&pipe_crc->lock); |
3122 | ||
3123 | ret = copy_to_user(user_buf, buf, PIPE_CRC_LINE_LEN); | |
07144428 DL |
3124 | if (ret == PIPE_CRC_LINE_LEN) |
3125 | return -EFAULT; | |
b2c88f5b | 3126 | |
9ad6d99f VS |
3127 | user_buf += PIPE_CRC_LINE_LEN; |
3128 | n_entries--; | |
3129 | ||
3130 | spin_lock_irq(&pipe_crc->lock); | |
3131 | } | |
8bf1e9f1 | 3132 | |
d538bbdf DL |
3133 | spin_unlock_irq(&pipe_crc->lock); |
3134 | ||
07144428 DL |
3135 | return bytes_read; |
3136 | } | |
3137 | ||
3138 | static const struct file_operations i915_pipe_crc_fops = { | |
3139 | .owner = THIS_MODULE, | |
3140 | .open = i915_pipe_crc_open, | |
3141 | .read = i915_pipe_crc_read, | |
3142 | .release = i915_pipe_crc_release, | |
3143 | }; | |
3144 | ||
3145 | static struct pipe_crc_info i915_pipe_crc_data[I915_MAX_PIPES] = { | |
3146 | { | |
3147 | .name = "i915_pipe_A_crc", | |
3148 | .pipe = PIPE_A, | |
3149 | }, | |
3150 | { | |
3151 | .name = "i915_pipe_B_crc", | |
3152 | .pipe = PIPE_B, | |
3153 | }, | |
3154 | { | |
3155 | .name = "i915_pipe_C_crc", | |
3156 | .pipe = PIPE_C, | |
3157 | }, | |
3158 | }; | |
3159 | ||
3160 | static int i915_pipe_crc_create(struct dentry *root, struct drm_minor *minor, | |
3161 | enum pipe pipe) | |
3162 | { | |
3163 | struct drm_device *dev = minor->dev; | |
3164 | struct dentry *ent; | |
3165 | struct pipe_crc_info *info = &i915_pipe_crc_data[pipe]; | |
3166 | ||
3167 | info->dev = dev; | |
3168 | ent = debugfs_create_file(info->name, S_IRUGO, root, info, | |
3169 | &i915_pipe_crc_fops); | |
f3c5fe97 WY |
3170 | if (!ent) |
3171 | return -ENOMEM; | |
07144428 DL |
3172 | |
3173 | return drm_add_fake_info_node(minor, ent, info); | |
8bf1e9f1 SH |
3174 | } |
3175 | ||
e8dfcf78 | 3176 | static const char * const pipe_crc_sources[] = { |
926321d5 DV |
3177 | "none", |
3178 | "plane1", | |
3179 | "plane2", | |
3180 | "pf", | |
5b3a856b | 3181 | "pipe", |
3d099a05 DV |
3182 | "TV", |
3183 | "DP-B", | |
3184 | "DP-C", | |
3185 | "DP-D", | |
46a19188 | 3186 | "auto", |
926321d5 DV |
3187 | }; |
3188 | ||
3189 | static const char *pipe_crc_source_name(enum intel_pipe_crc_source source) | |
3190 | { | |
3191 | BUILD_BUG_ON(ARRAY_SIZE(pipe_crc_sources) != INTEL_PIPE_CRC_SOURCE_MAX); | |
3192 | return pipe_crc_sources[source]; | |
3193 | } | |
3194 | ||
bd9db02f | 3195 | static int display_crc_ctl_show(struct seq_file *m, void *data) |
926321d5 DV |
3196 | { |
3197 | struct drm_device *dev = m->private; | |
3198 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3199 | int i; | |
3200 | ||
3201 | for (i = 0; i < I915_MAX_PIPES; i++) | |
3202 | seq_printf(m, "%c %s\n", pipe_name(i), | |
3203 | pipe_crc_source_name(dev_priv->pipe_crc[i].source)); | |
3204 | ||
3205 | return 0; | |
3206 | } | |
3207 | ||
bd9db02f | 3208 | static int display_crc_ctl_open(struct inode *inode, struct file *file) |
926321d5 DV |
3209 | { |
3210 | struct drm_device *dev = inode->i_private; | |
3211 | ||
bd9db02f | 3212 | return single_open(file, display_crc_ctl_show, dev); |
926321d5 DV |
3213 | } |
3214 | ||
46a19188 | 3215 | static int i8xx_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source, |
52f843f6 DV |
3216 | uint32_t *val) |
3217 | { | |
46a19188 DV |
3218 | if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) |
3219 | *source = INTEL_PIPE_CRC_SOURCE_PIPE; | |
3220 | ||
3221 | switch (*source) { | |
52f843f6 DV |
3222 | case INTEL_PIPE_CRC_SOURCE_PIPE: |
3223 | *val = PIPE_CRC_ENABLE | PIPE_CRC_INCLUDE_BORDER_I8XX; | |
3224 | break; | |
3225 | case INTEL_PIPE_CRC_SOURCE_NONE: | |
3226 | *val = 0; | |
3227 | break; | |
3228 | default: | |
3229 | return -EINVAL; | |
3230 | } | |
3231 | ||
3232 | return 0; | |
3233 | } | |
3234 | ||
46a19188 DV |
3235 | static int i9xx_pipe_crc_auto_source(struct drm_device *dev, enum pipe pipe, |
3236 | enum intel_pipe_crc_source *source) | |
3237 | { | |
3238 | struct intel_encoder *encoder; | |
3239 | struct intel_crtc *crtc; | |
26756809 | 3240 | struct intel_digital_port *dig_port; |
46a19188 DV |
3241 | int ret = 0; |
3242 | ||
3243 | *source = INTEL_PIPE_CRC_SOURCE_PIPE; | |
3244 | ||
6e9f798d | 3245 | drm_modeset_lock_all(dev); |
b2784e15 | 3246 | for_each_intel_encoder(dev, encoder) { |
46a19188 DV |
3247 | if (!encoder->base.crtc) |
3248 | continue; | |
3249 | ||
3250 | crtc = to_intel_crtc(encoder->base.crtc); | |
3251 | ||
3252 | if (crtc->pipe != pipe) | |
3253 | continue; | |
3254 | ||
3255 | switch (encoder->type) { | |
3256 | case INTEL_OUTPUT_TVOUT: | |
3257 | *source = INTEL_PIPE_CRC_SOURCE_TV; | |
3258 | break; | |
3259 | case INTEL_OUTPUT_DISPLAYPORT: | |
3260 | case INTEL_OUTPUT_EDP: | |
26756809 DV |
3261 | dig_port = enc_to_dig_port(&encoder->base); |
3262 | switch (dig_port->port) { | |
3263 | case PORT_B: | |
3264 | *source = INTEL_PIPE_CRC_SOURCE_DP_B; | |
3265 | break; | |
3266 | case PORT_C: | |
3267 | *source = INTEL_PIPE_CRC_SOURCE_DP_C; | |
3268 | break; | |
3269 | case PORT_D: | |
3270 | *source = INTEL_PIPE_CRC_SOURCE_DP_D; | |
3271 | break; | |
3272 | default: | |
3273 | WARN(1, "nonexisting DP port %c\n", | |
3274 | port_name(dig_port->port)); | |
3275 | break; | |
3276 | } | |
46a19188 | 3277 | break; |
6847d71b PZ |
3278 | default: |
3279 | break; | |
46a19188 DV |
3280 | } |
3281 | } | |
6e9f798d | 3282 | drm_modeset_unlock_all(dev); |
46a19188 DV |
3283 | |
3284 | return ret; | |
3285 | } | |
3286 | ||
3287 | static int vlv_pipe_crc_ctl_reg(struct drm_device *dev, | |
3288 | enum pipe pipe, | |
3289 | enum intel_pipe_crc_source *source, | |
7ac0129b DV |
3290 | uint32_t *val) |
3291 | { | |
8d2f24ca DV |
3292 | struct drm_i915_private *dev_priv = dev->dev_private; |
3293 | bool need_stable_symbols = false; | |
3294 | ||
46a19188 DV |
3295 | if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) { |
3296 | int ret = i9xx_pipe_crc_auto_source(dev, pipe, source); | |
3297 | if (ret) | |
3298 | return ret; | |
3299 | } | |
3300 | ||
3301 | switch (*source) { | |
7ac0129b DV |
3302 | case INTEL_PIPE_CRC_SOURCE_PIPE: |
3303 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_VLV; | |
3304 | break; | |
3305 | case INTEL_PIPE_CRC_SOURCE_DP_B: | |
3306 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_VLV; | |
8d2f24ca | 3307 | need_stable_symbols = true; |
7ac0129b DV |
3308 | break; |
3309 | case INTEL_PIPE_CRC_SOURCE_DP_C: | |
3310 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_VLV; | |
8d2f24ca | 3311 | need_stable_symbols = true; |
7ac0129b | 3312 | break; |
2be57922 VS |
3313 | case INTEL_PIPE_CRC_SOURCE_DP_D: |
3314 | if (!IS_CHERRYVIEW(dev)) | |
3315 | return -EINVAL; | |
3316 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_D_VLV; | |
3317 | need_stable_symbols = true; | |
3318 | break; | |
7ac0129b DV |
3319 | case INTEL_PIPE_CRC_SOURCE_NONE: |
3320 | *val = 0; | |
3321 | break; | |
3322 | default: | |
3323 | return -EINVAL; | |
3324 | } | |
3325 | ||
8d2f24ca DV |
3326 | /* |
3327 | * When the pipe CRC tap point is after the transcoders we need | |
3328 | * to tweak symbol-level features to produce a deterministic series of | |
3329 | * symbols for a given frame. We need to reset those features only once | |
3330 | * a frame (instead of every nth symbol): | |
3331 | * - DC-balance: used to ensure a better clock recovery from the data | |
3332 | * link (SDVO) | |
3333 | * - DisplayPort scrambling: used for EMI reduction | |
3334 | */ | |
3335 | if (need_stable_symbols) { | |
3336 | uint32_t tmp = I915_READ(PORT_DFT2_G4X); | |
3337 | ||
8d2f24ca | 3338 | tmp |= DC_BALANCE_RESET_VLV; |
eb736679 VS |
3339 | switch (pipe) { |
3340 | case PIPE_A: | |
8d2f24ca | 3341 | tmp |= PIPE_A_SCRAMBLE_RESET; |
eb736679 VS |
3342 | break; |
3343 | case PIPE_B: | |
8d2f24ca | 3344 | tmp |= PIPE_B_SCRAMBLE_RESET; |
eb736679 VS |
3345 | break; |
3346 | case PIPE_C: | |
3347 | tmp |= PIPE_C_SCRAMBLE_RESET; | |
3348 | break; | |
3349 | default: | |
3350 | return -EINVAL; | |
3351 | } | |
8d2f24ca DV |
3352 | I915_WRITE(PORT_DFT2_G4X, tmp); |
3353 | } | |
3354 | ||
7ac0129b DV |
3355 | return 0; |
3356 | } | |
3357 | ||
4b79ebf7 | 3358 | static int i9xx_pipe_crc_ctl_reg(struct drm_device *dev, |
46a19188 DV |
3359 | enum pipe pipe, |
3360 | enum intel_pipe_crc_source *source, | |
4b79ebf7 DV |
3361 | uint32_t *val) |
3362 | { | |
84093603 DV |
3363 | struct drm_i915_private *dev_priv = dev->dev_private; |
3364 | bool need_stable_symbols = false; | |
3365 | ||
46a19188 DV |
3366 | if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) { |
3367 | int ret = i9xx_pipe_crc_auto_source(dev, pipe, source); | |
3368 | if (ret) | |
3369 | return ret; | |
3370 | } | |
3371 | ||
3372 | switch (*source) { | |
4b79ebf7 DV |
3373 | case INTEL_PIPE_CRC_SOURCE_PIPE: |
3374 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_I9XX; | |
3375 | break; | |
3376 | case INTEL_PIPE_CRC_SOURCE_TV: | |
3377 | if (!SUPPORTS_TV(dev)) | |
3378 | return -EINVAL; | |
3379 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_TV_PRE; | |
3380 | break; | |
3381 | case INTEL_PIPE_CRC_SOURCE_DP_B: | |
3382 | if (!IS_G4X(dev)) | |
3383 | return -EINVAL; | |
3384 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_G4X; | |
84093603 | 3385 | need_stable_symbols = true; |
4b79ebf7 DV |
3386 | break; |
3387 | case INTEL_PIPE_CRC_SOURCE_DP_C: | |
3388 | if (!IS_G4X(dev)) | |
3389 | return -EINVAL; | |
3390 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_G4X; | |
84093603 | 3391 | need_stable_symbols = true; |
4b79ebf7 DV |
3392 | break; |
3393 | case INTEL_PIPE_CRC_SOURCE_DP_D: | |
3394 | if (!IS_G4X(dev)) | |
3395 | return -EINVAL; | |
3396 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_D_G4X; | |
84093603 | 3397 | need_stable_symbols = true; |
4b79ebf7 DV |
3398 | break; |
3399 | case INTEL_PIPE_CRC_SOURCE_NONE: | |
3400 | *val = 0; | |
3401 | break; | |
3402 | default: | |
3403 | return -EINVAL; | |
3404 | } | |
3405 | ||
84093603 DV |
3406 | /* |
3407 | * When the pipe CRC tap point is after the transcoders we need | |
3408 | * to tweak symbol-level features to produce a deterministic series of | |
3409 | * symbols for a given frame. We need to reset those features only once | |
3410 | * a frame (instead of every nth symbol): | |
3411 | * - DC-balance: used to ensure a better clock recovery from the data | |
3412 | * link (SDVO) | |
3413 | * - DisplayPort scrambling: used for EMI reduction | |
3414 | */ | |
3415 | if (need_stable_symbols) { | |
3416 | uint32_t tmp = I915_READ(PORT_DFT2_G4X); | |
3417 | ||
3418 | WARN_ON(!IS_G4X(dev)); | |
3419 | ||
3420 | I915_WRITE(PORT_DFT_I9XX, | |
3421 | I915_READ(PORT_DFT_I9XX) | DC_BALANCE_RESET); | |
3422 | ||
3423 | if (pipe == PIPE_A) | |
3424 | tmp |= PIPE_A_SCRAMBLE_RESET; | |
3425 | else | |
3426 | tmp |= PIPE_B_SCRAMBLE_RESET; | |
3427 | ||
3428 | I915_WRITE(PORT_DFT2_G4X, tmp); | |
3429 | } | |
3430 | ||
4b79ebf7 DV |
3431 | return 0; |
3432 | } | |
3433 | ||
8d2f24ca DV |
3434 | static void vlv_undo_pipe_scramble_reset(struct drm_device *dev, |
3435 | enum pipe pipe) | |
3436 | { | |
3437 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3438 | uint32_t tmp = I915_READ(PORT_DFT2_G4X); | |
3439 | ||
eb736679 VS |
3440 | switch (pipe) { |
3441 | case PIPE_A: | |
8d2f24ca | 3442 | tmp &= ~PIPE_A_SCRAMBLE_RESET; |
eb736679 VS |
3443 | break; |
3444 | case PIPE_B: | |
8d2f24ca | 3445 | tmp &= ~PIPE_B_SCRAMBLE_RESET; |
eb736679 VS |
3446 | break; |
3447 | case PIPE_C: | |
3448 | tmp &= ~PIPE_C_SCRAMBLE_RESET; | |
3449 | break; | |
3450 | default: | |
3451 | return; | |
3452 | } | |
8d2f24ca DV |
3453 | if (!(tmp & PIPE_SCRAMBLE_RESET_MASK)) |
3454 | tmp &= ~DC_BALANCE_RESET_VLV; | |
3455 | I915_WRITE(PORT_DFT2_G4X, tmp); | |
3456 | ||
3457 | } | |
3458 | ||
84093603 DV |
3459 | static void g4x_undo_pipe_scramble_reset(struct drm_device *dev, |
3460 | enum pipe pipe) | |
3461 | { | |
3462 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3463 | uint32_t tmp = I915_READ(PORT_DFT2_G4X); | |
3464 | ||
3465 | if (pipe == PIPE_A) | |
3466 | tmp &= ~PIPE_A_SCRAMBLE_RESET; | |
3467 | else | |
3468 | tmp &= ~PIPE_B_SCRAMBLE_RESET; | |
3469 | I915_WRITE(PORT_DFT2_G4X, tmp); | |
3470 | ||
3471 | if (!(tmp & PIPE_SCRAMBLE_RESET_MASK)) { | |
3472 | I915_WRITE(PORT_DFT_I9XX, | |
3473 | I915_READ(PORT_DFT_I9XX) & ~DC_BALANCE_RESET); | |
3474 | } | |
3475 | } | |
3476 | ||
46a19188 | 3477 | static int ilk_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source, |
5b3a856b DV |
3478 | uint32_t *val) |
3479 | { | |
46a19188 DV |
3480 | if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) |
3481 | *source = INTEL_PIPE_CRC_SOURCE_PIPE; | |
3482 | ||
3483 | switch (*source) { | |
5b3a856b DV |
3484 | case INTEL_PIPE_CRC_SOURCE_PLANE1: |
3485 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_ILK; | |
3486 | break; | |
3487 | case INTEL_PIPE_CRC_SOURCE_PLANE2: | |
3488 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_ILK; | |
3489 | break; | |
5b3a856b DV |
3490 | case INTEL_PIPE_CRC_SOURCE_PIPE: |
3491 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_ILK; | |
3492 | break; | |
3d099a05 | 3493 | case INTEL_PIPE_CRC_SOURCE_NONE: |
5b3a856b DV |
3494 | *val = 0; |
3495 | break; | |
3d099a05 DV |
3496 | default: |
3497 | return -EINVAL; | |
5b3a856b DV |
3498 | } |
3499 | ||
3500 | return 0; | |
3501 | } | |
3502 | ||
fabf6e51 DV |
3503 | static void hsw_trans_edp_pipe_A_crc_wa(struct drm_device *dev) |
3504 | { | |
3505 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3506 | struct intel_crtc *crtc = | |
3507 | to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_A]); | |
3508 | ||
3509 | drm_modeset_lock_all(dev); | |
3510 | /* | |
3511 | * If we use the eDP transcoder we need to make sure that we don't | |
3512 | * bypass the pfit, since otherwise the pipe CRC source won't work. Only | |
3513 | * relevant on hsw with pipe A when using the always-on power well | |
3514 | * routing. | |
3515 | */ | |
6e3c9717 ACO |
3516 | if (crtc->config->cpu_transcoder == TRANSCODER_EDP && |
3517 | !crtc->config->pch_pfit.enabled) { | |
3518 | crtc->config->pch_pfit.force_thru = true; | |
fabf6e51 DV |
3519 | |
3520 | intel_display_power_get(dev_priv, | |
3521 | POWER_DOMAIN_PIPE_PANEL_FITTER(PIPE_A)); | |
3522 | ||
3523 | dev_priv->display.crtc_disable(&crtc->base); | |
3524 | dev_priv->display.crtc_enable(&crtc->base); | |
3525 | } | |
3526 | drm_modeset_unlock_all(dev); | |
3527 | } | |
3528 | ||
3529 | static void hsw_undo_trans_edp_pipe_A_crc_wa(struct drm_device *dev) | |
3530 | { | |
3531 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3532 | struct intel_crtc *crtc = | |
3533 | to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_A]); | |
3534 | ||
3535 | drm_modeset_lock_all(dev); | |
3536 | /* | |
3537 | * If we use the eDP transcoder we need to make sure that we don't | |
3538 | * bypass the pfit, since otherwise the pipe CRC source won't work. Only | |
3539 | * relevant on hsw with pipe A when using the always-on power well | |
3540 | * routing. | |
3541 | */ | |
6e3c9717 ACO |
3542 | if (crtc->config->pch_pfit.force_thru) { |
3543 | crtc->config->pch_pfit.force_thru = false; | |
fabf6e51 DV |
3544 | |
3545 | dev_priv->display.crtc_disable(&crtc->base); | |
3546 | dev_priv->display.crtc_enable(&crtc->base); | |
3547 | ||
3548 | intel_display_power_put(dev_priv, | |
3549 | POWER_DOMAIN_PIPE_PANEL_FITTER(PIPE_A)); | |
3550 | } | |
3551 | drm_modeset_unlock_all(dev); | |
3552 | } | |
3553 | ||
3554 | static int ivb_pipe_crc_ctl_reg(struct drm_device *dev, | |
3555 | enum pipe pipe, | |
3556 | enum intel_pipe_crc_source *source, | |
5b3a856b DV |
3557 | uint32_t *val) |
3558 | { | |
46a19188 DV |
3559 | if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) |
3560 | *source = INTEL_PIPE_CRC_SOURCE_PF; | |
3561 | ||
3562 | switch (*source) { | |
5b3a856b DV |
3563 | case INTEL_PIPE_CRC_SOURCE_PLANE1: |
3564 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_IVB; | |
3565 | break; | |
3566 | case INTEL_PIPE_CRC_SOURCE_PLANE2: | |
3567 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_IVB; | |
3568 | break; | |
3569 | case INTEL_PIPE_CRC_SOURCE_PF: | |
fabf6e51 DV |
3570 | if (IS_HASWELL(dev) && pipe == PIPE_A) |
3571 | hsw_trans_edp_pipe_A_crc_wa(dev); | |
3572 | ||
5b3a856b DV |
3573 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PF_IVB; |
3574 | break; | |
3d099a05 | 3575 | case INTEL_PIPE_CRC_SOURCE_NONE: |
5b3a856b DV |
3576 | *val = 0; |
3577 | break; | |
3d099a05 DV |
3578 | default: |
3579 | return -EINVAL; | |
5b3a856b DV |
3580 | } |
3581 | ||
3582 | return 0; | |
3583 | } | |
3584 | ||
926321d5 DV |
3585 | static int pipe_crc_set_source(struct drm_device *dev, enum pipe pipe, |
3586 | enum intel_pipe_crc_source source) | |
3587 | { | |
3588 | struct drm_i915_private *dev_priv = dev->dev_private; | |
cc3da175 | 3589 | struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe]; |
8c740dce PZ |
3590 | struct intel_crtc *crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, |
3591 | pipe)); | |
432f3342 | 3592 | u32 val = 0; /* shut up gcc */ |
5b3a856b | 3593 | int ret; |
926321d5 | 3594 | |
cc3da175 DL |
3595 | if (pipe_crc->source == source) |
3596 | return 0; | |
3597 | ||
ae676fcd DL |
3598 | /* forbid changing the source without going back to 'none' */ |
3599 | if (pipe_crc->source && source) | |
3600 | return -EINVAL; | |
3601 | ||
9d8b0588 DV |
3602 | if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PIPE(pipe))) { |
3603 | DRM_DEBUG_KMS("Trying to capture CRC while pipe is off\n"); | |
3604 | return -EIO; | |
3605 | } | |
3606 | ||
52f843f6 | 3607 | if (IS_GEN2(dev)) |
46a19188 | 3608 | ret = i8xx_pipe_crc_ctl_reg(&source, &val); |
52f843f6 | 3609 | else if (INTEL_INFO(dev)->gen < 5) |
46a19188 | 3610 | ret = i9xx_pipe_crc_ctl_reg(dev, pipe, &source, &val); |
7ac0129b | 3611 | else if (IS_VALLEYVIEW(dev)) |
fabf6e51 | 3612 | ret = vlv_pipe_crc_ctl_reg(dev, pipe, &source, &val); |
4b79ebf7 | 3613 | else if (IS_GEN5(dev) || IS_GEN6(dev)) |
46a19188 | 3614 | ret = ilk_pipe_crc_ctl_reg(&source, &val); |
5b3a856b | 3615 | else |
fabf6e51 | 3616 | ret = ivb_pipe_crc_ctl_reg(dev, pipe, &source, &val); |
5b3a856b DV |
3617 | |
3618 | if (ret != 0) | |
3619 | return ret; | |
3620 | ||
4b584369 DL |
3621 | /* none -> real source transition */ |
3622 | if (source) { | |
4252fbc3 VS |
3623 | struct intel_pipe_crc_entry *entries; |
3624 | ||
7cd6ccff DL |
3625 | DRM_DEBUG_DRIVER("collecting CRCs for pipe %c, %s\n", |
3626 | pipe_name(pipe), pipe_crc_source_name(source)); | |
3627 | ||
3cf54b34 VS |
3628 | entries = kcalloc(INTEL_PIPE_CRC_ENTRIES_NR, |
3629 | sizeof(pipe_crc->entries[0]), | |
4252fbc3 VS |
3630 | GFP_KERNEL); |
3631 | if (!entries) | |
e5f75aca DL |
3632 | return -ENOMEM; |
3633 | ||
8c740dce PZ |
3634 | /* |
3635 | * When IPS gets enabled, the pipe CRC changes. Since IPS gets | |
3636 | * enabled and disabled dynamically based on package C states, | |
3637 | * user space can't make reliable use of the CRCs, so let's just | |
3638 | * completely disable it. | |
3639 | */ | |
3640 | hsw_disable_ips(crtc); | |
3641 | ||
d538bbdf | 3642 | spin_lock_irq(&pipe_crc->lock); |
64387b61 | 3643 | kfree(pipe_crc->entries); |
4252fbc3 | 3644 | pipe_crc->entries = entries; |
d538bbdf DL |
3645 | pipe_crc->head = 0; |
3646 | pipe_crc->tail = 0; | |
3647 | spin_unlock_irq(&pipe_crc->lock); | |
4b584369 DL |
3648 | } |
3649 | ||
cc3da175 | 3650 | pipe_crc->source = source; |
926321d5 | 3651 | |
926321d5 DV |
3652 | I915_WRITE(PIPE_CRC_CTL(pipe), val); |
3653 | POSTING_READ(PIPE_CRC_CTL(pipe)); | |
3654 | ||
e5f75aca DL |
3655 | /* real source -> none transition */ |
3656 | if (source == INTEL_PIPE_CRC_SOURCE_NONE) { | |
d538bbdf | 3657 | struct intel_pipe_crc_entry *entries; |
a33d7105 DV |
3658 | struct intel_crtc *crtc = |
3659 | to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); | |
d538bbdf | 3660 | |
7cd6ccff DL |
3661 | DRM_DEBUG_DRIVER("stopping CRCs for pipe %c\n", |
3662 | pipe_name(pipe)); | |
3663 | ||
a33d7105 DV |
3664 | drm_modeset_lock(&crtc->base.mutex, NULL); |
3665 | if (crtc->active) | |
3666 | intel_wait_for_vblank(dev, pipe); | |
3667 | drm_modeset_unlock(&crtc->base.mutex); | |
bcf17ab2 | 3668 | |
d538bbdf DL |
3669 | spin_lock_irq(&pipe_crc->lock); |
3670 | entries = pipe_crc->entries; | |
e5f75aca | 3671 | pipe_crc->entries = NULL; |
9ad6d99f VS |
3672 | pipe_crc->head = 0; |
3673 | pipe_crc->tail = 0; | |
d538bbdf DL |
3674 | spin_unlock_irq(&pipe_crc->lock); |
3675 | ||
3676 | kfree(entries); | |
84093603 DV |
3677 | |
3678 | if (IS_G4X(dev)) | |
3679 | g4x_undo_pipe_scramble_reset(dev, pipe); | |
8d2f24ca DV |
3680 | else if (IS_VALLEYVIEW(dev)) |
3681 | vlv_undo_pipe_scramble_reset(dev, pipe); | |
fabf6e51 DV |
3682 | else if (IS_HASWELL(dev) && pipe == PIPE_A) |
3683 | hsw_undo_trans_edp_pipe_A_crc_wa(dev); | |
8c740dce PZ |
3684 | |
3685 | hsw_enable_ips(crtc); | |
e5f75aca DL |
3686 | } |
3687 | ||
926321d5 DV |
3688 | return 0; |
3689 | } | |
3690 | ||
3691 | /* | |
3692 | * Parse pipe CRC command strings: | |
b94dec87 DL |
3693 | * command: wsp* object wsp+ name wsp+ source wsp* |
3694 | * object: 'pipe' | |
3695 | * name: (A | B | C) | |
926321d5 DV |
3696 | * source: (none | plane1 | plane2 | pf) |
3697 | * wsp: (#0x20 | #0x9 | #0xA)+ | |
3698 | * | |
3699 | * eg.: | |
b94dec87 DL |
3700 | * "pipe A plane1" -> Start CRC computations on plane1 of pipe A |
3701 | * "pipe A none" -> Stop CRC | |
926321d5 | 3702 | */ |
bd9db02f | 3703 | static int display_crc_ctl_tokenize(char *buf, char *words[], int max_words) |
926321d5 DV |
3704 | { |
3705 | int n_words = 0; | |
3706 | ||
3707 | while (*buf) { | |
3708 | char *end; | |
3709 | ||
3710 | /* skip leading white space */ | |
3711 | buf = skip_spaces(buf); | |
3712 | if (!*buf) | |
3713 | break; /* end of buffer */ | |
3714 | ||
3715 | /* find end of word */ | |
3716 | for (end = buf; *end && !isspace(*end); end++) | |
3717 | ; | |
3718 | ||
3719 | if (n_words == max_words) { | |
3720 | DRM_DEBUG_DRIVER("too many words, allowed <= %d\n", | |
3721 | max_words); | |
3722 | return -EINVAL; /* ran out of words[] before bytes */ | |
3723 | } | |
3724 | ||
3725 | if (*end) | |
3726 | *end++ = '\0'; | |
3727 | words[n_words++] = buf; | |
3728 | buf = end; | |
3729 | } | |
3730 | ||
3731 | return n_words; | |
3732 | } | |
3733 | ||
b94dec87 DL |
3734 | enum intel_pipe_crc_object { |
3735 | PIPE_CRC_OBJECT_PIPE, | |
3736 | }; | |
3737 | ||
e8dfcf78 | 3738 | static const char * const pipe_crc_objects[] = { |
b94dec87 DL |
3739 | "pipe", |
3740 | }; | |
3741 | ||
3742 | static int | |
bd9db02f | 3743 | display_crc_ctl_parse_object(const char *buf, enum intel_pipe_crc_object *o) |
b94dec87 DL |
3744 | { |
3745 | int i; | |
3746 | ||
3747 | for (i = 0; i < ARRAY_SIZE(pipe_crc_objects); i++) | |
3748 | if (!strcmp(buf, pipe_crc_objects[i])) { | |
bd9db02f | 3749 | *o = i; |
b94dec87 DL |
3750 | return 0; |
3751 | } | |
3752 | ||
3753 | return -EINVAL; | |
3754 | } | |
3755 | ||
bd9db02f | 3756 | static int display_crc_ctl_parse_pipe(const char *buf, enum pipe *pipe) |
926321d5 DV |
3757 | { |
3758 | const char name = buf[0]; | |
3759 | ||
3760 | if (name < 'A' || name >= pipe_name(I915_MAX_PIPES)) | |
3761 | return -EINVAL; | |
3762 | ||
3763 | *pipe = name - 'A'; | |
3764 | ||
3765 | return 0; | |
3766 | } | |
3767 | ||
3768 | static int | |
bd9db02f | 3769 | display_crc_ctl_parse_source(const char *buf, enum intel_pipe_crc_source *s) |
926321d5 DV |
3770 | { |
3771 | int i; | |
3772 | ||
3773 | for (i = 0; i < ARRAY_SIZE(pipe_crc_sources); i++) | |
3774 | if (!strcmp(buf, pipe_crc_sources[i])) { | |
bd9db02f | 3775 | *s = i; |
926321d5 DV |
3776 | return 0; |
3777 | } | |
3778 | ||
3779 | return -EINVAL; | |
3780 | } | |
3781 | ||
bd9db02f | 3782 | static int display_crc_ctl_parse(struct drm_device *dev, char *buf, size_t len) |
926321d5 | 3783 | { |
b94dec87 | 3784 | #define N_WORDS 3 |
926321d5 | 3785 | int n_words; |
b94dec87 | 3786 | char *words[N_WORDS]; |
926321d5 | 3787 | enum pipe pipe; |
b94dec87 | 3788 | enum intel_pipe_crc_object object; |
926321d5 DV |
3789 | enum intel_pipe_crc_source source; |
3790 | ||
bd9db02f | 3791 | n_words = display_crc_ctl_tokenize(buf, words, N_WORDS); |
b94dec87 DL |
3792 | if (n_words != N_WORDS) { |
3793 | DRM_DEBUG_DRIVER("tokenize failed, a command is %d words\n", | |
3794 | N_WORDS); | |
3795 | return -EINVAL; | |
3796 | } | |
3797 | ||
bd9db02f | 3798 | if (display_crc_ctl_parse_object(words[0], &object) < 0) { |
b94dec87 | 3799 | DRM_DEBUG_DRIVER("unknown object %s\n", words[0]); |
926321d5 DV |
3800 | return -EINVAL; |
3801 | } | |
3802 | ||
bd9db02f | 3803 | if (display_crc_ctl_parse_pipe(words[1], &pipe) < 0) { |
b94dec87 | 3804 | DRM_DEBUG_DRIVER("unknown pipe %s\n", words[1]); |
926321d5 DV |
3805 | return -EINVAL; |
3806 | } | |
3807 | ||
bd9db02f | 3808 | if (display_crc_ctl_parse_source(words[2], &source) < 0) { |
b94dec87 | 3809 | DRM_DEBUG_DRIVER("unknown source %s\n", words[2]); |
926321d5 DV |
3810 | return -EINVAL; |
3811 | } | |
3812 | ||
3813 | return pipe_crc_set_source(dev, pipe, source); | |
3814 | } | |
3815 | ||
bd9db02f DL |
3816 | static ssize_t display_crc_ctl_write(struct file *file, const char __user *ubuf, |
3817 | size_t len, loff_t *offp) | |
926321d5 DV |
3818 | { |
3819 | struct seq_file *m = file->private_data; | |
3820 | struct drm_device *dev = m->private; | |
3821 | char *tmpbuf; | |
3822 | int ret; | |
3823 | ||
3824 | if (len == 0) | |
3825 | return 0; | |
3826 | ||
3827 | if (len > PAGE_SIZE - 1) { | |
3828 | DRM_DEBUG_DRIVER("expected <%lu bytes into pipe crc control\n", | |
3829 | PAGE_SIZE); | |
3830 | return -E2BIG; | |
3831 | } | |
3832 | ||
3833 | tmpbuf = kmalloc(len + 1, GFP_KERNEL); | |
3834 | if (!tmpbuf) | |
3835 | return -ENOMEM; | |
3836 | ||
3837 | if (copy_from_user(tmpbuf, ubuf, len)) { | |
3838 | ret = -EFAULT; | |
3839 | goto out; | |
3840 | } | |
3841 | tmpbuf[len] = '\0'; | |
3842 | ||
bd9db02f | 3843 | ret = display_crc_ctl_parse(dev, tmpbuf, len); |
926321d5 DV |
3844 | |
3845 | out: | |
3846 | kfree(tmpbuf); | |
3847 | if (ret < 0) | |
3848 | return ret; | |
3849 | ||
3850 | *offp += len; | |
3851 | return len; | |
3852 | } | |
3853 | ||
bd9db02f | 3854 | static const struct file_operations i915_display_crc_ctl_fops = { |
926321d5 | 3855 | .owner = THIS_MODULE, |
bd9db02f | 3856 | .open = display_crc_ctl_open, |
926321d5 DV |
3857 | .read = seq_read, |
3858 | .llseek = seq_lseek, | |
3859 | .release = single_release, | |
bd9db02f | 3860 | .write = display_crc_ctl_write |
926321d5 DV |
3861 | }; |
3862 | ||
97e94b22 | 3863 | static void wm_latency_show(struct seq_file *m, const uint16_t wm[8]) |
369a1342 VS |
3864 | { |
3865 | struct drm_device *dev = m->private; | |
546c81fd | 3866 | int num_levels = ilk_wm_max_level(dev) + 1; |
369a1342 VS |
3867 | int level; |
3868 | ||
3869 | drm_modeset_lock_all(dev); | |
3870 | ||
3871 | for (level = 0; level < num_levels; level++) { | |
3872 | unsigned int latency = wm[level]; | |
3873 | ||
97e94b22 DL |
3874 | /* |
3875 | * - WM1+ latency values in 0.5us units | |
3876 | * - latencies are in us on gen9 | |
3877 | */ | |
3878 | if (INTEL_INFO(dev)->gen >= 9) | |
3879 | latency *= 10; | |
3880 | else if (level > 0) | |
369a1342 VS |
3881 | latency *= 5; |
3882 | ||
3883 | seq_printf(m, "WM%d %u (%u.%u usec)\n", | |
97e94b22 | 3884 | level, wm[level], latency / 10, latency % 10); |
369a1342 VS |
3885 | } |
3886 | ||
3887 | drm_modeset_unlock_all(dev); | |
3888 | } | |
3889 | ||
3890 | static int pri_wm_latency_show(struct seq_file *m, void *data) | |
3891 | { | |
3892 | struct drm_device *dev = m->private; | |
97e94b22 DL |
3893 | struct drm_i915_private *dev_priv = dev->dev_private; |
3894 | const uint16_t *latencies; | |
3895 | ||
3896 | if (INTEL_INFO(dev)->gen >= 9) | |
3897 | latencies = dev_priv->wm.skl_latency; | |
3898 | else | |
3899 | latencies = to_i915(dev)->wm.pri_latency; | |
369a1342 | 3900 | |
97e94b22 | 3901 | wm_latency_show(m, latencies); |
369a1342 VS |
3902 | |
3903 | return 0; | |
3904 | } | |
3905 | ||
3906 | static int spr_wm_latency_show(struct seq_file *m, void *data) | |
3907 | { | |
3908 | struct drm_device *dev = m->private; | |
97e94b22 DL |
3909 | struct drm_i915_private *dev_priv = dev->dev_private; |
3910 | const uint16_t *latencies; | |
3911 | ||
3912 | if (INTEL_INFO(dev)->gen >= 9) | |
3913 | latencies = dev_priv->wm.skl_latency; | |
3914 | else | |
3915 | latencies = to_i915(dev)->wm.spr_latency; | |
369a1342 | 3916 | |
97e94b22 | 3917 | wm_latency_show(m, latencies); |
369a1342 VS |
3918 | |
3919 | return 0; | |
3920 | } | |
3921 | ||
3922 | static int cur_wm_latency_show(struct seq_file *m, void *data) | |
3923 | { | |
3924 | struct drm_device *dev = m->private; | |
97e94b22 DL |
3925 | struct drm_i915_private *dev_priv = dev->dev_private; |
3926 | const uint16_t *latencies; | |
3927 | ||
3928 | if (INTEL_INFO(dev)->gen >= 9) | |
3929 | latencies = dev_priv->wm.skl_latency; | |
3930 | else | |
3931 | latencies = to_i915(dev)->wm.cur_latency; | |
369a1342 | 3932 | |
97e94b22 | 3933 | wm_latency_show(m, latencies); |
369a1342 VS |
3934 | |
3935 | return 0; | |
3936 | } | |
3937 | ||
3938 | static int pri_wm_latency_open(struct inode *inode, struct file *file) | |
3939 | { | |
3940 | struct drm_device *dev = inode->i_private; | |
3941 | ||
9ad0257c | 3942 | if (HAS_GMCH_DISPLAY(dev)) |
369a1342 VS |
3943 | return -ENODEV; |
3944 | ||
3945 | return single_open(file, pri_wm_latency_show, dev); | |
3946 | } | |
3947 | ||
3948 | static int spr_wm_latency_open(struct inode *inode, struct file *file) | |
3949 | { | |
3950 | struct drm_device *dev = inode->i_private; | |
3951 | ||
9ad0257c | 3952 | if (HAS_GMCH_DISPLAY(dev)) |
369a1342 VS |
3953 | return -ENODEV; |
3954 | ||
3955 | return single_open(file, spr_wm_latency_show, dev); | |
3956 | } | |
3957 | ||
3958 | static int cur_wm_latency_open(struct inode *inode, struct file *file) | |
3959 | { | |
3960 | struct drm_device *dev = inode->i_private; | |
3961 | ||
9ad0257c | 3962 | if (HAS_GMCH_DISPLAY(dev)) |
369a1342 VS |
3963 | return -ENODEV; |
3964 | ||
3965 | return single_open(file, cur_wm_latency_show, dev); | |
3966 | } | |
3967 | ||
3968 | static ssize_t wm_latency_write(struct file *file, const char __user *ubuf, | |
97e94b22 | 3969 | size_t len, loff_t *offp, uint16_t wm[8]) |
369a1342 VS |
3970 | { |
3971 | struct seq_file *m = file->private_data; | |
3972 | struct drm_device *dev = m->private; | |
97e94b22 | 3973 | uint16_t new[8] = { 0 }; |
546c81fd | 3974 | int num_levels = ilk_wm_max_level(dev) + 1; |
369a1342 VS |
3975 | int level; |
3976 | int ret; | |
3977 | char tmp[32]; | |
3978 | ||
3979 | if (len >= sizeof(tmp)) | |
3980 | return -EINVAL; | |
3981 | ||
3982 | if (copy_from_user(tmp, ubuf, len)) | |
3983 | return -EFAULT; | |
3984 | ||
3985 | tmp[len] = '\0'; | |
3986 | ||
97e94b22 DL |
3987 | ret = sscanf(tmp, "%hu %hu %hu %hu %hu %hu %hu %hu", |
3988 | &new[0], &new[1], &new[2], &new[3], | |
3989 | &new[4], &new[5], &new[6], &new[7]); | |
369a1342 VS |
3990 | if (ret != num_levels) |
3991 | return -EINVAL; | |
3992 | ||
3993 | drm_modeset_lock_all(dev); | |
3994 | ||
3995 | for (level = 0; level < num_levels; level++) | |
3996 | wm[level] = new[level]; | |
3997 | ||
3998 | drm_modeset_unlock_all(dev); | |
3999 | ||
4000 | return len; | |
4001 | } | |
4002 | ||
4003 | ||
4004 | static ssize_t pri_wm_latency_write(struct file *file, const char __user *ubuf, | |
4005 | size_t len, loff_t *offp) | |
4006 | { | |
4007 | struct seq_file *m = file->private_data; | |
4008 | struct drm_device *dev = m->private; | |
97e94b22 DL |
4009 | struct drm_i915_private *dev_priv = dev->dev_private; |
4010 | uint16_t *latencies; | |
369a1342 | 4011 | |
97e94b22 DL |
4012 | if (INTEL_INFO(dev)->gen >= 9) |
4013 | latencies = dev_priv->wm.skl_latency; | |
4014 | else | |
4015 | latencies = to_i915(dev)->wm.pri_latency; | |
4016 | ||
4017 | return wm_latency_write(file, ubuf, len, offp, latencies); | |
369a1342 VS |
4018 | } |
4019 | ||
4020 | static ssize_t spr_wm_latency_write(struct file *file, const char __user *ubuf, | |
4021 | size_t len, loff_t *offp) | |
4022 | { | |
4023 | struct seq_file *m = file->private_data; | |
4024 | struct drm_device *dev = m->private; | |
97e94b22 DL |
4025 | struct drm_i915_private *dev_priv = dev->dev_private; |
4026 | uint16_t *latencies; | |
369a1342 | 4027 | |
97e94b22 DL |
4028 | if (INTEL_INFO(dev)->gen >= 9) |
4029 | latencies = dev_priv->wm.skl_latency; | |
4030 | else | |
4031 | latencies = to_i915(dev)->wm.spr_latency; | |
4032 | ||
4033 | return wm_latency_write(file, ubuf, len, offp, latencies); | |
369a1342 VS |
4034 | } |
4035 | ||
4036 | static ssize_t cur_wm_latency_write(struct file *file, const char __user *ubuf, | |
4037 | size_t len, loff_t *offp) | |
4038 | { | |
4039 | struct seq_file *m = file->private_data; | |
4040 | struct drm_device *dev = m->private; | |
97e94b22 DL |
4041 | struct drm_i915_private *dev_priv = dev->dev_private; |
4042 | uint16_t *latencies; | |
4043 | ||
4044 | if (INTEL_INFO(dev)->gen >= 9) | |
4045 | latencies = dev_priv->wm.skl_latency; | |
4046 | else | |
4047 | latencies = to_i915(dev)->wm.cur_latency; | |
369a1342 | 4048 | |
97e94b22 | 4049 | return wm_latency_write(file, ubuf, len, offp, latencies); |
369a1342 VS |
4050 | } |
4051 | ||
4052 | static const struct file_operations i915_pri_wm_latency_fops = { | |
4053 | .owner = THIS_MODULE, | |
4054 | .open = pri_wm_latency_open, | |
4055 | .read = seq_read, | |
4056 | .llseek = seq_lseek, | |
4057 | .release = single_release, | |
4058 | .write = pri_wm_latency_write | |
4059 | }; | |
4060 | ||
4061 | static const struct file_operations i915_spr_wm_latency_fops = { | |
4062 | .owner = THIS_MODULE, | |
4063 | .open = spr_wm_latency_open, | |
4064 | .read = seq_read, | |
4065 | .llseek = seq_lseek, | |
4066 | .release = single_release, | |
4067 | .write = spr_wm_latency_write | |
4068 | }; | |
4069 | ||
4070 | static const struct file_operations i915_cur_wm_latency_fops = { | |
4071 | .owner = THIS_MODULE, | |
4072 | .open = cur_wm_latency_open, | |
4073 | .read = seq_read, | |
4074 | .llseek = seq_lseek, | |
4075 | .release = single_release, | |
4076 | .write = cur_wm_latency_write | |
4077 | }; | |
4078 | ||
647416f9 KC |
4079 | static int |
4080 | i915_wedged_get(void *data, u64 *val) | |
f3cd474b | 4081 | { |
647416f9 | 4082 | struct drm_device *dev = data; |
e277a1f8 | 4083 | struct drm_i915_private *dev_priv = dev->dev_private; |
f3cd474b | 4084 | |
647416f9 | 4085 | *val = atomic_read(&dev_priv->gpu_error.reset_counter); |
f3cd474b | 4086 | |
647416f9 | 4087 | return 0; |
f3cd474b CW |
4088 | } |
4089 | ||
647416f9 KC |
4090 | static int |
4091 | i915_wedged_set(void *data, u64 val) | |
f3cd474b | 4092 | { |
647416f9 | 4093 | struct drm_device *dev = data; |
d46c0517 ID |
4094 | struct drm_i915_private *dev_priv = dev->dev_private; |
4095 | ||
b8d24a06 MK |
4096 | /* |
4097 | * There is no safeguard against this debugfs entry colliding | |
4098 | * with the hangcheck calling same i915_handle_error() in | |
4099 | * parallel, causing an explosion. For now we assume that the | |
4100 | * test harness is responsible enough not to inject gpu hangs | |
4101 | * while it is writing to 'i915_wedged' | |
4102 | */ | |
4103 | ||
4104 | if (i915_reset_in_progress(&dev_priv->gpu_error)) | |
4105 | return -EAGAIN; | |
4106 | ||
d46c0517 | 4107 | intel_runtime_pm_get(dev_priv); |
f3cd474b | 4108 | |
58174462 MK |
4109 | i915_handle_error(dev, val, |
4110 | "Manually setting wedged to %llu", val); | |
d46c0517 ID |
4111 | |
4112 | intel_runtime_pm_put(dev_priv); | |
4113 | ||
647416f9 | 4114 | return 0; |
f3cd474b CW |
4115 | } |
4116 | ||
647416f9 KC |
4117 | DEFINE_SIMPLE_ATTRIBUTE(i915_wedged_fops, |
4118 | i915_wedged_get, i915_wedged_set, | |
3a3b4f98 | 4119 | "%llu\n"); |
f3cd474b | 4120 | |
647416f9 KC |
4121 | static int |
4122 | i915_ring_stop_get(void *data, u64 *val) | |
e5eb3d63 | 4123 | { |
647416f9 | 4124 | struct drm_device *dev = data; |
e277a1f8 | 4125 | struct drm_i915_private *dev_priv = dev->dev_private; |
e5eb3d63 | 4126 | |
647416f9 | 4127 | *val = dev_priv->gpu_error.stop_rings; |
e5eb3d63 | 4128 | |
647416f9 | 4129 | return 0; |
e5eb3d63 DV |
4130 | } |
4131 | ||
647416f9 KC |
4132 | static int |
4133 | i915_ring_stop_set(void *data, u64 val) | |
e5eb3d63 | 4134 | { |
647416f9 | 4135 | struct drm_device *dev = data; |
e5eb3d63 | 4136 | struct drm_i915_private *dev_priv = dev->dev_private; |
647416f9 | 4137 | int ret; |
e5eb3d63 | 4138 | |
647416f9 | 4139 | DRM_DEBUG_DRIVER("Stopping rings 0x%08llx\n", val); |
e5eb3d63 | 4140 | |
22bcfc6a DV |
4141 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
4142 | if (ret) | |
4143 | return ret; | |
4144 | ||
99584db3 | 4145 | dev_priv->gpu_error.stop_rings = val; |
e5eb3d63 DV |
4146 | mutex_unlock(&dev->struct_mutex); |
4147 | ||
647416f9 | 4148 | return 0; |
e5eb3d63 DV |
4149 | } |
4150 | ||
647416f9 KC |
4151 | DEFINE_SIMPLE_ATTRIBUTE(i915_ring_stop_fops, |
4152 | i915_ring_stop_get, i915_ring_stop_set, | |
4153 | "0x%08llx\n"); | |
d5442303 | 4154 | |
094f9a54 CW |
4155 | static int |
4156 | i915_ring_missed_irq_get(void *data, u64 *val) | |
4157 | { | |
4158 | struct drm_device *dev = data; | |
4159 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4160 | ||
4161 | *val = dev_priv->gpu_error.missed_irq_rings; | |
4162 | return 0; | |
4163 | } | |
4164 | ||
4165 | static int | |
4166 | i915_ring_missed_irq_set(void *data, u64 val) | |
4167 | { | |
4168 | struct drm_device *dev = data; | |
4169 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4170 | int ret; | |
4171 | ||
4172 | /* Lock against concurrent debugfs callers */ | |
4173 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
4174 | if (ret) | |
4175 | return ret; | |
4176 | dev_priv->gpu_error.missed_irq_rings = val; | |
4177 | mutex_unlock(&dev->struct_mutex); | |
4178 | ||
4179 | return 0; | |
4180 | } | |
4181 | ||
4182 | DEFINE_SIMPLE_ATTRIBUTE(i915_ring_missed_irq_fops, | |
4183 | i915_ring_missed_irq_get, i915_ring_missed_irq_set, | |
4184 | "0x%08llx\n"); | |
4185 | ||
4186 | static int | |
4187 | i915_ring_test_irq_get(void *data, u64 *val) | |
4188 | { | |
4189 | struct drm_device *dev = data; | |
4190 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4191 | ||
4192 | *val = dev_priv->gpu_error.test_irq_rings; | |
4193 | ||
4194 | return 0; | |
4195 | } | |
4196 | ||
4197 | static int | |
4198 | i915_ring_test_irq_set(void *data, u64 val) | |
4199 | { | |
4200 | struct drm_device *dev = data; | |
4201 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4202 | int ret; | |
4203 | ||
4204 | DRM_DEBUG_DRIVER("Masking interrupts on rings 0x%08llx\n", val); | |
4205 | ||
4206 | /* Lock against concurrent debugfs callers */ | |
4207 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
4208 | if (ret) | |
4209 | return ret; | |
4210 | ||
4211 | dev_priv->gpu_error.test_irq_rings = val; | |
4212 | mutex_unlock(&dev->struct_mutex); | |
4213 | ||
4214 | return 0; | |
4215 | } | |
4216 | ||
4217 | DEFINE_SIMPLE_ATTRIBUTE(i915_ring_test_irq_fops, | |
4218 | i915_ring_test_irq_get, i915_ring_test_irq_set, | |
4219 | "0x%08llx\n"); | |
4220 | ||
dd624afd CW |
4221 | #define DROP_UNBOUND 0x1 |
4222 | #define DROP_BOUND 0x2 | |
4223 | #define DROP_RETIRE 0x4 | |
4224 | #define DROP_ACTIVE 0x8 | |
4225 | #define DROP_ALL (DROP_UNBOUND | \ | |
4226 | DROP_BOUND | \ | |
4227 | DROP_RETIRE | \ | |
4228 | DROP_ACTIVE) | |
647416f9 KC |
4229 | static int |
4230 | i915_drop_caches_get(void *data, u64 *val) | |
dd624afd | 4231 | { |
647416f9 | 4232 | *val = DROP_ALL; |
dd624afd | 4233 | |
647416f9 | 4234 | return 0; |
dd624afd CW |
4235 | } |
4236 | ||
647416f9 KC |
4237 | static int |
4238 | i915_drop_caches_set(void *data, u64 val) | |
dd624afd | 4239 | { |
647416f9 | 4240 | struct drm_device *dev = data; |
dd624afd | 4241 | struct drm_i915_private *dev_priv = dev->dev_private; |
647416f9 | 4242 | int ret; |
dd624afd | 4243 | |
2f9fe5ff | 4244 | DRM_DEBUG("Dropping caches: 0x%08llx\n", val); |
dd624afd CW |
4245 | |
4246 | /* No need to check and wait for gpu resets, only libdrm auto-restarts | |
4247 | * on ioctls on -EAGAIN. */ | |
4248 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
4249 | if (ret) | |
4250 | return ret; | |
4251 | ||
4252 | if (val & DROP_ACTIVE) { | |
4253 | ret = i915_gpu_idle(dev); | |
4254 | if (ret) | |
4255 | goto unlock; | |
4256 | } | |
4257 | ||
4258 | if (val & (DROP_RETIRE | DROP_ACTIVE)) | |
4259 | i915_gem_retire_requests(dev); | |
4260 | ||
21ab4e74 CW |
4261 | if (val & DROP_BOUND) |
4262 | i915_gem_shrink(dev_priv, LONG_MAX, I915_SHRINK_BOUND); | |
4ad72b7f | 4263 | |
21ab4e74 CW |
4264 | if (val & DROP_UNBOUND) |
4265 | i915_gem_shrink(dev_priv, LONG_MAX, I915_SHRINK_UNBOUND); | |
dd624afd CW |
4266 | |
4267 | unlock: | |
4268 | mutex_unlock(&dev->struct_mutex); | |
4269 | ||
647416f9 | 4270 | return ret; |
dd624afd CW |
4271 | } |
4272 | ||
647416f9 KC |
4273 | DEFINE_SIMPLE_ATTRIBUTE(i915_drop_caches_fops, |
4274 | i915_drop_caches_get, i915_drop_caches_set, | |
4275 | "0x%08llx\n"); | |
dd624afd | 4276 | |
647416f9 KC |
4277 | static int |
4278 | i915_max_freq_get(void *data, u64 *val) | |
358733e9 | 4279 | { |
647416f9 | 4280 | struct drm_device *dev = data; |
e277a1f8 | 4281 | struct drm_i915_private *dev_priv = dev->dev_private; |
647416f9 | 4282 | int ret; |
004777cb | 4283 | |
daa3afb2 | 4284 | if (INTEL_INFO(dev)->gen < 6) |
004777cb DV |
4285 | return -ENODEV; |
4286 | ||
5c9669ce TR |
4287 | flush_delayed_work(&dev_priv->rps.delayed_resume_work); |
4288 | ||
4fc688ce | 4289 | ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock); |
004777cb DV |
4290 | if (ret) |
4291 | return ret; | |
358733e9 | 4292 | |
7c59a9c1 | 4293 | *val = intel_gpu_freq(dev_priv, dev_priv->rps.max_freq_softlimit); |
4fc688ce | 4294 | mutex_unlock(&dev_priv->rps.hw_lock); |
358733e9 | 4295 | |
647416f9 | 4296 | return 0; |
358733e9 JB |
4297 | } |
4298 | ||
647416f9 KC |
4299 | static int |
4300 | i915_max_freq_set(void *data, u64 val) | |
358733e9 | 4301 | { |
647416f9 | 4302 | struct drm_device *dev = data; |
358733e9 | 4303 | struct drm_i915_private *dev_priv = dev->dev_private; |
bc4d91f6 | 4304 | u32 hw_max, hw_min; |
647416f9 | 4305 | int ret; |
004777cb | 4306 | |
daa3afb2 | 4307 | if (INTEL_INFO(dev)->gen < 6) |
004777cb | 4308 | return -ENODEV; |
358733e9 | 4309 | |
5c9669ce TR |
4310 | flush_delayed_work(&dev_priv->rps.delayed_resume_work); |
4311 | ||
647416f9 | 4312 | DRM_DEBUG_DRIVER("Manually setting max freq to %llu\n", val); |
358733e9 | 4313 | |
4fc688ce | 4314 | ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock); |
004777cb DV |
4315 | if (ret) |
4316 | return ret; | |
4317 | ||
358733e9 JB |
4318 | /* |
4319 | * Turbo will still be enabled, but won't go above the set value. | |
4320 | */ | |
bc4d91f6 | 4321 | val = intel_freq_opcode(dev_priv, val); |
dd0a1aa1 | 4322 | |
bc4d91f6 AG |
4323 | hw_max = dev_priv->rps.max_freq; |
4324 | hw_min = dev_priv->rps.min_freq; | |
dd0a1aa1 | 4325 | |
b39fb297 | 4326 | if (val < hw_min || val > hw_max || val < dev_priv->rps.min_freq_softlimit) { |
dd0a1aa1 JM |
4327 | mutex_unlock(&dev_priv->rps.hw_lock); |
4328 | return -EINVAL; | |
0a073b84 JB |
4329 | } |
4330 | ||
b39fb297 | 4331 | dev_priv->rps.max_freq_softlimit = val; |
dd0a1aa1 | 4332 | |
ffe02b40 | 4333 | intel_set_rps(dev, val); |
dd0a1aa1 | 4334 | |
4fc688ce | 4335 | mutex_unlock(&dev_priv->rps.hw_lock); |
358733e9 | 4336 | |
647416f9 | 4337 | return 0; |
358733e9 JB |
4338 | } |
4339 | ||
647416f9 KC |
4340 | DEFINE_SIMPLE_ATTRIBUTE(i915_max_freq_fops, |
4341 | i915_max_freq_get, i915_max_freq_set, | |
3a3b4f98 | 4342 | "%llu\n"); |
358733e9 | 4343 | |
647416f9 KC |
4344 | static int |
4345 | i915_min_freq_get(void *data, u64 *val) | |
1523c310 | 4346 | { |
647416f9 | 4347 | struct drm_device *dev = data; |
e277a1f8 | 4348 | struct drm_i915_private *dev_priv = dev->dev_private; |
647416f9 | 4349 | int ret; |
004777cb | 4350 | |
daa3afb2 | 4351 | if (INTEL_INFO(dev)->gen < 6) |
004777cb DV |
4352 | return -ENODEV; |
4353 | ||
5c9669ce TR |
4354 | flush_delayed_work(&dev_priv->rps.delayed_resume_work); |
4355 | ||
4fc688ce | 4356 | ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock); |
004777cb DV |
4357 | if (ret) |
4358 | return ret; | |
1523c310 | 4359 | |
7c59a9c1 | 4360 | *val = intel_gpu_freq(dev_priv, dev_priv->rps.min_freq_softlimit); |
4fc688ce | 4361 | mutex_unlock(&dev_priv->rps.hw_lock); |
1523c310 | 4362 | |
647416f9 | 4363 | return 0; |
1523c310 JB |
4364 | } |
4365 | ||
647416f9 KC |
4366 | static int |
4367 | i915_min_freq_set(void *data, u64 val) | |
1523c310 | 4368 | { |
647416f9 | 4369 | struct drm_device *dev = data; |
1523c310 | 4370 | struct drm_i915_private *dev_priv = dev->dev_private; |
bc4d91f6 | 4371 | u32 hw_max, hw_min; |
647416f9 | 4372 | int ret; |
004777cb | 4373 | |
daa3afb2 | 4374 | if (INTEL_INFO(dev)->gen < 6) |
004777cb | 4375 | return -ENODEV; |
1523c310 | 4376 | |
5c9669ce TR |
4377 | flush_delayed_work(&dev_priv->rps.delayed_resume_work); |
4378 | ||
647416f9 | 4379 | DRM_DEBUG_DRIVER("Manually setting min freq to %llu\n", val); |
1523c310 | 4380 | |
4fc688ce | 4381 | ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock); |
004777cb DV |
4382 | if (ret) |
4383 | return ret; | |
4384 | ||
1523c310 JB |
4385 | /* |
4386 | * Turbo will still be enabled, but won't go below the set value. | |
4387 | */ | |
bc4d91f6 | 4388 | val = intel_freq_opcode(dev_priv, val); |
dd0a1aa1 | 4389 | |
bc4d91f6 AG |
4390 | hw_max = dev_priv->rps.max_freq; |
4391 | hw_min = dev_priv->rps.min_freq; | |
dd0a1aa1 | 4392 | |
b39fb297 | 4393 | if (val < hw_min || val > hw_max || val > dev_priv->rps.max_freq_softlimit) { |
dd0a1aa1 JM |
4394 | mutex_unlock(&dev_priv->rps.hw_lock); |
4395 | return -EINVAL; | |
0a073b84 | 4396 | } |
dd0a1aa1 | 4397 | |
b39fb297 | 4398 | dev_priv->rps.min_freq_softlimit = val; |
dd0a1aa1 | 4399 | |
ffe02b40 | 4400 | intel_set_rps(dev, val); |
dd0a1aa1 | 4401 | |
4fc688ce | 4402 | mutex_unlock(&dev_priv->rps.hw_lock); |
1523c310 | 4403 | |
647416f9 | 4404 | return 0; |
1523c310 JB |
4405 | } |
4406 | ||
647416f9 KC |
4407 | DEFINE_SIMPLE_ATTRIBUTE(i915_min_freq_fops, |
4408 | i915_min_freq_get, i915_min_freq_set, | |
3a3b4f98 | 4409 | "%llu\n"); |
1523c310 | 4410 | |
647416f9 KC |
4411 | static int |
4412 | i915_cache_sharing_get(void *data, u64 *val) | |
07b7ddd9 | 4413 | { |
647416f9 | 4414 | struct drm_device *dev = data; |
e277a1f8 | 4415 | struct drm_i915_private *dev_priv = dev->dev_private; |
07b7ddd9 | 4416 | u32 snpcr; |
647416f9 | 4417 | int ret; |
07b7ddd9 | 4418 | |
004777cb DV |
4419 | if (!(IS_GEN6(dev) || IS_GEN7(dev))) |
4420 | return -ENODEV; | |
4421 | ||
22bcfc6a DV |
4422 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
4423 | if (ret) | |
4424 | return ret; | |
c8c8fb33 | 4425 | intel_runtime_pm_get(dev_priv); |
22bcfc6a | 4426 | |
07b7ddd9 | 4427 | snpcr = I915_READ(GEN6_MBCUNIT_SNPCR); |
c8c8fb33 PZ |
4428 | |
4429 | intel_runtime_pm_put(dev_priv); | |
07b7ddd9 JB |
4430 | mutex_unlock(&dev_priv->dev->struct_mutex); |
4431 | ||
647416f9 | 4432 | *val = (snpcr & GEN6_MBC_SNPCR_MASK) >> GEN6_MBC_SNPCR_SHIFT; |
07b7ddd9 | 4433 | |
647416f9 | 4434 | return 0; |
07b7ddd9 JB |
4435 | } |
4436 | ||
647416f9 KC |
4437 | static int |
4438 | i915_cache_sharing_set(void *data, u64 val) | |
07b7ddd9 | 4439 | { |
647416f9 | 4440 | struct drm_device *dev = data; |
07b7ddd9 | 4441 | struct drm_i915_private *dev_priv = dev->dev_private; |
07b7ddd9 | 4442 | u32 snpcr; |
07b7ddd9 | 4443 | |
004777cb DV |
4444 | if (!(IS_GEN6(dev) || IS_GEN7(dev))) |
4445 | return -ENODEV; | |
4446 | ||
647416f9 | 4447 | if (val > 3) |
07b7ddd9 JB |
4448 | return -EINVAL; |
4449 | ||
c8c8fb33 | 4450 | intel_runtime_pm_get(dev_priv); |
647416f9 | 4451 | DRM_DEBUG_DRIVER("Manually setting uncore sharing to %llu\n", val); |
07b7ddd9 JB |
4452 | |
4453 | /* Update the cache sharing policy here as well */ | |
4454 | snpcr = I915_READ(GEN6_MBCUNIT_SNPCR); | |
4455 | snpcr &= ~GEN6_MBC_SNPCR_MASK; | |
4456 | snpcr |= (val << GEN6_MBC_SNPCR_SHIFT); | |
4457 | I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr); | |
4458 | ||
c8c8fb33 | 4459 | intel_runtime_pm_put(dev_priv); |
647416f9 | 4460 | return 0; |
07b7ddd9 JB |
4461 | } |
4462 | ||
647416f9 KC |
4463 | DEFINE_SIMPLE_ATTRIBUTE(i915_cache_sharing_fops, |
4464 | i915_cache_sharing_get, i915_cache_sharing_set, | |
4465 | "%llu\n"); | |
07b7ddd9 | 4466 | |
3873218f JM |
4467 | static int i915_sseu_status(struct seq_file *m, void *unused) |
4468 | { | |
4469 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
4470 | struct drm_device *dev = node->minor->dev; | |
7f992aba JM |
4471 | struct drm_i915_private *dev_priv = dev->dev_private; |
4472 | unsigned int s_tot = 0, ss_tot = 0, ss_per = 0, eu_tot = 0, eu_per = 0; | |
3873218f | 4473 | |
5575f03a | 4474 | if ((INTEL_INFO(dev)->gen < 8) || IS_BROADWELL(dev)) |
3873218f JM |
4475 | return -ENODEV; |
4476 | ||
4477 | seq_puts(m, "SSEU Device Info\n"); | |
4478 | seq_printf(m, " Available Slice Total: %u\n", | |
4479 | INTEL_INFO(dev)->slice_total); | |
4480 | seq_printf(m, " Available Subslice Total: %u\n", | |
4481 | INTEL_INFO(dev)->subslice_total); | |
4482 | seq_printf(m, " Available Subslice Per Slice: %u\n", | |
4483 | INTEL_INFO(dev)->subslice_per_slice); | |
4484 | seq_printf(m, " Available EU Total: %u\n", | |
4485 | INTEL_INFO(dev)->eu_total); | |
4486 | seq_printf(m, " Available EU Per Subslice: %u\n", | |
4487 | INTEL_INFO(dev)->eu_per_subslice); | |
4488 | seq_printf(m, " Has Slice Power Gating: %s\n", | |
4489 | yesno(INTEL_INFO(dev)->has_slice_pg)); | |
4490 | seq_printf(m, " Has Subslice Power Gating: %s\n", | |
4491 | yesno(INTEL_INFO(dev)->has_subslice_pg)); | |
4492 | seq_printf(m, " Has EU Power Gating: %s\n", | |
4493 | yesno(INTEL_INFO(dev)->has_eu_pg)); | |
4494 | ||
7f992aba | 4495 | seq_puts(m, "SSEU Device Status\n"); |
5575f03a JM |
4496 | if (IS_CHERRYVIEW(dev)) { |
4497 | const int ss_max = 2; | |
4498 | int ss; | |
4499 | u32 sig1[ss_max], sig2[ss_max]; | |
4500 | ||
4501 | sig1[0] = I915_READ(CHV_POWER_SS0_SIG1); | |
4502 | sig1[1] = I915_READ(CHV_POWER_SS1_SIG1); | |
4503 | sig2[0] = I915_READ(CHV_POWER_SS0_SIG2); | |
4504 | sig2[1] = I915_READ(CHV_POWER_SS1_SIG2); | |
4505 | ||
4506 | for (ss = 0; ss < ss_max; ss++) { | |
4507 | unsigned int eu_cnt; | |
4508 | ||
4509 | if (sig1[ss] & CHV_SS_PG_ENABLE) | |
4510 | /* skip disabled subslice */ | |
4511 | continue; | |
4512 | ||
4513 | s_tot = 1; | |
4514 | ss_per++; | |
4515 | eu_cnt = ((sig1[ss] & CHV_EU08_PG_ENABLE) ? 0 : 2) + | |
4516 | ((sig1[ss] & CHV_EU19_PG_ENABLE) ? 0 : 2) + | |
4517 | ((sig1[ss] & CHV_EU210_PG_ENABLE) ? 0 : 2) + | |
4518 | ((sig2[ss] & CHV_EU311_PG_ENABLE) ? 0 : 2); | |
4519 | eu_tot += eu_cnt; | |
4520 | eu_per = max(eu_per, eu_cnt); | |
4521 | } | |
4522 | ss_tot = ss_per; | |
4523 | } else if (IS_SKYLAKE(dev)) { | |
7f992aba JM |
4524 | const int s_max = 3, ss_max = 4; |
4525 | int s, ss; | |
4526 | u32 s_reg[s_max], eu_reg[2*s_max], eu_mask[2]; | |
4527 | ||
4528 | s_reg[0] = I915_READ(GEN9_SLICE0_PGCTL_ACK); | |
4529 | s_reg[1] = I915_READ(GEN9_SLICE1_PGCTL_ACK); | |
4530 | s_reg[2] = I915_READ(GEN9_SLICE2_PGCTL_ACK); | |
4531 | eu_reg[0] = I915_READ(GEN9_SLICE0_SS01_EU_PGCTL_ACK); | |
4532 | eu_reg[1] = I915_READ(GEN9_SLICE0_SS23_EU_PGCTL_ACK); | |
4533 | eu_reg[2] = I915_READ(GEN9_SLICE1_SS01_EU_PGCTL_ACK); | |
4534 | eu_reg[3] = I915_READ(GEN9_SLICE1_SS23_EU_PGCTL_ACK); | |
4535 | eu_reg[4] = I915_READ(GEN9_SLICE2_SS01_EU_PGCTL_ACK); | |
4536 | eu_reg[5] = I915_READ(GEN9_SLICE2_SS23_EU_PGCTL_ACK); | |
4537 | eu_mask[0] = GEN9_PGCTL_SSA_EU08_ACK | | |
4538 | GEN9_PGCTL_SSA_EU19_ACK | | |
4539 | GEN9_PGCTL_SSA_EU210_ACK | | |
4540 | GEN9_PGCTL_SSA_EU311_ACK; | |
4541 | eu_mask[1] = GEN9_PGCTL_SSB_EU08_ACK | | |
4542 | GEN9_PGCTL_SSB_EU19_ACK | | |
4543 | GEN9_PGCTL_SSB_EU210_ACK | | |
4544 | GEN9_PGCTL_SSB_EU311_ACK; | |
4545 | ||
4546 | for (s = 0; s < s_max; s++) { | |
4547 | if ((s_reg[s] & GEN9_PGCTL_SLICE_ACK) == 0) | |
4548 | /* skip disabled slice */ | |
4549 | continue; | |
4550 | ||
4551 | s_tot++; | |
4552 | ss_per = INTEL_INFO(dev)->subslice_per_slice; | |
4553 | ss_tot += ss_per; | |
4554 | for (ss = 0; ss < ss_max; ss++) { | |
4555 | unsigned int eu_cnt; | |
4556 | ||
4557 | eu_cnt = 2 * hweight32(eu_reg[2*s + ss/2] & | |
4558 | eu_mask[ss%2]); | |
4559 | eu_tot += eu_cnt; | |
4560 | eu_per = max(eu_per, eu_cnt); | |
4561 | } | |
4562 | } | |
4563 | } | |
4564 | seq_printf(m, " Enabled Slice Total: %u\n", s_tot); | |
4565 | seq_printf(m, " Enabled Subslice Total: %u\n", ss_tot); | |
4566 | seq_printf(m, " Enabled Subslice Per Slice: %u\n", ss_per); | |
4567 | seq_printf(m, " Enabled EU Total: %u\n", eu_tot); | |
4568 | seq_printf(m, " Enabled EU Per Subslice: %u\n", eu_per); | |
4569 | ||
3873218f JM |
4570 | return 0; |
4571 | } | |
4572 | ||
6d794d42 BW |
4573 | static int i915_forcewake_open(struct inode *inode, struct file *file) |
4574 | { | |
4575 | struct drm_device *dev = inode->i_private; | |
4576 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6d794d42 | 4577 | |
075edca4 | 4578 | if (INTEL_INFO(dev)->gen < 6) |
6d794d42 BW |
4579 | return 0; |
4580 | ||
6daccb0b | 4581 | intel_runtime_pm_get(dev_priv); |
59bad947 | 4582 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); |
6d794d42 BW |
4583 | |
4584 | return 0; | |
4585 | } | |
4586 | ||
c43b5634 | 4587 | static int i915_forcewake_release(struct inode *inode, struct file *file) |
6d794d42 BW |
4588 | { |
4589 | struct drm_device *dev = inode->i_private; | |
4590 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4591 | ||
075edca4 | 4592 | if (INTEL_INFO(dev)->gen < 6) |
6d794d42 BW |
4593 | return 0; |
4594 | ||
59bad947 | 4595 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); |
6daccb0b | 4596 | intel_runtime_pm_put(dev_priv); |
6d794d42 BW |
4597 | |
4598 | return 0; | |
4599 | } | |
4600 | ||
4601 | static const struct file_operations i915_forcewake_fops = { | |
4602 | .owner = THIS_MODULE, | |
4603 | .open = i915_forcewake_open, | |
4604 | .release = i915_forcewake_release, | |
4605 | }; | |
4606 | ||
4607 | static int i915_forcewake_create(struct dentry *root, struct drm_minor *minor) | |
4608 | { | |
4609 | struct drm_device *dev = minor->dev; | |
4610 | struct dentry *ent; | |
4611 | ||
4612 | ent = debugfs_create_file("i915_forcewake_user", | |
8eb57294 | 4613 | S_IRUSR, |
6d794d42 BW |
4614 | root, dev, |
4615 | &i915_forcewake_fops); | |
f3c5fe97 WY |
4616 | if (!ent) |
4617 | return -ENOMEM; | |
6d794d42 | 4618 | |
8eb57294 | 4619 | return drm_add_fake_info_node(minor, ent, &i915_forcewake_fops); |
6d794d42 BW |
4620 | } |
4621 | ||
6a9c308d DV |
4622 | static int i915_debugfs_create(struct dentry *root, |
4623 | struct drm_minor *minor, | |
4624 | const char *name, | |
4625 | const struct file_operations *fops) | |
07b7ddd9 JB |
4626 | { |
4627 | struct drm_device *dev = minor->dev; | |
4628 | struct dentry *ent; | |
4629 | ||
6a9c308d | 4630 | ent = debugfs_create_file(name, |
07b7ddd9 JB |
4631 | S_IRUGO | S_IWUSR, |
4632 | root, dev, | |
6a9c308d | 4633 | fops); |
f3c5fe97 WY |
4634 | if (!ent) |
4635 | return -ENOMEM; | |
07b7ddd9 | 4636 | |
6a9c308d | 4637 | return drm_add_fake_info_node(minor, ent, fops); |
07b7ddd9 JB |
4638 | } |
4639 | ||
06c5bf8c | 4640 | static const struct drm_info_list i915_debugfs_list[] = { |
311bd68e | 4641 | {"i915_capabilities", i915_capabilities, 0}, |
73aa808f | 4642 | {"i915_gem_objects", i915_gem_object_info, 0}, |
08c18323 | 4643 | {"i915_gem_gtt", i915_gem_gtt_info, 0}, |
1b50247a | 4644 | {"i915_gem_pinned", i915_gem_gtt_info, 0, (void *) PINNED_LIST}, |
433e12f7 | 4645 | {"i915_gem_active", i915_gem_object_list_info, 0, (void *) ACTIVE_LIST}, |
433e12f7 | 4646 | {"i915_gem_inactive", i915_gem_object_list_info, 0, (void *) INACTIVE_LIST}, |
6d2b8885 | 4647 | {"i915_gem_stolen", i915_gem_stolen_list_info }, |
4e5359cd | 4648 | {"i915_gem_pageflip", i915_gem_pageflip_info, 0}, |
2017263e BG |
4649 | {"i915_gem_request", i915_gem_request_info, 0}, |
4650 | {"i915_gem_seqno", i915_gem_seqno_info, 0}, | |
a6172a80 | 4651 | {"i915_gem_fence_regs", i915_gem_fence_regs_info, 0}, |
2017263e | 4652 | {"i915_gem_interrupt", i915_interrupt_info, 0}, |
1ec14ad3 CW |
4653 | {"i915_gem_hws", i915_hws_info, 0, (void *)RCS}, |
4654 | {"i915_gem_hws_blt", i915_hws_info, 0, (void *)BCS}, | |
4655 | {"i915_gem_hws_bsd", i915_hws_info, 0, (void *)VCS}, | |
9010ebfd | 4656 | {"i915_gem_hws_vebox", i915_hws_info, 0, (void *)VECS}, |
493018dc | 4657 | {"i915_gem_batch_pool", i915_gem_batch_pool_info, 0}, |
adb4bd12 | 4658 | {"i915_frequency_info", i915_frequency_info, 0}, |
f654449a | 4659 | {"i915_hangcheck_info", i915_hangcheck_info, 0}, |
f97108d1 | 4660 | {"i915_drpc_info", i915_drpc_info, 0}, |
7648fa99 | 4661 | {"i915_emon_status", i915_emon_status, 0}, |
23b2f8bb | 4662 | {"i915_ring_freq_table", i915_ring_freq_table, 0}, |
b5e50c3f | 4663 | {"i915_fbc_status", i915_fbc_status, 0}, |
92d44621 | 4664 | {"i915_ips_status", i915_ips_status, 0}, |
4a9bef37 | 4665 | {"i915_sr_status", i915_sr_status, 0}, |
44834a67 | 4666 | {"i915_opregion", i915_opregion, 0}, |
37811fcc | 4667 | {"i915_gem_framebuffer", i915_gem_framebuffer_info, 0}, |
e76d3630 | 4668 | {"i915_context_status", i915_context_status, 0}, |
c0ab1ae9 | 4669 | {"i915_dump_lrc", i915_dump_lrc, 0}, |
4ba70e44 | 4670 | {"i915_execlists", i915_execlists, 0}, |
f65367b5 | 4671 | {"i915_forcewake_domains", i915_forcewake_domains, 0}, |
ea16a3cd | 4672 | {"i915_swizzle_info", i915_swizzle_info, 0}, |
3cf17fc5 | 4673 | {"i915_ppgtt_info", i915_ppgtt_info, 0}, |
63573eb7 | 4674 | {"i915_llc", i915_llc, 0}, |
e91fd8c6 | 4675 | {"i915_edp_psr_status", i915_edp_psr_status, 0}, |
d2e216d0 | 4676 | {"i915_sink_crc_eDP1", i915_sink_crc, 0}, |
ec013e7f | 4677 | {"i915_energy_uJ", i915_energy_uJ, 0}, |
371db66a | 4678 | {"i915_pc8_status", i915_pc8_status, 0}, |
1da51581 | 4679 | {"i915_power_domain_info", i915_power_domain_info, 0}, |
53f5e3ca | 4680 | {"i915_display_info", i915_display_info, 0}, |
e04934cf | 4681 | {"i915_semaphore_status", i915_semaphore_status, 0}, |
728e29d7 | 4682 | {"i915_shared_dplls_info", i915_shared_dplls_info, 0}, |
11bed958 | 4683 | {"i915_dp_mst_info", i915_dp_mst_info, 0}, |
1ed1ef9d | 4684 | {"i915_wa_registers", i915_wa_registers, 0}, |
c5511e44 | 4685 | {"i915_ddb_info", i915_ddb_info, 0}, |
3873218f | 4686 | {"i915_sseu_status", i915_sseu_status, 0}, |
a54746e3 | 4687 | {"i915_drrs_status", i915_drrs_status, 0}, |
2017263e | 4688 | }; |
27c202ad | 4689 | #define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list) |
2017263e | 4690 | |
06c5bf8c | 4691 | static const struct i915_debugfs_files { |
34b9674c DV |
4692 | const char *name; |
4693 | const struct file_operations *fops; | |
4694 | } i915_debugfs_files[] = { | |
4695 | {"i915_wedged", &i915_wedged_fops}, | |
4696 | {"i915_max_freq", &i915_max_freq_fops}, | |
4697 | {"i915_min_freq", &i915_min_freq_fops}, | |
4698 | {"i915_cache_sharing", &i915_cache_sharing_fops}, | |
4699 | {"i915_ring_stop", &i915_ring_stop_fops}, | |
094f9a54 CW |
4700 | {"i915_ring_missed_irq", &i915_ring_missed_irq_fops}, |
4701 | {"i915_ring_test_irq", &i915_ring_test_irq_fops}, | |
34b9674c DV |
4702 | {"i915_gem_drop_caches", &i915_drop_caches_fops}, |
4703 | {"i915_error_state", &i915_error_state_fops}, | |
4704 | {"i915_next_seqno", &i915_next_seqno_fops}, | |
bd9db02f | 4705 | {"i915_display_crc_ctl", &i915_display_crc_ctl_fops}, |
369a1342 VS |
4706 | {"i915_pri_wm_latency", &i915_pri_wm_latency_fops}, |
4707 | {"i915_spr_wm_latency", &i915_spr_wm_latency_fops}, | |
4708 | {"i915_cur_wm_latency", &i915_cur_wm_latency_fops}, | |
da46f936 | 4709 | {"i915_fbc_false_color", &i915_fbc_fc_fops}, |
34b9674c DV |
4710 | }; |
4711 | ||
07144428 DL |
4712 | void intel_display_crc_init(struct drm_device *dev) |
4713 | { | |
4714 | struct drm_i915_private *dev_priv = dev->dev_private; | |
b378360e | 4715 | enum pipe pipe; |
07144428 | 4716 | |
055e393f | 4717 | for_each_pipe(dev_priv, pipe) { |
b378360e | 4718 | struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe]; |
07144428 | 4719 | |
d538bbdf DL |
4720 | pipe_crc->opened = false; |
4721 | spin_lock_init(&pipe_crc->lock); | |
07144428 DL |
4722 | init_waitqueue_head(&pipe_crc->wq); |
4723 | } | |
4724 | } | |
4725 | ||
27c202ad | 4726 | int i915_debugfs_init(struct drm_minor *minor) |
2017263e | 4727 | { |
34b9674c | 4728 | int ret, i; |
f3cd474b | 4729 | |
6d794d42 | 4730 | ret = i915_forcewake_create(minor->debugfs_root, minor); |
358733e9 JB |
4731 | if (ret) |
4732 | return ret; | |
6a9c308d | 4733 | |
07144428 DL |
4734 | for (i = 0; i < ARRAY_SIZE(i915_pipe_crc_data); i++) { |
4735 | ret = i915_pipe_crc_create(minor->debugfs_root, minor, i); | |
4736 | if (ret) | |
4737 | return ret; | |
4738 | } | |
4739 | ||
34b9674c DV |
4740 | for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) { |
4741 | ret = i915_debugfs_create(minor->debugfs_root, minor, | |
4742 | i915_debugfs_files[i].name, | |
4743 | i915_debugfs_files[i].fops); | |
4744 | if (ret) | |
4745 | return ret; | |
4746 | } | |
40633219 | 4747 | |
27c202ad BG |
4748 | return drm_debugfs_create_files(i915_debugfs_list, |
4749 | I915_DEBUGFS_ENTRIES, | |
2017263e BG |
4750 | minor->debugfs_root, minor); |
4751 | } | |
4752 | ||
27c202ad | 4753 | void i915_debugfs_cleanup(struct drm_minor *minor) |
2017263e | 4754 | { |
34b9674c DV |
4755 | int i; |
4756 | ||
27c202ad BG |
4757 | drm_debugfs_remove_files(i915_debugfs_list, |
4758 | I915_DEBUGFS_ENTRIES, minor); | |
07144428 | 4759 | |
6d794d42 BW |
4760 | drm_debugfs_remove_files((struct drm_info_list *) &i915_forcewake_fops, |
4761 | 1, minor); | |
07144428 | 4762 | |
e309a997 | 4763 | for (i = 0; i < ARRAY_SIZE(i915_pipe_crc_data); i++) { |
07144428 DL |
4764 | struct drm_info_list *info_list = |
4765 | (struct drm_info_list *)&i915_pipe_crc_data[i]; | |
4766 | ||
4767 | drm_debugfs_remove_files(info_list, 1, minor); | |
4768 | } | |
4769 | ||
34b9674c DV |
4770 | for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) { |
4771 | struct drm_info_list *info_list = | |
4772 | (struct drm_info_list *) i915_debugfs_files[i].fops; | |
4773 | ||
4774 | drm_debugfs_remove_files(info_list, 1, minor); | |
4775 | } | |
2017263e | 4776 | } |