Commit | Line | Data |
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1da177e4 LT |
1 | /* i915_dma.c -- DMA support for the I915 -*- linux-c -*- |
2 | */ | |
0d6aa60b | 3 | /* |
1da177e4 LT |
4 | * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. |
5 | * All Rights Reserved. | |
bc54fd1a DA |
6 | * |
7 | * Permission is hereby granted, free of charge, to any person obtaining a | |
8 | * copy of this software and associated documentation files (the | |
9 | * "Software"), to deal in the Software without restriction, including | |
10 | * without limitation the rights to use, copy, modify, merge, publish, | |
11 | * distribute, sub license, and/or sell copies of the Software, and to | |
12 | * permit persons to whom the Software is furnished to do so, subject to | |
13 | * the following conditions: | |
14 | * | |
15 | * The above copyright notice and this permission notice (including the | |
16 | * next paragraph) shall be included in all copies or substantial portions | |
17 | * of the Software. | |
18 | * | |
19 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS | |
20 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
21 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. | |
22 | * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR | |
23 | * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, | |
24 | * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE | |
25 | * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. | |
26 | * | |
0d6aa60b | 27 | */ |
1da177e4 LT |
28 | |
29 | #include "drmP.h" | |
30 | #include "drm.h" | |
79e53945 | 31 | #include "drm_crtc_helper.h" |
785b93ef | 32 | #include "drm_fb_helper.h" |
79e53945 | 33 | #include "intel_drv.h" |
1da177e4 LT |
34 | #include "i915_drm.h" |
35 | #include "i915_drv.h" | |
1c5d22f7 | 36 | #include "i915_trace.h" |
28d52043 | 37 | #include <linux/vgaarb.h> |
c4804411 ZW |
38 | #include <linux/acpi.h> |
39 | #include <linux/pnp.h> | |
6a9ee8af | 40 | #include <linux/vga_switcheroo.h> |
1da177e4 | 41 | |
1da177e4 LT |
42 | /* Really want an OS-independent resettable timer. Would like to have |
43 | * this loop run for (eg) 3 sec, but have the timer reset every time | |
44 | * the head pointer changes, so that EBUSY only happens if the ring | |
45 | * actually stalls for (eg) 3 seconds. | |
46 | */ | |
84b1fd10 | 47 | int i915_wait_ring(struct drm_device * dev, int n, const char *caller) |
1da177e4 LT |
48 | { |
49 | drm_i915_private_t *dev_priv = dev->dev_private; | |
50 | drm_i915_ring_buffer_t *ring = &(dev_priv->ring); | |
d3a6d446 KP |
51 | u32 acthd_reg = IS_I965G(dev) ? ACTHD_I965 : ACTHD; |
52 | u32 last_acthd = I915_READ(acthd_reg); | |
53 | u32 acthd; | |
585fb111 | 54 | u32 last_head = I915_READ(PRB0_HEAD) & HEAD_ADDR; |
1da177e4 LT |
55 | int i; |
56 | ||
1c5d22f7 CW |
57 | trace_i915_ring_wait_begin (dev); |
58 | ||
d3a6d446 | 59 | for (i = 0; i < 100000; i++) { |
585fb111 | 60 | ring->head = I915_READ(PRB0_HEAD) & HEAD_ADDR; |
d3a6d446 | 61 | acthd = I915_READ(acthd_reg); |
1da177e4 LT |
62 | ring->space = ring->head - (ring->tail + 8); |
63 | if (ring->space < 0) | |
64 | ring->space += ring->Size; | |
1c5d22f7 CW |
65 | if (ring->space >= n) { |
66 | trace_i915_ring_wait_end (dev); | |
1da177e4 | 67 | return 0; |
1c5d22f7 | 68 | } |
1da177e4 | 69 | |
98787c05 CW |
70 | if (dev->primary->master) { |
71 | struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv; | |
72 | if (master_priv->sarea_priv) | |
73 | master_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT; | |
74 | } | |
75 | ||
1da177e4 LT |
76 | |
77 | if (ring->head != last_head) | |
78 | i = 0; | |
d3a6d446 KP |
79 | if (acthd != last_acthd) |
80 | i = 0; | |
1da177e4 LT |
81 | |
82 | last_head = ring->head; | |
d3a6d446 KP |
83 | last_acthd = acthd; |
84 | msleep_interruptible(10); | |
85 | ||
1da177e4 LT |
86 | } |
87 | ||
1c5d22f7 | 88 | trace_i915_ring_wait_end (dev); |
20caafa6 | 89 | return -EBUSY; |
1da177e4 LT |
90 | } |
91 | ||
0ef82af7 CW |
92 | /* As a ringbuffer is only allowed to wrap between instructions, fill |
93 | * the tail with NOOPs. | |
94 | */ | |
95 | int i915_wrap_ring(struct drm_device *dev) | |
96 | { | |
97 | drm_i915_private_t *dev_priv = dev->dev_private; | |
98 | volatile unsigned int *virt; | |
99 | int rem; | |
100 | ||
101 | rem = dev_priv->ring.Size - dev_priv->ring.tail; | |
102 | if (dev_priv->ring.space < rem) { | |
103 | int ret = i915_wait_ring(dev, rem, __func__); | |
104 | if (ret) | |
105 | return ret; | |
106 | } | |
107 | dev_priv->ring.space -= rem; | |
108 | ||
109 | virt = (unsigned int *) | |
110 | (dev_priv->ring.virtual_start + dev_priv->ring.tail); | |
111 | rem /= 4; | |
112 | while (rem--) | |
113 | *virt++ = MI_NOOP; | |
114 | ||
115 | dev_priv->ring.tail = 0; | |
116 | ||
117 | return 0; | |
118 | } | |
119 | ||
398c9cb2 KP |
120 | /** |
121 | * Sets up the hardware status page for devices that need a physical address | |
122 | * in the register. | |
123 | */ | |
3043c60c | 124 | static int i915_init_phys_hws(struct drm_device *dev) |
398c9cb2 KP |
125 | { |
126 | drm_i915_private_t *dev_priv = dev->dev_private; | |
127 | /* Program Hardware Status Page */ | |
128 | dev_priv->status_page_dmah = | |
e6be8d9d | 129 | drm_pci_alloc(dev, PAGE_SIZE, PAGE_SIZE); |
398c9cb2 KP |
130 | |
131 | if (!dev_priv->status_page_dmah) { | |
132 | DRM_ERROR("Can not allocate hardware status page\n"); | |
133 | return -ENOMEM; | |
134 | } | |
135 | dev_priv->hw_status_page = dev_priv->status_page_dmah->vaddr; | |
136 | dev_priv->dma_status_page = dev_priv->status_page_dmah->busaddr; | |
137 | ||
138 | memset(dev_priv->hw_status_page, 0, PAGE_SIZE); | |
139 | ||
9b974cc1 ZW |
140 | if (IS_I965G(dev)) |
141 | dev_priv->dma_status_page |= (dev_priv->dma_status_page >> 28) & | |
142 | 0xf0; | |
143 | ||
398c9cb2 | 144 | I915_WRITE(HWS_PGA, dev_priv->dma_status_page); |
8a4c47f3 | 145 | DRM_DEBUG_DRIVER("Enabled hardware status page\n"); |
398c9cb2 KP |
146 | return 0; |
147 | } | |
148 | ||
149 | /** | |
150 | * Frees the hardware status page, whether it's a physical address or a virtual | |
151 | * address set up by the X Server. | |
152 | */ | |
3043c60c | 153 | static void i915_free_hws(struct drm_device *dev) |
398c9cb2 KP |
154 | { |
155 | drm_i915_private_t *dev_priv = dev->dev_private; | |
156 | if (dev_priv->status_page_dmah) { | |
157 | drm_pci_free(dev, dev_priv->status_page_dmah); | |
158 | dev_priv->status_page_dmah = NULL; | |
159 | } | |
160 | ||
161 | if (dev_priv->status_gfx_addr) { | |
162 | dev_priv->status_gfx_addr = 0; | |
163 | drm_core_ioremapfree(&dev_priv->hws_map, dev); | |
164 | } | |
165 | ||
166 | /* Need to rewrite hardware status page */ | |
167 | I915_WRITE(HWS_PGA, 0x1ffff000); | |
168 | } | |
169 | ||
84b1fd10 | 170 | void i915_kernel_lost_context(struct drm_device * dev) |
1da177e4 LT |
171 | { |
172 | drm_i915_private_t *dev_priv = dev->dev_private; | |
7c1c2871 | 173 | struct drm_i915_master_private *master_priv; |
1da177e4 LT |
174 | drm_i915_ring_buffer_t *ring = &(dev_priv->ring); |
175 | ||
79e53945 JB |
176 | /* |
177 | * We should never lose context on the ring with modesetting | |
178 | * as we don't expose it to userspace | |
179 | */ | |
180 | if (drm_core_check_feature(dev, DRIVER_MODESET)) | |
181 | return; | |
182 | ||
585fb111 JB |
183 | ring->head = I915_READ(PRB0_HEAD) & HEAD_ADDR; |
184 | ring->tail = I915_READ(PRB0_TAIL) & TAIL_ADDR; | |
1da177e4 LT |
185 | ring->space = ring->head - (ring->tail + 8); |
186 | if (ring->space < 0) | |
187 | ring->space += ring->Size; | |
188 | ||
7c1c2871 DA |
189 | if (!dev->primary->master) |
190 | return; | |
191 | ||
192 | master_priv = dev->primary->master->driver_priv; | |
193 | if (ring->head == ring->tail && master_priv->sarea_priv) | |
194 | master_priv->sarea_priv->perf_boxes |= I915_BOX_RING_EMPTY; | |
1da177e4 LT |
195 | } |
196 | ||
84b1fd10 | 197 | static int i915_dma_cleanup(struct drm_device * dev) |
1da177e4 | 198 | { |
ba8bbcf6 | 199 | drm_i915_private_t *dev_priv = dev->dev_private; |
1da177e4 LT |
200 | /* Make sure interrupts are disabled here because the uninstall ioctl |
201 | * may not have been called from userspace and after dev_private | |
202 | * is freed, it's too late. | |
203 | */ | |
ed4cb414 | 204 | if (dev->irq_enabled) |
b5e89ed5 | 205 | drm_irq_uninstall(dev); |
1da177e4 | 206 | |
ba8bbcf6 JB |
207 | if (dev_priv->ring.virtual_start) { |
208 | drm_core_ioremapfree(&dev_priv->ring.map, dev); | |
3043c60c EA |
209 | dev_priv->ring.virtual_start = NULL; |
210 | dev_priv->ring.map.handle = NULL; | |
ba8bbcf6 JB |
211 | dev_priv->ring.map.size = 0; |
212 | } | |
dc7a9319 | 213 | |
398c9cb2 KP |
214 | /* Clear the HWS virtual address at teardown */ |
215 | if (I915_NEED_GFX_HWS(dev)) | |
216 | i915_free_hws(dev); | |
1da177e4 LT |
217 | |
218 | return 0; | |
219 | } | |
220 | ||
ba8bbcf6 | 221 | static int i915_initialize(struct drm_device * dev, drm_i915_init_t * init) |
1da177e4 | 222 | { |
ba8bbcf6 | 223 | drm_i915_private_t *dev_priv = dev->dev_private; |
7c1c2871 | 224 | struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv; |
1da177e4 | 225 | |
3a03ac1a DA |
226 | master_priv->sarea = drm_getsarea(dev); |
227 | if (master_priv->sarea) { | |
228 | master_priv->sarea_priv = (drm_i915_sarea_t *) | |
229 | ((u8 *)master_priv->sarea->handle + init->sarea_priv_offset); | |
230 | } else { | |
8a4c47f3 | 231 | DRM_DEBUG_DRIVER("sarea not found assuming DRI2 userspace\n"); |
3a03ac1a DA |
232 | } |
233 | ||
673a394b EA |
234 | if (init->ring_size != 0) { |
235 | if (dev_priv->ring.ring_obj != NULL) { | |
236 | i915_dma_cleanup(dev); | |
237 | DRM_ERROR("Client tried to initialize ringbuffer in " | |
238 | "GEM mode\n"); | |
239 | return -EINVAL; | |
240 | } | |
1da177e4 | 241 | |
673a394b | 242 | dev_priv->ring.Size = init->ring_size; |
1da177e4 | 243 | |
673a394b EA |
244 | dev_priv->ring.map.offset = init->ring_start; |
245 | dev_priv->ring.map.size = init->ring_size; | |
246 | dev_priv->ring.map.type = 0; | |
247 | dev_priv->ring.map.flags = 0; | |
248 | dev_priv->ring.map.mtrr = 0; | |
1da177e4 | 249 | |
6fb88588 | 250 | drm_core_ioremap_wc(&dev_priv->ring.map, dev); |
673a394b EA |
251 | |
252 | if (dev_priv->ring.map.handle == NULL) { | |
253 | i915_dma_cleanup(dev); | |
254 | DRM_ERROR("can not ioremap virtual address for" | |
255 | " ring buffer\n"); | |
256 | return -ENOMEM; | |
257 | } | |
1da177e4 LT |
258 | } |
259 | ||
260 | dev_priv->ring.virtual_start = dev_priv->ring.map.handle; | |
261 | ||
a6b54f3f | 262 | dev_priv->cpp = init->cpp; |
1da177e4 LT |
263 | dev_priv->back_offset = init->back_offset; |
264 | dev_priv->front_offset = init->front_offset; | |
265 | dev_priv->current_page = 0; | |
7c1c2871 DA |
266 | if (master_priv->sarea_priv) |
267 | master_priv->sarea_priv->pf_current_page = 0; | |
1da177e4 | 268 | |
1da177e4 LT |
269 | /* Allow hardware batchbuffers unless told otherwise. |
270 | */ | |
271 | dev_priv->allow_batchbuffer = 1; | |
272 | ||
1da177e4 LT |
273 | return 0; |
274 | } | |
275 | ||
84b1fd10 | 276 | static int i915_dma_resume(struct drm_device * dev) |
1da177e4 LT |
277 | { |
278 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
279 | ||
8a4c47f3 | 280 | DRM_DEBUG_DRIVER("%s\n", __func__); |
1da177e4 | 281 | |
1da177e4 LT |
282 | if (dev_priv->ring.map.handle == NULL) { |
283 | DRM_ERROR("can not ioremap virtual address for" | |
284 | " ring buffer\n"); | |
20caafa6 | 285 | return -ENOMEM; |
1da177e4 LT |
286 | } |
287 | ||
288 | /* Program Hardware Status Page */ | |
289 | if (!dev_priv->hw_status_page) { | |
290 | DRM_ERROR("Can not find hardware status page\n"); | |
20caafa6 | 291 | return -EINVAL; |
1da177e4 | 292 | } |
8a4c47f3 | 293 | DRM_DEBUG_DRIVER("hw status page @ %p\n", |
be25ed9c | 294 | dev_priv->hw_status_page); |
1da177e4 | 295 | |
dc7a9319 | 296 | if (dev_priv->status_gfx_addr != 0) |
585fb111 | 297 | I915_WRITE(HWS_PGA, dev_priv->status_gfx_addr); |
dc7a9319 | 298 | else |
585fb111 | 299 | I915_WRITE(HWS_PGA, dev_priv->dma_status_page); |
8a4c47f3 | 300 | DRM_DEBUG_DRIVER("Enabled hardware status page\n"); |
1da177e4 LT |
301 | |
302 | return 0; | |
303 | } | |
304 | ||
c153f45f EA |
305 | static int i915_dma_init(struct drm_device *dev, void *data, |
306 | struct drm_file *file_priv) | |
1da177e4 | 307 | { |
c153f45f | 308 | drm_i915_init_t *init = data; |
1da177e4 LT |
309 | int retcode = 0; |
310 | ||
c153f45f | 311 | switch (init->func) { |
1da177e4 | 312 | case I915_INIT_DMA: |
ba8bbcf6 | 313 | retcode = i915_initialize(dev, init); |
1da177e4 LT |
314 | break; |
315 | case I915_CLEANUP_DMA: | |
316 | retcode = i915_dma_cleanup(dev); | |
317 | break; | |
318 | case I915_RESUME_DMA: | |
0d6aa60b | 319 | retcode = i915_dma_resume(dev); |
1da177e4 LT |
320 | break; |
321 | default: | |
20caafa6 | 322 | retcode = -EINVAL; |
1da177e4 LT |
323 | break; |
324 | } | |
325 | ||
326 | return retcode; | |
327 | } | |
328 | ||
329 | /* Implement basically the same security restrictions as hardware does | |
330 | * for MI_BATCH_NON_SECURE. These can be made stricter at any time. | |
331 | * | |
332 | * Most of the calculations below involve calculating the size of a | |
333 | * particular instruction. It's important to get the size right as | |
334 | * that tells us where the next instruction to check is. Any illegal | |
335 | * instruction detected will be given a size of zero, which is a | |
336 | * signal to abort the rest of the buffer. | |
337 | */ | |
338 | static int do_validate_cmd(int cmd) | |
339 | { | |
340 | switch (((cmd >> 29) & 0x7)) { | |
341 | case 0x0: | |
342 | switch ((cmd >> 23) & 0x3f) { | |
343 | case 0x0: | |
344 | return 1; /* MI_NOOP */ | |
345 | case 0x4: | |
346 | return 1; /* MI_FLUSH */ | |
347 | default: | |
348 | return 0; /* disallow everything else */ | |
349 | } | |
350 | break; | |
351 | case 0x1: | |
352 | return 0; /* reserved */ | |
353 | case 0x2: | |
354 | return (cmd & 0xff) + 2; /* 2d commands */ | |
355 | case 0x3: | |
356 | if (((cmd >> 24) & 0x1f) <= 0x18) | |
357 | return 1; | |
358 | ||
359 | switch ((cmd >> 24) & 0x1f) { | |
360 | case 0x1c: | |
361 | return 1; | |
362 | case 0x1d: | |
b5e89ed5 | 363 | switch ((cmd >> 16) & 0xff) { |
1da177e4 LT |
364 | case 0x3: |
365 | return (cmd & 0x1f) + 2; | |
366 | case 0x4: | |
367 | return (cmd & 0xf) + 2; | |
368 | default: | |
369 | return (cmd & 0xffff) + 2; | |
370 | } | |
371 | case 0x1e: | |
372 | if (cmd & (1 << 23)) | |
373 | return (cmd & 0xffff) + 1; | |
374 | else | |
375 | return 1; | |
376 | case 0x1f: | |
377 | if ((cmd & (1 << 23)) == 0) /* inline vertices */ | |
378 | return (cmd & 0x1ffff) + 2; | |
379 | else if (cmd & (1 << 17)) /* indirect random */ | |
380 | if ((cmd & 0xffff) == 0) | |
381 | return 0; /* unknown length, too hard */ | |
382 | else | |
383 | return (((cmd & 0xffff) + 1) / 2) + 1; | |
384 | else | |
385 | return 2; /* indirect sequential */ | |
386 | default: | |
387 | return 0; | |
388 | } | |
389 | default: | |
390 | return 0; | |
391 | } | |
392 | ||
393 | return 0; | |
394 | } | |
395 | ||
396 | static int validate_cmd(int cmd) | |
397 | { | |
398 | int ret = do_validate_cmd(cmd); | |
399 | ||
bc5f4523 | 400 | /* printk("validate_cmd( %x ): %d\n", cmd, ret); */ |
1da177e4 LT |
401 | |
402 | return ret; | |
403 | } | |
404 | ||
201361a5 | 405 | static int i915_emit_cmds(struct drm_device * dev, int *buffer, int dwords) |
1da177e4 LT |
406 | { |
407 | drm_i915_private_t *dev_priv = dev->dev_private; | |
408 | int i; | |
409 | RING_LOCALS; | |
410 | ||
de227f5f | 411 | if ((dwords+1) * sizeof(int) >= dev_priv->ring.Size - 8) |
20caafa6 | 412 | return -EINVAL; |
de227f5f | 413 | |
c29b669c | 414 | BEGIN_LP_RING((dwords+1)&~1); |
de227f5f | 415 | |
1da177e4 LT |
416 | for (i = 0; i < dwords;) { |
417 | int cmd, sz; | |
418 | ||
201361a5 | 419 | cmd = buffer[i]; |
1da177e4 | 420 | |
1da177e4 | 421 | if ((sz = validate_cmd(cmd)) == 0 || i + sz > dwords) |
20caafa6 | 422 | return -EINVAL; |
1da177e4 | 423 | |
1da177e4 LT |
424 | OUT_RING(cmd); |
425 | ||
426 | while (++i, --sz) { | |
201361a5 | 427 | OUT_RING(buffer[i]); |
1da177e4 | 428 | } |
1da177e4 LT |
429 | } |
430 | ||
de227f5f DA |
431 | if (dwords & 1) |
432 | OUT_RING(0); | |
433 | ||
434 | ADVANCE_LP_RING(); | |
435 | ||
1da177e4 LT |
436 | return 0; |
437 | } | |
438 | ||
673a394b EA |
439 | int |
440 | i915_emit_box(struct drm_device *dev, | |
201361a5 | 441 | struct drm_clip_rect *boxes, |
673a394b | 442 | int i, int DR1, int DR4) |
1da177e4 LT |
443 | { |
444 | drm_i915_private_t *dev_priv = dev->dev_private; | |
201361a5 | 445 | struct drm_clip_rect box = boxes[i]; |
1da177e4 LT |
446 | RING_LOCALS; |
447 | ||
1da177e4 LT |
448 | if (box.y2 <= box.y1 || box.x2 <= box.x1 || box.y2 <= 0 || box.x2 <= 0) { |
449 | DRM_ERROR("Bad box %d,%d..%d,%d\n", | |
450 | box.x1, box.y1, box.x2, box.y2); | |
20caafa6 | 451 | return -EINVAL; |
1da177e4 LT |
452 | } |
453 | ||
c29b669c AH |
454 | if (IS_I965G(dev)) { |
455 | BEGIN_LP_RING(4); | |
456 | OUT_RING(GFX_OP_DRAWRECT_INFO_I965); | |
457 | OUT_RING((box.x1 & 0xffff) | (box.y1 << 16)); | |
78eca43d | 458 | OUT_RING(((box.x2 - 1) & 0xffff) | ((box.y2 - 1) << 16)); |
c29b669c AH |
459 | OUT_RING(DR4); |
460 | ADVANCE_LP_RING(); | |
461 | } else { | |
462 | BEGIN_LP_RING(6); | |
463 | OUT_RING(GFX_OP_DRAWRECT_INFO); | |
464 | OUT_RING(DR1); | |
465 | OUT_RING((box.x1 & 0xffff) | (box.y1 << 16)); | |
466 | OUT_RING(((box.x2 - 1) & 0xffff) | ((box.y2 - 1) << 16)); | |
467 | OUT_RING(DR4); | |
468 | OUT_RING(0); | |
469 | ADVANCE_LP_RING(); | |
470 | } | |
1da177e4 LT |
471 | |
472 | return 0; | |
473 | } | |
474 | ||
c29b669c AH |
475 | /* XXX: Emitting the counter should really be moved to part of the IRQ |
476 | * emit. For now, do it in both places: | |
477 | */ | |
478 | ||
84b1fd10 | 479 | static void i915_emit_breadcrumb(struct drm_device *dev) |
de227f5f DA |
480 | { |
481 | drm_i915_private_t *dev_priv = dev->dev_private; | |
7c1c2871 | 482 | struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv; |
de227f5f DA |
483 | RING_LOCALS; |
484 | ||
c99b058f | 485 | dev_priv->counter++; |
af6061af | 486 | if (dev_priv->counter > 0x7FFFFFFFUL) |
c99b058f | 487 | dev_priv->counter = 0; |
7c1c2871 DA |
488 | if (master_priv->sarea_priv) |
489 | master_priv->sarea_priv->last_enqueue = dev_priv->counter; | |
de227f5f DA |
490 | |
491 | BEGIN_LP_RING(4); | |
585fb111 | 492 | OUT_RING(MI_STORE_DWORD_INDEX); |
0baf823a | 493 | OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT); |
de227f5f DA |
494 | OUT_RING(dev_priv->counter); |
495 | OUT_RING(0); | |
496 | ADVANCE_LP_RING(); | |
497 | } | |
498 | ||
84b1fd10 | 499 | static int i915_dispatch_cmdbuffer(struct drm_device * dev, |
201361a5 EA |
500 | drm_i915_cmdbuffer_t *cmd, |
501 | struct drm_clip_rect *cliprects, | |
502 | void *cmdbuf) | |
1da177e4 LT |
503 | { |
504 | int nbox = cmd->num_cliprects; | |
505 | int i = 0, count, ret; | |
506 | ||
507 | if (cmd->sz & 0x3) { | |
508 | DRM_ERROR("alignment"); | |
20caafa6 | 509 | return -EINVAL; |
1da177e4 LT |
510 | } |
511 | ||
512 | i915_kernel_lost_context(dev); | |
513 | ||
514 | count = nbox ? nbox : 1; | |
515 | ||
516 | for (i = 0; i < count; i++) { | |
517 | if (i < nbox) { | |
201361a5 | 518 | ret = i915_emit_box(dev, cliprects, i, |
1da177e4 LT |
519 | cmd->DR1, cmd->DR4); |
520 | if (ret) | |
521 | return ret; | |
522 | } | |
523 | ||
201361a5 | 524 | ret = i915_emit_cmds(dev, cmdbuf, cmd->sz / 4); |
1da177e4 LT |
525 | if (ret) |
526 | return ret; | |
527 | } | |
528 | ||
de227f5f | 529 | i915_emit_breadcrumb(dev); |
1da177e4 LT |
530 | return 0; |
531 | } | |
532 | ||
84b1fd10 | 533 | static int i915_dispatch_batchbuffer(struct drm_device * dev, |
201361a5 EA |
534 | drm_i915_batchbuffer_t * batch, |
535 | struct drm_clip_rect *cliprects) | |
1da177e4 LT |
536 | { |
537 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1da177e4 LT |
538 | int nbox = batch->num_cliprects; |
539 | int i = 0, count; | |
540 | RING_LOCALS; | |
541 | ||
542 | if ((batch->start | batch->used) & 0x7) { | |
543 | DRM_ERROR("alignment"); | |
20caafa6 | 544 | return -EINVAL; |
1da177e4 LT |
545 | } |
546 | ||
547 | i915_kernel_lost_context(dev); | |
548 | ||
549 | count = nbox ? nbox : 1; | |
550 | ||
551 | for (i = 0; i < count; i++) { | |
552 | if (i < nbox) { | |
201361a5 | 553 | int ret = i915_emit_box(dev, cliprects, i, |
1da177e4 LT |
554 | batch->DR1, batch->DR4); |
555 | if (ret) | |
556 | return ret; | |
557 | } | |
558 | ||
0790d5e1 | 559 | if (!IS_I830(dev) && !IS_845G(dev)) { |
1da177e4 | 560 | BEGIN_LP_RING(2); |
21f16289 DA |
561 | if (IS_I965G(dev)) { |
562 | OUT_RING(MI_BATCH_BUFFER_START | (2 << 6) | MI_BATCH_NON_SECURE_I965); | |
563 | OUT_RING(batch->start); | |
564 | } else { | |
565 | OUT_RING(MI_BATCH_BUFFER_START | (2 << 6)); | |
566 | OUT_RING(batch->start | MI_BATCH_NON_SECURE); | |
567 | } | |
1da177e4 LT |
568 | ADVANCE_LP_RING(); |
569 | } else { | |
570 | BEGIN_LP_RING(4); | |
571 | OUT_RING(MI_BATCH_BUFFER); | |
572 | OUT_RING(batch->start | MI_BATCH_NON_SECURE); | |
573 | OUT_RING(batch->start + batch->used - 4); | |
574 | OUT_RING(0); | |
575 | ADVANCE_LP_RING(); | |
576 | } | |
577 | } | |
578 | ||
de227f5f | 579 | i915_emit_breadcrumb(dev); |
1da177e4 LT |
580 | |
581 | return 0; | |
582 | } | |
583 | ||
af6061af | 584 | static int i915_dispatch_flip(struct drm_device * dev) |
1da177e4 LT |
585 | { |
586 | drm_i915_private_t *dev_priv = dev->dev_private; | |
7c1c2871 DA |
587 | struct drm_i915_master_private *master_priv = |
588 | dev->primary->master->driver_priv; | |
1da177e4 LT |
589 | RING_LOCALS; |
590 | ||
7c1c2871 | 591 | if (!master_priv->sarea_priv) |
c99b058f KH |
592 | return -EINVAL; |
593 | ||
8a4c47f3 | 594 | DRM_DEBUG_DRIVER("%s: page=%d pfCurrentPage=%d\n", |
be25ed9c | 595 | __func__, |
596 | dev_priv->current_page, | |
597 | master_priv->sarea_priv->pf_current_page); | |
1da177e4 | 598 | |
af6061af DA |
599 | i915_kernel_lost_context(dev); |
600 | ||
601 | BEGIN_LP_RING(2); | |
585fb111 | 602 | OUT_RING(MI_FLUSH | MI_READ_FLUSH); |
af6061af DA |
603 | OUT_RING(0); |
604 | ADVANCE_LP_RING(); | |
1da177e4 | 605 | |
af6061af DA |
606 | BEGIN_LP_RING(6); |
607 | OUT_RING(CMD_OP_DISPLAYBUFFER_INFO | ASYNC_FLIP); | |
608 | OUT_RING(0); | |
609 | if (dev_priv->current_page == 0) { | |
610 | OUT_RING(dev_priv->back_offset); | |
611 | dev_priv->current_page = 1; | |
1da177e4 | 612 | } else { |
af6061af DA |
613 | OUT_RING(dev_priv->front_offset); |
614 | dev_priv->current_page = 0; | |
1da177e4 | 615 | } |
af6061af DA |
616 | OUT_RING(0); |
617 | ADVANCE_LP_RING(); | |
1da177e4 | 618 | |
af6061af DA |
619 | BEGIN_LP_RING(2); |
620 | OUT_RING(MI_WAIT_FOR_EVENT | MI_WAIT_FOR_PLANE_A_FLIP); | |
621 | OUT_RING(0); | |
622 | ADVANCE_LP_RING(); | |
1da177e4 | 623 | |
7c1c2871 | 624 | master_priv->sarea_priv->last_enqueue = dev_priv->counter++; |
1da177e4 LT |
625 | |
626 | BEGIN_LP_RING(4); | |
585fb111 | 627 | OUT_RING(MI_STORE_DWORD_INDEX); |
0baf823a | 628 | OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT); |
af6061af DA |
629 | OUT_RING(dev_priv->counter); |
630 | OUT_RING(0); | |
1da177e4 LT |
631 | ADVANCE_LP_RING(); |
632 | ||
7c1c2871 | 633 | master_priv->sarea_priv->pf_current_page = dev_priv->current_page; |
af6061af | 634 | return 0; |
1da177e4 LT |
635 | } |
636 | ||
84b1fd10 | 637 | static int i915_quiescent(struct drm_device * dev) |
1da177e4 LT |
638 | { |
639 | drm_i915_private_t *dev_priv = dev->dev_private; | |
640 | ||
641 | i915_kernel_lost_context(dev); | |
bf9d8929 | 642 | return i915_wait_ring(dev, dev_priv->ring.Size - 8, __func__); |
1da177e4 LT |
643 | } |
644 | ||
c153f45f EA |
645 | static int i915_flush_ioctl(struct drm_device *dev, void *data, |
646 | struct drm_file *file_priv) | |
1da177e4 | 647 | { |
546b0974 EA |
648 | int ret; |
649 | ||
650 | RING_LOCK_TEST_WITH_RETURN(dev, file_priv); | |
1da177e4 | 651 | |
546b0974 EA |
652 | mutex_lock(&dev->struct_mutex); |
653 | ret = i915_quiescent(dev); | |
654 | mutex_unlock(&dev->struct_mutex); | |
655 | ||
656 | return ret; | |
1da177e4 LT |
657 | } |
658 | ||
c153f45f EA |
659 | static int i915_batchbuffer(struct drm_device *dev, void *data, |
660 | struct drm_file *file_priv) | |
1da177e4 | 661 | { |
1da177e4 | 662 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
7c1c2871 | 663 | struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv; |
1da177e4 | 664 | drm_i915_sarea_t *sarea_priv = (drm_i915_sarea_t *) |
7c1c2871 | 665 | master_priv->sarea_priv; |
c153f45f | 666 | drm_i915_batchbuffer_t *batch = data; |
1da177e4 | 667 | int ret; |
201361a5 | 668 | struct drm_clip_rect *cliprects = NULL; |
1da177e4 LT |
669 | |
670 | if (!dev_priv->allow_batchbuffer) { | |
671 | DRM_ERROR("Batchbuffer ioctl disabled\n"); | |
20caafa6 | 672 | return -EINVAL; |
1da177e4 LT |
673 | } |
674 | ||
8a4c47f3 | 675 | DRM_DEBUG_DRIVER("i915 batchbuffer, start %x used %d cliprects %d\n", |
be25ed9c | 676 | batch->start, batch->used, batch->num_cliprects); |
1da177e4 | 677 | |
546b0974 | 678 | RING_LOCK_TEST_WITH_RETURN(dev, file_priv); |
1da177e4 | 679 | |
201361a5 EA |
680 | if (batch->num_cliprects < 0) |
681 | return -EINVAL; | |
682 | ||
683 | if (batch->num_cliprects) { | |
9a298b2a EA |
684 | cliprects = kcalloc(batch->num_cliprects, |
685 | sizeof(struct drm_clip_rect), | |
686 | GFP_KERNEL); | |
201361a5 EA |
687 | if (cliprects == NULL) |
688 | return -ENOMEM; | |
689 | ||
690 | ret = copy_from_user(cliprects, batch->cliprects, | |
691 | batch->num_cliprects * | |
692 | sizeof(struct drm_clip_rect)); | |
693 | if (ret != 0) | |
694 | goto fail_free; | |
695 | } | |
1da177e4 | 696 | |
546b0974 | 697 | mutex_lock(&dev->struct_mutex); |
201361a5 | 698 | ret = i915_dispatch_batchbuffer(dev, batch, cliprects); |
546b0974 | 699 | mutex_unlock(&dev->struct_mutex); |
1da177e4 | 700 | |
c99b058f | 701 | if (sarea_priv) |
0baf823a | 702 | sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv); |
201361a5 EA |
703 | |
704 | fail_free: | |
9a298b2a | 705 | kfree(cliprects); |
201361a5 | 706 | |
1da177e4 LT |
707 | return ret; |
708 | } | |
709 | ||
c153f45f EA |
710 | static int i915_cmdbuffer(struct drm_device *dev, void *data, |
711 | struct drm_file *file_priv) | |
1da177e4 | 712 | { |
1da177e4 | 713 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
7c1c2871 | 714 | struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv; |
1da177e4 | 715 | drm_i915_sarea_t *sarea_priv = (drm_i915_sarea_t *) |
7c1c2871 | 716 | master_priv->sarea_priv; |
c153f45f | 717 | drm_i915_cmdbuffer_t *cmdbuf = data; |
201361a5 EA |
718 | struct drm_clip_rect *cliprects = NULL; |
719 | void *batch_data; | |
1da177e4 LT |
720 | int ret; |
721 | ||
8a4c47f3 | 722 | DRM_DEBUG_DRIVER("i915 cmdbuffer, buf %p sz %d cliprects %d\n", |
be25ed9c | 723 | cmdbuf->buf, cmdbuf->sz, cmdbuf->num_cliprects); |
1da177e4 | 724 | |
546b0974 | 725 | RING_LOCK_TEST_WITH_RETURN(dev, file_priv); |
1da177e4 | 726 | |
201361a5 EA |
727 | if (cmdbuf->num_cliprects < 0) |
728 | return -EINVAL; | |
729 | ||
9a298b2a | 730 | batch_data = kmalloc(cmdbuf->sz, GFP_KERNEL); |
201361a5 EA |
731 | if (batch_data == NULL) |
732 | return -ENOMEM; | |
733 | ||
734 | ret = copy_from_user(batch_data, cmdbuf->buf, cmdbuf->sz); | |
735 | if (ret != 0) | |
736 | goto fail_batch_free; | |
737 | ||
738 | if (cmdbuf->num_cliprects) { | |
9a298b2a EA |
739 | cliprects = kcalloc(cmdbuf->num_cliprects, |
740 | sizeof(struct drm_clip_rect), GFP_KERNEL); | |
a40e8d31 OA |
741 | if (cliprects == NULL) { |
742 | ret = -ENOMEM; | |
201361a5 | 743 | goto fail_batch_free; |
a40e8d31 | 744 | } |
201361a5 EA |
745 | |
746 | ret = copy_from_user(cliprects, cmdbuf->cliprects, | |
747 | cmdbuf->num_cliprects * | |
748 | sizeof(struct drm_clip_rect)); | |
749 | if (ret != 0) | |
750 | goto fail_clip_free; | |
1da177e4 LT |
751 | } |
752 | ||
546b0974 | 753 | mutex_lock(&dev->struct_mutex); |
201361a5 | 754 | ret = i915_dispatch_cmdbuffer(dev, cmdbuf, cliprects, batch_data); |
546b0974 | 755 | mutex_unlock(&dev->struct_mutex); |
1da177e4 LT |
756 | if (ret) { |
757 | DRM_ERROR("i915_dispatch_cmdbuffer failed\n"); | |
355d7f37 | 758 | goto fail_clip_free; |
1da177e4 LT |
759 | } |
760 | ||
c99b058f | 761 | if (sarea_priv) |
0baf823a | 762 | sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv); |
201361a5 | 763 | |
201361a5 | 764 | fail_clip_free: |
9a298b2a | 765 | kfree(cliprects); |
355d7f37 | 766 | fail_batch_free: |
9a298b2a | 767 | kfree(batch_data); |
201361a5 EA |
768 | |
769 | return ret; | |
1da177e4 LT |
770 | } |
771 | ||
c153f45f EA |
772 | static int i915_flip_bufs(struct drm_device *dev, void *data, |
773 | struct drm_file *file_priv) | |
1da177e4 | 774 | { |
546b0974 EA |
775 | int ret; |
776 | ||
8a4c47f3 | 777 | DRM_DEBUG_DRIVER("%s\n", __func__); |
1da177e4 | 778 | |
546b0974 | 779 | RING_LOCK_TEST_WITH_RETURN(dev, file_priv); |
1da177e4 | 780 | |
546b0974 EA |
781 | mutex_lock(&dev->struct_mutex); |
782 | ret = i915_dispatch_flip(dev); | |
783 | mutex_unlock(&dev->struct_mutex); | |
784 | ||
785 | return ret; | |
1da177e4 LT |
786 | } |
787 | ||
c153f45f EA |
788 | static int i915_getparam(struct drm_device *dev, void *data, |
789 | struct drm_file *file_priv) | |
1da177e4 | 790 | { |
1da177e4 | 791 | drm_i915_private_t *dev_priv = dev->dev_private; |
c153f45f | 792 | drm_i915_getparam_t *param = data; |
1da177e4 LT |
793 | int value; |
794 | ||
795 | if (!dev_priv) { | |
3e684eae | 796 | DRM_ERROR("called with no initialization\n"); |
20caafa6 | 797 | return -EINVAL; |
1da177e4 LT |
798 | } |
799 | ||
c153f45f | 800 | switch (param->param) { |
1da177e4 | 801 | case I915_PARAM_IRQ_ACTIVE: |
0a3e67a4 | 802 | value = dev->pdev->irq ? 1 : 0; |
1da177e4 LT |
803 | break; |
804 | case I915_PARAM_ALLOW_BATCHBUFFER: | |
805 | value = dev_priv->allow_batchbuffer ? 1 : 0; | |
806 | break; | |
0d6aa60b DA |
807 | case I915_PARAM_LAST_DISPATCH: |
808 | value = READ_BREADCRUMB(dev_priv); | |
809 | break; | |
ed4c9c4a KH |
810 | case I915_PARAM_CHIPSET_ID: |
811 | value = dev->pci_device; | |
812 | break; | |
673a394b | 813 | case I915_PARAM_HAS_GEM: |
ac5c4e76 | 814 | value = dev_priv->has_gem; |
673a394b | 815 | break; |
0f973f27 JB |
816 | case I915_PARAM_NUM_FENCES_AVAIL: |
817 | value = dev_priv->num_fence_regs - dev_priv->fence_reg_start; | |
818 | break; | |
02e792fb DV |
819 | case I915_PARAM_HAS_OVERLAY: |
820 | value = dev_priv->overlay ? 1 : 0; | |
821 | break; | |
e9560f7c JB |
822 | case I915_PARAM_HAS_PAGEFLIPPING: |
823 | value = 1; | |
824 | break; | |
76446cac JB |
825 | case I915_PARAM_HAS_EXECBUF2: |
826 | /* depends on GEM */ | |
827 | value = dev_priv->has_gem; | |
828 | break; | |
1da177e4 | 829 | default: |
8a4c47f3 | 830 | DRM_DEBUG_DRIVER("Unknown parameter %d\n", |
76446cac | 831 | param->param); |
20caafa6 | 832 | return -EINVAL; |
1da177e4 LT |
833 | } |
834 | ||
c153f45f | 835 | if (DRM_COPY_TO_USER(param->value, &value, sizeof(int))) { |
1da177e4 | 836 | DRM_ERROR("DRM_COPY_TO_USER failed\n"); |
20caafa6 | 837 | return -EFAULT; |
1da177e4 LT |
838 | } |
839 | ||
840 | return 0; | |
841 | } | |
842 | ||
c153f45f EA |
843 | static int i915_setparam(struct drm_device *dev, void *data, |
844 | struct drm_file *file_priv) | |
1da177e4 | 845 | { |
1da177e4 | 846 | drm_i915_private_t *dev_priv = dev->dev_private; |
c153f45f | 847 | drm_i915_setparam_t *param = data; |
1da177e4 LT |
848 | |
849 | if (!dev_priv) { | |
3e684eae | 850 | DRM_ERROR("called with no initialization\n"); |
20caafa6 | 851 | return -EINVAL; |
1da177e4 LT |
852 | } |
853 | ||
c153f45f | 854 | switch (param->param) { |
1da177e4 | 855 | case I915_SETPARAM_USE_MI_BATCHBUFFER_START: |
1da177e4 LT |
856 | break; |
857 | case I915_SETPARAM_TEX_LRU_LOG_GRANULARITY: | |
c153f45f | 858 | dev_priv->tex_lru_log_granularity = param->value; |
1da177e4 LT |
859 | break; |
860 | case I915_SETPARAM_ALLOW_BATCHBUFFER: | |
c153f45f | 861 | dev_priv->allow_batchbuffer = param->value; |
1da177e4 | 862 | break; |
0f973f27 JB |
863 | case I915_SETPARAM_NUM_USED_FENCES: |
864 | if (param->value > dev_priv->num_fence_regs || | |
865 | param->value < 0) | |
866 | return -EINVAL; | |
867 | /* Userspace can use first N regs */ | |
868 | dev_priv->fence_reg_start = param->value; | |
869 | break; | |
1da177e4 | 870 | default: |
8a4c47f3 | 871 | DRM_DEBUG_DRIVER("unknown parameter %d\n", |
be25ed9c | 872 | param->param); |
20caafa6 | 873 | return -EINVAL; |
1da177e4 LT |
874 | } |
875 | ||
876 | return 0; | |
877 | } | |
878 | ||
c153f45f EA |
879 | static int i915_set_status_page(struct drm_device *dev, void *data, |
880 | struct drm_file *file_priv) | |
dc7a9319 | 881 | { |
dc7a9319 | 882 | drm_i915_private_t *dev_priv = dev->dev_private; |
c153f45f | 883 | drm_i915_hws_addr_t *hws = data; |
b39d50e5 ZW |
884 | |
885 | if (!I915_NEED_GFX_HWS(dev)) | |
886 | return -EINVAL; | |
dc7a9319 WZ |
887 | |
888 | if (!dev_priv) { | |
3e684eae | 889 | DRM_ERROR("called with no initialization\n"); |
20caafa6 | 890 | return -EINVAL; |
dc7a9319 | 891 | } |
dc7a9319 | 892 | |
79e53945 JB |
893 | if (drm_core_check_feature(dev, DRIVER_MODESET)) { |
894 | WARN(1, "tried to set status page when mode setting active\n"); | |
895 | return 0; | |
896 | } | |
897 | ||
8a4c47f3 | 898 | DRM_DEBUG_DRIVER("set status page addr 0x%08x\n", (u32)hws->addr); |
c153f45f EA |
899 | |
900 | dev_priv->status_gfx_addr = hws->addr & (0x1ffff<<12); | |
dc7a9319 | 901 | |
8b409580 | 902 | dev_priv->hws_map.offset = dev->agp->base + hws->addr; |
dc7a9319 WZ |
903 | dev_priv->hws_map.size = 4*1024; |
904 | dev_priv->hws_map.type = 0; | |
905 | dev_priv->hws_map.flags = 0; | |
906 | dev_priv->hws_map.mtrr = 0; | |
907 | ||
dd0910b3 | 908 | drm_core_ioremap_wc(&dev_priv->hws_map, dev); |
dc7a9319 | 909 | if (dev_priv->hws_map.handle == NULL) { |
dc7a9319 WZ |
910 | i915_dma_cleanup(dev); |
911 | dev_priv->status_gfx_addr = 0; | |
912 | DRM_ERROR("can not ioremap virtual address for" | |
913 | " G33 hw status page\n"); | |
20caafa6 | 914 | return -ENOMEM; |
dc7a9319 WZ |
915 | } |
916 | dev_priv->hw_status_page = dev_priv->hws_map.handle; | |
917 | ||
918 | memset(dev_priv->hw_status_page, 0, PAGE_SIZE); | |
585fb111 | 919 | I915_WRITE(HWS_PGA, dev_priv->status_gfx_addr); |
8a4c47f3 | 920 | DRM_DEBUG_DRIVER("load hws HWS_PGA with gfx mem 0x%x\n", |
be25ed9c | 921 | dev_priv->status_gfx_addr); |
8a4c47f3 | 922 | DRM_DEBUG_DRIVER("load hws at %p\n", |
be25ed9c | 923 | dev_priv->hw_status_page); |
dc7a9319 WZ |
924 | return 0; |
925 | } | |
926 | ||
ec2a4c3f DA |
927 | static int i915_get_bridge_dev(struct drm_device *dev) |
928 | { | |
929 | struct drm_i915_private *dev_priv = dev->dev_private; | |
930 | ||
931 | dev_priv->bridge_dev = pci_get_bus_and_slot(0, PCI_DEVFN(0,0)); | |
932 | if (!dev_priv->bridge_dev) { | |
933 | DRM_ERROR("bridge device not found\n"); | |
934 | return -1; | |
935 | } | |
936 | return 0; | |
937 | } | |
938 | ||
c4804411 ZW |
939 | #define MCHBAR_I915 0x44 |
940 | #define MCHBAR_I965 0x48 | |
941 | #define MCHBAR_SIZE (4*4096) | |
942 | ||
943 | #define DEVEN_REG 0x54 | |
944 | #define DEVEN_MCHBAR_EN (1 << 28) | |
945 | ||
946 | /* Allocate space for the MCH regs if needed, return nonzero on error */ | |
947 | static int | |
948 | intel_alloc_mchbar_resource(struct drm_device *dev) | |
949 | { | |
950 | drm_i915_private_t *dev_priv = dev->dev_private; | |
951 | int reg = IS_I965G(dev) ? MCHBAR_I965 : MCHBAR_I915; | |
952 | u32 temp_lo, temp_hi = 0; | |
953 | u64 mchbar_addr; | |
954 | int ret = 0; | |
955 | ||
956 | if (IS_I965G(dev)) | |
957 | pci_read_config_dword(dev_priv->bridge_dev, reg + 4, &temp_hi); | |
958 | pci_read_config_dword(dev_priv->bridge_dev, reg, &temp_lo); | |
959 | mchbar_addr = ((u64)temp_hi << 32) | temp_lo; | |
960 | ||
961 | /* If ACPI doesn't have it, assume we need to allocate it ourselves */ | |
962 | #ifdef CONFIG_PNP | |
963 | if (mchbar_addr && | |
964 | pnp_range_reserved(mchbar_addr, mchbar_addr + MCHBAR_SIZE)) { | |
965 | ret = 0; | |
966 | goto out; | |
967 | } | |
968 | #endif | |
969 | ||
970 | /* Get some space for it */ | |
971 | ret = pci_bus_alloc_resource(dev_priv->bridge_dev->bus, &dev_priv->mch_res, | |
972 | MCHBAR_SIZE, MCHBAR_SIZE, | |
973 | PCIBIOS_MIN_MEM, | |
974 | 0, pcibios_align_resource, | |
975 | dev_priv->bridge_dev); | |
976 | if (ret) { | |
977 | DRM_DEBUG_DRIVER("failed bus alloc: %d\n", ret); | |
978 | dev_priv->mch_res.start = 0; | |
979 | goto out; | |
980 | } | |
981 | ||
982 | if (IS_I965G(dev)) | |
983 | pci_write_config_dword(dev_priv->bridge_dev, reg + 4, | |
984 | upper_32_bits(dev_priv->mch_res.start)); | |
985 | ||
986 | pci_write_config_dword(dev_priv->bridge_dev, reg, | |
987 | lower_32_bits(dev_priv->mch_res.start)); | |
988 | out: | |
989 | return ret; | |
990 | } | |
991 | ||
992 | /* Setup MCHBAR if possible, return true if we should disable it again */ | |
993 | static void | |
994 | intel_setup_mchbar(struct drm_device *dev) | |
995 | { | |
996 | drm_i915_private_t *dev_priv = dev->dev_private; | |
997 | int mchbar_reg = IS_I965G(dev) ? MCHBAR_I965 : MCHBAR_I915; | |
998 | u32 temp; | |
999 | bool enabled; | |
1000 | ||
1001 | dev_priv->mchbar_need_disable = false; | |
1002 | ||
1003 | if (IS_I915G(dev) || IS_I915GM(dev)) { | |
1004 | pci_read_config_dword(dev_priv->bridge_dev, DEVEN_REG, &temp); | |
1005 | enabled = !!(temp & DEVEN_MCHBAR_EN); | |
1006 | } else { | |
1007 | pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp); | |
1008 | enabled = temp & 1; | |
1009 | } | |
1010 | ||
1011 | /* If it's already enabled, don't have to do anything */ | |
1012 | if (enabled) | |
1013 | return; | |
1014 | ||
1015 | if (intel_alloc_mchbar_resource(dev)) | |
1016 | return; | |
1017 | ||
1018 | dev_priv->mchbar_need_disable = true; | |
1019 | ||
1020 | /* Space is allocated or reserved, so enable it. */ | |
1021 | if (IS_I915G(dev) || IS_I915GM(dev)) { | |
1022 | pci_write_config_dword(dev_priv->bridge_dev, DEVEN_REG, | |
1023 | temp | DEVEN_MCHBAR_EN); | |
1024 | } else { | |
1025 | pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp); | |
1026 | pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp | 1); | |
1027 | } | |
1028 | } | |
1029 | ||
1030 | static void | |
1031 | intel_teardown_mchbar(struct drm_device *dev) | |
1032 | { | |
1033 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1034 | int mchbar_reg = IS_I965G(dev) ? MCHBAR_I965 : MCHBAR_I915; | |
1035 | u32 temp; | |
1036 | ||
1037 | if (dev_priv->mchbar_need_disable) { | |
1038 | if (IS_I915G(dev) || IS_I915GM(dev)) { | |
1039 | pci_read_config_dword(dev_priv->bridge_dev, DEVEN_REG, &temp); | |
1040 | temp &= ~DEVEN_MCHBAR_EN; | |
1041 | pci_write_config_dword(dev_priv->bridge_dev, DEVEN_REG, temp); | |
1042 | } else { | |
1043 | pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp); | |
1044 | temp &= ~1; | |
1045 | pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp); | |
1046 | } | |
1047 | } | |
1048 | ||
1049 | if (dev_priv->mch_res.start) | |
1050 | release_resource(&dev_priv->mch_res); | |
1051 | } | |
1052 | ||
79e53945 JB |
1053 | /** |
1054 | * i915_probe_agp - get AGP bootup configuration | |
1055 | * @pdev: PCI device | |
1056 | * @aperture_size: returns AGP aperture configured size | |
1057 | * @preallocated_size: returns size of BIOS preallocated AGP space | |
1058 | * | |
1059 | * Since Intel integrated graphics are UMA, the BIOS has to set aside | |
1060 | * some RAM for the framebuffer at early boot. This code figures out | |
1061 | * how much was set aside so we can use it for our own purposes. | |
1062 | */ | |
2a34f5e6 | 1063 | static int i915_probe_agp(struct drm_device *dev, uint32_t *aperture_size, |
80824003 JB |
1064 | uint32_t *preallocated_size, |
1065 | uint32_t *start) | |
79e53945 | 1066 | { |
ec2a4c3f | 1067 | struct drm_i915_private *dev_priv = dev->dev_private; |
79e53945 JB |
1068 | u16 tmp = 0; |
1069 | unsigned long overhead; | |
241fa85b | 1070 | unsigned long stolen; |
79e53945 | 1071 | |
79e53945 | 1072 | /* Get the fb aperture size and "stolen" memory amount. */ |
ec2a4c3f | 1073 | pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &tmp); |
79e53945 JB |
1074 | |
1075 | *aperture_size = 1024 * 1024; | |
1076 | *preallocated_size = 1024 * 1024; | |
1077 | ||
60fd99e3 | 1078 | switch (dev->pdev->device) { |
79e53945 JB |
1079 | case PCI_DEVICE_ID_INTEL_82830_CGC: |
1080 | case PCI_DEVICE_ID_INTEL_82845G_IG: | |
1081 | case PCI_DEVICE_ID_INTEL_82855GM_IG: | |
1082 | case PCI_DEVICE_ID_INTEL_82865_IG: | |
1083 | if ((tmp & INTEL_GMCH_MEM_MASK) == INTEL_GMCH_MEM_64M) | |
1084 | *aperture_size *= 64; | |
1085 | else | |
1086 | *aperture_size *= 128; | |
1087 | break; | |
1088 | default: | |
1089 | /* 9xx supports large sizes, just look at the length */ | |
60fd99e3 | 1090 | *aperture_size = pci_resource_len(dev->pdev, 2); |
79e53945 JB |
1091 | break; |
1092 | } | |
1093 | ||
1094 | /* | |
1095 | * Some of the preallocated space is taken by the GTT | |
1096 | * and popup. GTT is 1K per MB of aperture size, and popup is 4K. | |
1097 | */ | |
bad720ff | 1098 | if (IS_G4X(dev) || IS_PINEVIEW(dev) || IS_IRONLAKE(dev) || IS_GEN6(dev)) |
60fd99e3 EA |
1099 | overhead = 4096; |
1100 | else | |
1101 | overhead = (*aperture_size / 1024) + 4096; | |
1102 | ||
14bc490b ZW |
1103 | if (IS_GEN6(dev)) { |
1104 | /* SNB has memory control reg at 0x50.w */ | |
1105 | pci_read_config_word(dev->pdev, SNB_GMCH_CTRL, &tmp); | |
1106 | ||
1107 | switch (tmp & SNB_GMCH_GMS_STOLEN_MASK) { | |
1108 | case INTEL_855_GMCH_GMS_DISABLED: | |
1109 | DRM_ERROR("video memory is disabled\n"); | |
1110 | return -1; | |
1111 | case SNB_GMCH_GMS_STOLEN_32M: | |
1112 | stolen = 32 * 1024 * 1024; | |
1113 | break; | |
1114 | case SNB_GMCH_GMS_STOLEN_64M: | |
bad720ff | 1115 | stolen = 64 * 1024 * 1024; |
14bc490b ZW |
1116 | break; |
1117 | case SNB_GMCH_GMS_STOLEN_96M: | |
1118 | stolen = 96 * 1024 * 1024; | |
1119 | break; | |
1120 | case SNB_GMCH_GMS_STOLEN_128M: | |
1121 | stolen = 128 * 1024 * 1024; | |
1122 | break; | |
1123 | case SNB_GMCH_GMS_STOLEN_160M: | |
1124 | stolen = 160 * 1024 * 1024; | |
1125 | break; | |
1126 | case SNB_GMCH_GMS_STOLEN_192M: | |
1127 | stolen = 192 * 1024 * 1024; | |
1128 | break; | |
1129 | case SNB_GMCH_GMS_STOLEN_224M: | |
1130 | stolen = 224 * 1024 * 1024; | |
1131 | break; | |
1132 | case SNB_GMCH_GMS_STOLEN_256M: | |
1133 | stolen = 256 * 1024 * 1024; | |
1134 | break; | |
1135 | case SNB_GMCH_GMS_STOLEN_288M: | |
1136 | stolen = 288 * 1024 * 1024; | |
1137 | break; | |
1138 | case SNB_GMCH_GMS_STOLEN_320M: | |
1139 | stolen = 320 * 1024 * 1024; | |
1140 | break; | |
1141 | case SNB_GMCH_GMS_STOLEN_352M: | |
1142 | stolen = 352 * 1024 * 1024; | |
1143 | break; | |
1144 | case SNB_GMCH_GMS_STOLEN_384M: | |
1145 | stolen = 384 * 1024 * 1024; | |
1146 | break; | |
1147 | case SNB_GMCH_GMS_STOLEN_416M: | |
1148 | stolen = 416 * 1024 * 1024; | |
1149 | break; | |
1150 | case SNB_GMCH_GMS_STOLEN_448M: | |
1151 | stolen = 448 * 1024 * 1024; | |
1152 | break; | |
1153 | case SNB_GMCH_GMS_STOLEN_480M: | |
1154 | stolen = 480 * 1024 * 1024; | |
1155 | break; | |
1156 | case SNB_GMCH_GMS_STOLEN_512M: | |
1157 | stolen = 512 * 1024 * 1024; | |
1158 | break; | |
1159 | default: | |
1160 | DRM_ERROR("unexpected GMCH_GMS value: 0x%02x\n", | |
1161 | tmp & SNB_GMCH_GMS_STOLEN_MASK); | |
1162 | return -1; | |
1163 | } | |
1164 | } else { | |
1165 | switch (tmp & INTEL_GMCH_GMS_MASK) { | |
1166 | case INTEL_855_GMCH_GMS_DISABLED: | |
bad720ff EA |
1167 | DRM_ERROR("video memory is disabled\n"); |
1168 | return -1; | |
14bc490b ZW |
1169 | case INTEL_855_GMCH_GMS_STOLEN_1M: |
1170 | stolen = 1 * 1024 * 1024; | |
1171 | break; | |
1172 | case INTEL_855_GMCH_GMS_STOLEN_4M: | |
1173 | stolen = 4 * 1024 * 1024; | |
1174 | break; | |
1175 | case INTEL_855_GMCH_GMS_STOLEN_8M: | |
1176 | stolen = 8 * 1024 * 1024; | |
1177 | break; | |
1178 | case INTEL_855_GMCH_GMS_STOLEN_16M: | |
1179 | stolen = 16 * 1024 * 1024; | |
1180 | break; | |
1181 | case INTEL_855_GMCH_GMS_STOLEN_32M: | |
1182 | stolen = 32 * 1024 * 1024; | |
1183 | break; | |
1184 | case INTEL_915G_GMCH_GMS_STOLEN_48M: | |
1185 | stolen = 48 * 1024 * 1024; | |
1186 | break; | |
1187 | case INTEL_915G_GMCH_GMS_STOLEN_64M: | |
1188 | stolen = 64 * 1024 * 1024; | |
1189 | break; | |
1190 | case INTEL_GMCH_GMS_STOLEN_128M: | |
1191 | stolen = 128 * 1024 * 1024; | |
1192 | break; | |
1193 | case INTEL_GMCH_GMS_STOLEN_256M: | |
1194 | stolen = 256 * 1024 * 1024; | |
1195 | break; | |
1196 | case INTEL_GMCH_GMS_STOLEN_96M: | |
1197 | stolen = 96 * 1024 * 1024; | |
1198 | break; | |
1199 | case INTEL_GMCH_GMS_STOLEN_160M: | |
1200 | stolen = 160 * 1024 * 1024; | |
1201 | break; | |
1202 | case INTEL_GMCH_GMS_STOLEN_224M: | |
1203 | stolen = 224 * 1024 * 1024; | |
1204 | break; | |
1205 | case INTEL_GMCH_GMS_STOLEN_352M: | |
1206 | stolen = 352 * 1024 * 1024; | |
1207 | break; | |
1208 | default: | |
1209 | DRM_ERROR("unexpected GMCH_GMS value: 0x%02x\n", | |
1210 | tmp & INTEL_GMCH_GMS_MASK); | |
1211 | return -1; | |
bad720ff | 1212 | } |
79e53945 | 1213 | } |
14bc490b | 1214 | |
241fa85b | 1215 | *preallocated_size = stolen - overhead; |
80824003 | 1216 | *start = overhead; |
79e53945 JB |
1217 | |
1218 | return 0; | |
1219 | } | |
1220 | ||
80824003 JB |
1221 | #define PTE_ADDRESS_MASK 0xfffff000 |
1222 | #define PTE_ADDRESS_MASK_HIGH 0x000000f0 /* i915+ */ | |
1223 | #define PTE_MAPPING_TYPE_UNCACHED (0 << 1) | |
1224 | #define PTE_MAPPING_TYPE_DCACHE (1 << 1) /* i830 only */ | |
1225 | #define PTE_MAPPING_TYPE_CACHED (3 << 1) | |
1226 | #define PTE_MAPPING_TYPE_MASK (3 << 1) | |
1227 | #define PTE_VALID (1 << 0) | |
1228 | ||
1229 | /** | |
1230 | * i915_gtt_to_phys - take a GTT address and turn it into a physical one | |
1231 | * @dev: drm device | |
1232 | * @gtt_addr: address to translate | |
1233 | * | |
1234 | * Some chip functions require allocations from stolen space but need the | |
1235 | * physical address of the memory in question. We use this routine | |
1236 | * to get a physical address suitable for register programming from a given | |
1237 | * GTT address. | |
1238 | */ | |
1239 | static unsigned long i915_gtt_to_phys(struct drm_device *dev, | |
1240 | unsigned long gtt_addr) | |
1241 | { | |
1242 | unsigned long *gtt; | |
1243 | unsigned long entry, phys; | |
1244 | int gtt_bar = IS_I9XX(dev) ? 0 : 1; | |
1245 | int gtt_offset, gtt_size; | |
1246 | ||
1247 | if (IS_I965G(dev)) { | |
bad720ff | 1248 | if (IS_G4X(dev) || IS_IRONLAKE(dev) || IS_GEN6(dev)) { |
80824003 JB |
1249 | gtt_offset = 2*1024*1024; |
1250 | gtt_size = 2*1024*1024; | |
1251 | } else { | |
1252 | gtt_offset = 512*1024; | |
1253 | gtt_size = 512*1024; | |
1254 | } | |
1255 | } else { | |
1256 | gtt_bar = 3; | |
1257 | gtt_offset = 0; | |
1258 | gtt_size = pci_resource_len(dev->pdev, gtt_bar); | |
1259 | } | |
1260 | ||
1261 | gtt = ioremap_wc(pci_resource_start(dev->pdev, gtt_bar) + gtt_offset, | |
1262 | gtt_size); | |
1263 | if (!gtt) { | |
1264 | DRM_ERROR("ioremap of GTT failed\n"); | |
1265 | return 0; | |
1266 | } | |
1267 | ||
1268 | entry = *(volatile u32 *)(gtt + (gtt_addr / 1024)); | |
1269 | ||
44d98a61 | 1270 | DRM_DEBUG_DRIVER("GTT addr: 0x%08lx, PTE: 0x%08lx\n", gtt_addr, entry); |
80824003 JB |
1271 | |
1272 | /* Mask out these reserved bits on this hardware. */ | |
1273 | if (!IS_I9XX(dev) || IS_I915G(dev) || IS_I915GM(dev) || | |
1274 | IS_I945G(dev) || IS_I945GM(dev)) { | |
1275 | entry &= ~PTE_ADDRESS_MASK_HIGH; | |
1276 | } | |
1277 | ||
1278 | /* If it's not a mapping type we know, then bail. */ | |
1279 | if ((entry & PTE_MAPPING_TYPE_MASK) != PTE_MAPPING_TYPE_UNCACHED && | |
1280 | (entry & PTE_MAPPING_TYPE_MASK) != PTE_MAPPING_TYPE_CACHED) { | |
1281 | iounmap(gtt); | |
1282 | return 0; | |
1283 | } | |
1284 | ||
1285 | if (!(entry & PTE_VALID)) { | |
1286 | DRM_ERROR("bad GTT entry in stolen space\n"); | |
1287 | iounmap(gtt); | |
1288 | return 0; | |
1289 | } | |
1290 | ||
1291 | iounmap(gtt); | |
1292 | ||
1293 | phys =(entry & PTE_ADDRESS_MASK) | | |
1294 | ((uint64_t)(entry & PTE_ADDRESS_MASK_HIGH) << (32 - 4)); | |
1295 | ||
44d98a61 | 1296 | DRM_DEBUG_DRIVER("GTT addr: 0x%08lx, phys addr: 0x%08lx\n", gtt_addr, phys); |
80824003 JB |
1297 | |
1298 | return phys; | |
1299 | } | |
1300 | ||
1301 | static void i915_warn_stolen(struct drm_device *dev) | |
1302 | { | |
1303 | DRM_ERROR("not enough stolen space for compressed buffer, disabling\n"); | |
1304 | DRM_ERROR("hint: you may be able to increase stolen memory size in the BIOS to avoid this\n"); | |
1305 | } | |
1306 | ||
1307 | static void i915_setup_compression(struct drm_device *dev, int size) | |
1308 | { | |
1309 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1310 | struct drm_mm_node *compressed_fb, *compressed_llb; | |
29bd0ae2 AM |
1311 | unsigned long cfb_base; |
1312 | unsigned long ll_base = 0; | |
80824003 JB |
1313 | |
1314 | /* Leave 1M for line length buffer & misc. */ | |
1315 | compressed_fb = drm_mm_search_free(&dev_priv->vram, size, 4096, 0); | |
1316 | if (!compressed_fb) { | |
b5e50c3f | 1317 | dev_priv->no_fbc_reason = FBC_STOLEN_TOO_SMALL; |
80824003 JB |
1318 | i915_warn_stolen(dev); |
1319 | return; | |
1320 | } | |
1321 | ||
1322 | compressed_fb = drm_mm_get_block(compressed_fb, size, 4096); | |
1323 | if (!compressed_fb) { | |
1324 | i915_warn_stolen(dev); | |
b5e50c3f | 1325 | dev_priv->no_fbc_reason = FBC_STOLEN_TOO_SMALL; |
80824003 JB |
1326 | return; |
1327 | } | |
1328 | ||
74dff282 JB |
1329 | cfb_base = i915_gtt_to_phys(dev, compressed_fb->start); |
1330 | if (!cfb_base) { | |
1331 | DRM_ERROR("failed to get stolen phys addr, disabling FBC\n"); | |
1332 | drm_mm_put_block(compressed_fb); | |
80824003 JB |
1333 | } |
1334 | ||
74dff282 JB |
1335 | if (!IS_GM45(dev)) { |
1336 | compressed_llb = drm_mm_search_free(&dev_priv->vram, 4096, | |
1337 | 4096, 0); | |
1338 | if (!compressed_llb) { | |
1339 | i915_warn_stolen(dev); | |
1340 | return; | |
1341 | } | |
1342 | ||
1343 | compressed_llb = drm_mm_get_block(compressed_llb, 4096, 4096); | |
1344 | if (!compressed_llb) { | |
1345 | i915_warn_stolen(dev); | |
1346 | return; | |
1347 | } | |
1348 | ||
1349 | ll_base = i915_gtt_to_phys(dev, compressed_llb->start); | |
1350 | if (!ll_base) { | |
1351 | DRM_ERROR("failed to get stolen phys addr, disabling FBC\n"); | |
1352 | drm_mm_put_block(compressed_fb); | |
1353 | drm_mm_put_block(compressed_llb); | |
1354 | } | |
80824003 JB |
1355 | } |
1356 | ||
1357 | dev_priv->cfb_size = size; | |
1358 | ||
74dff282 JB |
1359 | if (IS_GM45(dev)) { |
1360 | g4x_disable_fbc(dev); | |
1361 | I915_WRITE(DPFC_CB_BASE, compressed_fb->start); | |
1362 | } else { | |
1363 | i8xx_disable_fbc(dev); | |
1364 | I915_WRITE(FBC_CFB_BASE, cfb_base); | |
1365 | I915_WRITE(FBC_LL_BASE, ll_base); | |
80824003 JB |
1366 | } |
1367 | ||
80824003 JB |
1368 | DRM_DEBUG("FBC base 0x%08lx, ll base 0x%08lx, size %dM\n", cfb_base, |
1369 | ll_base, size >> 20); | |
80824003 JB |
1370 | } |
1371 | ||
28d52043 DA |
1372 | /* true = enable decode, false = disable decoder */ |
1373 | static unsigned int i915_vga_set_decode(void *cookie, bool state) | |
1374 | { | |
1375 | struct drm_device *dev = cookie; | |
1376 | ||
1377 | intel_modeset_vga_set_state(dev, state); | |
1378 | if (state) | |
1379 | return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM | | |
1380 | VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM; | |
1381 | else | |
1382 | return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM; | |
1383 | } | |
1384 | ||
6a9ee8af DA |
1385 | static void i915_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state) |
1386 | { | |
1387 | struct drm_device *dev = pci_get_drvdata(pdev); | |
1388 | pm_message_t pmm = { .event = PM_EVENT_SUSPEND }; | |
1389 | if (state == VGA_SWITCHEROO_ON) { | |
1390 | printk(KERN_INFO "i915: switched off\n"); | |
1391 | /* i915 resume handler doesn't set to D0 */ | |
1392 | pci_set_power_state(dev->pdev, PCI_D0); | |
1393 | i915_resume(dev); | |
1394 | } else { | |
1395 | printk(KERN_ERR "i915: switched off\n"); | |
1396 | i915_suspend(dev, pmm); | |
1397 | } | |
1398 | } | |
1399 | ||
1400 | static bool i915_switcheroo_can_switch(struct pci_dev *pdev) | |
1401 | { | |
1402 | struct drm_device *dev = pci_get_drvdata(pdev); | |
1403 | bool can_switch; | |
1404 | ||
1405 | spin_lock(&dev->count_lock); | |
1406 | can_switch = (dev->open_count == 0); | |
1407 | spin_unlock(&dev->count_lock); | |
1408 | return can_switch; | |
1409 | } | |
1410 | ||
2a34f5e6 | 1411 | static int i915_load_modeset_init(struct drm_device *dev, |
80824003 | 1412 | unsigned long prealloc_start, |
2a34f5e6 EA |
1413 | unsigned long prealloc_size, |
1414 | unsigned long agp_size) | |
79e53945 JB |
1415 | { |
1416 | struct drm_i915_private *dev_priv = dev->dev_private; | |
79e53945 JB |
1417 | int fb_bar = IS_I9XX(dev) ? 2 : 0; |
1418 | int ret = 0; | |
1419 | ||
1420 | dev->mode_config.fb_base = drm_get_resource_start(dev, fb_bar) & | |
1421 | 0xff000000; | |
1422 | ||
79e53945 JB |
1423 | /* Basic memrange allocator for stolen space (aka vram) */ |
1424 | drm_mm_init(&dev_priv->vram, 0, prealloc_size); | |
80824003 | 1425 | DRM_INFO("set up %ldM of stolen space\n", prealloc_size / (1024*1024)); |
79e53945 | 1426 | |
11ed50ec BG |
1427 | /* We're off and running w/KMS */ |
1428 | dev_priv->mm.suspended = 0; | |
79e53945 | 1429 | |
13f4c435 EA |
1430 | /* Let GEM Manage from end of prealloc space to end of aperture. |
1431 | * | |
1432 | * However, leave one page at the end still bound to the scratch page. | |
1433 | * There are a number of places where the hardware apparently | |
1434 | * prefetches past the end of the object, and we've seen multiple | |
1435 | * hangs with the GPU head pointer stuck in a batchbuffer bound | |
1436 | * at the last page of the aperture. One page should be enough to | |
1437 | * keep any prefetching inside of the aperture. | |
1438 | */ | |
1439 | i915_gem_do_init(dev, prealloc_size, agp_size - 4096); | |
79e53945 | 1440 | |
11ed50ec | 1441 | mutex_lock(&dev->struct_mutex); |
79e53945 | 1442 | ret = i915_gem_init_ringbuffer(dev); |
11ed50ec | 1443 | mutex_unlock(&dev->struct_mutex); |
79e53945 | 1444 | if (ret) |
b8da7de5 | 1445 | goto out; |
79e53945 | 1446 | |
80824003 | 1447 | /* Try to set up FBC with a reasonable compressed buffer size */ |
9216d44d | 1448 | if (I915_HAS_FBC(dev) && i915_powersave) { |
80824003 JB |
1449 | int cfb_size; |
1450 | ||
1451 | /* Try to get an 8M buffer... */ | |
1452 | if (prealloc_size > (9*1024*1024)) | |
1453 | cfb_size = 8*1024*1024; | |
1454 | else /* fall back to 7/8 of the stolen space */ | |
1455 | cfb_size = prealloc_size * 7 / 8; | |
1456 | i915_setup_compression(dev, cfb_size); | |
1457 | } | |
1458 | ||
79e53945 JB |
1459 | /* Allow hardware batchbuffers unless told otherwise. |
1460 | */ | |
1461 | dev_priv->allow_batchbuffer = 1; | |
1462 | ||
1463 | ret = intel_init_bios(dev); | |
1464 | if (ret) | |
1465 | DRM_INFO("failed to find VBIOS tables\n"); | |
1466 | ||
28d52043 DA |
1467 | /* if we have > 1 VGA cards, then disable the radeon VGA resources */ |
1468 | ret = vga_client_register(dev->pdev, dev, NULL, i915_vga_set_decode); | |
1469 | if (ret) | |
1470 | goto destroy_ringbuffer; | |
1471 | ||
6a9ee8af DA |
1472 | ret = vga_switcheroo_register_client(dev->pdev, |
1473 | i915_switcheroo_set_state, | |
1474 | i915_switcheroo_can_switch); | |
1475 | if (ret) | |
1476 | goto destroy_ringbuffer; | |
1477 | ||
b01f2c3a JB |
1478 | intel_modeset_init(dev); |
1479 | ||
79e53945 JB |
1480 | ret = drm_irq_install(dev); |
1481 | if (ret) | |
1482 | goto destroy_ringbuffer; | |
1483 | ||
79e53945 JB |
1484 | /* Always safe in the mode setting case. */ |
1485 | /* FIXME: do pre/post-mode set stuff in core KMS code */ | |
1486 | dev->vblank_disable_allowed = 1; | |
1487 | ||
1488 | /* | |
1489 | * Initialize the hardware status page IRQ location. | |
1490 | */ | |
1491 | ||
1492 | I915_WRITE(INSTPM, (1 << 5) | (1 << 21)); | |
1493 | ||
38651674 | 1494 | intel_fbdev_init(dev); |
79e53945 | 1495 | |
79e53945 JB |
1496 | return 0; |
1497 | ||
79e53945 | 1498 | destroy_ringbuffer: |
21099537 | 1499 | mutex_lock(&dev->struct_mutex); |
79e53945 | 1500 | i915_gem_cleanup_ringbuffer(dev); |
21099537 | 1501 | mutex_unlock(&dev->struct_mutex); |
79e53945 JB |
1502 | out: |
1503 | return ret; | |
1504 | } | |
1505 | ||
7c1c2871 DA |
1506 | int i915_master_create(struct drm_device *dev, struct drm_master *master) |
1507 | { | |
1508 | struct drm_i915_master_private *master_priv; | |
1509 | ||
9a298b2a | 1510 | master_priv = kzalloc(sizeof(*master_priv), GFP_KERNEL); |
7c1c2871 DA |
1511 | if (!master_priv) |
1512 | return -ENOMEM; | |
1513 | ||
1514 | master->driver_priv = master_priv; | |
1515 | return 0; | |
1516 | } | |
1517 | ||
1518 | void i915_master_destroy(struct drm_device *dev, struct drm_master *master) | |
1519 | { | |
1520 | struct drm_i915_master_private *master_priv = master->driver_priv; | |
1521 | ||
1522 | if (!master_priv) | |
1523 | return; | |
1524 | ||
9a298b2a | 1525 | kfree(master_priv); |
7c1c2871 DA |
1526 | |
1527 | master->driver_priv = NULL; | |
1528 | } | |
1529 | ||
7662c8bd SL |
1530 | static void i915_get_mem_freq(struct drm_device *dev) |
1531 | { | |
1532 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1533 | u32 tmp; | |
1534 | ||
f2b115e6 | 1535 | if (!IS_PINEVIEW(dev)) |
7662c8bd SL |
1536 | return; |
1537 | ||
1538 | tmp = I915_READ(CLKCFG); | |
1539 | ||
1540 | switch (tmp & CLKCFG_FSB_MASK) { | |
1541 | case CLKCFG_FSB_533: | |
1542 | dev_priv->fsb_freq = 533; /* 133*4 */ | |
1543 | break; | |
1544 | case CLKCFG_FSB_800: | |
1545 | dev_priv->fsb_freq = 800; /* 200*4 */ | |
1546 | break; | |
1547 | case CLKCFG_FSB_667: | |
1548 | dev_priv->fsb_freq = 667; /* 167*4 */ | |
1549 | break; | |
1550 | case CLKCFG_FSB_400: | |
1551 | dev_priv->fsb_freq = 400; /* 100*4 */ | |
1552 | break; | |
1553 | } | |
1554 | ||
1555 | switch (tmp & CLKCFG_MEM_MASK) { | |
1556 | case CLKCFG_MEM_533: | |
1557 | dev_priv->mem_freq = 533; | |
1558 | break; | |
1559 | case CLKCFG_MEM_667: | |
1560 | dev_priv->mem_freq = 667; | |
1561 | break; | |
1562 | case CLKCFG_MEM_800: | |
1563 | dev_priv->mem_freq = 800; | |
1564 | break; | |
1565 | } | |
1566 | } | |
1567 | ||
79e53945 JB |
1568 | /** |
1569 | * i915_driver_load - setup chip and create an initial config | |
1570 | * @dev: DRM device | |
1571 | * @flags: startup flags | |
1572 | * | |
1573 | * The driver load routine has to do several things: | |
1574 | * - drive output discovery via intel_modeset_init() | |
1575 | * - initialize the memory manager | |
1576 | * - allocate initial config memory | |
1577 | * - setup the DRM framebuffer with the allocated memory | |
1578 | */ | |
84b1fd10 | 1579 | int i915_driver_load(struct drm_device *dev, unsigned long flags) |
22eae947 | 1580 | { |
ba8bbcf6 | 1581 | struct drm_i915_private *dev_priv = dev->dev_private; |
d883f7f1 | 1582 | resource_size_t base, size; |
cfdf1fa2 | 1583 | int ret = 0, mmio_bar; |
80824003 | 1584 | uint32_t agp_size, prealloc_size, prealloc_start; |
ba8bbcf6 | 1585 | |
22eae947 DA |
1586 | /* i915 has 4 more counters */ |
1587 | dev->counters += 4; | |
1588 | dev->types[6] = _DRM_STAT_IRQ; | |
1589 | dev->types[7] = _DRM_STAT_PRIMARY; | |
1590 | dev->types[8] = _DRM_STAT_SECONDARY; | |
1591 | dev->types[9] = _DRM_STAT_DMA; | |
1592 | ||
9a298b2a | 1593 | dev_priv = kzalloc(sizeof(drm_i915_private_t), GFP_KERNEL); |
ba8bbcf6 JB |
1594 | if (dev_priv == NULL) |
1595 | return -ENOMEM; | |
1596 | ||
ba8bbcf6 | 1597 | dev->dev_private = (void *)dev_priv; |
673a394b | 1598 | dev_priv->dev = dev; |
cfdf1fa2 | 1599 | dev_priv->info = (struct intel_device_info *) flags; |
ba8bbcf6 JB |
1600 | |
1601 | /* Add register map (needed for suspend/resume) */ | |
cfdf1fa2 | 1602 | mmio_bar = IS_I9XX(dev) ? 0 : 1; |
ba8bbcf6 JB |
1603 | base = drm_get_resource_start(dev, mmio_bar); |
1604 | size = drm_get_resource_len(dev, mmio_bar); | |
1605 | ||
ec2a4c3f DA |
1606 | if (i915_get_bridge_dev(dev)) { |
1607 | ret = -EIO; | |
1608 | goto free_priv; | |
1609 | } | |
1610 | ||
3043c60c | 1611 | dev_priv->regs = ioremap(base, size); |
79e53945 JB |
1612 | if (!dev_priv->regs) { |
1613 | DRM_ERROR("failed to map registers\n"); | |
1614 | ret = -EIO; | |
ec2a4c3f | 1615 | goto put_bridge; |
79e53945 | 1616 | } |
ed4cb414 | 1617 | |
ab657db1 EA |
1618 | dev_priv->mm.gtt_mapping = |
1619 | io_mapping_create_wc(dev->agp->base, | |
1620 | dev->agp->agp_info.aper_size * 1024*1024); | |
6644107d VP |
1621 | if (dev_priv->mm.gtt_mapping == NULL) { |
1622 | ret = -EIO; | |
1623 | goto out_rmmap; | |
1624 | } | |
1625 | ||
ab657db1 EA |
1626 | /* Set up a WC MTRR for non-PAT systems. This is more common than |
1627 | * one would think, because the kernel disables PAT on first | |
1628 | * generation Core chips because WC PAT gets overridden by a UC | |
1629 | * MTRR if present. Even if a UC MTRR isn't present. | |
1630 | */ | |
1631 | dev_priv->mm.gtt_mtrr = mtrr_add(dev->agp->base, | |
1632 | dev->agp->agp_info.aper_size * | |
1633 | 1024 * 1024, | |
1634 | MTRR_TYPE_WRCOMB, 1); | |
1635 | if (dev_priv->mm.gtt_mtrr < 0) { | |
040aefa2 | 1636 | DRM_INFO("MTRR allocation failed. Graphics " |
ab657db1 EA |
1637 | "performance may suffer.\n"); |
1638 | } | |
1639 | ||
80824003 | 1640 | ret = i915_probe_agp(dev, &agp_size, &prealloc_size, &prealloc_start); |
2a34f5e6 EA |
1641 | if (ret) |
1642 | goto out_iomapfree; | |
1643 | ||
aed5f1dc | 1644 | dev_priv->wq = create_singlethread_workqueue("i915"); |
9c9fe1f8 EA |
1645 | if (dev_priv->wq == NULL) { |
1646 | DRM_ERROR("Failed to create our workqueue.\n"); | |
1647 | ret = -ENOMEM; | |
1648 | goto out_iomapfree; | |
1649 | } | |
1650 | ||
ac5c4e76 DA |
1651 | /* enable GEM by default */ |
1652 | dev_priv->has_gem = 1; | |
ac5c4e76 | 1653 | |
2a34f5e6 EA |
1654 | if (prealloc_size > agp_size * 3 / 4) { |
1655 | DRM_ERROR("Detected broken video BIOS with %d/%dkB of video " | |
1656 | "memory stolen.\n", | |
1657 | prealloc_size / 1024, agp_size / 1024); | |
1658 | DRM_ERROR("Disabling GEM. (try reducing stolen memory or " | |
1659 | "updating the BIOS to fix).\n"); | |
1660 | dev_priv->has_gem = 0; | |
1661 | } | |
1662 | ||
9880b7a5 | 1663 | dev->driver->get_vblank_counter = i915_get_vblank_counter; |
42c2798b | 1664 | dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */ |
bad720ff | 1665 | if (IS_G4X(dev) || IS_IRONLAKE(dev) || IS_GEN6(dev)) { |
42c2798b | 1666 | dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */ |
9880b7a5 | 1667 | dev->driver->get_vblank_counter = gm45_get_vblank_counter; |
42c2798b | 1668 | } |
9880b7a5 | 1669 | |
c4804411 ZW |
1670 | /* Try to make sure MCHBAR is enabled before poking at it */ |
1671 | intel_setup_mchbar(dev); | |
1672 | ||
673a394b EA |
1673 | i915_gem_load(dev); |
1674 | ||
398c9cb2 KP |
1675 | /* Init HWS */ |
1676 | if (!I915_NEED_GFX_HWS(dev)) { | |
1677 | ret = i915_init_phys_hws(dev); | |
1678 | if (ret != 0) | |
9c9fe1f8 | 1679 | goto out_workqueue_free; |
398c9cb2 | 1680 | } |
ed4cb414 | 1681 | |
7662c8bd SL |
1682 | i915_get_mem_freq(dev); |
1683 | ||
ed4cb414 EA |
1684 | /* On the 945G/GM, the chipset reports the MSI capability on the |
1685 | * integrated graphics even though the support isn't actually there | |
1686 | * according to the published specs. It doesn't appear to function | |
1687 | * correctly in testing on 945G. | |
1688 | * This may be a side effect of MSI having been made available for PEG | |
1689 | * and the registers being closely associated. | |
d1ed629f KP |
1690 | * |
1691 | * According to chipset errata, on the 965GM, MSI interrupts may | |
b60678a7 KP |
1692 | * be lost or delayed, but we use them anyways to avoid |
1693 | * stuck interrupts on some machines. | |
ed4cb414 | 1694 | */ |
b60678a7 | 1695 | if (!IS_I945G(dev) && !IS_I945GM(dev)) |
d3e74d02 | 1696 | pci_enable_msi(dev->pdev); |
ed4cb414 EA |
1697 | |
1698 | spin_lock_init(&dev_priv->user_irq_lock); | |
63eeaf38 | 1699 | spin_lock_init(&dev_priv->error_lock); |
79e53945 | 1700 | dev_priv->user_irq_refcount = 0; |
9d34e5db | 1701 | dev_priv->trace_irq_seqno = 0; |
ed4cb414 | 1702 | |
52440211 KP |
1703 | ret = drm_vblank_init(dev, I915_NUM_PIPE); |
1704 | ||
1705 | if (ret) { | |
1706 | (void) i915_driver_unload(dev); | |
1707 | return ret; | |
1708 | } | |
1709 | ||
11ed50ec BG |
1710 | /* Start out suspended */ |
1711 | dev_priv->mm.suspended = 1; | |
1712 | ||
79e53945 | 1713 | if (drm_core_check_feature(dev, DRIVER_MODESET)) { |
80824003 JB |
1714 | ret = i915_load_modeset_init(dev, prealloc_start, |
1715 | prealloc_size, agp_size); | |
79e53945 JB |
1716 | if (ret < 0) { |
1717 | DRM_ERROR("failed to init modeset\n"); | |
9c9fe1f8 | 1718 | goto out_workqueue_free; |
79e53945 JB |
1719 | } |
1720 | } | |
1721 | ||
74a365b3 | 1722 | /* Must be done after probing outputs */ |
01c66889 | 1723 | intel_opregion_init(dev, 0); |
74a365b3 | 1724 | |
f65d9421 BG |
1725 | setup_timer(&dev_priv->hangcheck_timer, i915_hangcheck_elapsed, |
1726 | (unsigned long) dev); | |
79e53945 JB |
1727 | return 0; |
1728 | ||
9c9fe1f8 EA |
1729 | out_workqueue_free: |
1730 | destroy_workqueue(dev_priv->wq); | |
6644107d VP |
1731 | out_iomapfree: |
1732 | io_mapping_free(dev_priv->mm.gtt_mapping); | |
79e53945 JB |
1733 | out_rmmap: |
1734 | iounmap(dev_priv->regs); | |
ec2a4c3f DA |
1735 | put_bridge: |
1736 | pci_dev_put(dev_priv->bridge_dev); | |
79e53945 | 1737 | free_priv: |
9a298b2a | 1738 | kfree(dev_priv); |
ba8bbcf6 JB |
1739 | return ret; |
1740 | } | |
1741 | ||
1742 | int i915_driver_unload(struct drm_device *dev) | |
1743 | { | |
1744 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1745 | ||
9df30794 CW |
1746 | i915_destroy_error_state(dev); |
1747 | ||
9c9fe1f8 | 1748 | destroy_workqueue(dev_priv->wq); |
f65d9421 | 1749 | del_timer_sync(&dev_priv->hangcheck_timer); |
9c9fe1f8 | 1750 | |
ab657db1 EA |
1751 | io_mapping_free(dev_priv->mm.gtt_mapping); |
1752 | if (dev_priv->mm.gtt_mtrr >= 0) { | |
1753 | mtrr_del(dev_priv->mm.gtt_mtrr, dev->agp->base, | |
1754 | dev->agp->agp_info.aper_size * 1024 * 1024); | |
1755 | dev_priv->mm.gtt_mtrr = -1; | |
1756 | } | |
1757 | ||
79e53945 | 1758 | if (drm_core_check_feature(dev, DRIVER_MODESET)) { |
6363ee6f ZY |
1759 | /* |
1760 | * free the memory space allocated for the child device | |
1761 | * config parsed from VBT | |
1762 | */ | |
1763 | if (dev_priv->child_dev && dev_priv->child_dev_num) { | |
1764 | kfree(dev_priv->child_dev); | |
1765 | dev_priv->child_dev = NULL; | |
1766 | dev_priv->child_dev_num = 0; | |
1767 | } | |
79e53945 | 1768 | drm_irq_uninstall(dev); |
6a9ee8af | 1769 | vga_switcheroo_unregister_client(dev->pdev); |
28d52043 | 1770 | vga_client_register(dev->pdev, NULL, NULL, NULL); |
79e53945 JB |
1771 | } |
1772 | ||
ed4cb414 EA |
1773 | if (dev->pdev->msi_enabled) |
1774 | pci_disable_msi(dev->pdev); | |
1775 | ||
3043c60c EA |
1776 | if (dev_priv->regs != NULL) |
1777 | iounmap(dev_priv->regs); | |
ba8bbcf6 | 1778 | |
01c66889 | 1779 | intel_opregion_free(dev, 0); |
8ee1c3db | 1780 | |
79e53945 JB |
1781 | if (drm_core_check_feature(dev, DRIVER_MODESET)) { |
1782 | intel_modeset_cleanup(dev); | |
1783 | ||
71acb5eb DA |
1784 | i915_gem_free_all_phys_object(dev); |
1785 | ||
79e53945 JB |
1786 | mutex_lock(&dev->struct_mutex); |
1787 | i915_gem_cleanup_ringbuffer(dev); | |
1788 | mutex_unlock(&dev->struct_mutex); | |
1789 | drm_mm_takedown(&dev_priv->vram); | |
1790 | i915_gem_lastclose(dev); | |
02e792fb DV |
1791 | |
1792 | intel_cleanup_overlay(dev); | |
79e53945 JB |
1793 | } |
1794 | ||
c4804411 ZW |
1795 | intel_teardown_mchbar(dev); |
1796 | ||
ec2a4c3f | 1797 | pci_dev_put(dev_priv->bridge_dev); |
9a298b2a | 1798 | kfree(dev->dev_private); |
ba8bbcf6 | 1799 | |
22eae947 DA |
1800 | return 0; |
1801 | } | |
1802 | ||
673a394b EA |
1803 | int i915_driver_open(struct drm_device *dev, struct drm_file *file_priv) |
1804 | { | |
1805 | struct drm_i915_file_private *i915_file_priv; | |
1806 | ||
8a4c47f3 | 1807 | DRM_DEBUG_DRIVER("\n"); |
673a394b | 1808 | i915_file_priv = (struct drm_i915_file_private *) |
9a298b2a | 1809 | kmalloc(sizeof(*i915_file_priv), GFP_KERNEL); |
673a394b EA |
1810 | |
1811 | if (!i915_file_priv) | |
1812 | return -ENOMEM; | |
1813 | ||
1814 | file_priv->driver_priv = i915_file_priv; | |
1815 | ||
b962442e | 1816 | INIT_LIST_HEAD(&i915_file_priv->mm.request_list); |
673a394b EA |
1817 | |
1818 | return 0; | |
1819 | } | |
1820 | ||
79e53945 JB |
1821 | /** |
1822 | * i915_driver_lastclose - clean up after all DRM clients have exited | |
1823 | * @dev: DRM device | |
1824 | * | |
1825 | * Take care of cleaning up after all DRM clients have exited. In the | |
1826 | * mode setting case, we want to restore the kernel's initial mode (just | |
1827 | * in case the last client left us in a bad state). | |
1828 | * | |
1829 | * Additionally, in the non-mode setting case, we'll tear down the AGP | |
1830 | * and DMA structures, since the kernel won't be using them, and clea | |
1831 | * up any GEM state. | |
1832 | */ | |
84b1fd10 | 1833 | void i915_driver_lastclose(struct drm_device * dev) |
1da177e4 | 1834 | { |
ba8bbcf6 JB |
1835 | drm_i915_private_t *dev_priv = dev->dev_private; |
1836 | ||
79e53945 | 1837 | if (!dev_priv || drm_core_check_feature(dev, DRIVER_MODESET)) { |
785b93ef | 1838 | drm_fb_helper_restore(); |
6a9ee8af | 1839 | vga_switcheroo_process_delayed_switch(); |
144a75fa | 1840 | return; |
79e53945 | 1841 | } |
144a75fa | 1842 | |
673a394b EA |
1843 | i915_gem_lastclose(dev); |
1844 | ||
ba8bbcf6 | 1845 | if (dev_priv->agp_heap) |
b5e89ed5 | 1846 | i915_mem_takedown(&(dev_priv->agp_heap)); |
ba8bbcf6 | 1847 | |
b5e89ed5 | 1848 | i915_dma_cleanup(dev); |
1da177e4 LT |
1849 | } |
1850 | ||
6c340eac | 1851 | void i915_driver_preclose(struct drm_device * dev, struct drm_file *file_priv) |
1da177e4 | 1852 | { |
ba8bbcf6 | 1853 | drm_i915_private_t *dev_priv = dev->dev_private; |
b962442e | 1854 | i915_gem_release(dev, file_priv); |
79e53945 JB |
1855 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) |
1856 | i915_mem_release(dev, file_priv, dev_priv->agp_heap); | |
1da177e4 LT |
1857 | } |
1858 | ||
673a394b EA |
1859 | void i915_driver_postclose(struct drm_device *dev, struct drm_file *file_priv) |
1860 | { | |
1861 | struct drm_i915_file_private *i915_file_priv = file_priv->driver_priv; | |
1862 | ||
9a298b2a | 1863 | kfree(i915_file_priv); |
673a394b EA |
1864 | } |
1865 | ||
c153f45f EA |
1866 | struct drm_ioctl_desc i915_ioctls[] = { |
1867 | DRM_IOCTL_DEF(DRM_I915_INIT, i915_dma_init, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), | |
1868 | DRM_IOCTL_DEF(DRM_I915_FLUSH, i915_flush_ioctl, DRM_AUTH), | |
1869 | DRM_IOCTL_DEF(DRM_I915_FLIP, i915_flip_bufs, DRM_AUTH), | |
1870 | DRM_IOCTL_DEF(DRM_I915_BATCHBUFFER, i915_batchbuffer, DRM_AUTH), | |
1871 | DRM_IOCTL_DEF(DRM_I915_IRQ_EMIT, i915_irq_emit, DRM_AUTH), | |
1872 | DRM_IOCTL_DEF(DRM_I915_IRQ_WAIT, i915_irq_wait, DRM_AUTH), | |
1873 | DRM_IOCTL_DEF(DRM_I915_GETPARAM, i915_getparam, DRM_AUTH), | |
1874 | DRM_IOCTL_DEF(DRM_I915_SETPARAM, i915_setparam, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), | |
1875 | DRM_IOCTL_DEF(DRM_I915_ALLOC, i915_mem_alloc, DRM_AUTH), | |
1876 | DRM_IOCTL_DEF(DRM_I915_FREE, i915_mem_free, DRM_AUTH), | |
1877 | DRM_IOCTL_DEF(DRM_I915_INIT_HEAP, i915_mem_init_heap, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), | |
1878 | DRM_IOCTL_DEF(DRM_I915_CMDBUFFER, i915_cmdbuffer, DRM_AUTH), | |
1879 | DRM_IOCTL_DEF(DRM_I915_DESTROY_HEAP, i915_mem_destroy_heap, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY ), | |
1880 | DRM_IOCTL_DEF(DRM_I915_SET_VBLANK_PIPE, i915_vblank_pipe_set, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY ), | |
1881 | DRM_IOCTL_DEF(DRM_I915_GET_VBLANK_PIPE, i915_vblank_pipe_get, DRM_AUTH ), | |
1882 | DRM_IOCTL_DEF(DRM_I915_VBLANK_SWAP, i915_vblank_swap, DRM_AUTH), | |
4b408939 | 1883 | DRM_IOCTL_DEF(DRM_I915_HWS_ADDR, i915_set_status_page, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), |
2bdf00b2 | 1884 | DRM_IOCTL_DEF(DRM_I915_GEM_INIT, i915_gem_init_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), |
673a394b | 1885 | DRM_IOCTL_DEF(DRM_I915_GEM_EXECBUFFER, i915_gem_execbuffer, DRM_AUTH), |
76446cac | 1886 | DRM_IOCTL_DEF(DRM_I915_GEM_EXECBUFFER2, i915_gem_execbuffer2, DRM_AUTH), |
673a394b EA |
1887 | DRM_IOCTL_DEF(DRM_I915_GEM_PIN, i915_gem_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY), |
1888 | DRM_IOCTL_DEF(DRM_I915_GEM_UNPIN, i915_gem_unpin_ioctl, DRM_AUTH|DRM_ROOT_ONLY), | |
1889 | DRM_IOCTL_DEF(DRM_I915_GEM_BUSY, i915_gem_busy_ioctl, DRM_AUTH), | |
1890 | DRM_IOCTL_DEF(DRM_I915_GEM_THROTTLE, i915_gem_throttle_ioctl, DRM_AUTH), | |
2bdf00b2 DA |
1891 | DRM_IOCTL_DEF(DRM_I915_GEM_ENTERVT, i915_gem_entervt_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), |
1892 | DRM_IOCTL_DEF(DRM_I915_GEM_LEAVEVT, i915_gem_leavevt_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), | |
673a394b EA |
1893 | DRM_IOCTL_DEF(DRM_I915_GEM_CREATE, i915_gem_create_ioctl, 0), |
1894 | DRM_IOCTL_DEF(DRM_I915_GEM_PREAD, i915_gem_pread_ioctl, 0), | |
1895 | DRM_IOCTL_DEF(DRM_I915_GEM_PWRITE, i915_gem_pwrite_ioctl, 0), | |
1896 | DRM_IOCTL_DEF(DRM_I915_GEM_MMAP, i915_gem_mmap_ioctl, 0), | |
de151cf6 | 1897 | DRM_IOCTL_DEF(DRM_I915_GEM_MMAP_GTT, i915_gem_mmap_gtt_ioctl, 0), |
673a394b EA |
1898 | DRM_IOCTL_DEF(DRM_I915_GEM_SET_DOMAIN, i915_gem_set_domain_ioctl, 0), |
1899 | DRM_IOCTL_DEF(DRM_I915_GEM_SW_FINISH, i915_gem_sw_finish_ioctl, 0), | |
1900 | DRM_IOCTL_DEF(DRM_I915_GEM_SET_TILING, i915_gem_set_tiling, 0), | |
1901 | DRM_IOCTL_DEF(DRM_I915_GEM_GET_TILING, i915_gem_get_tiling, 0), | |
5a125c3c | 1902 | DRM_IOCTL_DEF(DRM_I915_GEM_GET_APERTURE, i915_gem_get_aperture_ioctl, 0), |
08d7b3d1 | 1903 | DRM_IOCTL_DEF(DRM_I915_GET_PIPE_FROM_CRTC_ID, intel_get_pipe_from_crtc_id, 0), |
3ef94daa | 1904 | DRM_IOCTL_DEF(DRM_I915_GEM_MADVISE, i915_gem_madvise_ioctl, 0), |
02e792fb DV |
1905 | DRM_IOCTL_DEF(DRM_I915_OVERLAY_PUT_IMAGE, intel_overlay_put_image, DRM_MASTER|DRM_CONTROL_ALLOW), |
1906 | DRM_IOCTL_DEF(DRM_I915_OVERLAY_ATTRS, intel_overlay_attrs, DRM_MASTER|DRM_CONTROL_ALLOW), | |
c94f7029 DA |
1907 | }; |
1908 | ||
1909 | int i915_max_ioctl = DRM_ARRAY_SIZE(i915_ioctls); | |
cda17380 DA |
1910 | |
1911 | /** | |
1912 | * Determine if the device really is AGP or not. | |
1913 | * | |
1914 | * All Intel graphics chipsets are treated as AGP, even if they are really | |
1915 | * PCI-e. | |
1916 | * | |
1917 | * \param dev The device to be tested. | |
1918 | * | |
1919 | * \returns | |
1920 | * A value of 1 is always retured to indictate every i9x5 is AGP. | |
1921 | */ | |
84b1fd10 | 1922 | int i915_driver_device_is_agp(struct drm_device * dev) |
cda17380 DA |
1923 | { |
1924 | return 1; | |
1925 | } |