Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* i915_dma.c -- DMA support for the I915 -*- linux-c -*- |
2 | */ | |
0d6aa60b | 3 | /* |
1da177e4 LT |
4 | * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. |
5 | * All Rights Reserved. | |
bc54fd1a DA |
6 | * |
7 | * Permission is hereby granted, free of charge, to any person obtaining a | |
8 | * copy of this software and associated documentation files (the | |
9 | * "Software"), to deal in the Software without restriction, including | |
10 | * without limitation the rights to use, copy, modify, merge, publish, | |
11 | * distribute, sub license, and/or sell copies of the Software, and to | |
12 | * permit persons to whom the Software is furnished to do so, subject to | |
13 | * the following conditions: | |
14 | * | |
15 | * The above copyright notice and this permission notice (including the | |
16 | * next paragraph) shall be included in all copies or substantial portions | |
17 | * of the Software. | |
18 | * | |
19 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS | |
20 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
21 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. | |
22 | * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR | |
23 | * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, | |
24 | * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE | |
25 | * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. | |
26 | * | |
0d6aa60b | 27 | */ |
1da177e4 LT |
28 | |
29 | #include "drmP.h" | |
30 | #include "drm.h" | |
79e53945 JB |
31 | #include "drm_crtc_helper.h" |
32 | #include "intel_drv.h" | |
1da177e4 LT |
33 | #include "i915_drm.h" |
34 | #include "i915_drv.h" | |
35 | ||
1da177e4 LT |
36 | /* Really want an OS-independent resettable timer. Would like to have |
37 | * this loop run for (eg) 3 sec, but have the timer reset every time | |
38 | * the head pointer changes, so that EBUSY only happens if the ring | |
39 | * actually stalls for (eg) 3 seconds. | |
40 | */ | |
84b1fd10 | 41 | int i915_wait_ring(struct drm_device * dev, int n, const char *caller) |
1da177e4 LT |
42 | { |
43 | drm_i915_private_t *dev_priv = dev->dev_private; | |
7c1c2871 | 44 | struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv; |
1da177e4 | 45 | drm_i915_ring_buffer_t *ring = &(dev_priv->ring); |
d3a6d446 KP |
46 | u32 acthd_reg = IS_I965G(dev) ? ACTHD_I965 : ACTHD; |
47 | u32 last_acthd = I915_READ(acthd_reg); | |
48 | u32 acthd; | |
585fb111 | 49 | u32 last_head = I915_READ(PRB0_HEAD) & HEAD_ADDR; |
1da177e4 LT |
50 | int i; |
51 | ||
d3a6d446 | 52 | for (i = 0; i < 100000; i++) { |
585fb111 | 53 | ring->head = I915_READ(PRB0_HEAD) & HEAD_ADDR; |
d3a6d446 | 54 | acthd = I915_READ(acthd_reg); |
1da177e4 LT |
55 | ring->space = ring->head - (ring->tail + 8); |
56 | if (ring->space < 0) | |
57 | ring->space += ring->Size; | |
58 | if (ring->space >= n) | |
59 | return 0; | |
60 | ||
7c1c2871 DA |
61 | if (master_priv->sarea_priv) |
62 | master_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT; | |
1da177e4 LT |
63 | |
64 | if (ring->head != last_head) | |
65 | i = 0; | |
d3a6d446 KP |
66 | if (acthd != last_acthd) |
67 | i = 0; | |
1da177e4 LT |
68 | |
69 | last_head = ring->head; | |
d3a6d446 KP |
70 | last_acthd = acthd; |
71 | msleep_interruptible(10); | |
72 | ||
1da177e4 LT |
73 | } |
74 | ||
20caafa6 | 75 | return -EBUSY; |
1da177e4 LT |
76 | } |
77 | ||
398c9cb2 KP |
78 | /** |
79 | * Sets up the hardware status page for devices that need a physical address | |
80 | * in the register. | |
81 | */ | |
3043c60c | 82 | static int i915_init_phys_hws(struct drm_device *dev) |
398c9cb2 KP |
83 | { |
84 | drm_i915_private_t *dev_priv = dev->dev_private; | |
85 | /* Program Hardware Status Page */ | |
86 | dev_priv->status_page_dmah = | |
87 | drm_pci_alloc(dev, PAGE_SIZE, PAGE_SIZE, 0xffffffff); | |
88 | ||
89 | if (!dev_priv->status_page_dmah) { | |
90 | DRM_ERROR("Can not allocate hardware status page\n"); | |
91 | return -ENOMEM; | |
92 | } | |
93 | dev_priv->hw_status_page = dev_priv->status_page_dmah->vaddr; | |
94 | dev_priv->dma_status_page = dev_priv->status_page_dmah->busaddr; | |
95 | ||
96 | memset(dev_priv->hw_status_page, 0, PAGE_SIZE); | |
97 | ||
98 | I915_WRITE(HWS_PGA, dev_priv->dma_status_page); | |
99 | DRM_DEBUG("Enabled hardware status page\n"); | |
100 | return 0; | |
101 | } | |
102 | ||
103 | /** | |
104 | * Frees the hardware status page, whether it's a physical address or a virtual | |
105 | * address set up by the X Server. | |
106 | */ | |
3043c60c | 107 | static void i915_free_hws(struct drm_device *dev) |
398c9cb2 KP |
108 | { |
109 | drm_i915_private_t *dev_priv = dev->dev_private; | |
110 | if (dev_priv->status_page_dmah) { | |
111 | drm_pci_free(dev, dev_priv->status_page_dmah); | |
112 | dev_priv->status_page_dmah = NULL; | |
113 | } | |
114 | ||
115 | if (dev_priv->status_gfx_addr) { | |
116 | dev_priv->status_gfx_addr = 0; | |
117 | drm_core_ioremapfree(&dev_priv->hws_map, dev); | |
118 | } | |
119 | ||
120 | /* Need to rewrite hardware status page */ | |
121 | I915_WRITE(HWS_PGA, 0x1ffff000); | |
122 | } | |
123 | ||
84b1fd10 | 124 | void i915_kernel_lost_context(struct drm_device * dev) |
1da177e4 LT |
125 | { |
126 | drm_i915_private_t *dev_priv = dev->dev_private; | |
7c1c2871 | 127 | struct drm_i915_master_private *master_priv; |
1da177e4 LT |
128 | drm_i915_ring_buffer_t *ring = &(dev_priv->ring); |
129 | ||
79e53945 JB |
130 | /* |
131 | * We should never lose context on the ring with modesetting | |
132 | * as we don't expose it to userspace | |
133 | */ | |
134 | if (drm_core_check_feature(dev, DRIVER_MODESET)) | |
135 | return; | |
136 | ||
585fb111 JB |
137 | ring->head = I915_READ(PRB0_HEAD) & HEAD_ADDR; |
138 | ring->tail = I915_READ(PRB0_TAIL) & TAIL_ADDR; | |
1da177e4 LT |
139 | ring->space = ring->head - (ring->tail + 8); |
140 | if (ring->space < 0) | |
141 | ring->space += ring->Size; | |
142 | ||
7c1c2871 DA |
143 | if (!dev->primary->master) |
144 | return; | |
145 | ||
146 | master_priv = dev->primary->master->driver_priv; | |
147 | if (ring->head == ring->tail && master_priv->sarea_priv) | |
148 | master_priv->sarea_priv->perf_boxes |= I915_BOX_RING_EMPTY; | |
1da177e4 LT |
149 | } |
150 | ||
84b1fd10 | 151 | static int i915_dma_cleanup(struct drm_device * dev) |
1da177e4 | 152 | { |
ba8bbcf6 | 153 | drm_i915_private_t *dev_priv = dev->dev_private; |
1da177e4 LT |
154 | /* Make sure interrupts are disabled here because the uninstall ioctl |
155 | * may not have been called from userspace and after dev_private | |
156 | * is freed, it's too late. | |
157 | */ | |
ed4cb414 | 158 | if (dev->irq_enabled) |
b5e89ed5 | 159 | drm_irq_uninstall(dev); |
1da177e4 | 160 | |
ba8bbcf6 JB |
161 | if (dev_priv->ring.virtual_start) { |
162 | drm_core_ioremapfree(&dev_priv->ring.map, dev); | |
3043c60c EA |
163 | dev_priv->ring.virtual_start = NULL; |
164 | dev_priv->ring.map.handle = NULL; | |
ba8bbcf6 JB |
165 | dev_priv->ring.map.size = 0; |
166 | } | |
dc7a9319 | 167 | |
398c9cb2 KP |
168 | /* Clear the HWS virtual address at teardown */ |
169 | if (I915_NEED_GFX_HWS(dev)) | |
170 | i915_free_hws(dev); | |
1da177e4 LT |
171 | |
172 | return 0; | |
173 | } | |
174 | ||
ba8bbcf6 | 175 | static int i915_initialize(struct drm_device * dev, drm_i915_init_t * init) |
1da177e4 | 176 | { |
ba8bbcf6 | 177 | drm_i915_private_t *dev_priv = dev->dev_private; |
7c1c2871 | 178 | struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv; |
1da177e4 | 179 | |
3a03ac1a DA |
180 | master_priv->sarea = drm_getsarea(dev); |
181 | if (master_priv->sarea) { | |
182 | master_priv->sarea_priv = (drm_i915_sarea_t *) | |
183 | ((u8 *)master_priv->sarea->handle + init->sarea_priv_offset); | |
184 | } else { | |
185 | DRM_DEBUG("sarea not found assuming DRI2 userspace\n"); | |
186 | } | |
187 | ||
673a394b EA |
188 | if (init->ring_size != 0) { |
189 | if (dev_priv->ring.ring_obj != NULL) { | |
190 | i915_dma_cleanup(dev); | |
191 | DRM_ERROR("Client tried to initialize ringbuffer in " | |
192 | "GEM mode\n"); | |
193 | return -EINVAL; | |
194 | } | |
1da177e4 | 195 | |
673a394b EA |
196 | dev_priv->ring.Size = init->ring_size; |
197 | dev_priv->ring.tail_mask = dev_priv->ring.Size - 1; | |
1da177e4 | 198 | |
673a394b EA |
199 | dev_priv->ring.map.offset = init->ring_start; |
200 | dev_priv->ring.map.size = init->ring_size; | |
201 | dev_priv->ring.map.type = 0; | |
202 | dev_priv->ring.map.flags = 0; | |
203 | dev_priv->ring.map.mtrr = 0; | |
1da177e4 | 204 | |
673a394b EA |
205 | drm_core_ioremap(&dev_priv->ring.map, dev); |
206 | ||
207 | if (dev_priv->ring.map.handle == NULL) { | |
208 | i915_dma_cleanup(dev); | |
209 | DRM_ERROR("can not ioremap virtual address for" | |
210 | " ring buffer\n"); | |
211 | return -ENOMEM; | |
212 | } | |
1da177e4 LT |
213 | } |
214 | ||
215 | dev_priv->ring.virtual_start = dev_priv->ring.map.handle; | |
216 | ||
a6b54f3f | 217 | dev_priv->cpp = init->cpp; |
1da177e4 LT |
218 | dev_priv->back_offset = init->back_offset; |
219 | dev_priv->front_offset = init->front_offset; | |
220 | dev_priv->current_page = 0; | |
7c1c2871 DA |
221 | if (master_priv->sarea_priv) |
222 | master_priv->sarea_priv->pf_current_page = 0; | |
1da177e4 | 223 | |
1da177e4 LT |
224 | /* Allow hardware batchbuffers unless told otherwise. |
225 | */ | |
226 | dev_priv->allow_batchbuffer = 1; | |
227 | ||
1da177e4 LT |
228 | return 0; |
229 | } | |
230 | ||
84b1fd10 | 231 | static int i915_dma_resume(struct drm_device * dev) |
1da177e4 LT |
232 | { |
233 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
234 | ||
bf9d8929 | 235 | DRM_DEBUG("%s\n", __func__); |
1da177e4 | 236 | |
1da177e4 LT |
237 | if (dev_priv->ring.map.handle == NULL) { |
238 | DRM_ERROR("can not ioremap virtual address for" | |
239 | " ring buffer\n"); | |
20caafa6 | 240 | return -ENOMEM; |
1da177e4 LT |
241 | } |
242 | ||
243 | /* Program Hardware Status Page */ | |
244 | if (!dev_priv->hw_status_page) { | |
245 | DRM_ERROR("Can not find hardware status page\n"); | |
20caafa6 | 246 | return -EINVAL; |
1da177e4 LT |
247 | } |
248 | DRM_DEBUG("hw status page @ %p\n", dev_priv->hw_status_page); | |
249 | ||
dc7a9319 | 250 | if (dev_priv->status_gfx_addr != 0) |
585fb111 | 251 | I915_WRITE(HWS_PGA, dev_priv->status_gfx_addr); |
dc7a9319 | 252 | else |
585fb111 | 253 | I915_WRITE(HWS_PGA, dev_priv->dma_status_page); |
1da177e4 LT |
254 | DRM_DEBUG("Enabled hardware status page\n"); |
255 | ||
256 | return 0; | |
257 | } | |
258 | ||
c153f45f EA |
259 | static int i915_dma_init(struct drm_device *dev, void *data, |
260 | struct drm_file *file_priv) | |
1da177e4 | 261 | { |
c153f45f | 262 | drm_i915_init_t *init = data; |
1da177e4 LT |
263 | int retcode = 0; |
264 | ||
c153f45f | 265 | switch (init->func) { |
1da177e4 | 266 | case I915_INIT_DMA: |
ba8bbcf6 | 267 | retcode = i915_initialize(dev, init); |
1da177e4 LT |
268 | break; |
269 | case I915_CLEANUP_DMA: | |
270 | retcode = i915_dma_cleanup(dev); | |
271 | break; | |
272 | case I915_RESUME_DMA: | |
0d6aa60b | 273 | retcode = i915_dma_resume(dev); |
1da177e4 LT |
274 | break; |
275 | default: | |
20caafa6 | 276 | retcode = -EINVAL; |
1da177e4 LT |
277 | break; |
278 | } | |
279 | ||
280 | return retcode; | |
281 | } | |
282 | ||
283 | /* Implement basically the same security restrictions as hardware does | |
284 | * for MI_BATCH_NON_SECURE. These can be made stricter at any time. | |
285 | * | |
286 | * Most of the calculations below involve calculating the size of a | |
287 | * particular instruction. It's important to get the size right as | |
288 | * that tells us where the next instruction to check is. Any illegal | |
289 | * instruction detected will be given a size of zero, which is a | |
290 | * signal to abort the rest of the buffer. | |
291 | */ | |
292 | static int do_validate_cmd(int cmd) | |
293 | { | |
294 | switch (((cmd >> 29) & 0x7)) { | |
295 | case 0x0: | |
296 | switch ((cmd >> 23) & 0x3f) { | |
297 | case 0x0: | |
298 | return 1; /* MI_NOOP */ | |
299 | case 0x4: | |
300 | return 1; /* MI_FLUSH */ | |
301 | default: | |
302 | return 0; /* disallow everything else */ | |
303 | } | |
304 | break; | |
305 | case 0x1: | |
306 | return 0; /* reserved */ | |
307 | case 0x2: | |
308 | return (cmd & 0xff) + 2; /* 2d commands */ | |
309 | case 0x3: | |
310 | if (((cmd >> 24) & 0x1f) <= 0x18) | |
311 | return 1; | |
312 | ||
313 | switch ((cmd >> 24) & 0x1f) { | |
314 | case 0x1c: | |
315 | return 1; | |
316 | case 0x1d: | |
b5e89ed5 | 317 | switch ((cmd >> 16) & 0xff) { |
1da177e4 LT |
318 | case 0x3: |
319 | return (cmd & 0x1f) + 2; | |
320 | case 0x4: | |
321 | return (cmd & 0xf) + 2; | |
322 | default: | |
323 | return (cmd & 0xffff) + 2; | |
324 | } | |
325 | case 0x1e: | |
326 | if (cmd & (1 << 23)) | |
327 | return (cmd & 0xffff) + 1; | |
328 | else | |
329 | return 1; | |
330 | case 0x1f: | |
331 | if ((cmd & (1 << 23)) == 0) /* inline vertices */ | |
332 | return (cmd & 0x1ffff) + 2; | |
333 | else if (cmd & (1 << 17)) /* indirect random */ | |
334 | if ((cmd & 0xffff) == 0) | |
335 | return 0; /* unknown length, too hard */ | |
336 | else | |
337 | return (((cmd & 0xffff) + 1) / 2) + 1; | |
338 | else | |
339 | return 2; /* indirect sequential */ | |
340 | default: | |
341 | return 0; | |
342 | } | |
343 | default: | |
344 | return 0; | |
345 | } | |
346 | ||
347 | return 0; | |
348 | } | |
349 | ||
350 | static int validate_cmd(int cmd) | |
351 | { | |
352 | int ret = do_validate_cmd(cmd); | |
353 | ||
bc5f4523 | 354 | /* printk("validate_cmd( %x ): %d\n", cmd, ret); */ |
1da177e4 LT |
355 | |
356 | return ret; | |
357 | } | |
358 | ||
84b1fd10 | 359 | static int i915_emit_cmds(struct drm_device * dev, int __user * buffer, int dwords) |
1da177e4 LT |
360 | { |
361 | drm_i915_private_t *dev_priv = dev->dev_private; | |
362 | int i; | |
363 | RING_LOCALS; | |
364 | ||
de227f5f | 365 | if ((dwords+1) * sizeof(int) >= dev_priv->ring.Size - 8) |
20caafa6 | 366 | return -EINVAL; |
de227f5f | 367 | |
c29b669c | 368 | BEGIN_LP_RING((dwords+1)&~1); |
de227f5f | 369 | |
1da177e4 LT |
370 | for (i = 0; i < dwords;) { |
371 | int cmd, sz; | |
372 | ||
373 | if (DRM_COPY_FROM_USER_UNCHECKED(&cmd, &buffer[i], sizeof(cmd))) | |
20caafa6 | 374 | return -EINVAL; |
1da177e4 | 375 | |
1da177e4 | 376 | if ((sz = validate_cmd(cmd)) == 0 || i + sz > dwords) |
20caafa6 | 377 | return -EINVAL; |
1da177e4 | 378 | |
1da177e4 LT |
379 | OUT_RING(cmd); |
380 | ||
381 | while (++i, --sz) { | |
382 | if (DRM_COPY_FROM_USER_UNCHECKED(&cmd, &buffer[i], | |
383 | sizeof(cmd))) { | |
20caafa6 | 384 | return -EINVAL; |
1da177e4 LT |
385 | } |
386 | OUT_RING(cmd); | |
387 | } | |
1da177e4 LT |
388 | } |
389 | ||
de227f5f DA |
390 | if (dwords & 1) |
391 | OUT_RING(0); | |
392 | ||
393 | ADVANCE_LP_RING(); | |
394 | ||
1da177e4 LT |
395 | return 0; |
396 | } | |
397 | ||
673a394b EA |
398 | int |
399 | i915_emit_box(struct drm_device *dev, | |
400 | struct drm_clip_rect __user *boxes, | |
401 | int i, int DR1, int DR4) | |
1da177e4 LT |
402 | { |
403 | drm_i915_private_t *dev_priv = dev->dev_private; | |
c60ce623 | 404 | struct drm_clip_rect box; |
1da177e4 LT |
405 | RING_LOCALS; |
406 | ||
407 | if (DRM_COPY_FROM_USER_UNCHECKED(&box, &boxes[i], sizeof(box))) { | |
20caafa6 | 408 | return -EFAULT; |
1da177e4 LT |
409 | } |
410 | ||
411 | if (box.y2 <= box.y1 || box.x2 <= box.x1 || box.y2 <= 0 || box.x2 <= 0) { | |
412 | DRM_ERROR("Bad box %d,%d..%d,%d\n", | |
413 | box.x1, box.y1, box.x2, box.y2); | |
20caafa6 | 414 | return -EINVAL; |
1da177e4 LT |
415 | } |
416 | ||
c29b669c AH |
417 | if (IS_I965G(dev)) { |
418 | BEGIN_LP_RING(4); | |
419 | OUT_RING(GFX_OP_DRAWRECT_INFO_I965); | |
420 | OUT_RING((box.x1 & 0xffff) | (box.y1 << 16)); | |
78eca43d | 421 | OUT_RING(((box.x2 - 1) & 0xffff) | ((box.y2 - 1) << 16)); |
c29b669c AH |
422 | OUT_RING(DR4); |
423 | ADVANCE_LP_RING(); | |
424 | } else { | |
425 | BEGIN_LP_RING(6); | |
426 | OUT_RING(GFX_OP_DRAWRECT_INFO); | |
427 | OUT_RING(DR1); | |
428 | OUT_RING((box.x1 & 0xffff) | (box.y1 << 16)); | |
429 | OUT_RING(((box.x2 - 1) & 0xffff) | ((box.y2 - 1) << 16)); | |
430 | OUT_RING(DR4); | |
431 | OUT_RING(0); | |
432 | ADVANCE_LP_RING(); | |
433 | } | |
1da177e4 LT |
434 | |
435 | return 0; | |
436 | } | |
437 | ||
c29b669c AH |
438 | /* XXX: Emitting the counter should really be moved to part of the IRQ |
439 | * emit. For now, do it in both places: | |
440 | */ | |
441 | ||
84b1fd10 | 442 | static void i915_emit_breadcrumb(struct drm_device *dev) |
de227f5f DA |
443 | { |
444 | drm_i915_private_t *dev_priv = dev->dev_private; | |
7c1c2871 | 445 | struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv; |
de227f5f DA |
446 | RING_LOCALS; |
447 | ||
c99b058f | 448 | dev_priv->counter++; |
af6061af | 449 | if (dev_priv->counter > 0x7FFFFFFFUL) |
c99b058f | 450 | dev_priv->counter = 0; |
7c1c2871 DA |
451 | if (master_priv->sarea_priv) |
452 | master_priv->sarea_priv->last_enqueue = dev_priv->counter; | |
de227f5f DA |
453 | |
454 | BEGIN_LP_RING(4); | |
585fb111 | 455 | OUT_RING(MI_STORE_DWORD_INDEX); |
0baf823a | 456 | OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT); |
de227f5f DA |
457 | OUT_RING(dev_priv->counter); |
458 | OUT_RING(0); | |
459 | ADVANCE_LP_RING(); | |
460 | } | |
461 | ||
84b1fd10 | 462 | static int i915_dispatch_cmdbuffer(struct drm_device * dev, |
1da177e4 LT |
463 | drm_i915_cmdbuffer_t * cmd) |
464 | { | |
465 | int nbox = cmd->num_cliprects; | |
466 | int i = 0, count, ret; | |
467 | ||
468 | if (cmd->sz & 0x3) { | |
469 | DRM_ERROR("alignment"); | |
20caafa6 | 470 | return -EINVAL; |
1da177e4 LT |
471 | } |
472 | ||
473 | i915_kernel_lost_context(dev); | |
474 | ||
475 | count = nbox ? nbox : 1; | |
476 | ||
477 | for (i = 0; i < count; i++) { | |
478 | if (i < nbox) { | |
479 | ret = i915_emit_box(dev, cmd->cliprects, i, | |
480 | cmd->DR1, cmd->DR4); | |
481 | if (ret) | |
482 | return ret; | |
483 | } | |
484 | ||
485 | ret = i915_emit_cmds(dev, (int __user *)cmd->buf, cmd->sz / 4); | |
486 | if (ret) | |
487 | return ret; | |
488 | } | |
489 | ||
de227f5f | 490 | i915_emit_breadcrumb(dev); |
1da177e4 LT |
491 | return 0; |
492 | } | |
493 | ||
84b1fd10 | 494 | static int i915_dispatch_batchbuffer(struct drm_device * dev, |
1da177e4 LT |
495 | drm_i915_batchbuffer_t * batch) |
496 | { | |
497 | drm_i915_private_t *dev_priv = dev->dev_private; | |
c60ce623 | 498 | struct drm_clip_rect __user *boxes = batch->cliprects; |
1da177e4 LT |
499 | int nbox = batch->num_cliprects; |
500 | int i = 0, count; | |
501 | RING_LOCALS; | |
502 | ||
503 | if ((batch->start | batch->used) & 0x7) { | |
504 | DRM_ERROR("alignment"); | |
20caafa6 | 505 | return -EINVAL; |
1da177e4 LT |
506 | } |
507 | ||
508 | i915_kernel_lost_context(dev); | |
509 | ||
510 | count = nbox ? nbox : 1; | |
511 | ||
512 | for (i = 0; i < count; i++) { | |
513 | if (i < nbox) { | |
514 | int ret = i915_emit_box(dev, boxes, i, | |
515 | batch->DR1, batch->DR4); | |
516 | if (ret) | |
517 | return ret; | |
518 | } | |
519 | ||
0790d5e1 | 520 | if (!IS_I830(dev) && !IS_845G(dev)) { |
1da177e4 | 521 | BEGIN_LP_RING(2); |
21f16289 DA |
522 | if (IS_I965G(dev)) { |
523 | OUT_RING(MI_BATCH_BUFFER_START | (2 << 6) | MI_BATCH_NON_SECURE_I965); | |
524 | OUT_RING(batch->start); | |
525 | } else { | |
526 | OUT_RING(MI_BATCH_BUFFER_START | (2 << 6)); | |
527 | OUT_RING(batch->start | MI_BATCH_NON_SECURE); | |
528 | } | |
1da177e4 LT |
529 | ADVANCE_LP_RING(); |
530 | } else { | |
531 | BEGIN_LP_RING(4); | |
532 | OUT_RING(MI_BATCH_BUFFER); | |
533 | OUT_RING(batch->start | MI_BATCH_NON_SECURE); | |
534 | OUT_RING(batch->start + batch->used - 4); | |
535 | OUT_RING(0); | |
536 | ADVANCE_LP_RING(); | |
537 | } | |
538 | } | |
539 | ||
de227f5f | 540 | i915_emit_breadcrumb(dev); |
1da177e4 LT |
541 | |
542 | return 0; | |
543 | } | |
544 | ||
af6061af | 545 | static int i915_dispatch_flip(struct drm_device * dev) |
1da177e4 LT |
546 | { |
547 | drm_i915_private_t *dev_priv = dev->dev_private; | |
7c1c2871 DA |
548 | struct drm_i915_master_private *master_priv = |
549 | dev->primary->master->driver_priv; | |
1da177e4 LT |
550 | RING_LOCALS; |
551 | ||
7c1c2871 | 552 | if (!master_priv->sarea_priv) |
c99b058f KH |
553 | return -EINVAL; |
554 | ||
af6061af | 555 | DRM_DEBUG("%s: page=%d pfCurrentPage=%d\n", |
80a914dc | 556 | __func__, |
af6061af | 557 | dev_priv->current_page, |
7c1c2871 | 558 | master_priv->sarea_priv->pf_current_page); |
1da177e4 | 559 | |
af6061af DA |
560 | i915_kernel_lost_context(dev); |
561 | ||
562 | BEGIN_LP_RING(2); | |
585fb111 | 563 | OUT_RING(MI_FLUSH | MI_READ_FLUSH); |
af6061af DA |
564 | OUT_RING(0); |
565 | ADVANCE_LP_RING(); | |
1da177e4 | 566 | |
af6061af DA |
567 | BEGIN_LP_RING(6); |
568 | OUT_RING(CMD_OP_DISPLAYBUFFER_INFO | ASYNC_FLIP); | |
569 | OUT_RING(0); | |
570 | if (dev_priv->current_page == 0) { | |
571 | OUT_RING(dev_priv->back_offset); | |
572 | dev_priv->current_page = 1; | |
1da177e4 | 573 | } else { |
af6061af DA |
574 | OUT_RING(dev_priv->front_offset); |
575 | dev_priv->current_page = 0; | |
1da177e4 | 576 | } |
af6061af DA |
577 | OUT_RING(0); |
578 | ADVANCE_LP_RING(); | |
1da177e4 | 579 | |
af6061af DA |
580 | BEGIN_LP_RING(2); |
581 | OUT_RING(MI_WAIT_FOR_EVENT | MI_WAIT_FOR_PLANE_A_FLIP); | |
582 | OUT_RING(0); | |
583 | ADVANCE_LP_RING(); | |
1da177e4 | 584 | |
7c1c2871 | 585 | master_priv->sarea_priv->last_enqueue = dev_priv->counter++; |
1da177e4 LT |
586 | |
587 | BEGIN_LP_RING(4); | |
585fb111 | 588 | OUT_RING(MI_STORE_DWORD_INDEX); |
0baf823a | 589 | OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT); |
af6061af DA |
590 | OUT_RING(dev_priv->counter); |
591 | OUT_RING(0); | |
1da177e4 LT |
592 | ADVANCE_LP_RING(); |
593 | ||
7c1c2871 | 594 | master_priv->sarea_priv->pf_current_page = dev_priv->current_page; |
af6061af | 595 | return 0; |
1da177e4 LT |
596 | } |
597 | ||
84b1fd10 | 598 | static int i915_quiescent(struct drm_device * dev) |
1da177e4 LT |
599 | { |
600 | drm_i915_private_t *dev_priv = dev->dev_private; | |
601 | ||
602 | i915_kernel_lost_context(dev); | |
bf9d8929 | 603 | return i915_wait_ring(dev, dev_priv->ring.Size - 8, __func__); |
1da177e4 LT |
604 | } |
605 | ||
c153f45f EA |
606 | static int i915_flush_ioctl(struct drm_device *dev, void *data, |
607 | struct drm_file *file_priv) | |
1da177e4 | 608 | { |
546b0974 EA |
609 | int ret; |
610 | ||
611 | RING_LOCK_TEST_WITH_RETURN(dev, file_priv); | |
1da177e4 | 612 | |
546b0974 EA |
613 | mutex_lock(&dev->struct_mutex); |
614 | ret = i915_quiescent(dev); | |
615 | mutex_unlock(&dev->struct_mutex); | |
616 | ||
617 | return ret; | |
1da177e4 LT |
618 | } |
619 | ||
c153f45f EA |
620 | static int i915_batchbuffer(struct drm_device *dev, void *data, |
621 | struct drm_file *file_priv) | |
1da177e4 | 622 | { |
1da177e4 | 623 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
7c1c2871 | 624 | struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv; |
1da177e4 | 625 | drm_i915_sarea_t *sarea_priv = (drm_i915_sarea_t *) |
7c1c2871 | 626 | master_priv->sarea_priv; |
c153f45f | 627 | drm_i915_batchbuffer_t *batch = data; |
1da177e4 LT |
628 | int ret; |
629 | ||
630 | if (!dev_priv->allow_batchbuffer) { | |
631 | DRM_ERROR("Batchbuffer ioctl disabled\n"); | |
20caafa6 | 632 | return -EINVAL; |
1da177e4 LT |
633 | } |
634 | ||
1da177e4 | 635 | DRM_DEBUG("i915 batchbuffer, start %x used %d cliprects %d\n", |
c153f45f | 636 | batch->start, batch->used, batch->num_cliprects); |
1da177e4 | 637 | |
546b0974 | 638 | RING_LOCK_TEST_WITH_RETURN(dev, file_priv); |
1da177e4 | 639 | |
c153f45f EA |
640 | if (batch->num_cliprects && DRM_VERIFYAREA_READ(batch->cliprects, |
641 | batch->num_cliprects * | |
c60ce623 | 642 | sizeof(struct drm_clip_rect))) |
20caafa6 | 643 | return -EFAULT; |
1da177e4 | 644 | |
546b0974 | 645 | mutex_lock(&dev->struct_mutex); |
c153f45f | 646 | ret = i915_dispatch_batchbuffer(dev, batch); |
546b0974 | 647 | mutex_unlock(&dev->struct_mutex); |
1da177e4 | 648 | |
c99b058f | 649 | if (sarea_priv) |
0baf823a | 650 | sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv); |
1da177e4 LT |
651 | return ret; |
652 | } | |
653 | ||
c153f45f EA |
654 | static int i915_cmdbuffer(struct drm_device *dev, void *data, |
655 | struct drm_file *file_priv) | |
1da177e4 | 656 | { |
1da177e4 | 657 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
7c1c2871 | 658 | struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv; |
1da177e4 | 659 | drm_i915_sarea_t *sarea_priv = (drm_i915_sarea_t *) |
7c1c2871 | 660 | master_priv->sarea_priv; |
c153f45f | 661 | drm_i915_cmdbuffer_t *cmdbuf = data; |
1da177e4 LT |
662 | int ret; |
663 | ||
1da177e4 | 664 | DRM_DEBUG("i915 cmdbuffer, buf %p sz %d cliprects %d\n", |
c153f45f | 665 | cmdbuf->buf, cmdbuf->sz, cmdbuf->num_cliprects); |
1da177e4 | 666 | |
546b0974 | 667 | RING_LOCK_TEST_WITH_RETURN(dev, file_priv); |
1da177e4 | 668 | |
c153f45f EA |
669 | if (cmdbuf->num_cliprects && |
670 | DRM_VERIFYAREA_READ(cmdbuf->cliprects, | |
671 | cmdbuf->num_cliprects * | |
c60ce623 | 672 | sizeof(struct drm_clip_rect))) { |
1da177e4 | 673 | DRM_ERROR("Fault accessing cliprects\n"); |
20caafa6 | 674 | return -EFAULT; |
1da177e4 LT |
675 | } |
676 | ||
546b0974 | 677 | mutex_lock(&dev->struct_mutex); |
c153f45f | 678 | ret = i915_dispatch_cmdbuffer(dev, cmdbuf); |
546b0974 | 679 | mutex_unlock(&dev->struct_mutex); |
1da177e4 LT |
680 | if (ret) { |
681 | DRM_ERROR("i915_dispatch_cmdbuffer failed\n"); | |
682 | return ret; | |
683 | } | |
684 | ||
c99b058f | 685 | if (sarea_priv) |
0baf823a | 686 | sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv); |
1da177e4 LT |
687 | return 0; |
688 | } | |
689 | ||
c153f45f EA |
690 | static int i915_flip_bufs(struct drm_device *dev, void *data, |
691 | struct drm_file *file_priv) | |
1da177e4 | 692 | { |
546b0974 EA |
693 | int ret; |
694 | ||
80a914dc | 695 | DRM_DEBUG("%s\n", __func__); |
1da177e4 | 696 | |
546b0974 | 697 | RING_LOCK_TEST_WITH_RETURN(dev, file_priv); |
1da177e4 | 698 | |
546b0974 EA |
699 | mutex_lock(&dev->struct_mutex); |
700 | ret = i915_dispatch_flip(dev); | |
701 | mutex_unlock(&dev->struct_mutex); | |
702 | ||
703 | return ret; | |
1da177e4 LT |
704 | } |
705 | ||
c153f45f EA |
706 | static int i915_getparam(struct drm_device *dev, void *data, |
707 | struct drm_file *file_priv) | |
1da177e4 | 708 | { |
1da177e4 | 709 | drm_i915_private_t *dev_priv = dev->dev_private; |
c153f45f | 710 | drm_i915_getparam_t *param = data; |
1da177e4 LT |
711 | int value; |
712 | ||
713 | if (!dev_priv) { | |
3e684eae | 714 | DRM_ERROR("called with no initialization\n"); |
20caafa6 | 715 | return -EINVAL; |
1da177e4 LT |
716 | } |
717 | ||
c153f45f | 718 | switch (param->param) { |
1da177e4 | 719 | case I915_PARAM_IRQ_ACTIVE: |
0a3e67a4 | 720 | value = dev->pdev->irq ? 1 : 0; |
1da177e4 LT |
721 | break; |
722 | case I915_PARAM_ALLOW_BATCHBUFFER: | |
723 | value = dev_priv->allow_batchbuffer ? 1 : 0; | |
724 | break; | |
0d6aa60b DA |
725 | case I915_PARAM_LAST_DISPATCH: |
726 | value = READ_BREADCRUMB(dev_priv); | |
727 | break; | |
ed4c9c4a KH |
728 | case I915_PARAM_CHIPSET_ID: |
729 | value = dev->pci_device; | |
730 | break; | |
673a394b | 731 | case I915_PARAM_HAS_GEM: |
ac5c4e76 | 732 | value = dev_priv->has_gem; |
673a394b | 733 | break; |
1da177e4 | 734 | default: |
c153f45f | 735 | DRM_ERROR("Unknown parameter %d\n", param->param); |
20caafa6 | 736 | return -EINVAL; |
1da177e4 LT |
737 | } |
738 | ||
c153f45f | 739 | if (DRM_COPY_TO_USER(param->value, &value, sizeof(int))) { |
1da177e4 | 740 | DRM_ERROR("DRM_COPY_TO_USER failed\n"); |
20caafa6 | 741 | return -EFAULT; |
1da177e4 LT |
742 | } |
743 | ||
744 | return 0; | |
745 | } | |
746 | ||
c153f45f EA |
747 | static int i915_setparam(struct drm_device *dev, void *data, |
748 | struct drm_file *file_priv) | |
1da177e4 | 749 | { |
1da177e4 | 750 | drm_i915_private_t *dev_priv = dev->dev_private; |
c153f45f | 751 | drm_i915_setparam_t *param = data; |
1da177e4 LT |
752 | |
753 | if (!dev_priv) { | |
3e684eae | 754 | DRM_ERROR("called with no initialization\n"); |
20caafa6 | 755 | return -EINVAL; |
1da177e4 LT |
756 | } |
757 | ||
c153f45f | 758 | switch (param->param) { |
1da177e4 | 759 | case I915_SETPARAM_USE_MI_BATCHBUFFER_START: |
1da177e4 LT |
760 | break; |
761 | case I915_SETPARAM_TEX_LRU_LOG_GRANULARITY: | |
c153f45f | 762 | dev_priv->tex_lru_log_granularity = param->value; |
1da177e4 LT |
763 | break; |
764 | case I915_SETPARAM_ALLOW_BATCHBUFFER: | |
c153f45f | 765 | dev_priv->allow_batchbuffer = param->value; |
1da177e4 LT |
766 | break; |
767 | default: | |
c153f45f | 768 | DRM_ERROR("unknown parameter %d\n", param->param); |
20caafa6 | 769 | return -EINVAL; |
1da177e4 LT |
770 | } |
771 | ||
772 | return 0; | |
773 | } | |
774 | ||
c153f45f EA |
775 | static int i915_set_status_page(struct drm_device *dev, void *data, |
776 | struct drm_file *file_priv) | |
dc7a9319 | 777 | { |
dc7a9319 | 778 | drm_i915_private_t *dev_priv = dev->dev_private; |
c153f45f | 779 | drm_i915_hws_addr_t *hws = data; |
b39d50e5 ZW |
780 | |
781 | if (!I915_NEED_GFX_HWS(dev)) | |
782 | return -EINVAL; | |
dc7a9319 WZ |
783 | |
784 | if (!dev_priv) { | |
3e684eae | 785 | DRM_ERROR("called with no initialization\n"); |
20caafa6 | 786 | return -EINVAL; |
dc7a9319 | 787 | } |
dc7a9319 | 788 | |
79e53945 JB |
789 | if (drm_core_check_feature(dev, DRIVER_MODESET)) { |
790 | WARN(1, "tried to set status page when mode setting active\n"); | |
791 | return 0; | |
792 | } | |
793 | ||
c153f45f EA |
794 | printk(KERN_DEBUG "set status page addr 0x%08x\n", (u32)hws->addr); |
795 | ||
796 | dev_priv->status_gfx_addr = hws->addr & (0x1ffff<<12); | |
dc7a9319 | 797 | |
8b409580 | 798 | dev_priv->hws_map.offset = dev->agp->base + hws->addr; |
dc7a9319 WZ |
799 | dev_priv->hws_map.size = 4*1024; |
800 | dev_priv->hws_map.type = 0; | |
801 | dev_priv->hws_map.flags = 0; | |
802 | dev_priv->hws_map.mtrr = 0; | |
803 | ||
804 | drm_core_ioremap(&dev_priv->hws_map, dev); | |
805 | if (dev_priv->hws_map.handle == NULL) { | |
dc7a9319 WZ |
806 | i915_dma_cleanup(dev); |
807 | dev_priv->status_gfx_addr = 0; | |
808 | DRM_ERROR("can not ioremap virtual address for" | |
809 | " G33 hw status page\n"); | |
20caafa6 | 810 | return -ENOMEM; |
dc7a9319 WZ |
811 | } |
812 | dev_priv->hw_status_page = dev_priv->hws_map.handle; | |
813 | ||
814 | memset(dev_priv->hw_status_page, 0, PAGE_SIZE); | |
585fb111 JB |
815 | I915_WRITE(HWS_PGA, dev_priv->status_gfx_addr); |
816 | DRM_DEBUG("load hws HWS_PGA with gfx mem 0x%x\n", | |
dc7a9319 WZ |
817 | dev_priv->status_gfx_addr); |
818 | DRM_DEBUG("load hws at %p\n", dev_priv->hw_status_page); | |
819 | return 0; | |
820 | } | |
821 | ||
79e53945 JB |
822 | /** |
823 | * i915_probe_agp - get AGP bootup configuration | |
824 | * @pdev: PCI device | |
825 | * @aperture_size: returns AGP aperture configured size | |
826 | * @preallocated_size: returns size of BIOS preallocated AGP space | |
827 | * | |
828 | * Since Intel integrated graphics are UMA, the BIOS has to set aside | |
829 | * some RAM for the framebuffer at early boot. This code figures out | |
830 | * how much was set aside so we can use it for our own purposes. | |
831 | */ | |
b358d0a6 HE |
832 | static int i915_probe_agp(struct drm_device *dev, unsigned long *aperture_size, |
833 | unsigned long *preallocated_size) | |
79e53945 JB |
834 | { |
835 | struct pci_dev *bridge_dev; | |
836 | u16 tmp = 0; | |
837 | unsigned long overhead; | |
241fa85b | 838 | unsigned long stolen; |
79e53945 JB |
839 | |
840 | bridge_dev = pci_get_bus_and_slot(0, PCI_DEVFN(0,0)); | |
841 | if (!bridge_dev) { | |
842 | DRM_ERROR("bridge device not found\n"); | |
843 | return -1; | |
844 | } | |
845 | ||
846 | /* Get the fb aperture size and "stolen" memory amount. */ | |
847 | pci_read_config_word(bridge_dev, INTEL_GMCH_CTRL, &tmp); | |
848 | pci_dev_put(bridge_dev); | |
849 | ||
850 | *aperture_size = 1024 * 1024; | |
851 | *preallocated_size = 1024 * 1024; | |
852 | ||
60fd99e3 | 853 | switch (dev->pdev->device) { |
79e53945 JB |
854 | case PCI_DEVICE_ID_INTEL_82830_CGC: |
855 | case PCI_DEVICE_ID_INTEL_82845G_IG: | |
856 | case PCI_DEVICE_ID_INTEL_82855GM_IG: | |
857 | case PCI_DEVICE_ID_INTEL_82865_IG: | |
858 | if ((tmp & INTEL_GMCH_MEM_MASK) == INTEL_GMCH_MEM_64M) | |
859 | *aperture_size *= 64; | |
860 | else | |
861 | *aperture_size *= 128; | |
862 | break; | |
863 | default: | |
864 | /* 9xx supports large sizes, just look at the length */ | |
60fd99e3 | 865 | *aperture_size = pci_resource_len(dev->pdev, 2); |
79e53945 JB |
866 | break; |
867 | } | |
868 | ||
869 | /* | |
870 | * Some of the preallocated space is taken by the GTT | |
871 | * and popup. GTT is 1K per MB of aperture size, and popup is 4K. | |
872 | */ | |
60fd99e3 EA |
873 | if (IS_G4X(dev)) |
874 | overhead = 4096; | |
875 | else | |
876 | overhead = (*aperture_size / 1024) + 4096; | |
877 | ||
241fa85b EA |
878 | switch (tmp & INTEL_GMCH_GMS_MASK) { |
879 | case INTEL_855_GMCH_GMS_DISABLED: | |
880 | DRM_ERROR("video memory is disabled\n"); | |
881 | return -1; | |
79e53945 | 882 | case INTEL_855_GMCH_GMS_STOLEN_1M: |
241fa85b EA |
883 | stolen = 1 * 1024 * 1024; |
884 | break; | |
79e53945 | 885 | case INTEL_855_GMCH_GMS_STOLEN_4M: |
241fa85b | 886 | stolen = 4 * 1024 * 1024; |
79e53945 JB |
887 | break; |
888 | case INTEL_855_GMCH_GMS_STOLEN_8M: | |
241fa85b | 889 | stolen = 8 * 1024 * 1024; |
79e53945 JB |
890 | break; |
891 | case INTEL_855_GMCH_GMS_STOLEN_16M: | |
241fa85b | 892 | stolen = 16 * 1024 * 1024; |
79e53945 JB |
893 | break; |
894 | case INTEL_855_GMCH_GMS_STOLEN_32M: | |
241fa85b | 895 | stolen = 32 * 1024 * 1024; |
79e53945 JB |
896 | break; |
897 | case INTEL_915G_GMCH_GMS_STOLEN_48M: | |
241fa85b | 898 | stolen = 48 * 1024 * 1024; |
79e53945 JB |
899 | break; |
900 | case INTEL_915G_GMCH_GMS_STOLEN_64M: | |
241fa85b EA |
901 | stolen = 64 * 1024 * 1024; |
902 | break; | |
903 | case INTEL_GMCH_GMS_STOLEN_128M: | |
904 | stolen = 128 * 1024 * 1024; | |
905 | break; | |
906 | case INTEL_GMCH_GMS_STOLEN_256M: | |
907 | stolen = 256 * 1024 * 1024; | |
908 | break; | |
909 | case INTEL_GMCH_GMS_STOLEN_96M: | |
910 | stolen = 96 * 1024 * 1024; | |
911 | break; | |
912 | case INTEL_GMCH_GMS_STOLEN_160M: | |
913 | stolen = 160 * 1024 * 1024; | |
914 | break; | |
915 | case INTEL_GMCH_GMS_STOLEN_224M: | |
916 | stolen = 224 * 1024 * 1024; | |
917 | break; | |
918 | case INTEL_GMCH_GMS_STOLEN_352M: | |
919 | stolen = 352 * 1024 * 1024; | |
79e53945 | 920 | break; |
79e53945 JB |
921 | default: |
922 | DRM_ERROR("unexpected GMCH_GMS value: 0x%02x\n", | |
241fa85b | 923 | tmp & INTEL_GMCH_GMS_MASK); |
79e53945 JB |
924 | return -1; |
925 | } | |
241fa85b | 926 | *preallocated_size = stolen - overhead; |
79e53945 JB |
927 | |
928 | return 0; | |
929 | } | |
930 | ||
931 | static int i915_load_modeset_init(struct drm_device *dev) | |
932 | { | |
933 | struct drm_i915_private *dev_priv = dev->dev_private; | |
934 | unsigned long agp_size, prealloc_size; | |
935 | int fb_bar = IS_I9XX(dev) ? 2 : 0; | |
936 | int ret = 0; | |
937 | ||
aa596629 DA |
938 | dev->devname = kstrdup(DRIVER_NAME, GFP_KERNEL); |
939 | if (!dev->devname) { | |
940 | ret = -ENOMEM; | |
941 | goto out; | |
942 | } | |
943 | ||
79e53945 JB |
944 | dev->mode_config.fb_base = drm_get_resource_start(dev, fb_bar) & |
945 | 0xff000000; | |
946 | ||
2906f025 | 947 | if (IS_MOBILE(dev) || IS_I9XX(dev)) |
79e53945 JB |
948 | dev_priv->cursor_needs_physical = true; |
949 | else | |
950 | dev_priv->cursor_needs_physical = false; | |
951 | ||
2906f025 JB |
952 | if (IS_I965G(dev) || IS_G33(dev)) |
953 | dev_priv->cursor_needs_physical = false; | |
954 | ||
aa596629 DA |
955 | ret = i915_probe_agp(dev, &agp_size, &prealloc_size); |
956 | if (ret) | |
957 | goto kfree_devname; | |
79e53945 JB |
958 | |
959 | /* Basic memrange allocator for stolen space (aka vram) */ | |
960 | drm_mm_init(&dev_priv->vram, 0, prealloc_size); | |
961 | ||
962 | /* Let GEM Manage from end of prealloc space to end of aperture */ | |
963 | i915_gem_do_init(dev, prealloc_size, agp_size); | |
964 | ||
965 | ret = i915_gem_init_ringbuffer(dev); | |
966 | if (ret) | |
aa596629 | 967 | goto kfree_devname; |
79e53945 | 968 | |
79e53945 JB |
969 | /* Allow hardware batchbuffers unless told otherwise. |
970 | */ | |
971 | dev_priv->allow_batchbuffer = 1; | |
972 | ||
973 | ret = intel_init_bios(dev); | |
974 | if (ret) | |
975 | DRM_INFO("failed to find VBIOS tables\n"); | |
976 | ||
977 | ret = drm_irq_install(dev); | |
978 | if (ret) | |
979 | goto destroy_ringbuffer; | |
980 | ||
981 | /* FIXME: re-add hotplug support */ | |
982 | #if 0 | |
983 | ret = drm_hotplug_init(dev); | |
984 | if (ret) | |
985 | goto destroy_ringbuffer; | |
986 | #endif | |
987 | ||
988 | /* Always safe in the mode setting case. */ | |
989 | /* FIXME: do pre/post-mode set stuff in core KMS code */ | |
990 | dev->vblank_disable_allowed = 1; | |
991 | ||
992 | /* | |
993 | * Initialize the hardware status page IRQ location. | |
994 | */ | |
995 | ||
996 | I915_WRITE(INSTPM, (1 << 5) | (1 << 21)); | |
997 | ||
998 | intel_modeset_init(dev); | |
999 | ||
1000 | drm_helper_initial_config(dev, false); | |
1001 | ||
79e53945 JB |
1002 | return 0; |
1003 | ||
79e53945 JB |
1004 | destroy_ringbuffer: |
1005 | i915_gem_cleanup_ringbuffer(dev); | |
aa596629 DA |
1006 | kfree_devname: |
1007 | kfree(dev->devname); | |
79e53945 JB |
1008 | out: |
1009 | return ret; | |
1010 | } | |
1011 | ||
7c1c2871 DA |
1012 | int i915_master_create(struct drm_device *dev, struct drm_master *master) |
1013 | { | |
1014 | struct drm_i915_master_private *master_priv; | |
1015 | ||
1016 | master_priv = drm_calloc(1, sizeof(*master_priv), DRM_MEM_DRIVER); | |
1017 | if (!master_priv) | |
1018 | return -ENOMEM; | |
1019 | ||
1020 | master->driver_priv = master_priv; | |
1021 | return 0; | |
1022 | } | |
1023 | ||
1024 | void i915_master_destroy(struct drm_device *dev, struct drm_master *master) | |
1025 | { | |
1026 | struct drm_i915_master_private *master_priv = master->driver_priv; | |
1027 | ||
1028 | if (!master_priv) | |
1029 | return; | |
1030 | ||
1031 | drm_free(master_priv, sizeof(*master_priv), DRM_MEM_DRIVER); | |
1032 | ||
1033 | master->driver_priv = NULL; | |
1034 | } | |
1035 | ||
79e53945 JB |
1036 | /** |
1037 | * i915_driver_load - setup chip and create an initial config | |
1038 | * @dev: DRM device | |
1039 | * @flags: startup flags | |
1040 | * | |
1041 | * The driver load routine has to do several things: | |
1042 | * - drive output discovery via intel_modeset_init() | |
1043 | * - initialize the memory manager | |
1044 | * - allocate initial config memory | |
1045 | * - setup the DRM framebuffer with the allocated memory | |
1046 | */ | |
84b1fd10 | 1047 | int i915_driver_load(struct drm_device *dev, unsigned long flags) |
22eae947 | 1048 | { |
ba8bbcf6 JB |
1049 | struct drm_i915_private *dev_priv = dev->dev_private; |
1050 | unsigned long base, size; | |
1051 | int ret = 0, mmio_bar = IS_I9XX(dev) ? 0 : 1; | |
1052 | ||
22eae947 DA |
1053 | /* i915 has 4 more counters */ |
1054 | dev->counters += 4; | |
1055 | dev->types[6] = _DRM_STAT_IRQ; | |
1056 | dev->types[7] = _DRM_STAT_PRIMARY; | |
1057 | dev->types[8] = _DRM_STAT_SECONDARY; | |
1058 | dev->types[9] = _DRM_STAT_DMA; | |
1059 | ||
ba8bbcf6 JB |
1060 | dev_priv = drm_alloc(sizeof(drm_i915_private_t), DRM_MEM_DRIVER); |
1061 | if (dev_priv == NULL) | |
1062 | return -ENOMEM; | |
1063 | ||
1064 | memset(dev_priv, 0, sizeof(drm_i915_private_t)); | |
1065 | ||
1066 | dev->dev_private = (void *)dev_priv; | |
673a394b | 1067 | dev_priv->dev = dev; |
ba8bbcf6 JB |
1068 | |
1069 | /* Add register map (needed for suspend/resume) */ | |
1070 | base = drm_get_resource_start(dev, mmio_bar); | |
1071 | size = drm_get_resource_len(dev, mmio_bar); | |
1072 | ||
3043c60c | 1073 | dev_priv->regs = ioremap(base, size); |
79e53945 JB |
1074 | if (!dev_priv->regs) { |
1075 | DRM_ERROR("failed to map registers\n"); | |
1076 | ret = -EIO; | |
1077 | goto free_priv; | |
1078 | } | |
ed4cb414 | 1079 | |
ab657db1 EA |
1080 | dev_priv->mm.gtt_mapping = |
1081 | io_mapping_create_wc(dev->agp->base, | |
1082 | dev->agp->agp_info.aper_size * 1024*1024); | |
1083 | /* Set up a WC MTRR for non-PAT systems. This is more common than | |
1084 | * one would think, because the kernel disables PAT on first | |
1085 | * generation Core chips because WC PAT gets overridden by a UC | |
1086 | * MTRR if present. Even if a UC MTRR isn't present. | |
1087 | */ | |
1088 | dev_priv->mm.gtt_mtrr = mtrr_add(dev->agp->base, | |
1089 | dev->agp->agp_info.aper_size * | |
1090 | 1024 * 1024, | |
1091 | MTRR_TYPE_WRCOMB, 1); | |
1092 | if (dev_priv->mm.gtt_mtrr < 0) { | |
1093 | DRM_INFO("MTRR allocation failed\n. Graphics " | |
1094 | "performance may suffer.\n"); | |
1095 | } | |
1096 | ||
ac5c4e76 DA |
1097 | #ifdef CONFIG_HIGHMEM64G |
1098 | /* don't enable GEM on PAE - needs agp + set_memory_* interface fixes */ | |
1099 | dev_priv->has_gem = 0; | |
1100 | #else | |
1101 | /* enable GEM by default */ | |
1102 | dev_priv->has_gem = 1; | |
1103 | #endif | |
1104 | ||
673a394b EA |
1105 | i915_gem_load(dev); |
1106 | ||
398c9cb2 KP |
1107 | /* Init HWS */ |
1108 | if (!I915_NEED_GFX_HWS(dev)) { | |
1109 | ret = i915_init_phys_hws(dev); | |
1110 | if (ret != 0) | |
79e53945 | 1111 | goto out_rmmap; |
398c9cb2 | 1112 | } |
ed4cb414 EA |
1113 | |
1114 | /* On the 945G/GM, the chipset reports the MSI capability on the | |
1115 | * integrated graphics even though the support isn't actually there | |
1116 | * according to the published specs. It doesn't appear to function | |
1117 | * correctly in testing on 945G. | |
1118 | * This may be a side effect of MSI having been made available for PEG | |
1119 | * and the registers being closely associated. | |
d1ed629f KP |
1120 | * |
1121 | * According to chipset errata, on the 965GM, MSI interrupts may | |
b60678a7 KP |
1122 | * be lost or delayed, but we use them anyways to avoid |
1123 | * stuck interrupts on some machines. | |
ed4cb414 | 1124 | */ |
b60678a7 | 1125 | if (!IS_I945G(dev) && !IS_I945GM(dev)) |
d3e74d02 | 1126 | pci_enable_msi(dev->pdev); |
ed4cb414 | 1127 | |
8ee1c3db MG |
1128 | intel_opregion_init(dev); |
1129 | ||
ed4cb414 | 1130 | spin_lock_init(&dev_priv->user_irq_lock); |
79e53945 | 1131 | dev_priv->user_irq_refcount = 0; |
ed4cb414 | 1132 | |
52440211 KP |
1133 | ret = drm_vblank_init(dev, I915_NUM_PIPE); |
1134 | ||
1135 | if (ret) { | |
1136 | (void) i915_driver_unload(dev); | |
1137 | return ret; | |
1138 | } | |
1139 | ||
79e53945 JB |
1140 | if (drm_core_check_feature(dev, DRIVER_MODESET)) { |
1141 | ret = i915_load_modeset_init(dev); | |
1142 | if (ret < 0) { | |
1143 | DRM_ERROR("failed to init modeset\n"); | |
1144 | goto out_rmmap; | |
1145 | } | |
1146 | } | |
1147 | ||
1148 | return 0; | |
1149 | ||
1150 | out_rmmap: | |
1151 | iounmap(dev_priv->regs); | |
1152 | free_priv: | |
1153 | drm_free(dev_priv, sizeof(struct drm_i915_private), DRM_MEM_DRIVER); | |
ba8bbcf6 JB |
1154 | return ret; |
1155 | } | |
1156 | ||
1157 | int i915_driver_unload(struct drm_device *dev) | |
1158 | { | |
1159 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1160 | ||
ab657db1 EA |
1161 | io_mapping_free(dev_priv->mm.gtt_mapping); |
1162 | if (dev_priv->mm.gtt_mtrr >= 0) { | |
1163 | mtrr_del(dev_priv->mm.gtt_mtrr, dev->agp->base, | |
1164 | dev->agp->agp_info.aper_size * 1024 * 1024); | |
1165 | dev_priv->mm.gtt_mtrr = -1; | |
1166 | } | |
1167 | ||
79e53945 | 1168 | if (drm_core_check_feature(dev, DRIVER_MODESET)) { |
79e53945 JB |
1169 | drm_irq_uninstall(dev); |
1170 | } | |
1171 | ||
ed4cb414 EA |
1172 | if (dev->pdev->msi_enabled) |
1173 | pci_disable_msi(dev->pdev); | |
1174 | ||
3043c60c EA |
1175 | if (dev_priv->regs != NULL) |
1176 | iounmap(dev_priv->regs); | |
ba8bbcf6 | 1177 | |
8ee1c3db MG |
1178 | intel_opregion_free(dev); |
1179 | ||
79e53945 JB |
1180 | if (drm_core_check_feature(dev, DRIVER_MODESET)) { |
1181 | intel_modeset_cleanup(dev); | |
1182 | ||
71acb5eb DA |
1183 | i915_gem_free_all_phys_object(dev); |
1184 | ||
79e53945 JB |
1185 | mutex_lock(&dev->struct_mutex); |
1186 | i915_gem_cleanup_ringbuffer(dev); | |
1187 | mutex_unlock(&dev->struct_mutex); | |
1188 | drm_mm_takedown(&dev_priv->vram); | |
1189 | i915_gem_lastclose(dev); | |
1190 | } | |
1191 | ||
ba8bbcf6 JB |
1192 | drm_free(dev->dev_private, sizeof(drm_i915_private_t), |
1193 | DRM_MEM_DRIVER); | |
1194 | ||
22eae947 DA |
1195 | return 0; |
1196 | } | |
1197 | ||
673a394b EA |
1198 | int i915_driver_open(struct drm_device *dev, struct drm_file *file_priv) |
1199 | { | |
1200 | struct drm_i915_file_private *i915_file_priv; | |
1201 | ||
1202 | DRM_DEBUG("\n"); | |
1203 | i915_file_priv = (struct drm_i915_file_private *) | |
1204 | drm_alloc(sizeof(*i915_file_priv), DRM_MEM_FILES); | |
1205 | ||
1206 | if (!i915_file_priv) | |
1207 | return -ENOMEM; | |
1208 | ||
1209 | file_priv->driver_priv = i915_file_priv; | |
1210 | ||
1211 | i915_file_priv->mm.last_gem_seqno = 0; | |
1212 | i915_file_priv->mm.last_gem_throttle_seqno = 0; | |
1213 | ||
1214 | return 0; | |
1215 | } | |
1216 | ||
79e53945 JB |
1217 | /** |
1218 | * i915_driver_lastclose - clean up after all DRM clients have exited | |
1219 | * @dev: DRM device | |
1220 | * | |
1221 | * Take care of cleaning up after all DRM clients have exited. In the | |
1222 | * mode setting case, we want to restore the kernel's initial mode (just | |
1223 | * in case the last client left us in a bad state). | |
1224 | * | |
1225 | * Additionally, in the non-mode setting case, we'll tear down the AGP | |
1226 | * and DMA structures, since the kernel won't be using them, and clea | |
1227 | * up any GEM state. | |
1228 | */ | |
84b1fd10 | 1229 | void i915_driver_lastclose(struct drm_device * dev) |
1da177e4 | 1230 | { |
ba8bbcf6 JB |
1231 | drm_i915_private_t *dev_priv = dev->dev_private; |
1232 | ||
79e53945 JB |
1233 | if (!dev_priv || drm_core_check_feature(dev, DRIVER_MODESET)) { |
1234 | intelfb_restore(); | |
144a75fa | 1235 | return; |
79e53945 | 1236 | } |
144a75fa | 1237 | |
673a394b EA |
1238 | i915_gem_lastclose(dev); |
1239 | ||
ba8bbcf6 | 1240 | if (dev_priv->agp_heap) |
b5e89ed5 | 1241 | i915_mem_takedown(&(dev_priv->agp_heap)); |
ba8bbcf6 | 1242 | |
b5e89ed5 | 1243 | i915_dma_cleanup(dev); |
1da177e4 LT |
1244 | } |
1245 | ||
6c340eac | 1246 | void i915_driver_preclose(struct drm_device * dev, struct drm_file *file_priv) |
1da177e4 | 1247 | { |
ba8bbcf6 | 1248 | drm_i915_private_t *dev_priv = dev->dev_private; |
79e53945 JB |
1249 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) |
1250 | i915_mem_release(dev, file_priv, dev_priv->agp_heap); | |
1da177e4 LT |
1251 | } |
1252 | ||
673a394b EA |
1253 | void i915_driver_postclose(struct drm_device *dev, struct drm_file *file_priv) |
1254 | { | |
1255 | struct drm_i915_file_private *i915_file_priv = file_priv->driver_priv; | |
1256 | ||
1257 | drm_free(i915_file_priv, sizeof(*i915_file_priv), DRM_MEM_FILES); | |
1258 | } | |
1259 | ||
c153f45f EA |
1260 | struct drm_ioctl_desc i915_ioctls[] = { |
1261 | DRM_IOCTL_DEF(DRM_I915_INIT, i915_dma_init, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), | |
1262 | DRM_IOCTL_DEF(DRM_I915_FLUSH, i915_flush_ioctl, DRM_AUTH), | |
1263 | DRM_IOCTL_DEF(DRM_I915_FLIP, i915_flip_bufs, DRM_AUTH), | |
1264 | DRM_IOCTL_DEF(DRM_I915_BATCHBUFFER, i915_batchbuffer, DRM_AUTH), | |
1265 | DRM_IOCTL_DEF(DRM_I915_IRQ_EMIT, i915_irq_emit, DRM_AUTH), | |
1266 | DRM_IOCTL_DEF(DRM_I915_IRQ_WAIT, i915_irq_wait, DRM_AUTH), | |
1267 | DRM_IOCTL_DEF(DRM_I915_GETPARAM, i915_getparam, DRM_AUTH), | |
1268 | DRM_IOCTL_DEF(DRM_I915_SETPARAM, i915_setparam, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), | |
1269 | DRM_IOCTL_DEF(DRM_I915_ALLOC, i915_mem_alloc, DRM_AUTH), | |
1270 | DRM_IOCTL_DEF(DRM_I915_FREE, i915_mem_free, DRM_AUTH), | |
1271 | DRM_IOCTL_DEF(DRM_I915_INIT_HEAP, i915_mem_init_heap, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), | |
1272 | DRM_IOCTL_DEF(DRM_I915_CMDBUFFER, i915_cmdbuffer, DRM_AUTH), | |
1273 | DRM_IOCTL_DEF(DRM_I915_DESTROY_HEAP, i915_mem_destroy_heap, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY ), | |
1274 | DRM_IOCTL_DEF(DRM_I915_SET_VBLANK_PIPE, i915_vblank_pipe_set, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY ), | |
1275 | DRM_IOCTL_DEF(DRM_I915_GET_VBLANK_PIPE, i915_vblank_pipe_get, DRM_AUTH ), | |
1276 | DRM_IOCTL_DEF(DRM_I915_VBLANK_SWAP, i915_vblank_swap, DRM_AUTH), | |
4b408939 | 1277 | DRM_IOCTL_DEF(DRM_I915_HWS_ADDR, i915_set_status_page, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), |
2bdf00b2 | 1278 | DRM_IOCTL_DEF(DRM_I915_GEM_INIT, i915_gem_init_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), |
673a394b EA |
1279 | DRM_IOCTL_DEF(DRM_I915_GEM_EXECBUFFER, i915_gem_execbuffer, DRM_AUTH), |
1280 | DRM_IOCTL_DEF(DRM_I915_GEM_PIN, i915_gem_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY), | |
1281 | DRM_IOCTL_DEF(DRM_I915_GEM_UNPIN, i915_gem_unpin_ioctl, DRM_AUTH|DRM_ROOT_ONLY), | |
1282 | DRM_IOCTL_DEF(DRM_I915_GEM_BUSY, i915_gem_busy_ioctl, DRM_AUTH), | |
1283 | DRM_IOCTL_DEF(DRM_I915_GEM_THROTTLE, i915_gem_throttle_ioctl, DRM_AUTH), | |
2bdf00b2 DA |
1284 | DRM_IOCTL_DEF(DRM_I915_GEM_ENTERVT, i915_gem_entervt_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), |
1285 | DRM_IOCTL_DEF(DRM_I915_GEM_LEAVEVT, i915_gem_leavevt_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), | |
673a394b EA |
1286 | DRM_IOCTL_DEF(DRM_I915_GEM_CREATE, i915_gem_create_ioctl, 0), |
1287 | DRM_IOCTL_DEF(DRM_I915_GEM_PREAD, i915_gem_pread_ioctl, 0), | |
1288 | DRM_IOCTL_DEF(DRM_I915_GEM_PWRITE, i915_gem_pwrite_ioctl, 0), | |
1289 | DRM_IOCTL_DEF(DRM_I915_GEM_MMAP, i915_gem_mmap_ioctl, 0), | |
de151cf6 | 1290 | DRM_IOCTL_DEF(DRM_I915_GEM_MMAP_GTT, i915_gem_mmap_gtt_ioctl, 0), |
673a394b EA |
1291 | DRM_IOCTL_DEF(DRM_I915_GEM_SET_DOMAIN, i915_gem_set_domain_ioctl, 0), |
1292 | DRM_IOCTL_DEF(DRM_I915_GEM_SW_FINISH, i915_gem_sw_finish_ioctl, 0), | |
1293 | DRM_IOCTL_DEF(DRM_I915_GEM_SET_TILING, i915_gem_set_tiling, 0), | |
1294 | DRM_IOCTL_DEF(DRM_I915_GEM_GET_TILING, i915_gem_get_tiling, 0), | |
5a125c3c | 1295 | DRM_IOCTL_DEF(DRM_I915_GEM_GET_APERTURE, i915_gem_get_aperture_ioctl, 0), |
c94f7029 DA |
1296 | }; |
1297 | ||
1298 | int i915_max_ioctl = DRM_ARRAY_SIZE(i915_ioctls); | |
cda17380 DA |
1299 | |
1300 | /** | |
1301 | * Determine if the device really is AGP or not. | |
1302 | * | |
1303 | * All Intel graphics chipsets are treated as AGP, even if they are really | |
1304 | * PCI-e. | |
1305 | * | |
1306 | * \param dev The device to be tested. | |
1307 | * | |
1308 | * \returns | |
1309 | * A value of 1 is always retured to indictate every i9x5 is AGP. | |
1310 | */ | |
84b1fd10 | 1311 | int i915_driver_device_is_agp(struct drm_device * dev) |
cda17380 DA |
1312 | { |
1313 | return 1; | |
1314 | } |