Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* i915_dma.c -- DMA support for the I915 -*- linux-c -*- |
2 | */ | |
0d6aa60b | 3 | /* |
1da177e4 LT |
4 | * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. |
5 | * All Rights Reserved. | |
bc54fd1a DA |
6 | * |
7 | * Permission is hereby granted, free of charge, to any person obtaining a | |
8 | * copy of this software and associated documentation files (the | |
9 | * "Software"), to deal in the Software without restriction, including | |
10 | * without limitation the rights to use, copy, modify, merge, publish, | |
11 | * distribute, sub license, and/or sell copies of the Software, and to | |
12 | * permit persons to whom the Software is furnished to do so, subject to | |
13 | * the following conditions: | |
14 | * | |
15 | * The above copyright notice and this permission notice (including the | |
16 | * next paragraph) shall be included in all copies or substantial portions | |
17 | * of the Software. | |
18 | * | |
19 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS | |
20 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
21 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. | |
22 | * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR | |
23 | * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, | |
24 | * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE | |
25 | * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. | |
26 | * | |
0d6aa60b | 27 | */ |
1da177e4 | 28 | |
a70491cc JP |
29 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
30 | ||
760285e7 DH |
31 | #include <drm/drmP.h> |
32 | #include <drm/drm_crtc_helper.h> | |
33 | #include <drm/drm_fb_helper.h> | |
79e53945 | 34 | #include "intel_drv.h" |
760285e7 | 35 | #include <drm/i915_drm.h> |
1da177e4 | 36 | #include "i915_drv.h" |
1c5d22f7 | 37 | #include "i915_trace.h" |
dcdb1674 | 38 | #include <linux/pci.h> |
28d52043 | 39 | #include <linux/vgaarb.h> |
c4804411 ZW |
40 | #include <linux/acpi.h> |
41 | #include <linux/pnp.h> | |
6a9ee8af | 42 | #include <linux/vga_switcheroo.h> |
5a0e3ad6 | 43 | #include <linux/slab.h> |
44834a67 | 44 | #include <acpi/video.h> |
9e984bc1 | 45 | #include <asm/pat.h> |
1da177e4 | 46 | |
09422b2e DV |
47 | #define LP_RING(d) (&((struct drm_i915_private *)(d))->ring[RCS]) |
48 | ||
49 | #define BEGIN_LP_RING(n) \ | |
50 | intel_ring_begin(LP_RING(dev_priv), (n)) | |
51 | ||
52 | #define OUT_RING(x) \ | |
53 | intel_ring_emit(LP_RING(dev_priv), x) | |
54 | ||
55 | #define ADVANCE_LP_RING() \ | |
56 | intel_ring_advance(LP_RING(dev_priv)) | |
57 | ||
58 | /** | |
59 | * Lock test for when it's just for synchronization of ring access. | |
60 | * | |
61 | * In that case, we don't need to do it when GEM is initialized as nobody else | |
62 | * has access to the ring. | |
63 | */ | |
64 | #define RING_LOCK_TEST_WITH_RETURN(dev, file) do { \ | |
65 | if (LP_RING(dev->dev_private)->obj == NULL) \ | |
66 | LOCK_TEST_WITH_RETURN(dev, file); \ | |
67 | } while (0) | |
68 | ||
316d3884 DV |
69 | static inline u32 |
70 | intel_read_legacy_status_page(struct drm_i915_private *dev_priv, int reg) | |
71 | { | |
72 | if (I915_NEED_GFX_HWS(dev_priv->dev)) | |
73 | return ioread32(dev_priv->dri1.gfx_hws_cpu_addr + reg); | |
74 | else | |
75 | return intel_read_status_page(LP_RING(dev_priv), reg); | |
76 | } | |
77 | ||
78 | #define READ_HWSP(dev_priv, reg) intel_read_legacy_status_page(dev_priv, reg) | |
09422b2e DV |
79 | #define READ_BREADCRUMB(dev_priv) READ_HWSP(dev_priv, I915_BREADCRUMB_INDEX) |
80 | #define I915_BREADCRUMB_INDEX 0x21 | |
81 | ||
d05c617e DV |
82 | void i915_update_dri1_breadcrumb(struct drm_device *dev) |
83 | { | |
84 | drm_i915_private_t *dev_priv = dev->dev_private; | |
85 | struct drm_i915_master_private *master_priv; | |
86 | ||
87 | if (dev->primary->master) { | |
88 | master_priv = dev->primary->master->driver_priv; | |
89 | if (master_priv->sarea_priv) | |
90 | master_priv->sarea_priv->last_dispatch = | |
91 | READ_BREADCRUMB(dev_priv); | |
92 | } | |
93 | } | |
94 | ||
4cbf74cc CW |
95 | static void i915_write_hws_pga(struct drm_device *dev) |
96 | { | |
97 | drm_i915_private_t *dev_priv = dev->dev_private; | |
98 | u32 addr; | |
99 | ||
100 | addr = dev_priv->status_page_dmah->busaddr; | |
101 | if (INTEL_INFO(dev)->gen >= 4) | |
102 | addr |= (dev_priv->status_page_dmah->busaddr >> 28) & 0xf0; | |
103 | I915_WRITE(HWS_PGA, addr); | |
104 | } | |
105 | ||
398c9cb2 KP |
106 | /** |
107 | * Frees the hardware status page, whether it's a physical address or a virtual | |
108 | * address set up by the X Server. | |
109 | */ | |
3043c60c | 110 | static void i915_free_hws(struct drm_device *dev) |
398c9cb2 KP |
111 | { |
112 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1ec14ad3 CW |
113 | struct intel_ring_buffer *ring = LP_RING(dev_priv); |
114 | ||
398c9cb2 KP |
115 | if (dev_priv->status_page_dmah) { |
116 | drm_pci_free(dev, dev_priv->status_page_dmah); | |
117 | dev_priv->status_page_dmah = NULL; | |
118 | } | |
119 | ||
1ec14ad3 CW |
120 | if (ring->status_page.gfx_addr) { |
121 | ring->status_page.gfx_addr = 0; | |
316d3884 | 122 | iounmap(dev_priv->dri1.gfx_hws_cpu_addr); |
398c9cb2 KP |
123 | } |
124 | ||
125 | /* Need to rewrite hardware status page */ | |
126 | I915_WRITE(HWS_PGA, 0x1ffff000); | |
127 | } | |
128 | ||
84b1fd10 | 129 | void i915_kernel_lost_context(struct drm_device * dev) |
1da177e4 LT |
130 | { |
131 | drm_i915_private_t *dev_priv = dev->dev_private; | |
7c1c2871 | 132 | struct drm_i915_master_private *master_priv; |
1ec14ad3 | 133 | struct intel_ring_buffer *ring = LP_RING(dev_priv); |
1da177e4 | 134 | |
79e53945 JB |
135 | /* |
136 | * We should never lose context on the ring with modesetting | |
137 | * as we don't expose it to userspace | |
138 | */ | |
139 | if (drm_core_check_feature(dev, DRIVER_MODESET)) | |
140 | return; | |
141 | ||
8168bd48 CW |
142 | ring->head = I915_READ_HEAD(ring) & HEAD_ADDR; |
143 | ring->tail = I915_READ_TAIL(ring) & TAIL_ADDR; | |
633cf8f5 | 144 | ring->space = ring->head - (ring->tail + I915_RING_FREE_SPACE); |
1da177e4 | 145 | if (ring->space < 0) |
8187a2b7 | 146 | ring->space += ring->size; |
1da177e4 | 147 | |
7c1c2871 DA |
148 | if (!dev->primary->master) |
149 | return; | |
150 | ||
151 | master_priv = dev->primary->master->driver_priv; | |
152 | if (ring->head == ring->tail && master_priv->sarea_priv) | |
153 | master_priv->sarea_priv->perf_boxes |= I915_BOX_RING_EMPTY; | |
1da177e4 LT |
154 | } |
155 | ||
84b1fd10 | 156 | static int i915_dma_cleanup(struct drm_device * dev) |
1da177e4 | 157 | { |
ba8bbcf6 | 158 | drm_i915_private_t *dev_priv = dev->dev_private; |
1ec14ad3 CW |
159 | int i; |
160 | ||
1da177e4 LT |
161 | /* Make sure interrupts are disabled here because the uninstall ioctl |
162 | * may not have been called from userspace and after dev_private | |
163 | * is freed, it's too late. | |
164 | */ | |
ed4cb414 | 165 | if (dev->irq_enabled) |
b5e89ed5 | 166 | drm_irq_uninstall(dev); |
1da177e4 | 167 | |
ee0c6bfb | 168 | mutex_lock(&dev->struct_mutex); |
1ec14ad3 CW |
169 | for (i = 0; i < I915_NUM_RINGS; i++) |
170 | intel_cleanup_ring_buffer(&dev_priv->ring[i]); | |
ee0c6bfb | 171 | mutex_unlock(&dev->struct_mutex); |
dc7a9319 | 172 | |
398c9cb2 KP |
173 | /* Clear the HWS virtual address at teardown */ |
174 | if (I915_NEED_GFX_HWS(dev)) | |
175 | i915_free_hws(dev); | |
1da177e4 LT |
176 | |
177 | return 0; | |
178 | } | |
179 | ||
ba8bbcf6 | 180 | static int i915_initialize(struct drm_device * dev, drm_i915_init_t * init) |
1da177e4 | 181 | { |
ba8bbcf6 | 182 | drm_i915_private_t *dev_priv = dev->dev_private; |
7c1c2871 | 183 | struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv; |
e8616b6c | 184 | int ret; |
1da177e4 | 185 | |
3a03ac1a DA |
186 | master_priv->sarea = drm_getsarea(dev); |
187 | if (master_priv->sarea) { | |
188 | master_priv->sarea_priv = (drm_i915_sarea_t *) | |
189 | ((u8 *)master_priv->sarea->handle + init->sarea_priv_offset); | |
190 | } else { | |
8a4c47f3 | 191 | DRM_DEBUG_DRIVER("sarea not found assuming DRI2 userspace\n"); |
3a03ac1a DA |
192 | } |
193 | ||
673a394b | 194 | if (init->ring_size != 0) { |
e8616b6c | 195 | if (LP_RING(dev_priv)->obj != NULL) { |
673a394b EA |
196 | i915_dma_cleanup(dev); |
197 | DRM_ERROR("Client tried to initialize ringbuffer in " | |
198 | "GEM mode\n"); | |
199 | return -EINVAL; | |
200 | } | |
1da177e4 | 201 | |
e8616b6c CW |
202 | ret = intel_render_ring_init_dri(dev, |
203 | init->ring_start, | |
204 | init->ring_size); | |
205 | if (ret) { | |
673a394b | 206 | i915_dma_cleanup(dev); |
e8616b6c | 207 | return ret; |
673a394b | 208 | } |
1da177e4 LT |
209 | } |
210 | ||
5d985ac8 DV |
211 | dev_priv->dri1.cpp = init->cpp; |
212 | dev_priv->dri1.back_offset = init->back_offset; | |
213 | dev_priv->dri1.front_offset = init->front_offset; | |
214 | dev_priv->dri1.current_page = 0; | |
7c1c2871 DA |
215 | if (master_priv->sarea_priv) |
216 | master_priv->sarea_priv->pf_current_page = 0; | |
1da177e4 | 217 | |
1da177e4 LT |
218 | /* Allow hardware batchbuffers unless told otherwise. |
219 | */ | |
8781342d | 220 | dev_priv->dri1.allow_batchbuffer = 1; |
1da177e4 | 221 | |
1da177e4 LT |
222 | return 0; |
223 | } | |
224 | ||
84b1fd10 | 225 | static int i915_dma_resume(struct drm_device * dev) |
1da177e4 LT |
226 | { |
227 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
1ec14ad3 | 228 | struct intel_ring_buffer *ring = LP_RING(dev_priv); |
1da177e4 | 229 | |
8a4c47f3 | 230 | DRM_DEBUG_DRIVER("%s\n", __func__); |
1da177e4 | 231 | |
4225d0f2 | 232 | if (ring->virtual_start == NULL) { |
1da177e4 LT |
233 | DRM_ERROR("can not ioremap virtual address for" |
234 | " ring buffer\n"); | |
20caafa6 | 235 | return -ENOMEM; |
1da177e4 LT |
236 | } |
237 | ||
238 | /* Program Hardware Status Page */ | |
8187a2b7 | 239 | if (!ring->status_page.page_addr) { |
1da177e4 | 240 | DRM_ERROR("Can not find hardware status page\n"); |
20caafa6 | 241 | return -EINVAL; |
1da177e4 | 242 | } |
8a4c47f3 | 243 | DRM_DEBUG_DRIVER("hw status page @ %p\n", |
8187a2b7 ZN |
244 | ring->status_page.page_addr); |
245 | if (ring->status_page.gfx_addr != 0) | |
78501eac | 246 | intel_ring_setup_status_page(ring); |
dc7a9319 | 247 | else |
4cbf74cc | 248 | i915_write_hws_pga(dev); |
8187a2b7 | 249 | |
8a4c47f3 | 250 | DRM_DEBUG_DRIVER("Enabled hardware status page\n"); |
1da177e4 LT |
251 | |
252 | return 0; | |
253 | } | |
254 | ||
c153f45f EA |
255 | static int i915_dma_init(struct drm_device *dev, void *data, |
256 | struct drm_file *file_priv) | |
1da177e4 | 257 | { |
c153f45f | 258 | drm_i915_init_t *init = data; |
1da177e4 LT |
259 | int retcode = 0; |
260 | ||
cd9d4e9f DV |
261 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
262 | return -ENODEV; | |
263 | ||
c153f45f | 264 | switch (init->func) { |
1da177e4 | 265 | case I915_INIT_DMA: |
ba8bbcf6 | 266 | retcode = i915_initialize(dev, init); |
1da177e4 LT |
267 | break; |
268 | case I915_CLEANUP_DMA: | |
269 | retcode = i915_dma_cleanup(dev); | |
270 | break; | |
271 | case I915_RESUME_DMA: | |
0d6aa60b | 272 | retcode = i915_dma_resume(dev); |
1da177e4 LT |
273 | break; |
274 | default: | |
20caafa6 | 275 | retcode = -EINVAL; |
1da177e4 LT |
276 | break; |
277 | } | |
278 | ||
279 | return retcode; | |
280 | } | |
281 | ||
282 | /* Implement basically the same security restrictions as hardware does | |
283 | * for MI_BATCH_NON_SECURE. These can be made stricter at any time. | |
284 | * | |
285 | * Most of the calculations below involve calculating the size of a | |
286 | * particular instruction. It's important to get the size right as | |
287 | * that tells us where the next instruction to check is. Any illegal | |
288 | * instruction detected will be given a size of zero, which is a | |
289 | * signal to abort the rest of the buffer. | |
290 | */ | |
e1f99ce6 | 291 | static int validate_cmd(int cmd) |
1da177e4 LT |
292 | { |
293 | switch (((cmd >> 29) & 0x7)) { | |
294 | case 0x0: | |
295 | switch ((cmd >> 23) & 0x3f) { | |
296 | case 0x0: | |
297 | return 1; /* MI_NOOP */ | |
298 | case 0x4: | |
299 | return 1; /* MI_FLUSH */ | |
300 | default: | |
301 | return 0; /* disallow everything else */ | |
302 | } | |
303 | break; | |
304 | case 0x1: | |
305 | return 0; /* reserved */ | |
306 | case 0x2: | |
307 | return (cmd & 0xff) + 2; /* 2d commands */ | |
308 | case 0x3: | |
309 | if (((cmd >> 24) & 0x1f) <= 0x18) | |
310 | return 1; | |
311 | ||
312 | switch ((cmd >> 24) & 0x1f) { | |
313 | case 0x1c: | |
314 | return 1; | |
315 | case 0x1d: | |
b5e89ed5 | 316 | switch ((cmd >> 16) & 0xff) { |
1da177e4 LT |
317 | case 0x3: |
318 | return (cmd & 0x1f) + 2; | |
319 | case 0x4: | |
320 | return (cmd & 0xf) + 2; | |
321 | default: | |
322 | return (cmd & 0xffff) + 2; | |
323 | } | |
324 | case 0x1e: | |
325 | if (cmd & (1 << 23)) | |
326 | return (cmd & 0xffff) + 1; | |
327 | else | |
328 | return 1; | |
329 | case 0x1f: | |
330 | if ((cmd & (1 << 23)) == 0) /* inline vertices */ | |
331 | return (cmd & 0x1ffff) + 2; | |
332 | else if (cmd & (1 << 17)) /* indirect random */ | |
333 | if ((cmd & 0xffff) == 0) | |
334 | return 0; /* unknown length, too hard */ | |
335 | else | |
336 | return (((cmd & 0xffff) + 1) / 2) + 1; | |
337 | else | |
338 | return 2; /* indirect sequential */ | |
339 | default: | |
340 | return 0; | |
341 | } | |
342 | default: | |
343 | return 0; | |
344 | } | |
345 | ||
346 | return 0; | |
347 | } | |
348 | ||
201361a5 | 349 | static int i915_emit_cmds(struct drm_device * dev, int *buffer, int dwords) |
1da177e4 LT |
350 | { |
351 | drm_i915_private_t *dev_priv = dev->dev_private; | |
e1f99ce6 | 352 | int i, ret; |
1da177e4 | 353 | |
1ec14ad3 | 354 | if ((dwords+1) * sizeof(int) >= LP_RING(dev_priv)->size - 8) |
20caafa6 | 355 | return -EINVAL; |
de227f5f | 356 | |
1da177e4 | 357 | for (i = 0; i < dwords;) { |
e1f99ce6 CW |
358 | int sz = validate_cmd(buffer[i]); |
359 | if (sz == 0 || i + sz > dwords) | |
20caafa6 | 360 | return -EINVAL; |
e1f99ce6 | 361 | i += sz; |
1da177e4 LT |
362 | } |
363 | ||
e1f99ce6 CW |
364 | ret = BEGIN_LP_RING((dwords+1)&~1); |
365 | if (ret) | |
366 | return ret; | |
367 | ||
368 | for (i = 0; i < dwords; i++) | |
369 | OUT_RING(buffer[i]); | |
de227f5f DA |
370 | if (dwords & 1) |
371 | OUT_RING(0); | |
372 | ||
373 | ADVANCE_LP_RING(); | |
374 | ||
1da177e4 LT |
375 | return 0; |
376 | } | |
377 | ||
673a394b EA |
378 | int |
379 | i915_emit_box(struct drm_device *dev, | |
c4e7a414 CW |
380 | struct drm_clip_rect *box, |
381 | int DR1, int DR4) | |
1da177e4 | 382 | { |
e1f99ce6 | 383 | struct drm_i915_private *dev_priv = dev->dev_private; |
e1f99ce6 | 384 | int ret; |
1da177e4 | 385 | |
c4e7a414 CW |
386 | if (box->y2 <= box->y1 || box->x2 <= box->x1 || |
387 | box->y2 <= 0 || box->x2 <= 0) { | |
1da177e4 | 388 | DRM_ERROR("Bad box %d,%d..%d,%d\n", |
c4e7a414 | 389 | box->x1, box->y1, box->x2, box->y2); |
20caafa6 | 390 | return -EINVAL; |
1da177e4 LT |
391 | } |
392 | ||
a6c45cf0 | 393 | if (INTEL_INFO(dev)->gen >= 4) { |
e1f99ce6 CW |
394 | ret = BEGIN_LP_RING(4); |
395 | if (ret) | |
396 | return ret; | |
397 | ||
c29b669c | 398 | OUT_RING(GFX_OP_DRAWRECT_INFO_I965); |
c4e7a414 CW |
399 | OUT_RING((box->x1 & 0xffff) | (box->y1 << 16)); |
400 | OUT_RING(((box->x2 - 1) & 0xffff) | ((box->y2 - 1) << 16)); | |
c29b669c | 401 | OUT_RING(DR4); |
c29b669c | 402 | } else { |
e1f99ce6 CW |
403 | ret = BEGIN_LP_RING(6); |
404 | if (ret) | |
405 | return ret; | |
406 | ||
c29b669c AH |
407 | OUT_RING(GFX_OP_DRAWRECT_INFO); |
408 | OUT_RING(DR1); | |
c4e7a414 CW |
409 | OUT_RING((box->x1 & 0xffff) | (box->y1 << 16)); |
410 | OUT_RING(((box->x2 - 1) & 0xffff) | ((box->y2 - 1) << 16)); | |
c29b669c AH |
411 | OUT_RING(DR4); |
412 | OUT_RING(0); | |
c29b669c | 413 | } |
e1f99ce6 | 414 | ADVANCE_LP_RING(); |
1da177e4 LT |
415 | |
416 | return 0; | |
417 | } | |
418 | ||
c29b669c AH |
419 | /* XXX: Emitting the counter should really be moved to part of the IRQ |
420 | * emit. For now, do it in both places: | |
421 | */ | |
422 | ||
84b1fd10 | 423 | static void i915_emit_breadcrumb(struct drm_device *dev) |
de227f5f DA |
424 | { |
425 | drm_i915_private_t *dev_priv = dev->dev_private; | |
7c1c2871 | 426 | struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv; |
de227f5f | 427 | |
231f42a4 DV |
428 | dev_priv->dri1.counter++; |
429 | if (dev_priv->dri1.counter > 0x7FFFFFFFUL) | |
430 | dev_priv->dri1.counter = 0; | |
7c1c2871 | 431 | if (master_priv->sarea_priv) |
231f42a4 | 432 | master_priv->sarea_priv->last_enqueue = dev_priv->dri1.counter; |
de227f5f | 433 | |
e1f99ce6 CW |
434 | if (BEGIN_LP_RING(4) == 0) { |
435 | OUT_RING(MI_STORE_DWORD_INDEX); | |
436 | OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT); | |
231f42a4 | 437 | OUT_RING(dev_priv->dri1.counter); |
e1f99ce6 CW |
438 | OUT_RING(0); |
439 | ADVANCE_LP_RING(); | |
440 | } | |
de227f5f DA |
441 | } |
442 | ||
84b1fd10 | 443 | static int i915_dispatch_cmdbuffer(struct drm_device * dev, |
201361a5 EA |
444 | drm_i915_cmdbuffer_t *cmd, |
445 | struct drm_clip_rect *cliprects, | |
446 | void *cmdbuf) | |
1da177e4 LT |
447 | { |
448 | int nbox = cmd->num_cliprects; | |
449 | int i = 0, count, ret; | |
450 | ||
451 | if (cmd->sz & 0x3) { | |
452 | DRM_ERROR("alignment"); | |
20caafa6 | 453 | return -EINVAL; |
1da177e4 LT |
454 | } |
455 | ||
456 | i915_kernel_lost_context(dev); | |
457 | ||
458 | count = nbox ? nbox : 1; | |
459 | ||
460 | for (i = 0; i < count; i++) { | |
461 | if (i < nbox) { | |
c4e7a414 | 462 | ret = i915_emit_box(dev, &cliprects[i], |
1da177e4 LT |
463 | cmd->DR1, cmd->DR4); |
464 | if (ret) | |
465 | return ret; | |
466 | } | |
467 | ||
201361a5 | 468 | ret = i915_emit_cmds(dev, cmdbuf, cmd->sz / 4); |
1da177e4 LT |
469 | if (ret) |
470 | return ret; | |
471 | } | |
472 | ||
de227f5f | 473 | i915_emit_breadcrumb(dev); |
1da177e4 LT |
474 | return 0; |
475 | } | |
476 | ||
84b1fd10 | 477 | static int i915_dispatch_batchbuffer(struct drm_device * dev, |
201361a5 EA |
478 | drm_i915_batchbuffer_t * batch, |
479 | struct drm_clip_rect *cliprects) | |
1da177e4 | 480 | { |
e1f99ce6 | 481 | struct drm_i915_private *dev_priv = dev->dev_private; |
1da177e4 | 482 | int nbox = batch->num_cliprects; |
e1f99ce6 | 483 | int i, count, ret; |
1da177e4 LT |
484 | |
485 | if ((batch->start | batch->used) & 0x7) { | |
486 | DRM_ERROR("alignment"); | |
20caafa6 | 487 | return -EINVAL; |
1da177e4 LT |
488 | } |
489 | ||
490 | i915_kernel_lost_context(dev); | |
491 | ||
492 | count = nbox ? nbox : 1; | |
1da177e4 LT |
493 | for (i = 0; i < count; i++) { |
494 | if (i < nbox) { | |
c4e7a414 | 495 | ret = i915_emit_box(dev, &cliprects[i], |
e1f99ce6 | 496 | batch->DR1, batch->DR4); |
1da177e4 LT |
497 | if (ret) |
498 | return ret; | |
499 | } | |
500 | ||
0790d5e1 | 501 | if (!IS_I830(dev) && !IS_845G(dev)) { |
e1f99ce6 CW |
502 | ret = BEGIN_LP_RING(2); |
503 | if (ret) | |
504 | return ret; | |
505 | ||
a6c45cf0 | 506 | if (INTEL_INFO(dev)->gen >= 4) { |
21f16289 DA |
507 | OUT_RING(MI_BATCH_BUFFER_START | (2 << 6) | MI_BATCH_NON_SECURE_I965); |
508 | OUT_RING(batch->start); | |
509 | } else { | |
510 | OUT_RING(MI_BATCH_BUFFER_START | (2 << 6)); | |
511 | OUT_RING(batch->start | MI_BATCH_NON_SECURE); | |
512 | } | |
1da177e4 | 513 | } else { |
e1f99ce6 CW |
514 | ret = BEGIN_LP_RING(4); |
515 | if (ret) | |
516 | return ret; | |
517 | ||
1da177e4 LT |
518 | OUT_RING(MI_BATCH_BUFFER); |
519 | OUT_RING(batch->start | MI_BATCH_NON_SECURE); | |
520 | OUT_RING(batch->start + batch->used - 4); | |
521 | OUT_RING(0); | |
1da177e4 | 522 | } |
e1f99ce6 | 523 | ADVANCE_LP_RING(); |
1da177e4 LT |
524 | } |
525 | ||
1cafd347 | 526 | |
f00a3ddf | 527 | if (IS_G4X(dev) || IS_GEN5(dev)) { |
e1f99ce6 CW |
528 | if (BEGIN_LP_RING(2) == 0) { |
529 | OUT_RING(MI_FLUSH | MI_NO_WRITE_FLUSH | MI_INVALIDATE_ISP); | |
530 | OUT_RING(MI_NOOP); | |
531 | ADVANCE_LP_RING(); | |
532 | } | |
1cafd347 | 533 | } |
1da177e4 | 534 | |
e1f99ce6 | 535 | i915_emit_breadcrumb(dev); |
1da177e4 LT |
536 | return 0; |
537 | } | |
538 | ||
af6061af | 539 | static int i915_dispatch_flip(struct drm_device * dev) |
1da177e4 LT |
540 | { |
541 | drm_i915_private_t *dev_priv = dev->dev_private; | |
7c1c2871 DA |
542 | struct drm_i915_master_private *master_priv = |
543 | dev->primary->master->driver_priv; | |
e1f99ce6 | 544 | int ret; |
1da177e4 | 545 | |
7c1c2871 | 546 | if (!master_priv->sarea_priv) |
c99b058f KH |
547 | return -EINVAL; |
548 | ||
8a4c47f3 | 549 | DRM_DEBUG_DRIVER("%s: page=%d pfCurrentPage=%d\n", |
be25ed9c | 550 | __func__, |
5d985ac8 | 551 | dev_priv->dri1.current_page, |
be25ed9c | 552 | master_priv->sarea_priv->pf_current_page); |
1da177e4 | 553 | |
af6061af DA |
554 | i915_kernel_lost_context(dev); |
555 | ||
e1f99ce6 CW |
556 | ret = BEGIN_LP_RING(10); |
557 | if (ret) | |
558 | return ret; | |
559 | ||
585fb111 | 560 | OUT_RING(MI_FLUSH | MI_READ_FLUSH); |
af6061af | 561 | OUT_RING(0); |
1da177e4 | 562 | |
af6061af DA |
563 | OUT_RING(CMD_OP_DISPLAYBUFFER_INFO | ASYNC_FLIP); |
564 | OUT_RING(0); | |
5d985ac8 DV |
565 | if (dev_priv->dri1.current_page == 0) { |
566 | OUT_RING(dev_priv->dri1.back_offset); | |
567 | dev_priv->dri1.current_page = 1; | |
1da177e4 | 568 | } else { |
5d985ac8 DV |
569 | OUT_RING(dev_priv->dri1.front_offset); |
570 | dev_priv->dri1.current_page = 0; | |
1da177e4 | 571 | } |
af6061af | 572 | OUT_RING(0); |
1da177e4 | 573 | |
af6061af DA |
574 | OUT_RING(MI_WAIT_FOR_EVENT | MI_WAIT_FOR_PLANE_A_FLIP); |
575 | OUT_RING(0); | |
e1f99ce6 | 576 | |
af6061af | 577 | ADVANCE_LP_RING(); |
1da177e4 | 578 | |
231f42a4 | 579 | master_priv->sarea_priv->last_enqueue = dev_priv->dri1.counter++; |
1da177e4 | 580 | |
e1f99ce6 CW |
581 | if (BEGIN_LP_RING(4) == 0) { |
582 | OUT_RING(MI_STORE_DWORD_INDEX); | |
583 | OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT); | |
231f42a4 | 584 | OUT_RING(dev_priv->dri1.counter); |
e1f99ce6 CW |
585 | OUT_RING(0); |
586 | ADVANCE_LP_RING(); | |
587 | } | |
1da177e4 | 588 | |
5d985ac8 | 589 | master_priv->sarea_priv->pf_current_page = dev_priv->dri1.current_page; |
af6061af | 590 | return 0; |
1da177e4 LT |
591 | } |
592 | ||
1ec14ad3 | 593 | static int i915_quiescent(struct drm_device *dev) |
1da177e4 | 594 | { |
1da177e4 | 595 | i915_kernel_lost_context(dev); |
3e960501 | 596 | return intel_ring_idle(LP_RING(dev->dev_private)); |
1da177e4 LT |
597 | } |
598 | ||
c153f45f EA |
599 | static int i915_flush_ioctl(struct drm_device *dev, void *data, |
600 | struct drm_file *file_priv) | |
1da177e4 | 601 | { |
546b0974 EA |
602 | int ret; |
603 | ||
cd9d4e9f DV |
604 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
605 | return -ENODEV; | |
606 | ||
546b0974 | 607 | RING_LOCK_TEST_WITH_RETURN(dev, file_priv); |
1da177e4 | 608 | |
546b0974 EA |
609 | mutex_lock(&dev->struct_mutex); |
610 | ret = i915_quiescent(dev); | |
611 | mutex_unlock(&dev->struct_mutex); | |
612 | ||
613 | return ret; | |
1da177e4 LT |
614 | } |
615 | ||
c153f45f EA |
616 | static int i915_batchbuffer(struct drm_device *dev, void *data, |
617 | struct drm_file *file_priv) | |
1da177e4 | 618 | { |
1da177e4 | 619 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
7c1c2871 | 620 | struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv; |
1da177e4 | 621 | drm_i915_sarea_t *sarea_priv = (drm_i915_sarea_t *) |
7c1c2871 | 622 | master_priv->sarea_priv; |
c153f45f | 623 | drm_i915_batchbuffer_t *batch = data; |
1da177e4 | 624 | int ret; |
201361a5 | 625 | struct drm_clip_rect *cliprects = NULL; |
1da177e4 | 626 | |
cd9d4e9f DV |
627 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
628 | return -ENODEV; | |
629 | ||
8781342d | 630 | if (!dev_priv->dri1.allow_batchbuffer) { |
1da177e4 | 631 | DRM_ERROR("Batchbuffer ioctl disabled\n"); |
20caafa6 | 632 | return -EINVAL; |
1da177e4 LT |
633 | } |
634 | ||
8a4c47f3 | 635 | DRM_DEBUG_DRIVER("i915 batchbuffer, start %x used %d cliprects %d\n", |
be25ed9c | 636 | batch->start, batch->used, batch->num_cliprects); |
1da177e4 | 637 | |
546b0974 | 638 | RING_LOCK_TEST_WITH_RETURN(dev, file_priv); |
1da177e4 | 639 | |
201361a5 EA |
640 | if (batch->num_cliprects < 0) |
641 | return -EINVAL; | |
642 | ||
643 | if (batch->num_cliprects) { | |
9a298b2a EA |
644 | cliprects = kcalloc(batch->num_cliprects, |
645 | sizeof(struct drm_clip_rect), | |
646 | GFP_KERNEL); | |
201361a5 EA |
647 | if (cliprects == NULL) |
648 | return -ENOMEM; | |
649 | ||
650 | ret = copy_from_user(cliprects, batch->cliprects, | |
651 | batch->num_cliprects * | |
652 | sizeof(struct drm_clip_rect)); | |
9927a403 DC |
653 | if (ret != 0) { |
654 | ret = -EFAULT; | |
201361a5 | 655 | goto fail_free; |
9927a403 | 656 | } |
201361a5 | 657 | } |
1da177e4 | 658 | |
546b0974 | 659 | mutex_lock(&dev->struct_mutex); |
201361a5 | 660 | ret = i915_dispatch_batchbuffer(dev, batch, cliprects); |
546b0974 | 661 | mutex_unlock(&dev->struct_mutex); |
1da177e4 | 662 | |
c99b058f | 663 | if (sarea_priv) |
0baf823a | 664 | sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv); |
201361a5 EA |
665 | |
666 | fail_free: | |
9a298b2a | 667 | kfree(cliprects); |
201361a5 | 668 | |
1da177e4 LT |
669 | return ret; |
670 | } | |
671 | ||
c153f45f EA |
672 | static int i915_cmdbuffer(struct drm_device *dev, void *data, |
673 | struct drm_file *file_priv) | |
1da177e4 | 674 | { |
1da177e4 | 675 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
7c1c2871 | 676 | struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv; |
1da177e4 | 677 | drm_i915_sarea_t *sarea_priv = (drm_i915_sarea_t *) |
7c1c2871 | 678 | master_priv->sarea_priv; |
c153f45f | 679 | drm_i915_cmdbuffer_t *cmdbuf = data; |
201361a5 EA |
680 | struct drm_clip_rect *cliprects = NULL; |
681 | void *batch_data; | |
1da177e4 LT |
682 | int ret; |
683 | ||
8a4c47f3 | 684 | DRM_DEBUG_DRIVER("i915 cmdbuffer, buf %p sz %d cliprects %d\n", |
be25ed9c | 685 | cmdbuf->buf, cmdbuf->sz, cmdbuf->num_cliprects); |
1da177e4 | 686 | |
cd9d4e9f DV |
687 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
688 | return -ENODEV; | |
689 | ||
546b0974 | 690 | RING_LOCK_TEST_WITH_RETURN(dev, file_priv); |
1da177e4 | 691 | |
201361a5 EA |
692 | if (cmdbuf->num_cliprects < 0) |
693 | return -EINVAL; | |
694 | ||
9a298b2a | 695 | batch_data = kmalloc(cmdbuf->sz, GFP_KERNEL); |
201361a5 EA |
696 | if (batch_data == NULL) |
697 | return -ENOMEM; | |
698 | ||
699 | ret = copy_from_user(batch_data, cmdbuf->buf, cmdbuf->sz); | |
9927a403 DC |
700 | if (ret != 0) { |
701 | ret = -EFAULT; | |
201361a5 | 702 | goto fail_batch_free; |
9927a403 | 703 | } |
201361a5 EA |
704 | |
705 | if (cmdbuf->num_cliprects) { | |
9a298b2a EA |
706 | cliprects = kcalloc(cmdbuf->num_cliprects, |
707 | sizeof(struct drm_clip_rect), GFP_KERNEL); | |
a40e8d31 OA |
708 | if (cliprects == NULL) { |
709 | ret = -ENOMEM; | |
201361a5 | 710 | goto fail_batch_free; |
a40e8d31 | 711 | } |
201361a5 EA |
712 | |
713 | ret = copy_from_user(cliprects, cmdbuf->cliprects, | |
714 | cmdbuf->num_cliprects * | |
715 | sizeof(struct drm_clip_rect)); | |
9927a403 DC |
716 | if (ret != 0) { |
717 | ret = -EFAULT; | |
201361a5 | 718 | goto fail_clip_free; |
9927a403 | 719 | } |
1da177e4 LT |
720 | } |
721 | ||
546b0974 | 722 | mutex_lock(&dev->struct_mutex); |
201361a5 | 723 | ret = i915_dispatch_cmdbuffer(dev, cmdbuf, cliprects, batch_data); |
546b0974 | 724 | mutex_unlock(&dev->struct_mutex); |
1da177e4 LT |
725 | if (ret) { |
726 | DRM_ERROR("i915_dispatch_cmdbuffer failed\n"); | |
355d7f37 | 727 | goto fail_clip_free; |
1da177e4 LT |
728 | } |
729 | ||
c99b058f | 730 | if (sarea_priv) |
0baf823a | 731 | sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv); |
201361a5 | 732 | |
201361a5 | 733 | fail_clip_free: |
9a298b2a | 734 | kfree(cliprects); |
355d7f37 | 735 | fail_batch_free: |
9a298b2a | 736 | kfree(batch_data); |
201361a5 EA |
737 | |
738 | return ret; | |
1da177e4 LT |
739 | } |
740 | ||
9488867a DV |
741 | static int i915_emit_irq(struct drm_device * dev) |
742 | { | |
743 | drm_i915_private_t *dev_priv = dev->dev_private; | |
744 | struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv; | |
745 | ||
746 | i915_kernel_lost_context(dev); | |
747 | ||
748 | DRM_DEBUG_DRIVER("\n"); | |
749 | ||
231f42a4 DV |
750 | dev_priv->dri1.counter++; |
751 | if (dev_priv->dri1.counter > 0x7FFFFFFFUL) | |
752 | dev_priv->dri1.counter = 1; | |
9488867a | 753 | if (master_priv->sarea_priv) |
231f42a4 | 754 | master_priv->sarea_priv->last_enqueue = dev_priv->dri1.counter; |
9488867a DV |
755 | |
756 | if (BEGIN_LP_RING(4) == 0) { | |
757 | OUT_RING(MI_STORE_DWORD_INDEX); | |
758 | OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT); | |
231f42a4 | 759 | OUT_RING(dev_priv->dri1.counter); |
9488867a DV |
760 | OUT_RING(MI_USER_INTERRUPT); |
761 | ADVANCE_LP_RING(); | |
762 | } | |
763 | ||
231f42a4 | 764 | return dev_priv->dri1.counter; |
9488867a DV |
765 | } |
766 | ||
767 | static int i915_wait_irq(struct drm_device * dev, int irq_nr) | |
768 | { | |
769 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
770 | struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv; | |
771 | int ret = 0; | |
772 | struct intel_ring_buffer *ring = LP_RING(dev_priv); | |
773 | ||
774 | DRM_DEBUG_DRIVER("irq_nr=%d breadcrumb=%d\n", irq_nr, | |
775 | READ_BREADCRUMB(dev_priv)); | |
776 | ||
777 | if (READ_BREADCRUMB(dev_priv) >= irq_nr) { | |
778 | if (master_priv->sarea_priv) | |
779 | master_priv->sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv); | |
780 | return 0; | |
781 | } | |
782 | ||
783 | if (master_priv->sarea_priv) | |
784 | master_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT; | |
785 | ||
786 | if (ring->irq_get(ring)) { | |
787 | DRM_WAIT_ON(ret, ring->irq_queue, 3 * DRM_HZ, | |
788 | READ_BREADCRUMB(dev_priv) >= irq_nr); | |
789 | ring->irq_put(ring); | |
790 | } else if (wait_for(READ_BREADCRUMB(dev_priv) >= irq_nr, 3000)) | |
791 | ret = -EBUSY; | |
792 | ||
793 | if (ret == -EBUSY) { | |
794 | DRM_ERROR("EBUSY -- rec: %d emitted: %d\n", | |
231f42a4 | 795 | READ_BREADCRUMB(dev_priv), (int)dev_priv->dri1.counter); |
9488867a DV |
796 | } |
797 | ||
798 | return ret; | |
799 | } | |
800 | ||
801 | /* Needs the lock as it touches the ring. | |
802 | */ | |
803 | static int i915_irq_emit(struct drm_device *dev, void *data, | |
804 | struct drm_file *file_priv) | |
805 | { | |
806 | drm_i915_private_t *dev_priv = dev->dev_private; | |
807 | drm_i915_irq_emit_t *emit = data; | |
808 | int result; | |
809 | ||
810 | if (drm_core_check_feature(dev, DRIVER_MODESET)) | |
811 | return -ENODEV; | |
812 | ||
813 | if (!dev_priv || !LP_RING(dev_priv)->virtual_start) { | |
814 | DRM_ERROR("called with no initialization\n"); | |
815 | return -EINVAL; | |
816 | } | |
817 | ||
818 | RING_LOCK_TEST_WITH_RETURN(dev, file_priv); | |
819 | ||
820 | mutex_lock(&dev->struct_mutex); | |
821 | result = i915_emit_irq(dev); | |
822 | mutex_unlock(&dev->struct_mutex); | |
823 | ||
824 | if (DRM_COPY_TO_USER(emit->irq_seq, &result, sizeof(int))) { | |
825 | DRM_ERROR("copy_to_user\n"); | |
826 | return -EFAULT; | |
827 | } | |
828 | ||
829 | return 0; | |
830 | } | |
831 | ||
832 | /* Doesn't need the hardware lock. | |
833 | */ | |
834 | static int i915_irq_wait(struct drm_device *dev, void *data, | |
835 | struct drm_file *file_priv) | |
836 | { | |
837 | drm_i915_private_t *dev_priv = dev->dev_private; | |
838 | drm_i915_irq_wait_t *irqwait = data; | |
839 | ||
840 | if (drm_core_check_feature(dev, DRIVER_MODESET)) | |
841 | return -ENODEV; | |
842 | ||
843 | if (!dev_priv) { | |
844 | DRM_ERROR("called with no initialization\n"); | |
845 | return -EINVAL; | |
846 | } | |
847 | ||
848 | return i915_wait_irq(dev, irqwait->irq_seq); | |
849 | } | |
850 | ||
d1c1edbc DV |
851 | static int i915_vblank_pipe_get(struct drm_device *dev, void *data, |
852 | struct drm_file *file_priv) | |
853 | { | |
854 | drm_i915_private_t *dev_priv = dev->dev_private; | |
855 | drm_i915_vblank_pipe_t *pipe = data; | |
856 | ||
857 | if (drm_core_check_feature(dev, DRIVER_MODESET)) | |
858 | return -ENODEV; | |
859 | ||
860 | if (!dev_priv) { | |
861 | DRM_ERROR("called with no initialization\n"); | |
862 | return -EINVAL; | |
863 | } | |
864 | ||
865 | pipe->pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B; | |
866 | ||
867 | return 0; | |
868 | } | |
869 | ||
870 | /** | |
871 | * Schedule buffer swap at given vertical blank. | |
872 | */ | |
873 | static int i915_vblank_swap(struct drm_device *dev, void *data, | |
874 | struct drm_file *file_priv) | |
875 | { | |
876 | /* The delayed swap mechanism was fundamentally racy, and has been | |
877 | * removed. The model was that the client requested a delayed flip/swap | |
878 | * from the kernel, then waited for vblank before continuing to perform | |
879 | * rendering. The problem was that the kernel might wake the client | |
880 | * up before it dispatched the vblank swap (since the lock has to be | |
881 | * held while touching the ringbuffer), in which case the client would | |
882 | * clear and start the next frame before the swap occurred, and | |
883 | * flicker would occur in addition to likely missing the vblank. | |
884 | * | |
885 | * In the absence of this ioctl, userland falls back to a correct path | |
886 | * of waiting for a vblank, then dispatching the swap on its own. | |
887 | * Context switching to userland and back is plenty fast enough for | |
888 | * meeting the requirements of vblank swapping. | |
889 | */ | |
890 | return -EINVAL; | |
891 | } | |
892 | ||
c153f45f EA |
893 | static int i915_flip_bufs(struct drm_device *dev, void *data, |
894 | struct drm_file *file_priv) | |
1da177e4 | 895 | { |
546b0974 EA |
896 | int ret; |
897 | ||
cd9d4e9f DV |
898 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
899 | return -ENODEV; | |
900 | ||
8a4c47f3 | 901 | DRM_DEBUG_DRIVER("%s\n", __func__); |
1da177e4 | 902 | |
546b0974 | 903 | RING_LOCK_TEST_WITH_RETURN(dev, file_priv); |
1da177e4 | 904 | |
546b0974 EA |
905 | mutex_lock(&dev->struct_mutex); |
906 | ret = i915_dispatch_flip(dev); | |
907 | mutex_unlock(&dev->struct_mutex); | |
908 | ||
909 | return ret; | |
1da177e4 LT |
910 | } |
911 | ||
c153f45f EA |
912 | static int i915_getparam(struct drm_device *dev, void *data, |
913 | struct drm_file *file_priv) | |
1da177e4 | 914 | { |
1da177e4 | 915 | drm_i915_private_t *dev_priv = dev->dev_private; |
c153f45f | 916 | drm_i915_getparam_t *param = data; |
1da177e4 LT |
917 | int value; |
918 | ||
919 | if (!dev_priv) { | |
3e684eae | 920 | DRM_ERROR("called with no initialization\n"); |
20caafa6 | 921 | return -EINVAL; |
1da177e4 LT |
922 | } |
923 | ||
c153f45f | 924 | switch (param->param) { |
1da177e4 | 925 | case I915_PARAM_IRQ_ACTIVE: |
0a3e67a4 | 926 | value = dev->pdev->irq ? 1 : 0; |
1da177e4 LT |
927 | break; |
928 | case I915_PARAM_ALLOW_BATCHBUFFER: | |
8781342d | 929 | value = dev_priv->dri1.allow_batchbuffer ? 1 : 0; |
1da177e4 | 930 | break; |
0d6aa60b DA |
931 | case I915_PARAM_LAST_DISPATCH: |
932 | value = READ_BREADCRUMB(dev_priv); | |
933 | break; | |
ed4c9c4a KH |
934 | case I915_PARAM_CHIPSET_ID: |
935 | value = dev->pci_device; | |
936 | break; | |
673a394b | 937 | case I915_PARAM_HAS_GEM: |
2e895b17 | 938 | value = 1; |
673a394b | 939 | break; |
0f973f27 JB |
940 | case I915_PARAM_NUM_FENCES_AVAIL: |
941 | value = dev_priv->num_fence_regs - dev_priv->fence_reg_start; | |
942 | break; | |
02e792fb DV |
943 | case I915_PARAM_HAS_OVERLAY: |
944 | value = dev_priv->overlay ? 1 : 0; | |
945 | break; | |
e9560f7c JB |
946 | case I915_PARAM_HAS_PAGEFLIPPING: |
947 | value = 1; | |
948 | break; | |
76446cac JB |
949 | case I915_PARAM_HAS_EXECBUF2: |
950 | /* depends on GEM */ | |
2e895b17 | 951 | value = 1; |
76446cac | 952 | break; |
e3a815fc | 953 | case I915_PARAM_HAS_BSD: |
edc912f5 | 954 | value = intel_ring_initialized(&dev_priv->ring[VCS]); |
e3a815fc | 955 | break; |
549f7365 | 956 | case I915_PARAM_HAS_BLT: |
edc912f5 | 957 | value = intel_ring_initialized(&dev_priv->ring[BCS]); |
549f7365 | 958 | break; |
a00b10c3 CW |
959 | case I915_PARAM_HAS_RELAXED_FENCING: |
960 | value = 1; | |
961 | break; | |
bbf0c6b3 DV |
962 | case I915_PARAM_HAS_COHERENT_RINGS: |
963 | value = 1; | |
964 | break; | |
72bfa19c CW |
965 | case I915_PARAM_HAS_EXEC_CONSTANTS: |
966 | value = INTEL_INFO(dev)->gen >= 4; | |
967 | break; | |
271d81b8 CW |
968 | case I915_PARAM_HAS_RELAXED_DELTA: |
969 | value = 1; | |
970 | break; | |
ae662d31 EA |
971 | case I915_PARAM_HAS_GEN7_SOL_RESET: |
972 | value = 1; | |
973 | break; | |
3d29b842 ED |
974 | case I915_PARAM_HAS_LLC: |
975 | value = HAS_LLC(dev); | |
976 | break; | |
777ee96f DV |
977 | case I915_PARAM_HAS_ALIASING_PPGTT: |
978 | value = dev_priv->mm.aliasing_ppgtt ? 1 : 0; | |
979 | break; | |
172cf15d BW |
980 | case I915_PARAM_HAS_WAIT_TIMEOUT: |
981 | value = 1; | |
982 | break; | |
2fedbff9 CW |
983 | case I915_PARAM_HAS_SEMAPHORES: |
984 | value = i915_semaphore_is_enabled(dev); | |
985 | break; | |
ec6f1bb9 DA |
986 | case I915_PARAM_HAS_PRIME_VMAP_FLUSH: |
987 | value = 1; | |
988 | break; | |
d7d4eedd CW |
989 | case I915_PARAM_HAS_SECURE_BATCHES: |
990 | value = capable(CAP_SYS_ADMIN); | |
991 | break; | |
b45305fc DV |
992 | case I915_PARAM_HAS_PINNED_BATCHES: |
993 | value = 1; | |
994 | break; | |
1da177e4 | 995 | default: |
8a4c47f3 | 996 | DRM_DEBUG_DRIVER("Unknown parameter %d\n", |
76446cac | 997 | param->param); |
20caafa6 | 998 | return -EINVAL; |
1da177e4 LT |
999 | } |
1000 | ||
c153f45f | 1001 | if (DRM_COPY_TO_USER(param->value, &value, sizeof(int))) { |
1da177e4 | 1002 | DRM_ERROR("DRM_COPY_TO_USER failed\n"); |
20caafa6 | 1003 | return -EFAULT; |
1da177e4 LT |
1004 | } |
1005 | ||
1006 | return 0; | |
1007 | } | |
1008 | ||
c153f45f EA |
1009 | static int i915_setparam(struct drm_device *dev, void *data, |
1010 | struct drm_file *file_priv) | |
1da177e4 | 1011 | { |
1da177e4 | 1012 | drm_i915_private_t *dev_priv = dev->dev_private; |
c153f45f | 1013 | drm_i915_setparam_t *param = data; |
1da177e4 LT |
1014 | |
1015 | if (!dev_priv) { | |
3e684eae | 1016 | DRM_ERROR("called with no initialization\n"); |
20caafa6 | 1017 | return -EINVAL; |
1da177e4 LT |
1018 | } |
1019 | ||
c153f45f | 1020 | switch (param->param) { |
1da177e4 | 1021 | case I915_SETPARAM_USE_MI_BATCHBUFFER_START: |
1da177e4 LT |
1022 | break; |
1023 | case I915_SETPARAM_TEX_LRU_LOG_GRANULARITY: | |
1da177e4 LT |
1024 | break; |
1025 | case I915_SETPARAM_ALLOW_BATCHBUFFER: | |
8781342d | 1026 | dev_priv->dri1.allow_batchbuffer = param->value ? 1 : 0; |
1da177e4 | 1027 | break; |
0f973f27 JB |
1028 | case I915_SETPARAM_NUM_USED_FENCES: |
1029 | if (param->value > dev_priv->num_fence_regs || | |
1030 | param->value < 0) | |
1031 | return -EINVAL; | |
1032 | /* Userspace can use first N regs */ | |
1033 | dev_priv->fence_reg_start = param->value; | |
1034 | break; | |
1da177e4 | 1035 | default: |
8a4c47f3 | 1036 | DRM_DEBUG_DRIVER("unknown parameter %d\n", |
be25ed9c | 1037 | param->param); |
20caafa6 | 1038 | return -EINVAL; |
1da177e4 LT |
1039 | } |
1040 | ||
1041 | return 0; | |
1042 | } | |
1043 | ||
c153f45f EA |
1044 | static int i915_set_status_page(struct drm_device *dev, void *data, |
1045 | struct drm_file *file_priv) | |
dc7a9319 | 1046 | { |
dc7a9319 | 1047 | drm_i915_private_t *dev_priv = dev->dev_private; |
c153f45f | 1048 | drm_i915_hws_addr_t *hws = data; |
4f1ba0f8 | 1049 | struct intel_ring_buffer *ring; |
b39d50e5 | 1050 | |
cd9d4e9f DV |
1051 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
1052 | return -ENODEV; | |
1053 | ||
b39d50e5 ZW |
1054 | if (!I915_NEED_GFX_HWS(dev)) |
1055 | return -EINVAL; | |
dc7a9319 WZ |
1056 | |
1057 | if (!dev_priv) { | |
3e684eae | 1058 | DRM_ERROR("called with no initialization\n"); |
20caafa6 | 1059 | return -EINVAL; |
dc7a9319 | 1060 | } |
dc7a9319 | 1061 | |
79e53945 JB |
1062 | if (drm_core_check_feature(dev, DRIVER_MODESET)) { |
1063 | WARN(1, "tried to set status page when mode setting active\n"); | |
1064 | return 0; | |
1065 | } | |
1066 | ||
8a4c47f3 | 1067 | DRM_DEBUG_DRIVER("set status page addr 0x%08x\n", (u32)hws->addr); |
c153f45f | 1068 | |
4f1ba0f8 | 1069 | ring = LP_RING(dev_priv); |
8187a2b7 | 1070 | ring->status_page.gfx_addr = hws->addr & (0x1ffff<<12); |
dc7a9319 | 1071 | |
dd2757f8 DV |
1072 | dev_priv->dri1.gfx_hws_cpu_addr = |
1073 | ioremap_wc(dev_priv->mm.gtt_base_addr + hws->addr, 4096); | |
316d3884 | 1074 | if (dev_priv->dri1.gfx_hws_cpu_addr == NULL) { |
dc7a9319 | 1075 | i915_dma_cleanup(dev); |
e20f9c64 | 1076 | ring->status_page.gfx_addr = 0; |
dc7a9319 WZ |
1077 | DRM_ERROR("can not ioremap virtual address for" |
1078 | " G33 hw status page\n"); | |
20caafa6 | 1079 | return -ENOMEM; |
dc7a9319 | 1080 | } |
316d3884 DV |
1081 | |
1082 | memset_io(dev_priv->dri1.gfx_hws_cpu_addr, 0, PAGE_SIZE); | |
8187a2b7 | 1083 | I915_WRITE(HWS_PGA, ring->status_page.gfx_addr); |
dc7a9319 | 1084 | |
8a4c47f3 | 1085 | DRM_DEBUG_DRIVER("load hws HWS_PGA with gfx mem 0x%x\n", |
e20f9c64 | 1086 | ring->status_page.gfx_addr); |
8a4c47f3 | 1087 | DRM_DEBUG_DRIVER("load hws at %p\n", |
e20f9c64 | 1088 | ring->status_page.page_addr); |
dc7a9319 WZ |
1089 | return 0; |
1090 | } | |
1091 | ||
ec2a4c3f DA |
1092 | static int i915_get_bridge_dev(struct drm_device *dev) |
1093 | { | |
1094 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1095 | ||
0206e353 | 1096 | dev_priv->bridge_dev = pci_get_bus_and_slot(0, PCI_DEVFN(0, 0)); |
ec2a4c3f DA |
1097 | if (!dev_priv->bridge_dev) { |
1098 | DRM_ERROR("bridge device not found\n"); | |
1099 | return -1; | |
1100 | } | |
1101 | return 0; | |
1102 | } | |
1103 | ||
c4804411 ZW |
1104 | #define MCHBAR_I915 0x44 |
1105 | #define MCHBAR_I965 0x48 | |
1106 | #define MCHBAR_SIZE (4*4096) | |
1107 | ||
1108 | #define DEVEN_REG 0x54 | |
1109 | #define DEVEN_MCHBAR_EN (1 << 28) | |
1110 | ||
1111 | /* Allocate space for the MCH regs if needed, return nonzero on error */ | |
1112 | static int | |
1113 | intel_alloc_mchbar_resource(struct drm_device *dev) | |
1114 | { | |
1115 | drm_i915_private_t *dev_priv = dev->dev_private; | |
a6c45cf0 | 1116 | int reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915; |
c4804411 ZW |
1117 | u32 temp_lo, temp_hi = 0; |
1118 | u64 mchbar_addr; | |
a25c25c2 | 1119 | int ret; |
c4804411 | 1120 | |
a6c45cf0 | 1121 | if (INTEL_INFO(dev)->gen >= 4) |
c4804411 ZW |
1122 | pci_read_config_dword(dev_priv->bridge_dev, reg + 4, &temp_hi); |
1123 | pci_read_config_dword(dev_priv->bridge_dev, reg, &temp_lo); | |
1124 | mchbar_addr = ((u64)temp_hi << 32) | temp_lo; | |
1125 | ||
1126 | /* If ACPI doesn't have it, assume we need to allocate it ourselves */ | |
1127 | #ifdef CONFIG_PNP | |
1128 | if (mchbar_addr && | |
a25c25c2 CW |
1129 | pnp_range_reserved(mchbar_addr, mchbar_addr + MCHBAR_SIZE)) |
1130 | return 0; | |
c4804411 ZW |
1131 | #endif |
1132 | ||
1133 | /* Get some space for it */ | |
a25c25c2 CW |
1134 | dev_priv->mch_res.name = "i915 MCHBAR"; |
1135 | dev_priv->mch_res.flags = IORESOURCE_MEM; | |
1136 | ret = pci_bus_alloc_resource(dev_priv->bridge_dev->bus, | |
1137 | &dev_priv->mch_res, | |
c4804411 ZW |
1138 | MCHBAR_SIZE, MCHBAR_SIZE, |
1139 | PCIBIOS_MIN_MEM, | |
a25c25c2 | 1140 | 0, pcibios_align_resource, |
c4804411 ZW |
1141 | dev_priv->bridge_dev); |
1142 | if (ret) { | |
1143 | DRM_DEBUG_DRIVER("failed bus alloc: %d\n", ret); | |
1144 | dev_priv->mch_res.start = 0; | |
a25c25c2 | 1145 | return ret; |
c4804411 ZW |
1146 | } |
1147 | ||
a6c45cf0 | 1148 | if (INTEL_INFO(dev)->gen >= 4) |
c4804411 ZW |
1149 | pci_write_config_dword(dev_priv->bridge_dev, reg + 4, |
1150 | upper_32_bits(dev_priv->mch_res.start)); | |
1151 | ||
1152 | pci_write_config_dword(dev_priv->bridge_dev, reg, | |
1153 | lower_32_bits(dev_priv->mch_res.start)); | |
a25c25c2 | 1154 | return 0; |
c4804411 ZW |
1155 | } |
1156 | ||
1157 | /* Setup MCHBAR if possible, return true if we should disable it again */ | |
1158 | static void | |
1159 | intel_setup_mchbar(struct drm_device *dev) | |
1160 | { | |
1161 | drm_i915_private_t *dev_priv = dev->dev_private; | |
a6c45cf0 | 1162 | int mchbar_reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915; |
c4804411 ZW |
1163 | u32 temp; |
1164 | bool enabled; | |
1165 | ||
1166 | dev_priv->mchbar_need_disable = false; | |
1167 | ||
1168 | if (IS_I915G(dev) || IS_I915GM(dev)) { | |
1169 | pci_read_config_dword(dev_priv->bridge_dev, DEVEN_REG, &temp); | |
1170 | enabled = !!(temp & DEVEN_MCHBAR_EN); | |
1171 | } else { | |
1172 | pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp); | |
1173 | enabled = temp & 1; | |
1174 | } | |
1175 | ||
1176 | /* If it's already enabled, don't have to do anything */ | |
1177 | if (enabled) | |
1178 | return; | |
1179 | ||
1180 | if (intel_alloc_mchbar_resource(dev)) | |
1181 | return; | |
1182 | ||
1183 | dev_priv->mchbar_need_disable = true; | |
1184 | ||
1185 | /* Space is allocated or reserved, so enable it. */ | |
1186 | if (IS_I915G(dev) || IS_I915GM(dev)) { | |
1187 | pci_write_config_dword(dev_priv->bridge_dev, DEVEN_REG, | |
1188 | temp | DEVEN_MCHBAR_EN); | |
1189 | } else { | |
1190 | pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp); | |
1191 | pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp | 1); | |
1192 | } | |
1193 | } | |
1194 | ||
1195 | static void | |
1196 | intel_teardown_mchbar(struct drm_device *dev) | |
1197 | { | |
1198 | drm_i915_private_t *dev_priv = dev->dev_private; | |
a6c45cf0 | 1199 | int mchbar_reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915; |
c4804411 ZW |
1200 | u32 temp; |
1201 | ||
1202 | if (dev_priv->mchbar_need_disable) { | |
1203 | if (IS_I915G(dev) || IS_I915GM(dev)) { | |
1204 | pci_read_config_dword(dev_priv->bridge_dev, DEVEN_REG, &temp); | |
1205 | temp &= ~DEVEN_MCHBAR_EN; | |
1206 | pci_write_config_dword(dev_priv->bridge_dev, DEVEN_REG, temp); | |
1207 | } else { | |
1208 | pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp); | |
1209 | temp &= ~1; | |
1210 | pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp); | |
1211 | } | |
1212 | } | |
1213 | ||
1214 | if (dev_priv->mch_res.start) | |
1215 | release_resource(&dev_priv->mch_res); | |
1216 | } | |
1217 | ||
28d52043 DA |
1218 | /* true = enable decode, false = disable decoder */ |
1219 | static unsigned int i915_vga_set_decode(void *cookie, bool state) | |
1220 | { | |
1221 | struct drm_device *dev = cookie; | |
1222 | ||
1223 | intel_modeset_vga_set_state(dev, state); | |
1224 | if (state) | |
1225 | return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM | | |
1226 | VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM; | |
1227 | else | |
1228 | return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM; | |
1229 | } | |
1230 | ||
6a9ee8af DA |
1231 | static void i915_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state) |
1232 | { | |
1233 | struct drm_device *dev = pci_get_drvdata(pdev); | |
1234 | pm_message_t pmm = { .event = PM_EVENT_SUSPEND }; | |
1235 | if (state == VGA_SWITCHEROO_ON) { | |
a70491cc | 1236 | pr_info("switched on\n"); |
5bcf719b | 1237 | dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; |
6a9ee8af DA |
1238 | /* i915 resume handler doesn't set to D0 */ |
1239 | pci_set_power_state(dev->pdev, PCI_D0); | |
1240 | i915_resume(dev); | |
5bcf719b | 1241 | dev->switch_power_state = DRM_SWITCH_POWER_ON; |
6a9ee8af | 1242 | } else { |
a70491cc | 1243 | pr_err("switched off\n"); |
5bcf719b | 1244 | dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; |
6a9ee8af | 1245 | i915_suspend(dev, pmm); |
5bcf719b | 1246 | dev->switch_power_state = DRM_SWITCH_POWER_OFF; |
6a9ee8af DA |
1247 | } |
1248 | } | |
1249 | ||
1250 | static bool i915_switcheroo_can_switch(struct pci_dev *pdev) | |
1251 | { | |
1252 | struct drm_device *dev = pci_get_drvdata(pdev); | |
1253 | bool can_switch; | |
1254 | ||
1255 | spin_lock(&dev->count_lock); | |
1256 | can_switch = (dev->open_count == 0); | |
1257 | spin_unlock(&dev->count_lock); | |
1258 | return can_switch; | |
1259 | } | |
1260 | ||
26ec685f TI |
1261 | static const struct vga_switcheroo_client_ops i915_switcheroo_ops = { |
1262 | .set_gpu_state = i915_switcheroo_set_state, | |
1263 | .reprobe = NULL, | |
1264 | .can_switch = i915_switcheroo_can_switch, | |
1265 | }; | |
1266 | ||
2c7111db CW |
1267 | static int i915_load_modeset_init(struct drm_device *dev) |
1268 | { | |
1269 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1270 | int ret; | |
79e53945 | 1271 | |
6d139a87 | 1272 | ret = intel_parse_bios(dev); |
79e53945 JB |
1273 | if (ret) |
1274 | DRM_INFO("failed to find VBIOS tables\n"); | |
1275 | ||
934f992c CW |
1276 | /* If we have > 1 VGA cards, then we need to arbitrate access |
1277 | * to the common VGA resources. | |
1278 | * | |
1279 | * If we are a secondary display controller (!PCI_DISPLAY_CLASS_VGA), | |
1280 | * then we do not take part in VGA arbitration and the | |
1281 | * vga_client_register() fails with -ENODEV. | |
1282 | */ | |
28d52043 | 1283 | ret = vga_client_register(dev->pdev, dev, NULL, i915_vga_set_decode); |
934f992c | 1284 | if (ret && ret != -ENODEV) |
2c7111db | 1285 | goto out; |
28d52043 | 1286 | |
723bfd70 JB |
1287 | intel_register_dsm_handler(); |
1288 | ||
26ec685f | 1289 | ret = vga_switcheroo_register_client(dev->pdev, &i915_switcheroo_ops); |
6a9ee8af | 1290 | if (ret) |
5a79395b | 1291 | goto cleanup_vga_client; |
6a9ee8af | 1292 | |
9797fbfb CW |
1293 | /* Initialise stolen first so that we may reserve preallocated |
1294 | * objects for the BIOS to KMS transition. | |
1295 | */ | |
1296 | ret = i915_gem_init_stolen(dev); | |
1297 | if (ret) | |
1298 | goto cleanup_vga_switcheroo; | |
1299 | ||
b01f2c3a JB |
1300 | intel_modeset_init(dev); |
1301 | ||
1070a42b | 1302 | ret = i915_gem_init(dev); |
79e53945 | 1303 | if (ret) |
9797fbfb | 1304 | goto cleanup_gem_stolen; |
79e53945 | 1305 | |
2c7111db CW |
1306 | intel_modeset_gem_init(dev); |
1307 | ||
073f34d9 JB |
1308 | INIT_WORK(&dev_priv->console_resume_work, intel_console_resume); |
1309 | ||
2c7111db CW |
1310 | ret = drm_irq_install(dev); |
1311 | if (ret) | |
1312 | goto cleanup_gem; | |
1313 | ||
79e53945 JB |
1314 | /* Always safe in the mode setting case. */ |
1315 | /* FIXME: do pre/post-mode set stuff in core KMS code */ | |
1316 | dev->vblank_disable_allowed = 1; | |
1317 | ||
5a79395b CW |
1318 | ret = intel_fbdev_init(dev); |
1319 | if (ret) | |
1320 | goto cleanup_irq; | |
1321 | ||
eb1f8e4f | 1322 | drm_kms_helper_poll_init(dev); |
87acb0a5 CW |
1323 | |
1324 | /* We're off and running w/KMS */ | |
1325 | dev_priv->mm.suspended = 0; | |
1326 | ||
79e53945 JB |
1327 | return 0; |
1328 | ||
5a79395b CW |
1329 | cleanup_irq: |
1330 | drm_irq_uninstall(dev); | |
2c7111db CW |
1331 | cleanup_gem: |
1332 | mutex_lock(&dev->struct_mutex); | |
1333 | i915_gem_cleanup_ringbuffer(dev); | |
1334 | mutex_unlock(&dev->struct_mutex); | |
1d2a314c | 1335 | i915_gem_cleanup_aliasing_ppgtt(dev); |
9797fbfb CW |
1336 | cleanup_gem_stolen: |
1337 | i915_gem_cleanup_stolen(dev); | |
5a79395b CW |
1338 | cleanup_vga_switcheroo: |
1339 | vga_switcheroo_unregister_client(dev->pdev); | |
1340 | cleanup_vga_client: | |
1341 | vga_client_register(dev->pdev, NULL, NULL, NULL); | |
79e53945 JB |
1342 | out: |
1343 | return ret; | |
1344 | } | |
1345 | ||
7c1c2871 DA |
1346 | int i915_master_create(struct drm_device *dev, struct drm_master *master) |
1347 | { | |
1348 | struct drm_i915_master_private *master_priv; | |
1349 | ||
9a298b2a | 1350 | master_priv = kzalloc(sizeof(*master_priv), GFP_KERNEL); |
7c1c2871 DA |
1351 | if (!master_priv) |
1352 | return -ENOMEM; | |
1353 | ||
1354 | master->driver_priv = master_priv; | |
1355 | return 0; | |
1356 | } | |
1357 | ||
1358 | void i915_master_destroy(struct drm_device *dev, struct drm_master *master) | |
1359 | { | |
1360 | struct drm_i915_master_private *master_priv = master->driver_priv; | |
1361 | ||
1362 | if (!master_priv) | |
1363 | return; | |
1364 | ||
9a298b2a | 1365 | kfree(master_priv); |
7c1c2871 DA |
1366 | |
1367 | master->driver_priv = NULL; | |
1368 | } | |
1369 | ||
e2b665c4 AJ |
1370 | static void |
1371 | i915_mtrr_setup(struct drm_i915_private *dev_priv, unsigned long base, | |
1372 | unsigned long size) | |
1373 | { | |
23f54bea CW |
1374 | dev_priv->mm.gtt_mtrr = -1; |
1375 | ||
9e984bc1 AJ |
1376 | #if defined(CONFIG_X86_PAT) |
1377 | if (cpu_has_pat) | |
1378 | return; | |
1379 | #endif | |
1380 | ||
e2b665c4 AJ |
1381 | /* Set up a WC MTRR for non-PAT systems. This is more common than |
1382 | * one would think, because the kernel disables PAT on first | |
1383 | * generation Core chips because WC PAT gets overridden by a UC | |
1384 | * MTRR if present. Even if a UC MTRR isn't present. | |
1385 | */ | |
1386 | dev_priv->mm.gtt_mtrr = mtrr_add(base, size, MTRR_TYPE_WRCOMB, 1); | |
1387 | if (dev_priv->mm.gtt_mtrr < 0) { | |
1388 | DRM_INFO("MTRR allocation failed. Graphics " | |
1389 | "performance may suffer.\n"); | |
1390 | } | |
1391 | } | |
1392 | ||
e188719a DV |
1393 | static void i915_kick_out_firmware_fb(struct drm_i915_private *dev_priv) |
1394 | { | |
1395 | struct apertures_struct *ap; | |
1396 | struct pci_dev *pdev = dev_priv->dev->pdev; | |
1397 | bool primary; | |
1398 | ||
1399 | ap = alloc_apertures(1); | |
1400 | if (!ap) | |
1401 | return; | |
1402 | ||
87207ca2 | 1403 | ap->ranges[0].base = dev_priv->mm.gtt->gma_bus_addr; |
e188719a DV |
1404 | ap->ranges[0].size = |
1405 | dev_priv->mm.gtt->gtt_mappable_entries << PAGE_SHIFT; | |
1406 | primary = | |
1407 | pdev->resource[PCI_ROM_RESOURCE].flags & IORESOURCE_ROM_SHADOW; | |
1408 | ||
1409 | remove_conflicting_framebuffers(ap, "inteldrmfb", primary); | |
1410 | ||
1411 | kfree(ap); | |
1412 | } | |
1413 | ||
c96ea64e DV |
1414 | static void i915_dump_device_info(struct drm_i915_private *dev_priv) |
1415 | { | |
1416 | const struct intel_device_info *info = dev_priv->info; | |
1417 | ||
1418 | #define DEV_INFO_FLAG(name) info->name ? #name "," : "" | |
1419 | #define DEV_INFO_SEP , | |
1420 | DRM_DEBUG_DRIVER("i915 device info: gen=%i, pciid=0x%04x flags=" | |
1421 | "%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s", | |
1422 | info->gen, | |
1423 | dev_priv->dev->pdev->device, | |
1424 | DEV_INFO_FLAGS); | |
1425 | #undef DEV_INFO_FLAG | |
1426 | #undef DEV_INFO_SEP | |
1427 | } | |
1428 | ||
79e53945 JB |
1429 | /** |
1430 | * i915_driver_load - setup chip and create an initial config | |
1431 | * @dev: DRM device | |
1432 | * @flags: startup flags | |
1433 | * | |
1434 | * The driver load routine has to do several things: | |
1435 | * - drive output discovery via intel_modeset_init() | |
1436 | * - initialize the memory manager | |
1437 | * - allocate initial config memory | |
1438 | * - setup the DRM framebuffer with the allocated memory | |
1439 | */ | |
84b1fd10 | 1440 | int i915_driver_load(struct drm_device *dev, unsigned long flags) |
22eae947 | 1441 | { |
ea059a1e | 1442 | struct drm_i915_private *dev_priv; |
26394d92 | 1443 | struct intel_device_info *info; |
934d6086 | 1444 | int ret = 0, mmio_bar, mmio_size; |
9021f284 | 1445 | uint32_t aperture_size; |
fe669bf8 | 1446 | |
26394d92 DV |
1447 | info = (struct intel_device_info *) flags; |
1448 | ||
1449 | /* Refuse to load on gen6+ without kms enabled. */ | |
1450 | if (info->gen >= 6 && !drm_core_check_feature(dev, DRIVER_MODESET)) | |
1451 | return -ENODEV; | |
1452 | ||
22eae947 DA |
1453 | /* i915 has 4 more counters */ |
1454 | dev->counters += 4; | |
1455 | dev->types[6] = _DRM_STAT_IRQ; | |
1456 | dev->types[7] = _DRM_STAT_PRIMARY; | |
1457 | dev->types[8] = _DRM_STAT_SECONDARY; | |
1458 | dev->types[9] = _DRM_STAT_DMA; | |
1459 | ||
9a298b2a | 1460 | dev_priv = kzalloc(sizeof(drm_i915_private_t), GFP_KERNEL); |
ba8bbcf6 JB |
1461 | if (dev_priv == NULL) |
1462 | return -ENOMEM; | |
1463 | ||
ba8bbcf6 | 1464 | dev->dev_private = (void *)dev_priv; |
673a394b | 1465 | dev_priv->dev = dev; |
26394d92 | 1466 | dev_priv->info = info; |
ba8bbcf6 | 1467 | |
c96ea64e DV |
1468 | i915_dump_device_info(dev_priv); |
1469 | ||
ec2a4c3f DA |
1470 | if (i915_get_bridge_dev(dev)) { |
1471 | ret = -EIO; | |
1472 | goto free_priv; | |
1473 | } | |
1474 | ||
e76e9aeb BW |
1475 | ret = i915_gem_gtt_init(dev); |
1476 | if (ret) | |
e188719a | 1477 | goto put_bridge; |
e188719a | 1478 | |
1623392a CW |
1479 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
1480 | i915_kick_out_firmware_fb(dev_priv); | |
e188719a | 1481 | |
466e69b8 DA |
1482 | pci_set_master(dev->pdev); |
1483 | ||
9f82d238 DV |
1484 | /* overlay on gen2 is broken and can't address above 1G */ |
1485 | if (IS_GEN2(dev)) | |
1486 | dma_set_coherent_mask(&dev->pdev->dev, DMA_BIT_MASK(30)); | |
1487 | ||
6927faf3 JN |
1488 | /* 965GM sometimes incorrectly writes to hardware status page (HWS) |
1489 | * using 32bit addressing, overwriting memory if HWS is located | |
1490 | * above 4GB. | |
1491 | * | |
1492 | * The documentation also mentions an issue with undefined | |
1493 | * behaviour if any general state is accessed within a page above 4GB, | |
1494 | * which also needs to be handled carefully. | |
1495 | */ | |
1496 | if (IS_BROADWATER(dev) || IS_CRESTLINE(dev)) | |
1497 | dma_set_coherent_mask(&dev->pdev->dev, DMA_BIT_MASK(32)); | |
1498 | ||
b4ce0f85 | 1499 | mmio_bar = IS_GEN2(dev) ? 1 : 0; |
934d6086 CW |
1500 | /* Before gen4, the registers and the GTT are behind different BARs. |
1501 | * However, from gen4 onwards, the registers and the GTT are shared | |
1502 | * in the same BAR, so we want to restrict this ioremap from | |
1503 | * clobbering the GTT which we want ioremap_wc instead. Fortunately, | |
1504 | * the register BAR remains the same size for all the earlier | |
1505 | * generations up to Ironlake. | |
1506 | */ | |
1507 | if (info->gen < 5) | |
1508 | mmio_size = 512*1024; | |
1509 | else | |
1510 | mmio_size = 2*1024*1024; | |
1511 | ||
1512 | dev_priv->regs = pci_iomap(dev->pdev, mmio_bar, mmio_size); | |
b4ce0f85 CW |
1513 | if (!dev_priv->regs) { |
1514 | DRM_ERROR("failed to map registers\n"); | |
1515 | ret = -EIO; | |
14be93dd | 1516 | goto put_gmch; |
71e9339c CW |
1517 | } |
1518 | ||
9021f284 | 1519 | aperture_size = dev_priv->mm.gtt->gtt_mappable_entries << PAGE_SHIFT; |
dd2757f8 | 1520 | dev_priv->mm.gtt_base_addr = dev_priv->mm.gtt->gma_bus_addr; |
71e9339c | 1521 | |
0206e353 | 1522 | dev_priv->mm.gtt_mapping = |
dd2757f8 DV |
1523 | io_mapping_create_wc(dev_priv->mm.gtt_base_addr, |
1524 | aperture_size); | |
6644107d VP |
1525 | if (dev_priv->mm.gtt_mapping == NULL) { |
1526 | ret = -EIO; | |
e188719a | 1527 | goto out_rmmap; |
6644107d VP |
1528 | } |
1529 | ||
dd2757f8 DV |
1530 | i915_mtrr_setup(dev_priv, dev_priv->mm.gtt_base_addr, |
1531 | aperture_size); | |
19966754 | 1532 | |
e642abbf CW |
1533 | /* The i915 workqueue is primarily used for batched retirement of |
1534 | * requests (and thus managing bo) once the task has been completed | |
1535 | * by the GPU. i915_gem_retire_requests() is called directly when we | |
1536 | * need high-priority retirement, such as waiting for an explicit | |
1537 | * bo. | |
1538 | * | |
1539 | * It is also used for periodic low-priority events, such as | |
df9c2042 | 1540 | * idle-timers and recording error state. |
e642abbf CW |
1541 | * |
1542 | * All tasks on the workqueue are expected to acquire the dev mutex | |
1543 | * so there is no point in running more than one instance of the | |
53621860 | 1544 | * workqueue at any time. Use an ordered one. |
e642abbf | 1545 | */ |
53621860 | 1546 | dev_priv->wq = alloc_ordered_workqueue("i915", 0); |
9c9fe1f8 EA |
1547 | if (dev_priv->wq == NULL) { |
1548 | DRM_ERROR("Failed to create our workqueue.\n"); | |
1549 | ret = -ENOMEM; | |
a7b85d2a | 1550 | goto out_mtrrfree; |
9c9fe1f8 EA |
1551 | } |
1552 | ||
45e6e3a1 PZ |
1553 | /* This must be called before any calls to HAS_PCH_* */ |
1554 | intel_detect_pch(dev); | |
1555 | ||
f71d4af4 | 1556 | intel_irq_init(dev); |
990bbdad | 1557 | intel_gt_init(dev); |
9880b7a5 | 1558 | |
c4804411 ZW |
1559 | /* Try to make sure MCHBAR is enabled before poking at it */ |
1560 | intel_setup_mchbar(dev); | |
f899fc64 | 1561 | intel_setup_gmbus(dev); |
44834a67 | 1562 | intel_opregion_setup(dev); |
c4804411 | 1563 | |
6d139a87 BF |
1564 | intel_setup_bios(dev); |
1565 | ||
673a394b EA |
1566 | i915_gem_load(dev); |
1567 | ||
ed4cb414 EA |
1568 | /* On the 945G/GM, the chipset reports the MSI capability on the |
1569 | * integrated graphics even though the support isn't actually there | |
1570 | * according to the published specs. It doesn't appear to function | |
1571 | * correctly in testing on 945G. | |
1572 | * This may be a side effect of MSI having been made available for PEG | |
1573 | * and the registers being closely associated. | |
d1ed629f KP |
1574 | * |
1575 | * According to chipset errata, on the 965GM, MSI interrupts may | |
b60678a7 KP |
1576 | * be lost or delayed, but we use them anyways to avoid |
1577 | * stuck interrupts on some machines. | |
ed4cb414 | 1578 | */ |
b60678a7 | 1579 | if (!IS_I945G(dev) && !IS_I945GM(dev)) |
d3e74d02 | 1580 | pci_enable_msi(dev->pdev); |
ed4cb414 | 1581 | |
1ec14ad3 | 1582 | spin_lock_init(&dev_priv->irq_lock); |
63eeaf38 | 1583 | spin_lock_init(&dev_priv->error_lock); |
c6a828d3 | 1584 | spin_lock_init(&dev_priv->rps.lock); |
99d0b1db | 1585 | spin_lock_init(&dev_priv->dpio_lock); |
ed4cb414 | 1586 | |
4fc688ce JB |
1587 | mutex_init(&dev_priv->rps.hw_lock); |
1588 | ||
c51ed787 | 1589 | if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) |
27f8227b JB |
1590 | dev_priv->num_pipe = 3; |
1591 | else if (IS_MOBILE(dev) || !IS_GEN2(dev)) | |
9db4a9c7 JB |
1592 | dev_priv->num_pipe = 2; |
1593 | else | |
1594 | dev_priv->num_pipe = 1; | |
1595 | ||
1596 | ret = drm_vblank_init(dev, dev_priv->num_pipe); | |
56e2ea34 CW |
1597 | if (ret) |
1598 | goto out_gem_unload; | |
52440211 | 1599 | |
11ed50ec BG |
1600 | /* Start out suspended */ |
1601 | dev_priv->mm.suspended = 1; | |
1602 | ||
79e53945 | 1603 | if (drm_core_check_feature(dev, DRIVER_MODESET)) { |
53984635 | 1604 | ret = i915_load_modeset_init(dev); |
79e53945 JB |
1605 | if (ret < 0) { |
1606 | DRM_ERROR("failed to init modeset\n"); | |
56e2ea34 | 1607 | goto out_gem_unload; |
79e53945 JB |
1608 | } |
1609 | } | |
1610 | ||
0136db58 BW |
1611 | i915_setup_sysfs(dev); |
1612 | ||
74a365b3 | 1613 | /* Must be done after probing outputs */ |
44834a67 CW |
1614 | intel_opregion_init(dev); |
1615 | acpi_video_register(); | |
74a365b3 | 1616 | |
f65d9421 BG |
1617 | setup_timer(&dev_priv->hangcheck_timer, i915_hangcheck_elapsed, |
1618 | (unsigned long) dev); | |
7648fa99 | 1619 | |
eb48eb00 DV |
1620 | if (IS_GEN5(dev)) |
1621 | intel_gpu_ips_init(dev_priv); | |
63ee41d7 | 1622 | |
79e53945 JB |
1623 | return 0; |
1624 | ||
56e2ea34 | 1625 | out_gem_unload: |
a7b85d2a KP |
1626 | if (dev_priv->mm.inactive_shrinker.shrink) |
1627 | unregister_shrinker(&dev_priv->mm.inactive_shrinker); | |
1628 | ||
56e2ea34 CW |
1629 | if (dev->pdev->msi_enabled) |
1630 | pci_disable_msi(dev->pdev); | |
1631 | ||
1632 | intel_teardown_gmbus(dev); | |
1633 | intel_teardown_mchbar(dev); | |
9c9fe1f8 | 1634 | destroy_workqueue(dev_priv->wq); |
a7b85d2a KP |
1635 | out_mtrrfree: |
1636 | if (dev_priv->mm.gtt_mtrr >= 0) { | |
dd2757f8 DV |
1637 | mtrr_del(dev_priv->mm.gtt_mtrr, |
1638 | dev_priv->mm.gtt_base_addr, | |
1639 | aperture_size); | |
a7b85d2a KP |
1640 | dev_priv->mm.gtt_mtrr = -1; |
1641 | } | |
6644107d | 1642 | io_mapping_free(dev_priv->mm.gtt_mapping); |
79e53945 | 1643 | out_rmmap: |
6dda569f | 1644 | pci_iounmap(dev->pdev, dev_priv->regs); |
e188719a | 1645 | put_gmch: |
e76e9aeb | 1646 | i915_gem_gtt_fini(dev); |
ec2a4c3f DA |
1647 | put_bridge: |
1648 | pci_dev_put(dev_priv->bridge_dev); | |
79e53945 | 1649 | free_priv: |
9a298b2a | 1650 | kfree(dev_priv); |
ba8bbcf6 JB |
1651 | return ret; |
1652 | } | |
1653 | ||
1654 | int i915_driver_unload(struct drm_device *dev) | |
1655 | { | |
1656 | struct drm_i915_private *dev_priv = dev->dev_private; | |
c911fc1c | 1657 | int ret; |
ba8bbcf6 | 1658 | |
eb48eb00 | 1659 | intel_gpu_ips_teardown(); |
7648fa99 | 1660 | |
0136db58 BW |
1661 | i915_teardown_sysfs(dev); |
1662 | ||
17250b71 CW |
1663 | if (dev_priv->mm.inactive_shrinker.shrink) |
1664 | unregister_shrinker(&dev_priv->mm.inactive_shrinker); | |
1665 | ||
c911fc1c | 1666 | mutex_lock(&dev->struct_mutex); |
b2da9fe5 | 1667 | ret = i915_gpu_idle(dev); |
c911fc1c DV |
1668 | if (ret) |
1669 | DRM_ERROR("failed to idle hardware: %d\n", ret); | |
b2da9fe5 | 1670 | i915_gem_retire_requests(dev); |
c911fc1c DV |
1671 | mutex_unlock(&dev->struct_mutex); |
1672 | ||
75ef9da2 DV |
1673 | /* Cancel the retire work handler, which should be idle now. */ |
1674 | cancel_delayed_work_sync(&dev_priv->mm.retire_work); | |
1675 | ||
ab657db1 EA |
1676 | io_mapping_free(dev_priv->mm.gtt_mapping); |
1677 | if (dev_priv->mm.gtt_mtrr >= 0) { | |
dd2757f8 DV |
1678 | mtrr_del(dev_priv->mm.gtt_mtrr, |
1679 | dev_priv->mm.gtt_base_addr, | |
1680 | dev_priv->mm.gtt->gtt_mappable_entries * PAGE_SIZE); | |
ab657db1 EA |
1681 | dev_priv->mm.gtt_mtrr = -1; |
1682 | } | |
1683 | ||
44834a67 CW |
1684 | acpi_video_unregister(); |
1685 | ||
79e53945 | 1686 | if (drm_core_check_feature(dev, DRIVER_MODESET)) { |
7b4f3990 | 1687 | intel_fbdev_fini(dev); |
3d8620cc | 1688 | intel_modeset_cleanup(dev); |
073f34d9 | 1689 | cancel_work_sync(&dev_priv->console_resume_work); |
3d8620cc | 1690 | |
6363ee6f ZY |
1691 | /* |
1692 | * free the memory space allocated for the child device | |
1693 | * config parsed from VBT | |
1694 | */ | |
1695 | if (dev_priv->child_dev && dev_priv->child_dev_num) { | |
1696 | kfree(dev_priv->child_dev); | |
1697 | dev_priv->child_dev = NULL; | |
1698 | dev_priv->child_dev_num = 0; | |
1699 | } | |
6c0d9350 | 1700 | |
6a9ee8af | 1701 | vga_switcheroo_unregister_client(dev->pdev); |
28d52043 | 1702 | vga_client_register(dev->pdev, NULL, NULL, NULL); |
79e53945 JB |
1703 | } |
1704 | ||
a8b4899e | 1705 | /* Free error state after interrupts are fully disabled. */ |
bc0c7f14 DV |
1706 | del_timer_sync(&dev_priv->hangcheck_timer); |
1707 | cancel_work_sync(&dev_priv->error_work); | |
a8b4899e | 1708 | i915_destroy_error_state(dev); |
bc0c7f14 | 1709 | |
ed4cb414 EA |
1710 | if (dev->pdev->msi_enabled) |
1711 | pci_disable_msi(dev->pdev); | |
1712 | ||
44834a67 | 1713 | intel_opregion_fini(dev); |
8ee1c3db | 1714 | |
79e53945 | 1715 | if (drm_core_check_feature(dev, DRIVER_MODESET)) { |
67e77c5a DV |
1716 | /* Flush any outstanding unpin_work. */ |
1717 | flush_workqueue(dev_priv->wq); | |
1718 | ||
79e53945 | 1719 | mutex_lock(&dev->struct_mutex); |
ecbec53b | 1720 | i915_gem_free_all_phys_object(dev); |
79e53945 | 1721 | i915_gem_cleanup_ringbuffer(dev); |
55a66628 | 1722 | i915_gem_context_fini(dev); |
79e53945 | 1723 | mutex_unlock(&dev->struct_mutex); |
1d2a314c | 1724 | i915_gem_cleanup_aliasing_ppgtt(dev); |
9797fbfb | 1725 | i915_gem_cleanup_stolen(dev); |
fe669bf8 | 1726 | drm_mm_takedown(&dev_priv->mm.stolen); |
02e792fb DV |
1727 | |
1728 | intel_cleanup_overlay(dev); | |
c2873e96 KP |
1729 | |
1730 | if (!I915_NEED_GFX_HWS(dev)) | |
1731 | i915_free_hws(dev); | |
79e53945 JB |
1732 | } |
1733 | ||
701394cc | 1734 | if (dev_priv->regs != NULL) |
6dda569f | 1735 | pci_iounmap(dev->pdev, dev_priv->regs); |
701394cc | 1736 | |
f899fc64 | 1737 | intel_teardown_gmbus(dev); |
c4804411 ZW |
1738 | intel_teardown_mchbar(dev); |
1739 | ||
bc0c7f14 DV |
1740 | destroy_workqueue(dev_priv->wq); |
1741 | ||
ec2a4c3f | 1742 | pci_dev_put(dev_priv->bridge_dev); |
9a298b2a | 1743 | kfree(dev->dev_private); |
ba8bbcf6 | 1744 | |
22eae947 DA |
1745 | return 0; |
1746 | } | |
1747 | ||
f787a5f5 | 1748 | int i915_driver_open(struct drm_device *dev, struct drm_file *file) |
673a394b | 1749 | { |
f787a5f5 | 1750 | struct drm_i915_file_private *file_priv; |
673a394b | 1751 | |
8a4c47f3 | 1752 | DRM_DEBUG_DRIVER("\n"); |
f787a5f5 CW |
1753 | file_priv = kmalloc(sizeof(*file_priv), GFP_KERNEL); |
1754 | if (!file_priv) | |
673a394b EA |
1755 | return -ENOMEM; |
1756 | ||
f787a5f5 | 1757 | file->driver_priv = file_priv; |
673a394b | 1758 | |
1c25595f | 1759 | spin_lock_init(&file_priv->mm.lock); |
f787a5f5 | 1760 | INIT_LIST_HEAD(&file_priv->mm.request_list); |
673a394b | 1761 | |
df12c6d5 | 1762 | idr_init(&file_priv->context_idr); |
254f965c | 1763 | |
673a394b EA |
1764 | return 0; |
1765 | } | |
1766 | ||
79e53945 JB |
1767 | /** |
1768 | * i915_driver_lastclose - clean up after all DRM clients have exited | |
1769 | * @dev: DRM device | |
1770 | * | |
1771 | * Take care of cleaning up after all DRM clients have exited. In the | |
1772 | * mode setting case, we want to restore the kernel's initial mode (just | |
1773 | * in case the last client left us in a bad state). | |
1774 | * | |
9021f284 | 1775 | * Additionally, in the non-mode setting case, we'll tear down the GTT |
79e53945 JB |
1776 | * and DMA structures, since the kernel won't be using them, and clea |
1777 | * up any GEM state. | |
1778 | */ | |
84b1fd10 | 1779 | void i915_driver_lastclose(struct drm_device * dev) |
1da177e4 | 1780 | { |
ba8bbcf6 JB |
1781 | drm_i915_private_t *dev_priv = dev->dev_private; |
1782 | ||
e8aeaee7 DV |
1783 | /* On gen6+ we refuse to init without kms enabled, but then the drm core |
1784 | * goes right around and calls lastclose. Check for this and don't clean | |
1785 | * up anything. */ | |
1786 | if (!dev_priv) | |
1787 | return; | |
1788 | ||
1789 | if (drm_core_check_feature(dev, DRIVER_MODESET)) { | |
e8e7a2b8 | 1790 | intel_fb_restore_mode(dev); |
6a9ee8af | 1791 | vga_switcheroo_process_delayed_switch(); |
144a75fa | 1792 | return; |
79e53945 | 1793 | } |
144a75fa | 1794 | |
673a394b EA |
1795 | i915_gem_lastclose(dev); |
1796 | ||
b5e89ed5 | 1797 | i915_dma_cleanup(dev); |
1da177e4 LT |
1798 | } |
1799 | ||
6c340eac | 1800 | void i915_driver_preclose(struct drm_device * dev, struct drm_file *file_priv) |
1da177e4 | 1801 | { |
254f965c | 1802 | i915_gem_context_close(dev, file_priv); |
b962442e | 1803 | i915_gem_release(dev, file_priv); |
1da177e4 LT |
1804 | } |
1805 | ||
f787a5f5 | 1806 | void i915_driver_postclose(struct drm_device *dev, struct drm_file *file) |
673a394b | 1807 | { |
f787a5f5 | 1808 | struct drm_i915_file_private *file_priv = file->driver_priv; |
673a394b | 1809 | |
f787a5f5 | 1810 | kfree(file_priv); |
673a394b EA |
1811 | } |
1812 | ||
c153f45f | 1813 | struct drm_ioctl_desc i915_ioctls[] = { |
1b2f1489 DA |
1814 | DRM_IOCTL_DEF_DRV(I915_INIT, i915_dma_init, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), |
1815 | DRM_IOCTL_DEF_DRV(I915_FLUSH, i915_flush_ioctl, DRM_AUTH), | |
1816 | DRM_IOCTL_DEF_DRV(I915_FLIP, i915_flip_bufs, DRM_AUTH), | |
1817 | DRM_IOCTL_DEF_DRV(I915_BATCHBUFFER, i915_batchbuffer, DRM_AUTH), | |
1818 | DRM_IOCTL_DEF_DRV(I915_IRQ_EMIT, i915_irq_emit, DRM_AUTH), | |
1819 | DRM_IOCTL_DEF_DRV(I915_IRQ_WAIT, i915_irq_wait, DRM_AUTH), | |
1820 | DRM_IOCTL_DEF_DRV(I915_GETPARAM, i915_getparam, DRM_AUTH), | |
1821 | DRM_IOCTL_DEF_DRV(I915_SETPARAM, i915_setparam, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), | |
b2c606fe DV |
1822 | DRM_IOCTL_DEF_DRV(I915_ALLOC, drm_noop, DRM_AUTH), |
1823 | DRM_IOCTL_DEF_DRV(I915_FREE, drm_noop, DRM_AUTH), | |
1824 | DRM_IOCTL_DEF_DRV(I915_INIT_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), | |
1b2f1489 | 1825 | DRM_IOCTL_DEF_DRV(I915_CMDBUFFER, i915_cmdbuffer, DRM_AUTH), |
b2c606fe | 1826 | DRM_IOCTL_DEF_DRV(I915_DESTROY_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), |
d1c1edbc | 1827 | DRM_IOCTL_DEF_DRV(I915_SET_VBLANK_PIPE, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), |
1b2f1489 DA |
1828 | DRM_IOCTL_DEF_DRV(I915_GET_VBLANK_PIPE, i915_vblank_pipe_get, DRM_AUTH), |
1829 | DRM_IOCTL_DEF_DRV(I915_VBLANK_SWAP, i915_vblank_swap, DRM_AUTH), | |
1830 | DRM_IOCTL_DEF_DRV(I915_HWS_ADDR, i915_set_status_page, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), | |
1831 | DRM_IOCTL_DEF_DRV(I915_GEM_INIT, i915_gem_init_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED), | |
1832 | DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER, i915_gem_execbuffer, DRM_AUTH|DRM_UNLOCKED), | |
1833 | DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER2, i915_gem_execbuffer2, DRM_AUTH|DRM_UNLOCKED), | |
1834 | DRM_IOCTL_DEF_DRV(I915_GEM_PIN, i915_gem_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY|DRM_UNLOCKED), | |
1835 | DRM_IOCTL_DEF_DRV(I915_GEM_UNPIN, i915_gem_unpin_ioctl, DRM_AUTH|DRM_ROOT_ONLY|DRM_UNLOCKED), | |
1836 | DRM_IOCTL_DEF_DRV(I915_GEM_BUSY, i915_gem_busy_ioctl, DRM_AUTH|DRM_UNLOCKED), | |
199adf40 BW |
1837 | DRM_IOCTL_DEF_DRV(I915_GEM_SET_CACHING, i915_gem_set_caching_ioctl, DRM_UNLOCKED), |
1838 | DRM_IOCTL_DEF_DRV(I915_GEM_GET_CACHING, i915_gem_get_caching_ioctl, DRM_UNLOCKED), | |
1b2f1489 DA |
1839 | DRM_IOCTL_DEF_DRV(I915_GEM_THROTTLE, i915_gem_throttle_ioctl, DRM_AUTH|DRM_UNLOCKED), |
1840 | DRM_IOCTL_DEF_DRV(I915_GEM_ENTERVT, i915_gem_entervt_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED), | |
1841 | DRM_IOCTL_DEF_DRV(I915_GEM_LEAVEVT, i915_gem_leavevt_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED), | |
1842 | DRM_IOCTL_DEF_DRV(I915_GEM_CREATE, i915_gem_create_ioctl, DRM_UNLOCKED), | |
1843 | DRM_IOCTL_DEF_DRV(I915_GEM_PREAD, i915_gem_pread_ioctl, DRM_UNLOCKED), | |
1844 | DRM_IOCTL_DEF_DRV(I915_GEM_PWRITE, i915_gem_pwrite_ioctl, DRM_UNLOCKED), | |
1845 | DRM_IOCTL_DEF_DRV(I915_GEM_MMAP, i915_gem_mmap_ioctl, DRM_UNLOCKED), | |
1846 | DRM_IOCTL_DEF_DRV(I915_GEM_MMAP_GTT, i915_gem_mmap_gtt_ioctl, DRM_UNLOCKED), | |
1847 | DRM_IOCTL_DEF_DRV(I915_GEM_SET_DOMAIN, i915_gem_set_domain_ioctl, DRM_UNLOCKED), | |
1848 | DRM_IOCTL_DEF_DRV(I915_GEM_SW_FINISH, i915_gem_sw_finish_ioctl, DRM_UNLOCKED), | |
1849 | DRM_IOCTL_DEF_DRV(I915_GEM_SET_TILING, i915_gem_set_tiling, DRM_UNLOCKED), | |
1850 | DRM_IOCTL_DEF_DRV(I915_GEM_GET_TILING, i915_gem_get_tiling, DRM_UNLOCKED), | |
1851 | DRM_IOCTL_DEF_DRV(I915_GEM_GET_APERTURE, i915_gem_get_aperture_ioctl, DRM_UNLOCKED), | |
1852 | DRM_IOCTL_DEF_DRV(I915_GET_PIPE_FROM_CRTC_ID, intel_get_pipe_from_crtc_id, DRM_UNLOCKED), | |
1853 | DRM_IOCTL_DEF_DRV(I915_GEM_MADVISE, i915_gem_madvise_ioctl, DRM_UNLOCKED), | |
1854 | DRM_IOCTL_DEF_DRV(I915_OVERLAY_PUT_IMAGE, intel_overlay_put_image, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED), | |
1855 | DRM_IOCTL_DEF_DRV(I915_OVERLAY_ATTRS, intel_overlay_attrs, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED), | |
8ea30864 JB |
1856 | DRM_IOCTL_DEF_DRV(I915_SET_SPRITE_COLORKEY, intel_sprite_set_colorkey, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED), |
1857 | DRM_IOCTL_DEF_DRV(I915_GET_SPRITE_COLORKEY, intel_sprite_get_colorkey, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED), | |
23ba4fd0 | 1858 | DRM_IOCTL_DEF_DRV(I915_GEM_WAIT, i915_gem_wait_ioctl, DRM_AUTH|DRM_UNLOCKED), |
84624813 BW |
1859 | DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_CREATE, i915_gem_context_create_ioctl, DRM_UNLOCKED), |
1860 | DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_DESTROY, i915_gem_context_destroy_ioctl, DRM_UNLOCKED), | |
c0c7babc | 1861 | DRM_IOCTL_DEF_DRV(I915_REG_READ, i915_reg_read_ioctl, DRM_UNLOCKED), |
c94f7029 DA |
1862 | }; |
1863 | ||
1864 | int i915_max_ioctl = DRM_ARRAY_SIZE(i915_ioctls); | |
cda17380 | 1865 | |
9021f284 DV |
1866 | /* |
1867 | * This is really ugly: Because old userspace abused the linux agp interface to | |
1868 | * manage the gtt, we need to claim that all intel devices are agp. For | |
1869 | * otherwise the drm core refuses to initialize the agp support code. | |
cda17380 | 1870 | */ |
84b1fd10 | 1871 | int i915_driver_device_is_agp(struct drm_device * dev) |
cda17380 DA |
1872 | { |
1873 | return 1; | |
1874 | } |