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drm/i915: ppgtt debugfs info
[deliverable/linux.git] / drivers / gpu / drm / i915 / i915_drv.c
CommitLineData
1da177e4
LT		 1/* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*-
2 */
0d6aa60b 3/*
bc54fd1a 4 *
1da177e4
LT		 5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
6 * All Rights Reserved.
bc54fd1a
DA		 7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
15 *
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
18 * of the Software.
19 *
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27 *
0d6aa60b 28 */
1da177e4 29
5669fcac 30#include <linux/device.h>
1da177e4
LT		 31#include "drmP.h"
32#include "drm.h"
33#include "i915_drm.h"
34#include "i915_drv.h"
f49f0586 35#include "intel_drv.h"
1da177e4 36
79e53945 37#include <linux/console.h>
e0cd3608 38#include <linux/module.h>
354ff967 39#include "drm_crtc_helper.h"
79e53945 40
a35d9d3c 41static int i915_modeset __read_mostly = -1;
79e53945 42module_param_named(modeset, i915_modeset, int, 0400);
6e96e775
BW		 43MODULE_PARM_DESC(modeset,
44 "Use kernel modesetting [KMS] (0=DRM_I915_KMS from .config, "
45 "1=on, -1=force vga console preference [default])");
79e53945 46
a35d9d3c 47unsigned int i915_fbpercrtc __always_unused = 0;
79e53945 48module_param_named(fbpercrtc, i915_fbpercrtc, int, 0400);
1da177e4 49
a35d9d3c 50int i915_panel_ignore_lid __read_mostly = 0;
fca87409 51module_param_named(panel_ignore_lid, i915_panel_ignore_lid, int, 0600);
6e96e775
BW		 52MODULE_PARM_DESC(panel_ignore_lid,
53 "Override lid status (0=autodetect [default], 1=lid open, "
54 "-1=lid closed)");
fca87409 55
a35d9d3c 56unsigned int i915_powersave __read_mostly = 1;
0aa99277 57module_param_named(powersave, i915_powersave, int, 0600);
6e96e775
BW		 58MODULE_PARM_DESC(powersave,
59 "Enable powersavings, fbc, downclocking, etc. (default: true)");
652c393a 60
f45b5557 61int i915_semaphores __read_mostly = -1;
a1656b90 62module_param_named(semaphores, i915_semaphores, int, 0600);
6e96e775 63MODULE_PARM_DESC(semaphores,
f45b5557 64 "Use semaphores for inter-ring sync (default: -1 (use per-chip defaults))");
a1656b90 65
c0f372b3 66int i915_enable_rc6 __read_mostly = -1;
ac668088 67module_param_named(i915_enable_rc6, i915_enable_rc6, int, 0600);
6e96e775 68MODULE_PARM_DESC(i915_enable_rc6,
c0f372b3 69 "Enable power-saving render C-state 6 (default: -1 (use per-chip default)");
ac668088 70
4415e63b 71int i915_enable_fbc __read_mostly = -1;
c1a9f047 72module_param_named(i915_enable_fbc, i915_enable_fbc, int, 0600);
6e96e775
BW		 73MODULE_PARM_DESC(i915_enable_fbc,
74 "Enable frame buffer compression for power savings "
cd0de039 75 "(default: -1 (use per-chip default))");
c1a9f047 76
a35d9d3c 77unsigned int i915_lvds_downclock __read_mostly = 0;
33814341 78module_param_named(lvds_downclock, i915_lvds_downclock, int, 0400);
6e96e775
BW		 79MODULE_PARM_DESC(lvds_downclock,
80 "Use panel (LVDS/eDP) downclocking for power savings "
81 "(default: false)");
33814341 82
4415e63b 83int i915_panel_use_ssc __read_mostly = -1;
a7615030 84module_param_named(lvds_use_ssc, i915_panel_use_ssc, int, 0600);
6e96e775
BW		 85MODULE_PARM_DESC(lvds_use_ssc,
86 "Use Spread Spectrum Clock with panels [LVDS/eDP] "
72bbe58c 87 "(default: auto from VBT)");
a7615030 88
a35d9d3c 89int i915_vbt_sdvo_panel_type __read_mostly = -1;
5a1e5b6c 90module_param_named(vbt_sdvo_panel_type, i915_vbt_sdvo_panel_type, int, 0600);
6e96e775
BW		 91MODULE_PARM_DESC(vbt_sdvo_panel_type,
92 "Override selection of SDVO panel mode in the VBT "
93 "(default: auto)");
5a1e5b6c 94
a35d9d3c 95static bool i915_try_reset __read_mostly = true;
d78cb50b 96module_param_named(reset, i915_try_reset, bool, 0600);
6e96e775 97MODULE_PARM_DESC(reset, "Attempt GPU resets (default: true)");
d78cb50b 98
a35d9d3c 99bool i915_enable_hangcheck __read_mostly = true;
3e0dc6b0 100module_param_named(enable_hangcheck, i915_enable_hangcheck, bool, 0644);
6e96e775
BW		 101MODULE_PARM_DESC(enable_hangcheck,
102 "Periodically check GPU activity for detecting hangs. "
103 "WARNING: Disabling this can cause system wide hangs. "
104 "(default: true)");
3e0dc6b0 105
112b715e 106static struct drm_driver driver;
1f7a6e37 107extern int intel_agp_enabled;
112b715e 108
cfdf1fa2 109#define INTEL_VGA_DEVICE(id, info) { \
80a2901d 110 .class = PCI_BASE_CLASS_DISPLAY << 16, \
934f992c 111 .class_mask = 0xff0000, \
49ae35f2
KH		 112 .vendor = 0x8086, \
113 .device = id, \
114 .subvendor = PCI_ANY_ID, \
115 .subdevice = PCI_ANY_ID, \
cfdf1fa2
KH		 116 .driver_data = (unsigned long) info }
117
9a7e8492 118static const struct intel_device_info intel_i830_info = {
a6c45cf0 119 .gen = 2, .is_mobile = 1, .cursor_needs_physical = 1,
31578148 120 .has_overlay = 1, .overlay_needs_physical = 1,
cfdf1fa2
KH		 121};
122
9a7e8492 123static const struct intel_device_info intel_845g_info = {
a6c45cf0 124 .gen = 2,
31578148 125 .has_overlay = 1, .overlay_needs_physical = 1,
cfdf1fa2
KH		 126};
127
9a7e8492 128static const struct intel_device_info intel_i85x_info = {
a6c45cf0 129 .gen = 2, .is_i85x = 1, .is_mobile = 1,
5ce8ba7c 130 .cursor_needs_physical = 1,
31578148 131 .has_overlay = 1, .overlay_needs_physical = 1,
cfdf1fa2
KH		 132};
133
9a7e8492 134static const struct intel_device_info intel_i865g_info = {
a6c45cf0 135 .gen = 2,
31578148 136 .has_overlay = 1, .overlay_needs_physical = 1,
cfdf1fa2
KH		 137};
138
9a7e8492 139static const struct intel_device_info intel_i915g_info = {
a6c45cf0 140 .gen = 3, .is_i915g = 1, .cursor_needs_physical = 1,
31578148 141 .has_overlay = 1, .overlay_needs_physical = 1,
cfdf1fa2 142};
9a7e8492 143static const struct intel_device_info intel_i915gm_info = {
a6c45cf0 144 .gen = 3, .is_mobile = 1,
b295d1b6 145 .cursor_needs_physical = 1,
31578148 146 .has_overlay = 1, .overlay_needs_physical = 1,
a6c45cf0 147 .supports_tv = 1,
cfdf1fa2 148};
9a7e8492 149static const struct intel_device_info intel_i945g_info = {
a6c45cf0 150 .gen = 3, .has_hotplug = 1, .cursor_needs_physical = 1,
31578148 151 .has_overlay = 1, .overlay_needs_physical = 1,
cfdf1fa2 152};
9a7e8492 153static const struct intel_device_info intel_i945gm_info = {
a6c45cf0 154 .gen = 3, .is_i945gm = 1, .is_mobile = 1,
b295d1b6 155 .has_hotplug = 1, .cursor_needs_physical = 1,
31578148 156 .has_overlay = 1, .overlay_needs_physical = 1,
a6c45cf0 157 .supports_tv = 1,
cfdf1fa2
KH		 158};
159
9a7e8492 160static const struct intel_device_info intel_i965g_info = {
a6c45cf0 161 .gen = 4, .is_broadwater = 1,
c96c3a8c 162 .has_hotplug = 1,
31578148 163 .has_overlay = 1,
cfdf1fa2
KH		 164};
165
9a7e8492 166static const struct intel_device_info intel_i965gm_info = {
a6c45cf0 167 .gen = 4, .is_crestline = 1,
e3c4e5dd 168 .is_mobile = 1, .has_fbc = 1, .has_hotplug = 1,
31578148 169 .has_overlay = 1,
a6c45cf0 170 .supports_tv = 1,
cfdf1fa2
KH		 171};
172
9a7e8492 173static const struct intel_device_info intel_g33_info = {
a6c45cf0 174 .gen = 3, .is_g33 = 1,
c96c3a8c 175 .need_gfx_hws = 1, .has_hotplug = 1,
31578148 176 .has_overlay = 1,
cfdf1fa2
KH		 177};
178
9a7e8492 179static const struct intel_device_info intel_g45_info = {
a6c45cf0 180 .gen = 4, .is_g4x = 1, .need_gfx_hws = 1,
c96c3a8c 181 .has_pipe_cxsr = 1, .has_hotplug = 1,
92f49d9c 182 .has_bsd_ring = 1,
cfdf1fa2
KH		 183};
184
9a7e8492 185static const struct intel_device_info intel_gm45_info = {
a6c45cf0 186 .gen = 4, .is_g4x = 1,
e3c4e5dd 187 .is_mobile = 1, .need_gfx_hws = 1, .has_fbc = 1,
c96c3a8c 188 .has_pipe_cxsr = 1, .has_hotplug = 1,
a6c45cf0 189 .supports_tv = 1,
92f49d9c 190 .has_bsd_ring = 1,
cfdf1fa2
KH		 191};
192
9a7e8492 193static const struct intel_device_info intel_pineview_info = {
a6c45cf0 194 .gen = 3, .is_g33 = 1, .is_pineview = 1, .is_mobile = 1,
c96c3a8c 195 .need_gfx_hws = 1, .has_hotplug = 1,
31578148 196 .has_overlay = 1,
cfdf1fa2
KH		 197};
198
9a7e8492 199static const struct intel_device_info intel_ironlake_d_info = {
f00a3ddf 200 .gen = 5,
5a117db7 201 .need_gfx_hws = 1, .has_hotplug = 1,
92f49d9c 202 .has_bsd_ring = 1,
cfdf1fa2
KH		 203};
204
9a7e8492 205static const struct intel_device_info intel_ironlake_m_info = {
f00a3ddf 206 .gen = 5, .is_mobile = 1,
e3c4e5dd 207 .need_gfx_hws = 1, .has_hotplug = 1,
c1a9f047 208 .has_fbc = 1,
92f49d9c 209 .has_bsd_ring = 1,
cfdf1fa2
KH		 210};
211
9a7e8492 212static const struct intel_device_info intel_sandybridge_d_info = {
a6c45cf0 213 .gen = 6,
c96c3a8c 214 .need_gfx_hws = 1, .has_hotplug = 1,
881f47b6 215 .has_bsd_ring = 1,
549f7365 216 .has_blt_ring = 1,
3d29b842 217 .has_llc = 1,
f6e450a6
EA		 218};
219
9a7e8492 220static const struct intel_device_info intel_sandybridge_m_info = {
a6c45cf0 221 .gen = 6, .is_mobile = 1,
c96c3a8c 222 .need_gfx_hws = 1, .has_hotplug = 1,
9c04f015 223 .has_fbc = 1,
881f47b6 224 .has_bsd_ring = 1,
549f7365 225 .has_blt_ring = 1,
3d29b842 226 .has_llc = 1,
a13e4093
EA		 227};
228
c76b615c
JB		 229static const struct intel_device_info intel_ivybridge_d_info = {
230 .is_ivybridge = 1, .gen = 7,
231 .need_gfx_hws = 1, .has_hotplug = 1,
232 .has_bsd_ring = 1,
233 .has_blt_ring = 1,
3d29b842 234 .has_llc = 1,
c76b615c
JB		 235};
236
237static const struct intel_device_info intel_ivybridge_m_info = {
238 .is_ivybridge = 1, .gen = 7, .is_mobile = 1,
239 .need_gfx_hws = 1, .has_hotplug = 1,
240 .has_fbc = 0, /* FBC is not enabled on Ivybridge mobile yet */
241 .has_bsd_ring = 1,
242 .has_blt_ring = 1,
3d29b842 243 .has_llc = 1,
c76b615c
JB		 244};
245
6103da0d
CW		 246static const struct pci_device_id pciidlist[] = { /* aka */
247 INTEL_VGA_DEVICE(0x3577, &intel_i830_info), /* I830_M */
248 INTEL_VGA_DEVICE(0x2562, &intel_845g_info), /* 845_G */
249 INTEL_VGA_DEVICE(0x3582, &intel_i85x_info), /* I855_GM */
5ce8ba7c 250 INTEL_VGA_DEVICE(0x358e, &intel_i85x_info),
6103da0d
CW		 251 INTEL_VGA_DEVICE(0x2572, &intel_i865g_info), /* I865_G */
252 INTEL_VGA_DEVICE(0x2582, &intel_i915g_info), /* I915_G */
253 INTEL_VGA_DEVICE(0x258a, &intel_i915g_info), /* E7221_G */
254 INTEL_VGA_DEVICE(0x2592, &intel_i915gm_info), /* I915_GM */
255 INTEL_VGA_DEVICE(0x2772, &intel_i945g_info), /* I945_G */
256 INTEL_VGA_DEVICE(0x27a2, &intel_i945gm_info), /* I945_GM */
257 INTEL_VGA_DEVICE(0x27ae, &intel_i945gm_info), /* I945_GME */
258 INTEL_VGA_DEVICE(0x2972, &intel_i965g_info), /* I946_GZ */
259 INTEL_VGA_DEVICE(0x2982, &intel_i965g_info), /* G35_G */
260 INTEL_VGA_DEVICE(0x2992, &intel_i965g_info), /* I965_Q */
261 INTEL_VGA_DEVICE(0x29a2, &intel_i965g_info), /* I965_G */
262 INTEL_VGA_DEVICE(0x29b2, &intel_g33_info), /* Q35_G */
263 INTEL_VGA_DEVICE(0x29c2, &intel_g33_info), /* G33_G */
264 INTEL_VGA_DEVICE(0x29d2, &intel_g33_info), /* Q33_G */
265 INTEL_VGA_DEVICE(0x2a02, &intel_i965gm_info), /* I965_GM */
266 INTEL_VGA_DEVICE(0x2a12, &intel_i965gm_info), /* I965_GME */
267 INTEL_VGA_DEVICE(0x2a42, &intel_gm45_info), /* GM45_G */
268 INTEL_VGA_DEVICE(0x2e02, &intel_g45_info), /* IGD_E_G */
269 INTEL_VGA_DEVICE(0x2e12, &intel_g45_info), /* Q45_G */
270 INTEL_VGA_DEVICE(0x2e22, &intel_g45_info), /* G45_G */
271 INTEL_VGA_DEVICE(0x2e32, &intel_g45_info), /* G41_G */
272 INTEL_VGA_DEVICE(0x2e42, &intel_g45_info), /* B43_G */
41a51428 273 INTEL_VGA_DEVICE(0x2e92, &intel_g45_info), /* B43_G.1 */
cfdf1fa2
KH		 274 INTEL_VGA_DEVICE(0xa001, &intel_pineview_info),
275 INTEL_VGA_DEVICE(0xa011, &intel_pineview_info),
276 INTEL_VGA_DEVICE(0x0042, &intel_ironlake_d_info),
277 INTEL_VGA_DEVICE(0x0046, &intel_ironlake_m_info),
f6e450a6 278 INTEL_VGA_DEVICE(0x0102, &intel_sandybridge_d_info),
85540480
ZW		 279 INTEL_VGA_DEVICE(0x0112, &intel_sandybridge_d_info),
280 INTEL_VGA_DEVICE(0x0122, &intel_sandybridge_d_info),
a13e4093 281 INTEL_VGA_DEVICE(0x0106, &intel_sandybridge_m_info),
85540480 282 INTEL_VGA_DEVICE(0x0116, &intel_sandybridge_m_info),
4fefe435 283 INTEL_VGA_DEVICE(0x0126, &intel_sandybridge_m_info),
85540480 284 INTEL_VGA_DEVICE(0x010A, &intel_sandybridge_d_info),
c76b615c
JB		 285 INTEL_VGA_DEVICE(0x0156, &intel_ivybridge_m_info), /* GT1 mobile */
286 INTEL_VGA_DEVICE(0x0166, &intel_ivybridge_m_info), /* GT2 mobile */
287 INTEL_VGA_DEVICE(0x0152, &intel_ivybridge_d_info), /* GT1 desktop */
288 INTEL_VGA_DEVICE(0x0162, &intel_ivybridge_d_info), /* GT2 desktop */
289 INTEL_VGA_DEVICE(0x015a, &intel_ivybridge_d_info), /* GT1 server */
49ae35f2 290 {0, 0, 0}
1da177e4
LT		 291};
292
79e53945
JB		 293#if defined(CONFIG_DRM_I915_KMS)
294MODULE_DEVICE_TABLE(pci, pciidlist);
295#endif
296
3bad0781 297#define INTEL_PCH_DEVICE_ID_MASK 0xff00
90711d50 298#define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00
3bad0781 299#define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00
c792513b 300#define INTEL_PCH_PPT_DEVICE_ID_TYPE 0x1e00
3bad0781 301
0206e353 302void intel_detect_pch(struct drm_device *dev)
3bad0781
ZW		 303{
304 struct drm_i915_private *dev_priv = dev->dev_private;
305 struct pci_dev *pch;
306
307 /*
308 * The reason to probe ISA bridge instead of Dev31:Fun0 is to
309 * make graphics device passthrough work easy for VMM, that only
310 * need to expose ISA bridge to let driver know the real hardware
311 * underneath. This is a requirement from virtualization team.
312 */
313 pch = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, NULL);
314 if (pch) {
315 if (pch->vendor == PCI_VENDOR_ID_INTEL) {
316 int id;
317 id = pch->device & INTEL_PCH_DEVICE_ID_MASK;
318
90711d50
JB		 319 if (id == INTEL_PCH_IBX_DEVICE_ID_TYPE) {
320 dev_priv->pch_type = PCH_IBX;
321 DRM_DEBUG_KMS("Found Ibex Peak PCH\n");
322 } else if (id == INTEL_PCH_CPT_DEVICE_ID_TYPE) {
3bad0781
ZW		 323 dev_priv->pch_type = PCH_CPT;
324 DRM_DEBUG_KMS("Found CougarPoint PCH\n");
c792513b
JB		 325 } else if (id == INTEL_PCH_PPT_DEVICE_ID_TYPE) {
326 /* PantherPoint is CPT compatible */
327 dev_priv->pch_type = PCH_CPT;
328 DRM_DEBUG_KMS("Found PatherPoint PCH\n");
3bad0781
ZW		 329 }
330 }
331 pci_dev_put(pch);
332 }
333}
334
8d715f00 335void __gen6_gt_force_wake_get(struct drm_i915_private *dev_priv)
eb43f4af
CW		 336{
337 int count;
338
339 count = 0;
340 while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1))
341 udelay(10);
342
343 I915_WRITE_NOTRACE(FORCEWAKE, 1);
344 POSTING_READ(FORCEWAKE);
345
346 count = 0;
347 while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1) == 0)
348 udelay(10);
349}
350
8d715f00
KP		 351void __gen6_gt_force_wake_mt_get(struct drm_i915_private *dev_priv)
352{
353 int count;
354
355 count = 0;
356 while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_MT_ACK) & 1))
357 udelay(10);
358
359 I915_WRITE_NOTRACE(FORCEWAKE_MT, (1<<16) | 1);
360 POSTING_READ(FORCEWAKE_MT);
361
362 count = 0;
363 while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_MT_ACK) & 1) == 0)
364 udelay(10);
365}
366
fcca7926
BW		 367/*
368 * Generally this is called implicitly by the register read function. However,
369 * if some sequence requires the GT to not power down then this function should
370 * be called at the beginning of the sequence followed by a call to
371 * gen6_gt_force_wake_put() at the end of the sequence.
372 */
373void gen6_gt_force_wake_get(struct drm_i915_private *dev_priv)
374{
375 WARN_ON(!mutex_is_locked(&dev_priv->dev->struct_mutex));
376
377 /* Forcewake is atomic in case we get in here without the lock */
378 if (atomic_add_return(1, &dev_priv->forcewake_count) == 1)
8d715f00 379 dev_priv->display.force_wake_get(dev_priv);
fcca7926
BW		 380}
381
8d715f00 382void __gen6_gt_force_wake_put(struct drm_i915_private *dev_priv)
eb43f4af
CW		 383{
384 I915_WRITE_NOTRACE(FORCEWAKE, 0);
385 POSTING_READ(FORCEWAKE);
386}
387
8d715f00
KP		 388void __gen6_gt_force_wake_mt_put(struct drm_i915_private *dev_priv)
389{
390 I915_WRITE_NOTRACE(FORCEWAKE_MT, (1<<16) | 0);
391 POSTING_READ(FORCEWAKE_MT);
392}
393
fcca7926
BW		 394/*
395 * see gen6_gt_force_wake_get()
396 */
397void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv)
398{
399 WARN_ON(!mutex_is_locked(&dev_priv->dev->struct_mutex));
400
401 if (atomic_dec_and_test(&dev_priv->forcewake_count))
8d715f00 402 dev_priv->display.force_wake_put(dev_priv);
fcca7926
BW		 403}
404
91355834
CW		 405void __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv)
406{
0206e353 407 if (dev_priv->gt_fifo_count < GT_FIFO_NUM_RESERVED_ENTRIES) {
95736720
CW		 408 int loop = 500;
409 u32 fifo = I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES);
410 while (fifo <= GT_FIFO_NUM_RESERVED_ENTRIES && loop--) {
411 udelay(10);
412 fifo = I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES);
413 }
414 WARN_ON(loop < 0 && fifo <= GT_FIFO_NUM_RESERVED_ENTRIES);
415 dev_priv->gt_fifo_count = fifo;
91355834 416 }
95736720 417 dev_priv->gt_fifo_count--;
91355834
CW		 418}
419
84b79f8d 420static int i915_drm_freeze(struct drm_device *dev)
ba8bbcf6 421{
61caf87c
RW		 422 struct drm_i915_private *dev_priv = dev->dev_private;
423
5bcf719b
DA		 424 drm_kms_helper_poll_disable(dev);
425
ba8bbcf6 426 pci_save_state(dev->pdev);
ba8bbcf6 427
5669fcac 428 /* If KMS is active, we do the leavevt stuff here */
226485e9 429 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
84b79f8d
RW		 430 int error = i915_gem_idle(dev);
431 if (error) {
226485e9 432 dev_err(&dev->pdev->dev,
84b79f8d
RW		 433 "GEM idle failed, resume might fail\n");
434 return error;
435 }
226485e9 436 drm_irq_uninstall(dev);
5669fcac
JB		 437 }
438
9e06dd39
JB		 439 i915_save_state(dev);
440
44834a67 441 intel_opregion_fini(dev);
8ee1c3db 442
84b79f8d
RW		 443 /* Modeset on resume, not lid events */
444 dev_priv->modeset_on_lid = 0;
61caf87c
RW		 445
446 return 0;
84b79f8d
RW		 447}
448
6a9ee8af 449int i915_suspend(struct drm_device *dev, pm_message_t state)
84b79f8d
RW		 450{
451 int error;
452
453 if (!dev || !dev->dev_private) {
454 DRM_ERROR("dev: %p\n", dev);
455 DRM_ERROR("DRM not initialized, aborting suspend.\n");
456 return -ENODEV;
457 }
458
459 if (state.event == PM_EVENT_PRETHAW)
460 return 0;
461
5bcf719b
DA		 462
463 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
464 return 0;
6eecba33 465
84b79f8d
RW		 466 error = i915_drm_freeze(dev);
467 if (error)
468 return error;
469
b932ccb5
DA		 470 if (state.event == PM_EVENT_SUSPEND) {
471 /* Shut down the device */
472 pci_disable_device(dev->pdev);
473 pci_set_power_state(dev->pdev, PCI_D3hot);
474 }
ba8bbcf6
JB		 475
476 return 0;
477}
478
84b79f8d 479static int i915_drm_thaw(struct drm_device *dev)
ba8bbcf6 480{
5669fcac 481 struct drm_i915_private *dev_priv = dev->dev_private;
84b79f8d 482 int error = 0;
8ee1c3db 483
d1c3b177
CW		 484 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
485 mutex_lock(&dev->struct_mutex);
486 i915_gem_restore_gtt_mappings(dev);
487 mutex_unlock(&dev->struct_mutex);
488 }
489
61caf87c 490 i915_restore_state(dev);
44834a67 491 intel_opregion_setup(dev);
61caf87c 492
5669fcac
JB		 493 /* KMS EnterVT equivalent */
494 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
495 mutex_lock(&dev->struct_mutex);
496 dev_priv->mm.suspended = 0;
497
f691e2f4 498 error = i915_gem_init_hw(dev);
5669fcac 499 mutex_unlock(&dev->struct_mutex);
226485e9 500
9fb526db
KP		 501 if (HAS_PCH_SPLIT(dev))
502 ironlake_init_pch_refclk(dev);
503
500f7147 504 drm_mode_config_reset(dev);
226485e9 505 drm_irq_install(dev);
84b79f8d 506
354ff967
ZY		 507 /* Resume the modeset for every activated CRTC */
508 drm_helper_resume_force_mode(dev);
5669fcac 509
ac668088 510 if (IS_IRONLAKE_M(dev))
d5bb081b
JB		 511 ironlake_enable_rc6(dev);
512 }
1daed3fb 513
44834a67
CW		 514 intel_opregion_init(dev);
515
c9354c85 516 dev_priv->modeset_on_lid = 0;
06891e27 517
84b79f8d
RW		 518 return error;
519}
520
6a9ee8af 521int i915_resume(struct drm_device *dev)
84b79f8d 522{
6eecba33
CW		 523 int ret;
524
5bcf719b
DA		 525 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
526 return 0;
527
84b79f8d
RW		 528 if (pci_enable_device(dev->pdev))
529 return -EIO;
530
531 pci_set_master(dev->pdev);
532
6eecba33
CW		 533 ret = i915_drm_thaw(dev);
534 if (ret)
535 return ret;
536
537 drm_kms_helper_poll_enable(dev);
538 return 0;
ba8bbcf6
JB		 539}
540
dc96e9b8
CW		 541static int i8xx_do_reset(struct drm_device *dev, u8 flags)
542{
543 struct drm_i915_private *dev_priv = dev->dev_private;
544
545 if (IS_I85X(dev))
546 return -ENODEV;
547
548 I915_WRITE(D_STATE, I915_READ(D_STATE) | DSTATE_GFX_RESET_I830);
549 POSTING_READ(D_STATE);
550
551 if (IS_I830(dev) || IS_845G(dev)) {
552 I915_WRITE(DEBUG_RESET_I830,
553 DEBUG_RESET_DISPLAY |
554 DEBUG_RESET_RENDER |
555 DEBUG_RESET_FULL);
556 POSTING_READ(DEBUG_RESET_I830);
557 msleep(1);
558
559 I915_WRITE(DEBUG_RESET_I830, 0);
560 POSTING_READ(DEBUG_RESET_I830);
561 }
562
563 msleep(1);
564
565 I915_WRITE(D_STATE, I915_READ(D_STATE) & ~DSTATE_GFX_RESET_I830);
566 POSTING_READ(D_STATE);
567
568 return 0;
569}
570
f49f0586
KG		 571static int i965_reset_complete(struct drm_device *dev)
572{
573 u8 gdrst;
eeccdcac 574 pci_read_config_byte(dev->pdev, I965_GDRST, &gdrst);
f49f0586
KG		 575 return gdrst & 0x1;
576}
577
0573ed4a
KG		 578static int i965_do_reset(struct drm_device *dev, u8 flags)
579{
580 u8 gdrst;
581
ae681d96
CW		 582 /*
583 * Set the domains we want to reset (GRDOM/bits 2 and 3) as
584 * well as the reset bit (GR/bit 0). Setting the GR bit
585 * triggers the reset; when done, the hardware will clear it.
586 */
0573ed4a
KG		 587 pci_read_config_byte(dev->pdev, I965_GDRST, &gdrst);
588 pci_write_config_byte(dev->pdev, I965_GDRST, gdrst | flags | 0x1);
589
590 return wait_for(i965_reset_complete(dev), 500);
591}
592
593static int ironlake_do_reset(struct drm_device *dev, u8 flags)
594{
595 struct drm_i915_private *dev_priv = dev->dev_private;
596 u32 gdrst = I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR);
597 I915_WRITE(MCHBAR_MIRROR_BASE + ILK_GDSR, gdrst | flags | 0x1);
598 return wait_for(I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR) & 0x1, 500);
ba8bbcf6
JB		 599}
600
cff458c2
EA		 601static int gen6_do_reset(struct drm_device *dev, u8 flags)
602{
603 struct drm_i915_private *dev_priv = dev->dev_private;
604
605 I915_WRITE(GEN6_GDRST, GEN6_GRDOM_FULL);
606 return wait_for((I915_READ(GEN6_GDRST) & GEN6_GRDOM_FULL) == 0, 500);
607}
608
11ed50ec 609/**
f3953dcb 610 * i915_reset - reset chip after a hang
11ed50ec
BG		 611 * @dev: drm device to reset
612 * @flags: reset domains
613 *
614 * Reset the chip. Useful if a hang is detected. Returns zero on successful
615 * reset or otherwise an error code.
616 *
617 * Procedure is fairly simple:
618 * - reset the chip using the reset reg
619 * - re-init context state
620 * - re-init hardware status page
621 * - re-init ring buffer
622 * - re-init interrupt state
623 * - re-init display
624 */
f803aa55 625int i915_reset(struct drm_device *dev, u8 flags)
11ed50ec
BG		 626{
627 drm_i915_private_t *dev_priv = dev->dev_private;
11ed50ec
BG		 628 /*
629 * We really should only reset the display subsystem if we actually
630 * need to
631 */
632 bool need_display = true;
0573ed4a 633 int ret;
11ed50ec 634
d78cb50b
CW		 635 if (!i915_try_reset)
636 return 0;
637
340479aa
CW		 638 if (!mutex_trylock(&dev->struct_mutex))
639 return -EBUSY;
11ed50ec 640
069efc1d 641 i915_gem_reset(dev);
77f01230 642
f803aa55 643 ret = -ENODEV;
ae681d96
CW		 644 if (get_seconds() - dev_priv->last_gpu_reset < 5) {
645 DRM_ERROR("GPU hanging too fast, declaring wedged!\n");
646 } else switch (INTEL_INFO(dev)->gen) {
1083694a 647 case 7:
cff458c2
EA		 648 case 6:
649 ret = gen6_do_reset(dev, flags);
25732821
BW		 650 /* If reset with a user forcewake, try to restore */
651 if (atomic_read(&dev_priv->forcewake_count))
652 __gen6_gt_force_wake_get(dev_priv);
cff458c2 653 break;
f803aa55 654 case 5:
0573ed4a 655 ret = ironlake_do_reset(dev, flags);
f803aa55
CW		 656 break;
657 case 4:
0573ed4a 658 ret = i965_do_reset(dev, flags);
f803aa55 659 break;
dc96e9b8
CW		 660 case 2:
661 ret = i8xx_do_reset(dev, flags);
662 break;
f803aa55 663 }
ae681d96 664 dev_priv->last_gpu_reset = get_seconds();
0573ed4a 665 if (ret) {
f803aa55 666 DRM_ERROR("Failed to reset chip.\n");
f953c935 667 mutex_unlock(&dev->struct_mutex);
f803aa55 668 return ret;
11ed50ec
BG		 669 }
670
671 /* Ok, now get things going again... */
672
673 /*
674 * Everything depends on having the GTT running, so we need to start
675 * there. Fortunately we don't need to do this unless we reset the
676 * chip at a PCI level.
677 *
678 * Next we need to restore the context, but we don't use those
679 * yet either...
680 *
681 * Ring buffer needs to be re-initialized in the KMS case, or if X
682 * was running at the time of the reset (i.e. we weren't VT
683 * switched away).
684 */
685 if (drm_core_check_feature(dev, DRIVER_MODESET) ||
8187a2b7 686 !dev_priv->mm.suspended) {
11ed50ec 687 dev_priv->mm.suspended = 0;
75a6898f 688
f691e2f4
DV		 689 i915_gem_init_swizzling(dev);
690
1ec14ad3 691 dev_priv->ring[RCS].init(&dev_priv->ring[RCS]);
75a6898f 692 if (HAS_BSD(dev))
1ec14ad3 693 dev_priv->ring[VCS].init(&dev_priv->ring[VCS]);
75a6898f 694 if (HAS_BLT(dev))
1ec14ad3 695 dev_priv->ring[BCS].init(&dev_priv->ring[BCS]);
75a6898f 696
11ed50ec
BG		 697 mutex_unlock(&dev->struct_mutex);
698 drm_irq_uninstall(dev);
500f7147 699 drm_mode_config_reset(dev);
11ed50ec
BG		 700 drm_irq_install(dev);
701 mutex_lock(&dev->struct_mutex);
702 }
703
9fd98141
CW		 704 mutex_unlock(&dev->struct_mutex);
705
11ed50ec 706 /*
9fd98141
CW		 707 * Perform a full modeset as on later generations, e.g. Ironlake, we may
708 * need to retrain the display link and cannot just restore the register
709 * values.
11ed50ec 710 */
9fd98141
CW		 711 if (need_display) {
712 mutex_lock(&dev->mode_config.mutex);
713 drm_helper_resume_force_mode(dev);
714 mutex_unlock(&dev->mode_config.mutex);
715 }
11ed50ec 716
11ed50ec
BG		 717 return 0;
718}
719
720
112b715e
KH		 721static int __devinit
722i915_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
723{
5fe49d86
CW		 724 /* Only bind to function 0 of the device. Early generations
725 * used function 1 as a placeholder for multi-head. This causes
726 * us confusion instead, especially on the systems where both
727 * functions have the same PCI-ID!
728 */
729 if (PCI_FUNC(pdev->devfn))
730 return -ENODEV;
731
dcdb1674 732 return drm_get_pci_dev(pdev, ent, &driver);
112b715e
KH		 733}
734
735static void
736i915_pci_remove(struct pci_dev *pdev)
737{
738 struct drm_device *dev = pci_get_drvdata(pdev);
739
740 drm_put_dev(dev);
741}
742
84b79f8d 743static int i915_pm_suspend(struct device *dev)
112b715e 744{
84b79f8d
RW		 745 struct pci_dev *pdev = to_pci_dev(dev);
746 struct drm_device *drm_dev = pci_get_drvdata(pdev);
747 int error;
112b715e 748
84b79f8d
RW		 749 if (!drm_dev || !drm_dev->dev_private) {
750 dev_err(dev, "DRM not initialized, aborting suspend.\n");
751 return -ENODEV;
752 }
112b715e 753
5bcf719b
DA		 754 if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF)
755 return 0;
756
84b79f8d
RW		 757 error = i915_drm_freeze(drm_dev);
758 if (error)
759 return error;
112b715e 760
84b79f8d
RW		 761 pci_disable_device(pdev);
762 pci_set_power_state(pdev, PCI_D3hot);
cbda12d7 763
84b79f8d 764 return 0;
cbda12d7
ZW		 765}
766
84b79f8d 767static int i915_pm_resume(struct device *dev)
cbda12d7 768{
84b79f8d
RW		 769 struct pci_dev *pdev = to_pci_dev(dev);
770 struct drm_device *drm_dev = pci_get_drvdata(pdev);
771
772 return i915_resume(drm_dev);
cbda12d7
ZW		 773}
774
84b79f8d 775static int i915_pm_freeze(struct device *dev)
cbda12d7 776{
84b79f8d
RW		 777 struct pci_dev *pdev = to_pci_dev(dev);
778 struct drm_device *drm_dev = pci_get_drvdata(pdev);
779
780 if (!drm_dev || !drm_dev->dev_private) {
781 dev_err(dev, "DRM not initialized, aborting suspend.\n");
782 return -ENODEV;
783 }
784
785 return i915_drm_freeze(drm_dev);
cbda12d7
ZW		 786}
787
84b79f8d 788static int i915_pm_thaw(struct device *dev)
cbda12d7 789{
84b79f8d
RW		 790 struct pci_dev *pdev = to_pci_dev(dev);
791 struct drm_device *drm_dev = pci_get_drvdata(pdev);
792
793 return i915_drm_thaw(drm_dev);
cbda12d7
ZW		 794}
795
84b79f8d 796static int i915_pm_poweroff(struct device *dev)
cbda12d7 797{
84b79f8d
RW		 798 struct pci_dev *pdev = to_pci_dev(dev);
799 struct drm_device *drm_dev = pci_get_drvdata(pdev);
84b79f8d 800
61caf87c 801 return i915_drm_freeze(drm_dev);
cbda12d7
ZW		 802}
803
b4b78d12 804static const struct dev_pm_ops i915_pm_ops = {
0206e353
AJ		 805 .suspend = i915_pm_suspend,
806 .resume = i915_pm_resume,
807 .freeze = i915_pm_freeze,
808 .thaw = i915_pm_thaw,
809 .poweroff = i915_pm_poweroff,
810 .restore = i915_pm_resume,
cbda12d7
ZW		 811};
812
de151cf6
JB		 813static struct vm_operations_struct i915_gem_vm_ops = {
814 .fault = i915_gem_fault,
ab00b3e5
JB		 815 .open = drm_gem_vm_open,
816 .close = drm_gem_vm_close,
de151cf6
JB		 817};
818
e08e96de
AV		 819static const struct file_operations i915_driver_fops = {
820 .owner = THIS_MODULE,
821 .open = drm_open,
822 .release = drm_release,
823 .unlocked_ioctl = drm_ioctl,
824 .mmap = drm_gem_mmap,
825 .poll = drm_poll,
826 .fasync = drm_fasync,
827 .read = drm_read,
828#ifdef CONFIG_COMPAT
829 .compat_ioctl = i915_compat_ioctl,
830#endif
831 .llseek = noop_llseek,
832};
833
1da177e4 834static struct drm_driver driver = {
0c54781b
MW		 835 /* Don't use MTRRs here; the Xserver or userspace app should
836 * deal with them for Intel hardware.
792d2b9a 837 */
673a394b
EA		 838 .driver_features =
839 DRIVER_USE_AGP | DRIVER_REQUIRE_AGP | /* DRIVER_USE_MTRR |*/
840 DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM,
22eae947 841 .load = i915_driver_load,
ba8bbcf6 842 .unload = i915_driver_unload,
673a394b 843 .open = i915_driver_open,
22eae947
DA		 844 .lastclose = i915_driver_lastclose,
845 .preclose = i915_driver_preclose,
673a394b 846 .postclose = i915_driver_postclose,
d8e29209
RW		 847
848 /* Used in place of i915_pm_ops for non-DRIVER_MODESET */
849 .suspend = i915_suspend,
850 .resume = i915_resume,
851
cda17380 852 .device_is_agp = i915_driver_device_is_agp,
1da177e4 853 .reclaim_buffers = drm_core_reclaim_buffers,
7c1c2871
DA		 854 .master_create = i915_master_create,
855 .master_destroy = i915_master_destroy,
955b12de 856#if defined(CONFIG_DEBUG_FS)
27c202ad
BG		 857 .debugfs_init = i915_debugfs_init,
858 .debugfs_cleanup = i915_debugfs_cleanup,
955b12de 859#endif
673a394b
EA		 860 .gem_init_object = i915_gem_init_object,
861 .gem_free_object = i915_gem_free_object,
de151cf6 862 .gem_vm_ops = &i915_gem_vm_ops,
ff72145b
DA		 863 .dumb_create = i915_gem_dumb_create,
864 .dumb_map_offset = i915_gem_mmap_gtt,
865 .dumb_destroy = i915_gem_dumb_destroy,
1da177e4 866 .ioctls = i915_ioctls,
e08e96de 867 .fops = &i915_driver_fops,
22eae947
DA		 868 .name = DRIVER_NAME,
869 .desc = DRIVER_DESC,
870 .date = DRIVER_DATE,
871 .major = DRIVER_MAJOR,
872 .minor = DRIVER_MINOR,
873 .patchlevel = DRIVER_PATCHLEVEL,
1da177e4
LT		 874};
875
8410ea3b
DA		 876static struct pci_driver i915_pci_driver = {
877 .name = DRIVER_NAME,
878 .id_table = pciidlist,
879 .probe = i915_pci_probe,
880 .remove = i915_pci_remove,
881 .driver.pm = &i915_pm_ops,
882};
883
1da177e4
LT		 884static int __init i915_init(void)
885{
1f7a6e37
ZW		 886 if (!intel_agp_enabled) {
887 DRM_ERROR("drm/i915 can't work without intel_agp module!\n");
888 return -ENODEV;
889 }
890
1da177e4 891 driver.num_ioctls = i915_max_ioctl;
79e53945
JB		 892
893 /*
894 * If CONFIG_DRM_I915_KMS is set, default to KMS unless
895 * explicitly disabled with the module pararmeter.
896 *
897 * Otherwise, just follow the parameter (defaulting to off).
898 *
899 * Allow optional vga_text_mode_force boot option to override
900 * the default behavior.
901 */
902#if defined(CONFIG_DRM_I915_KMS)
903 if (i915_modeset != 0)
904 driver.driver_features |= DRIVER_MODESET;
905#endif
906 if (i915_modeset == 1)
907 driver.driver_features |= DRIVER_MODESET;
908
909#ifdef CONFIG_VGA_CONSOLE
910 if (vgacon_text_force() && i915_modeset == -1)
911 driver.driver_features &= ~DRIVER_MODESET;
912#endif
913
3885c6bb
CW		 914 if (!(driver.driver_features & DRIVER_MODESET))
915 driver.get_vblank_timestamp = NULL;
916
8410ea3b 917 return drm_pci_init(&driver, &i915_pci_driver);
1da177e4
LT		 918}
919
920static void __exit i915_exit(void)
921{
8410ea3b 922 drm_pci_exit(&driver, &i915_pci_driver);
1da177e4
LT		 923}
924
925module_init(i915_init);
926module_exit(i915_exit);
927
b5e89ed5
DA		 928MODULE_AUTHOR(DRIVER_AUTHOR);
929MODULE_DESCRIPTION(DRIVER_DESC);
1da177e4 930MODULE_LICENSE("GPL and additional rights");
f7000883 931
f7000883
AK		 932#define __i915_read(x, y) \
933u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg) { \
934 u##x val = 0; \
935 if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
936 gen6_gt_force_wake_get(dev_priv); \
937 val = read##y(dev_priv->regs + reg); \
938 gen6_gt_force_wake_put(dev_priv); \
939 } else { \
940 val = read##y(dev_priv->regs + reg); \
941 } \
942 trace_i915_reg_rw(false, reg, val, sizeof(val)); \
943 return val; \
944}
945
946__i915_read(8, b)
947__i915_read(16, w)
948__i915_read(32, l)
949__i915_read(64, q)
950#undef __i915_read
951
952#define __i915_write(x, y) \
953void i915_write##x(struct drm_i915_private *dev_priv, u32 reg, u##x val) { \
954 trace_i915_reg_rw(true, reg, val, sizeof(val)); \
955 if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
956 __gen6_gt_wait_for_fifo(dev_priv); \
957 } \
958 write##y(val, dev_priv->regs + reg); \
959}
960__i915_write(8, b)
961__i915_write(16, w)
962__i915_write(32, l)
963__i915_write(64, q)
964#undef __i915_write
Linux kernel - Deliverables
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