drm/i915: Implement IS_* macros using static tables
[deliverable/linux.git] / drivers / gpu / drm / i915 / i915_drv.c
CommitLineData
1da177e4
LT
1/* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*-
2 */
0d6aa60b 3/*
bc54fd1a 4 *
1da177e4
LT
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
6 * All Rights Reserved.
bc54fd1a
DA
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
15 *
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
18 * of the Software.
19 *
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27 *
0d6aa60b 28 */
1da177e4 29
5669fcac 30#include <linux/device.h>
1da177e4
LT
31#include "drmP.h"
32#include "drm.h"
33#include "i915_drm.h"
34#include "i915_drv.h"
35
79e53945 36#include <linux/console.h>
354ff967 37#include "drm_crtc_helper.h"
79e53945 38
d6073d77 39static int i915_modeset = -1;
79e53945
JB
40module_param_named(modeset, i915_modeset, int, 0400);
41
42unsigned int i915_fbpercrtc = 0;
43module_param_named(fbpercrtc, i915_fbpercrtc, int, 0400);
1da177e4 44
652c393a
JB
45unsigned int i915_powersave = 1;
46module_param_named(powersave, i915_powersave, int, 0400);
47
112b715e
KH
48static struct drm_driver driver;
49
cfdf1fa2 50#define INTEL_VGA_DEVICE(id, info) { \
49ae35f2
KH
51 .class = PCI_CLASS_DISPLAY_VGA << 8, \
52 .class_mask = 0xffff00, \
53 .vendor = 0x8086, \
54 .device = id, \
55 .subvendor = PCI_ANY_ID, \
56 .subdevice = PCI_ANY_ID, \
cfdf1fa2
KH
57 .driver_data = (unsigned long) info }
58
59const static struct intel_device_info intel_i830_info = {
60 .is_i8xx = 1, .is_mobile = 1,
61};
62
63const static struct intel_device_info intel_845g_info = {
64 .is_i8xx = 1,
65};
66
67const static struct intel_device_info intel_i85x_info = {
68 .is_i8xx = 1, .is_mobile = 1,
69};
70
71const static struct intel_device_info intel_i865g_info = {
72 .is_i8xx = 1,
73};
74
75const static struct intel_device_info intel_i915g_info = {
76 .is_i915g = 1, .is_i9xx = 1,
77};
78const static struct intel_device_info intel_i915gm_info = {
79 .is_i9xx = 1, .is_mobile = 1, .has_fbc = 1,
80};
81const static struct intel_device_info intel_i945g_info = {
82 .is_i9xx = 1, .has_hotplug = 1,
83};
84const static struct intel_device_info intel_i945gm_info = {
85 .is_i945gm = 1, .is_i9xx = 1, .is_mobile = 1, .has_fbc = 1,
86 .has_hotplug = 1,
87};
88
89const static struct intel_device_info intel_i965g_info = {
90 .is_i965g = 1, .is_i9xx = 1, .has_hotplug = 1,
91};
92
93const static struct intel_device_info intel_i965gm_info = {
94 .is_i965g = 1, .is_mobile = 1, .is_i965gm = 1, .is_i9xx = 1,
95 .is_mobile = 1, .has_fbc = 1, .has_rc6 = 1,
96 .has_hotplug = 1,
97};
98
99const static struct intel_device_info intel_g33_info = {
100 .is_g33 = 1, .is_i9xx = 1, .need_gfx_hws = 1,
101 .has_hotplug = 1,
102};
103
104const static struct intel_device_info intel_g45_info = {
105 .is_i965g = 1, .is_g4x = 1, .is_i9xx = 1, .need_gfx_hws = 1,
106 .has_pipe_cxsr = 1,
107 .has_hotplug = 1,
108};
109
110const static struct intel_device_info intel_gm45_info = {
111 .is_i965g = 1, .is_mobile = 1, .is_g4x = 1, .is_i9xx = 1,
112 .is_mobile = 1, .need_gfx_hws = 1, .has_fbc = 1, .has_rc6 = 1,
113 .has_pipe_cxsr = 1,
114 .has_hotplug = 1,
115};
116
117const static struct intel_device_info intel_pineview_info = {
118 .is_g33 = 1, .is_pineview = 1, .is_mobile = 1, .is_i9xx = 1,
119 .has_pipe_cxsr = 1,
120 .has_hotplug = 1,
121};
122
123const static struct intel_device_info intel_ironlake_d_info = {
124 .is_ironlake = 1, .is_i965g = 1, .is_i9xx = 1, .need_gfx_hws = 1,
125 .has_pipe_cxsr = 1,
126 .has_hotplug = 1,
127};
128
129const static struct intel_device_info intel_ironlake_m_info = {
130 .is_ironlake = 1, .is_mobile = 1, .is_i965g = 1, .is_i9xx = 1,
131 .need_gfx_hws = 1, .has_rc6 = 1,
132 .has_hotplug = 1,
133};
134
135const static struct pci_device_id pciidlist[] = {
136 INTEL_VGA_DEVICE(0x3577, &intel_i830_info),
137 INTEL_VGA_DEVICE(0x2562, &intel_845g_info),
138 INTEL_VGA_DEVICE(0x3582, &intel_i85x_info),
139 INTEL_VGA_DEVICE(0x35e8, &intel_i85x_info),
140 INTEL_VGA_DEVICE(0x2572, &intel_i865g_info),
141 INTEL_VGA_DEVICE(0x2582, &intel_i915g_info),
142 INTEL_VGA_DEVICE(0x258a, &intel_i915g_info),
143 INTEL_VGA_DEVICE(0x2592, &intel_i915gm_info),
144 INTEL_VGA_DEVICE(0x2772, &intel_i945g_info),
145 INTEL_VGA_DEVICE(0x27a2, &intel_i945gm_info),
146 INTEL_VGA_DEVICE(0x27ae, &intel_i945gm_info),
147 INTEL_VGA_DEVICE(0x2972, &intel_i965g_info),
148 INTEL_VGA_DEVICE(0x2982, &intel_i965g_info),
149 INTEL_VGA_DEVICE(0x2992, &intel_i965g_info),
150 INTEL_VGA_DEVICE(0x29a2, &intel_i965g_info),
151 INTEL_VGA_DEVICE(0x29b2, &intel_g33_info),
152 INTEL_VGA_DEVICE(0x29c2, &intel_g33_info),
153 INTEL_VGA_DEVICE(0x29d2, &intel_g33_info),
154 INTEL_VGA_DEVICE(0x2a02, &intel_i965gm_info),
155 INTEL_VGA_DEVICE(0x2a12, &intel_i965gm_info),
156 INTEL_VGA_DEVICE(0x2a42, &intel_gm45_info),
157 INTEL_VGA_DEVICE(0x2e02, &intel_g45_info),
158 INTEL_VGA_DEVICE(0x2e12, &intel_g45_info),
159 INTEL_VGA_DEVICE(0x2e22, &intel_g45_info),
160 INTEL_VGA_DEVICE(0x2e32, &intel_g45_info),
161 INTEL_VGA_DEVICE(0x2e42, &intel_g45_info),
162 INTEL_VGA_DEVICE(0xa001, &intel_pineview_info),
163 INTEL_VGA_DEVICE(0xa011, &intel_pineview_info),
164 INTEL_VGA_DEVICE(0x0042, &intel_ironlake_d_info),
165 INTEL_VGA_DEVICE(0x0046, &intel_ironlake_m_info),
49ae35f2 166 {0, 0, 0}
1da177e4
LT
167};
168
79e53945
JB
169#if defined(CONFIG_DRM_I915_KMS)
170MODULE_DEVICE_TABLE(pci, pciidlist);
171#endif
172
b932ccb5 173static int i915_suspend(struct drm_device *dev, pm_message_t state)
ba8bbcf6
JB
174{
175 struct drm_i915_private *dev_priv = dev->dev_private;
ba8bbcf6
JB
176
177 if (!dev || !dev_priv) {
1ae8c0a5
KP
178 DRM_ERROR("dev: %p, dev_priv: %p\n", dev, dev_priv);
179 DRM_ERROR("DRM not initialized, aborting suspend.\n");
ba8bbcf6
JB
180 return -ENODEV;
181 }
182
b932ccb5
DA
183 if (state.event == PM_EVENT_PRETHAW)
184 return 0;
185
ba8bbcf6 186 pci_save_state(dev->pdev);
ba8bbcf6 187
5669fcac 188 /* If KMS is active, we do the leavevt stuff here */
226485e9
JB
189 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
190 if (i915_gem_idle(dev))
191 dev_err(&dev->pdev->dev,
192 "GEM idle failed, resume may fail\n");
193 drm_irq_uninstall(dev);
5669fcac
JB
194 }
195
9e06dd39
JB
196 i915_save_state(dev);
197
3b1c1c11 198 intel_opregion_free(dev, 1);
8ee1c3db 199
b932ccb5
DA
200 if (state.event == PM_EVENT_SUSPEND) {
201 /* Shut down the device */
202 pci_disable_device(dev->pdev);
203 pci_set_power_state(dev->pdev, PCI_D3hot);
204 }
ba8bbcf6 205
c9354c85
LT
206 /* Modeset on resume, not lid events */
207 dev_priv->modeset_on_lid = 0;
06891e27 208
ba8bbcf6
JB
209 return 0;
210}
211
212static int i915_resume(struct drm_device *dev)
213{
5669fcac
JB
214 struct drm_i915_private *dev_priv = dev->dev_private;
215 int ret = 0;
216
ba8bbcf6
JB
217 if (pci_enable_device(dev->pdev))
218 return -1;
ea7b44c8 219 pci_set_master(dev->pdev);
ba8bbcf6 220
317c35d1 221 i915_restore_state(dev);
ba8bbcf6 222
74a365b3 223 intel_opregion_init(dev, 1);
8ee1c3db 224
5669fcac
JB
225 /* KMS EnterVT equivalent */
226 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
227 mutex_lock(&dev->struct_mutex);
228 dev_priv->mm.suspended = 0;
229
230 ret = i915_gem_init_ringbuffer(dev);
231 if (ret != 0)
232 ret = -1;
233 mutex_unlock(&dev->struct_mutex);
226485e9
JB
234
235 drm_irq_install(dev);
5669fcac 236 }
354ff967
ZY
237 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
238 /* Resume the modeset for every activated CRTC */
239 drm_helper_resume_force_mode(dev);
240 }
5669fcac 241
c9354c85 242 dev_priv->modeset_on_lid = 0;
06891e27 243
5669fcac 244 return ret;
ba8bbcf6
JB
245}
246
11ed50ec
BG
247/**
248 * i965_reset - reset chip after a hang
249 * @dev: drm device to reset
250 * @flags: reset domains
251 *
252 * Reset the chip. Useful if a hang is detected. Returns zero on successful
253 * reset or otherwise an error code.
254 *
255 * Procedure is fairly simple:
256 * - reset the chip using the reset reg
257 * - re-init context state
258 * - re-init hardware status page
259 * - re-init ring buffer
260 * - re-init interrupt state
261 * - re-init display
262 */
263int i965_reset(struct drm_device *dev, u8 flags)
264{
265 drm_i915_private_t *dev_priv = dev->dev_private;
266 unsigned long timeout;
267 u8 gdrst;
268 /*
269 * We really should only reset the display subsystem if we actually
270 * need to
271 */
272 bool need_display = true;
273
274 mutex_lock(&dev->struct_mutex);
275
276 /*
277 * Clear request list
278 */
279 i915_gem_retire_requests(dev);
280
281 if (need_display)
282 i915_save_display(dev);
283
284 if (IS_I965G(dev) || IS_G4X(dev)) {
285 /*
286 * Set the domains we want to reset, then the reset bit (bit 0).
287 * Clear the reset bit after a while and wait for hardware status
288 * bit (bit 1) to be set
289 */
290 pci_read_config_byte(dev->pdev, GDRST, &gdrst);
291 pci_write_config_byte(dev->pdev, GDRST, gdrst | flags | ((flags == GDRST_FULL) ? 0x1 : 0x0));
292 udelay(50);
293 pci_write_config_byte(dev->pdev, GDRST, gdrst & 0xfe);
294
295 /* ...we don't want to loop forever though, 500ms should be plenty */
296 timeout = jiffies + msecs_to_jiffies(500);
297 do {
298 udelay(100);
299 pci_read_config_byte(dev->pdev, GDRST, &gdrst);
300 } while ((gdrst & 0x1) && time_after(timeout, jiffies));
301
302 if (gdrst & 0x1) {
303 WARN(true, "i915: Failed to reset chip\n");
304 mutex_unlock(&dev->struct_mutex);
305 return -EIO;
306 }
307 } else {
308 DRM_ERROR("Error occurred. Don't know how to reset this chip.\n");
309 return -ENODEV;
310 }
311
312 /* Ok, now get things going again... */
313
314 /*
315 * Everything depends on having the GTT running, so we need to start
316 * there. Fortunately we don't need to do this unless we reset the
317 * chip at a PCI level.
318 *
319 * Next we need to restore the context, but we don't use those
320 * yet either...
321 *
322 * Ring buffer needs to be re-initialized in the KMS case, or if X
323 * was running at the time of the reset (i.e. we weren't VT
324 * switched away).
325 */
326 if (drm_core_check_feature(dev, DRIVER_MODESET) ||
327 !dev_priv->mm.suspended) {
328 drm_i915_ring_buffer_t *ring = &dev_priv->ring;
329 struct drm_gem_object *obj = ring->ring_obj;
330 struct drm_i915_gem_object *obj_priv = obj->driver_private;
331 dev_priv->mm.suspended = 0;
332
333 /* Stop the ring if it's running. */
334 I915_WRITE(PRB0_CTL, 0);
335 I915_WRITE(PRB0_TAIL, 0);
336 I915_WRITE(PRB0_HEAD, 0);
337
338 /* Initialize the ring. */
339 I915_WRITE(PRB0_START, obj_priv->gtt_offset);
340 I915_WRITE(PRB0_CTL,
341 ((obj->size - 4096) & RING_NR_PAGES) |
342 RING_NO_REPORT |
343 RING_VALID);
344 if (!drm_core_check_feature(dev, DRIVER_MODESET))
345 i915_kernel_lost_context(dev);
346 else {
347 ring->head = I915_READ(PRB0_HEAD) & HEAD_ADDR;
348 ring->tail = I915_READ(PRB0_TAIL) & TAIL_ADDR;
349 ring->space = ring->head - (ring->tail + 8);
350 if (ring->space < 0)
351 ring->space += ring->Size;
352 }
353
354 mutex_unlock(&dev->struct_mutex);
355 drm_irq_uninstall(dev);
356 drm_irq_install(dev);
357 mutex_lock(&dev->struct_mutex);
358 }
359
360 /*
361 * Display needs restore too...
362 */
363 if (need_display)
364 i915_restore_display(dev);
365
366 mutex_unlock(&dev->struct_mutex);
367 return 0;
368}
369
370
112b715e
KH
371static int __devinit
372i915_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
373{
374 return drm_get_dev(pdev, ent, &driver);
375}
376
377static void
378i915_pci_remove(struct pci_dev *pdev)
379{
380 struct drm_device *dev = pci_get_drvdata(pdev);
381
382 drm_put_dev(dev);
383}
384
385static int
386i915_pci_suspend(struct pci_dev *pdev, pm_message_t state)
387{
388 struct drm_device *dev = pci_get_drvdata(pdev);
389
390 return i915_suspend(dev, state);
391}
392
393static int
394i915_pci_resume(struct pci_dev *pdev)
395{
396 struct drm_device *dev = pci_get_drvdata(pdev);
397
398 return i915_resume(dev);
399}
400
cbda12d7
ZW
401static int
402i915_pm_suspend(struct device *dev)
403{
404 return i915_pci_suspend(to_pci_dev(dev), PMSG_SUSPEND);
405}
406
407static int
408i915_pm_resume(struct device *dev)
409{
410 return i915_pci_resume(to_pci_dev(dev));
411}
412
413static int
414i915_pm_freeze(struct device *dev)
415{
416 return i915_pci_suspend(to_pci_dev(dev), PMSG_FREEZE);
417}
418
419static int
420i915_pm_thaw(struct device *dev)
421{
422 /* thaw during hibernate, do nothing! */
423 return 0;
424}
425
426static int
427i915_pm_poweroff(struct device *dev)
428{
429 return i915_pci_suspend(to_pci_dev(dev), PMSG_HIBERNATE);
430}
431
432static int
433i915_pm_restore(struct device *dev)
434{
435 return i915_pci_resume(to_pci_dev(dev));
436}
437
438const struct dev_pm_ops i915_pm_ops = {
439 .suspend = i915_pm_suspend,
440 .resume = i915_pm_resume,
441 .freeze = i915_pm_freeze,
442 .thaw = i915_pm_thaw,
443 .poweroff = i915_pm_poweroff,
444 .restore = i915_pm_restore,
445};
446
de151cf6
JB
447static struct vm_operations_struct i915_gem_vm_ops = {
448 .fault = i915_gem_fault,
ab00b3e5
JB
449 .open = drm_gem_vm_open,
450 .close = drm_gem_vm_close,
de151cf6
JB
451};
452
1da177e4 453static struct drm_driver driver = {
792d2b9a
DA
454 /* don't use mtrr's here, the Xserver or user space app should
455 * deal with them for intel hardware.
456 */
673a394b
EA
457 .driver_features =
458 DRIVER_USE_AGP | DRIVER_REQUIRE_AGP | /* DRIVER_USE_MTRR |*/
459 DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM,
22eae947 460 .load = i915_driver_load,
ba8bbcf6 461 .unload = i915_driver_unload,
673a394b 462 .open = i915_driver_open,
22eae947
DA
463 .lastclose = i915_driver_lastclose,
464 .preclose = i915_driver_preclose,
673a394b 465 .postclose = i915_driver_postclose,
cda17380 466 .device_is_agp = i915_driver_device_is_agp,
0a3e67a4
JB
467 .enable_vblank = i915_enable_vblank,
468 .disable_vblank = i915_disable_vblank,
1da177e4
LT
469 .irq_preinstall = i915_driver_irq_preinstall,
470 .irq_postinstall = i915_driver_irq_postinstall,
471 .irq_uninstall = i915_driver_irq_uninstall,
472 .irq_handler = i915_driver_irq_handler,
473 .reclaim_buffers = drm_core_reclaim_buffers,
474 .get_map_ofs = drm_core_get_map_ofs,
475 .get_reg_ofs = drm_core_get_reg_ofs,
7c1c2871
DA
476 .master_create = i915_master_create,
477 .master_destroy = i915_master_destroy,
955b12de 478#if defined(CONFIG_DEBUG_FS)
27c202ad
BG
479 .debugfs_init = i915_debugfs_init,
480 .debugfs_cleanup = i915_debugfs_cleanup,
955b12de 481#endif
673a394b
EA
482 .gem_init_object = i915_gem_init_object,
483 .gem_free_object = i915_gem_free_object,
de151cf6 484 .gem_vm_ops = &i915_gem_vm_ops,
1da177e4
LT
485 .ioctls = i915_ioctls,
486 .fops = {
b5e89ed5
DA
487 .owner = THIS_MODULE,
488 .open = drm_open,
489 .release = drm_release,
490 .ioctl = drm_ioctl,
de151cf6 491 .mmap = drm_gem_mmap,
b5e89ed5
DA
492 .poll = drm_poll,
493 .fasync = drm_fasync,
c9a9c5e0 494 .read = drm_read,
8ca7c1df 495#ifdef CONFIG_COMPAT
b5e89ed5 496 .compat_ioctl = i915_compat_ioctl,
8ca7c1df 497#endif
22eae947
DA
498 },
499
1da177e4 500 .pci_driver = {
22eae947
DA
501 .name = DRIVER_NAME,
502 .id_table = pciidlist,
112b715e
KH
503 .probe = i915_pci_probe,
504 .remove = i915_pci_remove,
cbda12d7 505 .driver.pm = &i915_pm_ops,
22eae947 506 },
bc5f4523 507
22eae947
DA
508 .name = DRIVER_NAME,
509 .desc = DRIVER_DESC,
510 .date = DRIVER_DATE,
511 .major = DRIVER_MAJOR,
512 .minor = DRIVER_MINOR,
513 .patchlevel = DRIVER_PATCHLEVEL,
1da177e4
LT
514};
515
516static int __init i915_init(void)
517{
518 driver.num_ioctls = i915_max_ioctl;
79e53945 519
31169714
CW
520 i915_gem_shrinker_init();
521
79e53945
JB
522 /*
523 * If CONFIG_DRM_I915_KMS is set, default to KMS unless
524 * explicitly disabled with the module pararmeter.
525 *
526 * Otherwise, just follow the parameter (defaulting to off).
527 *
528 * Allow optional vga_text_mode_force boot option to override
529 * the default behavior.
530 */
531#if defined(CONFIG_DRM_I915_KMS)
532 if (i915_modeset != 0)
533 driver.driver_features |= DRIVER_MODESET;
534#endif
535 if (i915_modeset == 1)
536 driver.driver_features |= DRIVER_MODESET;
537
538#ifdef CONFIG_VGA_CONSOLE
539 if (vgacon_text_force() && i915_modeset == -1)
540 driver.driver_features &= ~DRIVER_MODESET;
541#endif
542
1da177e4
LT
543 return drm_init(&driver);
544}
545
546static void __exit i915_exit(void)
547{
31169714 548 i915_gem_shrinker_exit();
1da177e4
LT
549 drm_exit(&driver);
550}
551
552module_init(i915_init);
553module_exit(i915_exit);
554
b5e89ed5
DA
555MODULE_AUTHOR(DRIVER_AUTHOR);
556MODULE_DESCRIPTION(DRIVER_DESC);
1da177e4 557MODULE_LICENSE("GPL and additional rights");
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