Commit | Line | Data |
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1da177e4 LT |
1 | /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*- |
2 | */ | |
0d6aa60b | 3 | /* |
bc54fd1a | 4 | * |
1da177e4 LT |
5 | * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. |
6 | * All Rights Reserved. | |
bc54fd1a DA |
7 | * |
8 | * Permission is hereby granted, free of charge, to any person obtaining a | |
9 | * copy of this software and associated documentation files (the | |
10 | * "Software"), to deal in the Software without restriction, including | |
11 | * without limitation the rights to use, copy, modify, merge, publish, | |
12 | * distribute, sub license, and/or sell copies of the Software, and to | |
13 | * permit persons to whom the Software is furnished to do so, subject to | |
14 | * the following conditions: | |
15 | * | |
16 | * The above copyright notice and this permission notice (including the | |
17 | * next paragraph) shall be included in all copies or substantial portions | |
18 | * of the Software. | |
19 | * | |
20 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS | |
21 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
22 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. | |
23 | * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR | |
24 | * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, | |
25 | * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE | |
26 | * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. | |
27 | * | |
0d6aa60b | 28 | */ |
1da177e4 LT |
29 | |
30 | #ifndef _I915_DRV_H_ | |
31 | #define _I915_DRV_H_ | |
32 | ||
e9b73c67 | 33 | #include <uapi/drm/i915_drm.h> |
93b81f51 | 34 | #include <uapi/drm/drm_fourcc.h> |
e9b73c67 | 35 | |
0839ccb8 | 36 | #include <linux/io-mapping.h> |
f899fc64 | 37 | #include <linux/i2c.h> |
c167a6fc | 38 | #include <linux/i2c-algo-bit.h> |
aaa6fd2a | 39 | #include <linux/backlight.h> |
5cc9ed4b | 40 | #include <linux/hashtable.h> |
2911a35b | 41 | #include <linux/intel-iommu.h> |
742cbee8 | 42 | #include <linux/kref.h> |
9ee32fea | 43 | #include <linux/pm_qos.h> |
e73bdd20 CW |
44 | #include <linux/shmem_fs.h> |
45 | ||
46 | #include <drm/drmP.h> | |
47 | #include <drm/intel-gtt.h> | |
48 | #include <drm/drm_legacy.h> /* for struct drm_dma_handle */ | |
49 | #include <drm/drm_gem.h> | |
3b96a0b1 | 50 | #include <drm/drm_auth.h> |
e73bdd20 CW |
51 | |
52 | #include "i915_params.h" | |
53 | #include "i915_reg.h" | |
54 | ||
55 | #include "intel_bios.h" | |
ac7f11c6 | 56 | #include "intel_dpll_mgr.h" |
e73bdd20 CW |
57 | #include "intel_guc.h" |
58 | #include "intel_lrc.h" | |
59 | #include "intel_ringbuffer.h" | |
60 | ||
d501b1d2 | 61 | #include "i915_gem.h" |
e73bdd20 CW |
62 | #include "i915_gem_gtt.h" |
63 | #include "i915_gem_render_state.h" | |
585fb111 | 64 | |
0ad35fed ZW |
65 | #include "intel_gvt.h" |
66 | ||
1da177e4 LT |
67 | /* General customization: |
68 | */ | |
69 | ||
1da177e4 LT |
70 | #define DRIVER_NAME "i915" |
71 | #define DRIVER_DESC "Intel Graphics" | |
0b2c0582 | 72 | #define DRIVER_DATE "20160711" |
1da177e4 | 73 | |
c883ef1b | 74 | #undef WARN_ON |
5f77eeb0 DV |
75 | /* Many gcc seem to no see through this and fall over :( */ |
76 | #if 0 | |
77 | #define WARN_ON(x) ({ \ | |
78 | bool __i915_warn_cond = (x); \ | |
79 | if (__builtin_constant_p(__i915_warn_cond)) \ | |
80 | BUILD_BUG_ON(__i915_warn_cond); \ | |
81 | WARN(__i915_warn_cond, "WARN_ON(" #x ")"); }) | |
82 | #else | |
152b2262 | 83 | #define WARN_ON(x) WARN((x), "%s", "WARN_ON(" __stringify(x) ")") |
5f77eeb0 DV |
84 | #endif |
85 | ||
cd9bfacb | 86 | #undef WARN_ON_ONCE |
152b2262 | 87 | #define WARN_ON_ONCE(x) WARN_ONCE((x), "%s", "WARN_ON_ONCE(" __stringify(x) ")") |
cd9bfacb | 88 | |
5f77eeb0 DV |
89 | #define MISSING_CASE(x) WARN(1, "Missing switch case (%lu) in %s\n", \ |
90 | (long) (x), __func__); | |
c883ef1b | 91 | |
e2c719b7 RC |
92 | /* Use I915_STATE_WARN(x) and I915_STATE_WARN_ON() (rather than WARN() and |
93 | * WARN_ON()) for hw state sanity checks to check for unexpected conditions | |
94 | * which may not necessarily be a user visible problem. This will either | |
95 | * WARN() or DRM_ERROR() depending on the verbose_checks moduleparam, to | |
96 | * enable distros and users to tailor their preferred amount of i915 abrt | |
97 | * spam. | |
98 | */ | |
99 | #define I915_STATE_WARN(condition, format...) ({ \ | |
100 | int __ret_warn_on = !!(condition); \ | |
32753cb8 JL |
101 | if (unlikely(__ret_warn_on)) \ |
102 | if (!WARN(i915.verbose_state_checks, format)) \ | |
e2c719b7 | 103 | DRM_ERROR(format); \ |
e2c719b7 RC |
104 | unlikely(__ret_warn_on); \ |
105 | }) | |
106 | ||
152b2262 JL |
107 | #define I915_STATE_WARN_ON(x) \ |
108 | I915_STATE_WARN((x), "%s", "WARN_ON(" __stringify(x) ")") | |
c883ef1b | 109 | |
4fec15d1 ID |
110 | bool __i915_inject_load_failure(const char *func, int line); |
111 | #define i915_inject_load_failure() \ | |
112 | __i915_inject_load_failure(__func__, __LINE__) | |
113 | ||
42a8ca4c JN |
114 | static inline const char *yesno(bool v) |
115 | { | |
116 | return v ? "yes" : "no"; | |
117 | } | |
118 | ||
87ad3212 JN |
119 | static inline const char *onoff(bool v) |
120 | { | |
121 | return v ? "on" : "off"; | |
122 | } | |
123 | ||
317c35d1 | 124 | enum pipe { |
752aa88a | 125 | INVALID_PIPE = -1, |
317c35d1 JB |
126 | PIPE_A = 0, |
127 | PIPE_B, | |
9db4a9c7 | 128 | PIPE_C, |
a57c774a AK |
129 | _PIPE_EDP, |
130 | I915_MAX_PIPES = _PIPE_EDP | |
317c35d1 | 131 | }; |
9db4a9c7 | 132 | #define pipe_name(p) ((p) + 'A') |
317c35d1 | 133 | |
a5c961d1 PZ |
134 | enum transcoder { |
135 | TRANSCODER_A = 0, | |
136 | TRANSCODER_B, | |
137 | TRANSCODER_C, | |
a57c774a | 138 | TRANSCODER_EDP, |
4d1de975 JN |
139 | TRANSCODER_DSI_A, |
140 | TRANSCODER_DSI_C, | |
a57c774a | 141 | I915_MAX_TRANSCODERS |
a5c961d1 | 142 | }; |
da205630 JN |
143 | |
144 | static inline const char *transcoder_name(enum transcoder transcoder) | |
145 | { | |
146 | switch (transcoder) { | |
147 | case TRANSCODER_A: | |
148 | return "A"; | |
149 | case TRANSCODER_B: | |
150 | return "B"; | |
151 | case TRANSCODER_C: | |
152 | return "C"; | |
153 | case TRANSCODER_EDP: | |
154 | return "EDP"; | |
4d1de975 JN |
155 | case TRANSCODER_DSI_A: |
156 | return "DSI A"; | |
157 | case TRANSCODER_DSI_C: | |
158 | return "DSI C"; | |
da205630 JN |
159 | default: |
160 | return "<invalid>"; | |
161 | } | |
162 | } | |
a5c961d1 | 163 | |
4d1de975 JN |
164 | static inline bool transcoder_is_dsi(enum transcoder transcoder) |
165 | { | |
166 | return transcoder == TRANSCODER_DSI_A || transcoder == TRANSCODER_DSI_C; | |
167 | } | |
168 | ||
84139d1e | 169 | /* |
31409e97 MR |
170 | * I915_MAX_PLANES in the enum below is the maximum (across all platforms) |
171 | * number of planes per CRTC. Not all platforms really have this many planes, | |
172 | * which means some arrays of size I915_MAX_PLANES may have unused entries | |
173 | * between the topmost sprite plane and the cursor plane. | |
84139d1e | 174 | */ |
80824003 JB |
175 | enum plane { |
176 | PLANE_A = 0, | |
177 | PLANE_B, | |
9db4a9c7 | 178 | PLANE_C, |
31409e97 MR |
179 | PLANE_CURSOR, |
180 | I915_MAX_PLANES, | |
80824003 | 181 | }; |
9db4a9c7 | 182 | #define plane_name(p) ((p) + 'A') |
52440211 | 183 | |
d615a166 | 184 | #define sprite_name(p, s) ((p) * INTEL_INFO(dev)->num_sprites[(p)] + (s) + 'A') |
06da8da2 | 185 | |
2b139522 ED |
186 | enum port { |
187 | PORT_A = 0, | |
188 | PORT_B, | |
189 | PORT_C, | |
190 | PORT_D, | |
191 | PORT_E, | |
192 | I915_MAX_PORTS | |
193 | }; | |
194 | #define port_name(p) ((p) + 'A') | |
195 | ||
a09caddd | 196 | #define I915_NUM_PHYS_VLV 2 |
e4607fcf CML |
197 | |
198 | enum dpio_channel { | |
199 | DPIO_CH0, | |
200 | DPIO_CH1 | |
201 | }; | |
202 | ||
203 | enum dpio_phy { | |
204 | DPIO_PHY0, | |
205 | DPIO_PHY1 | |
206 | }; | |
207 | ||
b97186f0 PZ |
208 | enum intel_display_power_domain { |
209 | POWER_DOMAIN_PIPE_A, | |
210 | POWER_DOMAIN_PIPE_B, | |
211 | POWER_DOMAIN_PIPE_C, | |
212 | POWER_DOMAIN_PIPE_A_PANEL_FITTER, | |
213 | POWER_DOMAIN_PIPE_B_PANEL_FITTER, | |
214 | POWER_DOMAIN_PIPE_C_PANEL_FITTER, | |
215 | POWER_DOMAIN_TRANSCODER_A, | |
216 | POWER_DOMAIN_TRANSCODER_B, | |
217 | POWER_DOMAIN_TRANSCODER_C, | |
f52e353e | 218 | POWER_DOMAIN_TRANSCODER_EDP, |
4d1de975 JN |
219 | POWER_DOMAIN_TRANSCODER_DSI_A, |
220 | POWER_DOMAIN_TRANSCODER_DSI_C, | |
6331a704 PJ |
221 | POWER_DOMAIN_PORT_DDI_A_LANES, |
222 | POWER_DOMAIN_PORT_DDI_B_LANES, | |
223 | POWER_DOMAIN_PORT_DDI_C_LANES, | |
224 | POWER_DOMAIN_PORT_DDI_D_LANES, | |
225 | POWER_DOMAIN_PORT_DDI_E_LANES, | |
319be8ae ID |
226 | POWER_DOMAIN_PORT_DSI, |
227 | POWER_DOMAIN_PORT_CRT, | |
228 | POWER_DOMAIN_PORT_OTHER, | |
cdf8dd7f | 229 | POWER_DOMAIN_VGA, |
fbeeaa23 | 230 | POWER_DOMAIN_AUDIO, |
bd2bb1b9 | 231 | POWER_DOMAIN_PLLS, |
1407121a S |
232 | POWER_DOMAIN_AUX_A, |
233 | POWER_DOMAIN_AUX_B, | |
234 | POWER_DOMAIN_AUX_C, | |
235 | POWER_DOMAIN_AUX_D, | |
f0ab43e6 | 236 | POWER_DOMAIN_GMBUS, |
dfa57627 | 237 | POWER_DOMAIN_MODESET, |
baa70707 | 238 | POWER_DOMAIN_INIT, |
bddc7645 ID |
239 | |
240 | POWER_DOMAIN_NUM, | |
b97186f0 PZ |
241 | }; |
242 | ||
243 | #define POWER_DOMAIN_PIPE(pipe) ((pipe) + POWER_DOMAIN_PIPE_A) | |
244 | #define POWER_DOMAIN_PIPE_PANEL_FITTER(pipe) \ | |
245 | ((pipe) + POWER_DOMAIN_PIPE_A_PANEL_FITTER) | |
f52e353e ID |
246 | #define POWER_DOMAIN_TRANSCODER(tran) \ |
247 | ((tran) == TRANSCODER_EDP ? POWER_DOMAIN_TRANSCODER_EDP : \ | |
248 | (tran) + POWER_DOMAIN_TRANSCODER_A) | |
b97186f0 | 249 | |
1d843f9d EE |
250 | enum hpd_pin { |
251 | HPD_NONE = 0, | |
1d843f9d EE |
252 | HPD_TV = HPD_NONE, /* TV is known to be unreliable */ |
253 | HPD_CRT, | |
254 | HPD_SDVO_B, | |
255 | HPD_SDVO_C, | |
cc24fcdc | 256 | HPD_PORT_A, |
1d843f9d EE |
257 | HPD_PORT_B, |
258 | HPD_PORT_C, | |
259 | HPD_PORT_D, | |
26951caf | 260 | HPD_PORT_E, |
1d843f9d EE |
261 | HPD_NUM_PINS |
262 | }; | |
263 | ||
c91711f9 JN |
264 | #define for_each_hpd_pin(__pin) \ |
265 | for ((__pin) = (HPD_NONE + 1); (__pin) < HPD_NUM_PINS; (__pin)++) | |
266 | ||
5fcece80 JN |
267 | struct i915_hotplug { |
268 | struct work_struct hotplug_work; | |
269 | ||
270 | struct { | |
271 | unsigned long last_jiffies; | |
272 | int count; | |
273 | enum { | |
274 | HPD_ENABLED = 0, | |
275 | HPD_DISABLED = 1, | |
276 | HPD_MARK_DISABLED = 2 | |
277 | } state; | |
278 | } stats[HPD_NUM_PINS]; | |
279 | u32 event_bits; | |
280 | struct delayed_work reenable_work; | |
281 | ||
282 | struct intel_digital_port *irq_port[I915_MAX_PORTS]; | |
283 | u32 long_port_mask; | |
284 | u32 short_port_mask; | |
285 | struct work_struct dig_port_work; | |
286 | ||
84c8e096 L |
287 | struct work_struct poll_init_work; |
288 | bool poll_enabled; | |
289 | ||
5fcece80 JN |
290 | /* |
291 | * if we get a HPD irq from DP and a HPD irq from non-DP | |
292 | * the non-DP HPD could block the workqueue on a mode config | |
293 | * mutex getting, that userspace may have taken. However | |
294 | * userspace is waiting on the DP workqueue to run which is | |
295 | * blocked behind the non-DP one. | |
296 | */ | |
297 | struct workqueue_struct *dp_wq; | |
298 | }; | |
299 | ||
2a2d5482 CW |
300 | #define I915_GEM_GPU_DOMAINS \ |
301 | (I915_GEM_DOMAIN_RENDER | \ | |
302 | I915_GEM_DOMAIN_SAMPLER | \ | |
303 | I915_GEM_DOMAIN_COMMAND | \ | |
304 | I915_GEM_DOMAIN_INSTRUCTION | \ | |
305 | I915_GEM_DOMAIN_VERTEX) | |
62fdfeaf | 306 | |
055e393f DL |
307 | #define for_each_pipe(__dev_priv, __p) \ |
308 | for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes; (__p)++) | |
6831f3e3 VS |
309 | #define for_each_pipe_masked(__dev_priv, __p, __mask) \ |
310 | for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes; (__p)++) \ | |
311 | for_each_if ((__mask) & (1 << (__p))) | |
dd740780 DL |
312 | #define for_each_plane(__dev_priv, __pipe, __p) \ |
313 | for ((__p) = 0; \ | |
314 | (__p) < INTEL_INFO(__dev_priv)->num_sprites[(__pipe)] + 1; \ | |
315 | (__p)++) | |
3bdcfc0c DL |
316 | #define for_each_sprite(__dev_priv, __p, __s) \ |
317 | for ((__s) = 0; \ | |
318 | (__s) < INTEL_INFO(__dev_priv)->num_sprites[(__p)]; \ | |
319 | (__s)++) | |
9db4a9c7 | 320 | |
c3aeadc8 JN |
321 | #define for_each_port_masked(__port, __ports_mask) \ |
322 | for ((__port) = PORT_A; (__port) < I915_MAX_PORTS; (__port)++) \ | |
323 | for_each_if ((__ports_mask) & (1 << (__port))) | |
324 | ||
d79b814d | 325 | #define for_each_crtc(dev, crtc) \ |
91c8a326 | 326 | list_for_each_entry(crtc, &(dev)->mode_config.crtc_list, head) |
d79b814d | 327 | |
27321ae8 ML |
328 | #define for_each_intel_plane(dev, intel_plane) \ |
329 | list_for_each_entry(intel_plane, \ | |
91c8a326 | 330 | &(dev)->mode_config.plane_list, \ |
27321ae8 ML |
331 | base.head) |
332 | ||
c107acfe | 333 | #define for_each_intel_plane_mask(dev, intel_plane, plane_mask) \ |
91c8a326 CW |
334 | list_for_each_entry(intel_plane, \ |
335 | &(dev)->mode_config.plane_list, \ | |
c107acfe MR |
336 | base.head) \ |
337 | for_each_if ((plane_mask) & \ | |
338 | (1 << drm_plane_index(&intel_plane->base))) | |
339 | ||
262cd2e1 VS |
340 | #define for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) \ |
341 | list_for_each_entry(intel_plane, \ | |
342 | &(dev)->mode_config.plane_list, \ | |
343 | base.head) \ | |
95150bdf | 344 | for_each_if ((intel_plane)->pipe == (intel_crtc)->pipe) |
262cd2e1 | 345 | |
91c8a326 CW |
346 | #define for_each_intel_crtc(dev, intel_crtc) \ |
347 | list_for_each_entry(intel_crtc, \ | |
348 | &(dev)->mode_config.crtc_list, \ | |
349 | base.head) | |
d063ae48 | 350 | |
91c8a326 CW |
351 | #define for_each_intel_crtc_mask(dev, intel_crtc, crtc_mask) \ |
352 | list_for_each_entry(intel_crtc, \ | |
353 | &(dev)->mode_config.crtc_list, \ | |
354 | base.head) \ | |
98d39494 MR |
355 | for_each_if ((crtc_mask) & (1 << drm_crtc_index(&intel_crtc->base))) |
356 | ||
b2784e15 DL |
357 | #define for_each_intel_encoder(dev, intel_encoder) \ |
358 | list_for_each_entry(intel_encoder, \ | |
359 | &(dev)->mode_config.encoder_list, \ | |
360 | base.head) | |
361 | ||
3a3371ff ACO |
362 | #define for_each_intel_connector(dev, intel_connector) \ |
363 | list_for_each_entry(intel_connector, \ | |
91c8a326 | 364 | &(dev)->mode_config.connector_list, \ |
3a3371ff ACO |
365 | base.head) |
366 | ||
6c2b7c12 DV |
367 | #define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \ |
368 | list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \ | |
95150bdf | 369 | for_each_if ((intel_encoder)->base.crtc == (__crtc)) |
6c2b7c12 | 370 | |
53f5e3ca JB |
371 | #define for_each_connector_on_encoder(dev, __encoder, intel_connector) \ |
372 | list_for_each_entry((intel_connector), &(dev)->mode_config.connector_list, base.head) \ | |
95150bdf | 373 | for_each_if ((intel_connector)->base.encoder == (__encoder)) |
53f5e3ca | 374 | |
b04c5bd6 BF |
375 | #define for_each_power_domain(domain, mask) \ |
376 | for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \ | |
95150bdf | 377 | for_each_if ((1 << (domain)) & (mask)) |
b04c5bd6 | 378 | |
e7b903d2 | 379 | struct drm_i915_private; |
ad46cb53 | 380 | struct i915_mm_struct; |
5cc9ed4b | 381 | struct i915_mmu_object; |
e7b903d2 | 382 | |
a6f766f3 CW |
383 | struct drm_i915_file_private { |
384 | struct drm_i915_private *dev_priv; | |
385 | struct drm_file *file; | |
386 | ||
387 | struct { | |
388 | spinlock_t lock; | |
389 | struct list_head request_list; | |
d0bc54f2 CW |
390 | /* 20ms is a fairly arbitrary limit (greater than the average frame time) |
391 | * chosen to prevent the CPU getting more than a frame ahead of the GPU | |
392 | * (when using lax throttling for the frontbuffer). We also use it to | |
393 | * offer free GPU waitboosts for severely congested workloads. | |
394 | */ | |
395 | #define DRM_I915_THROTTLE_JIFFIES msecs_to_jiffies(20) | |
a6f766f3 CW |
396 | } mm; |
397 | struct idr context_idr; | |
398 | ||
2e1b8730 CW |
399 | struct intel_rps_client { |
400 | struct list_head link; | |
401 | unsigned boosts; | |
402 | } rps; | |
a6f766f3 | 403 | |
de1add36 | 404 | unsigned int bsd_ring; |
a6f766f3 CW |
405 | }; |
406 | ||
e69d0bc1 DV |
407 | /* Used by dp and fdi links */ |
408 | struct intel_link_m_n { | |
409 | uint32_t tu; | |
410 | uint32_t gmch_m; | |
411 | uint32_t gmch_n; | |
412 | uint32_t link_m; | |
413 | uint32_t link_n; | |
414 | }; | |
415 | ||
416 | void intel_link_compute_m_n(int bpp, int nlanes, | |
417 | int pixel_clock, int link_clock, | |
418 | struct intel_link_m_n *m_n); | |
419 | ||
1da177e4 LT |
420 | /* Interface history: |
421 | * | |
422 | * 1.1: Original. | |
0d6aa60b DA |
423 | * 1.2: Add Power Management |
424 | * 1.3: Add vblank support | |
de227f5f | 425 | * 1.4: Fix cmdbuffer path, add heap destroy |
702880f2 | 426 | * 1.5: Add vblank pipe configuration |
2228ed67 MCA |
427 | * 1.6: - New ioctl for scheduling buffer swaps on vertical blank |
428 | * - Support vertical blank on secondary display pipe | |
1da177e4 LT |
429 | */ |
430 | #define DRIVER_MAJOR 1 | |
2228ed67 | 431 | #define DRIVER_MINOR 6 |
1da177e4 LT |
432 | #define DRIVER_PATCHLEVEL 0 |
433 | ||
23bc5982 | 434 | #define WATCH_LISTS 0 |
673a394b | 435 | |
0a3e67a4 JB |
436 | struct opregion_header; |
437 | struct opregion_acpi; | |
438 | struct opregion_swsci; | |
439 | struct opregion_asle; | |
440 | ||
8ee1c3db | 441 | struct intel_opregion { |
115719fc WD |
442 | struct opregion_header *header; |
443 | struct opregion_acpi *acpi; | |
444 | struct opregion_swsci *swsci; | |
ebde53c7 JN |
445 | u32 swsci_gbda_sub_functions; |
446 | u32 swsci_sbcb_sub_functions; | |
115719fc | 447 | struct opregion_asle *asle; |
04ebaadb | 448 | void *rvda; |
82730385 | 449 | const void *vbt; |
ada8f955 | 450 | u32 vbt_size; |
115719fc | 451 | u32 *lid_state; |
91a60f20 | 452 | struct work_struct asle_work; |
8ee1c3db | 453 | }; |
44834a67 | 454 | #define OPREGION_SIZE (8*1024) |
8ee1c3db | 455 | |
6ef3d427 CW |
456 | struct intel_overlay; |
457 | struct intel_overlay_error_state; | |
458 | ||
de151cf6 | 459 | #define I915_FENCE_REG_NONE -1 |
42b5aeab VS |
460 | #define I915_MAX_NUM_FENCES 32 |
461 | /* 32 fences + sign bit for FENCE_REG_NONE */ | |
462 | #define I915_MAX_NUM_FENCE_BITS 6 | |
de151cf6 JB |
463 | |
464 | struct drm_i915_fence_reg { | |
007cc8ac | 465 | struct list_head lru_list; |
caea7476 | 466 | struct drm_i915_gem_object *obj; |
1690e1eb | 467 | int pin_count; |
de151cf6 | 468 | }; |
7c1c2871 | 469 | |
9b9d172d | 470 | struct sdvo_device_mapping { |
e957d772 | 471 | u8 initialized; |
9b9d172d | 472 | u8 dvo_port; |
473 | u8 slave_addr; | |
474 | u8 dvo_wiring; | |
e957d772 | 475 | u8 i2c_pin; |
b1083333 | 476 | u8 ddc_pin; |
9b9d172d | 477 | }; |
478 | ||
c4a1d9e4 CW |
479 | struct intel_display_error_state; |
480 | ||
63eeaf38 | 481 | struct drm_i915_error_state { |
742cbee8 | 482 | struct kref ref; |
585b0288 BW |
483 | struct timeval time; |
484 | ||
cb383002 | 485 | char error_msg[128]; |
bc3d6744 | 486 | bool simulated; |
eb5be9d0 | 487 | int iommu; |
48b031e3 | 488 | u32 reset_count; |
62d5d69b | 489 | u32 suspend_count; |
cb383002 | 490 | |
585b0288 | 491 | /* Generic register state */ |
63eeaf38 JB |
492 | u32 eir; |
493 | u32 pgtbl_er; | |
be998e2e | 494 | u32 ier; |
885ea5a8 | 495 | u32 gtier[4]; |
b9a3906b | 496 | u32 ccid; |
0f3b6849 CW |
497 | u32 derrmr; |
498 | u32 forcewake; | |
585b0288 BW |
499 | u32 error; /* gen6+ */ |
500 | u32 err_int; /* gen7 */ | |
6c826f34 MK |
501 | u32 fault_data0; /* gen8, gen9 */ |
502 | u32 fault_data1; /* gen8, gen9 */ | |
585b0288 | 503 | u32 done_reg; |
91ec5d11 BW |
504 | u32 gac_eco; |
505 | u32 gam_ecochk; | |
506 | u32 gab_ctl; | |
507 | u32 gfx_mode; | |
585b0288 | 508 | u32 extra_instdone[I915_NUM_INSTDONE_REG]; |
585b0288 BW |
509 | u64 fence[I915_MAX_NUM_FENCES]; |
510 | struct intel_overlay_error_state *overlay; | |
511 | struct intel_display_error_state *display; | |
0ca36d78 | 512 | struct drm_i915_error_object *semaphore_obj; |
585b0288 | 513 | |
52d39a21 | 514 | struct drm_i915_error_ring { |
372fbb8e | 515 | bool valid; |
362b8af7 BW |
516 | /* Software tracked state */ |
517 | bool waiting; | |
688e6c72 | 518 | int num_waiters; |
362b8af7 BW |
519 | int hangcheck_score; |
520 | enum intel_ring_hangcheck_action hangcheck_action; | |
521 | int num_requests; | |
522 | ||
523 | /* our own tracking of ring head and tail */ | |
524 | u32 cpu_ring_head; | |
525 | u32 cpu_ring_tail; | |
526 | ||
14fd0d6d | 527 | u32 last_seqno; |
666796da | 528 | u32 semaphore_seqno[I915_NUM_ENGINES - 1]; |
362b8af7 BW |
529 | |
530 | /* Register state */ | |
94f8cf10 | 531 | u32 start; |
362b8af7 BW |
532 | u32 tail; |
533 | u32 head; | |
534 | u32 ctl; | |
535 | u32 hws; | |
536 | u32 ipeir; | |
537 | u32 ipehr; | |
538 | u32 instdone; | |
362b8af7 BW |
539 | u32 bbstate; |
540 | u32 instpm; | |
541 | u32 instps; | |
542 | u32 seqno; | |
543 | u64 bbaddr; | |
50877445 | 544 | u64 acthd; |
362b8af7 | 545 | u32 fault_reg; |
13ffadd1 | 546 | u64 faddr; |
362b8af7 | 547 | u32 rc_psmi; /* sleep state */ |
666796da | 548 | u32 semaphore_mboxes[I915_NUM_ENGINES - 1]; |
362b8af7 | 549 | |
52d39a21 CW |
550 | struct drm_i915_error_object { |
551 | int page_count; | |
e1f12325 | 552 | u64 gtt_offset; |
52d39a21 | 553 | u32 *pages[0]; |
ab0e7ff9 | 554 | } *ringbuffer, *batchbuffer, *wa_batchbuffer, *ctx, *hws_page; |
362b8af7 | 555 | |
f85db059 | 556 | struct drm_i915_error_object *wa_ctx; |
557 | ||
52d39a21 CW |
558 | struct drm_i915_error_request { |
559 | long jiffies; | |
560 | u32 seqno; | |
ee4f42b1 | 561 | u32 tail; |
52d39a21 | 562 | } *requests; |
6c7a01ec | 563 | |
688e6c72 CW |
564 | struct drm_i915_error_waiter { |
565 | char comm[TASK_COMM_LEN]; | |
566 | pid_t pid; | |
567 | u32 seqno; | |
568 | } *waiters; | |
569 | ||
6c7a01ec BW |
570 | struct { |
571 | u32 gfx_mode; | |
572 | union { | |
573 | u64 pdp[4]; | |
574 | u32 pp_dir_base; | |
575 | }; | |
576 | } vm_info; | |
ab0e7ff9 CW |
577 | |
578 | pid_t pid; | |
579 | char comm[TASK_COMM_LEN]; | |
666796da | 580 | } ring[I915_NUM_ENGINES]; |
3a448734 | 581 | |
9df30794 | 582 | struct drm_i915_error_buffer { |
a779e5ab | 583 | u32 size; |
9df30794 | 584 | u32 name; |
666796da | 585 | u32 rseqno[I915_NUM_ENGINES], wseqno; |
e1f12325 | 586 | u64 gtt_offset; |
9df30794 CW |
587 | u32 read_domains; |
588 | u32 write_domain; | |
4b9de737 | 589 | s32 fence_reg:I915_MAX_NUM_FENCE_BITS; |
9df30794 CW |
590 | s32 pinned:2; |
591 | u32 tiling:2; | |
592 | u32 dirty:1; | |
593 | u32 purgeable:1; | |
5cc9ed4b | 594 | u32 userptr:1; |
5d1333fc | 595 | s32 ring:4; |
f56383cb | 596 | u32 cache_level:3; |
95f5301d | 597 | } **active_bo, **pinned_bo; |
6c7a01ec | 598 | |
95f5301d | 599 | u32 *active_bo_count, *pinned_bo_count; |
3a448734 | 600 | u32 vm_count; |
63eeaf38 JB |
601 | }; |
602 | ||
7bd688cd | 603 | struct intel_connector; |
820d2d77 | 604 | struct intel_encoder; |
5cec258b | 605 | struct intel_crtc_state; |
5724dbd1 | 606 | struct intel_initial_plane_config; |
0e8ffe1b | 607 | struct intel_crtc; |
ee9300bb DV |
608 | struct intel_limit; |
609 | struct dpll; | |
b8cecdf5 | 610 | |
e70236a8 | 611 | struct drm_i915_display_funcs { |
e70236a8 JB |
612 | int (*get_display_clock_speed)(struct drm_device *dev); |
613 | int (*get_fifo_size)(struct drm_device *dev, int plane); | |
e3bddded | 614 | int (*compute_pipe_wm)(struct intel_crtc_state *cstate); |
ed4a6a7c MR |
615 | int (*compute_intermediate_wm)(struct drm_device *dev, |
616 | struct intel_crtc *intel_crtc, | |
617 | struct intel_crtc_state *newstate); | |
618 | void (*initial_watermarks)(struct intel_crtc_state *cstate); | |
619 | void (*optimize_watermarks)(struct intel_crtc_state *cstate); | |
98d39494 | 620 | int (*compute_global_watermarks)(struct drm_atomic_state *state); |
46ba614c | 621 | void (*update_wm)(struct drm_crtc *crtc); |
27c329ed ML |
622 | int (*modeset_calc_cdclk)(struct drm_atomic_state *state); |
623 | void (*modeset_commit_cdclk)(struct drm_atomic_state *state); | |
0e8ffe1b DV |
624 | /* Returns the active state of the crtc, and if the crtc is active, |
625 | * fills out the pipe-config with the hw state. */ | |
626 | bool (*get_pipe_config)(struct intel_crtc *, | |
5cec258b | 627 | struct intel_crtc_state *); |
5724dbd1 DL |
628 | void (*get_initial_plane_config)(struct intel_crtc *, |
629 | struct intel_initial_plane_config *); | |
190f68c5 ACO |
630 | int (*crtc_compute_clock)(struct intel_crtc *crtc, |
631 | struct intel_crtc_state *crtc_state); | |
76e5a89c DV |
632 | void (*crtc_enable)(struct drm_crtc *crtc); |
633 | void (*crtc_disable)(struct drm_crtc *crtc); | |
69bfe1a9 JN |
634 | void (*audio_codec_enable)(struct drm_connector *connector, |
635 | struct intel_encoder *encoder, | |
5e7234c9 | 636 | const struct drm_display_mode *adjusted_mode); |
69bfe1a9 | 637 | void (*audio_codec_disable)(struct intel_encoder *encoder); |
674cf967 | 638 | void (*fdi_link_train)(struct drm_crtc *crtc); |
6067aaea | 639 | void (*init_clock_gating)(struct drm_device *dev); |
5a21b665 DV |
640 | int (*queue_flip)(struct drm_device *dev, struct drm_crtc *crtc, |
641 | struct drm_framebuffer *fb, | |
642 | struct drm_i915_gem_object *obj, | |
643 | struct drm_i915_gem_request *req, | |
644 | uint32_t flags); | |
91d14251 | 645 | void (*hpd_irq_setup)(struct drm_i915_private *dev_priv); |
e70236a8 JB |
646 | /* clock updates for mode set */ |
647 | /* cursor updates */ | |
648 | /* render clock increase/decrease */ | |
649 | /* display clock increase/decrease */ | |
650 | /* pll clock increase/decrease */ | |
8563b1e8 | 651 | |
b95c5321 ML |
652 | void (*load_csc_matrix)(struct drm_crtc_state *crtc_state); |
653 | void (*load_luts)(struct drm_crtc_state *crtc_state); | |
e70236a8 JB |
654 | }; |
655 | ||
48c1026a MK |
656 | enum forcewake_domain_id { |
657 | FW_DOMAIN_ID_RENDER = 0, | |
658 | FW_DOMAIN_ID_BLITTER, | |
659 | FW_DOMAIN_ID_MEDIA, | |
660 | ||
661 | FW_DOMAIN_ID_COUNT | |
662 | }; | |
663 | ||
664 | enum forcewake_domains { | |
665 | FORCEWAKE_RENDER = (1 << FW_DOMAIN_ID_RENDER), | |
666 | FORCEWAKE_BLITTER = (1 << FW_DOMAIN_ID_BLITTER), | |
667 | FORCEWAKE_MEDIA = (1 << FW_DOMAIN_ID_MEDIA), | |
668 | FORCEWAKE_ALL = (FORCEWAKE_RENDER | | |
669 | FORCEWAKE_BLITTER | | |
670 | FORCEWAKE_MEDIA) | |
671 | }; | |
672 | ||
3756685a TU |
673 | #define FW_REG_READ (1) |
674 | #define FW_REG_WRITE (2) | |
675 | ||
676 | enum forcewake_domains | |
677 | intel_uncore_forcewake_for_reg(struct drm_i915_private *dev_priv, | |
678 | i915_reg_t reg, unsigned int op); | |
679 | ||
907b28c5 | 680 | struct intel_uncore_funcs { |
c8d9a590 | 681 | void (*force_wake_get)(struct drm_i915_private *dev_priv, |
48c1026a | 682 | enum forcewake_domains domains); |
c8d9a590 | 683 | void (*force_wake_put)(struct drm_i915_private *dev_priv, |
48c1026a | 684 | enum forcewake_domains domains); |
0b274481 | 685 | |
f0f59a00 VS |
686 | uint8_t (*mmio_readb)(struct drm_i915_private *dev_priv, i915_reg_t r, bool trace); |
687 | uint16_t (*mmio_readw)(struct drm_i915_private *dev_priv, i915_reg_t r, bool trace); | |
688 | uint32_t (*mmio_readl)(struct drm_i915_private *dev_priv, i915_reg_t r, bool trace); | |
689 | uint64_t (*mmio_readq)(struct drm_i915_private *dev_priv, i915_reg_t r, bool trace); | |
0b274481 | 690 | |
f0f59a00 | 691 | void (*mmio_writeb)(struct drm_i915_private *dev_priv, i915_reg_t r, |
0b274481 | 692 | uint8_t val, bool trace); |
f0f59a00 | 693 | void (*mmio_writew)(struct drm_i915_private *dev_priv, i915_reg_t r, |
0b274481 | 694 | uint16_t val, bool trace); |
f0f59a00 | 695 | void (*mmio_writel)(struct drm_i915_private *dev_priv, i915_reg_t r, |
0b274481 | 696 | uint32_t val, bool trace); |
f0f59a00 | 697 | void (*mmio_writeq)(struct drm_i915_private *dev_priv, i915_reg_t r, |
0b274481 | 698 | uint64_t val, bool trace); |
990bbdad CW |
699 | }; |
700 | ||
907b28c5 CW |
701 | struct intel_uncore { |
702 | spinlock_t lock; /** lock is also taken in irq contexts. */ | |
703 | ||
704 | struct intel_uncore_funcs funcs; | |
705 | ||
706 | unsigned fifo_count; | |
48c1026a | 707 | enum forcewake_domains fw_domains; |
b2cff0db CW |
708 | |
709 | struct intel_uncore_forcewake_domain { | |
710 | struct drm_i915_private *i915; | |
48c1026a | 711 | enum forcewake_domain_id id; |
33c582c1 | 712 | enum forcewake_domains mask; |
b2cff0db | 713 | unsigned wake_count; |
a57a4a67 | 714 | struct hrtimer timer; |
f0f59a00 | 715 | i915_reg_t reg_set; |
05a2fb15 MK |
716 | u32 val_set; |
717 | u32 val_clear; | |
f0f59a00 VS |
718 | i915_reg_t reg_ack; |
719 | i915_reg_t reg_post; | |
05a2fb15 | 720 | u32 val_reset; |
b2cff0db | 721 | } fw_domain[FW_DOMAIN_ID_COUNT]; |
75714940 MK |
722 | |
723 | int unclaimed_mmio_check; | |
b2cff0db CW |
724 | }; |
725 | ||
726 | /* Iterate over initialised fw domains */ | |
33c582c1 TU |
727 | #define for_each_fw_domain_masked(domain__, mask__, dev_priv__) \ |
728 | for ((domain__) = &(dev_priv__)->uncore.fw_domain[0]; \ | |
729 | (domain__) < &(dev_priv__)->uncore.fw_domain[FW_DOMAIN_ID_COUNT]; \ | |
730 | (domain__)++) \ | |
731 | for_each_if ((mask__) & (domain__)->mask) | |
732 | ||
733 | #define for_each_fw_domain(domain__, dev_priv__) \ | |
734 | for_each_fw_domain_masked(domain__, FORCEWAKE_ALL, dev_priv__) | |
907b28c5 | 735 | |
b6e7d894 DL |
736 | #define CSR_VERSION(major, minor) ((major) << 16 | (minor)) |
737 | #define CSR_VERSION_MAJOR(version) ((version) >> 16) | |
738 | #define CSR_VERSION_MINOR(version) ((version) & 0xffff) | |
739 | ||
eb805623 | 740 | struct intel_csr { |
8144ac59 | 741 | struct work_struct work; |
eb805623 | 742 | const char *fw_path; |
a7f749f9 | 743 | uint32_t *dmc_payload; |
eb805623 | 744 | uint32_t dmc_fw_size; |
b6e7d894 | 745 | uint32_t version; |
eb805623 | 746 | uint32_t mmio_count; |
f0f59a00 | 747 | i915_reg_t mmioaddr[8]; |
eb805623 | 748 | uint32_t mmiodata[8]; |
832dba88 | 749 | uint32_t dc_state; |
a37baf3b | 750 | uint32_t allowed_dc_mask; |
eb805623 DV |
751 | }; |
752 | ||
79fc46df DL |
753 | #define DEV_INFO_FOR_EACH_FLAG(func, sep) \ |
754 | func(is_mobile) sep \ | |
755 | func(is_i85x) sep \ | |
756 | func(is_i915g) sep \ | |
757 | func(is_i945gm) sep \ | |
758 | func(is_g33) sep \ | |
759 | func(need_gfx_hws) sep \ | |
760 | func(is_g4x) sep \ | |
761 | func(is_pineview) sep \ | |
762 | func(is_broadwater) sep \ | |
763 | func(is_crestline) sep \ | |
764 | func(is_ivybridge) sep \ | |
765 | func(is_valleyview) sep \ | |
666a4537 | 766 | func(is_cherryview) sep \ |
79fc46df | 767 | func(is_haswell) sep \ |
ab0d24ac | 768 | func(is_broadwell) sep \ |
7201c0b3 | 769 | func(is_skylake) sep \ |
7526ac19 | 770 | func(is_broxton) sep \ |
ef11bdb3 | 771 | func(is_kabylake) sep \ |
b833d685 | 772 | func(is_preliminary) sep \ |
79fc46df DL |
773 | func(has_fbc) sep \ |
774 | func(has_pipe_cxsr) sep \ | |
775 | func(has_hotplug) sep \ | |
776 | func(cursor_needs_physical) sep \ | |
777 | func(has_overlay) sep \ | |
778 | func(overlay_needs_physical) sep \ | |
779 | func(supports_tv) sep \ | |
dd93be58 | 780 | func(has_llc) sep \ |
ca377809 | 781 | func(has_snoop) sep \ |
30568c45 | 782 | func(has_ddi) sep \ |
33e141ed | 783 | func(has_fpga_dbg) sep \ |
784 | func(has_pooled_eu) | |
c96ea64e | 785 | |
a587f779 DL |
786 | #define DEFINE_FLAG(name) u8 name:1 |
787 | #define SEP_SEMICOLON ; | |
c96ea64e | 788 | |
cfdf1fa2 | 789 | struct intel_device_info { |
10fce67a | 790 | u32 display_mmio_offset; |
87f1f465 | 791 | u16 device_id; |
ac208a8b | 792 | u8 num_pipes; |
d615a166 | 793 | u8 num_sprites[I915_MAX_PIPES]; |
c96c3a8c | 794 | u8 gen; |
ae5702d2 | 795 | u16 gen_mask; |
73ae478c | 796 | u8 ring_mask; /* Rings supported by the HW */ |
a587f779 | 797 | DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG, SEP_SEMICOLON); |
a57c774a AK |
798 | /* Register offsets for the various display pipes and transcoders */ |
799 | int pipe_offsets[I915_MAX_TRANSCODERS]; | |
800 | int trans_offsets[I915_MAX_TRANSCODERS]; | |
a57c774a | 801 | int palette_offsets[I915_MAX_PIPES]; |
5efb3e28 | 802 | int cursor_offsets[I915_MAX_PIPES]; |
3873218f JM |
803 | |
804 | /* Slice/subslice/EU info */ | |
805 | u8 slice_total; | |
806 | u8 subslice_total; | |
807 | u8 subslice_per_slice; | |
808 | u8 eu_total; | |
809 | u8 eu_per_subslice; | |
33e141ed | 810 | u8 min_eu_in_pool; |
b7668791 DL |
811 | /* For each slice, which subslice(s) has(have) 7 EUs (bitfield)? */ |
812 | u8 subslice_7eu[3]; | |
3873218f JM |
813 | u8 has_slice_pg:1; |
814 | u8 has_subslice_pg:1; | |
815 | u8 has_eu_pg:1; | |
82cf435b LL |
816 | |
817 | struct color_luts { | |
818 | u16 degamma_lut_size; | |
819 | u16 gamma_lut_size; | |
820 | } color; | |
cfdf1fa2 KH |
821 | }; |
822 | ||
a587f779 DL |
823 | #undef DEFINE_FLAG |
824 | #undef SEP_SEMICOLON | |
825 | ||
7faf1ab2 DV |
826 | enum i915_cache_level { |
827 | I915_CACHE_NONE = 0, | |
350ec881 CW |
828 | I915_CACHE_LLC, /* also used for snoopable memory on non-LLC */ |
829 | I915_CACHE_L3_LLC, /* gen7+, L3 sits between the domain specifc | |
830 | caches, eg sampler/render caches, and the | |
831 | large Last-Level-Cache. LLC is coherent with | |
832 | the CPU, but L3 is only visible to the GPU. */ | |
651d794f | 833 | I915_CACHE_WT, /* hsw:gt3e WriteThrough for scanouts */ |
7faf1ab2 DV |
834 | }; |
835 | ||
e59ec13d MK |
836 | struct i915_ctx_hang_stats { |
837 | /* This context had batch pending when hang was declared */ | |
838 | unsigned batch_pending; | |
839 | ||
840 | /* This context had batch active when hang was declared */ | |
841 | unsigned batch_active; | |
be62acb4 MK |
842 | |
843 | /* Time when this context was last blamed for a GPU reset */ | |
844 | unsigned long guilty_ts; | |
845 | ||
676fa572 CW |
846 | /* If the contexts causes a second GPU hang within this time, |
847 | * it is permanently banned from submitting any more work. | |
848 | */ | |
849 | unsigned long ban_period_seconds; | |
850 | ||
be62acb4 MK |
851 | /* This context is banned to submit more work */ |
852 | bool banned; | |
e59ec13d | 853 | }; |
40521054 BW |
854 | |
855 | /* This must match up with the value previously used for execbuf2.rsvd1. */ | |
821d66dd | 856 | #define DEFAULT_CONTEXT_HANDLE 0 |
b1b38278 | 857 | |
31b7a88d | 858 | /** |
e2efd130 | 859 | * struct i915_gem_context - as the name implies, represents a context. |
31b7a88d OM |
860 | * @ref: reference count. |
861 | * @user_handle: userspace tracking identity for this context. | |
862 | * @remap_slice: l3 row remapping information. | |
b1b38278 DW |
863 | * @flags: context specific flags: |
864 | * CONTEXT_NO_ZEROMAP: do not allow mapping things to page 0. | |
31b7a88d OM |
865 | * @file_priv: filp associated with this context (NULL for global default |
866 | * context). | |
867 | * @hang_stats: information about the role of this context in possible GPU | |
868 | * hangs. | |
7df113e4 | 869 | * @ppgtt: virtual memory space used by this context. |
31b7a88d OM |
870 | * @legacy_hw_ctx: render context backing object and whether it is correctly |
871 | * initialized (legacy ring submission mechanism only). | |
872 | * @link: link in the global list of contexts. | |
873 | * | |
874 | * Contexts are memory images used by the hardware to store copies of their | |
875 | * internal state. | |
876 | */ | |
e2efd130 | 877 | struct i915_gem_context { |
dce3271b | 878 | struct kref ref; |
9ea4feec | 879 | struct drm_i915_private *i915; |
40521054 | 880 | struct drm_i915_file_private *file_priv; |
ae6c4806 | 881 | struct i915_hw_ppgtt *ppgtt; |
a33afea5 | 882 | |
8d59bc6a CW |
883 | struct i915_ctx_hang_stats hang_stats; |
884 | ||
8d59bc6a | 885 | unsigned long flags; |
bc3d6744 CW |
886 | #define CONTEXT_NO_ZEROMAP BIT(0) |
887 | #define CONTEXT_NO_ERROR_CAPTURE BIT(1) | |
0184c2ff DG |
888 | |
889 | /* Unique identifier for this context, used by the hw for tracking */ | |
890 | unsigned int hw_id; | |
8d59bc6a | 891 | u32 user_handle; |
5d1808ec | 892 | |
0cb26a8e CW |
893 | u32 ggtt_alignment; |
894 | ||
9021ad03 | 895 | struct intel_context { |
c9e003af | 896 | struct drm_i915_gem_object *state; |
84c2377f | 897 | struct intel_ringbuffer *ringbuf; |
ca82580c | 898 | struct i915_vma *lrc_vma; |
82352e90 | 899 | uint32_t *lrc_reg_state; |
8d59bc6a CW |
900 | u64 lrc_desc; |
901 | int pin_count; | |
24f1d3cc | 902 | bool initialised; |
666796da | 903 | } engine[I915_NUM_ENGINES]; |
bcd794c2 | 904 | u32 ring_size; |
c01fc532 | 905 | u32 desc_template; |
3c7ba635 | 906 | struct atomic_notifier_head status_notifier; |
80a9a8db | 907 | bool execlists_force_single_submission; |
c9e003af | 908 | |
a33afea5 | 909 | struct list_head link; |
8d59bc6a CW |
910 | |
911 | u8 remap_slice; | |
40521054 BW |
912 | }; |
913 | ||
a4001f1b PZ |
914 | enum fb_op_origin { |
915 | ORIGIN_GTT, | |
916 | ORIGIN_CPU, | |
917 | ORIGIN_CS, | |
918 | ORIGIN_FLIP, | |
74b4ea1e | 919 | ORIGIN_DIRTYFB, |
a4001f1b PZ |
920 | }; |
921 | ||
ab34a7e8 | 922 | struct intel_fbc { |
25ad93fd PZ |
923 | /* This is always the inner lock when overlapping with struct_mutex and |
924 | * it's the outer lock when overlapping with stolen_lock. */ | |
925 | struct mutex lock; | |
5e59f717 | 926 | unsigned threshold; |
dbef0f15 PZ |
927 | unsigned int possible_framebuffer_bits; |
928 | unsigned int busy_bits; | |
010cf73d | 929 | unsigned int visible_pipes_mask; |
e35fef21 | 930 | struct intel_crtc *crtc; |
5c3fe8b0 | 931 | |
c4213885 | 932 | struct drm_mm_node compressed_fb; |
5c3fe8b0 BW |
933 | struct drm_mm_node *compressed_llb; |
934 | ||
da46f936 RV |
935 | bool false_color; |
936 | ||
d029bcad | 937 | bool enabled; |
0e631adc | 938 | bool active; |
9adccc60 | 939 | |
aaf78d27 PZ |
940 | struct intel_fbc_state_cache { |
941 | struct { | |
942 | unsigned int mode_flags; | |
943 | uint32_t hsw_bdw_pixel_rate; | |
944 | } crtc; | |
945 | ||
946 | struct { | |
947 | unsigned int rotation; | |
948 | int src_w; | |
949 | int src_h; | |
950 | bool visible; | |
951 | } plane; | |
952 | ||
953 | struct { | |
954 | u64 ilk_ggtt_offset; | |
aaf78d27 PZ |
955 | uint32_t pixel_format; |
956 | unsigned int stride; | |
957 | int fence_reg; | |
958 | unsigned int tiling_mode; | |
959 | } fb; | |
960 | } state_cache; | |
961 | ||
b183b3f1 PZ |
962 | struct intel_fbc_reg_params { |
963 | struct { | |
964 | enum pipe pipe; | |
965 | enum plane plane; | |
966 | unsigned int fence_y_offset; | |
967 | } crtc; | |
968 | ||
969 | struct { | |
970 | u64 ggtt_offset; | |
b183b3f1 PZ |
971 | uint32_t pixel_format; |
972 | unsigned int stride; | |
973 | int fence_reg; | |
974 | } fb; | |
975 | ||
976 | int cfb_size; | |
977 | } params; | |
978 | ||
5c3fe8b0 | 979 | struct intel_fbc_work { |
128d7356 | 980 | bool scheduled; |
ca18d51d | 981 | u32 scheduled_vblank; |
128d7356 | 982 | struct work_struct work; |
128d7356 | 983 | } work; |
5c3fe8b0 | 984 | |
bf6189c6 | 985 | const char *no_fbc_reason; |
b5e50c3f JB |
986 | }; |
987 | ||
96178eeb VK |
988 | /** |
989 | * HIGH_RR is the highest eDP panel refresh rate read from EDID | |
990 | * LOW_RR is the lowest eDP panel refresh rate found from EDID | |
991 | * parsing for same resolution. | |
992 | */ | |
993 | enum drrs_refresh_rate_type { | |
994 | DRRS_HIGH_RR, | |
995 | DRRS_LOW_RR, | |
996 | DRRS_MAX_RR, /* RR count */ | |
997 | }; | |
998 | ||
999 | enum drrs_support_type { | |
1000 | DRRS_NOT_SUPPORTED = 0, | |
1001 | STATIC_DRRS_SUPPORT = 1, | |
1002 | SEAMLESS_DRRS_SUPPORT = 2 | |
439d7ac0 PB |
1003 | }; |
1004 | ||
2807cf69 | 1005 | struct intel_dp; |
96178eeb VK |
1006 | struct i915_drrs { |
1007 | struct mutex mutex; | |
1008 | struct delayed_work work; | |
1009 | struct intel_dp *dp; | |
1010 | unsigned busy_frontbuffer_bits; | |
1011 | enum drrs_refresh_rate_type refresh_rate_type; | |
1012 | enum drrs_support_type type; | |
1013 | }; | |
1014 | ||
a031d709 | 1015 | struct i915_psr { |
f0355c4a | 1016 | struct mutex lock; |
a031d709 RV |
1017 | bool sink_support; |
1018 | bool source_ok; | |
2807cf69 | 1019 | struct intel_dp *enabled; |
7c8f8a70 RV |
1020 | bool active; |
1021 | struct delayed_work work; | |
9ca15301 | 1022 | unsigned busy_frontbuffer_bits; |
474d1ec4 SJ |
1023 | bool psr2_support; |
1024 | bool aux_frame_sync; | |
60e5ffe3 | 1025 | bool link_standby; |
3f51e471 | 1026 | }; |
5c3fe8b0 | 1027 | |
3bad0781 | 1028 | enum intel_pch { |
f0350830 | 1029 | PCH_NONE = 0, /* No PCH present */ |
3bad0781 ZW |
1030 | PCH_IBX, /* Ibexpeak PCH */ |
1031 | PCH_CPT, /* Cougarpoint PCH */ | |
eb877ebf | 1032 | PCH_LPT, /* Lynxpoint PCH */ |
e7e7ea20 | 1033 | PCH_SPT, /* Sunrisepoint PCH */ |
22dea0be | 1034 | PCH_KBP, /* Kabypoint PCH */ |
40c7ead9 | 1035 | PCH_NOP, |
3bad0781 ZW |
1036 | }; |
1037 | ||
988d6ee8 PZ |
1038 | enum intel_sbi_destination { |
1039 | SBI_ICLK, | |
1040 | SBI_MPHY, | |
1041 | }; | |
1042 | ||
b690e96c | 1043 | #define QUIRK_PIPEA_FORCE (1<<0) |
435793df | 1044 | #define QUIRK_LVDS_SSC_DISABLE (1<<1) |
4dca20ef | 1045 | #define QUIRK_INVERT_BRIGHTNESS (1<<2) |
9c72cc6f | 1046 | #define QUIRK_BACKLIGHT_PRESENT (1<<3) |
b6b5d049 | 1047 | #define QUIRK_PIPEB_FORCE (1<<4) |
656bfa3a | 1048 | #define QUIRK_PIN_SWIZZLED_PAGES (1<<5) |
b690e96c | 1049 | |
8be48d92 | 1050 | struct intel_fbdev; |
1630fe75 | 1051 | struct intel_fbc_work; |
38651674 | 1052 | |
c2b9152f DV |
1053 | struct intel_gmbus { |
1054 | struct i2c_adapter adapter; | |
3e4d44e0 | 1055 | #define GMBUS_FORCE_BIT_RETRY (1U << 31) |
f2ce9faf | 1056 | u32 force_bit; |
c2b9152f | 1057 | u32 reg0; |
f0f59a00 | 1058 | i915_reg_t gpio_reg; |
c167a6fc | 1059 | struct i2c_algo_bit_data bit_algo; |
c2b9152f DV |
1060 | struct drm_i915_private *dev_priv; |
1061 | }; | |
1062 | ||
f4c956ad | 1063 | struct i915_suspend_saved_registers { |
e948e994 | 1064 | u32 saveDSPARB; |
ba8bbcf6 | 1065 | u32 saveLVDS; |
585fb111 JB |
1066 | u32 savePP_ON_DELAYS; |
1067 | u32 savePP_OFF_DELAYS; | |
ba8bbcf6 JB |
1068 | u32 savePP_ON; |
1069 | u32 savePP_OFF; | |
1070 | u32 savePP_CONTROL; | |
585fb111 | 1071 | u32 savePP_DIVISOR; |
ba8bbcf6 | 1072 | u32 saveFBC_CONTROL; |
1f84e550 | 1073 | u32 saveCACHE_MODE_0; |
1f84e550 | 1074 | u32 saveMI_ARB_STATE; |
ba8bbcf6 JB |
1075 | u32 saveSWF0[16]; |
1076 | u32 saveSWF1[16]; | |
85fa792b | 1077 | u32 saveSWF3[3]; |
4b9de737 | 1078 | uint64_t saveFENCE[I915_MAX_NUM_FENCES]; |
cda2bb78 | 1079 | u32 savePCH_PORT_HOTPLUG; |
9f49c376 | 1080 | u16 saveGCDGMBUS; |
f4c956ad | 1081 | }; |
c85aa885 | 1082 | |
ddeea5b0 ID |
1083 | struct vlv_s0ix_state { |
1084 | /* GAM */ | |
1085 | u32 wr_watermark; | |
1086 | u32 gfx_prio_ctrl; | |
1087 | u32 arb_mode; | |
1088 | u32 gfx_pend_tlb0; | |
1089 | u32 gfx_pend_tlb1; | |
1090 | u32 lra_limits[GEN7_LRA_LIMITS_REG_NUM]; | |
1091 | u32 media_max_req_count; | |
1092 | u32 gfx_max_req_count; | |
1093 | u32 render_hwsp; | |
1094 | u32 ecochk; | |
1095 | u32 bsd_hwsp; | |
1096 | u32 blt_hwsp; | |
1097 | u32 tlb_rd_addr; | |
1098 | ||
1099 | /* MBC */ | |
1100 | u32 g3dctl; | |
1101 | u32 gsckgctl; | |
1102 | u32 mbctl; | |
1103 | ||
1104 | /* GCP */ | |
1105 | u32 ucgctl1; | |
1106 | u32 ucgctl3; | |
1107 | u32 rcgctl1; | |
1108 | u32 rcgctl2; | |
1109 | u32 rstctl; | |
1110 | u32 misccpctl; | |
1111 | ||
1112 | /* GPM */ | |
1113 | u32 gfxpause; | |
1114 | u32 rpdeuhwtc; | |
1115 | u32 rpdeuc; | |
1116 | u32 ecobus; | |
1117 | u32 pwrdwnupctl; | |
1118 | u32 rp_down_timeout; | |
1119 | u32 rp_deucsw; | |
1120 | u32 rcubmabdtmr; | |
1121 | u32 rcedata; | |
1122 | u32 spare2gh; | |
1123 | ||
1124 | /* Display 1 CZ domain */ | |
1125 | u32 gt_imr; | |
1126 | u32 gt_ier; | |
1127 | u32 pm_imr; | |
1128 | u32 pm_ier; | |
1129 | u32 gt_scratch[GEN7_GT_SCRATCH_REG_NUM]; | |
1130 | ||
1131 | /* GT SA CZ domain */ | |
1132 | u32 tilectl; | |
1133 | u32 gt_fifoctl; | |
1134 | u32 gtlc_wake_ctrl; | |
1135 | u32 gtlc_survive; | |
1136 | u32 pmwgicz; | |
1137 | ||
1138 | /* Display 2 CZ domain */ | |
1139 | u32 gu_ctl0; | |
1140 | u32 gu_ctl1; | |
9c25210f | 1141 | u32 pcbr; |
ddeea5b0 ID |
1142 | u32 clock_gate_dis2; |
1143 | }; | |
1144 | ||
bf225f20 CW |
1145 | struct intel_rps_ei { |
1146 | u32 cz_clock; | |
1147 | u32 render_c0; | |
1148 | u32 media_c0; | |
31685c25 D |
1149 | }; |
1150 | ||
c85aa885 | 1151 | struct intel_gen6_power_mgmt { |
d4d70aa5 ID |
1152 | /* |
1153 | * work, interrupts_enabled and pm_iir are protected by | |
1154 | * dev_priv->irq_lock | |
1155 | */ | |
c85aa885 | 1156 | struct work_struct work; |
d4d70aa5 | 1157 | bool interrupts_enabled; |
c85aa885 | 1158 | u32 pm_iir; |
59cdb63d | 1159 | |
1800ad25 SAK |
1160 | u32 pm_intr_keep; |
1161 | ||
b39fb297 BW |
1162 | /* Frequencies are stored in potentially platform dependent multiples. |
1163 | * In other words, *_freq needs to be multiplied by X to be interesting. | |
1164 | * Soft limits are those which are used for the dynamic reclocking done | |
1165 | * by the driver (raise frequencies under heavy loads, and lower for | |
1166 | * lighter loads). Hard limits are those imposed by the hardware. | |
1167 | * | |
1168 | * A distinction is made for overclocking, which is never enabled by | |
1169 | * default, and is considered to be above the hard limit if it's | |
1170 | * possible at all. | |
1171 | */ | |
1172 | u8 cur_freq; /* Current frequency (cached, may not == HW) */ | |
1173 | u8 min_freq_softlimit; /* Minimum frequency permitted by the driver */ | |
1174 | u8 max_freq_softlimit; /* Max frequency permitted by the driver */ | |
1175 | u8 max_freq; /* Maximum frequency, RP0 if not overclocking */ | |
1176 | u8 min_freq; /* AKA RPn. Minimum frequency */ | |
aed242ff | 1177 | u8 idle_freq; /* Frequency to request when we are idle */ |
b39fb297 BW |
1178 | u8 efficient_freq; /* AKA RPe. Pre-determined balanced frequency */ |
1179 | u8 rp1_freq; /* "less than" RP0 power/freqency */ | |
1180 | u8 rp0_freq; /* Non-overclocked max frequency. */ | |
c30fec65 | 1181 | u16 gpll_ref_freq; /* vlv/chv GPLL reference frequency */ |
1a01ab3b | 1182 | |
8fb55197 CW |
1183 | u8 up_threshold; /* Current %busy required to uplock */ |
1184 | u8 down_threshold; /* Current %busy required to downclock */ | |
1185 | ||
dd75fdc8 CW |
1186 | int last_adj; |
1187 | enum { LOW_POWER, BETWEEN, HIGH_POWER } power; | |
1188 | ||
8d3afd7d CW |
1189 | spinlock_t client_lock; |
1190 | struct list_head clients; | |
1191 | bool client_boost; | |
1192 | ||
c0951f0c | 1193 | bool enabled; |
1a01ab3b | 1194 | struct delayed_work delayed_resume_work; |
1854d5ca | 1195 | unsigned boosts; |
4fc688ce | 1196 | |
2e1b8730 | 1197 | struct intel_rps_client semaphores, mmioflips; |
a6f766f3 | 1198 | |
bf225f20 CW |
1199 | /* manual wa residency calculations */ |
1200 | struct intel_rps_ei up_ei, down_ei; | |
1201 | ||
4fc688ce JB |
1202 | /* |
1203 | * Protects RPS/RC6 register access and PCU communication. | |
8d3afd7d CW |
1204 | * Must be taken after struct_mutex if nested. Note that |
1205 | * this lock may be held for long periods of time when | |
1206 | * talking to hw - so only take it when talking to hw! | |
4fc688ce JB |
1207 | */ |
1208 | struct mutex hw_lock; | |
c85aa885 DV |
1209 | }; |
1210 | ||
1a240d4d DV |
1211 | /* defined intel_pm.c */ |
1212 | extern spinlock_t mchdev_lock; | |
1213 | ||
c85aa885 DV |
1214 | struct intel_ilk_power_mgmt { |
1215 | u8 cur_delay; | |
1216 | u8 min_delay; | |
1217 | u8 max_delay; | |
1218 | u8 fmax; | |
1219 | u8 fstart; | |
1220 | ||
1221 | u64 last_count1; | |
1222 | unsigned long last_time1; | |
1223 | unsigned long chipset_power; | |
1224 | u64 last_count2; | |
5ed0bdf2 | 1225 | u64 last_time2; |
c85aa885 DV |
1226 | unsigned long gfx_power; |
1227 | u8 corr; | |
1228 | ||
1229 | int c_m; | |
1230 | int r_t; | |
1231 | }; | |
1232 | ||
c6cb582e ID |
1233 | struct drm_i915_private; |
1234 | struct i915_power_well; | |
1235 | ||
1236 | struct i915_power_well_ops { | |
1237 | /* | |
1238 | * Synchronize the well's hw state to match the current sw state, for | |
1239 | * example enable/disable it based on the current refcount. Called | |
1240 | * during driver init and resume time, possibly after first calling | |
1241 | * the enable/disable handlers. | |
1242 | */ | |
1243 | void (*sync_hw)(struct drm_i915_private *dev_priv, | |
1244 | struct i915_power_well *power_well); | |
1245 | /* | |
1246 | * Enable the well and resources that depend on it (for example | |
1247 | * interrupts located on the well). Called after the 0->1 refcount | |
1248 | * transition. | |
1249 | */ | |
1250 | void (*enable)(struct drm_i915_private *dev_priv, | |
1251 | struct i915_power_well *power_well); | |
1252 | /* | |
1253 | * Disable the well and resources that depend on it. Called after | |
1254 | * the 1->0 refcount transition. | |
1255 | */ | |
1256 | void (*disable)(struct drm_i915_private *dev_priv, | |
1257 | struct i915_power_well *power_well); | |
1258 | /* Returns the hw enabled state. */ | |
1259 | bool (*is_enabled)(struct drm_i915_private *dev_priv, | |
1260 | struct i915_power_well *power_well); | |
1261 | }; | |
1262 | ||
a38911a3 WX |
1263 | /* Power well structure for haswell */ |
1264 | struct i915_power_well { | |
c1ca727f | 1265 | const char *name; |
6f3ef5dd | 1266 | bool always_on; |
a38911a3 WX |
1267 | /* power well enable/disable usage count */ |
1268 | int count; | |
bfafe93a ID |
1269 | /* cached hw enabled state */ |
1270 | bool hw_enabled; | |
c1ca727f | 1271 | unsigned long domains; |
77961eb9 | 1272 | unsigned long data; |
c6cb582e | 1273 | const struct i915_power_well_ops *ops; |
a38911a3 WX |
1274 | }; |
1275 | ||
83c00f55 | 1276 | struct i915_power_domains { |
baa70707 ID |
1277 | /* |
1278 | * Power wells needed for initialization at driver init and suspend | |
1279 | * time are on. They are kept on until after the first modeset. | |
1280 | */ | |
1281 | bool init_power_on; | |
0d116a29 | 1282 | bool initializing; |
c1ca727f | 1283 | int power_well_count; |
baa70707 | 1284 | |
83c00f55 | 1285 | struct mutex lock; |
1da51581 | 1286 | int domain_use_count[POWER_DOMAIN_NUM]; |
c1ca727f | 1287 | struct i915_power_well *power_wells; |
83c00f55 ID |
1288 | }; |
1289 | ||
35a85ac6 | 1290 | #define MAX_L3_SLICES 2 |
a4da4fa4 | 1291 | struct intel_l3_parity { |
35a85ac6 | 1292 | u32 *remap_info[MAX_L3_SLICES]; |
a4da4fa4 | 1293 | struct work_struct error_work; |
35a85ac6 | 1294 | int which_slice; |
a4da4fa4 DV |
1295 | }; |
1296 | ||
4b5aed62 | 1297 | struct i915_gem_mm { |
4b5aed62 DV |
1298 | /** Memory allocator for GTT stolen memory */ |
1299 | struct drm_mm stolen; | |
92e97d2f PZ |
1300 | /** Protects the usage of the GTT stolen memory allocator. This is |
1301 | * always the inner lock when overlapping with struct_mutex. */ | |
1302 | struct mutex stolen_lock; | |
1303 | ||
4b5aed62 DV |
1304 | /** List of all objects in gtt_space. Used to restore gtt |
1305 | * mappings on resume */ | |
1306 | struct list_head bound_list; | |
1307 | /** | |
1308 | * List of objects which are not bound to the GTT (thus | |
1309 | * are idle and not used by the GPU) but still have | |
1310 | * (presumably uncached) pages still attached. | |
1311 | */ | |
1312 | struct list_head unbound_list; | |
1313 | ||
1314 | /** Usable portion of the GTT for GEM */ | |
1315 | unsigned long stolen_base; /* limited to low memory (32-bit) */ | |
1316 | ||
4b5aed62 DV |
1317 | /** PPGTT used for aliasing the PPGTT with the GTT */ |
1318 | struct i915_hw_ppgtt *aliasing_ppgtt; | |
1319 | ||
2cfcd32a | 1320 | struct notifier_block oom_notifier; |
e87666b5 | 1321 | struct notifier_block vmap_notifier; |
ceabbba5 | 1322 | struct shrinker shrinker; |
4b5aed62 DV |
1323 | bool shrinker_no_lock_stealing; |
1324 | ||
4b5aed62 DV |
1325 | /** LRU list of objects with fence regs on them. */ |
1326 | struct list_head fence_list; | |
1327 | ||
4b5aed62 DV |
1328 | /** |
1329 | * Are we in a non-interruptible section of code like | |
1330 | * modesetting? | |
1331 | */ | |
1332 | bool interruptible; | |
1333 | ||
bdf1e7e3 | 1334 | /* the indicator for dispatch video commands on two BSD rings */ |
de1add36 | 1335 | unsigned int bsd_ring_dispatch_index; |
bdf1e7e3 | 1336 | |
4b5aed62 DV |
1337 | /** Bit 6 swizzling required for X tiling */ |
1338 | uint32_t bit_6_swizzle_x; | |
1339 | /** Bit 6 swizzling required for Y tiling */ | |
1340 | uint32_t bit_6_swizzle_y; | |
1341 | ||
4b5aed62 | 1342 | /* accounting, useful for userland debugging */ |
c20e8355 | 1343 | spinlock_t object_stat_lock; |
4b5aed62 DV |
1344 | size_t object_memory; |
1345 | u32 object_count; | |
1346 | }; | |
1347 | ||
edc3d884 | 1348 | struct drm_i915_error_state_buf { |
0a4cd7c8 | 1349 | struct drm_i915_private *i915; |
edc3d884 MK |
1350 | unsigned bytes; |
1351 | unsigned size; | |
1352 | int err; | |
1353 | u8 *buf; | |
1354 | loff_t start; | |
1355 | loff_t pos; | |
1356 | }; | |
1357 | ||
fc16b48b MK |
1358 | struct i915_error_state_file_priv { |
1359 | struct drm_device *dev; | |
1360 | struct drm_i915_error_state *error; | |
1361 | }; | |
1362 | ||
99584db3 DV |
1363 | struct i915_gpu_error { |
1364 | /* For hangcheck timer */ | |
1365 | #define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */ | |
1366 | #define DRM_I915_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD) | |
be62acb4 MK |
1367 | /* Hang gpu twice in this window and your context gets banned */ |
1368 | #define DRM_I915_CTX_BAN_PERIOD DIV_ROUND_UP(8*DRM_I915_HANGCHECK_PERIOD, 1000) | |
1369 | ||
737b1506 | 1370 | struct delayed_work hangcheck_work; |
99584db3 DV |
1371 | |
1372 | /* For reset and error_state handling. */ | |
1373 | spinlock_t lock; | |
1374 | /* Protected by the above dev->gpu_error.lock. */ | |
1375 | struct drm_i915_error_state *first_error; | |
094f9a54 CW |
1376 | |
1377 | unsigned long missed_irq_rings; | |
1378 | ||
1f83fee0 | 1379 | /** |
2ac0f450 | 1380 | * State variable controlling the reset flow and count |
1f83fee0 | 1381 | * |
2ac0f450 MK |
1382 | * This is a counter which gets incremented when reset is triggered, |
1383 | * and again when reset has been handled. So odd values (lowest bit set) | |
1384 | * means that reset is in progress and even values that | |
1385 | * (reset_counter >> 1):th reset was successfully completed. | |
1386 | * | |
1387 | * If reset is not completed succesfully, the I915_WEDGE bit is | |
1388 | * set meaning that hardware is terminally sour and there is no | |
1389 | * recovery. All waiters on the reset_queue will be woken when | |
1390 | * that happens. | |
1391 | * | |
1392 | * This counter is used by the wait_seqno code to notice that reset | |
1393 | * event happened and it needs to restart the entire ioctl (since most | |
1394 | * likely the seqno it waited for won't ever signal anytime soon). | |
f69061be DV |
1395 | * |
1396 | * This is important for lock-free wait paths, where no contended lock | |
1397 | * naturally enforces the correct ordering between the bail-out of the | |
1398 | * waiter and the gpu reset work code. | |
1f83fee0 DV |
1399 | */ |
1400 | atomic_t reset_counter; | |
1401 | ||
1f83fee0 | 1402 | #define I915_RESET_IN_PROGRESS_FLAG 1 |
2ac0f450 | 1403 | #define I915_WEDGED (1 << 31) |
1f83fee0 | 1404 | |
1f15b76f CW |
1405 | /** |
1406 | * Waitqueue to signal when a hang is detected. Used to for waiters | |
1407 | * to release the struct_mutex for the reset to procede. | |
1408 | */ | |
1409 | wait_queue_head_t wait_queue; | |
1410 | ||
1f83fee0 DV |
1411 | /** |
1412 | * Waitqueue to signal when the reset has completed. Used by clients | |
1413 | * that wait for dev_priv->mm.wedged to settle. | |
1414 | */ | |
1415 | wait_queue_head_t reset_queue; | |
33196ded | 1416 | |
094f9a54 | 1417 | /* For missed irq/seqno simulation. */ |
688e6c72 | 1418 | unsigned long test_irq_rings; |
99584db3 DV |
1419 | }; |
1420 | ||
b8efb17b ZR |
1421 | enum modeset_restore { |
1422 | MODESET_ON_LID_OPEN, | |
1423 | MODESET_DONE, | |
1424 | MODESET_SUSPENDED, | |
1425 | }; | |
1426 | ||
500ea70d RV |
1427 | #define DP_AUX_A 0x40 |
1428 | #define DP_AUX_B 0x10 | |
1429 | #define DP_AUX_C 0x20 | |
1430 | #define DP_AUX_D 0x30 | |
1431 | ||
11c1b657 XZ |
1432 | #define DDC_PIN_B 0x05 |
1433 | #define DDC_PIN_C 0x04 | |
1434 | #define DDC_PIN_D 0x06 | |
1435 | ||
6acab15a | 1436 | struct ddi_vbt_port_info { |
ce4dd49e DL |
1437 | /* |
1438 | * This is an index in the HDMI/DVI DDI buffer translation table. | |
1439 | * The special value HDMI_LEVEL_SHIFT_UNKNOWN means the VBT didn't | |
1440 | * populate this field. | |
1441 | */ | |
1442 | #define HDMI_LEVEL_SHIFT_UNKNOWN 0xff | |
6acab15a | 1443 | uint8_t hdmi_level_shift; |
311a2094 PZ |
1444 | |
1445 | uint8_t supports_dvi:1; | |
1446 | uint8_t supports_hdmi:1; | |
1447 | uint8_t supports_dp:1; | |
500ea70d RV |
1448 | |
1449 | uint8_t alternate_aux_channel; | |
11c1b657 | 1450 | uint8_t alternate_ddc_pin; |
75067dde AK |
1451 | |
1452 | uint8_t dp_boost_level; | |
1453 | uint8_t hdmi_boost_level; | |
6acab15a PZ |
1454 | }; |
1455 | ||
bfd7ebda RV |
1456 | enum psr_lines_to_wait { |
1457 | PSR_0_LINES_TO_WAIT = 0, | |
1458 | PSR_1_LINE_TO_WAIT, | |
1459 | PSR_4_LINES_TO_WAIT, | |
1460 | PSR_8_LINES_TO_WAIT | |
83a7280e PB |
1461 | }; |
1462 | ||
41aa3448 RV |
1463 | struct intel_vbt_data { |
1464 | struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */ | |
1465 | struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */ | |
1466 | ||
1467 | /* Feature bits */ | |
1468 | unsigned int int_tv_support:1; | |
1469 | unsigned int lvds_dither:1; | |
1470 | unsigned int lvds_vbt:1; | |
1471 | unsigned int int_crt_support:1; | |
1472 | unsigned int lvds_use_ssc:1; | |
1473 | unsigned int display_clock_mode:1; | |
1474 | unsigned int fdi_rx_polarity_inverted:1; | |
3e845c7a | 1475 | unsigned int panel_type:4; |
41aa3448 RV |
1476 | int lvds_ssc_freq; |
1477 | unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */ | |
1478 | ||
83a7280e PB |
1479 | enum drrs_support_type drrs_type; |
1480 | ||
6aa23e65 JN |
1481 | struct { |
1482 | int rate; | |
1483 | int lanes; | |
1484 | int preemphasis; | |
1485 | int vswing; | |
06411f08 | 1486 | bool low_vswing; |
6aa23e65 JN |
1487 | bool initialized; |
1488 | bool support; | |
1489 | int bpp; | |
1490 | struct edp_power_seq pps; | |
1491 | } edp; | |
41aa3448 | 1492 | |
bfd7ebda RV |
1493 | struct { |
1494 | bool full_link; | |
1495 | bool require_aux_wakeup; | |
1496 | int idle_frames; | |
1497 | enum psr_lines_to_wait lines_to_wait; | |
1498 | int tp1_wakeup_time; | |
1499 | int tp2_tp3_wakeup_time; | |
1500 | } psr; | |
1501 | ||
f00076d2 JN |
1502 | struct { |
1503 | u16 pwm_freq_hz; | |
39fbc9c8 | 1504 | bool present; |
f00076d2 | 1505 | bool active_low_pwm; |
1de6068e | 1506 | u8 min_brightness; /* min_brightness/255 of max */ |
9a41e17d | 1507 | enum intel_backlight_type type; |
f00076d2 JN |
1508 | } backlight; |
1509 | ||
d17c5443 SK |
1510 | /* MIPI DSI */ |
1511 | struct { | |
1512 | u16 panel_id; | |
d3b542fc SK |
1513 | struct mipi_config *config; |
1514 | struct mipi_pps_data *pps; | |
1515 | u8 seq_version; | |
1516 | u32 size; | |
1517 | u8 *data; | |
8d3ed2f3 | 1518 | const u8 *sequence[MIPI_SEQ_MAX]; |
d17c5443 SK |
1519 | } dsi; |
1520 | ||
41aa3448 RV |
1521 | int crt_ddc_pin; |
1522 | ||
1523 | int child_dev_num; | |
768f69c9 | 1524 | union child_device_config *child_dev; |
6acab15a PZ |
1525 | |
1526 | struct ddi_vbt_port_info ddi_port_info[I915_MAX_PORTS]; | |
9d6c875d | 1527 | struct sdvo_device_mapping sdvo_mappings[2]; |
41aa3448 RV |
1528 | }; |
1529 | ||
77c122bc VS |
1530 | enum intel_ddb_partitioning { |
1531 | INTEL_DDB_PART_1_2, | |
1532 | INTEL_DDB_PART_5_6, /* IVB+ */ | |
1533 | }; | |
1534 | ||
1fd527cc VS |
1535 | struct intel_wm_level { |
1536 | bool enable; | |
1537 | uint32_t pri_val; | |
1538 | uint32_t spr_val; | |
1539 | uint32_t cur_val; | |
1540 | uint32_t fbc_val; | |
1541 | }; | |
1542 | ||
820c1980 | 1543 | struct ilk_wm_values { |
609cedef VS |
1544 | uint32_t wm_pipe[3]; |
1545 | uint32_t wm_lp[3]; | |
1546 | uint32_t wm_lp_spr[3]; | |
1547 | uint32_t wm_linetime[3]; | |
1548 | bool enable_fbc_wm; | |
1549 | enum intel_ddb_partitioning partitioning; | |
1550 | }; | |
1551 | ||
262cd2e1 VS |
1552 | struct vlv_pipe_wm { |
1553 | uint16_t primary; | |
1554 | uint16_t sprite[2]; | |
1555 | uint8_t cursor; | |
1556 | }; | |
ae80152d | 1557 | |
262cd2e1 VS |
1558 | struct vlv_sr_wm { |
1559 | uint16_t plane; | |
1560 | uint8_t cursor; | |
1561 | }; | |
ae80152d | 1562 | |
262cd2e1 VS |
1563 | struct vlv_wm_values { |
1564 | struct vlv_pipe_wm pipe[3]; | |
1565 | struct vlv_sr_wm sr; | |
0018fda1 VS |
1566 | struct { |
1567 | uint8_t cursor; | |
1568 | uint8_t sprite[2]; | |
1569 | uint8_t primary; | |
1570 | } ddl[3]; | |
6eb1a681 VS |
1571 | uint8_t level; |
1572 | bool cxsr; | |
0018fda1 VS |
1573 | }; |
1574 | ||
c193924e | 1575 | struct skl_ddb_entry { |
16160e3d | 1576 | uint16_t start, end; /* in number of blocks, 'end' is exclusive */ |
c193924e DL |
1577 | }; |
1578 | ||
1579 | static inline uint16_t skl_ddb_entry_size(const struct skl_ddb_entry *entry) | |
1580 | { | |
16160e3d | 1581 | return entry->end - entry->start; |
c193924e DL |
1582 | } |
1583 | ||
08db6652 DL |
1584 | static inline bool skl_ddb_entry_equal(const struct skl_ddb_entry *e1, |
1585 | const struct skl_ddb_entry *e2) | |
1586 | { | |
1587 | if (e1->start == e2->start && e1->end == e2->end) | |
1588 | return true; | |
1589 | ||
1590 | return false; | |
1591 | } | |
1592 | ||
c193924e | 1593 | struct skl_ddb_allocation { |
34bb56af | 1594 | struct skl_ddb_entry pipe[I915_MAX_PIPES]; |
2cd601c6 | 1595 | struct skl_ddb_entry plane[I915_MAX_PIPES][I915_MAX_PLANES]; /* packed/uv */ |
4969d33e | 1596 | struct skl_ddb_entry y_plane[I915_MAX_PIPES][I915_MAX_PLANES]; |
c193924e DL |
1597 | }; |
1598 | ||
2ac96d2a | 1599 | struct skl_wm_values { |
2b4b9f35 | 1600 | unsigned dirty_pipes; |
c193924e | 1601 | struct skl_ddb_allocation ddb; |
2ac96d2a PB |
1602 | uint32_t wm_linetime[I915_MAX_PIPES]; |
1603 | uint32_t plane[I915_MAX_PIPES][I915_MAX_PLANES][8]; | |
2ac96d2a | 1604 | uint32_t plane_trans[I915_MAX_PIPES][I915_MAX_PLANES]; |
2ac96d2a PB |
1605 | }; |
1606 | ||
1607 | struct skl_wm_level { | |
1608 | bool plane_en[I915_MAX_PLANES]; | |
1609 | uint16_t plane_res_b[I915_MAX_PLANES]; | |
1610 | uint8_t plane_res_l[I915_MAX_PLANES]; | |
2ac96d2a PB |
1611 | }; |
1612 | ||
c67a470b | 1613 | /* |
765dab67 PZ |
1614 | * This struct helps tracking the state needed for runtime PM, which puts the |
1615 | * device in PCI D3 state. Notice that when this happens, nothing on the | |
1616 | * graphics device works, even register access, so we don't get interrupts nor | |
1617 | * anything else. | |
c67a470b | 1618 | * |
765dab67 PZ |
1619 | * Every piece of our code that needs to actually touch the hardware needs to |
1620 | * either call intel_runtime_pm_get or call intel_display_power_get with the | |
1621 | * appropriate power domain. | |
a8a8bd54 | 1622 | * |
765dab67 PZ |
1623 | * Our driver uses the autosuspend delay feature, which means we'll only really |
1624 | * suspend if we stay with zero refcount for a certain amount of time. The | |
f458ebbc | 1625 | * default value is currently very conservative (see intel_runtime_pm_enable), but |
765dab67 | 1626 | * it can be changed with the standard runtime PM files from sysfs. |
c67a470b PZ |
1627 | * |
1628 | * The irqs_disabled variable becomes true exactly after we disable the IRQs and | |
1629 | * goes back to false exactly before we reenable the IRQs. We use this variable | |
1630 | * to check if someone is trying to enable/disable IRQs while they're supposed | |
1631 | * to be disabled. This shouldn't happen and we'll print some error messages in | |
730488b2 | 1632 | * case it happens. |
c67a470b | 1633 | * |
765dab67 | 1634 | * For more, read the Documentation/power/runtime_pm.txt. |
c67a470b | 1635 | */ |
5d584b2e | 1636 | struct i915_runtime_pm { |
1f814dac | 1637 | atomic_t wakeref_count; |
2b19efeb | 1638 | atomic_t atomic_seq; |
5d584b2e | 1639 | bool suspended; |
2aeb7d3a | 1640 | bool irqs_enabled; |
c67a470b PZ |
1641 | }; |
1642 | ||
926321d5 DV |
1643 | enum intel_pipe_crc_source { |
1644 | INTEL_PIPE_CRC_SOURCE_NONE, | |
1645 | INTEL_PIPE_CRC_SOURCE_PLANE1, | |
1646 | INTEL_PIPE_CRC_SOURCE_PLANE2, | |
1647 | INTEL_PIPE_CRC_SOURCE_PF, | |
5b3a856b | 1648 | INTEL_PIPE_CRC_SOURCE_PIPE, |
3d099a05 DV |
1649 | /* TV/DP on pre-gen5/vlv can't use the pipe source. */ |
1650 | INTEL_PIPE_CRC_SOURCE_TV, | |
1651 | INTEL_PIPE_CRC_SOURCE_DP_B, | |
1652 | INTEL_PIPE_CRC_SOURCE_DP_C, | |
1653 | INTEL_PIPE_CRC_SOURCE_DP_D, | |
46a19188 | 1654 | INTEL_PIPE_CRC_SOURCE_AUTO, |
926321d5 DV |
1655 | INTEL_PIPE_CRC_SOURCE_MAX, |
1656 | }; | |
1657 | ||
8bf1e9f1 | 1658 | struct intel_pipe_crc_entry { |
ac2300d4 | 1659 | uint32_t frame; |
8bf1e9f1 SH |
1660 | uint32_t crc[5]; |
1661 | }; | |
1662 | ||
b2c88f5b | 1663 | #define INTEL_PIPE_CRC_ENTRIES_NR 128 |
8bf1e9f1 | 1664 | struct intel_pipe_crc { |
d538bbdf DL |
1665 | spinlock_t lock; |
1666 | bool opened; /* exclusive access to the result file */ | |
e5f75aca | 1667 | struct intel_pipe_crc_entry *entries; |
926321d5 | 1668 | enum intel_pipe_crc_source source; |
d538bbdf | 1669 | int head, tail; |
07144428 | 1670 | wait_queue_head_t wq; |
8bf1e9f1 SH |
1671 | }; |
1672 | ||
f99d7069 DV |
1673 | struct i915_frontbuffer_tracking { |
1674 | struct mutex lock; | |
1675 | ||
1676 | /* | |
1677 | * Tracking bits for delayed frontbuffer flushing du to gpu activity or | |
1678 | * scheduled flips. | |
1679 | */ | |
1680 | unsigned busy_bits; | |
1681 | unsigned flip_bits; | |
1682 | }; | |
1683 | ||
7225342a | 1684 | struct i915_wa_reg { |
f0f59a00 | 1685 | i915_reg_t addr; |
7225342a MK |
1686 | u32 value; |
1687 | /* bitmask representing WA bits */ | |
1688 | u32 mask; | |
1689 | }; | |
1690 | ||
33136b06 AS |
1691 | /* |
1692 | * RING_MAX_NONPRIV_SLOTS is per-engine but at this point we are only | |
1693 | * allowing it for RCS as we don't foresee any requirement of having | |
1694 | * a whitelist for other engines. When it is really required for | |
1695 | * other engines then the limit need to be increased. | |
1696 | */ | |
1697 | #define I915_MAX_WA_REGS (16 + RING_MAX_NONPRIV_SLOTS) | |
7225342a MK |
1698 | |
1699 | struct i915_workarounds { | |
1700 | struct i915_wa_reg reg[I915_MAX_WA_REGS]; | |
1701 | u32 count; | |
666796da | 1702 | u32 hw_whitelist_count[I915_NUM_ENGINES]; |
7225342a MK |
1703 | }; |
1704 | ||
cf9d2890 YZ |
1705 | struct i915_virtual_gpu { |
1706 | bool active; | |
1707 | }; | |
1708 | ||
5f19e2bf JH |
1709 | struct i915_execbuffer_params { |
1710 | struct drm_device *dev; | |
1711 | struct drm_file *file; | |
1712 | uint32_t dispatch_flags; | |
1713 | uint32_t args_batch_start_offset; | |
af98714e | 1714 | uint64_t batch_obj_vm_offset; |
4a570db5 | 1715 | struct intel_engine_cs *engine; |
5f19e2bf | 1716 | struct drm_i915_gem_object *batch_obj; |
e2efd130 | 1717 | struct i915_gem_context *ctx; |
6a6ae79a | 1718 | struct drm_i915_gem_request *request; |
5f19e2bf JH |
1719 | }; |
1720 | ||
aa363136 MR |
1721 | /* used in computing the new watermarks state */ |
1722 | struct intel_wm_config { | |
1723 | unsigned int num_pipes_active; | |
1724 | bool sprites_enabled; | |
1725 | bool sprites_scaled; | |
1726 | }; | |
1727 | ||
77fec556 | 1728 | struct drm_i915_private { |
8f460e2c CW |
1729 | struct drm_device drm; |
1730 | ||
efab6d8d | 1731 | struct kmem_cache *objects; |
e20d2ab7 | 1732 | struct kmem_cache *vmas; |
efab6d8d | 1733 | struct kmem_cache *requests; |
f4c956ad | 1734 | |
5c969aa7 | 1735 | const struct intel_device_info info; |
f4c956ad DV |
1736 | |
1737 | int relative_constants_mode; | |
1738 | ||
1739 | void __iomem *regs; | |
1740 | ||
907b28c5 | 1741 | struct intel_uncore uncore; |
f4c956ad | 1742 | |
cf9d2890 YZ |
1743 | struct i915_virtual_gpu vgpu; |
1744 | ||
0ad35fed ZW |
1745 | struct intel_gvt gvt; |
1746 | ||
33a732f4 AD |
1747 | struct intel_guc guc; |
1748 | ||
eb805623 DV |
1749 | struct intel_csr csr; |
1750 | ||
5ea6e5e3 | 1751 | struct intel_gmbus gmbus[GMBUS_NUM_PINS]; |
28c70f16 | 1752 | |
f4c956ad DV |
1753 | /** gmbus_mutex protects against concurrent usage of the single hw gmbus |
1754 | * controller on different i2c buses. */ | |
1755 | struct mutex gmbus_mutex; | |
1756 | ||
1757 | /** | |
1758 | * Base address of the gmbus and gpio block. | |
1759 | */ | |
1760 | uint32_t gpio_mmio_base; | |
1761 | ||
b6fdd0f2 SS |
1762 | /* MMIO base address for MIPI regs */ |
1763 | uint32_t mipi_mmio_base; | |
1764 | ||
443a389f VS |
1765 | uint32_t psr_mmio_base; |
1766 | ||
28c70f16 DV |
1767 | wait_queue_head_t gmbus_wait_queue; |
1768 | ||
f4c956ad | 1769 | struct pci_dev *bridge_dev; |
0ca5fa3a | 1770 | struct i915_gem_context *kernel_context; |
666796da | 1771 | struct intel_engine_cs engine[I915_NUM_ENGINES]; |
3e78998a | 1772 | struct drm_i915_gem_object *semaphore_obj; |
f72b3435 | 1773 | uint32_t last_seqno, next_seqno; |
f4c956ad | 1774 | |
ba8286fa | 1775 | struct drm_dma_handle *status_page_dmah; |
f4c956ad DV |
1776 | struct resource mch_res; |
1777 | ||
f4c956ad DV |
1778 | /* protects the irq masks */ |
1779 | spinlock_t irq_lock; | |
1780 | ||
84c33a64 SG |
1781 | /* protects the mmio flip data */ |
1782 | spinlock_t mmio_flip_lock; | |
1783 | ||
f8b79e58 ID |
1784 | bool display_irqs_enabled; |
1785 | ||
9ee32fea DV |
1786 | /* To control wakeup latency, e.g. for irq-driven dp aux transfers. */ |
1787 | struct pm_qos_request pm_qos; | |
1788 | ||
a580516d VS |
1789 | /* Sideband mailbox protection */ |
1790 | struct mutex sb_lock; | |
f4c956ad DV |
1791 | |
1792 | /** Cached value of IMR to avoid reads in updating the bitfield */ | |
abd58f01 BW |
1793 | union { |
1794 | u32 irq_mask; | |
1795 | u32 de_irq_mask[I915_MAX_PIPES]; | |
1796 | }; | |
f4c956ad | 1797 | u32 gt_irq_mask; |
605cd25b | 1798 | u32 pm_irq_mask; |
a6706b45 | 1799 | u32 pm_rps_events; |
91d181dd | 1800 | u32 pipestat_irq_mask[I915_MAX_PIPES]; |
f4c956ad | 1801 | |
5fcece80 | 1802 | struct i915_hotplug hotplug; |
ab34a7e8 | 1803 | struct intel_fbc fbc; |
439d7ac0 | 1804 | struct i915_drrs drrs; |
f4c956ad | 1805 | struct intel_opregion opregion; |
41aa3448 | 1806 | struct intel_vbt_data vbt; |
f4c956ad | 1807 | |
d9ceb816 JB |
1808 | bool preserve_bios_swizzle; |
1809 | ||
f4c956ad DV |
1810 | /* overlay */ |
1811 | struct intel_overlay *overlay; | |
f4c956ad | 1812 | |
58c68779 | 1813 | /* backlight registers and fields in struct intel_panel */ |
07f11d49 | 1814 | struct mutex backlight_lock; |
31ad8ec6 | 1815 | |
f4c956ad | 1816 | /* LVDS info */ |
f4c956ad DV |
1817 | bool no_aux_handshake; |
1818 | ||
e39b999a VS |
1819 | /* protects panel power sequencer state */ |
1820 | struct mutex pps_mutex; | |
1821 | ||
f4c956ad | 1822 | struct drm_i915_fence_reg fence_regs[I915_MAX_NUM_FENCES]; /* assume 965 */ |
f4c956ad DV |
1823 | int num_fence_regs; /* 8 on pre-965, 16 otherwise */ |
1824 | ||
1825 | unsigned int fsb_freq, mem_freq, is_ddr3; | |
b2045352 | 1826 | unsigned int skl_preferred_vco_freq; |
1a617b77 | 1827 | unsigned int cdclk_freq, max_cdclk_freq, atomic_cdclk_freq; |
adafdc6f | 1828 | unsigned int max_dotclk_freq; |
e7dc33f3 | 1829 | unsigned int rawclk_freq; |
6bcda4f0 | 1830 | unsigned int hpll_freq; |
bfa7df01 | 1831 | unsigned int czclk_freq; |
f4c956ad | 1832 | |
63911d72 | 1833 | struct { |
709e05c3 | 1834 | unsigned int vco, ref; |
63911d72 VS |
1835 | } cdclk_pll; |
1836 | ||
645416f5 DV |
1837 | /** |
1838 | * wq - Driver workqueue for GEM. | |
1839 | * | |
1840 | * NOTE: Work items scheduled here are not allowed to grab any modeset | |
1841 | * locks, for otherwise the flushing done in the pageflip code will | |
1842 | * result in deadlocks. | |
1843 | */ | |
f4c956ad DV |
1844 | struct workqueue_struct *wq; |
1845 | ||
1846 | /* Display functions */ | |
1847 | struct drm_i915_display_funcs display; | |
1848 | ||
1849 | /* PCH chipset type */ | |
1850 | enum intel_pch pch_type; | |
17a303ec | 1851 | unsigned short pch_id; |
f4c956ad DV |
1852 | |
1853 | unsigned long quirks; | |
1854 | ||
b8efb17b ZR |
1855 | enum modeset_restore modeset_restore; |
1856 | struct mutex modeset_restore_lock; | |
e2c8b870 | 1857 | struct drm_atomic_state *modeset_restore_state; |
dfa29970 | 1858 | struct drm_modeset_acquire_ctx reset_ctx; |
673a394b | 1859 | |
a7bbbd63 | 1860 | struct list_head vm_list; /* Global list of all address spaces */ |
62106b4f | 1861 | struct i915_ggtt ggtt; /* VM representing the global address space */ |
5d4545ae | 1862 | |
4b5aed62 | 1863 | struct i915_gem_mm mm; |
ad46cb53 CW |
1864 | DECLARE_HASHTABLE(mm_structs, 7); |
1865 | struct mutex mm_lock; | |
8781342d | 1866 | |
5d1808ec CW |
1867 | /* The hw wants to have a stable context identifier for the lifetime |
1868 | * of the context (for OA, PASID, faults, etc). This is limited | |
1869 | * in execlists to 21 bits. | |
1870 | */ | |
1871 | struct ida context_hw_ida; | |
1872 | #define MAX_CONTEXT_HW_ID (1<<21) /* exclusive */ | |
1873 | ||
8781342d DV |
1874 | /* Kernel Modesetting */ |
1875 | ||
76c4ac04 DL |
1876 | struct drm_crtc *plane_to_crtc_mapping[I915_MAX_PIPES]; |
1877 | struct drm_crtc *pipe_to_crtc_mapping[I915_MAX_PIPES]; | |
6b95a207 KH |
1878 | wait_queue_head_t pending_flip_queue; |
1879 | ||
c4597872 DV |
1880 | #ifdef CONFIG_DEBUG_FS |
1881 | struct intel_pipe_crc pipe_crc[I915_MAX_PIPES]; | |
1882 | #endif | |
1883 | ||
565602d7 | 1884 | /* dpll and cdclk state is protected by connection_mutex */ |
e72f9fbf DV |
1885 | int num_shared_dpll; |
1886 | struct intel_shared_dpll shared_dplls[I915_NUM_PLLS]; | |
f9476a6c | 1887 | const struct intel_dpll_mgr *dpll_mgr; |
565602d7 | 1888 | |
fbf6d879 ML |
1889 | /* |
1890 | * dpll_lock serializes intel_{prepare,enable,disable}_shared_dpll. | |
1891 | * Must be global rather than per dpll, because on some platforms | |
1892 | * plls share registers. | |
1893 | */ | |
1894 | struct mutex dpll_lock; | |
1895 | ||
565602d7 ML |
1896 | unsigned int active_crtcs; |
1897 | unsigned int min_pixclk[I915_MAX_PIPES]; | |
1898 | ||
e4607fcf | 1899 | int dpio_phy_iosf_port[I915_NUM_PHYS_VLV]; |
ee7b9f93 | 1900 | |
7225342a | 1901 | struct i915_workarounds workarounds; |
888b5995 | 1902 | |
f99d7069 DV |
1903 | struct i915_frontbuffer_tracking fb_tracking; |
1904 | ||
652c393a | 1905 | u16 orig_clock; |
f97108d1 | 1906 | |
c4804411 | 1907 | bool mchbar_need_disable; |
f97108d1 | 1908 | |
a4da4fa4 DV |
1909 | struct intel_l3_parity l3_parity; |
1910 | ||
59124506 | 1911 | /* Cannot be determined by PCIID. You must always read a register. */ |
3accaf7e | 1912 | u32 edram_cap; |
59124506 | 1913 | |
c6a828d3 | 1914 | /* gen6+ rps state */ |
c85aa885 | 1915 | struct intel_gen6_power_mgmt rps; |
c6a828d3 | 1916 | |
20e4d407 DV |
1917 | /* ilk-only ips/rps state. Everything in here is protected by the global |
1918 | * mchdev_lock in intel_pm.c */ | |
c85aa885 | 1919 | struct intel_ilk_power_mgmt ips; |
b5e50c3f | 1920 | |
83c00f55 | 1921 | struct i915_power_domains power_domains; |
a38911a3 | 1922 | |
a031d709 | 1923 | struct i915_psr psr; |
3f51e471 | 1924 | |
99584db3 | 1925 | struct i915_gpu_error gpu_error; |
ae681d96 | 1926 | |
c9cddffc JB |
1927 | struct drm_i915_gem_object *vlv_pctx; |
1928 | ||
0695726e | 1929 | #ifdef CONFIG_DRM_FBDEV_EMULATION |
8be48d92 DA |
1930 | /* list of fbdev register on this device */ |
1931 | struct intel_fbdev *fbdev; | |
82e3b8c1 | 1932 | struct work_struct fbdev_suspend_work; |
4520f53a | 1933 | #endif |
e953fd7b CW |
1934 | |
1935 | struct drm_property *broadcast_rgb_property; | |
3f43c48d | 1936 | struct drm_property *force_audio_property; |
e3689190 | 1937 | |
58fddc28 | 1938 | /* hda/i915 audio component */ |
51e1d83c | 1939 | struct i915_audio_component *audio_component; |
58fddc28 | 1940 | bool audio_component_registered; |
4a21ef7d LY |
1941 | /** |
1942 | * av_mutex - mutex for audio/video sync | |
1943 | * | |
1944 | */ | |
1945 | struct mutex av_mutex; | |
58fddc28 | 1946 | |
254f965c | 1947 | uint32_t hw_context_size; |
a33afea5 | 1948 | struct list_head context_list; |
f4c956ad | 1949 | |
3e68320e | 1950 | u32 fdi_rx_config; |
68d18ad7 | 1951 | |
c231775c | 1952 | /* Shadow for DISPLAY_PHY_CONTROL which can't be safely read */ |
70722468 | 1953 | u32 chv_phy_control; |
c231775c VS |
1954 | /* |
1955 | * Shadows for CHV DPLL_MD regs to keep the state | |
1956 | * checker somewhat working in the presence hardware | |
1957 | * crappiness (can't read out DPLL_MD for pipes B & C). | |
1958 | */ | |
1959 | u32 chv_dpll_md[I915_MAX_PIPES]; | |
adc7f04b | 1960 | u32 bxt_phy_grc; |
70722468 | 1961 | |
842f1c8b | 1962 | u32 suspend_count; |
bc87229f | 1963 | bool suspended_to_idle; |
f4c956ad | 1964 | struct i915_suspend_saved_registers regfile; |
ddeea5b0 | 1965 | struct vlv_s0ix_state vlv_s0ix_state; |
231f42a4 | 1966 | |
f4033726 L |
1967 | enum { |
1968 | I915_SKL_SAGV_UNKNOWN = 0, | |
1969 | I915_SKL_SAGV_DISABLED, | |
1970 | I915_SKL_SAGV_ENABLED, | |
1971 | I915_SKL_SAGV_NOT_CONTROLLED | |
1972 | } skl_sagv_status; | |
1973 | ||
53615a5e VS |
1974 | struct { |
1975 | /* | |
1976 | * Raw watermark latency values: | |
1977 | * in 0.1us units for WM0, | |
1978 | * in 0.5us units for WM1+. | |
1979 | */ | |
1980 | /* primary */ | |
1981 | uint16_t pri_latency[5]; | |
1982 | /* sprite */ | |
1983 | uint16_t spr_latency[5]; | |
1984 | /* cursor */ | |
1985 | uint16_t cur_latency[5]; | |
2af30a5c PB |
1986 | /* |
1987 | * Raw watermark memory latency values | |
1988 | * for SKL for all 8 levels | |
1989 | * in 1us units. | |
1990 | */ | |
1991 | uint16_t skl_latency[8]; | |
609cedef | 1992 | |
2d41c0b5 PB |
1993 | /* |
1994 | * The skl_wm_values structure is a bit too big for stack | |
1995 | * allocation, so we keep the staging struct where we store | |
1996 | * intermediate results here instead. | |
1997 | */ | |
1998 | struct skl_wm_values skl_results; | |
1999 | ||
609cedef | 2000 | /* current hardware state */ |
2d41c0b5 PB |
2001 | union { |
2002 | struct ilk_wm_values hw; | |
2003 | struct skl_wm_values skl_hw; | |
0018fda1 | 2004 | struct vlv_wm_values vlv; |
2d41c0b5 | 2005 | }; |
58590c14 VS |
2006 | |
2007 | uint8_t max_level; | |
ed4a6a7c MR |
2008 | |
2009 | /* | |
2010 | * Should be held around atomic WM register writing; also | |
2011 | * protects * intel_crtc->wm.active and | |
2012 | * cstate->wm.need_postvbl_update. | |
2013 | */ | |
2014 | struct mutex wm_mutex; | |
279e99d7 MR |
2015 | |
2016 | /* | |
2017 | * Set during HW readout of watermarks/DDB. Some platforms | |
2018 | * need to know when we're still using BIOS-provided values | |
2019 | * (which we don't fully trust). | |
2020 | */ | |
2021 | bool distrust_bios_wm; | |
53615a5e VS |
2022 | } wm; |
2023 | ||
8a187455 PZ |
2024 | struct i915_runtime_pm pm; |
2025 | ||
a83014d3 OM |
2026 | /* Abstract the submission mechanism (legacy ringbuffer or execlists) away */ |
2027 | struct { | |
5f19e2bf | 2028 | int (*execbuf_submit)(struct i915_execbuffer_params *params, |
f3dc74c0 | 2029 | struct drm_i915_gem_execbuffer2 *args, |
5f19e2bf | 2030 | struct list_head *vmas); |
117897f4 TU |
2031 | int (*init_engines)(struct drm_device *dev); |
2032 | void (*cleanup_engine)(struct intel_engine_cs *engine); | |
2033 | void (*stop_engine)(struct intel_engine_cs *engine); | |
67d97da3 CW |
2034 | |
2035 | /** | |
2036 | * Is the GPU currently considered idle, or busy executing | |
2037 | * userspace requests? Whilst idle, we allow runtime power | |
2038 | * management to power down the hardware and display clocks. | |
2039 | * In order to reduce the effect on performance, there | |
2040 | * is a slight delay before we do so. | |
2041 | */ | |
2042 | unsigned int active_engines; | |
2043 | bool awake; | |
2044 | ||
2045 | /** | |
2046 | * We leave the user IRQ off as much as possible, | |
2047 | * but this means that requests will finish and never | |
2048 | * be retired once the system goes idle. Set a timer to | |
2049 | * fire periodically while the ring is running. When it | |
2050 | * fires, go retire requests. | |
2051 | */ | |
2052 | struct delayed_work retire_work; | |
2053 | ||
2054 | /** | |
2055 | * When we detect an idle GPU, we want to turn on | |
2056 | * powersaving features. So once we see that there | |
2057 | * are no more requests outstanding and no more | |
2058 | * arrive within a small period of time, we fire | |
2059 | * off the idle_work. | |
2060 | */ | |
2061 | struct delayed_work idle_work; | |
a83014d3 OM |
2062 | } gt; |
2063 | ||
3be60de9 VS |
2064 | /* perform PHY state sanity checks? */ |
2065 | bool chv_phy_assert[2]; | |
2066 | ||
0bdf5a05 TI |
2067 | struct intel_encoder *dig_port_map[I915_MAX_PORTS]; |
2068 | ||
bdf1e7e3 DV |
2069 | /* |
2070 | * NOTE: This is the dri1/ums dungeon, don't add stuff here. Your patch | |
2071 | * will be rejected. Instead look for a better place. | |
2072 | */ | |
77fec556 | 2073 | }; |
1da177e4 | 2074 | |
2c1792a1 CW |
2075 | static inline struct drm_i915_private *to_i915(const struct drm_device *dev) |
2076 | { | |
091387c1 | 2077 | return container_of(dev, struct drm_i915_private, drm); |
2c1792a1 CW |
2078 | } |
2079 | ||
888d0d42 ID |
2080 | static inline struct drm_i915_private *dev_to_i915(struct device *dev) |
2081 | { | |
2082 | return to_i915(dev_get_drvdata(dev)); | |
2083 | } | |
2084 | ||
33a732f4 AD |
2085 | static inline struct drm_i915_private *guc_to_i915(struct intel_guc *guc) |
2086 | { | |
2087 | return container_of(guc, struct drm_i915_private, guc); | |
2088 | } | |
2089 | ||
b4ac5afc DG |
2090 | /* Simple iterator over all initialised engines */ |
2091 | #define for_each_engine(engine__, dev_priv__) \ | |
2092 | for ((engine__) = &(dev_priv__)->engine[0]; \ | |
2093 | (engine__) < &(dev_priv__)->engine[I915_NUM_ENGINES]; \ | |
2094 | (engine__)++) \ | |
2095 | for_each_if (intel_engine_initialized(engine__)) | |
b4519513 | 2096 | |
c3232b18 DG |
2097 | /* Iterator with engine_id */ |
2098 | #define for_each_engine_id(engine__, dev_priv__, id__) \ | |
2099 | for ((engine__) = &(dev_priv__)->engine[0], (id__) = 0; \ | |
2100 | (engine__) < &(dev_priv__)->engine[I915_NUM_ENGINES]; \ | |
2101 | (engine__)++) \ | |
2102 | for_each_if (((id__) = (engine__)->id, \ | |
2103 | intel_engine_initialized(engine__))) | |
2104 | ||
2105 | /* Iterator over subset of engines selected by mask */ | |
ee4b6faf | 2106 | #define for_each_engine_masked(engine__, dev_priv__, mask__) \ |
b4ac5afc DG |
2107 | for ((engine__) = &(dev_priv__)->engine[0]; \ |
2108 | (engine__) < &(dev_priv__)->engine[I915_NUM_ENGINES]; \ | |
2109 | (engine__)++) \ | |
2110 | for_each_if (((mask__) & intel_engine_flag(engine__)) && \ | |
2111 | intel_engine_initialized(engine__)) | |
ee4b6faf | 2112 | |
b1d7e4b4 WF |
2113 | enum hdmi_force_audio { |
2114 | HDMI_AUDIO_OFF_DVI = -2, /* no aux data for HDMI-DVI converter */ | |
2115 | HDMI_AUDIO_OFF, /* force turn off HDMI audio */ | |
2116 | HDMI_AUDIO_AUTO, /* trust EDID */ | |
2117 | HDMI_AUDIO_ON, /* force turn on HDMI audio */ | |
2118 | }; | |
2119 | ||
190d6cd5 | 2120 | #define I915_GTT_OFFSET_NONE ((u32)-1) |
ed2f3452 | 2121 | |
37e680a1 | 2122 | struct drm_i915_gem_object_ops { |
de472664 CW |
2123 | unsigned int flags; |
2124 | #define I915_GEM_OBJECT_HAS_STRUCT_PAGE 0x1 | |
2125 | ||
37e680a1 CW |
2126 | /* Interface between the GEM object and its backing storage. |
2127 | * get_pages() is called once prior to the use of the associated set | |
2128 | * of pages before to binding them into the GTT, and put_pages() is | |
2129 | * called after we no longer need them. As we expect there to be | |
2130 | * associated cost with migrating pages between the backing storage | |
2131 | * and making them available for the GPU (e.g. clflush), we may hold | |
2132 | * onto the pages after they are no longer referenced by the GPU | |
2133 | * in case they may be used again shortly (for example migrating the | |
2134 | * pages to a different memory domain within the GTT). put_pages() | |
2135 | * will therefore most likely be called when the object itself is | |
2136 | * being released or under memory pressure (where we attempt to | |
2137 | * reap pages for the shrinker). | |
2138 | */ | |
2139 | int (*get_pages)(struct drm_i915_gem_object *); | |
2140 | void (*put_pages)(struct drm_i915_gem_object *); | |
de472664 | 2141 | |
5cc9ed4b CW |
2142 | int (*dmabuf_export)(struct drm_i915_gem_object *); |
2143 | void (*release)(struct drm_i915_gem_object *); | |
37e680a1 CW |
2144 | }; |
2145 | ||
a071fa00 DV |
2146 | /* |
2147 | * Frontbuffer tracking bits. Set in obj->frontbuffer_bits while a gem bo is | |
d1b9d039 | 2148 | * considered to be the frontbuffer for the given plane interface-wise. This |
a071fa00 DV |
2149 | * doesn't mean that the hw necessarily already scans it out, but that any |
2150 | * rendering (by the cpu or gpu) will land in the frontbuffer eventually. | |
2151 | * | |
2152 | * We have one bit per pipe and per scanout plane type. | |
2153 | */ | |
d1b9d039 SAK |
2154 | #define INTEL_MAX_SPRITE_BITS_PER_PIPE 5 |
2155 | #define INTEL_FRONTBUFFER_BITS_PER_PIPE 8 | |
a071fa00 DV |
2156 | #define INTEL_FRONTBUFFER_BITS \ |
2157 | (INTEL_FRONTBUFFER_BITS_PER_PIPE * I915_MAX_PIPES) | |
2158 | #define INTEL_FRONTBUFFER_PRIMARY(pipe) \ | |
2159 | (1 << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))) | |
2160 | #define INTEL_FRONTBUFFER_CURSOR(pipe) \ | |
d1b9d039 SAK |
2161 | (1 << (1 + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))) |
2162 | #define INTEL_FRONTBUFFER_SPRITE(pipe, plane) \ | |
2163 | (1 << (2 + plane + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))) | |
a071fa00 | 2164 | #define INTEL_FRONTBUFFER_OVERLAY(pipe) \ |
d1b9d039 | 2165 | (1 << (2 + INTEL_MAX_SPRITE_BITS_PER_PIPE + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))) |
cc36513c | 2166 | #define INTEL_FRONTBUFFER_ALL_MASK(pipe) \ |
d1b9d039 | 2167 | (0xff << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))) |
a071fa00 | 2168 | |
673a394b | 2169 | struct drm_i915_gem_object { |
c397b908 | 2170 | struct drm_gem_object base; |
673a394b | 2171 | |
37e680a1 CW |
2172 | const struct drm_i915_gem_object_ops *ops; |
2173 | ||
2f633156 BW |
2174 | /** List of VMAs backed by this object */ |
2175 | struct list_head vma_list; | |
2176 | ||
c1ad11fc CW |
2177 | /** Stolen memory for this object, instead of being backed by shmem. */ |
2178 | struct drm_mm_node *stolen; | |
35c20a60 | 2179 | struct list_head global_list; |
673a394b | 2180 | |
117897f4 | 2181 | struct list_head engine_list[I915_NUM_ENGINES]; |
b25cb2f8 BW |
2182 | /** Used in execbuf to temporarily hold a ref */ |
2183 | struct list_head obj_exec_link; | |
673a394b | 2184 | |
8d9d5744 | 2185 | struct list_head batch_pool_link; |
493018dc | 2186 | |
673a394b | 2187 | /** |
65ce3027 CW |
2188 | * This is set if the object is on the active lists (has pending |
2189 | * rendering and so a non-zero seqno), and is not set if it i s on | |
2190 | * inactive (ready to be unbound) list. | |
673a394b | 2191 | */ |
666796da | 2192 | unsigned int active:I915_NUM_ENGINES; |
673a394b EA |
2193 | |
2194 | /** | |
2195 | * This is set if the object has been written to since last bound | |
2196 | * to the GTT | |
2197 | */ | |
0206e353 | 2198 | unsigned int dirty:1; |
778c3544 DV |
2199 | |
2200 | /** | |
2201 | * Fence register bits (if any) for this object. Will be set | |
2202 | * as needed when mapped into the GTT. | |
2203 | * Protected by dev->struct_mutex. | |
778c3544 | 2204 | */ |
4b9de737 | 2205 | signed int fence_reg:I915_MAX_NUM_FENCE_BITS; |
778c3544 | 2206 | |
778c3544 DV |
2207 | /** |
2208 | * Advice: are the backing pages purgeable? | |
2209 | */ | |
0206e353 | 2210 | unsigned int madv:2; |
778c3544 | 2211 | |
778c3544 DV |
2212 | /** |
2213 | * Current tiling mode for the object. | |
2214 | */ | |
0206e353 | 2215 | unsigned int tiling_mode:2; |
5d82e3e6 CW |
2216 | /** |
2217 | * Whether the tiling parameters for the currently associated fence | |
2218 | * register have changed. Note that for the purposes of tracking | |
2219 | * tiling changes we also treat the unfenced register, the register | |
2220 | * slot that the object occupies whilst it executes a fenced | |
2221 | * command (such as BLT on gen2/3), as a "fence". | |
2222 | */ | |
2223 | unsigned int fence_dirty:1; | |
778c3544 | 2224 | |
75e9e915 DV |
2225 | /** |
2226 | * Is the object at the current location in the gtt mappable and | |
2227 | * fenceable? Used to avoid costly recalculations. | |
2228 | */ | |
0206e353 | 2229 | unsigned int map_and_fenceable:1; |
75e9e915 | 2230 | |
fb7d516a DV |
2231 | /** |
2232 | * Whether the current gtt mapping needs to be mappable (and isn't just | |
2233 | * mappable by accident). Track pin and fault separate for a more | |
2234 | * accurate mappable working set. | |
2235 | */ | |
0206e353 | 2236 | unsigned int fault_mappable:1; |
fb7d516a | 2237 | |
24f3a8cf AG |
2238 | /* |
2239 | * Is the object to be mapped as read-only to the GPU | |
2240 | * Only honoured if hardware has relevant pte bit | |
2241 | */ | |
2242 | unsigned long gt_ro:1; | |
651d794f | 2243 | unsigned int cache_level:3; |
0f71979a | 2244 | unsigned int cache_dirty:1; |
93dfb40c | 2245 | |
a071fa00 DV |
2246 | unsigned int frontbuffer_bits:INTEL_FRONTBUFFER_BITS; |
2247 | ||
aeecc969 | 2248 | unsigned int has_wc_mmap; |
8a0c39b1 TU |
2249 | unsigned int pin_display; |
2250 | ||
9da3da66 | 2251 | struct sg_table *pages; |
a5570178 | 2252 | int pages_pin_count; |
ee286370 CW |
2253 | struct get_page { |
2254 | struct scatterlist *sg; | |
2255 | int last; | |
2256 | } get_page; | |
0a798eb9 | 2257 | void *mapping; |
9a70cc2a | 2258 | |
b4716185 CW |
2259 | /** Breadcrumb of last rendering to the buffer. |
2260 | * There can only be one writer, but we allow for multiple readers. | |
2261 | * If there is a writer that necessarily implies that all other | |
2262 | * read requests are complete - but we may only be lazily clearing | |
2263 | * the read requests. A read request is naturally the most recent | |
2264 | * request on a ring, so we may have two different write and read | |
2265 | * requests on one ring where the write request is older than the | |
2266 | * read request. This allows for the CPU to read from an active | |
2267 | * buffer by only waiting for the write to complete. | |
2268 | * */ | |
666796da | 2269 | struct drm_i915_gem_request *last_read_req[I915_NUM_ENGINES]; |
97b2a6a1 | 2270 | struct drm_i915_gem_request *last_write_req; |
caea7476 | 2271 | /** Breadcrumb of last fenced GPU access to the buffer. */ |
97b2a6a1 | 2272 | struct drm_i915_gem_request *last_fenced_req; |
673a394b | 2273 | |
778c3544 | 2274 | /** Current tiling stride for the object, if it's tiled. */ |
de151cf6 | 2275 | uint32_t stride; |
673a394b | 2276 | |
80075d49 DV |
2277 | /** References from framebuffers, locks out tiling changes. */ |
2278 | unsigned long framebuffer_references; | |
2279 | ||
280b713b | 2280 | /** Record of address bit 17 of each page at last unbind. */ |
d312ec25 | 2281 | unsigned long *bit_17; |
280b713b | 2282 | |
5cc9ed4b | 2283 | union { |
6a2c4232 CW |
2284 | /** for phy allocated objects */ |
2285 | struct drm_dma_handle *phys_handle; | |
2286 | ||
5cc9ed4b CW |
2287 | struct i915_gem_userptr { |
2288 | uintptr_t ptr; | |
2289 | unsigned read_only :1; | |
2290 | unsigned workers :4; | |
2291 | #define I915_GEM_USERPTR_MAX_WORKERS 15 | |
2292 | ||
ad46cb53 CW |
2293 | struct i915_mm_struct *mm; |
2294 | struct i915_mmu_object *mmu_object; | |
5cc9ed4b CW |
2295 | struct work_struct *work; |
2296 | } userptr; | |
2297 | }; | |
2298 | }; | |
62b8b215 | 2299 | #define to_intel_bo(x) container_of(x, struct drm_i915_gem_object, base) |
23010e43 | 2300 | |
b9bcd14a CW |
2301 | static inline bool |
2302 | i915_gem_object_has_struct_page(const struct drm_i915_gem_object *obj) | |
2303 | { | |
2304 | return obj->ops->flags & I915_GEM_OBJECT_HAS_STRUCT_PAGE; | |
2305 | } | |
2306 | ||
85d1225e DG |
2307 | /* |
2308 | * Optimised SGL iterator for GEM objects | |
2309 | */ | |
2310 | static __always_inline struct sgt_iter { | |
2311 | struct scatterlist *sgp; | |
2312 | union { | |
2313 | unsigned long pfn; | |
2314 | dma_addr_t dma; | |
2315 | }; | |
2316 | unsigned int curr; | |
2317 | unsigned int max; | |
2318 | } __sgt_iter(struct scatterlist *sgl, bool dma) { | |
2319 | struct sgt_iter s = { .sgp = sgl }; | |
2320 | ||
2321 | if (s.sgp) { | |
2322 | s.max = s.curr = s.sgp->offset; | |
2323 | s.max += s.sgp->length; | |
2324 | if (dma) | |
2325 | s.dma = sg_dma_address(s.sgp); | |
2326 | else | |
2327 | s.pfn = page_to_pfn(sg_page(s.sgp)); | |
2328 | } | |
2329 | ||
2330 | return s; | |
2331 | } | |
2332 | ||
63d15326 DG |
2333 | /** |
2334 | * __sg_next - return the next scatterlist entry in a list | |
2335 | * @sg: The current sg entry | |
2336 | * | |
2337 | * Description: | |
2338 | * If the entry is the last, return NULL; otherwise, step to the next | |
2339 | * element in the array (@sg@+1). If that's a chain pointer, follow it; | |
2340 | * otherwise just return the pointer to the current element. | |
2341 | **/ | |
2342 | static inline struct scatterlist *__sg_next(struct scatterlist *sg) | |
2343 | { | |
2344 | #ifdef CONFIG_DEBUG_SG | |
2345 | BUG_ON(sg->sg_magic != SG_MAGIC); | |
2346 | #endif | |
2347 | return sg_is_last(sg) ? NULL : | |
2348 | likely(!sg_is_chain(++sg)) ? sg : | |
2349 | sg_chain_ptr(sg); | |
2350 | } | |
2351 | ||
85d1225e DG |
2352 | /** |
2353 | * for_each_sgt_dma - iterate over the DMA addresses of the given sg_table | |
2354 | * @__dmap: DMA address (output) | |
2355 | * @__iter: 'struct sgt_iter' (iterator state, internal) | |
2356 | * @__sgt: sg_table to iterate over (input) | |
2357 | */ | |
2358 | #define for_each_sgt_dma(__dmap, __iter, __sgt) \ | |
2359 | for ((__iter) = __sgt_iter((__sgt)->sgl, true); \ | |
2360 | ((__dmap) = (__iter).dma + (__iter).curr); \ | |
2361 | (((__iter).curr += PAGE_SIZE) < (__iter).max) || \ | |
63d15326 | 2362 | ((__iter) = __sgt_iter(__sg_next((__iter).sgp), true), 0)) |
85d1225e DG |
2363 | |
2364 | /** | |
2365 | * for_each_sgt_page - iterate over the pages of the given sg_table | |
2366 | * @__pp: page pointer (output) | |
2367 | * @__iter: 'struct sgt_iter' (iterator state, internal) | |
2368 | * @__sgt: sg_table to iterate over (input) | |
2369 | */ | |
2370 | #define for_each_sgt_page(__pp, __iter, __sgt) \ | |
2371 | for ((__iter) = __sgt_iter((__sgt)->sgl, false); \ | |
2372 | ((__pp) = (__iter).pfn == 0 ? NULL : \ | |
2373 | pfn_to_page((__iter).pfn + ((__iter).curr >> PAGE_SHIFT))); \ | |
2374 | (((__iter).curr += PAGE_SIZE) < (__iter).max) || \ | |
63d15326 | 2375 | ((__iter) = __sgt_iter(__sg_next((__iter).sgp), false), 0)) |
a071fa00 | 2376 | |
673a394b EA |
2377 | /** |
2378 | * Request queue structure. | |
2379 | * | |
2380 | * The request queue allows us to note sequence numbers that have been emitted | |
2381 | * and may be associated with active buffers to be retired. | |
2382 | * | |
97b2a6a1 JH |
2383 | * By keeping this list, we can avoid having to do questionable sequence |
2384 | * number comparisons on buffer last_read|write_seqno. It also allows an | |
2385 | * emission time to be associated with the request for tracking how far ahead | |
2386 | * of the GPU the submission is. | |
b3a38998 NH |
2387 | * |
2388 | * The requests are reference counted, so upon creation they should have an | |
2389 | * initial reference taken using kref_init | |
673a394b EA |
2390 | */ |
2391 | struct drm_i915_gem_request { | |
abfe262a JH |
2392 | struct kref ref; |
2393 | ||
852835f3 | 2394 | /** On Which ring this request was generated */ |
efab6d8d | 2395 | struct drm_i915_private *i915; |
4a570db5 | 2396 | struct intel_engine_cs *engine; |
b3850855 | 2397 | struct intel_signal_node signaling; |
852835f3 | 2398 | |
821485dc CW |
2399 | /** GEM sequence number associated with the previous request, |
2400 | * when the HWS breadcrumb is equal to this the GPU is processing | |
2401 | * this request. | |
2402 | */ | |
2403 | u32 previous_seqno; | |
2404 | ||
2405 | /** GEM sequence number associated with this request, | |
2406 | * when the HWS breadcrumb is equal or greater than this the GPU | |
2407 | * has finished processing this request. | |
2408 | */ | |
2409 | u32 seqno; | |
673a394b | 2410 | |
7d736f4f MK |
2411 | /** Position in the ringbuffer of the start of the request */ |
2412 | u32 head; | |
2413 | ||
72f95afa NH |
2414 | /** |
2415 | * Position in the ringbuffer of the start of the postfix. | |
2416 | * This is required to calculate the maximum available ringbuffer | |
2417 | * space without overwriting the postfix. | |
2418 | */ | |
2419 | u32 postfix; | |
2420 | ||
2421 | /** Position in the ringbuffer of the end of the whole request */ | |
a71d8d94 CW |
2422 | u32 tail; |
2423 | ||
0251a963 CW |
2424 | /** Preallocate space in the ringbuffer for the emitting the request */ |
2425 | u32 reserved_space; | |
2426 | ||
b3a38998 | 2427 | /** |
a8c6ecb3 | 2428 | * Context and ring buffer related to this request |
b3a38998 NH |
2429 | * Contexts are refcounted, so when this request is associated with a |
2430 | * context, we must increment the context's refcount, to guarantee that | |
2431 | * it persists while any request is linked to it. Requests themselves | |
2432 | * are also refcounted, so the request will only be freed when the last | |
2433 | * reference to it is dismissed, and the code in | |
2434 | * i915_gem_request_free() will then decrement the refcount on the | |
2435 | * context. | |
2436 | */ | |
e2efd130 | 2437 | struct i915_gem_context *ctx; |
98e1bd4a | 2438 | struct intel_ringbuffer *ringbuf; |
0e50e96b | 2439 | |
a16a4052 CW |
2440 | /** |
2441 | * Context related to the previous request. | |
2442 | * As the contexts are accessed by the hardware until the switch is | |
2443 | * completed to a new context, the hardware may still be writing | |
2444 | * to the context object after the breadcrumb is visible. We must | |
2445 | * not unpin/unbind/prune that object whilst still active and so | |
2446 | * we keep the previous context pinned until the following (this) | |
2447 | * request is retired. | |
2448 | */ | |
e2efd130 | 2449 | struct i915_gem_context *previous_context; |
a16a4052 | 2450 | |
dc4be607 JH |
2451 | /** Batch buffer related to this request if any (used for |
2452 | error state dump only) */ | |
7d736f4f MK |
2453 | struct drm_i915_gem_object *batch_obj; |
2454 | ||
673a394b EA |
2455 | /** Time at which this request was emitted, in jiffies. */ |
2456 | unsigned long emitted_jiffies; | |
2457 | ||
b962442e | 2458 | /** global list entry for this request */ |
673a394b | 2459 | struct list_head list; |
b962442e | 2460 | |
f787a5f5 | 2461 | struct drm_i915_file_private *file_priv; |
b962442e EA |
2462 | /** file_priv list entry for this request */ |
2463 | struct list_head client_list; | |
67e2937b | 2464 | |
071c92de MK |
2465 | /** process identifier submitting this request */ |
2466 | struct pid *pid; | |
2467 | ||
6d3d8274 NH |
2468 | /** |
2469 | * The ELSP only accepts two elements at a time, so we queue | |
2470 | * context/tail pairs on a given queue (ring->execlist_queue) until the | |
2471 | * hardware is available. The queue serves a double purpose: we also use | |
2472 | * it to keep track of the up to 2 contexts currently in the hardware | |
2473 | * (usually one in execution and the other queued up by the GPU): We | |
2474 | * only remove elements from the head of the queue when the hardware | |
2475 | * informs us that an element has been completed. | |
2476 | * | |
2477 | * All accesses to the queue are mediated by a spinlock | |
2478 | * (ring->execlist_lock). | |
2479 | */ | |
2480 | ||
2481 | /** Execlist link in the submission queue.*/ | |
2482 | struct list_head execlist_link; | |
2483 | ||
2484 | /** Execlists no. of times this request has been sent to the ELSP */ | |
2485 | int elsp_submitted; | |
2486 | ||
a3d12761 TU |
2487 | /** Execlists context hardware id. */ |
2488 | unsigned ctx_hw_id; | |
673a394b EA |
2489 | }; |
2490 | ||
26827088 DG |
2491 | struct drm_i915_gem_request * __must_check |
2492 | i915_gem_request_alloc(struct intel_engine_cs *engine, | |
e2efd130 | 2493 | struct i915_gem_context *ctx); |
abfe262a | 2494 | void i915_gem_request_free(struct kref *req_ref); |
fcfa423c JH |
2495 | int i915_gem_request_add_to_client(struct drm_i915_gem_request *req, |
2496 | struct drm_file *file); | |
abfe262a | 2497 | |
b793a00a JH |
2498 | static inline uint32_t |
2499 | i915_gem_request_get_seqno(struct drm_i915_gem_request *req) | |
2500 | { | |
2501 | return req ? req->seqno : 0; | |
2502 | } | |
2503 | ||
2504 | static inline struct intel_engine_cs * | |
666796da | 2505 | i915_gem_request_get_engine(struct drm_i915_gem_request *req) |
b793a00a | 2506 | { |
4a570db5 | 2507 | return req ? req->engine : NULL; |
b793a00a JH |
2508 | } |
2509 | ||
b2cfe0ab | 2510 | static inline struct drm_i915_gem_request * |
abfe262a JH |
2511 | i915_gem_request_reference(struct drm_i915_gem_request *req) |
2512 | { | |
b2cfe0ab CW |
2513 | if (req) |
2514 | kref_get(&req->ref); | |
2515 | return req; | |
abfe262a JH |
2516 | } |
2517 | ||
2518 | static inline void | |
2519 | i915_gem_request_unreference(struct drm_i915_gem_request *req) | |
2520 | { | |
2521 | kref_put(&req->ref, i915_gem_request_free); | |
2522 | } | |
2523 | ||
2524 | static inline void i915_gem_request_assign(struct drm_i915_gem_request **pdst, | |
2525 | struct drm_i915_gem_request *src) | |
2526 | { | |
2527 | if (src) | |
2528 | i915_gem_request_reference(src); | |
2529 | ||
2530 | if (*pdst) | |
2531 | i915_gem_request_unreference(*pdst); | |
2532 | ||
2533 | *pdst = src; | |
2534 | } | |
2535 | ||
1b5a433a JH |
2536 | /* |
2537 | * XXX: i915_gem_request_completed should be here but currently needs the | |
2538 | * definition of i915_seqno_passed() which is below. It will be moved in | |
2539 | * a later patch when the call to i915_seqno_passed() is obsoleted... | |
2540 | */ | |
2541 | ||
351e3db2 BV |
2542 | /* |
2543 | * A command that requires special handling by the command parser. | |
2544 | */ | |
2545 | struct drm_i915_cmd_descriptor { | |
2546 | /* | |
2547 | * Flags describing how the command parser processes the command. | |
2548 | * | |
2549 | * CMD_DESC_FIXED: The command has a fixed length if this is set, | |
2550 | * a length mask if not set | |
2551 | * CMD_DESC_SKIP: The command is allowed but does not follow the | |
2552 | * standard length encoding for the opcode range in | |
2553 | * which it falls | |
2554 | * CMD_DESC_REJECT: The command is never allowed | |
2555 | * CMD_DESC_REGISTER: The command should be checked against the | |
2556 | * register whitelist for the appropriate ring | |
2557 | * CMD_DESC_MASTER: The command is allowed if the submitting process | |
2558 | * is the DRM master | |
2559 | */ | |
2560 | u32 flags; | |
2561 | #define CMD_DESC_FIXED (1<<0) | |
2562 | #define CMD_DESC_SKIP (1<<1) | |
2563 | #define CMD_DESC_REJECT (1<<2) | |
2564 | #define CMD_DESC_REGISTER (1<<3) | |
2565 | #define CMD_DESC_BITMASK (1<<4) | |
2566 | #define CMD_DESC_MASTER (1<<5) | |
2567 | ||
2568 | /* | |
2569 | * The command's unique identification bits and the bitmask to get them. | |
2570 | * This isn't strictly the opcode field as defined in the spec and may | |
2571 | * also include type, subtype, and/or subop fields. | |
2572 | */ | |
2573 | struct { | |
2574 | u32 value; | |
2575 | u32 mask; | |
2576 | } cmd; | |
2577 | ||
2578 | /* | |
2579 | * The command's length. The command is either fixed length (i.e. does | |
2580 | * not include a length field) or has a length field mask. The flag | |
2581 | * CMD_DESC_FIXED indicates a fixed length. Otherwise, the command has | |
2582 | * a length mask. All command entries in a command table must include | |
2583 | * length information. | |
2584 | */ | |
2585 | union { | |
2586 | u32 fixed; | |
2587 | u32 mask; | |
2588 | } length; | |
2589 | ||
2590 | /* | |
2591 | * Describes where to find a register address in the command to check | |
2592 | * against the ring's register whitelist. Only valid if flags has the | |
2593 | * CMD_DESC_REGISTER bit set. | |
6a65c5b9 FJ |
2594 | * |
2595 | * A non-zero step value implies that the command may access multiple | |
2596 | * registers in sequence (e.g. LRI), in that case step gives the | |
2597 | * distance in dwords between individual offset fields. | |
351e3db2 BV |
2598 | */ |
2599 | struct { | |
2600 | u32 offset; | |
2601 | u32 mask; | |
6a65c5b9 | 2602 | u32 step; |
351e3db2 BV |
2603 | } reg; |
2604 | ||
2605 | #define MAX_CMD_DESC_BITMASKS 3 | |
2606 | /* | |
2607 | * Describes command checks where a particular dword is masked and | |
2608 | * compared against an expected value. If the command does not match | |
2609 | * the expected value, the parser rejects it. Only valid if flags has | |
2610 | * the CMD_DESC_BITMASK bit set. Only entries where mask is non-zero | |
2611 | * are valid. | |
d4d48035 BV |
2612 | * |
2613 | * If the check specifies a non-zero condition_mask then the parser | |
2614 | * only performs the check when the bits specified by condition_mask | |
2615 | * are non-zero. | |
351e3db2 BV |
2616 | */ |
2617 | struct { | |
2618 | u32 offset; | |
2619 | u32 mask; | |
2620 | u32 expected; | |
d4d48035 BV |
2621 | u32 condition_offset; |
2622 | u32 condition_mask; | |
351e3db2 BV |
2623 | } bits[MAX_CMD_DESC_BITMASKS]; |
2624 | }; | |
2625 | ||
2626 | /* | |
2627 | * A table of commands requiring special handling by the command parser. | |
2628 | * | |
2629 | * Each ring has an array of tables. Each table consists of an array of command | |
2630 | * descriptors, which must be sorted with command opcodes in ascending order. | |
2631 | */ | |
2632 | struct drm_i915_cmd_table { | |
2633 | const struct drm_i915_cmd_descriptor *table; | |
2634 | int count; | |
2635 | }; | |
2636 | ||
dbbe9127 | 2637 | /* Note that the (struct drm_i915_private *) cast is just to shut up gcc. */ |
7312e2dd CW |
2638 | #define __I915__(p) ({ \ |
2639 | struct drm_i915_private *__p; \ | |
2640 | if (__builtin_types_compatible_p(typeof(*p), struct drm_i915_private)) \ | |
2641 | __p = (struct drm_i915_private *)p; \ | |
2642 | else if (__builtin_types_compatible_p(typeof(*p), struct drm_device)) \ | |
2643 | __p = to_i915((struct drm_device *)p); \ | |
2644 | else \ | |
2645 | BUILD_BUG(); \ | |
2646 | __p; \ | |
2647 | }) | |
dbbe9127 | 2648 | #define INTEL_INFO(p) (&__I915__(p)->info) |
3f10e82f | 2649 | #define INTEL_GEN(p) (INTEL_INFO(p)->gen) |
87f1f465 | 2650 | #define INTEL_DEVID(p) (INTEL_INFO(p)->device_id) |
cae5852d | 2651 | |
e87a005d | 2652 | #define REVID_FOREVER 0xff |
091387c1 | 2653 | #define INTEL_REVID(p) (__I915__(p)->drm.pdev->revision) |
ac657f64 TU |
2654 | |
2655 | #define GEN_FOREVER (0) | |
2656 | /* | |
2657 | * Returns true if Gen is in inclusive range [Start, End]. | |
2658 | * | |
2659 | * Use GEN_FOREVER for unbound start and or end. | |
2660 | */ | |
2661 | #define IS_GEN(p, s, e) ({ \ | |
2662 | unsigned int __s = (s), __e = (e); \ | |
2663 | BUILD_BUG_ON(!__builtin_constant_p(s)); \ | |
2664 | BUILD_BUG_ON(!__builtin_constant_p(e)); \ | |
2665 | if ((__s) != GEN_FOREVER) \ | |
2666 | __s = (s) - 1; \ | |
2667 | if ((__e) == GEN_FOREVER) \ | |
2668 | __e = BITS_PER_LONG - 1; \ | |
2669 | else \ | |
2670 | __e = (e) - 1; \ | |
2671 | !!(INTEL_INFO(p)->gen_mask & GENMASK((__e), (__s))); \ | |
2672 | }) | |
2673 | ||
e87a005d JN |
2674 | /* |
2675 | * Return true if revision is in range [since,until] inclusive. | |
2676 | * | |
2677 | * Use 0 for open-ended since, and REVID_FOREVER for open-ended until. | |
2678 | */ | |
2679 | #define IS_REVID(p, since, until) \ | |
2680 | (INTEL_REVID(p) >= (since) && INTEL_REVID(p) <= (until)) | |
2681 | ||
87f1f465 CW |
2682 | #define IS_I830(dev) (INTEL_DEVID(dev) == 0x3577) |
2683 | #define IS_845G(dev) (INTEL_DEVID(dev) == 0x2562) | |
cae5852d | 2684 | #define IS_I85X(dev) (INTEL_INFO(dev)->is_i85x) |
87f1f465 | 2685 | #define IS_I865G(dev) (INTEL_DEVID(dev) == 0x2572) |
cae5852d | 2686 | #define IS_I915G(dev) (INTEL_INFO(dev)->is_i915g) |
87f1f465 CW |
2687 | #define IS_I915GM(dev) (INTEL_DEVID(dev) == 0x2592) |
2688 | #define IS_I945G(dev) (INTEL_DEVID(dev) == 0x2772) | |
cae5852d ZN |
2689 | #define IS_I945GM(dev) (INTEL_INFO(dev)->is_i945gm) |
2690 | #define IS_BROADWATER(dev) (INTEL_INFO(dev)->is_broadwater) | |
2691 | #define IS_CRESTLINE(dev) (INTEL_INFO(dev)->is_crestline) | |
87f1f465 | 2692 | #define IS_GM45(dev) (INTEL_DEVID(dev) == 0x2A42) |
cae5852d | 2693 | #define IS_G4X(dev) (INTEL_INFO(dev)->is_g4x) |
87f1f465 CW |
2694 | #define IS_PINEVIEW_G(dev) (INTEL_DEVID(dev) == 0xa001) |
2695 | #define IS_PINEVIEW_M(dev) (INTEL_DEVID(dev) == 0xa011) | |
cae5852d ZN |
2696 | #define IS_PINEVIEW(dev) (INTEL_INFO(dev)->is_pineview) |
2697 | #define IS_G33(dev) (INTEL_INFO(dev)->is_g33) | |
87f1f465 | 2698 | #define IS_IRONLAKE_M(dev) (INTEL_DEVID(dev) == 0x0046) |
4b65177b | 2699 | #define IS_IVYBRIDGE(dev) (INTEL_INFO(dev)->is_ivybridge) |
87f1f465 CW |
2700 | #define IS_IVB_GT1(dev) (INTEL_DEVID(dev) == 0x0156 || \ |
2701 | INTEL_DEVID(dev) == 0x0152 || \ | |
2702 | INTEL_DEVID(dev) == 0x015a) | |
70a3eb7a | 2703 | #define IS_VALLEYVIEW(dev) (INTEL_INFO(dev)->is_valleyview) |
666a4537 | 2704 | #define IS_CHERRYVIEW(dev) (INTEL_INFO(dev)->is_cherryview) |
4cae9ae0 | 2705 | #define IS_HASWELL(dev) (INTEL_INFO(dev)->is_haswell) |
ab0d24ac | 2706 | #define IS_BROADWELL(dev) (INTEL_INFO(dev)->is_broadwell) |
7201c0b3 | 2707 | #define IS_SKYLAKE(dev) (INTEL_INFO(dev)->is_skylake) |
7526ac19 | 2708 | #define IS_BROXTON(dev) (INTEL_INFO(dev)->is_broxton) |
ef11bdb3 | 2709 | #define IS_KABYLAKE(dev) (INTEL_INFO(dev)->is_kabylake) |
cae5852d | 2710 | #define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile) |
ed1c9e2c | 2711 | #define IS_HSW_EARLY_SDV(dev) (IS_HASWELL(dev) && \ |
87f1f465 | 2712 | (INTEL_DEVID(dev) & 0xFF00) == 0x0C00) |
5dd8c4c3 | 2713 | #define IS_BDW_ULT(dev) (IS_BROADWELL(dev) && \ |
6b96d705 | 2714 | ((INTEL_DEVID(dev) & 0xf) == 0x6 || \ |
0dc6f20b | 2715 | (INTEL_DEVID(dev) & 0xf) == 0xb || \ |
87f1f465 | 2716 | (INTEL_DEVID(dev) & 0xf) == 0xe)) |
ebb72aad VS |
2717 | /* ULX machines are also considered ULT. */ |
2718 | #define IS_BDW_ULX(dev) (IS_BROADWELL(dev) && \ | |
2719 | (INTEL_DEVID(dev) & 0xf) == 0xe) | |
a0fcbd95 RV |
2720 | #define IS_BDW_GT3(dev) (IS_BROADWELL(dev) && \ |
2721 | (INTEL_DEVID(dev) & 0x00F0) == 0x0020) | |
5dd8c4c3 | 2722 | #define IS_HSW_ULT(dev) (IS_HASWELL(dev) && \ |
87f1f465 | 2723 | (INTEL_DEVID(dev) & 0xFF00) == 0x0A00) |
9435373e | 2724 | #define IS_HSW_GT3(dev) (IS_HASWELL(dev) && \ |
87f1f465 | 2725 | (INTEL_DEVID(dev) & 0x00F0) == 0x0020) |
9bbfd20a | 2726 | /* ULX machines are also considered ULT. */ |
87f1f465 CW |
2727 | #define IS_HSW_ULX(dev) (INTEL_DEVID(dev) == 0x0A0E || \ |
2728 | INTEL_DEVID(dev) == 0x0A1E) | |
f8896f5d DW |
2729 | #define IS_SKL_ULT(dev) (INTEL_DEVID(dev) == 0x1906 || \ |
2730 | INTEL_DEVID(dev) == 0x1913 || \ | |
2731 | INTEL_DEVID(dev) == 0x1916 || \ | |
2732 | INTEL_DEVID(dev) == 0x1921 || \ | |
2733 | INTEL_DEVID(dev) == 0x1926) | |
2734 | #define IS_SKL_ULX(dev) (INTEL_DEVID(dev) == 0x190E || \ | |
2735 | INTEL_DEVID(dev) == 0x1915 || \ | |
2736 | INTEL_DEVID(dev) == 0x191E) | |
a5b7991c RV |
2737 | #define IS_KBL_ULT(dev) (INTEL_DEVID(dev) == 0x5906 || \ |
2738 | INTEL_DEVID(dev) == 0x5913 || \ | |
2739 | INTEL_DEVID(dev) == 0x5916 || \ | |
2740 | INTEL_DEVID(dev) == 0x5921 || \ | |
2741 | INTEL_DEVID(dev) == 0x5926) | |
2742 | #define IS_KBL_ULX(dev) (INTEL_DEVID(dev) == 0x590E || \ | |
2743 | INTEL_DEVID(dev) == 0x5915 || \ | |
2744 | INTEL_DEVID(dev) == 0x591E) | |
7a58bad0 SAK |
2745 | #define IS_SKL_GT3(dev) (IS_SKYLAKE(dev) && \ |
2746 | (INTEL_DEVID(dev) & 0x00F0) == 0x0020) | |
2747 | #define IS_SKL_GT4(dev) (IS_SKYLAKE(dev) && \ | |
2748 | (INTEL_DEVID(dev) & 0x00F0) == 0x0030) | |
2749 | ||
b833d685 | 2750 | #define IS_PRELIMINARY_HW(intel_info) ((intel_info)->is_preliminary) |
cae5852d | 2751 | |
ef712bb4 JN |
2752 | #define SKL_REVID_A0 0x0 |
2753 | #define SKL_REVID_B0 0x1 | |
2754 | #define SKL_REVID_C0 0x2 | |
2755 | #define SKL_REVID_D0 0x3 | |
2756 | #define SKL_REVID_E0 0x4 | |
2757 | #define SKL_REVID_F0 0x5 | |
f15f6ca1 MK |
2758 | #define SKL_REVID_G0 0x6 |
2759 | #define SKL_REVID_H0 0x7 | |
ef712bb4 | 2760 | |
e87a005d JN |
2761 | #define IS_SKL_REVID(p, since, until) (IS_SKYLAKE(p) && IS_REVID(p, since, until)) |
2762 | ||
ef712bb4 | 2763 | #define BXT_REVID_A0 0x0 |
fffda3f4 | 2764 | #define BXT_REVID_A1 0x1 |
ef712bb4 JN |
2765 | #define BXT_REVID_B0 0x3 |
2766 | #define BXT_REVID_C0 0x9 | |
6c74c87f | 2767 | |
e87a005d JN |
2768 | #define IS_BXT_REVID(p, since, until) (IS_BROXTON(p) && IS_REVID(p, since, until)) |
2769 | ||
c033a37c MK |
2770 | #define KBL_REVID_A0 0x0 |
2771 | #define KBL_REVID_B0 0x1 | |
fe905819 MK |
2772 | #define KBL_REVID_C0 0x2 |
2773 | #define KBL_REVID_D0 0x3 | |
2774 | #define KBL_REVID_E0 0x4 | |
c033a37c MK |
2775 | |
2776 | #define IS_KBL_REVID(p, since, until) \ | |
2777 | (IS_KABYLAKE(p) && IS_REVID(p, since, until)) | |
2778 | ||
85436696 JB |
2779 | /* |
2780 | * The genX designation typically refers to the render engine, so render | |
2781 | * capability related checks should use IS_GEN, while display and other checks | |
2782 | * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular | |
2783 | * chips, etc.). | |
2784 | */ | |
af1346a0 TU |
2785 | #define IS_GEN2(dev) (!!(INTEL_INFO(dev)->gen_mask & BIT(1))) |
2786 | #define IS_GEN3(dev) (!!(INTEL_INFO(dev)->gen_mask & BIT(2))) | |
2787 | #define IS_GEN4(dev) (!!(INTEL_INFO(dev)->gen_mask & BIT(3))) | |
2788 | #define IS_GEN5(dev) (!!(INTEL_INFO(dev)->gen_mask & BIT(4))) | |
2789 | #define IS_GEN6(dev) (!!(INTEL_INFO(dev)->gen_mask & BIT(5))) | |
2790 | #define IS_GEN7(dev) (!!(INTEL_INFO(dev)->gen_mask & BIT(6))) | |
2791 | #define IS_GEN8(dev) (!!(INTEL_INFO(dev)->gen_mask & BIT(7))) | |
2792 | #define IS_GEN9(dev) (!!(INTEL_INFO(dev)->gen_mask & BIT(8))) | |
cae5852d | 2793 | |
a19d6ff2 TU |
2794 | #define ENGINE_MASK(id) BIT(id) |
2795 | #define RENDER_RING ENGINE_MASK(RCS) | |
2796 | #define BSD_RING ENGINE_MASK(VCS) | |
2797 | #define BLT_RING ENGINE_MASK(BCS) | |
2798 | #define VEBOX_RING ENGINE_MASK(VECS) | |
2799 | #define BSD2_RING ENGINE_MASK(VCS2) | |
2800 | #define ALL_ENGINES (~0) | |
2801 | ||
2802 | #define HAS_ENGINE(dev_priv, id) \ | |
af1346a0 | 2803 | (!!(INTEL_INFO(dev_priv)->ring_mask & ENGINE_MASK(id))) |
a19d6ff2 TU |
2804 | |
2805 | #define HAS_BSD(dev_priv) HAS_ENGINE(dev_priv, VCS) | |
2806 | #define HAS_BSD2(dev_priv) HAS_ENGINE(dev_priv, VCS2) | |
2807 | #define HAS_BLT(dev_priv) HAS_ENGINE(dev_priv, BCS) | |
2808 | #define HAS_VEBOX(dev_priv) HAS_ENGINE(dev_priv, VECS) | |
2809 | ||
63c42e56 | 2810 | #define HAS_LLC(dev) (INTEL_INFO(dev)->has_llc) |
ca377809 | 2811 | #define HAS_SNOOP(dev) (INTEL_INFO(dev)->has_snoop) |
af1346a0 | 2812 | #define HAS_EDRAM(dev) (!!(__I915__(dev)->edram_cap & EDRAM_ENABLED)) |
63c42e56 | 2813 | #define HAS_WT(dev) ((IS_HASWELL(dev) || IS_BROADWELL(dev)) && \ |
3accaf7e | 2814 | HAS_EDRAM(dev)) |
cae5852d ZN |
2815 | #define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws) |
2816 | ||
254f965c | 2817 | #define HAS_HW_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 6) |
d7f621e5 | 2818 | #define HAS_LOGICAL_RING_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 8) |
692ef70c | 2819 | #define USES_PPGTT(dev) (i915.enable_ppgtt) |
81ba8aef MT |
2820 | #define USES_FULL_PPGTT(dev) (i915.enable_ppgtt >= 2) |
2821 | #define USES_FULL_48BIT_PPGTT(dev) (i915.enable_ppgtt == 3) | |
1d2a314c | 2822 | |
05394f39 | 2823 | #define HAS_OVERLAY(dev) (INTEL_INFO(dev)->has_overlay) |
cae5852d ZN |
2824 | #define OVERLAY_NEEDS_PHYSICAL(dev) (INTEL_INFO(dev)->overlay_needs_physical) |
2825 | ||
b45305fc DV |
2826 | /* Early gen2 have a totally busted CS tlb and require pinned batches. */ |
2827 | #define HAS_BROKEN_CS_TLB(dev) (IS_I830(dev) || IS_845G(dev)) | |
06e668ac MK |
2828 | |
2829 | /* WaRsDisableCoarsePowerGating:skl,bxt */ | |
61251512 TU |
2830 | #define NEEDS_WaRsDisableCoarsePowerGating(dev_priv) \ |
2831 | (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1) || \ | |
2832 | IS_SKL_GT3(dev_priv) || \ | |
2833 | IS_SKL_GT4(dev_priv)) | |
185c66e5 | 2834 | |
4e6b788c DV |
2835 | /* |
2836 | * dp aux and gmbus irq on gen4 seems to be able to generate legacy interrupts | |
2837 | * even when in MSI mode. This results in spurious interrupt warnings if the | |
2838 | * legacy irq no. is shared with another device. The kernel then disables that | |
2839 | * interrupt source and so prevents the other device from working properly. | |
2840 | */ | |
2841 | #define HAS_AUX_IRQ(dev) (INTEL_INFO(dev)->gen >= 5) | |
2842 | #define HAS_GMBUS_IRQ(dev) (INTEL_INFO(dev)->gen >= 5) | |
b45305fc | 2843 | |
cae5852d ZN |
2844 | /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte |
2845 | * rows, which changed the alignment requirements and fence programming. | |
2846 | */ | |
2847 | #define HAS_128_BYTE_Y_TILING(dev) (!IS_GEN2(dev) && !(IS_I915G(dev) || \ | |
2848 | IS_I915GM(dev))) | |
cae5852d ZN |
2849 | #define SUPPORTS_TV(dev) (INTEL_INFO(dev)->supports_tv) |
2850 | #define I915_HAS_HOTPLUG(dev) (INTEL_INFO(dev)->has_hotplug) | |
cae5852d ZN |
2851 | |
2852 | #define HAS_FW_BLC(dev) (INTEL_INFO(dev)->gen > 2) | |
2853 | #define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr) | |
3a77c4c4 | 2854 | #define HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc) |
cae5852d | 2855 | |
dbf7786e | 2856 | #define HAS_IPS(dev) (IS_HSW_ULT(dev) || IS_BROADWELL(dev)) |
f5adf94e | 2857 | |
0c9b3715 JN |
2858 | #define HAS_DP_MST(dev) (IS_HASWELL(dev) || IS_BROADWELL(dev) || \ |
2859 | INTEL_INFO(dev)->gen >= 9) | |
2860 | ||
dd93be58 | 2861 | #define HAS_DDI(dev) (INTEL_INFO(dev)->has_ddi) |
30568c45 | 2862 | #define HAS_FPGA_DBG_UNCLAIMED(dev) (INTEL_INFO(dev)->has_fpga_dbg) |
b32c6f48 | 2863 | #define HAS_PSR(dev) (IS_HASWELL(dev) || IS_BROADWELL(dev) || \ |
e3d99845 | 2864 | IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev) || \ |
ef11bdb3 | 2865 | IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) |
6157d3c8 | 2866 | #define HAS_RUNTIME_PM(dev) (IS_GEN6(dev) || IS_HASWELL(dev) || \ |
00776511 | 2867 | IS_BROADWELL(dev) || IS_VALLEYVIEW(dev) || \ |
666a4537 | 2868 | IS_CHERRYVIEW(dev) || IS_SKYLAKE(dev) || \ |
8f6d855c | 2869 | IS_KABYLAKE(dev) || IS_BROXTON(dev)) |
58abf1da | 2870 | #define HAS_RC6(dev) (INTEL_INFO(dev)->gen >= 6) |
7e22dbbb | 2871 | #define HAS_RC6p(dev) (IS_GEN6(dev) || IS_IVYBRIDGE(dev)) |
affa9354 | 2872 | |
7b403ffb | 2873 | #define HAS_CSR(dev) (IS_GEN9(dev)) |
eb805623 | 2874 | |
1a3d1898 DG |
2875 | /* |
2876 | * For now, anything with a GuC requires uCode loading, and then supports | |
2877 | * command submission once loaded. But these are logically independent | |
2878 | * properties, so we have separate macros to test them. | |
2879 | */ | |
6f8be280 | 2880 | #define HAS_GUC(dev) (IS_GEN9(dev)) |
1a3d1898 DG |
2881 | #define HAS_GUC_UCODE(dev) (HAS_GUC(dev)) |
2882 | #define HAS_GUC_SCHED(dev) (HAS_GUC(dev)) | |
33a732f4 | 2883 | |
a9ed33ca AJ |
2884 | #define HAS_RESOURCE_STREAMER(dev) (IS_HASWELL(dev) || \ |
2885 | INTEL_INFO(dev)->gen >= 8) | |
2886 | ||
97d3308a | 2887 | #define HAS_CORE_RING_FREQ(dev) (INTEL_INFO(dev)->gen >= 6 && \ |
666a4537 WB |
2888 | !IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) && \ |
2889 | !IS_BROXTON(dev)) | |
97d3308a | 2890 | |
33e141ed | 2891 | #define HAS_POOLED_EU(dev) (INTEL_INFO(dev)->has_pooled_eu) |
2892 | ||
17a303ec PZ |
2893 | #define INTEL_PCH_DEVICE_ID_MASK 0xff00 |
2894 | #define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00 | |
2895 | #define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00 | |
2896 | #define INTEL_PCH_PPT_DEVICE_ID_TYPE 0x1e00 | |
2897 | #define INTEL_PCH_LPT_DEVICE_ID_TYPE 0x8c00 | |
2898 | #define INTEL_PCH_LPT_LP_DEVICE_ID_TYPE 0x9c00 | |
e7e7ea20 S |
2899 | #define INTEL_PCH_SPT_DEVICE_ID_TYPE 0xA100 |
2900 | #define INTEL_PCH_SPT_LP_DEVICE_ID_TYPE 0x9D00 | |
22dea0be | 2901 | #define INTEL_PCH_KBP_DEVICE_ID_TYPE 0xA200 |
30c964a6 | 2902 | #define INTEL_PCH_P2X_DEVICE_ID_TYPE 0x7100 |
1844a66b | 2903 | #define INTEL_PCH_P3X_DEVICE_ID_TYPE 0x7000 |
39bfcd52 | 2904 | #define INTEL_PCH_QEMU_DEVICE_ID_TYPE 0x2900 /* qemu q35 has 2918 */ |
17a303ec | 2905 | |
f2fbc690 | 2906 | #define INTEL_PCH_TYPE(dev) (__I915__(dev)->pch_type) |
22dea0be | 2907 | #define HAS_PCH_KBP(dev) (INTEL_PCH_TYPE(dev) == PCH_KBP) |
e7e7ea20 | 2908 | #define HAS_PCH_SPT(dev) (INTEL_PCH_TYPE(dev) == PCH_SPT) |
eb877ebf | 2909 | #define HAS_PCH_LPT(dev) (INTEL_PCH_TYPE(dev) == PCH_LPT) |
c2699524 | 2910 | #define HAS_PCH_LPT_LP(dev) (__I915__(dev)->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) |
56f5f700 | 2911 | #define HAS_PCH_LPT_H(dev) (__I915__(dev)->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE) |
cae5852d ZN |
2912 | #define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT) |
2913 | #define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX) | |
40c7ead9 | 2914 | #define HAS_PCH_NOP(dev) (INTEL_PCH_TYPE(dev) == PCH_NOP) |
45e6e3a1 | 2915 | #define HAS_PCH_SPLIT(dev) (INTEL_PCH_TYPE(dev) != PCH_NONE) |
cae5852d | 2916 | |
666a4537 WB |
2917 | #define HAS_GMCH_DISPLAY(dev) (INTEL_INFO(dev)->gen < 5 || \ |
2918 | IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) | |
5fafe292 | 2919 | |
040d2baa BW |
2920 | /* DPF == dynamic parity feature */ |
2921 | #define HAS_L3_DPF(dev) (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) | |
2922 | #define NUM_L3_SLICES(dev) (IS_HSW_GT3(dev) ? 2 : HAS_L3_DPF(dev)) | |
e1ef7cc2 | 2923 | |
c8735b0c | 2924 | #define GT_FREQUENCY_MULTIPLIER 50 |
de43ae9d | 2925 | #define GEN9_FREQ_SCALER 3 |
c8735b0c | 2926 | |
05394f39 CW |
2927 | #include "i915_trace.h" |
2928 | ||
48f112fe CW |
2929 | static inline bool intel_scanout_needs_vtd_wa(struct drm_i915_private *dev_priv) |
2930 | { | |
2931 | #ifdef CONFIG_INTEL_IOMMU | |
2932 | if (INTEL_GEN(dev_priv) >= 6 && intel_iommu_gfx_mapped) | |
2933 | return true; | |
2934 | #endif | |
2935 | return false; | |
2936 | } | |
2937 | ||
1751fcf9 ML |
2938 | extern int i915_suspend_switcheroo(struct drm_device *dev, pm_message_t state); |
2939 | extern int i915_resume_switcheroo(struct drm_device *dev); | |
7c1c2871 | 2940 | |
c033666a CW |
2941 | int intel_sanitize_enable_ppgtt(struct drm_i915_private *dev_priv, |
2942 | int enable_ppgtt); | |
0e4ca100 | 2943 | |
0673ad47 | 2944 | /* i915_drv.c */ |
d15d7538 ID |
2945 | void __printf(3, 4) |
2946 | __i915_printk(struct drm_i915_private *dev_priv, const char *level, | |
2947 | const char *fmt, ...); | |
2948 | ||
2949 | #define i915_report_error(dev_priv, fmt, ...) \ | |
2950 | __i915_printk(dev_priv, KERN_ERR, fmt, ##__VA_ARGS__) | |
2951 | ||
c43b5634 | 2952 | #ifdef CONFIG_COMPAT |
0d6aa60b DA |
2953 | extern long i915_compat_ioctl(struct file *filp, unsigned int cmd, |
2954 | unsigned long arg); | |
c43b5634 | 2955 | #endif |
dc97997a CW |
2956 | extern int intel_gpu_reset(struct drm_i915_private *dev_priv, u32 engine_mask); |
2957 | extern bool intel_has_gpu_reset(struct drm_i915_private *dev_priv); | |
c033666a | 2958 | extern int i915_reset(struct drm_i915_private *dev_priv); |
6b332fa2 | 2959 | extern int intel_guc_reset(struct drm_i915_private *dev_priv); |
fc0768ce | 2960 | extern void intel_engine_init_hangcheck(struct intel_engine_cs *engine); |
7648fa99 JB |
2961 | extern unsigned long i915_chipset_val(struct drm_i915_private *dev_priv); |
2962 | extern unsigned long i915_mch_val(struct drm_i915_private *dev_priv); | |
2963 | extern unsigned long i915_gfx_val(struct drm_i915_private *dev_priv); | |
2964 | extern void i915_update_gfx_val(struct drm_i915_private *dev_priv); | |
650ad970 | 2965 | int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool on); |
7648fa99 | 2966 | |
77913b39 | 2967 | /* intel_hotplug.c */ |
91d14251 TU |
2968 | void intel_hpd_irq_handler(struct drm_i915_private *dev_priv, |
2969 | u32 pin_mask, u32 long_mask); | |
77913b39 JN |
2970 | void intel_hpd_init(struct drm_i915_private *dev_priv); |
2971 | void intel_hpd_init_work(struct drm_i915_private *dev_priv); | |
2972 | void intel_hpd_cancel_work(struct drm_i915_private *dev_priv); | |
cc24fcdc | 2973 | bool intel_hpd_pin_to_port(enum hpd_pin pin, enum port *port); |
21842ea8 L |
2974 | bool intel_hpd_disable(struct drm_i915_private *dev_priv, enum hpd_pin pin); |
2975 | void intel_hpd_enable(struct drm_i915_private *dev_priv, enum hpd_pin pin); | |
77913b39 | 2976 | |
1da177e4 | 2977 | /* i915_irq.c */ |
26a02b8f CW |
2978 | static inline void i915_queue_hangcheck(struct drm_i915_private *dev_priv) |
2979 | { | |
2980 | unsigned long delay; | |
2981 | ||
2982 | if (unlikely(!i915.enable_hangcheck)) | |
2983 | return; | |
2984 | ||
2985 | /* Don't continually defer the hangcheck so that it is always run at | |
2986 | * least once after work has been scheduled on any ring. Otherwise, | |
2987 | * we will ignore a hung ring if a second ring is kept busy. | |
2988 | */ | |
2989 | ||
2990 | delay = round_jiffies_up_relative(DRM_I915_HANGCHECK_JIFFIES); | |
2991 | queue_delayed_work(system_long_wq, | |
2992 | &dev_priv->gpu_error.hangcheck_work, delay); | |
2993 | } | |
2994 | ||
58174462 | 2995 | __printf(3, 4) |
c033666a CW |
2996 | void i915_handle_error(struct drm_i915_private *dev_priv, |
2997 | u32 engine_mask, | |
58174462 | 2998 | const char *fmt, ...); |
1da177e4 | 2999 | |
b963291c | 3000 | extern void intel_irq_init(struct drm_i915_private *dev_priv); |
2aeb7d3a DV |
3001 | int intel_irq_install(struct drm_i915_private *dev_priv); |
3002 | void intel_irq_uninstall(struct drm_i915_private *dev_priv); | |
907b28c5 | 3003 | |
dc97997a CW |
3004 | extern void intel_uncore_sanitize(struct drm_i915_private *dev_priv); |
3005 | extern void intel_uncore_early_sanitize(struct drm_i915_private *dev_priv, | |
10018603 | 3006 | bool restore_forcewake); |
dc97997a | 3007 | extern void intel_uncore_init(struct drm_i915_private *dev_priv); |
fc97618b | 3008 | extern bool intel_uncore_unclaimed_mmio(struct drm_i915_private *dev_priv); |
bc3b9346 | 3009 | extern bool intel_uncore_arm_unclaimed_mmio_detection(struct drm_i915_private *dev_priv); |
dc97997a CW |
3010 | extern void intel_uncore_fini(struct drm_i915_private *dev_priv); |
3011 | extern void intel_uncore_forcewake_reset(struct drm_i915_private *dev_priv, | |
3012 | bool restore); | |
48c1026a | 3013 | const char *intel_uncore_forcewake_domain_to_str(const enum forcewake_domain_id id); |
59bad947 | 3014 | void intel_uncore_forcewake_get(struct drm_i915_private *dev_priv, |
48c1026a | 3015 | enum forcewake_domains domains); |
59bad947 | 3016 | void intel_uncore_forcewake_put(struct drm_i915_private *dev_priv, |
48c1026a | 3017 | enum forcewake_domains domains); |
a6111f7b CW |
3018 | /* Like above but the caller must manage the uncore.lock itself. |
3019 | * Must be used with I915_READ_FW and friends. | |
3020 | */ | |
3021 | void intel_uncore_forcewake_get__locked(struct drm_i915_private *dev_priv, | |
3022 | enum forcewake_domains domains); | |
3023 | void intel_uncore_forcewake_put__locked(struct drm_i915_private *dev_priv, | |
3024 | enum forcewake_domains domains); | |
3accaf7e MK |
3025 | u64 intel_uncore_edram_size(struct drm_i915_private *dev_priv); |
3026 | ||
59bad947 | 3027 | void assert_forcewakes_inactive(struct drm_i915_private *dev_priv); |
0ad35fed | 3028 | |
1758b90e CW |
3029 | int intel_wait_for_register(struct drm_i915_private *dev_priv, |
3030 | i915_reg_t reg, | |
3031 | const u32 mask, | |
3032 | const u32 value, | |
3033 | const unsigned long timeout_ms); | |
3034 | int intel_wait_for_register_fw(struct drm_i915_private *dev_priv, | |
3035 | i915_reg_t reg, | |
3036 | const u32 mask, | |
3037 | const u32 value, | |
3038 | const unsigned long timeout_ms); | |
3039 | ||
0ad35fed ZW |
3040 | static inline bool intel_gvt_active(struct drm_i915_private *dev_priv) |
3041 | { | |
3042 | return dev_priv->gvt.initialized; | |
3043 | } | |
3044 | ||
c033666a | 3045 | static inline bool intel_vgpu_active(struct drm_i915_private *dev_priv) |
cf9d2890 | 3046 | { |
c033666a | 3047 | return dev_priv->vgpu.active; |
cf9d2890 | 3048 | } |
b1f14ad0 | 3049 | |
7c463586 | 3050 | void |
50227e1c | 3051 | i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe, |
755e9019 | 3052 | u32 status_mask); |
7c463586 KP |
3053 | |
3054 | void | |
50227e1c | 3055 | i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe, |
755e9019 | 3056 | u32 status_mask); |
7c463586 | 3057 | |
f8b79e58 ID |
3058 | void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv); |
3059 | void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv); | |
0706f17c EE |
3060 | void i915_hotplug_interrupt_update(struct drm_i915_private *dev_priv, |
3061 | uint32_t mask, | |
3062 | uint32_t bits); | |
fbdedaea VS |
3063 | void ilk_update_display_irq(struct drm_i915_private *dev_priv, |
3064 | uint32_t interrupt_mask, | |
3065 | uint32_t enabled_irq_mask); | |
3066 | static inline void | |
3067 | ilk_enable_display_irq(struct drm_i915_private *dev_priv, uint32_t bits) | |
3068 | { | |
3069 | ilk_update_display_irq(dev_priv, bits, bits); | |
3070 | } | |
3071 | static inline void | |
3072 | ilk_disable_display_irq(struct drm_i915_private *dev_priv, uint32_t bits) | |
3073 | { | |
3074 | ilk_update_display_irq(dev_priv, bits, 0); | |
3075 | } | |
013d3752 VS |
3076 | void bdw_update_pipe_irq(struct drm_i915_private *dev_priv, |
3077 | enum pipe pipe, | |
3078 | uint32_t interrupt_mask, | |
3079 | uint32_t enabled_irq_mask); | |
3080 | static inline void bdw_enable_pipe_irq(struct drm_i915_private *dev_priv, | |
3081 | enum pipe pipe, uint32_t bits) | |
3082 | { | |
3083 | bdw_update_pipe_irq(dev_priv, pipe, bits, bits); | |
3084 | } | |
3085 | static inline void bdw_disable_pipe_irq(struct drm_i915_private *dev_priv, | |
3086 | enum pipe pipe, uint32_t bits) | |
3087 | { | |
3088 | bdw_update_pipe_irq(dev_priv, pipe, bits, 0); | |
3089 | } | |
47339cd9 DV |
3090 | void ibx_display_interrupt_update(struct drm_i915_private *dev_priv, |
3091 | uint32_t interrupt_mask, | |
3092 | uint32_t enabled_irq_mask); | |
14443261 VS |
3093 | static inline void |
3094 | ibx_enable_display_interrupt(struct drm_i915_private *dev_priv, uint32_t bits) | |
3095 | { | |
3096 | ibx_display_interrupt_update(dev_priv, bits, bits); | |
3097 | } | |
3098 | static inline void | |
3099 | ibx_disable_display_interrupt(struct drm_i915_private *dev_priv, uint32_t bits) | |
3100 | { | |
3101 | ibx_display_interrupt_update(dev_priv, bits, 0); | |
3102 | } | |
3103 | ||
673a394b | 3104 | /* i915_gem.c */ |
673a394b EA |
3105 | int i915_gem_create_ioctl(struct drm_device *dev, void *data, |
3106 | struct drm_file *file_priv); | |
3107 | int i915_gem_pread_ioctl(struct drm_device *dev, void *data, | |
3108 | struct drm_file *file_priv); | |
3109 | int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data, | |
3110 | struct drm_file *file_priv); | |
3111 | int i915_gem_mmap_ioctl(struct drm_device *dev, void *data, | |
3112 | struct drm_file *file_priv); | |
de151cf6 JB |
3113 | int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data, |
3114 | struct drm_file *file_priv); | |
673a394b EA |
3115 | int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data, |
3116 | struct drm_file *file_priv); | |
3117 | int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data, | |
3118 | struct drm_file *file_priv); | |
ba8b7ccb | 3119 | void i915_gem_execbuffer_move_to_active(struct list_head *vmas, |
8a8edb59 | 3120 | struct drm_i915_gem_request *req); |
5f19e2bf | 3121 | int i915_gem_ringbuffer_submission(struct i915_execbuffer_params *params, |
a83014d3 | 3122 | struct drm_i915_gem_execbuffer2 *args, |
5f19e2bf | 3123 | struct list_head *vmas); |
673a394b EA |
3124 | int i915_gem_execbuffer(struct drm_device *dev, void *data, |
3125 | struct drm_file *file_priv); | |
76446cac JB |
3126 | int i915_gem_execbuffer2(struct drm_device *dev, void *data, |
3127 | struct drm_file *file_priv); | |
673a394b EA |
3128 | int i915_gem_busy_ioctl(struct drm_device *dev, void *data, |
3129 | struct drm_file *file_priv); | |
199adf40 BW |
3130 | int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data, |
3131 | struct drm_file *file); | |
3132 | int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data, | |
3133 | struct drm_file *file); | |
673a394b EA |
3134 | int i915_gem_throttle_ioctl(struct drm_device *dev, void *data, |
3135 | struct drm_file *file_priv); | |
3ef94daa CW |
3136 | int i915_gem_madvise_ioctl(struct drm_device *dev, void *data, |
3137 | struct drm_file *file_priv); | |
673a394b EA |
3138 | int i915_gem_set_tiling(struct drm_device *dev, void *data, |
3139 | struct drm_file *file_priv); | |
3140 | int i915_gem_get_tiling(struct drm_device *dev, void *data, | |
3141 | struct drm_file *file_priv); | |
72778cb2 | 3142 | void i915_gem_init_userptr(struct drm_i915_private *dev_priv); |
5cc9ed4b CW |
3143 | int i915_gem_userptr_ioctl(struct drm_device *dev, void *data, |
3144 | struct drm_file *file); | |
5a125c3c EA |
3145 | int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data, |
3146 | struct drm_file *file_priv); | |
23ba4fd0 BW |
3147 | int i915_gem_wait_ioctl(struct drm_device *dev, void *data, |
3148 | struct drm_file *file_priv); | |
d64aa096 ID |
3149 | void i915_gem_load_init(struct drm_device *dev); |
3150 | void i915_gem_load_cleanup(struct drm_device *dev); | |
40ae4e16 | 3151 | void i915_gem_load_init_fences(struct drm_i915_private *dev_priv); |
461fb99c CW |
3152 | int i915_gem_freeze_late(struct drm_i915_private *dev_priv); |
3153 | ||
42dcedd4 CW |
3154 | void *i915_gem_object_alloc(struct drm_device *dev); |
3155 | void i915_gem_object_free(struct drm_i915_gem_object *obj); | |
37e680a1 CW |
3156 | void i915_gem_object_init(struct drm_i915_gem_object *obj, |
3157 | const struct drm_i915_gem_object_ops *ops); | |
d37cd8a8 | 3158 | struct drm_i915_gem_object *i915_gem_object_create(struct drm_device *dev, |
05394f39 | 3159 | size_t size); |
ea70299d DG |
3160 | struct drm_i915_gem_object *i915_gem_object_create_from_data( |
3161 | struct drm_device *dev, const void *data, size_t size); | |
673a394b | 3162 | void i915_gem_free_object(struct drm_gem_object *obj); |
2f633156 | 3163 | void i915_gem_vma_destroy(struct i915_vma *vma); |
42dcedd4 | 3164 | |
0875546c DV |
3165 | /* Flags used by pin/bind&friends. */ |
3166 | #define PIN_MAPPABLE (1<<0) | |
3167 | #define PIN_NONBLOCK (1<<1) | |
3168 | #define PIN_GLOBAL (1<<2) | |
3169 | #define PIN_OFFSET_BIAS (1<<3) | |
3170 | #define PIN_USER (1<<4) | |
3171 | #define PIN_UPDATE (1<<5) | |
101b506a MT |
3172 | #define PIN_ZONE_4G (1<<6) |
3173 | #define PIN_HIGH (1<<7) | |
506a8e87 | 3174 | #define PIN_OFFSET_FIXED (1<<8) |
d23db88c | 3175 | #define PIN_OFFSET_MASK (~4095) |
ec7adb6e JL |
3176 | int __must_check |
3177 | i915_gem_object_pin(struct drm_i915_gem_object *obj, | |
3178 | struct i915_address_space *vm, | |
3179 | uint32_t alignment, | |
3180 | uint64_t flags); | |
3181 | int __must_check | |
3182 | i915_gem_object_ggtt_pin(struct drm_i915_gem_object *obj, | |
3183 | const struct i915_ggtt_view *view, | |
3184 | uint32_t alignment, | |
3185 | uint64_t flags); | |
fe14d5f4 TU |
3186 | |
3187 | int i915_vma_bind(struct i915_vma *vma, enum i915_cache_level cache_level, | |
3188 | u32 flags); | |
d0710abb | 3189 | void __i915_vma_set_map_and_fenceable(struct i915_vma *vma); |
07fe0b12 | 3190 | int __must_check i915_vma_unbind(struct i915_vma *vma); |
e9f24d5f TU |
3191 | /* |
3192 | * BEWARE: Do not use the function below unless you can _absolutely_ | |
3193 | * _guarantee_ VMA in question is _not in use_ anywhere. | |
3194 | */ | |
3195 | int __must_check __i915_vma_unbind_no_wait(struct i915_vma *vma); | |
dd624afd | 3196 | int i915_gem_object_put_pages(struct drm_i915_gem_object *obj); |
48018a57 | 3197 | void i915_gem_release_all_mmaps(struct drm_i915_private *dev_priv); |
05394f39 | 3198 | void i915_gem_release_mmap(struct drm_i915_gem_object *obj); |
f787a5f5 | 3199 | |
4c914c0c BV |
3200 | int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object *obj, |
3201 | int *needs_clflush); | |
3202 | ||
37e680a1 | 3203 | int __must_check i915_gem_object_get_pages(struct drm_i915_gem_object *obj); |
ee286370 CW |
3204 | |
3205 | static inline int __sg_page_count(struct scatterlist *sg) | |
9da3da66 | 3206 | { |
ee286370 CW |
3207 | return sg->length >> PAGE_SHIFT; |
3208 | } | |
67d5a50c | 3209 | |
033908ae DG |
3210 | struct page * |
3211 | i915_gem_object_get_dirty_page(struct drm_i915_gem_object *obj, int n); | |
3212 | ||
341be1cd CW |
3213 | static inline dma_addr_t |
3214 | i915_gem_object_get_dma_address(struct drm_i915_gem_object *obj, int n) | |
3215 | { | |
3216 | if (n < obj->get_page.last) { | |
3217 | obj->get_page.sg = obj->pages->sgl; | |
3218 | obj->get_page.last = 0; | |
3219 | } | |
3220 | ||
3221 | while (obj->get_page.last + __sg_page_count(obj->get_page.sg) <= n) { | |
3222 | obj->get_page.last += __sg_page_count(obj->get_page.sg++); | |
3223 | if (unlikely(sg_is_chain(obj->get_page.sg))) | |
3224 | obj->get_page.sg = sg_chain_ptr(obj->get_page.sg); | |
3225 | } | |
3226 | ||
3227 | return sg_dma_address(obj->get_page.sg) + ((n - obj->get_page.last) << PAGE_SHIFT); | |
3228 | } | |
3229 | ||
ee286370 CW |
3230 | static inline struct page * |
3231 | i915_gem_object_get_page(struct drm_i915_gem_object *obj, int n) | |
9da3da66 | 3232 | { |
ee286370 CW |
3233 | if (WARN_ON(n >= obj->base.size >> PAGE_SHIFT)) |
3234 | return NULL; | |
67d5a50c | 3235 | |
ee286370 CW |
3236 | if (n < obj->get_page.last) { |
3237 | obj->get_page.sg = obj->pages->sgl; | |
3238 | obj->get_page.last = 0; | |
3239 | } | |
67d5a50c | 3240 | |
ee286370 CW |
3241 | while (obj->get_page.last + __sg_page_count(obj->get_page.sg) <= n) { |
3242 | obj->get_page.last += __sg_page_count(obj->get_page.sg++); | |
3243 | if (unlikely(sg_is_chain(obj->get_page.sg))) | |
3244 | obj->get_page.sg = sg_chain_ptr(obj->get_page.sg); | |
3245 | } | |
67d5a50c | 3246 | |
ee286370 | 3247 | return nth_page(sg_page(obj->get_page.sg), n - obj->get_page.last); |
9da3da66 | 3248 | } |
ee286370 | 3249 | |
a5570178 CW |
3250 | static inline void i915_gem_object_pin_pages(struct drm_i915_gem_object *obj) |
3251 | { | |
3252 | BUG_ON(obj->pages == NULL); | |
3253 | obj->pages_pin_count++; | |
3254 | } | |
0a798eb9 | 3255 | |
a5570178 CW |
3256 | static inline void i915_gem_object_unpin_pages(struct drm_i915_gem_object *obj) |
3257 | { | |
3258 | BUG_ON(obj->pages_pin_count == 0); | |
3259 | obj->pages_pin_count--; | |
3260 | } | |
3261 | ||
0a798eb9 CW |
3262 | /** |
3263 | * i915_gem_object_pin_map - return a contiguous mapping of the entire object | |
3264 | * @obj - the object to map into kernel address space | |
3265 | * | |
3266 | * Calls i915_gem_object_pin_pages() to prevent reaping of the object's | |
3267 | * pages and then returns a contiguous mapping of the backing storage into | |
3268 | * the kernel address space. | |
3269 | * | |
8305216f DG |
3270 | * The caller must hold the struct_mutex, and is responsible for calling |
3271 | * i915_gem_object_unpin_map() when the mapping is no longer required. | |
0a798eb9 | 3272 | * |
8305216f DG |
3273 | * Returns the pointer through which to access the mapped object, or an |
3274 | * ERR_PTR() on error. | |
0a798eb9 CW |
3275 | */ |
3276 | void *__must_check i915_gem_object_pin_map(struct drm_i915_gem_object *obj); | |
3277 | ||
3278 | /** | |
3279 | * i915_gem_object_unpin_map - releases an earlier mapping | |
3280 | * @obj - the object to unmap | |
3281 | * | |
3282 | * After pinning the object and mapping its pages, once you are finished | |
3283 | * with your access, call i915_gem_object_unpin_map() to release the pin | |
3284 | * upon the mapping. Once the pin count reaches zero, that mapping may be | |
3285 | * removed. | |
3286 | * | |
3287 | * The caller must hold the struct_mutex. | |
3288 | */ | |
3289 | static inline void i915_gem_object_unpin_map(struct drm_i915_gem_object *obj) | |
3290 | { | |
3291 | lockdep_assert_held(&obj->base.dev->struct_mutex); | |
3292 | i915_gem_object_unpin_pages(obj); | |
3293 | } | |
3294 | ||
54cf91dc | 3295 | int __must_check i915_mutex_lock_interruptible(struct drm_device *dev); |
2911a35b | 3296 | int i915_gem_object_sync(struct drm_i915_gem_object *obj, |
91af127f JH |
3297 | struct intel_engine_cs *to, |
3298 | struct drm_i915_gem_request **to_req); | |
e2d05a8b | 3299 | void i915_vma_move_to_active(struct i915_vma *vma, |
b2af0376 | 3300 | struct drm_i915_gem_request *req); |
ff72145b DA |
3301 | int i915_gem_dumb_create(struct drm_file *file_priv, |
3302 | struct drm_device *dev, | |
3303 | struct drm_mode_create_dumb *args); | |
da6b51d0 DA |
3304 | int i915_gem_mmap_gtt(struct drm_file *file_priv, struct drm_device *dev, |
3305 | uint32_t handle, uint64_t *offset); | |
85d1225e DG |
3306 | |
3307 | void i915_gem_track_fb(struct drm_i915_gem_object *old, | |
3308 | struct drm_i915_gem_object *new, | |
3309 | unsigned frontbuffer_bits); | |
3310 | ||
f787a5f5 CW |
3311 | /** |
3312 | * Returns true if seq1 is later than seq2. | |
3313 | */ | |
3314 | static inline bool | |
3315 | i915_seqno_passed(uint32_t seq1, uint32_t seq2) | |
3316 | { | |
3317 | return (int32_t)(seq1 - seq2) >= 0; | |
3318 | } | |
3319 | ||
f69a02c9 | 3320 | static inline bool i915_gem_request_started(const struct drm_i915_gem_request *req) |
821485dc | 3321 | { |
1b7744e7 | 3322 | return i915_seqno_passed(intel_engine_get_seqno(req->engine), |
c04e0f3b | 3323 | req->previous_seqno); |
821485dc CW |
3324 | } |
3325 | ||
f69a02c9 | 3326 | static inline bool i915_gem_request_completed(const struct drm_i915_gem_request *req) |
1b5a433a | 3327 | { |
1b7744e7 | 3328 | return i915_seqno_passed(intel_engine_get_seqno(req->engine), |
c04e0f3b | 3329 | req->seqno); |
1b5a433a JH |
3330 | } |
3331 | ||
f69a02c9 CW |
3332 | bool __i915_spin_request(const struct drm_i915_gem_request *request, |
3333 | int state, unsigned long timeout_us); | |
3334 | static inline bool i915_spin_request(const struct drm_i915_gem_request *request, | |
3335 | int state, unsigned long timeout_us) | |
3336 | { | |
3337 | return (i915_gem_request_started(request) && | |
3338 | __i915_spin_request(request, state, timeout_us)); | |
3339 | } | |
3340 | ||
c033666a | 3341 | int __must_check i915_gem_get_seqno(struct drm_i915_private *dev_priv, u32 *seqno); |
fca26bb4 | 3342 | int __must_check i915_gem_set_seqno(struct drm_device *dev, u32 seqno); |
1690e1eb | 3343 | |
8d9fc7fd | 3344 | struct drm_i915_gem_request * |
0bc40be8 | 3345 | i915_gem_find_active_request(struct intel_engine_cs *engine); |
8d9fc7fd | 3346 | |
67d97da3 | 3347 | void i915_gem_retire_requests(struct drm_i915_private *dev_priv); |
0bc40be8 | 3348 | void i915_gem_retire_requests_ring(struct intel_engine_cs *engine); |
84c33a64 | 3349 | |
c19ae989 CW |
3350 | static inline u32 i915_reset_counter(struct i915_gpu_error *error) |
3351 | { | |
3352 | return atomic_read(&error->reset_counter); | |
3353 | } | |
3354 | ||
3355 | static inline bool __i915_reset_in_progress(u32 reset) | |
3356 | { | |
3357 | return unlikely(reset & I915_RESET_IN_PROGRESS_FLAG); | |
3358 | } | |
3359 | ||
3360 | static inline bool __i915_reset_in_progress_or_wedged(u32 reset) | |
3361 | { | |
3362 | return unlikely(reset & (I915_RESET_IN_PROGRESS_FLAG | I915_WEDGED)); | |
3363 | } | |
3364 | ||
3365 | static inline bool __i915_terminally_wedged(u32 reset) | |
3366 | { | |
3367 | return unlikely(reset & I915_WEDGED); | |
3368 | } | |
3369 | ||
1f83fee0 DV |
3370 | static inline bool i915_reset_in_progress(struct i915_gpu_error *error) |
3371 | { | |
c19ae989 CW |
3372 | return __i915_reset_in_progress(i915_reset_counter(error)); |
3373 | } | |
3374 | ||
3375 | static inline bool i915_reset_in_progress_or_wedged(struct i915_gpu_error *error) | |
3376 | { | |
3377 | return __i915_reset_in_progress_or_wedged(i915_reset_counter(error)); | |
1f83fee0 DV |
3378 | } |
3379 | ||
3380 | static inline bool i915_terminally_wedged(struct i915_gpu_error *error) | |
3381 | { | |
c19ae989 | 3382 | return __i915_terminally_wedged(i915_reset_counter(error)); |
2ac0f450 MK |
3383 | } |
3384 | ||
3385 | static inline u32 i915_reset_count(struct i915_gpu_error *error) | |
3386 | { | |
c19ae989 | 3387 | return ((i915_reset_counter(error) & ~I915_WEDGED) + 1) / 2; |
1f83fee0 | 3388 | } |
a71d8d94 | 3389 | |
069efc1d | 3390 | void i915_gem_reset(struct drm_device *dev); |
000433b6 | 3391 | bool i915_gem_clflush_object(struct drm_i915_gem_object *obj, bool force); |
1070a42b | 3392 | int __must_check i915_gem_init(struct drm_device *dev); |
117897f4 | 3393 | int i915_gem_init_engines(struct drm_device *dev); |
f691e2f4 DV |
3394 | int __must_check i915_gem_init_hw(struct drm_device *dev); |
3395 | void i915_gem_init_swizzling(struct drm_device *dev); | |
117897f4 | 3396 | void i915_gem_cleanup_engines(struct drm_device *dev); |
6e5a5beb | 3397 | int __must_check i915_gem_wait_for_idle(struct drm_i915_private *dev_priv); |
45c5f202 | 3398 | int __must_check i915_gem_suspend(struct drm_device *dev); |
75289874 | 3399 | void __i915_add_request(struct drm_i915_gem_request *req, |
5b4a60c2 JH |
3400 | struct drm_i915_gem_object *batch_obj, |
3401 | bool flush_caches); | |
75289874 | 3402 | #define i915_add_request(req) \ |
fcfa423c | 3403 | __i915_add_request(req, NULL, true) |
75289874 | 3404 | #define i915_add_request_no_flush(req) \ |
fcfa423c | 3405 | __i915_add_request(req, NULL, false) |
9c654818 | 3406 | int __i915_wait_request(struct drm_i915_gem_request *req, |
16e9a21f ACO |
3407 | bool interruptible, |
3408 | s64 *timeout, | |
2e1b8730 | 3409 | struct intel_rps_client *rps); |
a4b3a571 | 3410 | int __must_check i915_wait_request(struct drm_i915_gem_request *req); |
de151cf6 | 3411 | int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf); |
2021746e | 3412 | int __must_check |
2e2f351d CW |
3413 | i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj, |
3414 | bool readonly); | |
3415 | int __must_check | |
2021746e CW |
3416 | i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, |
3417 | bool write); | |
3418 | int __must_check | |
dabdfe02 CW |
3419 | i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write); |
3420 | int __must_check | |
2da3b9b9 CW |
3421 | i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj, |
3422 | u32 alignment, | |
e6617330 TU |
3423 | const struct i915_ggtt_view *view); |
3424 | void i915_gem_object_unpin_from_display_plane(struct drm_i915_gem_object *obj, | |
3425 | const struct i915_ggtt_view *view); | |
00731155 | 3426 | int i915_gem_object_attach_phys(struct drm_i915_gem_object *obj, |
6eeefaf3 | 3427 | int align); |
b29c19b6 | 3428 | int i915_gem_open(struct drm_device *dev, struct drm_file *file); |
05394f39 | 3429 | void i915_gem_release(struct drm_device *dev, struct drm_file *file); |
673a394b | 3430 | |
0fa87796 ID |
3431 | uint32_t |
3432 | i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode); | |
467cffba | 3433 | uint32_t |
d865110c ID |
3434 | i915_gem_get_gtt_alignment(struct drm_device *dev, uint32_t size, |
3435 | int tiling_mode, bool fenced); | |
467cffba | 3436 | |
e4ffd173 CW |
3437 | int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj, |
3438 | enum i915_cache_level cache_level); | |
3439 | ||
1286ff73 DV |
3440 | struct drm_gem_object *i915_gem_prime_import(struct drm_device *dev, |
3441 | struct dma_buf *dma_buf); | |
3442 | ||
3443 | struct dma_buf *i915_gem_prime_export(struct drm_device *dev, | |
3444 | struct drm_gem_object *gem_obj, int flags); | |
3445 | ||
088e0df4 MT |
3446 | u64 i915_gem_obj_ggtt_offset_view(struct drm_i915_gem_object *o, |
3447 | const struct i915_ggtt_view *view); | |
3448 | u64 i915_gem_obj_offset(struct drm_i915_gem_object *o, | |
3449 | struct i915_address_space *vm); | |
3450 | static inline u64 | |
ec7adb6e | 3451 | i915_gem_obj_ggtt_offset(struct drm_i915_gem_object *o) |
fe14d5f4 | 3452 | { |
9abc4648 | 3453 | return i915_gem_obj_ggtt_offset_view(o, &i915_ggtt_view_normal); |
fe14d5f4 | 3454 | } |
ec7adb6e | 3455 | |
a70a3148 | 3456 | bool i915_gem_obj_bound_any(struct drm_i915_gem_object *o); |
ec7adb6e | 3457 | bool i915_gem_obj_ggtt_bound_view(struct drm_i915_gem_object *o, |
9abc4648 | 3458 | const struct i915_ggtt_view *view); |
a70a3148 | 3459 | bool i915_gem_obj_bound(struct drm_i915_gem_object *o, |
ec7adb6e | 3460 | struct i915_address_space *vm); |
fe14d5f4 | 3461 | |
fe14d5f4 | 3462 | struct i915_vma * |
ec7adb6e JL |
3463 | i915_gem_obj_to_vma(struct drm_i915_gem_object *obj, |
3464 | struct i915_address_space *vm); | |
3465 | struct i915_vma * | |
3466 | i915_gem_obj_to_ggtt_view(struct drm_i915_gem_object *obj, | |
3467 | const struct i915_ggtt_view *view); | |
fe14d5f4 | 3468 | |
accfef2e BW |
3469 | struct i915_vma * |
3470 | i915_gem_obj_lookup_or_create_vma(struct drm_i915_gem_object *obj, | |
ec7adb6e JL |
3471 | struct i915_address_space *vm); |
3472 | struct i915_vma * | |
3473 | i915_gem_obj_lookup_or_create_ggtt_vma(struct drm_i915_gem_object *obj, | |
3474 | const struct i915_ggtt_view *view); | |
5c2abbea | 3475 | |
ec7adb6e JL |
3476 | static inline struct i915_vma * |
3477 | i915_gem_obj_to_ggtt(struct drm_i915_gem_object *obj) | |
3478 | { | |
3479 | return i915_gem_obj_to_ggtt_view(obj, &i915_ggtt_view_normal); | |
d7f46fc4 | 3480 | } |
ec7adb6e | 3481 | bool i915_gem_obj_is_pinned(struct drm_i915_gem_object *obj); |
5c2abbea | 3482 | |
a70a3148 | 3483 | /* Some GGTT VM helpers */ |
841cd773 DV |
3484 | static inline struct i915_hw_ppgtt * |
3485 | i915_vm_to_ppgtt(struct i915_address_space *vm) | |
3486 | { | |
841cd773 DV |
3487 | return container_of(vm, struct i915_hw_ppgtt, base); |
3488 | } | |
3489 | ||
3490 | ||
a70a3148 BW |
3491 | static inline bool i915_gem_obj_ggtt_bound(struct drm_i915_gem_object *obj) |
3492 | { | |
9abc4648 | 3493 | return i915_gem_obj_ggtt_bound_view(obj, &i915_ggtt_view_normal); |
a70a3148 BW |
3494 | } |
3495 | ||
8da32727 TU |
3496 | unsigned long |
3497 | i915_gem_obj_ggtt_size(struct drm_i915_gem_object *obj); | |
c37e2204 BW |
3498 | |
3499 | static inline int __must_check | |
3500 | i915_gem_obj_ggtt_pin(struct drm_i915_gem_object *obj, | |
3501 | uint32_t alignment, | |
1ec9e26d | 3502 | unsigned flags) |
c37e2204 | 3503 | { |
72e96d64 JL |
3504 | struct drm_i915_private *dev_priv = to_i915(obj->base.dev); |
3505 | struct i915_ggtt *ggtt = &dev_priv->ggtt; | |
3506 | ||
3507 | return i915_gem_object_pin(obj, &ggtt->base, | |
5dc383b0 | 3508 | alignment, flags | PIN_GLOBAL); |
c37e2204 | 3509 | } |
a70a3148 | 3510 | |
e6617330 TU |
3511 | void i915_gem_object_ggtt_unpin_view(struct drm_i915_gem_object *obj, |
3512 | const struct i915_ggtt_view *view); | |
3513 | static inline void | |
3514 | i915_gem_object_ggtt_unpin(struct drm_i915_gem_object *obj) | |
3515 | { | |
3516 | i915_gem_object_ggtt_unpin_view(obj, &i915_ggtt_view_normal); | |
3517 | } | |
b287110e | 3518 | |
41a36b73 DV |
3519 | /* i915_gem_fence.c */ |
3520 | int __must_check i915_gem_object_get_fence(struct drm_i915_gem_object *obj); | |
3521 | int __must_check i915_gem_object_put_fence(struct drm_i915_gem_object *obj); | |
3522 | ||
3523 | bool i915_gem_object_pin_fence(struct drm_i915_gem_object *obj); | |
3524 | void i915_gem_object_unpin_fence(struct drm_i915_gem_object *obj); | |
3525 | ||
3526 | void i915_gem_restore_fences(struct drm_device *dev); | |
3527 | ||
7f96ecaf DV |
3528 | void i915_gem_detect_bit_6_swizzle(struct drm_device *dev); |
3529 | void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj); | |
3530 | void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj); | |
3531 | ||
254f965c | 3532 | /* i915_gem_context.c */ |
8245be31 | 3533 | int __must_check i915_gem_context_init(struct drm_device *dev); |
b2e862d0 | 3534 | void i915_gem_context_lost(struct drm_i915_private *dev_priv); |
254f965c | 3535 | void i915_gem_context_fini(struct drm_device *dev); |
acce9ffa | 3536 | void i915_gem_context_reset(struct drm_device *dev); |
e422b888 | 3537 | int i915_gem_context_open(struct drm_device *dev, struct drm_file *file); |
254f965c | 3538 | void i915_gem_context_close(struct drm_device *dev, struct drm_file *file); |
ba01cc93 | 3539 | int i915_switch_context(struct drm_i915_gem_request *req); |
dce3271b | 3540 | void i915_gem_context_free(struct kref *ctx_ref); |
8c857917 OM |
3541 | struct drm_i915_gem_object * |
3542 | i915_gem_alloc_context_obj(struct drm_device *dev, size_t size); | |
c8c35799 ZW |
3543 | struct i915_gem_context * |
3544 | i915_gem_context_create_gvt(struct drm_device *dev); | |
ca585b5d CW |
3545 | |
3546 | static inline struct i915_gem_context * | |
3547 | i915_gem_context_lookup(struct drm_i915_file_private *file_priv, u32 id) | |
3548 | { | |
3549 | struct i915_gem_context *ctx; | |
3550 | ||
091387c1 | 3551 | lockdep_assert_held(&file_priv->dev_priv->drm.struct_mutex); |
ca585b5d CW |
3552 | |
3553 | ctx = idr_find(&file_priv->context_idr, id); | |
3554 | if (!ctx) | |
3555 | return ERR_PTR(-ENOENT); | |
3556 | ||
3557 | return ctx; | |
3558 | } | |
3559 | ||
e2efd130 | 3560 | static inline void i915_gem_context_reference(struct i915_gem_context *ctx) |
dce3271b | 3561 | { |
691e6415 | 3562 | kref_get(&ctx->ref); |
dce3271b MK |
3563 | } |
3564 | ||
e2efd130 | 3565 | static inline void i915_gem_context_unreference(struct i915_gem_context *ctx) |
dce3271b | 3566 | { |
091387c1 | 3567 | lockdep_assert_held(&ctx->i915->drm.struct_mutex); |
691e6415 | 3568 | kref_put(&ctx->ref, i915_gem_context_free); |
dce3271b MK |
3569 | } |
3570 | ||
e2efd130 | 3571 | static inline bool i915_gem_context_is_default(const struct i915_gem_context *c) |
3fac8978 | 3572 | { |
821d66dd | 3573 | return c->user_handle == DEFAULT_CONTEXT_HANDLE; |
3fac8978 MK |
3574 | } |
3575 | ||
84624813 BW |
3576 | int i915_gem_context_create_ioctl(struct drm_device *dev, void *data, |
3577 | struct drm_file *file); | |
3578 | int i915_gem_context_destroy_ioctl(struct drm_device *dev, void *data, | |
3579 | struct drm_file *file); | |
c9dc0f35 CW |
3580 | int i915_gem_context_getparam_ioctl(struct drm_device *dev, void *data, |
3581 | struct drm_file *file_priv); | |
3582 | int i915_gem_context_setparam_ioctl(struct drm_device *dev, void *data, | |
3583 | struct drm_file *file_priv); | |
d538704b CW |
3584 | int i915_gem_context_reset_stats_ioctl(struct drm_device *dev, void *data, |
3585 | struct drm_file *file); | |
1286ff73 | 3586 | |
679845ed BW |
3587 | /* i915_gem_evict.c */ |
3588 | int __must_check i915_gem_evict_something(struct drm_device *dev, | |
3589 | struct i915_address_space *vm, | |
3590 | int min_size, | |
3591 | unsigned alignment, | |
3592 | unsigned cache_level, | |
d23db88c CW |
3593 | unsigned long start, |
3594 | unsigned long end, | |
1ec9e26d | 3595 | unsigned flags); |
506a8e87 | 3596 | int __must_check i915_gem_evict_for_vma(struct i915_vma *target); |
679845ed | 3597 | int i915_gem_evict_vm(struct i915_address_space *vm, bool do_idle); |
1d2a314c | 3598 | |
0260c420 | 3599 | /* belongs in i915_gem_gtt.h */ |
c033666a | 3600 | static inline void i915_gem_chipset_flush(struct drm_i915_private *dev_priv) |
e76e9aeb | 3601 | { |
dcd79934 | 3602 | wmb(); |
c033666a | 3603 | if (INTEL_GEN(dev_priv) < 6) |
e76e9aeb BW |
3604 | intel_gtt_chipset_flush(); |
3605 | } | |
246cbfb5 | 3606 | |
9797fbfb | 3607 | /* i915_gem_stolen.c */ |
d713fd49 PZ |
3608 | int i915_gem_stolen_insert_node(struct drm_i915_private *dev_priv, |
3609 | struct drm_mm_node *node, u64 size, | |
3610 | unsigned alignment); | |
a9da512b PZ |
3611 | int i915_gem_stolen_insert_node_in_range(struct drm_i915_private *dev_priv, |
3612 | struct drm_mm_node *node, u64 size, | |
3613 | unsigned alignment, u64 start, | |
3614 | u64 end); | |
d713fd49 PZ |
3615 | void i915_gem_stolen_remove_node(struct drm_i915_private *dev_priv, |
3616 | struct drm_mm_node *node); | |
9797fbfb CW |
3617 | int i915_gem_init_stolen(struct drm_device *dev); |
3618 | void i915_gem_cleanup_stolen(struct drm_device *dev); | |
0104fdbb CW |
3619 | struct drm_i915_gem_object * |
3620 | i915_gem_object_create_stolen(struct drm_device *dev, u32 size); | |
866d12b4 CW |
3621 | struct drm_i915_gem_object * |
3622 | i915_gem_object_create_stolen_for_preallocated(struct drm_device *dev, | |
3623 | u32 stolen_offset, | |
3624 | u32 gtt_offset, | |
3625 | u32 size); | |
9797fbfb | 3626 | |
be6a0376 DV |
3627 | /* i915_gem_shrinker.c */ |
3628 | unsigned long i915_gem_shrink(struct drm_i915_private *dev_priv, | |
14387540 | 3629 | unsigned long target, |
be6a0376 DV |
3630 | unsigned flags); |
3631 | #define I915_SHRINK_PURGEABLE 0x1 | |
3632 | #define I915_SHRINK_UNBOUND 0x2 | |
3633 | #define I915_SHRINK_BOUND 0x4 | |
5763ff04 | 3634 | #define I915_SHRINK_ACTIVE 0x8 |
eae2c43b | 3635 | #define I915_SHRINK_VMAPS 0x10 |
be6a0376 DV |
3636 | unsigned long i915_gem_shrink_all(struct drm_i915_private *dev_priv); |
3637 | void i915_gem_shrinker_init(struct drm_i915_private *dev_priv); | |
a8a40589 | 3638 | void i915_gem_shrinker_cleanup(struct drm_i915_private *dev_priv); |
be6a0376 DV |
3639 | |
3640 | ||
673a394b | 3641 | /* i915_gem_tiling.c */ |
2c1792a1 | 3642 | static inline bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj) |
e9b73c67 | 3643 | { |
091387c1 | 3644 | struct drm_i915_private *dev_priv = to_i915(obj->base.dev); |
e9b73c67 CW |
3645 | |
3646 | return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 && | |
3647 | obj->tiling_mode != I915_TILING_NONE; | |
3648 | } | |
3649 | ||
673a394b | 3650 | /* i915_gem_debug.c */ |
23bc5982 CW |
3651 | #if WATCH_LISTS |
3652 | int i915_verify_lists(struct drm_device *dev); | |
673a394b | 3653 | #else |
23bc5982 | 3654 | #define i915_verify_lists(dev) 0 |
673a394b | 3655 | #endif |
1da177e4 | 3656 | |
2017263e | 3657 | /* i915_debugfs.c */ |
f8c168fa | 3658 | #ifdef CONFIG_DEBUG_FS |
1dac891c CW |
3659 | int i915_debugfs_register(struct drm_i915_private *dev_priv); |
3660 | void i915_debugfs_unregister(struct drm_i915_private *dev_priv); | |
249e87de | 3661 | int i915_debugfs_connector_add(struct drm_connector *connector); |
07144428 DL |
3662 | void intel_display_crc_init(struct drm_device *dev); |
3663 | #else | |
25fd91dc LT |
3664 | static inline int i915_debugfs_register(struct drm_i915_private *dev_priv) {return 0;} |
3665 | static inline void i915_debugfs_unregister(struct drm_i915_private *dev_priv) {} | |
101057fa DV |
3666 | static inline int i915_debugfs_connector_add(struct drm_connector *connector) |
3667 | { return 0; } | |
f8c168fa | 3668 | static inline void intel_display_crc_init(struct drm_device *dev) {} |
07144428 | 3669 | #endif |
84734a04 MK |
3670 | |
3671 | /* i915_gpu_error.c */ | |
edc3d884 MK |
3672 | __printf(2, 3) |
3673 | void i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...); | |
fc16b48b MK |
3674 | int i915_error_state_to_str(struct drm_i915_error_state_buf *estr, |
3675 | const struct i915_error_state_file_priv *error); | |
4dc955f7 | 3676 | int i915_error_state_buf_init(struct drm_i915_error_state_buf *eb, |
0a4cd7c8 | 3677 | struct drm_i915_private *i915, |
4dc955f7 MK |
3678 | size_t count, loff_t pos); |
3679 | static inline void i915_error_state_buf_release( | |
3680 | struct drm_i915_error_state_buf *eb) | |
3681 | { | |
3682 | kfree(eb->buf); | |
3683 | } | |
c033666a CW |
3684 | void i915_capture_error_state(struct drm_i915_private *dev_priv, |
3685 | u32 engine_mask, | |
58174462 | 3686 | const char *error_msg); |
84734a04 MK |
3687 | void i915_error_state_get(struct drm_device *dev, |
3688 | struct i915_error_state_file_priv *error_priv); | |
3689 | void i915_error_state_put(struct i915_error_state_file_priv *error_priv); | |
3690 | void i915_destroy_error_state(struct drm_device *dev); | |
3691 | ||
c033666a | 3692 | void i915_get_extra_instdone(struct drm_i915_private *dev_priv, uint32_t *instdone); |
0a4cd7c8 | 3693 | const char *i915_cache_level_str(struct drm_i915_private *i915, int type); |
2017263e | 3694 | |
351e3db2 | 3695 | /* i915_cmd_parser.c */ |
1ca3712c | 3696 | int i915_cmd_parser_get_version(struct drm_i915_private *dev_priv); |
0bc40be8 TU |
3697 | int i915_cmd_parser_init_ring(struct intel_engine_cs *engine); |
3698 | void i915_cmd_parser_fini_ring(struct intel_engine_cs *engine); | |
3699 | bool i915_needs_cmd_parser(struct intel_engine_cs *engine); | |
3700 | int i915_parse_cmds(struct intel_engine_cs *engine, | |
351e3db2 | 3701 | struct drm_i915_gem_object *batch_obj, |
78a42377 | 3702 | struct drm_i915_gem_object *shadow_batch_obj, |
351e3db2 | 3703 | u32 batch_start_offset, |
b9ffd80e | 3704 | u32 batch_len, |
351e3db2 BV |
3705 | bool is_master); |
3706 | ||
317c35d1 JB |
3707 | /* i915_suspend.c */ |
3708 | extern int i915_save_state(struct drm_device *dev); | |
3709 | extern int i915_restore_state(struct drm_device *dev); | |
0a3e67a4 | 3710 | |
0136db58 BW |
3711 | /* i915_sysfs.c */ |
3712 | void i915_setup_sysfs(struct drm_device *dev_priv); | |
3713 | void i915_teardown_sysfs(struct drm_device *dev_priv); | |
3714 | ||
f899fc64 CW |
3715 | /* intel_i2c.c */ |
3716 | extern int intel_setup_gmbus(struct drm_device *dev); | |
3717 | extern void intel_teardown_gmbus(struct drm_device *dev); | |
88ac7939 JN |
3718 | extern bool intel_gmbus_is_valid_pin(struct drm_i915_private *dev_priv, |
3719 | unsigned int pin); | |
3bd7d909 | 3720 | |
0184df46 JN |
3721 | extern struct i2c_adapter * |
3722 | intel_gmbus_get_adapter(struct drm_i915_private *dev_priv, unsigned int pin); | |
e957d772 CW |
3723 | extern void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed); |
3724 | extern void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit); | |
8f375e10 | 3725 | static inline bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter) |
b8232e90 CW |
3726 | { |
3727 | return container_of(adapter, struct intel_gmbus, adapter)->force_bit; | |
3728 | } | |
f899fc64 CW |
3729 | extern void intel_i2c_reset(struct drm_device *dev); |
3730 | ||
8b8e1a89 | 3731 | /* intel_bios.c */ |
98f3a1dc | 3732 | int intel_bios_init(struct drm_i915_private *dev_priv); |
f0067a31 | 3733 | bool intel_bios_is_valid_vbt(const void *buf, size_t size); |
3bdd14d5 | 3734 | bool intel_bios_is_tv_present(struct drm_i915_private *dev_priv); |
5a69d13d | 3735 | bool intel_bios_is_lvds_present(struct drm_i915_private *dev_priv, u8 *i2c_pin); |
22f35042 | 3736 | bool intel_bios_is_port_present(struct drm_i915_private *dev_priv, enum port port); |
951d9efe | 3737 | bool intel_bios_is_port_edp(struct drm_i915_private *dev_priv, enum port port); |
d6199256 | 3738 | bool intel_bios_is_port_dp_dual_mode(struct drm_i915_private *dev_priv, enum port port); |
7137aec1 | 3739 | bool intel_bios_is_dsi_present(struct drm_i915_private *dev_priv, enum port *port); |
d252bf68 SS |
3740 | bool intel_bios_is_port_hpd_inverted(struct drm_i915_private *dev_priv, |
3741 | enum port port); | |
8b8e1a89 | 3742 | |
3b617967 | 3743 | /* intel_opregion.c */ |
44834a67 | 3744 | #ifdef CONFIG_ACPI |
6f9f4b7a | 3745 | extern int intel_opregion_setup(struct drm_i915_private *dev_priv); |
03d92e47 CW |
3746 | extern void intel_opregion_register(struct drm_i915_private *dev_priv); |
3747 | extern void intel_opregion_unregister(struct drm_i915_private *dev_priv); | |
91d14251 | 3748 | extern void intel_opregion_asle_intr(struct drm_i915_private *dev_priv); |
9c4b0a68 JN |
3749 | extern int intel_opregion_notify_encoder(struct intel_encoder *intel_encoder, |
3750 | bool enable); | |
6f9f4b7a | 3751 | extern int intel_opregion_notify_adapter(struct drm_i915_private *dev_priv, |
ecbc5cf3 | 3752 | pci_power_t state); |
6f9f4b7a | 3753 | extern int intel_opregion_get_panel_type(struct drm_i915_private *dev_priv); |
65e082c9 | 3754 | #else |
6f9f4b7a | 3755 | static inline int intel_opregion_setup(struct drm_i915_private *dev) { return 0; } |
bdaa2dfb RD |
3756 | static inline void intel_opregion_register(struct drm_i915_private *dev_priv) { } |
3757 | static inline void intel_opregion_unregister(struct drm_i915_private *dev_priv) { } | |
91d14251 TU |
3758 | static inline void intel_opregion_asle_intr(struct drm_i915_private *dev_priv) |
3759 | { | |
3760 | } | |
9c4b0a68 JN |
3761 | static inline int |
3762 | intel_opregion_notify_encoder(struct intel_encoder *intel_encoder, bool enable) | |
3763 | { | |
3764 | return 0; | |
3765 | } | |
ecbc5cf3 | 3766 | static inline int |
6f9f4b7a | 3767 | intel_opregion_notify_adapter(struct drm_i915_private *dev, pci_power_t state) |
ecbc5cf3 JN |
3768 | { |
3769 | return 0; | |
3770 | } | |
6f9f4b7a | 3771 | static inline int intel_opregion_get_panel_type(struct drm_i915_private *dev) |
a0562819 VS |
3772 | { |
3773 | return -ENODEV; | |
3774 | } | |
65e082c9 | 3775 | #endif |
8ee1c3db | 3776 | |
723bfd70 JB |
3777 | /* intel_acpi.c */ |
3778 | #ifdef CONFIG_ACPI | |
3779 | extern void intel_register_dsm_handler(void); | |
3780 | extern void intel_unregister_dsm_handler(void); | |
3781 | #else | |
3782 | static inline void intel_register_dsm_handler(void) { return; } | |
3783 | static inline void intel_unregister_dsm_handler(void) { return; } | |
3784 | #endif /* CONFIG_ACPI */ | |
3785 | ||
94b4f3ba CW |
3786 | /* intel_device_info.c */ |
3787 | static inline struct intel_device_info * | |
3788 | mkwrite_device_info(struct drm_i915_private *dev_priv) | |
3789 | { | |
3790 | return (struct intel_device_info *)&dev_priv->info; | |
3791 | } | |
3792 | ||
3793 | void intel_device_info_runtime_init(struct drm_i915_private *dev_priv); | |
3794 | void intel_device_info_dump(struct drm_i915_private *dev_priv); | |
3795 | ||
79e53945 | 3796 | /* modesetting */ |
f817586c | 3797 | extern void intel_modeset_init_hw(struct drm_device *dev); |
79e53945 | 3798 | extern void intel_modeset_init(struct drm_device *dev); |
2c7111db | 3799 | extern void intel_modeset_gem_init(struct drm_device *dev); |
79e53945 | 3800 | extern void intel_modeset_cleanup(struct drm_device *dev); |
1ebaa0b9 | 3801 | extern int intel_connector_register(struct drm_connector *); |
c191eca1 | 3802 | extern void intel_connector_unregister(struct drm_connector *); |
28d52043 | 3803 | extern int intel_modeset_vga_set_state(struct drm_device *dev, bool state); |
043e9bda | 3804 | extern void intel_display_resume(struct drm_device *dev); |
44cec740 | 3805 | extern void i915_redisable_vga(struct drm_device *dev); |
04098753 | 3806 | extern void i915_redisable_vga_power_on(struct drm_device *dev); |
91d14251 | 3807 | extern bool ironlake_set_drps(struct drm_i915_private *dev_priv, u8 val); |
dde86e2d | 3808 | extern void intel_init_pch_refclk(struct drm_device *dev); |
dc97997a | 3809 | extern void intel_set_rps(struct drm_i915_private *dev_priv, u8 val); |
5209b1f4 ID |
3810 | extern void intel_set_memory_cxsr(struct drm_i915_private *dev_priv, |
3811 | bool enable); | |
3bad0781 | 3812 | |
c033666a | 3813 | extern bool i915_semaphore_is_enabled(struct drm_i915_private *dev_priv); |
c0c7babc BW |
3814 | int i915_reg_read_ioctl(struct drm_device *dev, void *data, |
3815 | struct drm_file *file); | |
575155a9 | 3816 | |
6ef3d427 | 3817 | /* overlay */ |
c033666a CW |
3818 | extern struct intel_overlay_error_state * |
3819 | intel_overlay_capture_error_state(struct drm_i915_private *dev_priv); | |
edc3d884 MK |
3820 | extern void intel_overlay_print_error_state(struct drm_i915_error_state_buf *e, |
3821 | struct intel_overlay_error_state *error); | |
c4a1d9e4 | 3822 | |
c033666a CW |
3823 | extern struct intel_display_error_state * |
3824 | intel_display_capture_error_state(struct drm_i915_private *dev_priv); | |
edc3d884 | 3825 | extern void intel_display_print_error_state(struct drm_i915_error_state_buf *e, |
c4a1d9e4 CW |
3826 | struct drm_device *dev, |
3827 | struct intel_display_error_state *error); | |
6ef3d427 | 3828 | |
151a49d0 TR |
3829 | int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *val); |
3830 | int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u32 mbox, u32 val); | |
59de0813 JN |
3831 | |
3832 | /* intel_sideband.c */ | |
707b6e3d D |
3833 | u32 vlv_punit_read(struct drm_i915_private *dev_priv, u32 addr); |
3834 | void vlv_punit_write(struct drm_i915_private *dev_priv, u32 addr, u32 val); | |
64936258 | 3835 | u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr); |
dfb19ed2 D |
3836 | u32 vlv_iosf_sb_read(struct drm_i915_private *dev_priv, u8 port, u32 reg); |
3837 | void vlv_iosf_sb_write(struct drm_i915_private *dev_priv, u8 port, u32 reg, u32 val); | |
e9f882a3 JN |
3838 | u32 vlv_cck_read(struct drm_i915_private *dev_priv, u32 reg); |
3839 | void vlv_cck_write(struct drm_i915_private *dev_priv, u32 reg, u32 val); | |
3840 | u32 vlv_ccu_read(struct drm_i915_private *dev_priv, u32 reg); | |
3841 | void vlv_ccu_write(struct drm_i915_private *dev_priv, u32 reg, u32 val); | |
f3419158 JB |
3842 | u32 vlv_bunit_read(struct drm_i915_private *dev_priv, u32 reg); |
3843 | void vlv_bunit_write(struct drm_i915_private *dev_priv, u32 reg, u32 val); | |
5e69f97f CML |
3844 | u32 vlv_dpio_read(struct drm_i915_private *dev_priv, enum pipe pipe, int reg); |
3845 | void vlv_dpio_write(struct drm_i915_private *dev_priv, enum pipe pipe, int reg, u32 val); | |
59de0813 JN |
3846 | u32 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg, |
3847 | enum intel_sbi_destination destination); | |
3848 | void intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value, | |
3849 | enum intel_sbi_destination destination); | |
e9fe51c6 SK |
3850 | u32 vlv_flisdsi_read(struct drm_i915_private *dev_priv, u32 reg); |
3851 | void vlv_flisdsi_write(struct drm_i915_private *dev_priv, u32 reg, u32 val); | |
0a073b84 | 3852 | |
b7fa22d8 ACO |
3853 | /* intel_dpio_phy.c */ |
3854 | void chv_set_phy_signal_level(struct intel_encoder *encoder, | |
3855 | u32 deemph_reg_value, u32 margin_reg_value, | |
3856 | bool uniq_trans_scale); | |
844b2f9a ACO |
3857 | void chv_data_lane_soft_reset(struct intel_encoder *encoder, |
3858 | bool reset); | |
419b1b7a | 3859 | void chv_phy_pre_pll_enable(struct intel_encoder *encoder); |
e7d2a717 ACO |
3860 | void chv_phy_pre_encoder_enable(struct intel_encoder *encoder); |
3861 | void chv_phy_release_cl2_override(struct intel_encoder *encoder); | |
204970b5 | 3862 | void chv_phy_post_pll_disable(struct intel_encoder *encoder); |
b7fa22d8 | 3863 | |
53d98725 ACO |
3864 | void vlv_set_phy_signal_level(struct intel_encoder *encoder, |
3865 | u32 demph_reg_value, u32 preemph_reg_value, | |
3866 | u32 uniqtranscale_reg_value, u32 tx3_demph); | |
6da2e616 | 3867 | void vlv_phy_pre_pll_enable(struct intel_encoder *encoder); |
5f68c275 | 3868 | void vlv_phy_pre_encoder_enable(struct intel_encoder *encoder); |
0f572ebe | 3869 | void vlv_phy_reset_lanes(struct intel_encoder *encoder); |
53d98725 | 3870 | |
616bc820 VS |
3871 | int intel_gpu_freq(struct drm_i915_private *dev_priv, int val); |
3872 | int intel_freq_opcode(struct drm_i915_private *dev_priv, int val); | |
c8d9a590 | 3873 | |
0b274481 BW |
3874 | #define I915_READ8(reg) dev_priv->uncore.funcs.mmio_readb(dev_priv, (reg), true) |
3875 | #define I915_WRITE8(reg, val) dev_priv->uncore.funcs.mmio_writeb(dev_priv, (reg), (val), true) | |
3876 | ||
3877 | #define I915_READ16(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), true) | |
3878 | #define I915_WRITE16(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), true) | |
3879 | #define I915_READ16_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), false) | |
3880 | #define I915_WRITE16_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), false) | |
3881 | ||
3882 | #define I915_READ(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), true) | |
3883 | #define I915_WRITE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), true) | |
3884 | #define I915_READ_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), false) | |
3885 | #define I915_WRITE_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), false) | |
3886 | ||
698b3135 CW |
3887 | /* Be very careful with read/write 64-bit values. On 32-bit machines, they |
3888 | * will be implemented using 2 32-bit writes in an arbitrary order with | |
3889 | * an arbitrary delay between them. This can cause the hardware to | |
3890 | * act upon the intermediate value, possibly leading to corruption and | |
3891 | * machine death. You have been warned. | |
3892 | */ | |
0b274481 BW |
3893 | #define I915_WRITE64(reg, val) dev_priv->uncore.funcs.mmio_writeq(dev_priv, (reg), (val), true) |
3894 | #define I915_READ64(reg) dev_priv->uncore.funcs.mmio_readq(dev_priv, (reg), true) | |
cae5852d | 3895 | |
50877445 | 3896 | #define I915_READ64_2x32(lower_reg, upper_reg) ({ \ |
acd29f7b CW |
3897 | u32 upper, lower, old_upper, loop = 0; \ |
3898 | upper = I915_READ(upper_reg); \ | |
ee0a227b | 3899 | do { \ |
acd29f7b | 3900 | old_upper = upper; \ |
ee0a227b | 3901 | lower = I915_READ(lower_reg); \ |
acd29f7b CW |
3902 | upper = I915_READ(upper_reg); \ |
3903 | } while (upper != old_upper && loop++ < 2); \ | |
ee0a227b | 3904 | (u64)upper << 32 | lower; }) |
50877445 | 3905 | |
cae5852d ZN |
3906 | #define POSTING_READ(reg) (void)I915_READ_NOTRACE(reg) |
3907 | #define POSTING_READ16(reg) (void)I915_READ16_NOTRACE(reg) | |
3908 | ||
75aa3f63 VS |
3909 | #define __raw_read(x, s) \ |
3910 | static inline uint##x##_t __raw_i915_read##x(struct drm_i915_private *dev_priv, \ | |
f0f59a00 | 3911 | i915_reg_t reg) \ |
75aa3f63 | 3912 | { \ |
f0f59a00 | 3913 | return read##s(dev_priv->regs + i915_mmio_reg_offset(reg)); \ |
75aa3f63 VS |
3914 | } |
3915 | ||
3916 | #define __raw_write(x, s) \ | |
3917 | static inline void __raw_i915_write##x(struct drm_i915_private *dev_priv, \ | |
f0f59a00 | 3918 | i915_reg_t reg, uint##x##_t val) \ |
75aa3f63 | 3919 | { \ |
f0f59a00 | 3920 | write##s(val, dev_priv->regs + i915_mmio_reg_offset(reg)); \ |
75aa3f63 VS |
3921 | } |
3922 | __raw_read(8, b) | |
3923 | __raw_read(16, w) | |
3924 | __raw_read(32, l) | |
3925 | __raw_read(64, q) | |
3926 | ||
3927 | __raw_write(8, b) | |
3928 | __raw_write(16, w) | |
3929 | __raw_write(32, l) | |
3930 | __raw_write(64, q) | |
3931 | ||
3932 | #undef __raw_read | |
3933 | #undef __raw_write | |
3934 | ||
a6111f7b CW |
3935 | /* These are untraced mmio-accessors that are only valid to be used inside |
3936 | * criticial sections inside IRQ handlers where forcewake is explicitly | |
3937 | * controlled. | |
3938 | * Think twice, and think again, before using these. | |
3939 | * Note: Should only be used between intel_uncore_forcewake_irqlock() and | |
3940 | * intel_uncore_forcewake_irqunlock(). | |
3941 | */ | |
75aa3f63 VS |
3942 | #define I915_READ_FW(reg__) __raw_i915_read32(dev_priv, (reg__)) |
3943 | #define I915_WRITE_FW(reg__, val__) __raw_i915_write32(dev_priv, (reg__), (val__)) | |
76f8421f | 3944 | #define I915_WRITE64_FW(reg__, val__) __raw_i915_write64(dev_priv, (reg__), (val__)) |
a6111f7b CW |
3945 | #define POSTING_READ_FW(reg__) (void)I915_READ_FW(reg__) |
3946 | ||
55bc60db VS |
3947 | /* "Broadcast RGB" property */ |
3948 | #define INTEL_BROADCAST_RGB_AUTO 0 | |
3949 | #define INTEL_BROADCAST_RGB_FULL 1 | |
3950 | #define INTEL_BROADCAST_RGB_LIMITED 2 | |
ba4f01a3 | 3951 | |
f0f59a00 | 3952 | static inline i915_reg_t i915_vgacntrl_reg(struct drm_device *dev) |
766aa1c4 | 3953 | { |
666a4537 | 3954 | if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) |
766aa1c4 | 3955 | return VLV_VGACNTRL; |
92e23b99 SJ |
3956 | else if (INTEL_INFO(dev)->gen >= 5) |
3957 | return CPU_VGACNTRL; | |
766aa1c4 VS |
3958 | else |
3959 | return VGACNTRL; | |
3960 | } | |
3961 | ||
df97729f ID |
3962 | static inline unsigned long msecs_to_jiffies_timeout(const unsigned int m) |
3963 | { | |
3964 | unsigned long j = msecs_to_jiffies(m); | |
3965 | ||
3966 | return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1); | |
3967 | } | |
3968 | ||
7bd0e226 DV |
3969 | static inline unsigned long nsecs_to_jiffies_timeout(const u64 n) |
3970 | { | |
3971 | return min_t(u64, MAX_JIFFY_OFFSET, nsecs_to_jiffies64(n) + 1); | |
3972 | } | |
3973 | ||
df97729f ID |
3974 | static inline unsigned long |
3975 | timespec_to_jiffies_timeout(const struct timespec *value) | |
3976 | { | |
3977 | unsigned long j = timespec_to_jiffies(value); | |
3978 | ||
3979 | return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1); | |
3980 | } | |
3981 | ||
dce56b3c PZ |
3982 | /* |
3983 | * If you need to wait X milliseconds between events A and B, but event B | |
3984 | * doesn't happen exactly after event A, you record the timestamp (jiffies) of | |
3985 | * when event A happened, then just before event B you call this function and | |
3986 | * pass the timestamp as the first argument, and X as the second argument. | |
3987 | */ | |
3988 | static inline void | |
3989 | wait_remaining_ms_from_jiffies(unsigned long timestamp_jiffies, int to_wait_ms) | |
3990 | { | |
ec5e0cfb | 3991 | unsigned long target_jiffies, tmp_jiffies, remaining_jiffies; |
dce56b3c PZ |
3992 | |
3993 | /* | |
3994 | * Don't re-read the value of "jiffies" every time since it may change | |
3995 | * behind our back and break the math. | |
3996 | */ | |
3997 | tmp_jiffies = jiffies; | |
3998 | target_jiffies = timestamp_jiffies + | |
3999 | msecs_to_jiffies_timeout(to_wait_ms); | |
4000 | ||
4001 | if (time_after(target_jiffies, tmp_jiffies)) { | |
ec5e0cfb ID |
4002 | remaining_jiffies = target_jiffies - tmp_jiffies; |
4003 | while (remaining_jiffies) | |
4004 | remaining_jiffies = | |
4005 | schedule_timeout_uninterruptible(remaining_jiffies); | |
dce56b3c PZ |
4006 | } |
4007 | } | |
688e6c72 CW |
4008 | static inline bool __i915_request_irq_complete(struct drm_i915_gem_request *req) |
4009 | { | |
f69a02c9 CW |
4010 | struct intel_engine_cs *engine = req->engine; |
4011 | ||
7ec2c73b CW |
4012 | /* Before we do the heavier coherent read of the seqno, |
4013 | * check the value (hopefully) in the CPU cacheline. | |
4014 | */ | |
4015 | if (i915_gem_request_completed(req)) | |
4016 | return true; | |
4017 | ||
688e6c72 CW |
4018 | /* Ensure our read of the seqno is coherent so that we |
4019 | * do not "miss an interrupt" (i.e. if this is the last | |
4020 | * request and the seqno write from the GPU is not visible | |
4021 | * by the time the interrupt fires, we will see that the | |
4022 | * request is incomplete and go back to sleep awaiting | |
4023 | * another interrupt that will never come.) | |
4024 | * | |
4025 | * Strictly, we only need to do this once after an interrupt, | |
4026 | * but it is easier and safer to do it every time the waiter | |
4027 | * is woken. | |
4028 | */ | |
3d5564e9 | 4029 | if (engine->irq_seqno_barrier && |
aca34b6e CW |
4030 | READ_ONCE(engine->breadcrumbs.irq_seqno_bh) == current && |
4031 | cmpxchg_relaxed(&engine->breadcrumbs.irq_posted, 1, 0)) { | |
99fe4a5f CW |
4032 | struct task_struct *tsk; |
4033 | ||
3d5564e9 CW |
4034 | /* The ordering of irq_posted versus applying the barrier |
4035 | * is crucial. The clearing of the current irq_posted must | |
4036 | * be visible before we perform the barrier operation, | |
4037 | * such that if a subsequent interrupt arrives, irq_posted | |
4038 | * is reasserted and our task rewoken (which causes us to | |
4039 | * do another __i915_request_irq_complete() immediately | |
4040 | * and reapply the barrier). Conversely, if the clear | |
4041 | * occurs after the barrier, then an interrupt that arrived | |
4042 | * whilst we waited on the barrier would not trigger a | |
4043 | * barrier on the next pass, and the read may not see the | |
4044 | * seqno update. | |
4045 | */ | |
f69a02c9 | 4046 | engine->irq_seqno_barrier(engine); |
99fe4a5f CW |
4047 | |
4048 | /* If we consume the irq, but we are no longer the bottom-half, | |
4049 | * the real bottom-half may not have serialised their own | |
4050 | * seqno check with the irq-barrier (i.e. may have inspected | |
4051 | * the seqno before we believe it coherent since they see | |
4052 | * irq_posted == false but we are still running). | |
4053 | */ | |
4054 | rcu_read_lock(); | |
aca34b6e | 4055 | tsk = READ_ONCE(engine->breadcrumbs.irq_seqno_bh); |
99fe4a5f CW |
4056 | if (tsk && tsk != current) |
4057 | /* Note that if the bottom-half is changed as we | |
4058 | * are sending the wake-up, the new bottom-half will | |
4059 | * be woken by whomever made the change. We only have | |
4060 | * to worry about when we steal the irq-posted for | |
4061 | * ourself. | |
4062 | */ | |
4063 | wake_up_process(tsk); | |
4064 | rcu_read_unlock(); | |
4065 | ||
7ec2c73b CW |
4066 | if (i915_gem_request_completed(req)) |
4067 | return true; | |
4068 | } | |
688e6c72 CW |
4069 | |
4070 | /* We need to check whether any gpu reset happened in between | |
4071 | * the request being submitted and now. If a reset has occurred, | |
4072 | * the seqno will have been advance past ours and our request | |
4073 | * is complete. If we are in the process of handling a reset, | |
4074 | * the request is effectively complete as the rendering will | |
4075 | * be discarded, but we need to return in order to drop the | |
4076 | * struct_mutex. | |
4077 | */ | |
4078 | if (i915_reset_in_progress(&req->i915->gpu_error)) | |
4079 | return true; | |
4080 | ||
4081 | return false; | |
4082 | } | |
4083 | ||
1da177e4 | 4084 | #endif |