Commit | Line | Data |
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1da177e4 LT |
1 | /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*- |
2 | */ | |
0d6aa60b | 3 | /* |
bc54fd1a | 4 | * |
1da177e4 LT |
5 | * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. |
6 | * All Rights Reserved. | |
bc54fd1a DA |
7 | * |
8 | * Permission is hereby granted, free of charge, to any person obtaining a | |
9 | * copy of this software and associated documentation files (the | |
10 | * "Software"), to deal in the Software without restriction, including | |
11 | * without limitation the rights to use, copy, modify, merge, publish, | |
12 | * distribute, sub license, and/or sell copies of the Software, and to | |
13 | * permit persons to whom the Software is furnished to do so, subject to | |
14 | * the following conditions: | |
15 | * | |
16 | * The above copyright notice and this permission notice (including the | |
17 | * next paragraph) shall be included in all copies or substantial portions | |
18 | * of the Software. | |
19 | * | |
20 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS | |
21 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
22 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. | |
23 | * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR | |
24 | * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, | |
25 | * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE | |
26 | * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. | |
27 | * | |
0d6aa60b | 28 | */ |
1da177e4 LT |
29 | |
30 | #ifndef _I915_DRV_H_ | |
31 | #define _I915_DRV_H_ | |
32 | ||
e9b73c67 | 33 | #include <uapi/drm/i915_drm.h> |
93b81f51 | 34 | #include <uapi/drm/drm_fourcc.h> |
e9b73c67 | 35 | |
0839ccb8 | 36 | #include <linux/io-mapping.h> |
f899fc64 | 37 | #include <linux/i2c.h> |
c167a6fc | 38 | #include <linux/i2c-algo-bit.h> |
aaa6fd2a | 39 | #include <linux/backlight.h> |
5cc9ed4b | 40 | #include <linux/hashtable.h> |
2911a35b | 41 | #include <linux/intel-iommu.h> |
742cbee8 | 42 | #include <linux/kref.h> |
9ee32fea | 43 | #include <linux/pm_qos.h> |
e73bdd20 CW |
44 | #include <linux/shmem_fs.h> |
45 | ||
46 | #include <drm/drmP.h> | |
47 | #include <drm/intel-gtt.h> | |
48 | #include <drm/drm_legacy.h> /* for struct drm_dma_handle */ | |
49 | #include <drm/drm_gem.h> | |
3b96a0b1 | 50 | #include <drm/drm_auth.h> |
e73bdd20 CW |
51 | |
52 | #include "i915_params.h" | |
53 | #include "i915_reg.h" | |
54 | ||
55 | #include "intel_bios.h" | |
ac7f11c6 | 56 | #include "intel_dpll_mgr.h" |
e73bdd20 CW |
57 | #include "intel_guc.h" |
58 | #include "intel_lrc.h" | |
59 | #include "intel_ringbuffer.h" | |
60 | ||
d501b1d2 | 61 | #include "i915_gem.h" |
e73bdd20 CW |
62 | #include "i915_gem_gtt.h" |
63 | #include "i915_gem_render_state.h" | |
05235c53 | 64 | #include "i915_gem_request.h" |
585fb111 | 65 | |
0ad35fed ZW |
66 | #include "intel_gvt.h" |
67 | ||
1da177e4 LT |
68 | /* General customization: |
69 | */ | |
70 | ||
1da177e4 LT |
71 | #define DRIVER_NAME "i915" |
72 | #define DRIVER_DESC "Intel Graphics" | |
c4a8a7c7 | 73 | #define DRIVER_DATE "20160902" |
1da177e4 | 74 | |
c883ef1b | 75 | #undef WARN_ON |
5f77eeb0 DV |
76 | /* Many gcc seem to no see through this and fall over :( */ |
77 | #if 0 | |
78 | #define WARN_ON(x) ({ \ | |
79 | bool __i915_warn_cond = (x); \ | |
80 | if (__builtin_constant_p(__i915_warn_cond)) \ | |
81 | BUILD_BUG_ON(__i915_warn_cond); \ | |
82 | WARN(__i915_warn_cond, "WARN_ON(" #x ")"); }) | |
83 | #else | |
152b2262 | 84 | #define WARN_ON(x) WARN((x), "%s", "WARN_ON(" __stringify(x) ")") |
5f77eeb0 DV |
85 | #endif |
86 | ||
cd9bfacb | 87 | #undef WARN_ON_ONCE |
152b2262 | 88 | #define WARN_ON_ONCE(x) WARN_ONCE((x), "%s", "WARN_ON_ONCE(" __stringify(x) ")") |
cd9bfacb | 89 | |
5f77eeb0 DV |
90 | #define MISSING_CASE(x) WARN(1, "Missing switch case (%lu) in %s\n", \ |
91 | (long) (x), __func__); | |
c883ef1b | 92 | |
e2c719b7 RC |
93 | /* Use I915_STATE_WARN(x) and I915_STATE_WARN_ON() (rather than WARN() and |
94 | * WARN_ON()) for hw state sanity checks to check for unexpected conditions | |
95 | * which may not necessarily be a user visible problem. This will either | |
96 | * WARN() or DRM_ERROR() depending on the verbose_checks moduleparam, to | |
97 | * enable distros and users to tailor their preferred amount of i915 abrt | |
98 | * spam. | |
99 | */ | |
100 | #define I915_STATE_WARN(condition, format...) ({ \ | |
101 | int __ret_warn_on = !!(condition); \ | |
32753cb8 JL |
102 | if (unlikely(__ret_warn_on)) \ |
103 | if (!WARN(i915.verbose_state_checks, format)) \ | |
e2c719b7 | 104 | DRM_ERROR(format); \ |
e2c719b7 RC |
105 | unlikely(__ret_warn_on); \ |
106 | }) | |
107 | ||
152b2262 JL |
108 | #define I915_STATE_WARN_ON(x) \ |
109 | I915_STATE_WARN((x), "%s", "WARN_ON(" __stringify(x) ")") | |
c883ef1b | 110 | |
4fec15d1 ID |
111 | bool __i915_inject_load_failure(const char *func, int line); |
112 | #define i915_inject_load_failure() \ | |
113 | __i915_inject_load_failure(__func__, __LINE__) | |
114 | ||
42a8ca4c JN |
115 | static inline const char *yesno(bool v) |
116 | { | |
117 | return v ? "yes" : "no"; | |
118 | } | |
119 | ||
87ad3212 JN |
120 | static inline const char *onoff(bool v) |
121 | { | |
122 | return v ? "on" : "off"; | |
123 | } | |
124 | ||
317c35d1 | 125 | enum pipe { |
752aa88a | 126 | INVALID_PIPE = -1, |
317c35d1 JB |
127 | PIPE_A = 0, |
128 | PIPE_B, | |
9db4a9c7 | 129 | PIPE_C, |
a57c774a AK |
130 | _PIPE_EDP, |
131 | I915_MAX_PIPES = _PIPE_EDP | |
317c35d1 | 132 | }; |
9db4a9c7 | 133 | #define pipe_name(p) ((p) + 'A') |
317c35d1 | 134 | |
a5c961d1 PZ |
135 | enum transcoder { |
136 | TRANSCODER_A = 0, | |
137 | TRANSCODER_B, | |
138 | TRANSCODER_C, | |
a57c774a | 139 | TRANSCODER_EDP, |
4d1de975 JN |
140 | TRANSCODER_DSI_A, |
141 | TRANSCODER_DSI_C, | |
a57c774a | 142 | I915_MAX_TRANSCODERS |
a5c961d1 | 143 | }; |
da205630 JN |
144 | |
145 | static inline const char *transcoder_name(enum transcoder transcoder) | |
146 | { | |
147 | switch (transcoder) { | |
148 | case TRANSCODER_A: | |
149 | return "A"; | |
150 | case TRANSCODER_B: | |
151 | return "B"; | |
152 | case TRANSCODER_C: | |
153 | return "C"; | |
154 | case TRANSCODER_EDP: | |
155 | return "EDP"; | |
4d1de975 JN |
156 | case TRANSCODER_DSI_A: |
157 | return "DSI A"; | |
158 | case TRANSCODER_DSI_C: | |
159 | return "DSI C"; | |
da205630 JN |
160 | default: |
161 | return "<invalid>"; | |
162 | } | |
163 | } | |
a5c961d1 | 164 | |
4d1de975 JN |
165 | static inline bool transcoder_is_dsi(enum transcoder transcoder) |
166 | { | |
167 | return transcoder == TRANSCODER_DSI_A || transcoder == TRANSCODER_DSI_C; | |
168 | } | |
169 | ||
84139d1e | 170 | /* |
31409e97 MR |
171 | * I915_MAX_PLANES in the enum below is the maximum (across all platforms) |
172 | * number of planes per CRTC. Not all platforms really have this many planes, | |
173 | * which means some arrays of size I915_MAX_PLANES may have unused entries | |
174 | * between the topmost sprite plane and the cursor plane. | |
84139d1e | 175 | */ |
80824003 JB |
176 | enum plane { |
177 | PLANE_A = 0, | |
178 | PLANE_B, | |
9db4a9c7 | 179 | PLANE_C, |
31409e97 MR |
180 | PLANE_CURSOR, |
181 | I915_MAX_PLANES, | |
80824003 | 182 | }; |
9db4a9c7 | 183 | #define plane_name(p) ((p) + 'A') |
52440211 | 184 | |
d615a166 | 185 | #define sprite_name(p, s) ((p) * INTEL_INFO(dev)->num_sprites[(p)] + (s) + 'A') |
06da8da2 | 186 | |
2b139522 ED |
187 | enum port { |
188 | PORT_A = 0, | |
189 | PORT_B, | |
190 | PORT_C, | |
191 | PORT_D, | |
192 | PORT_E, | |
193 | I915_MAX_PORTS | |
194 | }; | |
195 | #define port_name(p) ((p) + 'A') | |
196 | ||
a09caddd | 197 | #define I915_NUM_PHYS_VLV 2 |
e4607fcf CML |
198 | |
199 | enum dpio_channel { | |
200 | DPIO_CH0, | |
201 | DPIO_CH1 | |
202 | }; | |
203 | ||
204 | enum dpio_phy { | |
205 | DPIO_PHY0, | |
206 | DPIO_PHY1 | |
207 | }; | |
208 | ||
b97186f0 PZ |
209 | enum intel_display_power_domain { |
210 | POWER_DOMAIN_PIPE_A, | |
211 | POWER_DOMAIN_PIPE_B, | |
212 | POWER_DOMAIN_PIPE_C, | |
213 | POWER_DOMAIN_PIPE_A_PANEL_FITTER, | |
214 | POWER_DOMAIN_PIPE_B_PANEL_FITTER, | |
215 | POWER_DOMAIN_PIPE_C_PANEL_FITTER, | |
216 | POWER_DOMAIN_TRANSCODER_A, | |
217 | POWER_DOMAIN_TRANSCODER_B, | |
218 | POWER_DOMAIN_TRANSCODER_C, | |
f52e353e | 219 | POWER_DOMAIN_TRANSCODER_EDP, |
4d1de975 JN |
220 | POWER_DOMAIN_TRANSCODER_DSI_A, |
221 | POWER_DOMAIN_TRANSCODER_DSI_C, | |
6331a704 PJ |
222 | POWER_DOMAIN_PORT_DDI_A_LANES, |
223 | POWER_DOMAIN_PORT_DDI_B_LANES, | |
224 | POWER_DOMAIN_PORT_DDI_C_LANES, | |
225 | POWER_DOMAIN_PORT_DDI_D_LANES, | |
226 | POWER_DOMAIN_PORT_DDI_E_LANES, | |
319be8ae ID |
227 | POWER_DOMAIN_PORT_DSI, |
228 | POWER_DOMAIN_PORT_CRT, | |
229 | POWER_DOMAIN_PORT_OTHER, | |
cdf8dd7f | 230 | POWER_DOMAIN_VGA, |
fbeeaa23 | 231 | POWER_DOMAIN_AUDIO, |
bd2bb1b9 | 232 | POWER_DOMAIN_PLLS, |
1407121a S |
233 | POWER_DOMAIN_AUX_A, |
234 | POWER_DOMAIN_AUX_B, | |
235 | POWER_DOMAIN_AUX_C, | |
236 | POWER_DOMAIN_AUX_D, | |
f0ab43e6 | 237 | POWER_DOMAIN_GMBUS, |
dfa57627 | 238 | POWER_DOMAIN_MODESET, |
baa70707 | 239 | POWER_DOMAIN_INIT, |
bddc7645 ID |
240 | |
241 | POWER_DOMAIN_NUM, | |
b97186f0 PZ |
242 | }; |
243 | ||
244 | #define POWER_DOMAIN_PIPE(pipe) ((pipe) + POWER_DOMAIN_PIPE_A) | |
245 | #define POWER_DOMAIN_PIPE_PANEL_FITTER(pipe) \ | |
246 | ((pipe) + POWER_DOMAIN_PIPE_A_PANEL_FITTER) | |
f52e353e ID |
247 | #define POWER_DOMAIN_TRANSCODER(tran) \ |
248 | ((tran) == TRANSCODER_EDP ? POWER_DOMAIN_TRANSCODER_EDP : \ | |
249 | (tran) + POWER_DOMAIN_TRANSCODER_A) | |
b97186f0 | 250 | |
1d843f9d EE |
251 | enum hpd_pin { |
252 | HPD_NONE = 0, | |
1d843f9d EE |
253 | HPD_TV = HPD_NONE, /* TV is known to be unreliable */ |
254 | HPD_CRT, | |
255 | HPD_SDVO_B, | |
256 | HPD_SDVO_C, | |
cc24fcdc | 257 | HPD_PORT_A, |
1d843f9d EE |
258 | HPD_PORT_B, |
259 | HPD_PORT_C, | |
260 | HPD_PORT_D, | |
26951caf | 261 | HPD_PORT_E, |
1d843f9d EE |
262 | HPD_NUM_PINS |
263 | }; | |
264 | ||
c91711f9 JN |
265 | #define for_each_hpd_pin(__pin) \ |
266 | for ((__pin) = (HPD_NONE + 1); (__pin) < HPD_NUM_PINS; (__pin)++) | |
267 | ||
5fcece80 JN |
268 | struct i915_hotplug { |
269 | struct work_struct hotplug_work; | |
270 | ||
271 | struct { | |
272 | unsigned long last_jiffies; | |
273 | int count; | |
274 | enum { | |
275 | HPD_ENABLED = 0, | |
276 | HPD_DISABLED = 1, | |
277 | HPD_MARK_DISABLED = 2 | |
278 | } state; | |
279 | } stats[HPD_NUM_PINS]; | |
280 | u32 event_bits; | |
281 | struct delayed_work reenable_work; | |
282 | ||
283 | struct intel_digital_port *irq_port[I915_MAX_PORTS]; | |
284 | u32 long_port_mask; | |
285 | u32 short_port_mask; | |
286 | struct work_struct dig_port_work; | |
287 | ||
19625e85 L |
288 | struct work_struct poll_init_work; |
289 | bool poll_enabled; | |
290 | ||
5fcece80 JN |
291 | /* |
292 | * if we get a HPD irq from DP and a HPD irq from non-DP | |
293 | * the non-DP HPD could block the workqueue on a mode config | |
294 | * mutex getting, that userspace may have taken. However | |
295 | * userspace is waiting on the DP workqueue to run which is | |
296 | * blocked behind the non-DP one. | |
297 | */ | |
298 | struct workqueue_struct *dp_wq; | |
299 | }; | |
300 | ||
2a2d5482 CW |
301 | #define I915_GEM_GPU_DOMAINS \ |
302 | (I915_GEM_DOMAIN_RENDER | \ | |
303 | I915_GEM_DOMAIN_SAMPLER | \ | |
304 | I915_GEM_DOMAIN_COMMAND | \ | |
305 | I915_GEM_DOMAIN_INSTRUCTION | \ | |
306 | I915_GEM_DOMAIN_VERTEX) | |
62fdfeaf | 307 | |
055e393f DL |
308 | #define for_each_pipe(__dev_priv, __p) \ |
309 | for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes; (__p)++) | |
6831f3e3 VS |
310 | #define for_each_pipe_masked(__dev_priv, __p, __mask) \ |
311 | for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes; (__p)++) \ | |
312 | for_each_if ((__mask) & (1 << (__p))) | |
dd740780 DL |
313 | #define for_each_plane(__dev_priv, __pipe, __p) \ |
314 | for ((__p) = 0; \ | |
315 | (__p) < INTEL_INFO(__dev_priv)->num_sprites[(__pipe)] + 1; \ | |
316 | (__p)++) | |
3bdcfc0c DL |
317 | #define for_each_sprite(__dev_priv, __p, __s) \ |
318 | for ((__s) = 0; \ | |
319 | (__s) < INTEL_INFO(__dev_priv)->num_sprites[(__p)]; \ | |
320 | (__s)++) | |
9db4a9c7 | 321 | |
c3aeadc8 JN |
322 | #define for_each_port_masked(__port, __ports_mask) \ |
323 | for ((__port) = PORT_A; (__port) < I915_MAX_PORTS; (__port)++) \ | |
324 | for_each_if ((__ports_mask) & (1 << (__port))) | |
325 | ||
d79b814d | 326 | #define for_each_crtc(dev, crtc) \ |
91c8a326 | 327 | list_for_each_entry(crtc, &(dev)->mode_config.crtc_list, head) |
d79b814d | 328 | |
27321ae8 ML |
329 | #define for_each_intel_plane(dev, intel_plane) \ |
330 | list_for_each_entry(intel_plane, \ | |
91c8a326 | 331 | &(dev)->mode_config.plane_list, \ |
27321ae8 ML |
332 | base.head) |
333 | ||
c107acfe | 334 | #define for_each_intel_plane_mask(dev, intel_plane, plane_mask) \ |
91c8a326 CW |
335 | list_for_each_entry(intel_plane, \ |
336 | &(dev)->mode_config.plane_list, \ | |
c107acfe MR |
337 | base.head) \ |
338 | for_each_if ((plane_mask) & \ | |
339 | (1 << drm_plane_index(&intel_plane->base))) | |
340 | ||
262cd2e1 VS |
341 | #define for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) \ |
342 | list_for_each_entry(intel_plane, \ | |
343 | &(dev)->mode_config.plane_list, \ | |
344 | base.head) \ | |
95150bdf | 345 | for_each_if ((intel_plane)->pipe == (intel_crtc)->pipe) |
262cd2e1 | 346 | |
91c8a326 CW |
347 | #define for_each_intel_crtc(dev, intel_crtc) \ |
348 | list_for_each_entry(intel_crtc, \ | |
349 | &(dev)->mode_config.crtc_list, \ | |
350 | base.head) | |
d063ae48 | 351 | |
91c8a326 CW |
352 | #define for_each_intel_crtc_mask(dev, intel_crtc, crtc_mask) \ |
353 | list_for_each_entry(intel_crtc, \ | |
354 | &(dev)->mode_config.crtc_list, \ | |
355 | base.head) \ | |
98d39494 MR |
356 | for_each_if ((crtc_mask) & (1 << drm_crtc_index(&intel_crtc->base))) |
357 | ||
b2784e15 DL |
358 | #define for_each_intel_encoder(dev, intel_encoder) \ |
359 | list_for_each_entry(intel_encoder, \ | |
360 | &(dev)->mode_config.encoder_list, \ | |
361 | base.head) | |
362 | ||
3a3371ff ACO |
363 | #define for_each_intel_connector(dev, intel_connector) \ |
364 | list_for_each_entry(intel_connector, \ | |
91c8a326 | 365 | &(dev)->mode_config.connector_list, \ |
3a3371ff ACO |
366 | base.head) |
367 | ||
6c2b7c12 DV |
368 | #define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \ |
369 | list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \ | |
95150bdf | 370 | for_each_if ((intel_encoder)->base.crtc == (__crtc)) |
6c2b7c12 | 371 | |
53f5e3ca JB |
372 | #define for_each_connector_on_encoder(dev, __encoder, intel_connector) \ |
373 | list_for_each_entry((intel_connector), &(dev)->mode_config.connector_list, base.head) \ | |
95150bdf | 374 | for_each_if ((intel_connector)->base.encoder == (__encoder)) |
53f5e3ca | 375 | |
b04c5bd6 BF |
376 | #define for_each_power_domain(domain, mask) \ |
377 | for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \ | |
95150bdf | 378 | for_each_if ((1 << (domain)) & (mask)) |
b04c5bd6 | 379 | |
e7b903d2 | 380 | struct drm_i915_private; |
ad46cb53 | 381 | struct i915_mm_struct; |
5cc9ed4b | 382 | struct i915_mmu_object; |
e7b903d2 | 383 | |
a6f766f3 CW |
384 | struct drm_i915_file_private { |
385 | struct drm_i915_private *dev_priv; | |
386 | struct drm_file *file; | |
387 | ||
388 | struct { | |
389 | spinlock_t lock; | |
390 | struct list_head request_list; | |
d0bc54f2 CW |
391 | /* 20ms is a fairly arbitrary limit (greater than the average frame time) |
392 | * chosen to prevent the CPU getting more than a frame ahead of the GPU | |
393 | * (when using lax throttling for the frontbuffer). We also use it to | |
394 | * offer free GPU waitboosts for severely congested workloads. | |
395 | */ | |
396 | #define DRM_I915_THROTTLE_JIFFIES msecs_to_jiffies(20) | |
a6f766f3 CW |
397 | } mm; |
398 | struct idr context_idr; | |
399 | ||
2e1b8730 CW |
400 | struct intel_rps_client { |
401 | struct list_head link; | |
402 | unsigned boosts; | |
403 | } rps; | |
a6f766f3 | 404 | |
c80ff16e | 405 | unsigned int bsd_engine; |
a6f766f3 CW |
406 | }; |
407 | ||
e69d0bc1 DV |
408 | /* Used by dp and fdi links */ |
409 | struct intel_link_m_n { | |
410 | uint32_t tu; | |
411 | uint32_t gmch_m; | |
412 | uint32_t gmch_n; | |
413 | uint32_t link_m; | |
414 | uint32_t link_n; | |
415 | }; | |
416 | ||
417 | void intel_link_compute_m_n(int bpp, int nlanes, | |
418 | int pixel_clock, int link_clock, | |
419 | struct intel_link_m_n *m_n); | |
420 | ||
1da177e4 LT |
421 | /* Interface history: |
422 | * | |
423 | * 1.1: Original. | |
0d6aa60b DA |
424 | * 1.2: Add Power Management |
425 | * 1.3: Add vblank support | |
de227f5f | 426 | * 1.4: Fix cmdbuffer path, add heap destroy |
702880f2 | 427 | * 1.5: Add vblank pipe configuration |
2228ed67 MCA |
428 | * 1.6: - New ioctl for scheduling buffer swaps on vertical blank |
429 | * - Support vertical blank on secondary display pipe | |
1da177e4 LT |
430 | */ |
431 | #define DRIVER_MAJOR 1 | |
2228ed67 | 432 | #define DRIVER_MINOR 6 |
1da177e4 LT |
433 | #define DRIVER_PATCHLEVEL 0 |
434 | ||
0a3e67a4 JB |
435 | struct opregion_header; |
436 | struct opregion_acpi; | |
437 | struct opregion_swsci; | |
438 | struct opregion_asle; | |
439 | ||
8ee1c3db | 440 | struct intel_opregion { |
115719fc WD |
441 | struct opregion_header *header; |
442 | struct opregion_acpi *acpi; | |
443 | struct opregion_swsci *swsci; | |
ebde53c7 JN |
444 | u32 swsci_gbda_sub_functions; |
445 | u32 swsci_sbcb_sub_functions; | |
115719fc | 446 | struct opregion_asle *asle; |
04ebaadb | 447 | void *rvda; |
82730385 | 448 | const void *vbt; |
ada8f955 | 449 | u32 vbt_size; |
115719fc | 450 | u32 *lid_state; |
91a60f20 | 451 | struct work_struct asle_work; |
8ee1c3db | 452 | }; |
44834a67 | 453 | #define OPREGION_SIZE (8*1024) |
8ee1c3db | 454 | |
6ef3d427 CW |
455 | struct intel_overlay; |
456 | struct intel_overlay_error_state; | |
457 | ||
de151cf6 | 458 | struct drm_i915_fence_reg { |
a1e5afbe | 459 | struct list_head link; |
49ef5294 CW |
460 | struct drm_i915_private *i915; |
461 | struct i915_vma *vma; | |
1690e1eb | 462 | int pin_count; |
49ef5294 CW |
463 | int id; |
464 | /** | |
465 | * Whether the tiling parameters for the currently | |
466 | * associated fence register have changed. Note that | |
467 | * for the purposes of tracking tiling changes we also | |
468 | * treat the unfenced register, the register slot that | |
469 | * the object occupies whilst it executes a fenced | |
470 | * command (such as BLT on gen2/3), as a "fence". | |
471 | */ | |
472 | bool dirty; | |
de151cf6 | 473 | }; |
7c1c2871 | 474 | |
9b9d172d | 475 | struct sdvo_device_mapping { |
e957d772 | 476 | u8 initialized; |
9b9d172d | 477 | u8 dvo_port; |
478 | u8 slave_addr; | |
479 | u8 dvo_wiring; | |
e957d772 | 480 | u8 i2c_pin; |
b1083333 | 481 | u8 ddc_pin; |
9b9d172d | 482 | }; |
483 | ||
7bd688cd | 484 | struct intel_connector; |
820d2d77 | 485 | struct intel_encoder; |
5cec258b | 486 | struct intel_crtc_state; |
5724dbd1 | 487 | struct intel_initial_plane_config; |
0e8ffe1b | 488 | struct intel_crtc; |
ee9300bb DV |
489 | struct intel_limit; |
490 | struct dpll; | |
b8cecdf5 | 491 | |
e70236a8 | 492 | struct drm_i915_display_funcs { |
e70236a8 JB |
493 | int (*get_display_clock_speed)(struct drm_device *dev); |
494 | int (*get_fifo_size)(struct drm_device *dev, int plane); | |
e3bddded | 495 | int (*compute_pipe_wm)(struct intel_crtc_state *cstate); |
ed4a6a7c MR |
496 | int (*compute_intermediate_wm)(struct drm_device *dev, |
497 | struct intel_crtc *intel_crtc, | |
498 | struct intel_crtc_state *newstate); | |
499 | void (*initial_watermarks)(struct intel_crtc_state *cstate); | |
500 | void (*optimize_watermarks)(struct intel_crtc_state *cstate); | |
98d39494 | 501 | int (*compute_global_watermarks)(struct drm_atomic_state *state); |
46ba614c | 502 | void (*update_wm)(struct drm_crtc *crtc); |
27c329ed ML |
503 | int (*modeset_calc_cdclk)(struct drm_atomic_state *state); |
504 | void (*modeset_commit_cdclk)(struct drm_atomic_state *state); | |
0e8ffe1b DV |
505 | /* Returns the active state of the crtc, and if the crtc is active, |
506 | * fills out the pipe-config with the hw state. */ | |
507 | bool (*get_pipe_config)(struct intel_crtc *, | |
5cec258b | 508 | struct intel_crtc_state *); |
5724dbd1 DL |
509 | void (*get_initial_plane_config)(struct intel_crtc *, |
510 | struct intel_initial_plane_config *); | |
190f68c5 ACO |
511 | int (*crtc_compute_clock)(struct intel_crtc *crtc, |
512 | struct intel_crtc_state *crtc_state); | |
4a806558 ML |
513 | void (*crtc_enable)(struct intel_crtc_state *pipe_config, |
514 | struct drm_atomic_state *old_state); | |
515 | void (*crtc_disable)(struct intel_crtc_state *old_crtc_state, | |
516 | struct drm_atomic_state *old_state); | |
896e5bb0 L |
517 | void (*update_crtcs)(struct drm_atomic_state *state, |
518 | unsigned int *crtc_vblank_mask); | |
69bfe1a9 JN |
519 | void (*audio_codec_enable)(struct drm_connector *connector, |
520 | struct intel_encoder *encoder, | |
5e7234c9 | 521 | const struct drm_display_mode *adjusted_mode); |
69bfe1a9 | 522 | void (*audio_codec_disable)(struct intel_encoder *encoder); |
674cf967 | 523 | void (*fdi_link_train)(struct drm_crtc *crtc); |
6067aaea | 524 | void (*init_clock_gating)(struct drm_device *dev); |
5a21b665 DV |
525 | int (*queue_flip)(struct drm_device *dev, struct drm_crtc *crtc, |
526 | struct drm_framebuffer *fb, | |
527 | struct drm_i915_gem_object *obj, | |
528 | struct drm_i915_gem_request *req, | |
529 | uint32_t flags); | |
91d14251 | 530 | void (*hpd_irq_setup)(struct drm_i915_private *dev_priv); |
e70236a8 JB |
531 | /* clock updates for mode set */ |
532 | /* cursor updates */ | |
533 | /* render clock increase/decrease */ | |
534 | /* display clock increase/decrease */ | |
535 | /* pll clock increase/decrease */ | |
8563b1e8 | 536 | |
b95c5321 ML |
537 | void (*load_csc_matrix)(struct drm_crtc_state *crtc_state); |
538 | void (*load_luts)(struct drm_crtc_state *crtc_state); | |
e70236a8 JB |
539 | }; |
540 | ||
48c1026a MK |
541 | enum forcewake_domain_id { |
542 | FW_DOMAIN_ID_RENDER = 0, | |
543 | FW_DOMAIN_ID_BLITTER, | |
544 | FW_DOMAIN_ID_MEDIA, | |
545 | ||
546 | FW_DOMAIN_ID_COUNT | |
547 | }; | |
548 | ||
549 | enum forcewake_domains { | |
550 | FORCEWAKE_RENDER = (1 << FW_DOMAIN_ID_RENDER), | |
551 | FORCEWAKE_BLITTER = (1 << FW_DOMAIN_ID_BLITTER), | |
552 | FORCEWAKE_MEDIA = (1 << FW_DOMAIN_ID_MEDIA), | |
553 | FORCEWAKE_ALL = (FORCEWAKE_RENDER | | |
554 | FORCEWAKE_BLITTER | | |
555 | FORCEWAKE_MEDIA) | |
556 | }; | |
557 | ||
3756685a TU |
558 | #define FW_REG_READ (1) |
559 | #define FW_REG_WRITE (2) | |
560 | ||
561 | enum forcewake_domains | |
562 | intel_uncore_forcewake_for_reg(struct drm_i915_private *dev_priv, | |
563 | i915_reg_t reg, unsigned int op); | |
564 | ||
907b28c5 | 565 | struct intel_uncore_funcs { |
c8d9a590 | 566 | void (*force_wake_get)(struct drm_i915_private *dev_priv, |
48c1026a | 567 | enum forcewake_domains domains); |
c8d9a590 | 568 | void (*force_wake_put)(struct drm_i915_private *dev_priv, |
48c1026a | 569 | enum forcewake_domains domains); |
0b274481 | 570 | |
f0f59a00 VS |
571 | uint8_t (*mmio_readb)(struct drm_i915_private *dev_priv, i915_reg_t r, bool trace); |
572 | uint16_t (*mmio_readw)(struct drm_i915_private *dev_priv, i915_reg_t r, bool trace); | |
573 | uint32_t (*mmio_readl)(struct drm_i915_private *dev_priv, i915_reg_t r, bool trace); | |
574 | uint64_t (*mmio_readq)(struct drm_i915_private *dev_priv, i915_reg_t r, bool trace); | |
0b274481 | 575 | |
f0f59a00 | 576 | void (*mmio_writeb)(struct drm_i915_private *dev_priv, i915_reg_t r, |
0b274481 | 577 | uint8_t val, bool trace); |
f0f59a00 | 578 | void (*mmio_writew)(struct drm_i915_private *dev_priv, i915_reg_t r, |
0b274481 | 579 | uint16_t val, bool trace); |
f0f59a00 | 580 | void (*mmio_writel)(struct drm_i915_private *dev_priv, i915_reg_t r, |
0b274481 | 581 | uint32_t val, bool trace); |
990bbdad CW |
582 | }; |
583 | ||
907b28c5 CW |
584 | struct intel_uncore { |
585 | spinlock_t lock; /** lock is also taken in irq contexts. */ | |
586 | ||
587 | struct intel_uncore_funcs funcs; | |
588 | ||
589 | unsigned fifo_count; | |
48c1026a | 590 | enum forcewake_domains fw_domains; |
b2cff0db CW |
591 | |
592 | struct intel_uncore_forcewake_domain { | |
593 | struct drm_i915_private *i915; | |
48c1026a | 594 | enum forcewake_domain_id id; |
33c582c1 | 595 | enum forcewake_domains mask; |
b2cff0db | 596 | unsigned wake_count; |
a57a4a67 | 597 | struct hrtimer timer; |
f0f59a00 | 598 | i915_reg_t reg_set; |
05a2fb15 MK |
599 | u32 val_set; |
600 | u32 val_clear; | |
f0f59a00 VS |
601 | i915_reg_t reg_ack; |
602 | i915_reg_t reg_post; | |
05a2fb15 | 603 | u32 val_reset; |
b2cff0db | 604 | } fw_domain[FW_DOMAIN_ID_COUNT]; |
75714940 MK |
605 | |
606 | int unclaimed_mmio_check; | |
b2cff0db CW |
607 | }; |
608 | ||
609 | /* Iterate over initialised fw domains */ | |
33c582c1 TU |
610 | #define for_each_fw_domain_masked(domain__, mask__, dev_priv__) \ |
611 | for ((domain__) = &(dev_priv__)->uncore.fw_domain[0]; \ | |
612 | (domain__) < &(dev_priv__)->uncore.fw_domain[FW_DOMAIN_ID_COUNT]; \ | |
613 | (domain__)++) \ | |
614 | for_each_if ((mask__) & (domain__)->mask) | |
615 | ||
616 | #define for_each_fw_domain(domain__, dev_priv__) \ | |
617 | for_each_fw_domain_masked(domain__, FORCEWAKE_ALL, dev_priv__) | |
907b28c5 | 618 | |
b6e7d894 DL |
619 | #define CSR_VERSION(major, minor) ((major) << 16 | (minor)) |
620 | #define CSR_VERSION_MAJOR(version) ((version) >> 16) | |
621 | #define CSR_VERSION_MINOR(version) ((version) & 0xffff) | |
622 | ||
eb805623 | 623 | struct intel_csr { |
8144ac59 | 624 | struct work_struct work; |
eb805623 | 625 | const char *fw_path; |
a7f749f9 | 626 | uint32_t *dmc_payload; |
eb805623 | 627 | uint32_t dmc_fw_size; |
b6e7d894 | 628 | uint32_t version; |
eb805623 | 629 | uint32_t mmio_count; |
f0f59a00 | 630 | i915_reg_t mmioaddr[8]; |
eb805623 | 631 | uint32_t mmiodata[8]; |
832dba88 | 632 | uint32_t dc_state; |
a37baf3b | 633 | uint32_t allowed_dc_mask; |
eb805623 DV |
634 | }; |
635 | ||
79fc46df DL |
636 | #define DEV_INFO_FOR_EACH_FLAG(func, sep) \ |
637 | func(is_mobile) sep \ | |
638 | func(is_i85x) sep \ | |
639 | func(is_i915g) sep \ | |
640 | func(is_i945gm) sep \ | |
641 | func(is_g33) sep \ | |
642 | func(need_gfx_hws) sep \ | |
643 | func(is_g4x) sep \ | |
644 | func(is_pineview) sep \ | |
645 | func(is_broadwater) sep \ | |
646 | func(is_crestline) sep \ | |
647 | func(is_ivybridge) sep \ | |
648 | func(is_valleyview) sep \ | |
666a4537 | 649 | func(is_cherryview) sep \ |
79fc46df | 650 | func(is_haswell) sep \ |
ab0d24ac | 651 | func(is_broadwell) sep \ |
7201c0b3 | 652 | func(is_skylake) sep \ |
7526ac19 | 653 | func(is_broxton) sep \ |
ef11bdb3 | 654 | func(is_kabylake) sep \ |
b833d685 | 655 | func(is_preliminary) sep \ |
79fc46df | 656 | func(has_fbc) sep \ |
6e3b84d8 | 657 | func(has_psr) sep \ |
4aa4c23f | 658 | func(has_runtime_pm) sep \ |
3bacde19 | 659 | func(has_csr) sep \ |
79fc46df DL |
660 | func(has_pipe_cxsr) sep \ |
661 | func(has_hotplug) sep \ | |
662 | func(cursor_needs_physical) sep \ | |
663 | func(has_overlay) sep \ | |
664 | func(overlay_needs_physical) sep \ | |
665 | func(supports_tv) sep \ | |
dd93be58 | 666 | func(has_llc) sep \ |
ca377809 | 667 | func(has_snoop) sep \ |
30568c45 | 668 | func(has_ddi) sep \ |
33e141ed | 669 | func(has_fpga_dbg) sep \ |
670 | func(has_pooled_eu) | |
c96ea64e | 671 | |
a587f779 DL |
672 | #define DEFINE_FLAG(name) u8 name:1 |
673 | #define SEP_SEMICOLON ; | |
c96ea64e | 674 | |
915490d5 | 675 | struct sseu_dev_info { |
f08a0c92 | 676 | u8 slice_mask; |
57ec171e | 677 | u8 subslice_mask; |
915490d5 ID |
678 | u8 eu_total; |
679 | u8 eu_per_subslice; | |
43b67998 ID |
680 | u8 min_eu_in_pool; |
681 | /* For each slice, which subslice(s) has(have) 7 EUs (bitfield)? */ | |
682 | u8 subslice_7eu[3]; | |
683 | u8 has_slice_pg:1; | |
684 | u8 has_subslice_pg:1; | |
685 | u8 has_eu_pg:1; | |
915490d5 ID |
686 | }; |
687 | ||
57ec171e ID |
688 | static inline unsigned int sseu_subslice_total(const struct sseu_dev_info *sseu) |
689 | { | |
690 | return hweight8(sseu->slice_mask) * hweight8(sseu->subslice_mask); | |
691 | } | |
692 | ||
cfdf1fa2 | 693 | struct intel_device_info { |
10fce67a | 694 | u32 display_mmio_offset; |
87f1f465 | 695 | u16 device_id; |
ac208a8b | 696 | u8 num_pipes; |
d615a166 | 697 | u8 num_sprites[I915_MAX_PIPES]; |
c96c3a8c | 698 | u8 gen; |
ae5702d2 | 699 | u16 gen_mask; |
73ae478c | 700 | u8 ring_mask; /* Rings supported by the HW */ |
c1bb1145 | 701 | u8 num_rings; |
a587f779 | 702 | DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG, SEP_SEMICOLON); |
a57c774a AK |
703 | /* Register offsets for the various display pipes and transcoders */ |
704 | int pipe_offsets[I915_MAX_TRANSCODERS]; | |
705 | int trans_offsets[I915_MAX_TRANSCODERS]; | |
a57c774a | 706 | int palette_offsets[I915_MAX_PIPES]; |
5efb3e28 | 707 | int cursor_offsets[I915_MAX_PIPES]; |
3873218f JM |
708 | |
709 | /* Slice/subslice/EU info */ | |
43b67998 | 710 | struct sseu_dev_info sseu; |
82cf435b LL |
711 | |
712 | struct color_luts { | |
713 | u16 degamma_lut_size; | |
714 | u16 gamma_lut_size; | |
715 | } color; | |
cfdf1fa2 KH |
716 | }; |
717 | ||
a587f779 DL |
718 | #undef DEFINE_FLAG |
719 | #undef SEP_SEMICOLON | |
720 | ||
2bd160a1 CW |
721 | struct intel_display_error_state; |
722 | ||
723 | struct drm_i915_error_state { | |
724 | struct kref ref; | |
725 | struct timeval time; | |
726 | ||
727 | char error_msg[128]; | |
728 | bool simulated; | |
729 | int iommu; | |
730 | u32 reset_count; | |
731 | u32 suspend_count; | |
732 | struct intel_device_info device_info; | |
733 | ||
734 | /* Generic register state */ | |
735 | u32 eir; | |
736 | u32 pgtbl_er; | |
737 | u32 ier; | |
738 | u32 gtier[4]; | |
739 | u32 ccid; | |
740 | u32 derrmr; | |
741 | u32 forcewake; | |
742 | u32 error; /* gen6+ */ | |
743 | u32 err_int; /* gen7 */ | |
744 | u32 fault_data0; /* gen8, gen9 */ | |
745 | u32 fault_data1; /* gen8, gen9 */ | |
746 | u32 done_reg; | |
747 | u32 gac_eco; | |
748 | u32 gam_ecochk; | |
749 | u32 gab_ctl; | |
750 | u32 gfx_mode; | |
751 | u32 extra_instdone[I915_NUM_INSTDONE_REG]; | |
752 | u64 fence[I915_MAX_NUM_FENCES]; | |
753 | struct intel_overlay_error_state *overlay; | |
754 | struct intel_display_error_state *display; | |
51d545d0 | 755 | struct drm_i915_error_object *semaphore; |
2bd160a1 CW |
756 | |
757 | struct drm_i915_error_engine { | |
758 | int engine_id; | |
759 | /* Software tracked state */ | |
760 | bool waiting; | |
761 | int num_waiters; | |
762 | int hangcheck_score; | |
763 | enum intel_engine_hangcheck_action hangcheck_action; | |
764 | struct i915_address_space *vm; | |
765 | int num_requests; | |
766 | ||
767 | /* our own tracking of ring head and tail */ | |
768 | u32 cpu_ring_head; | |
769 | u32 cpu_ring_tail; | |
770 | ||
771 | u32 last_seqno; | |
772 | u32 semaphore_seqno[I915_NUM_ENGINES - 1]; | |
773 | ||
774 | /* Register state */ | |
775 | u32 start; | |
776 | u32 tail; | |
777 | u32 head; | |
778 | u32 ctl; | |
21a2c58a | 779 | u32 mode; |
2bd160a1 CW |
780 | u32 hws; |
781 | u32 ipeir; | |
782 | u32 ipehr; | |
783 | u32 instdone; | |
784 | u32 bbstate; | |
785 | u32 instpm; | |
786 | u32 instps; | |
787 | u32 seqno; | |
788 | u64 bbaddr; | |
789 | u64 acthd; | |
790 | u32 fault_reg; | |
791 | u64 faddr; | |
792 | u32 rc_psmi; /* sleep state */ | |
793 | u32 semaphore_mboxes[I915_NUM_ENGINES - 1]; | |
794 | ||
795 | struct drm_i915_error_object { | |
796 | int page_count; | |
797 | u64 gtt_offset; | |
03382dfb | 798 | u64 gtt_size; |
2bd160a1 CW |
799 | u32 *pages[0]; |
800 | } *ringbuffer, *batchbuffer, *wa_batchbuffer, *ctx, *hws_page; | |
801 | ||
802 | struct drm_i915_error_object *wa_ctx; | |
803 | ||
804 | struct drm_i915_error_request { | |
805 | long jiffies; | |
c84455b4 | 806 | pid_t pid; |
2bd160a1 CW |
807 | u32 seqno; |
808 | u32 head; | |
809 | u32 tail; | |
810 | } *requests; | |
811 | ||
812 | struct drm_i915_error_waiter { | |
813 | char comm[TASK_COMM_LEN]; | |
814 | pid_t pid; | |
815 | u32 seqno; | |
816 | } *waiters; | |
817 | ||
818 | struct { | |
819 | u32 gfx_mode; | |
820 | union { | |
821 | u64 pdp[4]; | |
822 | u32 pp_dir_base; | |
823 | }; | |
824 | } vm_info; | |
825 | ||
826 | pid_t pid; | |
827 | char comm[TASK_COMM_LEN]; | |
828 | } engine[I915_NUM_ENGINES]; | |
829 | ||
830 | struct drm_i915_error_buffer { | |
831 | u32 size; | |
832 | u32 name; | |
833 | u32 rseqno[I915_NUM_ENGINES], wseqno; | |
834 | u64 gtt_offset; | |
835 | u32 read_domains; | |
836 | u32 write_domain; | |
837 | s32 fence_reg:I915_MAX_NUM_FENCE_BITS; | |
838 | u32 tiling:2; | |
839 | u32 dirty:1; | |
840 | u32 purgeable:1; | |
841 | u32 userptr:1; | |
842 | s32 engine:4; | |
843 | u32 cache_level:3; | |
844 | } *active_bo[I915_NUM_ENGINES], *pinned_bo; | |
845 | u32 active_bo_count[I915_NUM_ENGINES], pinned_bo_count; | |
846 | struct i915_address_space *active_vm[I915_NUM_ENGINES]; | |
847 | }; | |
848 | ||
7faf1ab2 DV |
849 | enum i915_cache_level { |
850 | I915_CACHE_NONE = 0, | |
350ec881 CW |
851 | I915_CACHE_LLC, /* also used for snoopable memory on non-LLC */ |
852 | I915_CACHE_L3_LLC, /* gen7+, L3 sits between the domain specifc | |
853 | caches, eg sampler/render caches, and the | |
854 | large Last-Level-Cache. LLC is coherent with | |
855 | the CPU, but L3 is only visible to the GPU. */ | |
651d794f | 856 | I915_CACHE_WT, /* hsw:gt3e WriteThrough for scanouts */ |
7faf1ab2 DV |
857 | }; |
858 | ||
e59ec13d MK |
859 | struct i915_ctx_hang_stats { |
860 | /* This context had batch pending when hang was declared */ | |
861 | unsigned batch_pending; | |
862 | ||
863 | /* This context had batch active when hang was declared */ | |
864 | unsigned batch_active; | |
be62acb4 MK |
865 | |
866 | /* Time when this context was last blamed for a GPU reset */ | |
867 | unsigned long guilty_ts; | |
868 | ||
676fa572 CW |
869 | /* If the contexts causes a second GPU hang within this time, |
870 | * it is permanently banned from submitting any more work. | |
871 | */ | |
872 | unsigned long ban_period_seconds; | |
873 | ||
be62acb4 MK |
874 | /* This context is banned to submit more work */ |
875 | bool banned; | |
e59ec13d | 876 | }; |
40521054 BW |
877 | |
878 | /* This must match up with the value previously used for execbuf2.rsvd1. */ | |
821d66dd | 879 | #define DEFAULT_CONTEXT_HANDLE 0 |
b1b38278 | 880 | |
31b7a88d | 881 | /** |
e2efd130 | 882 | * struct i915_gem_context - as the name implies, represents a context. |
31b7a88d OM |
883 | * @ref: reference count. |
884 | * @user_handle: userspace tracking identity for this context. | |
885 | * @remap_slice: l3 row remapping information. | |
b1b38278 DW |
886 | * @flags: context specific flags: |
887 | * CONTEXT_NO_ZEROMAP: do not allow mapping things to page 0. | |
31b7a88d OM |
888 | * @file_priv: filp associated with this context (NULL for global default |
889 | * context). | |
890 | * @hang_stats: information about the role of this context in possible GPU | |
891 | * hangs. | |
7df113e4 | 892 | * @ppgtt: virtual memory space used by this context. |
31b7a88d OM |
893 | * @legacy_hw_ctx: render context backing object and whether it is correctly |
894 | * initialized (legacy ring submission mechanism only). | |
895 | * @link: link in the global list of contexts. | |
896 | * | |
897 | * Contexts are memory images used by the hardware to store copies of their | |
898 | * internal state. | |
899 | */ | |
e2efd130 | 900 | struct i915_gem_context { |
dce3271b | 901 | struct kref ref; |
9ea4feec | 902 | struct drm_i915_private *i915; |
40521054 | 903 | struct drm_i915_file_private *file_priv; |
ae6c4806 | 904 | struct i915_hw_ppgtt *ppgtt; |
c84455b4 | 905 | struct pid *pid; |
a33afea5 | 906 | |
8d59bc6a CW |
907 | struct i915_ctx_hang_stats hang_stats; |
908 | ||
8d59bc6a | 909 | unsigned long flags; |
bc3d6744 CW |
910 | #define CONTEXT_NO_ZEROMAP BIT(0) |
911 | #define CONTEXT_NO_ERROR_CAPTURE BIT(1) | |
0be81156 DG |
912 | |
913 | /* Unique identifier for this context, used by the hw for tracking */ | |
914 | unsigned int hw_id; | |
8d59bc6a | 915 | u32 user_handle; |
5d1808ec | 916 | |
0cb26a8e CW |
917 | u32 ggtt_alignment; |
918 | ||
9021ad03 | 919 | struct intel_context { |
bf3783e5 | 920 | struct i915_vma *state; |
7e37f889 | 921 | struct intel_ring *ring; |
82352e90 | 922 | uint32_t *lrc_reg_state; |
8d59bc6a CW |
923 | u64 lrc_desc; |
924 | int pin_count; | |
24f1d3cc | 925 | bool initialised; |
666796da | 926 | } engine[I915_NUM_ENGINES]; |
bcd794c2 | 927 | u32 ring_size; |
c01fc532 | 928 | u32 desc_template; |
3c7ba635 | 929 | struct atomic_notifier_head status_notifier; |
80a9a8db | 930 | bool execlists_force_single_submission; |
c9e003af | 931 | |
a33afea5 | 932 | struct list_head link; |
8d59bc6a CW |
933 | |
934 | u8 remap_slice; | |
50e046b6 | 935 | bool closed:1; |
40521054 BW |
936 | }; |
937 | ||
a4001f1b PZ |
938 | enum fb_op_origin { |
939 | ORIGIN_GTT, | |
940 | ORIGIN_CPU, | |
941 | ORIGIN_CS, | |
942 | ORIGIN_FLIP, | |
74b4ea1e | 943 | ORIGIN_DIRTYFB, |
a4001f1b PZ |
944 | }; |
945 | ||
ab34a7e8 | 946 | struct intel_fbc { |
25ad93fd PZ |
947 | /* This is always the inner lock when overlapping with struct_mutex and |
948 | * it's the outer lock when overlapping with stolen_lock. */ | |
949 | struct mutex lock; | |
5e59f717 | 950 | unsigned threshold; |
dbef0f15 PZ |
951 | unsigned int possible_framebuffer_bits; |
952 | unsigned int busy_bits; | |
010cf73d | 953 | unsigned int visible_pipes_mask; |
e35fef21 | 954 | struct intel_crtc *crtc; |
5c3fe8b0 | 955 | |
c4213885 | 956 | struct drm_mm_node compressed_fb; |
5c3fe8b0 BW |
957 | struct drm_mm_node *compressed_llb; |
958 | ||
da46f936 RV |
959 | bool false_color; |
960 | ||
d029bcad | 961 | bool enabled; |
0e631adc | 962 | bool active; |
9adccc60 | 963 | |
aaf78d27 PZ |
964 | struct intel_fbc_state_cache { |
965 | struct { | |
966 | unsigned int mode_flags; | |
967 | uint32_t hsw_bdw_pixel_rate; | |
968 | } crtc; | |
969 | ||
970 | struct { | |
971 | unsigned int rotation; | |
972 | int src_w; | |
973 | int src_h; | |
974 | bool visible; | |
975 | } plane; | |
976 | ||
977 | struct { | |
978 | u64 ilk_ggtt_offset; | |
aaf78d27 PZ |
979 | uint32_t pixel_format; |
980 | unsigned int stride; | |
981 | int fence_reg; | |
982 | unsigned int tiling_mode; | |
983 | } fb; | |
984 | } state_cache; | |
985 | ||
b183b3f1 PZ |
986 | struct intel_fbc_reg_params { |
987 | struct { | |
988 | enum pipe pipe; | |
989 | enum plane plane; | |
990 | unsigned int fence_y_offset; | |
991 | } crtc; | |
992 | ||
993 | struct { | |
994 | u64 ggtt_offset; | |
b183b3f1 PZ |
995 | uint32_t pixel_format; |
996 | unsigned int stride; | |
997 | int fence_reg; | |
998 | } fb; | |
999 | ||
1000 | int cfb_size; | |
1001 | } params; | |
1002 | ||
5c3fe8b0 | 1003 | struct intel_fbc_work { |
128d7356 | 1004 | bool scheduled; |
ca18d51d | 1005 | u32 scheduled_vblank; |
128d7356 | 1006 | struct work_struct work; |
128d7356 | 1007 | } work; |
5c3fe8b0 | 1008 | |
bf6189c6 | 1009 | const char *no_fbc_reason; |
b5e50c3f JB |
1010 | }; |
1011 | ||
96178eeb VK |
1012 | /** |
1013 | * HIGH_RR is the highest eDP panel refresh rate read from EDID | |
1014 | * LOW_RR is the lowest eDP panel refresh rate found from EDID | |
1015 | * parsing for same resolution. | |
1016 | */ | |
1017 | enum drrs_refresh_rate_type { | |
1018 | DRRS_HIGH_RR, | |
1019 | DRRS_LOW_RR, | |
1020 | DRRS_MAX_RR, /* RR count */ | |
1021 | }; | |
1022 | ||
1023 | enum drrs_support_type { | |
1024 | DRRS_NOT_SUPPORTED = 0, | |
1025 | STATIC_DRRS_SUPPORT = 1, | |
1026 | SEAMLESS_DRRS_SUPPORT = 2 | |
439d7ac0 PB |
1027 | }; |
1028 | ||
2807cf69 | 1029 | struct intel_dp; |
96178eeb VK |
1030 | struct i915_drrs { |
1031 | struct mutex mutex; | |
1032 | struct delayed_work work; | |
1033 | struct intel_dp *dp; | |
1034 | unsigned busy_frontbuffer_bits; | |
1035 | enum drrs_refresh_rate_type refresh_rate_type; | |
1036 | enum drrs_support_type type; | |
1037 | }; | |
1038 | ||
a031d709 | 1039 | struct i915_psr { |
f0355c4a | 1040 | struct mutex lock; |
a031d709 RV |
1041 | bool sink_support; |
1042 | bool source_ok; | |
2807cf69 | 1043 | struct intel_dp *enabled; |
7c8f8a70 RV |
1044 | bool active; |
1045 | struct delayed_work work; | |
9ca15301 | 1046 | unsigned busy_frontbuffer_bits; |
474d1ec4 SJ |
1047 | bool psr2_support; |
1048 | bool aux_frame_sync; | |
60e5ffe3 | 1049 | bool link_standby; |
3f51e471 | 1050 | }; |
5c3fe8b0 | 1051 | |
3bad0781 | 1052 | enum intel_pch { |
f0350830 | 1053 | PCH_NONE = 0, /* No PCH present */ |
3bad0781 ZW |
1054 | PCH_IBX, /* Ibexpeak PCH */ |
1055 | PCH_CPT, /* Cougarpoint PCH */ | |
eb877ebf | 1056 | PCH_LPT, /* Lynxpoint PCH */ |
e7e7ea20 | 1057 | PCH_SPT, /* Sunrisepoint PCH */ |
22dea0be | 1058 | PCH_KBP, /* Kabypoint PCH */ |
40c7ead9 | 1059 | PCH_NOP, |
3bad0781 ZW |
1060 | }; |
1061 | ||
988d6ee8 PZ |
1062 | enum intel_sbi_destination { |
1063 | SBI_ICLK, | |
1064 | SBI_MPHY, | |
1065 | }; | |
1066 | ||
b690e96c | 1067 | #define QUIRK_PIPEA_FORCE (1<<0) |
435793df | 1068 | #define QUIRK_LVDS_SSC_DISABLE (1<<1) |
4dca20ef | 1069 | #define QUIRK_INVERT_BRIGHTNESS (1<<2) |
9c72cc6f | 1070 | #define QUIRK_BACKLIGHT_PRESENT (1<<3) |
b6b5d049 | 1071 | #define QUIRK_PIPEB_FORCE (1<<4) |
656bfa3a | 1072 | #define QUIRK_PIN_SWIZZLED_PAGES (1<<5) |
b690e96c | 1073 | |
8be48d92 | 1074 | struct intel_fbdev; |
1630fe75 | 1075 | struct intel_fbc_work; |
38651674 | 1076 | |
c2b9152f DV |
1077 | struct intel_gmbus { |
1078 | struct i2c_adapter adapter; | |
3e4d44e0 | 1079 | #define GMBUS_FORCE_BIT_RETRY (1U << 31) |
f2ce9faf | 1080 | u32 force_bit; |
c2b9152f | 1081 | u32 reg0; |
f0f59a00 | 1082 | i915_reg_t gpio_reg; |
c167a6fc | 1083 | struct i2c_algo_bit_data bit_algo; |
c2b9152f DV |
1084 | struct drm_i915_private *dev_priv; |
1085 | }; | |
1086 | ||
f4c956ad | 1087 | struct i915_suspend_saved_registers { |
e948e994 | 1088 | u32 saveDSPARB; |
ba8bbcf6 | 1089 | u32 saveFBC_CONTROL; |
1f84e550 | 1090 | u32 saveCACHE_MODE_0; |
1f84e550 | 1091 | u32 saveMI_ARB_STATE; |
ba8bbcf6 JB |
1092 | u32 saveSWF0[16]; |
1093 | u32 saveSWF1[16]; | |
85fa792b | 1094 | u32 saveSWF3[3]; |
4b9de737 | 1095 | uint64_t saveFENCE[I915_MAX_NUM_FENCES]; |
cda2bb78 | 1096 | u32 savePCH_PORT_HOTPLUG; |
9f49c376 | 1097 | u16 saveGCDGMBUS; |
f4c956ad | 1098 | }; |
c85aa885 | 1099 | |
ddeea5b0 ID |
1100 | struct vlv_s0ix_state { |
1101 | /* GAM */ | |
1102 | u32 wr_watermark; | |
1103 | u32 gfx_prio_ctrl; | |
1104 | u32 arb_mode; | |
1105 | u32 gfx_pend_tlb0; | |
1106 | u32 gfx_pend_tlb1; | |
1107 | u32 lra_limits[GEN7_LRA_LIMITS_REG_NUM]; | |
1108 | u32 media_max_req_count; | |
1109 | u32 gfx_max_req_count; | |
1110 | u32 render_hwsp; | |
1111 | u32 ecochk; | |
1112 | u32 bsd_hwsp; | |
1113 | u32 blt_hwsp; | |
1114 | u32 tlb_rd_addr; | |
1115 | ||
1116 | /* MBC */ | |
1117 | u32 g3dctl; | |
1118 | u32 gsckgctl; | |
1119 | u32 mbctl; | |
1120 | ||
1121 | /* GCP */ | |
1122 | u32 ucgctl1; | |
1123 | u32 ucgctl3; | |
1124 | u32 rcgctl1; | |
1125 | u32 rcgctl2; | |
1126 | u32 rstctl; | |
1127 | u32 misccpctl; | |
1128 | ||
1129 | /* GPM */ | |
1130 | u32 gfxpause; | |
1131 | u32 rpdeuhwtc; | |
1132 | u32 rpdeuc; | |
1133 | u32 ecobus; | |
1134 | u32 pwrdwnupctl; | |
1135 | u32 rp_down_timeout; | |
1136 | u32 rp_deucsw; | |
1137 | u32 rcubmabdtmr; | |
1138 | u32 rcedata; | |
1139 | u32 spare2gh; | |
1140 | ||
1141 | /* Display 1 CZ domain */ | |
1142 | u32 gt_imr; | |
1143 | u32 gt_ier; | |
1144 | u32 pm_imr; | |
1145 | u32 pm_ier; | |
1146 | u32 gt_scratch[GEN7_GT_SCRATCH_REG_NUM]; | |
1147 | ||
1148 | /* GT SA CZ domain */ | |
1149 | u32 tilectl; | |
1150 | u32 gt_fifoctl; | |
1151 | u32 gtlc_wake_ctrl; | |
1152 | u32 gtlc_survive; | |
1153 | u32 pmwgicz; | |
1154 | ||
1155 | /* Display 2 CZ domain */ | |
1156 | u32 gu_ctl0; | |
1157 | u32 gu_ctl1; | |
9c25210f | 1158 | u32 pcbr; |
ddeea5b0 ID |
1159 | u32 clock_gate_dis2; |
1160 | }; | |
1161 | ||
bf225f20 CW |
1162 | struct intel_rps_ei { |
1163 | u32 cz_clock; | |
1164 | u32 render_c0; | |
1165 | u32 media_c0; | |
31685c25 D |
1166 | }; |
1167 | ||
c85aa885 | 1168 | struct intel_gen6_power_mgmt { |
d4d70aa5 ID |
1169 | /* |
1170 | * work, interrupts_enabled and pm_iir are protected by | |
1171 | * dev_priv->irq_lock | |
1172 | */ | |
c85aa885 | 1173 | struct work_struct work; |
d4d70aa5 | 1174 | bool interrupts_enabled; |
c85aa885 | 1175 | u32 pm_iir; |
59cdb63d | 1176 | |
1800ad25 SAK |
1177 | u32 pm_intr_keep; |
1178 | ||
b39fb297 BW |
1179 | /* Frequencies are stored in potentially platform dependent multiples. |
1180 | * In other words, *_freq needs to be multiplied by X to be interesting. | |
1181 | * Soft limits are those which are used for the dynamic reclocking done | |
1182 | * by the driver (raise frequencies under heavy loads, and lower for | |
1183 | * lighter loads). Hard limits are those imposed by the hardware. | |
1184 | * | |
1185 | * A distinction is made for overclocking, which is never enabled by | |
1186 | * default, and is considered to be above the hard limit if it's | |
1187 | * possible at all. | |
1188 | */ | |
1189 | u8 cur_freq; /* Current frequency (cached, may not == HW) */ | |
1190 | u8 min_freq_softlimit; /* Minimum frequency permitted by the driver */ | |
1191 | u8 max_freq_softlimit; /* Max frequency permitted by the driver */ | |
1192 | u8 max_freq; /* Maximum frequency, RP0 if not overclocking */ | |
1193 | u8 min_freq; /* AKA RPn. Minimum frequency */ | |
29ecd78d | 1194 | u8 boost_freq; /* Frequency to request when wait boosting */ |
aed242ff | 1195 | u8 idle_freq; /* Frequency to request when we are idle */ |
b39fb297 BW |
1196 | u8 efficient_freq; /* AKA RPe. Pre-determined balanced frequency */ |
1197 | u8 rp1_freq; /* "less than" RP0 power/freqency */ | |
1198 | u8 rp0_freq; /* Non-overclocked max frequency. */ | |
c30fec65 | 1199 | u16 gpll_ref_freq; /* vlv/chv GPLL reference frequency */ |
1a01ab3b | 1200 | |
8fb55197 CW |
1201 | u8 up_threshold; /* Current %busy required to uplock */ |
1202 | u8 down_threshold; /* Current %busy required to downclock */ | |
1203 | ||
dd75fdc8 CW |
1204 | int last_adj; |
1205 | enum { LOW_POWER, BETWEEN, HIGH_POWER } power; | |
1206 | ||
8d3afd7d CW |
1207 | spinlock_t client_lock; |
1208 | struct list_head clients; | |
1209 | bool client_boost; | |
1210 | ||
c0951f0c | 1211 | bool enabled; |
54b4f68f | 1212 | struct delayed_work autoenable_work; |
1854d5ca | 1213 | unsigned boosts; |
4fc688ce | 1214 | |
bf225f20 CW |
1215 | /* manual wa residency calculations */ |
1216 | struct intel_rps_ei up_ei, down_ei; | |
1217 | ||
4fc688ce JB |
1218 | /* |
1219 | * Protects RPS/RC6 register access and PCU communication. | |
8d3afd7d CW |
1220 | * Must be taken after struct_mutex if nested. Note that |
1221 | * this lock may be held for long periods of time when | |
1222 | * talking to hw - so only take it when talking to hw! | |
4fc688ce JB |
1223 | */ |
1224 | struct mutex hw_lock; | |
c85aa885 DV |
1225 | }; |
1226 | ||
1a240d4d DV |
1227 | /* defined intel_pm.c */ |
1228 | extern spinlock_t mchdev_lock; | |
1229 | ||
c85aa885 DV |
1230 | struct intel_ilk_power_mgmt { |
1231 | u8 cur_delay; | |
1232 | u8 min_delay; | |
1233 | u8 max_delay; | |
1234 | u8 fmax; | |
1235 | u8 fstart; | |
1236 | ||
1237 | u64 last_count1; | |
1238 | unsigned long last_time1; | |
1239 | unsigned long chipset_power; | |
1240 | u64 last_count2; | |
5ed0bdf2 | 1241 | u64 last_time2; |
c85aa885 DV |
1242 | unsigned long gfx_power; |
1243 | u8 corr; | |
1244 | ||
1245 | int c_m; | |
1246 | int r_t; | |
1247 | }; | |
1248 | ||
c6cb582e ID |
1249 | struct drm_i915_private; |
1250 | struct i915_power_well; | |
1251 | ||
1252 | struct i915_power_well_ops { | |
1253 | /* | |
1254 | * Synchronize the well's hw state to match the current sw state, for | |
1255 | * example enable/disable it based on the current refcount. Called | |
1256 | * during driver init and resume time, possibly after first calling | |
1257 | * the enable/disable handlers. | |
1258 | */ | |
1259 | void (*sync_hw)(struct drm_i915_private *dev_priv, | |
1260 | struct i915_power_well *power_well); | |
1261 | /* | |
1262 | * Enable the well and resources that depend on it (for example | |
1263 | * interrupts located on the well). Called after the 0->1 refcount | |
1264 | * transition. | |
1265 | */ | |
1266 | void (*enable)(struct drm_i915_private *dev_priv, | |
1267 | struct i915_power_well *power_well); | |
1268 | /* | |
1269 | * Disable the well and resources that depend on it. Called after | |
1270 | * the 1->0 refcount transition. | |
1271 | */ | |
1272 | void (*disable)(struct drm_i915_private *dev_priv, | |
1273 | struct i915_power_well *power_well); | |
1274 | /* Returns the hw enabled state. */ | |
1275 | bool (*is_enabled)(struct drm_i915_private *dev_priv, | |
1276 | struct i915_power_well *power_well); | |
1277 | }; | |
1278 | ||
a38911a3 WX |
1279 | /* Power well structure for haswell */ |
1280 | struct i915_power_well { | |
c1ca727f | 1281 | const char *name; |
6f3ef5dd | 1282 | bool always_on; |
a38911a3 WX |
1283 | /* power well enable/disable usage count */ |
1284 | int count; | |
bfafe93a ID |
1285 | /* cached hw enabled state */ |
1286 | bool hw_enabled; | |
c1ca727f | 1287 | unsigned long domains; |
77961eb9 | 1288 | unsigned long data; |
c6cb582e | 1289 | const struct i915_power_well_ops *ops; |
a38911a3 WX |
1290 | }; |
1291 | ||
83c00f55 | 1292 | struct i915_power_domains { |
baa70707 ID |
1293 | /* |
1294 | * Power wells needed for initialization at driver init and suspend | |
1295 | * time are on. They are kept on until after the first modeset. | |
1296 | */ | |
1297 | bool init_power_on; | |
0d116a29 | 1298 | bool initializing; |
c1ca727f | 1299 | int power_well_count; |
baa70707 | 1300 | |
83c00f55 | 1301 | struct mutex lock; |
1da51581 | 1302 | int domain_use_count[POWER_DOMAIN_NUM]; |
c1ca727f | 1303 | struct i915_power_well *power_wells; |
83c00f55 ID |
1304 | }; |
1305 | ||
35a85ac6 | 1306 | #define MAX_L3_SLICES 2 |
a4da4fa4 | 1307 | struct intel_l3_parity { |
35a85ac6 | 1308 | u32 *remap_info[MAX_L3_SLICES]; |
a4da4fa4 | 1309 | struct work_struct error_work; |
35a85ac6 | 1310 | int which_slice; |
a4da4fa4 DV |
1311 | }; |
1312 | ||
4b5aed62 | 1313 | struct i915_gem_mm { |
4b5aed62 DV |
1314 | /** Memory allocator for GTT stolen memory */ |
1315 | struct drm_mm stolen; | |
92e97d2f PZ |
1316 | /** Protects the usage of the GTT stolen memory allocator. This is |
1317 | * always the inner lock when overlapping with struct_mutex. */ | |
1318 | struct mutex stolen_lock; | |
1319 | ||
4b5aed62 DV |
1320 | /** List of all objects in gtt_space. Used to restore gtt |
1321 | * mappings on resume */ | |
1322 | struct list_head bound_list; | |
1323 | /** | |
1324 | * List of objects which are not bound to the GTT (thus | |
1325 | * are idle and not used by the GPU) but still have | |
1326 | * (presumably uncached) pages still attached. | |
1327 | */ | |
1328 | struct list_head unbound_list; | |
1329 | ||
1330 | /** Usable portion of the GTT for GEM */ | |
1331 | unsigned long stolen_base; /* limited to low memory (32-bit) */ | |
1332 | ||
4b5aed62 DV |
1333 | /** PPGTT used for aliasing the PPGTT with the GTT */ |
1334 | struct i915_hw_ppgtt *aliasing_ppgtt; | |
1335 | ||
2cfcd32a | 1336 | struct notifier_block oom_notifier; |
e87666b5 | 1337 | struct notifier_block vmap_notifier; |
ceabbba5 | 1338 | struct shrinker shrinker; |
4b5aed62 | 1339 | |
4b5aed62 DV |
1340 | /** LRU list of objects with fence regs on them. */ |
1341 | struct list_head fence_list; | |
1342 | ||
4b5aed62 DV |
1343 | /** |
1344 | * Are we in a non-interruptible section of code like | |
1345 | * modesetting? | |
1346 | */ | |
1347 | bool interruptible; | |
1348 | ||
bdf1e7e3 | 1349 | /* the indicator for dispatch video commands on two BSD rings */ |
6f633402 | 1350 | atomic_t bsd_engine_dispatch_index; |
bdf1e7e3 | 1351 | |
4b5aed62 DV |
1352 | /** Bit 6 swizzling required for X tiling */ |
1353 | uint32_t bit_6_swizzle_x; | |
1354 | /** Bit 6 swizzling required for Y tiling */ | |
1355 | uint32_t bit_6_swizzle_y; | |
1356 | ||
4b5aed62 | 1357 | /* accounting, useful for userland debugging */ |
c20e8355 | 1358 | spinlock_t object_stat_lock; |
4b5aed62 DV |
1359 | size_t object_memory; |
1360 | u32 object_count; | |
1361 | }; | |
1362 | ||
edc3d884 | 1363 | struct drm_i915_error_state_buf { |
0a4cd7c8 | 1364 | struct drm_i915_private *i915; |
edc3d884 MK |
1365 | unsigned bytes; |
1366 | unsigned size; | |
1367 | int err; | |
1368 | u8 *buf; | |
1369 | loff_t start; | |
1370 | loff_t pos; | |
1371 | }; | |
1372 | ||
fc16b48b MK |
1373 | struct i915_error_state_file_priv { |
1374 | struct drm_device *dev; | |
1375 | struct drm_i915_error_state *error; | |
1376 | }; | |
1377 | ||
99584db3 DV |
1378 | struct i915_gpu_error { |
1379 | /* For hangcheck timer */ | |
1380 | #define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */ | |
1381 | #define DRM_I915_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD) | |
be62acb4 MK |
1382 | /* Hang gpu twice in this window and your context gets banned */ |
1383 | #define DRM_I915_CTX_BAN_PERIOD DIV_ROUND_UP(8*DRM_I915_HANGCHECK_PERIOD, 1000) | |
1384 | ||
737b1506 | 1385 | struct delayed_work hangcheck_work; |
99584db3 DV |
1386 | |
1387 | /* For reset and error_state handling. */ | |
1388 | spinlock_t lock; | |
1389 | /* Protected by the above dev->gpu_error.lock. */ | |
1390 | struct drm_i915_error_state *first_error; | |
094f9a54 CW |
1391 | |
1392 | unsigned long missed_irq_rings; | |
1393 | ||
1f83fee0 | 1394 | /** |
2ac0f450 | 1395 | * State variable controlling the reset flow and count |
1f83fee0 | 1396 | * |
2ac0f450 MK |
1397 | * This is a counter which gets incremented when reset is triggered, |
1398 | * and again when reset has been handled. So odd values (lowest bit set) | |
1399 | * means that reset is in progress and even values that | |
1400 | * (reset_counter >> 1):th reset was successfully completed. | |
1401 | * | |
1402 | * If reset is not completed succesfully, the I915_WEDGE bit is | |
1403 | * set meaning that hardware is terminally sour and there is no | |
1404 | * recovery. All waiters on the reset_queue will be woken when | |
1405 | * that happens. | |
1406 | * | |
1407 | * This counter is used by the wait_seqno code to notice that reset | |
1408 | * event happened and it needs to restart the entire ioctl (since most | |
1409 | * likely the seqno it waited for won't ever signal anytime soon). | |
f69061be DV |
1410 | * |
1411 | * This is important for lock-free wait paths, where no contended lock | |
1412 | * naturally enforces the correct ordering between the bail-out of the | |
1413 | * waiter and the gpu reset work code. | |
1f83fee0 DV |
1414 | */ |
1415 | atomic_t reset_counter; | |
1416 | ||
1f83fee0 | 1417 | #define I915_RESET_IN_PROGRESS_FLAG 1 |
2ac0f450 | 1418 | #define I915_WEDGED (1 << 31) |
1f83fee0 | 1419 | |
1f15b76f CW |
1420 | /** |
1421 | * Waitqueue to signal when a hang is detected. Used to for waiters | |
1422 | * to release the struct_mutex for the reset to procede. | |
1423 | */ | |
1424 | wait_queue_head_t wait_queue; | |
1425 | ||
1f83fee0 DV |
1426 | /** |
1427 | * Waitqueue to signal when the reset has completed. Used by clients | |
1428 | * that wait for dev_priv->mm.wedged to settle. | |
1429 | */ | |
1430 | wait_queue_head_t reset_queue; | |
33196ded | 1431 | |
094f9a54 | 1432 | /* For missed irq/seqno simulation. */ |
688e6c72 | 1433 | unsigned long test_irq_rings; |
99584db3 DV |
1434 | }; |
1435 | ||
b8efb17b ZR |
1436 | enum modeset_restore { |
1437 | MODESET_ON_LID_OPEN, | |
1438 | MODESET_DONE, | |
1439 | MODESET_SUSPENDED, | |
1440 | }; | |
1441 | ||
500ea70d RV |
1442 | #define DP_AUX_A 0x40 |
1443 | #define DP_AUX_B 0x10 | |
1444 | #define DP_AUX_C 0x20 | |
1445 | #define DP_AUX_D 0x30 | |
1446 | ||
11c1b657 XZ |
1447 | #define DDC_PIN_B 0x05 |
1448 | #define DDC_PIN_C 0x04 | |
1449 | #define DDC_PIN_D 0x06 | |
1450 | ||
6acab15a | 1451 | struct ddi_vbt_port_info { |
ce4dd49e DL |
1452 | /* |
1453 | * This is an index in the HDMI/DVI DDI buffer translation table. | |
1454 | * The special value HDMI_LEVEL_SHIFT_UNKNOWN means the VBT didn't | |
1455 | * populate this field. | |
1456 | */ | |
1457 | #define HDMI_LEVEL_SHIFT_UNKNOWN 0xff | |
6acab15a | 1458 | uint8_t hdmi_level_shift; |
311a2094 PZ |
1459 | |
1460 | uint8_t supports_dvi:1; | |
1461 | uint8_t supports_hdmi:1; | |
1462 | uint8_t supports_dp:1; | |
500ea70d RV |
1463 | |
1464 | uint8_t alternate_aux_channel; | |
11c1b657 | 1465 | uint8_t alternate_ddc_pin; |
75067dde AK |
1466 | |
1467 | uint8_t dp_boost_level; | |
1468 | uint8_t hdmi_boost_level; | |
6acab15a PZ |
1469 | }; |
1470 | ||
bfd7ebda RV |
1471 | enum psr_lines_to_wait { |
1472 | PSR_0_LINES_TO_WAIT = 0, | |
1473 | PSR_1_LINE_TO_WAIT, | |
1474 | PSR_4_LINES_TO_WAIT, | |
1475 | PSR_8_LINES_TO_WAIT | |
83a7280e PB |
1476 | }; |
1477 | ||
41aa3448 RV |
1478 | struct intel_vbt_data { |
1479 | struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */ | |
1480 | struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */ | |
1481 | ||
1482 | /* Feature bits */ | |
1483 | unsigned int int_tv_support:1; | |
1484 | unsigned int lvds_dither:1; | |
1485 | unsigned int lvds_vbt:1; | |
1486 | unsigned int int_crt_support:1; | |
1487 | unsigned int lvds_use_ssc:1; | |
1488 | unsigned int display_clock_mode:1; | |
1489 | unsigned int fdi_rx_polarity_inverted:1; | |
3e845c7a | 1490 | unsigned int panel_type:4; |
41aa3448 RV |
1491 | int lvds_ssc_freq; |
1492 | unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */ | |
1493 | ||
83a7280e PB |
1494 | enum drrs_support_type drrs_type; |
1495 | ||
6aa23e65 JN |
1496 | struct { |
1497 | int rate; | |
1498 | int lanes; | |
1499 | int preemphasis; | |
1500 | int vswing; | |
06411f08 | 1501 | bool low_vswing; |
6aa23e65 JN |
1502 | bool initialized; |
1503 | bool support; | |
1504 | int bpp; | |
1505 | struct edp_power_seq pps; | |
1506 | } edp; | |
41aa3448 | 1507 | |
bfd7ebda RV |
1508 | struct { |
1509 | bool full_link; | |
1510 | bool require_aux_wakeup; | |
1511 | int idle_frames; | |
1512 | enum psr_lines_to_wait lines_to_wait; | |
1513 | int tp1_wakeup_time; | |
1514 | int tp2_tp3_wakeup_time; | |
1515 | } psr; | |
1516 | ||
f00076d2 JN |
1517 | struct { |
1518 | u16 pwm_freq_hz; | |
39fbc9c8 | 1519 | bool present; |
f00076d2 | 1520 | bool active_low_pwm; |
1de6068e | 1521 | u8 min_brightness; /* min_brightness/255 of max */ |
9a41e17d | 1522 | enum intel_backlight_type type; |
f00076d2 JN |
1523 | } backlight; |
1524 | ||
d17c5443 SK |
1525 | /* MIPI DSI */ |
1526 | struct { | |
1527 | u16 panel_id; | |
d3b542fc SK |
1528 | struct mipi_config *config; |
1529 | struct mipi_pps_data *pps; | |
1530 | u8 seq_version; | |
1531 | u32 size; | |
1532 | u8 *data; | |
8d3ed2f3 | 1533 | const u8 *sequence[MIPI_SEQ_MAX]; |
d17c5443 SK |
1534 | } dsi; |
1535 | ||
41aa3448 RV |
1536 | int crt_ddc_pin; |
1537 | ||
1538 | int child_dev_num; | |
768f69c9 | 1539 | union child_device_config *child_dev; |
6acab15a PZ |
1540 | |
1541 | struct ddi_vbt_port_info ddi_port_info[I915_MAX_PORTS]; | |
9d6c875d | 1542 | struct sdvo_device_mapping sdvo_mappings[2]; |
41aa3448 RV |
1543 | }; |
1544 | ||
77c122bc VS |
1545 | enum intel_ddb_partitioning { |
1546 | INTEL_DDB_PART_1_2, | |
1547 | INTEL_DDB_PART_5_6, /* IVB+ */ | |
1548 | }; | |
1549 | ||
1fd527cc VS |
1550 | struct intel_wm_level { |
1551 | bool enable; | |
1552 | uint32_t pri_val; | |
1553 | uint32_t spr_val; | |
1554 | uint32_t cur_val; | |
1555 | uint32_t fbc_val; | |
1556 | }; | |
1557 | ||
820c1980 | 1558 | struct ilk_wm_values { |
609cedef VS |
1559 | uint32_t wm_pipe[3]; |
1560 | uint32_t wm_lp[3]; | |
1561 | uint32_t wm_lp_spr[3]; | |
1562 | uint32_t wm_linetime[3]; | |
1563 | bool enable_fbc_wm; | |
1564 | enum intel_ddb_partitioning partitioning; | |
1565 | }; | |
1566 | ||
262cd2e1 VS |
1567 | struct vlv_pipe_wm { |
1568 | uint16_t primary; | |
1569 | uint16_t sprite[2]; | |
1570 | uint8_t cursor; | |
1571 | }; | |
ae80152d | 1572 | |
262cd2e1 VS |
1573 | struct vlv_sr_wm { |
1574 | uint16_t plane; | |
1575 | uint8_t cursor; | |
1576 | }; | |
ae80152d | 1577 | |
262cd2e1 VS |
1578 | struct vlv_wm_values { |
1579 | struct vlv_pipe_wm pipe[3]; | |
1580 | struct vlv_sr_wm sr; | |
0018fda1 VS |
1581 | struct { |
1582 | uint8_t cursor; | |
1583 | uint8_t sprite[2]; | |
1584 | uint8_t primary; | |
1585 | } ddl[3]; | |
6eb1a681 VS |
1586 | uint8_t level; |
1587 | bool cxsr; | |
0018fda1 VS |
1588 | }; |
1589 | ||
c193924e | 1590 | struct skl_ddb_entry { |
16160e3d | 1591 | uint16_t start, end; /* in number of blocks, 'end' is exclusive */ |
c193924e DL |
1592 | }; |
1593 | ||
1594 | static inline uint16_t skl_ddb_entry_size(const struct skl_ddb_entry *entry) | |
1595 | { | |
16160e3d | 1596 | return entry->end - entry->start; |
c193924e DL |
1597 | } |
1598 | ||
08db6652 DL |
1599 | static inline bool skl_ddb_entry_equal(const struct skl_ddb_entry *e1, |
1600 | const struct skl_ddb_entry *e2) | |
1601 | { | |
1602 | if (e1->start == e2->start && e1->end == e2->end) | |
1603 | return true; | |
1604 | ||
1605 | return false; | |
1606 | } | |
1607 | ||
c193924e | 1608 | struct skl_ddb_allocation { |
34bb56af | 1609 | struct skl_ddb_entry pipe[I915_MAX_PIPES]; |
2cd601c6 | 1610 | struct skl_ddb_entry plane[I915_MAX_PIPES][I915_MAX_PLANES]; /* packed/uv */ |
4969d33e | 1611 | struct skl_ddb_entry y_plane[I915_MAX_PIPES][I915_MAX_PLANES]; |
c193924e DL |
1612 | }; |
1613 | ||
2ac96d2a | 1614 | struct skl_wm_values { |
2b4b9f35 | 1615 | unsigned dirty_pipes; |
c193924e | 1616 | struct skl_ddb_allocation ddb; |
2ac96d2a PB |
1617 | uint32_t wm_linetime[I915_MAX_PIPES]; |
1618 | uint32_t plane[I915_MAX_PIPES][I915_MAX_PLANES][8]; | |
2ac96d2a | 1619 | uint32_t plane_trans[I915_MAX_PIPES][I915_MAX_PLANES]; |
2ac96d2a PB |
1620 | }; |
1621 | ||
1622 | struct skl_wm_level { | |
1623 | bool plane_en[I915_MAX_PLANES]; | |
1624 | uint16_t plane_res_b[I915_MAX_PLANES]; | |
1625 | uint8_t plane_res_l[I915_MAX_PLANES]; | |
2ac96d2a PB |
1626 | }; |
1627 | ||
c67a470b | 1628 | /* |
765dab67 PZ |
1629 | * This struct helps tracking the state needed for runtime PM, which puts the |
1630 | * device in PCI D3 state. Notice that when this happens, nothing on the | |
1631 | * graphics device works, even register access, so we don't get interrupts nor | |
1632 | * anything else. | |
c67a470b | 1633 | * |
765dab67 PZ |
1634 | * Every piece of our code that needs to actually touch the hardware needs to |
1635 | * either call intel_runtime_pm_get or call intel_display_power_get with the | |
1636 | * appropriate power domain. | |
a8a8bd54 | 1637 | * |
765dab67 PZ |
1638 | * Our driver uses the autosuspend delay feature, which means we'll only really |
1639 | * suspend if we stay with zero refcount for a certain amount of time. The | |
f458ebbc | 1640 | * default value is currently very conservative (see intel_runtime_pm_enable), but |
765dab67 | 1641 | * it can be changed with the standard runtime PM files from sysfs. |
c67a470b PZ |
1642 | * |
1643 | * The irqs_disabled variable becomes true exactly after we disable the IRQs and | |
1644 | * goes back to false exactly before we reenable the IRQs. We use this variable | |
1645 | * to check if someone is trying to enable/disable IRQs while they're supposed | |
1646 | * to be disabled. This shouldn't happen and we'll print some error messages in | |
730488b2 | 1647 | * case it happens. |
c67a470b | 1648 | * |
765dab67 | 1649 | * For more, read the Documentation/power/runtime_pm.txt. |
c67a470b | 1650 | */ |
5d584b2e | 1651 | struct i915_runtime_pm { |
1f814dac | 1652 | atomic_t wakeref_count; |
2b19efeb | 1653 | atomic_t atomic_seq; |
5d584b2e | 1654 | bool suspended; |
2aeb7d3a | 1655 | bool irqs_enabled; |
c67a470b PZ |
1656 | }; |
1657 | ||
926321d5 DV |
1658 | enum intel_pipe_crc_source { |
1659 | INTEL_PIPE_CRC_SOURCE_NONE, | |
1660 | INTEL_PIPE_CRC_SOURCE_PLANE1, | |
1661 | INTEL_PIPE_CRC_SOURCE_PLANE2, | |
1662 | INTEL_PIPE_CRC_SOURCE_PF, | |
5b3a856b | 1663 | INTEL_PIPE_CRC_SOURCE_PIPE, |
3d099a05 DV |
1664 | /* TV/DP on pre-gen5/vlv can't use the pipe source. */ |
1665 | INTEL_PIPE_CRC_SOURCE_TV, | |
1666 | INTEL_PIPE_CRC_SOURCE_DP_B, | |
1667 | INTEL_PIPE_CRC_SOURCE_DP_C, | |
1668 | INTEL_PIPE_CRC_SOURCE_DP_D, | |
46a19188 | 1669 | INTEL_PIPE_CRC_SOURCE_AUTO, |
926321d5 DV |
1670 | INTEL_PIPE_CRC_SOURCE_MAX, |
1671 | }; | |
1672 | ||
8bf1e9f1 | 1673 | struct intel_pipe_crc_entry { |
ac2300d4 | 1674 | uint32_t frame; |
8bf1e9f1 SH |
1675 | uint32_t crc[5]; |
1676 | }; | |
1677 | ||
b2c88f5b | 1678 | #define INTEL_PIPE_CRC_ENTRIES_NR 128 |
8bf1e9f1 | 1679 | struct intel_pipe_crc { |
d538bbdf DL |
1680 | spinlock_t lock; |
1681 | bool opened; /* exclusive access to the result file */ | |
e5f75aca | 1682 | struct intel_pipe_crc_entry *entries; |
926321d5 | 1683 | enum intel_pipe_crc_source source; |
d538bbdf | 1684 | int head, tail; |
07144428 | 1685 | wait_queue_head_t wq; |
8bf1e9f1 SH |
1686 | }; |
1687 | ||
f99d7069 | 1688 | struct i915_frontbuffer_tracking { |
b5add959 | 1689 | spinlock_t lock; |
f99d7069 DV |
1690 | |
1691 | /* | |
1692 | * Tracking bits for delayed frontbuffer flushing du to gpu activity or | |
1693 | * scheduled flips. | |
1694 | */ | |
1695 | unsigned busy_bits; | |
1696 | unsigned flip_bits; | |
1697 | }; | |
1698 | ||
7225342a | 1699 | struct i915_wa_reg { |
f0f59a00 | 1700 | i915_reg_t addr; |
7225342a MK |
1701 | u32 value; |
1702 | /* bitmask representing WA bits */ | |
1703 | u32 mask; | |
1704 | }; | |
1705 | ||
33136b06 AS |
1706 | /* |
1707 | * RING_MAX_NONPRIV_SLOTS is per-engine but at this point we are only | |
1708 | * allowing it for RCS as we don't foresee any requirement of having | |
1709 | * a whitelist for other engines. When it is really required for | |
1710 | * other engines then the limit need to be increased. | |
1711 | */ | |
1712 | #define I915_MAX_WA_REGS (16 + RING_MAX_NONPRIV_SLOTS) | |
7225342a MK |
1713 | |
1714 | struct i915_workarounds { | |
1715 | struct i915_wa_reg reg[I915_MAX_WA_REGS]; | |
1716 | u32 count; | |
666796da | 1717 | u32 hw_whitelist_count[I915_NUM_ENGINES]; |
7225342a MK |
1718 | }; |
1719 | ||
cf9d2890 YZ |
1720 | struct i915_virtual_gpu { |
1721 | bool active; | |
1722 | }; | |
1723 | ||
aa363136 MR |
1724 | /* used in computing the new watermarks state */ |
1725 | struct intel_wm_config { | |
1726 | unsigned int num_pipes_active; | |
1727 | bool sprites_enabled; | |
1728 | bool sprites_scaled; | |
1729 | }; | |
1730 | ||
77fec556 | 1731 | struct drm_i915_private { |
8f460e2c CW |
1732 | struct drm_device drm; |
1733 | ||
efab6d8d | 1734 | struct kmem_cache *objects; |
e20d2ab7 | 1735 | struct kmem_cache *vmas; |
efab6d8d | 1736 | struct kmem_cache *requests; |
f4c956ad | 1737 | |
5c969aa7 | 1738 | const struct intel_device_info info; |
f4c956ad DV |
1739 | |
1740 | int relative_constants_mode; | |
1741 | ||
1742 | void __iomem *regs; | |
1743 | ||
907b28c5 | 1744 | struct intel_uncore uncore; |
f4c956ad | 1745 | |
cf9d2890 YZ |
1746 | struct i915_virtual_gpu vgpu; |
1747 | ||
0ad35fed ZW |
1748 | struct intel_gvt gvt; |
1749 | ||
33a732f4 AD |
1750 | struct intel_guc guc; |
1751 | ||
eb805623 DV |
1752 | struct intel_csr csr; |
1753 | ||
5ea6e5e3 | 1754 | struct intel_gmbus gmbus[GMBUS_NUM_PINS]; |
28c70f16 | 1755 | |
f4c956ad DV |
1756 | /** gmbus_mutex protects against concurrent usage of the single hw gmbus |
1757 | * controller on different i2c buses. */ | |
1758 | struct mutex gmbus_mutex; | |
1759 | ||
1760 | /** | |
1761 | * Base address of the gmbus and gpio block. | |
1762 | */ | |
1763 | uint32_t gpio_mmio_base; | |
1764 | ||
b6fdd0f2 SS |
1765 | /* MMIO base address for MIPI regs */ |
1766 | uint32_t mipi_mmio_base; | |
1767 | ||
443a389f VS |
1768 | uint32_t psr_mmio_base; |
1769 | ||
44cb734c ID |
1770 | uint32_t pps_mmio_base; |
1771 | ||
28c70f16 DV |
1772 | wait_queue_head_t gmbus_wait_queue; |
1773 | ||
f4c956ad | 1774 | struct pci_dev *bridge_dev; |
0ca5fa3a | 1775 | struct i915_gem_context *kernel_context; |
666796da | 1776 | struct intel_engine_cs engine[I915_NUM_ENGINES]; |
51d545d0 | 1777 | struct i915_vma *semaphore; |
ddf07be7 | 1778 | u32 next_seqno; |
f4c956ad | 1779 | |
ba8286fa | 1780 | struct drm_dma_handle *status_page_dmah; |
f4c956ad DV |
1781 | struct resource mch_res; |
1782 | ||
f4c956ad DV |
1783 | /* protects the irq masks */ |
1784 | spinlock_t irq_lock; | |
1785 | ||
84c33a64 SG |
1786 | /* protects the mmio flip data */ |
1787 | spinlock_t mmio_flip_lock; | |
1788 | ||
f8b79e58 ID |
1789 | bool display_irqs_enabled; |
1790 | ||
9ee32fea DV |
1791 | /* To control wakeup latency, e.g. for irq-driven dp aux transfers. */ |
1792 | struct pm_qos_request pm_qos; | |
1793 | ||
a580516d VS |
1794 | /* Sideband mailbox protection */ |
1795 | struct mutex sb_lock; | |
f4c956ad DV |
1796 | |
1797 | /** Cached value of IMR to avoid reads in updating the bitfield */ | |
abd58f01 BW |
1798 | union { |
1799 | u32 irq_mask; | |
1800 | u32 de_irq_mask[I915_MAX_PIPES]; | |
1801 | }; | |
f4c956ad | 1802 | u32 gt_irq_mask; |
605cd25b | 1803 | u32 pm_irq_mask; |
a6706b45 | 1804 | u32 pm_rps_events; |
91d181dd | 1805 | u32 pipestat_irq_mask[I915_MAX_PIPES]; |
f4c956ad | 1806 | |
5fcece80 | 1807 | struct i915_hotplug hotplug; |
ab34a7e8 | 1808 | struct intel_fbc fbc; |
439d7ac0 | 1809 | struct i915_drrs drrs; |
f4c956ad | 1810 | struct intel_opregion opregion; |
41aa3448 | 1811 | struct intel_vbt_data vbt; |
f4c956ad | 1812 | |
d9ceb816 JB |
1813 | bool preserve_bios_swizzle; |
1814 | ||
f4c956ad DV |
1815 | /* overlay */ |
1816 | struct intel_overlay *overlay; | |
f4c956ad | 1817 | |
58c68779 | 1818 | /* backlight registers and fields in struct intel_panel */ |
07f11d49 | 1819 | struct mutex backlight_lock; |
31ad8ec6 | 1820 | |
f4c956ad | 1821 | /* LVDS info */ |
f4c956ad DV |
1822 | bool no_aux_handshake; |
1823 | ||
e39b999a VS |
1824 | /* protects panel power sequencer state */ |
1825 | struct mutex pps_mutex; | |
1826 | ||
f4c956ad | 1827 | struct drm_i915_fence_reg fence_regs[I915_MAX_NUM_FENCES]; /* assume 965 */ |
f4c956ad DV |
1828 | int num_fence_regs; /* 8 on pre-965, 16 otherwise */ |
1829 | ||
1830 | unsigned int fsb_freq, mem_freq, is_ddr3; | |
b2045352 | 1831 | unsigned int skl_preferred_vco_freq; |
1a617b77 | 1832 | unsigned int cdclk_freq, max_cdclk_freq, atomic_cdclk_freq; |
adafdc6f | 1833 | unsigned int max_dotclk_freq; |
e7dc33f3 | 1834 | unsigned int rawclk_freq; |
6bcda4f0 | 1835 | unsigned int hpll_freq; |
bfa7df01 | 1836 | unsigned int czclk_freq; |
f4c956ad | 1837 | |
63911d72 | 1838 | struct { |
709e05c3 | 1839 | unsigned int vco, ref; |
63911d72 VS |
1840 | } cdclk_pll; |
1841 | ||
645416f5 DV |
1842 | /** |
1843 | * wq - Driver workqueue for GEM. | |
1844 | * | |
1845 | * NOTE: Work items scheduled here are not allowed to grab any modeset | |
1846 | * locks, for otherwise the flushing done in the pageflip code will | |
1847 | * result in deadlocks. | |
1848 | */ | |
f4c956ad DV |
1849 | struct workqueue_struct *wq; |
1850 | ||
1851 | /* Display functions */ | |
1852 | struct drm_i915_display_funcs display; | |
1853 | ||
1854 | /* PCH chipset type */ | |
1855 | enum intel_pch pch_type; | |
17a303ec | 1856 | unsigned short pch_id; |
f4c956ad DV |
1857 | |
1858 | unsigned long quirks; | |
1859 | ||
b8efb17b ZR |
1860 | enum modeset_restore modeset_restore; |
1861 | struct mutex modeset_restore_lock; | |
e2c8b870 | 1862 | struct drm_atomic_state *modeset_restore_state; |
73974893 | 1863 | struct drm_modeset_acquire_ctx reset_ctx; |
673a394b | 1864 | |
a7bbbd63 | 1865 | struct list_head vm_list; /* Global list of all address spaces */ |
62106b4f | 1866 | struct i915_ggtt ggtt; /* VM representing the global address space */ |
5d4545ae | 1867 | |
4b5aed62 | 1868 | struct i915_gem_mm mm; |
ad46cb53 CW |
1869 | DECLARE_HASHTABLE(mm_structs, 7); |
1870 | struct mutex mm_lock; | |
8781342d | 1871 | |
5d1808ec CW |
1872 | /* The hw wants to have a stable context identifier for the lifetime |
1873 | * of the context (for OA, PASID, faults, etc). This is limited | |
1874 | * in execlists to 21 bits. | |
1875 | */ | |
1876 | struct ida context_hw_ida; | |
1877 | #define MAX_CONTEXT_HW_ID (1<<21) /* exclusive */ | |
1878 | ||
8781342d DV |
1879 | /* Kernel Modesetting */ |
1880 | ||
76c4ac04 DL |
1881 | struct drm_crtc *plane_to_crtc_mapping[I915_MAX_PIPES]; |
1882 | struct drm_crtc *pipe_to_crtc_mapping[I915_MAX_PIPES]; | |
6b95a207 KH |
1883 | wait_queue_head_t pending_flip_queue; |
1884 | ||
c4597872 DV |
1885 | #ifdef CONFIG_DEBUG_FS |
1886 | struct intel_pipe_crc pipe_crc[I915_MAX_PIPES]; | |
1887 | #endif | |
1888 | ||
565602d7 | 1889 | /* dpll and cdclk state is protected by connection_mutex */ |
e72f9fbf DV |
1890 | int num_shared_dpll; |
1891 | struct intel_shared_dpll shared_dplls[I915_NUM_PLLS]; | |
f9476a6c | 1892 | const struct intel_dpll_mgr *dpll_mgr; |
565602d7 | 1893 | |
fbf6d879 ML |
1894 | /* |
1895 | * dpll_lock serializes intel_{prepare,enable,disable}_shared_dpll. | |
1896 | * Must be global rather than per dpll, because on some platforms | |
1897 | * plls share registers. | |
1898 | */ | |
1899 | struct mutex dpll_lock; | |
1900 | ||
565602d7 ML |
1901 | unsigned int active_crtcs; |
1902 | unsigned int min_pixclk[I915_MAX_PIPES]; | |
1903 | ||
e4607fcf | 1904 | int dpio_phy_iosf_port[I915_NUM_PHYS_VLV]; |
ee7b9f93 | 1905 | |
7225342a | 1906 | struct i915_workarounds workarounds; |
888b5995 | 1907 | |
f99d7069 DV |
1908 | struct i915_frontbuffer_tracking fb_tracking; |
1909 | ||
652c393a | 1910 | u16 orig_clock; |
f97108d1 | 1911 | |
c4804411 | 1912 | bool mchbar_need_disable; |
f97108d1 | 1913 | |
a4da4fa4 DV |
1914 | struct intel_l3_parity l3_parity; |
1915 | ||
59124506 | 1916 | /* Cannot be determined by PCIID. You must always read a register. */ |
3accaf7e | 1917 | u32 edram_cap; |
59124506 | 1918 | |
c6a828d3 | 1919 | /* gen6+ rps state */ |
c85aa885 | 1920 | struct intel_gen6_power_mgmt rps; |
c6a828d3 | 1921 | |
20e4d407 DV |
1922 | /* ilk-only ips/rps state. Everything in here is protected by the global |
1923 | * mchdev_lock in intel_pm.c */ | |
c85aa885 | 1924 | struct intel_ilk_power_mgmt ips; |
b5e50c3f | 1925 | |
83c00f55 | 1926 | struct i915_power_domains power_domains; |
a38911a3 | 1927 | |
a031d709 | 1928 | struct i915_psr psr; |
3f51e471 | 1929 | |
99584db3 | 1930 | struct i915_gpu_error gpu_error; |
ae681d96 | 1931 | |
c9cddffc JB |
1932 | struct drm_i915_gem_object *vlv_pctx; |
1933 | ||
0695726e | 1934 | #ifdef CONFIG_DRM_FBDEV_EMULATION |
8be48d92 DA |
1935 | /* list of fbdev register on this device */ |
1936 | struct intel_fbdev *fbdev; | |
82e3b8c1 | 1937 | struct work_struct fbdev_suspend_work; |
4520f53a | 1938 | #endif |
e953fd7b CW |
1939 | |
1940 | struct drm_property *broadcast_rgb_property; | |
3f43c48d | 1941 | struct drm_property *force_audio_property; |
e3689190 | 1942 | |
58fddc28 | 1943 | /* hda/i915 audio component */ |
51e1d83c | 1944 | struct i915_audio_component *audio_component; |
58fddc28 | 1945 | bool audio_component_registered; |
4a21ef7d LY |
1946 | /** |
1947 | * av_mutex - mutex for audio/video sync | |
1948 | * | |
1949 | */ | |
1950 | struct mutex av_mutex; | |
58fddc28 | 1951 | |
254f965c | 1952 | uint32_t hw_context_size; |
a33afea5 | 1953 | struct list_head context_list; |
f4c956ad | 1954 | |
3e68320e | 1955 | u32 fdi_rx_config; |
68d18ad7 | 1956 | |
c231775c | 1957 | /* Shadow for DISPLAY_PHY_CONTROL which can't be safely read */ |
70722468 | 1958 | u32 chv_phy_control; |
c231775c VS |
1959 | /* |
1960 | * Shadows for CHV DPLL_MD regs to keep the state | |
1961 | * checker somewhat working in the presence hardware | |
1962 | * crappiness (can't read out DPLL_MD for pipes B & C). | |
1963 | */ | |
1964 | u32 chv_dpll_md[I915_MAX_PIPES]; | |
adc7f04b | 1965 | u32 bxt_phy_grc; |
70722468 | 1966 | |
842f1c8b | 1967 | u32 suspend_count; |
bc87229f | 1968 | bool suspended_to_idle; |
f4c956ad | 1969 | struct i915_suspend_saved_registers regfile; |
ddeea5b0 | 1970 | struct vlv_s0ix_state vlv_s0ix_state; |
231f42a4 | 1971 | |
656d1b89 L |
1972 | enum { |
1973 | I915_SKL_SAGV_UNKNOWN = 0, | |
1974 | I915_SKL_SAGV_DISABLED, | |
1975 | I915_SKL_SAGV_ENABLED, | |
1976 | I915_SKL_SAGV_NOT_CONTROLLED | |
1977 | } skl_sagv_status; | |
1978 | ||
53615a5e VS |
1979 | struct { |
1980 | /* | |
1981 | * Raw watermark latency values: | |
1982 | * in 0.1us units for WM0, | |
1983 | * in 0.5us units for WM1+. | |
1984 | */ | |
1985 | /* primary */ | |
1986 | uint16_t pri_latency[5]; | |
1987 | /* sprite */ | |
1988 | uint16_t spr_latency[5]; | |
1989 | /* cursor */ | |
1990 | uint16_t cur_latency[5]; | |
2af30a5c PB |
1991 | /* |
1992 | * Raw watermark memory latency values | |
1993 | * for SKL for all 8 levels | |
1994 | * in 1us units. | |
1995 | */ | |
1996 | uint16_t skl_latency[8]; | |
609cedef | 1997 | |
2d41c0b5 PB |
1998 | /* |
1999 | * The skl_wm_values structure is a bit too big for stack | |
2000 | * allocation, so we keep the staging struct where we store | |
2001 | * intermediate results here instead. | |
2002 | */ | |
2003 | struct skl_wm_values skl_results; | |
2004 | ||
609cedef | 2005 | /* current hardware state */ |
2d41c0b5 PB |
2006 | union { |
2007 | struct ilk_wm_values hw; | |
2008 | struct skl_wm_values skl_hw; | |
0018fda1 | 2009 | struct vlv_wm_values vlv; |
2d41c0b5 | 2010 | }; |
58590c14 VS |
2011 | |
2012 | uint8_t max_level; | |
ed4a6a7c MR |
2013 | |
2014 | /* | |
2015 | * Should be held around atomic WM register writing; also | |
2016 | * protects * intel_crtc->wm.active and | |
2017 | * cstate->wm.need_postvbl_update. | |
2018 | */ | |
2019 | struct mutex wm_mutex; | |
279e99d7 MR |
2020 | |
2021 | /* | |
2022 | * Set during HW readout of watermarks/DDB. Some platforms | |
2023 | * need to know when we're still using BIOS-provided values | |
2024 | * (which we don't fully trust). | |
2025 | */ | |
2026 | bool distrust_bios_wm; | |
53615a5e VS |
2027 | } wm; |
2028 | ||
8a187455 PZ |
2029 | struct i915_runtime_pm pm; |
2030 | ||
a83014d3 OM |
2031 | /* Abstract the submission mechanism (legacy ringbuffer or execlists) away */ |
2032 | struct { | |
117897f4 | 2033 | void (*cleanup_engine)(struct intel_engine_cs *engine); |
67d97da3 CW |
2034 | |
2035 | /** | |
2036 | * Is the GPU currently considered idle, or busy executing | |
2037 | * userspace requests? Whilst idle, we allow runtime power | |
2038 | * management to power down the hardware and display clocks. | |
2039 | * In order to reduce the effect on performance, there | |
2040 | * is a slight delay before we do so. | |
2041 | */ | |
2042 | unsigned int active_engines; | |
2043 | bool awake; | |
2044 | ||
2045 | /** | |
2046 | * We leave the user IRQ off as much as possible, | |
2047 | * but this means that requests will finish and never | |
2048 | * be retired once the system goes idle. Set a timer to | |
2049 | * fire periodically while the ring is running. When it | |
2050 | * fires, go retire requests. | |
2051 | */ | |
2052 | struct delayed_work retire_work; | |
2053 | ||
2054 | /** | |
2055 | * When we detect an idle GPU, we want to turn on | |
2056 | * powersaving features. So once we see that there | |
2057 | * are no more requests outstanding and no more | |
2058 | * arrive within a small period of time, we fire | |
2059 | * off the idle_work. | |
2060 | */ | |
2061 | struct delayed_work idle_work; | |
a83014d3 OM |
2062 | } gt; |
2063 | ||
3be60de9 VS |
2064 | /* perform PHY state sanity checks? */ |
2065 | bool chv_phy_assert[2]; | |
2066 | ||
0bdf5a05 TI |
2067 | struct intel_encoder *dig_port_map[I915_MAX_PORTS]; |
2068 | ||
bdf1e7e3 DV |
2069 | /* |
2070 | * NOTE: This is the dri1/ums dungeon, don't add stuff here. Your patch | |
2071 | * will be rejected. Instead look for a better place. | |
2072 | */ | |
77fec556 | 2073 | }; |
1da177e4 | 2074 | |
2c1792a1 CW |
2075 | static inline struct drm_i915_private *to_i915(const struct drm_device *dev) |
2076 | { | |
091387c1 | 2077 | return container_of(dev, struct drm_i915_private, drm); |
2c1792a1 CW |
2078 | } |
2079 | ||
c49d13ee | 2080 | static inline struct drm_i915_private *kdev_to_i915(struct device *kdev) |
888d0d42 | 2081 | { |
c49d13ee | 2082 | return to_i915(dev_get_drvdata(kdev)); |
888d0d42 ID |
2083 | } |
2084 | ||
33a732f4 AD |
2085 | static inline struct drm_i915_private *guc_to_i915(struct intel_guc *guc) |
2086 | { | |
2087 | return container_of(guc, struct drm_i915_private, guc); | |
2088 | } | |
2089 | ||
b4ac5afc DG |
2090 | /* Simple iterator over all initialised engines */ |
2091 | #define for_each_engine(engine__, dev_priv__) \ | |
2092 | for ((engine__) = &(dev_priv__)->engine[0]; \ | |
2093 | (engine__) < &(dev_priv__)->engine[I915_NUM_ENGINES]; \ | |
2094 | (engine__)++) \ | |
2095 | for_each_if (intel_engine_initialized(engine__)) | |
b4519513 | 2096 | |
c3232b18 DG |
2097 | /* Iterator with engine_id */ |
2098 | #define for_each_engine_id(engine__, dev_priv__, id__) \ | |
2099 | for ((engine__) = &(dev_priv__)->engine[0], (id__) = 0; \ | |
2100 | (engine__) < &(dev_priv__)->engine[I915_NUM_ENGINES]; \ | |
2101 | (engine__)++) \ | |
2102 | for_each_if (((id__) = (engine__)->id, \ | |
2103 | intel_engine_initialized(engine__))) | |
2104 | ||
bafb0fce CW |
2105 | #define __mask_next_bit(mask) ({ \ |
2106 | int __idx = ffs(mask) - 1; \ | |
2107 | mask &= ~BIT(__idx); \ | |
2108 | __idx; \ | |
2109 | }) | |
2110 | ||
c3232b18 | 2111 | /* Iterator over subset of engines selected by mask */ |
bafb0fce CW |
2112 | #define for_each_engine_masked(engine__, dev_priv__, mask__, tmp__) \ |
2113 | for (tmp__ = mask__ & INTEL_INFO(dev_priv__)->ring_mask; \ | |
2114 | tmp__ ? (engine__ = &(dev_priv__)->engine[__mask_next_bit(tmp__)]), 1 : 0; ) | |
ee4b6faf | 2115 | |
b1d7e4b4 WF |
2116 | enum hdmi_force_audio { |
2117 | HDMI_AUDIO_OFF_DVI = -2, /* no aux data for HDMI-DVI converter */ | |
2118 | HDMI_AUDIO_OFF, /* force turn off HDMI audio */ | |
2119 | HDMI_AUDIO_AUTO, /* trust EDID */ | |
2120 | HDMI_AUDIO_ON, /* force turn on HDMI audio */ | |
2121 | }; | |
2122 | ||
190d6cd5 | 2123 | #define I915_GTT_OFFSET_NONE ((u32)-1) |
ed2f3452 | 2124 | |
37e680a1 | 2125 | struct drm_i915_gem_object_ops { |
de472664 CW |
2126 | unsigned int flags; |
2127 | #define I915_GEM_OBJECT_HAS_STRUCT_PAGE 0x1 | |
2128 | ||
37e680a1 CW |
2129 | /* Interface between the GEM object and its backing storage. |
2130 | * get_pages() is called once prior to the use of the associated set | |
2131 | * of pages before to binding them into the GTT, and put_pages() is | |
2132 | * called after we no longer need them. As we expect there to be | |
2133 | * associated cost with migrating pages between the backing storage | |
2134 | * and making them available for the GPU (e.g. clflush), we may hold | |
2135 | * onto the pages after they are no longer referenced by the GPU | |
2136 | * in case they may be used again shortly (for example migrating the | |
2137 | * pages to a different memory domain within the GTT). put_pages() | |
2138 | * will therefore most likely be called when the object itself is | |
2139 | * being released or under memory pressure (where we attempt to | |
2140 | * reap pages for the shrinker). | |
2141 | */ | |
2142 | int (*get_pages)(struct drm_i915_gem_object *); | |
2143 | void (*put_pages)(struct drm_i915_gem_object *); | |
de472664 | 2144 | |
5cc9ed4b CW |
2145 | int (*dmabuf_export)(struct drm_i915_gem_object *); |
2146 | void (*release)(struct drm_i915_gem_object *); | |
37e680a1 CW |
2147 | }; |
2148 | ||
a071fa00 DV |
2149 | /* |
2150 | * Frontbuffer tracking bits. Set in obj->frontbuffer_bits while a gem bo is | |
d1b9d039 | 2151 | * considered to be the frontbuffer for the given plane interface-wise. This |
a071fa00 DV |
2152 | * doesn't mean that the hw necessarily already scans it out, but that any |
2153 | * rendering (by the cpu or gpu) will land in the frontbuffer eventually. | |
2154 | * | |
2155 | * We have one bit per pipe and per scanout plane type. | |
2156 | */ | |
d1b9d039 SAK |
2157 | #define INTEL_MAX_SPRITE_BITS_PER_PIPE 5 |
2158 | #define INTEL_FRONTBUFFER_BITS_PER_PIPE 8 | |
a071fa00 DV |
2159 | #define INTEL_FRONTBUFFER_PRIMARY(pipe) \ |
2160 | (1 << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))) | |
2161 | #define INTEL_FRONTBUFFER_CURSOR(pipe) \ | |
d1b9d039 SAK |
2162 | (1 << (1 + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))) |
2163 | #define INTEL_FRONTBUFFER_SPRITE(pipe, plane) \ | |
2164 | (1 << (2 + plane + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))) | |
a071fa00 | 2165 | #define INTEL_FRONTBUFFER_OVERLAY(pipe) \ |
d1b9d039 | 2166 | (1 << (2 + INTEL_MAX_SPRITE_BITS_PER_PIPE + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))) |
cc36513c | 2167 | #define INTEL_FRONTBUFFER_ALL_MASK(pipe) \ |
d1b9d039 | 2168 | (0xff << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))) |
a071fa00 | 2169 | |
673a394b | 2170 | struct drm_i915_gem_object { |
c397b908 | 2171 | struct drm_gem_object base; |
673a394b | 2172 | |
37e680a1 CW |
2173 | const struct drm_i915_gem_object_ops *ops; |
2174 | ||
2f633156 BW |
2175 | /** List of VMAs backed by this object */ |
2176 | struct list_head vma_list; | |
2177 | ||
c1ad11fc CW |
2178 | /** Stolen memory for this object, instead of being backed by shmem. */ |
2179 | struct drm_mm_node *stolen; | |
35c20a60 | 2180 | struct list_head global_list; |
673a394b | 2181 | |
b25cb2f8 BW |
2182 | /** Used in execbuf to temporarily hold a ref */ |
2183 | struct list_head obj_exec_link; | |
673a394b | 2184 | |
8d9d5744 | 2185 | struct list_head batch_pool_link; |
493018dc | 2186 | |
573adb39 | 2187 | unsigned long flags; |
673a394b | 2188 | /** |
65ce3027 CW |
2189 | * This is set if the object is on the active lists (has pending |
2190 | * rendering and so a non-zero seqno), and is not set if it i s on | |
2191 | * inactive (ready to be unbound) list. | |
673a394b | 2192 | */ |
573adb39 CW |
2193 | #define I915_BO_ACTIVE_SHIFT 0 |
2194 | #define I915_BO_ACTIVE_MASK ((1 << I915_NUM_ENGINES) - 1) | |
2195 | #define __I915_BO_ACTIVE(bo) \ | |
2196 | ((READ_ONCE((bo)->flags) >> I915_BO_ACTIVE_SHIFT) & I915_BO_ACTIVE_MASK) | |
673a394b EA |
2197 | |
2198 | /** | |
2199 | * This is set if the object has been written to since last bound | |
2200 | * to the GTT | |
2201 | */ | |
0206e353 | 2202 | unsigned int dirty:1; |
778c3544 | 2203 | |
778c3544 DV |
2204 | /** |
2205 | * Advice: are the backing pages purgeable? | |
2206 | */ | |
0206e353 | 2207 | unsigned int madv:2; |
778c3544 | 2208 | |
fb7d516a DV |
2209 | /** |
2210 | * Whether the current gtt mapping needs to be mappable (and isn't just | |
2211 | * mappable by accident). Track pin and fault separate for a more | |
2212 | * accurate mappable working set. | |
2213 | */ | |
0206e353 | 2214 | unsigned int fault_mappable:1; |
fb7d516a | 2215 | |
24f3a8cf AG |
2216 | /* |
2217 | * Is the object to be mapped as read-only to the GPU | |
2218 | * Only honoured if hardware has relevant pte bit | |
2219 | */ | |
2220 | unsigned long gt_ro:1; | |
651d794f | 2221 | unsigned int cache_level:3; |
0f71979a | 2222 | unsigned int cache_dirty:1; |
93dfb40c | 2223 | |
faf5bf0a | 2224 | atomic_t frontbuffer_bits; |
50349247 | 2225 | unsigned int frontbuffer_ggtt_origin; /* write once */ |
a071fa00 | 2226 | |
9ad36761 | 2227 | /** Current tiling stride for the object, if it's tiled. */ |
3e510a8e CW |
2228 | unsigned int tiling_and_stride; |
2229 | #define FENCE_MINIMUM_STRIDE 128 /* See i915_tiling_ok() */ | |
2230 | #define TILING_MASK (FENCE_MINIMUM_STRIDE-1) | |
2231 | #define STRIDE_MASK (~TILING_MASK) | |
9ad36761 | 2232 | |
15717de2 CW |
2233 | /** Count of VMA actually bound by this object */ |
2234 | unsigned int bind_count; | |
8a0c39b1 TU |
2235 | unsigned int pin_display; |
2236 | ||
9da3da66 | 2237 | struct sg_table *pages; |
a5570178 | 2238 | int pages_pin_count; |
ee286370 CW |
2239 | struct get_page { |
2240 | struct scatterlist *sg; | |
2241 | int last; | |
2242 | } get_page; | |
0a798eb9 | 2243 | void *mapping; |
9a70cc2a | 2244 | |
b4716185 CW |
2245 | /** Breadcrumb of last rendering to the buffer. |
2246 | * There can only be one writer, but we allow for multiple readers. | |
2247 | * If there is a writer that necessarily implies that all other | |
2248 | * read requests are complete - but we may only be lazily clearing | |
2249 | * the read requests. A read request is naturally the most recent | |
2250 | * request on a ring, so we may have two different write and read | |
2251 | * requests on one ring where the write request is older than the | |
2252 | * read request. This allows for the CPU to read from an active | |
2253 | * buffer by only waiting for the write to complete. | |
381f371b CW |
2254 | */ |
2255 | struct i915_gem_active last_read[I915_NUM_ENGINES]; | |
2256 | struct i915_gem_active last_write; | |
673a394b | 2257 | |
80075d49 DV |
2258 | /** References from framebuffers, locks out tiling changes. */ |
2259 | unsigned long framebuffer_references; | |
2260 | ||
280b713b | 2261 | /** Record of address bit 17 of each page at last unbind. */ |
d312ec25 | 2262 | unsigned long *bit_17; |
280b713b | 2263 | |
5cc9ed4b | 2264 | union { |
6a2c4232 CW |
2265 | /** for phy allocated objects */ |
2266 | struct drm_dma_handle *phys_handle; | |
2267 | ||
5cc9ed4b CW |
2268 | struct i915_gem_userptr { |
2269 | uintptr_t ptr; | |
2270 | unsigned read_only :1; | |
2271 | unsigned workers :4; | |
2272 | #define I915_GEM_USERPTR_MAX_WORKERS 15 | |
2273 | ||
ad46cb53 CW |
2274 | struct i915_mm_struct *mm; |
2275 | struct i915_mmu_object *mmu_object; | |
5cc9ed4b CW |
2276 | struct work_struct *work; |
2277 | } userptr; | |
2278 | }; | |
2279 | }; | |
03ac0642 CW |
2280 | |
2281 | static inline struct drm_i915_gem_object * | |
2282 | to_intel_bo(struct drm_gem_object *gem) | |
2283 | { | |
2284 | /* Assert that to_intel_bo(NULL) == NULL */ | |
2285 | BUILD_BUG_ON(offsetof(struct drm_i915_gem_object, base)); | |
2286 | ||
2287 | return container_of(gem, struct drm_i915_gem_object, base); | |
2288 | } | |
2289 | ||
2290 | static inline struct drm_i915_gem_object * | |
2291 | i915_gem_object_lookup(struct drm_file *file, u32 handle) | |
2292 | { | |
2293 | return to_intel_bo(drm_gem_object_lookup(file, handle)); | |
2294 | } | |
2295 | ||
2296 | __deprecated | |
2297 | extern struct drm_gem_object * | |
2298 | drm_gem_object_lookup(struct drm_file *file, u32 handle); | |
23010e43 | 2299 | |
25dc556a CW |
2300 | __attribute__((nonnull)) |
2301 | static inline struct drm_i915_gem_object * | |
2302 | i915_gem_object_get(struct drm_i915_gem_object *obj) | |
2303 | { | |
2304 | drm_gem_object_reference(&obj->base); | |
2305 | return obj; | |
2306 | } | |
2307 | ||
2308 | __deprecated | |
2309 | extern void drm_gem_object_reference(struct drm_gem_object *); | |
2310 | ||
f8c417cd CW |
2311 | __attribute__((nonnull)) |
2312 | static inline void | |
2313 | i915_gem_object_put(struct drm_i915_gem_object *obj) | |
2314 | { | |
2315 | drm_gem_object_unreference(&obj->base); | |
2316 | } | |
2317 | ||
2318 | __deprecated | |
2319 | extern void drm_gem_object_unreference(struct drm_gem_object *); | |
2320 | ||
34911fd3 CW |
2321 | __attribute__((nonnull)) |
2322 | static inline void | |
2323 | i915_gem_object_put_unlocked(struct drm_i915_gem_object *obj) | |
2324 | { | |
2325 | drm_gem_object_unreference_unlocked(&obj->base); | |
2326 | } | |
2327 | ||
2328 | __deprecated | |
2329 | extern void drm_gem_object_unreference_unlocked(struct drm_gem_object *); | |
2330 | ||
b9bcd14a CW |
2331 | static inline bool |
2332 | i915_gem_object_has_struct_page(const struct drm_i915_gem_object *obj) | |
2333 | { | |
2334 | return obj->ops->flags & I915_GEM_OBJECT_HAS_STRUCT_PAGE; | |
2335 | } | |
2336 | ||
573adb39 CW |
2337 | static inline unsigned long |
2338 | i915_gem_object_get_active(const struct drm_i915_gem_object *obj) | |
2339 | { | |
2340 | return (obj->flags >> I915_BO_ACTIVE_SHIFT) & I915_BO_ACTIVE_MASK; | |
2341 | } | |
2342 | ||
2343 | static inline bool | |
2344 | i915_gem_object_is_active(const struct drm_i915_gem_object *obj) | |
2345 | { | |
2346 | return i915_gem_object_get_active(obj); | |
2347 | } | |
2348 | ||
2349 | static inline void | |
2350 | i915_gem_object_set_active(struct drm_i915_gem_object *obj, int engine) | |
2351 | { | |
2352 | obj->flags |= BIT(engine + I915_BO_ACTIVE_SHIFT); | |
2353 | } | |
2354 | ||
2355 | static inline void | |
2356 | i915_gem_object_clear_active(struct drm_i915_gem_object *obj, int engine) | |
2357 | { | |
2358 | obj->flags &= ~BIT(engine + I915_BO_ACTIVE_SHIFT); | |
2359 | } | |
2360 | ||
2361 | static inline bool | |
2362 | i915_gem_object_has_active_engine(const struct drm_i915_gem_object *obj, | |
2363 | int engine) | |
2364 | { | |
2365 | return obj->flags & BIT(engine + I915_BO_ACTIVE_SHIFT); | |
2366 | } | |
2367 | ||
3e510a8e CW |
2368 | static inline unsigned int |
2369 | i915_gem_object_get_tiling(struct drm_i915_gem_object *obj) | |
2370 | { | |
2371 | return obj->tiling_and_stride & TILING_MASK; | |
2372 | } | |
2373 | ||
2374 | static inline bool | |
2375 | i915_gem_object_is_tiled(struct drm_i915_gem_object *obj) | |
2376 | { | |
2377 | return i915_gem_object_get_tiling(obj) != I915_TILING_NONE; | |
2378 | } | |
2379 | ||
2380 | static inline unsigned int | |
2381 | i915_gem_object_get_stride(struct drm_i915_gem_object *obj) | |
2382 | { | |
2383 | return obj->tiling_and_stride & STRIDE_MASK; | |
2384 | } | |
2385 | ||
624192cf CW |
2386 | static inline struct i915_vma *i915_vma_get(struct i915_vma *vma) |
2387 | { | |
2388 | i915_gem_object_get(vma->obj); | |
2389 | return vma; | |
2390 | } | |
2391 | ||
2392 | static inline void i915_vma_put(struct i915_vma *vma) | |
2393 | { | |
2394 | lockdep_assert_held(&vma->vm->dev->struct_mutex); | |
2395 | i915_gem_object_put(vma->obj); | |
2396 | } | |
2397 | ||
85d1225e DG |
2398 | /* |
2399 | * Optimised SGL iterator for GEM objects | |
2400 | */ | |
2401 | static __always_inline struct sgt_iter { | |
2402 | struct scatterlist *sgp; | |
2403 | union { | |
2404 | unsigned long pfn; | |
2405 | dma_addr_t dma; | |
2406 | }; | |
2407 | unsigned int curr; | |
2408 | unsigned int max; | |
2409 | } __sgt_iter(struct scatterlist *sgl, bool dma) { | |
2410 | struct sgt_iter s = { .sgp = sgl }; | |
2411 | ||
2412 | if (s.sgp) { | |
2413 | s.max = s.curr = s.sgp->offset; | |
2414 | s.max += s.sgp->length; | |
2415 | if (dma) | |
2416 | s.dma = sg_dma_address(s.sgp); | |
2417 | else | |
2418 | s.pfn = page_to_pfn(sg_page(s.sgp)); | |
2419 | } | |
2420 | ||
2421 | return s; | |
2422 | } | |
2423 | ||
63d15326 DG |
2424 | /** |
2425 | * __sg_next - return the next scatterlist entry in a list | |
2426 | * @sg: The current sg entry | |
2427 | * | |
2428 | * Description: | |
2429 | * If the entry is the last, return NULL; otherwise, step to the next | |
2430 | * element in the array (@sg@+1). If that's a chain pointer, follow it; | |
2431 | * otherwise just return the pointer to the current element. | |
2432 | **/ | |
2433 | static inline struct scatterlist *__sg_next(struct scatterlist *sg) | |
2434 | { | |
2435 | #ifdef CONFIG_DEBUG_SG | |
2436 | BUG_ON(sg->sg_magic != SG_MAGIC); | |
2437 | #endif | |
2438 | return sg_is_last(sg) ? NULL : | |
2439 | likely(!sg_is_chain(++sg)) ? sg : | |
2440 | sg_chain_ptr(sg); | |
2441 | } | |
2442 | ||
85d1225e DG |
2443 | /** |
2444 | * for_each_sgt_dma - iterate over the DMA addresses of the given sg_table | |
2445 | * @__dmap: DMA address (output) | |
2446 | * @__iter: 'struct sgt_iter' (iterator state, internal) | |
2447 | * @__sgt: sg_table to iterate over (input) | |
2448 | */ | |
2449 | #define for_each_sgt_dma(__dmap, __iter, __sgt) \ | |
2450 | for ((__iter) = __sgt_iter((__sgt)->sgl, true); \ | |
2451 | ((__dmap) = (__iter).dma + (__iter).curr); \ | |
2452 | (((__iter).curr += PAGE_SIZE) < (__iter).max) || \ | |
63d15326 | 2453 | ((__iter) = __sgt_iter(__sg_next((__iter).sgp), true), 0)) |
85d1225e DG |
2454 | |
2455 | /** | |
2456 | * for_each_sgt_page - iterate over the pages of the given sg_table | |
2457 | * @__pp: page pointer (output) | |
2458 | * @__iter: 'struct sgt_iter' (iterator state, internal) | |
2459 | * @__sgt: sg_table to iterate over (input) | |
2460 | */ | |
2461 | #define for_each_sgt_page(__pp, __iter, __sgt) \ | |
2462 | for ((__iter) = __sgt_iter((__sgt)->sgl, false); \ | |
2463 | ((__pp) = (__iter).pfn == 0 ? NULL : \ | |
2464 | pfn_to_page((__iter).pfn + ((__iter).curr >> PAGE_SHIFT))); \ | |
2465 | (((__iter).curr += PAGE_SIZE) < (__iter).max) || \ | |
63d15326 | 2466 | ((__iter) = __sgt_iter(__sg_next((__iter).sgp), false), 0)) |
a071fa00 | 2467 | |
351e3db2 BV |
2468 | /* |
2469 | * A command that requires special handling by the command parser. | |
2470 | */ | |
2471 | struct drm_i915_cmd_descriptor { | |
2472 | /* | |
2473 | * Flags describing how the command parser processes the command. | |
2474 | * | |
2475 | * CMD_DESC_FIXED: The command has a fixed length if this is set, | |
2476 | * a length mask if not set | |
2477 | * CMD_DESC_SKIP: The command is allowed but does not follow the | |
2478 | * standard length encoding for the opcode range in | |
2479 | * which it falls | |
2480 | * CMD_DESC_REJECT: The command is never allowed | |
2481 | * CMD_DESC_REGISTER: The command should be checked against the | |
2482 | * register whitelist for the appropriate ring | |
2483 | * CMD_DESC_MASTER: The command is allowed if the submitting process | |
2484 | * is the DRM master | |
2485 | */ | |
2486 | u32 flags; | |
2487 | #define CMD_DESC_FIXED (1<<0) | |
2488 | #define CMD_DESC_SKIP (1<<1) | |
2489 | #define CMD_DESC_REJECT (1<<2) | |
2490 | #define CMD_DESC_REGISTER (1<<3) | |
2491 | #define CMD_DESC_BITMASK (1<<4) | |
2492 | #define CMD_DESC_MASTER (1<<5) | |
2493 | ||
2494 | /* | |
2495 | * The command's unique identification bits and the bitmask to get them. | |
2496 | * This isn't strictly the opcode field as defined in the spec and may | |
2497 | * also include type, subtype, and/or subop fields. | |
2498 | */ | |
2499 | struct { | |
2500 | u32 value; | |
2501 | u32 mask; | |
2502 | } cmd; | |
2503 | ||
2504 | /* | |
2505 | * The command's length. The command is either fixed length (i.e. does | |
2506 | * not include a length field) or has a length field mask. The flag | |
2507 | * CMD_DESC_FIXED indicates a fixed length. Otherwise, the command has | |
2508 | * a length mask. All command entries in a command table must include | |
2509 | * length information. | |
2510 | */ | |
2511 | union { | |
2512 | u32 fixed; | |
2513 | u32 mask; | |
2514 | } length; | |
2515 | ||
2516 | /* | |
2517 | * Describes where to find a register address in the command to check | |
2518 | * against the ring's register whitelist. Only valid if flags has the | |
2519 | * CMD_DESC_REGISTER bit set. | |
6a65c5b9 FJ |
2520 | * |
2521 | * A non-zero step value implies that the command may access multiple | |
2522 | * registers in sequence (e.g. LRI), in that case step gives the | |
2523 | * distance in dwords between individual offset fields. | |
351e3db2 BV |
2524 | */ |
2525 | struct { | |
2526 | u32 offset; | |
2527 | u32 mask; | |
6a65c5b9 | 2528 | u32 step; |
351e3db2 BV |
2529 | } reg; |
2530 | ||
2531 | #define MAX_CMD_DESC_BITMASKS 3 | |
2532 | /* | |
2533 | * Describes command checks where a particular dword is masked and | |
2534 | * compared against an expected value. If the command does not match | |
2535 | * the expected value, the parser rejects it. Only valid if flags has | |
2536 | * the CMD_DESC_BITMASK bit set. Only entries where mask is non-zero | |
2537 | * are valid. | |
d4d48035 BV |
2538 | * |
2539 | * If the check specifies a non-zero condition_mask then the parser | |
2540 | * only performs the check when the bits specified by condition_mask | |
2541 | * are non-zero. | |
351e3db2 BV |
2542 | */ |
2543 | struct { | |
2544 | u32 offset; | |
2545 | u32 mask; | |
2546 | u32 expected; | |
d4d48035 BV |
2547 | u32 condition_offset; |
2548 | u32 condition_mask; | |
351e3db2 BV |
2549 | } bits[MAX_CMD_DESC_BITMASKS]; |
2550 | }; | |
2551 | ||
2552 | /* | |
2553 | * A table of commands requiring special handling by the command parser. | |
2554 | * | |
33a051a5 CW |
2555 | * Each engine has an array of tables. Each table consists of an array of |
2556 | * command descriptors, which must be sorted with command opcodes in | |
2557 | * ascending order. | |
351e3db2 BV |
2558 | */ |
2559 | struct drm_i915_cmd_table { | |
2560 | const struct drm_i915_cmd_descriptor *table; | |
2561 | int count; | |
2562 | }; | |
2563 | ||
dbbe9127 | 2564 | /* Note that the (struct drm_i915_private *) cast is just to shut up gcc. */ |
7312e2dd CW |
2565 | #define __I915__(p) ({ \ |
2566 | struct drm_i915_private *__p; \ | |
2567 | if (__builtin_types_compatible_p(typeof(*p), struct drm_i915_private)) \ | |
2568 | __p = (struct drm_i915_private *)p; \ | |
2569 | else if (__builtin_types_compatible_p(typeof(*p), struct drm_device)) \ | |
2570 | __p = to_i915((struct drm_device *)p); \ | |
2571 | else \ | |
2572 | BUILD_BUG(); \ | |
2573 | __p; \ | |
2574 | }) | |
351c3b53 | 2575 | #define INTEL_INFO(p) (&__I915__(p)->info) |
3f10e82f | 2576 | #define INTEL_GEN(p) (INTEL_INFO(p)->gen) |
87f1f465 | 2577 | #define INTEL_DEVID(p) (INTEL_INFO(p)->device_id) |
cae5852d | 2578 | |
e87a005d | 2579 | #define REVID_FOREVER 0xff |
091387c1 | 2580 | #define INTEL_REVID(p) (__I915__(p)->drm.pdev->revision) |
ac657f64 TU |
2581 | |
2582 | #define GEN_FOREVER (0) | |
2583 | /* | |
2584 | * Returns true if Gen is in inclusive range [Start, End]. | |
2585 | * | |
2586 | * Use GEN_FOREVER for unbound start and or end. | |
2587 | */ | |
2588 | #define IS_GEN(p, s, e) ({ \ | |
2589 | unsigned int __s = (s), __e = (e); \ | |
2590 | BUILD_BUG_ON(!__builtin_constant_p(s)); \ | |
2591 | BUILD_BUG_ON(!__builtin_constant_p(e)); \ | |
2592 | if ((__s) != GEN_FOREVER) \ | |
2593 | __s = (s) - 1; \ | |
2594 | if ((__e) == GEN_FOREVER) \ | |
2595 | __e = BITS_PER_LONG - 1; \ | |
2596 | else \ | |
2597 | __e = (e) - 1; \ | |
2598 | !!(INTEL_INFO(p)->gen_mask & GENMASK((__e), (__s))); \ | |
2599 | }) | |
2600 | ||
e87a005d JN |
2601 | /* |
2602 | * Return true if revision is in range [since,until] inclusive. | |
2603 | * | |
2604 | * Use 0 for open-ended since, and REVID_FOREVER for open-ended until. | |
2605 | */ | |
2606 | #define IS_REVID(p, since, until) \ | |
2607 | (INTEL_REVID(p) >= (since) && INTEL_REVID(p) <= (until)) | |
2608 | ||
87f1f465 CW |
2609 | #define IS_I830(dev) (INTEL_DEVID(dev) == 0x3577) |
2610 | #define IS_845G(dev) (INTEL_DEVID(dev) == 0x2562) | |
cae5852d | 2611 | #define IS_I85X(dev) (INTEL_INFO(dev)->is_i85x) |
87f1f465 | 2612 | #define IS_I865G(dev) (INTEL_DEVID(dev) == 0x2572) |
cae5852d | 2613 | #define IS_I915G(dev) (INTEL_INFO(dev)->is_i915g) |
87f1f465 CW |
2614 | #define IS_I915GM(dev) (INTEL_DEVID(dev) == 0x2592) |
2615 | #define IS_I945G(dev) (INTEL_DEVID(dev) == 0x2772) | |
cae5852d ZN |
2616 | #define IS_I945GM(dev) (INTEL_INFO(dev)->is_i945gm) |
2617 | #define IS_BROADWATER(dev) (INTEL_INFO(dev)->is_broadwater) | |
2618 | #define IS_CRESTLINE(dev) (INTEL_INFO(dev)->is_crestline) | |
87f1f465 | 2619 | #define IS_GM45(dev) (INTEL_DEVID(dev) == 0x2A42) |
cae5852d | 2620 | #define IS_G4X(dev) (INTEL_INFO(dev)->is_g4x) |
87f1f465 CW |
2621 | #define IS_PINEVIEW_G(dev) (INTEL_DEVID(dev) == 0xa001) |
2622 | #define IS_PINEVIEW_M(dev) (INTEL_DEVID(dev) == 0xa011) | |
cae5852d ZN |
2623 | #define IS_PINEVIEW(dev) (INTEL_INFO(dev)->is_pineview) |
2624 | #define IS_G33(dev) (INTEL_INFO(dev)->is_g33) | |
87f1f465 | 2625 | #define IS_IRONLAKE_M(dev) (INTEL_DEVID(dev) == 0x0046) |
4b65177b | 2626 | #define IS_IVYBRIDGE(dev) (INTEL_INFO(dev)->is_ivybridge) |
87f1f465 CW |
2627 | #define IS_IVB_GT1(dev) (INTEL_DEVID(dev) == 0x0156 || \ |
2628 | INTEL_DEVID(dev) == 0x0152 || \ | |
2629 | INTEL_DEVID(dev) == 0x015a) | |
70a3eb7a | 2630 | #define IS_VALLEYVIEW(dev) (INTEL_INFO(dev)->is_valleyview) |
666a4537 | 2631 | #define IS_CHERRYVIEW(dev) (INTEL_INFO(dev)->is_cherryview) |
4cae9ae0 | 2632 | #define IS_HASWELL(dev) (INTEL_INFO(dev)->is_haswell) |
ab0d24ac | 2633 | #define IS_BROADWELL(dev) (INTEL_INFO(dev)->is_broadwell) |
7201c0b3 | 2634 | #define IS_SKYLAKE(dev) (INTEL_INFO(dev)->is_skylake) |
7526ac19 | 2635 | #define IS_BROXTON(dev) (INTEL_INFO(dev)->is_broxton) |
ef11bdb3 | 2636 | #define IS_KABYLAKE(dev) (INTEL_INFO(dev)->is_kabylake) |
cae5852d | 2637 | #define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile) |
ed1c9e2c | 2638 | #define IS_HSW_EARLY_SDV(dev) (IS_HASWELL(dev) && \ |
87f1f465 | 2639 | (INTEL_DEVID(dev) & 0xFF00) == 0x0C00) |
5dd8c4c3 | 2640 | #define IS_BDW_ULT(dev) (IS_BROADWELL(dev) && \ |
6b96d705 | 2641 | ((INTEL_DEVID(dev) & 0xf) == 0x6 || \ |
0dc6f20b | 2642 | (INTEL_DEVID(dev) & 0xf) == 0xb || \ |
87f1f465 | 2643 | (INTEL_DEVID(dev) & 0xf) == 0xe)) |
ebb72aad VS |
2644 | /* ULX machines are also considered ULT. */ |
2645 | #define IS_BDW_ULX(dev) (IS_BROADWELL(dev) && \ | |
2646 | (INTEL_DEVID(dev) & 0xf) == 0xe) | |
a0fcbd95 RV |
2647 | #define IS_BDW_GT3(dev) (IS_BROADWELL(dev) && \ |
2648 | (INTEL_DEVID(dev) & 0x00F0) == 0x0020) | |
5dd8c4c3 | 2649 | #define IS_HSW_ULT(dev) (IS_HASWELL(dev) && \ |
87f1f465 | 2650 | (INTEL_DEVID(dev) & 0xFF00) == 0x0A00) |
9435373e | 2651 | #define IS_HSW_GT3(dev) (IS_HASWELL(dev) && \ |
87f1f465 | 2652 | (INTEL_DEVID(dev) & 0x00F0) == 0x0020) |
9bbfd20a | 2653 | /* ULX machines are also considered ULT. */ |
87f1f465 CW |
2654 | #define IS_HSW_ULX(dev) (INTEL_DEVID(dev) == 0x0A0E || \ |
2655 | INTEL_DEVID(dev) == 0x0A1E) | |
f8896f5d DW |
2656 | #define IS_SKL_ULT(dev) (INTEL_DEVID(dev) == 0x1906 || \ |
2657 | INTEL_DEVID(dev) == 0x1913 || \ | |
2658 | INTEL_DEVID(dev) == 0x1916 || \ | |
2659 | INTEL_DEVID(dev) == 0x1921 || \ | |
2660 | INTEL_DEVID(dev) == 0x1926) | |
2661 | #define IS_SKL_ULX(dev) (INTEL_DEVID(dev) == 0x190E || \ | |
2662 | INTEL_DEVID(dev) == 0x1915 || \ | |
2663 | INTEL_DEVID(dev) == 0x191E) | |
a5b7991c RV |
2664 | #define IS_KBL_ULT(dev) (INTEL_DEVID(dev) == 0x5906 || \ |
2665 | INTEL_DEVID(dev) == 0x5913 || \ | |
2666 | INTEL_DEVID(dev) == 0x5916 || \ | |
2667 | INTEL_DEVID(dev) == 0x5921 || \ | |
2668 | INTEL_DEVID(dev) == 0x5926) | |
2669 | #define IS_KBL_ULX(dev) (INTEL_DEVID(dev) == 0x590E || \ | |
2670 | INTEL_DEVID(dev) == 0x5915 || \ | |
2671 | INTEL_DEVID(dev) == 0x591E) | |
7a58bad0 SAK |
2672 | #define IS_SKL_GT3(dev) (IS_SKYLAKE(dev) && \ |
2673 | (INTEL_DEVID(dev) & 0x00F0) == 0x0020) | |
2674 | #define IS_SKL_GT4(dev) (IS_SKYLAKE(dev) && \ | |
2675 | (INTEL_DEVID(dev) & 0x00F0) == 0x0030) | |
2676 | ||
b833d685 | 2677 | #define IS_PRELIMINARY_HW(intel_info) ((intel_info)->is_preliminary) |
cae5852d | 2678 | |
ef712bb4 JN |
2679 | #define SKL_REVID_A0 0x0 |
2680 | #define SKL_REVID_B0 0x1 | |
2681 | #define SKL_REVID_C0 0x2 | |
2682 | #define SKL_REVID_D0 0x3 | |
2683 | #define SKL_REVID_E0 0x4 | |
2684 | #define SKL_REVID_F0 0x5 | |
4ba9c1f7 MK |
2685 | #define SKL_REVID_G0 0x6 |
2686 | #define SKL_REVID_H0 0x7 | |
ef712bb4 | 2687 | |
e87a005d JN |
2688 | #define IS_SKL_REVID(p, since, until) (IS_SKYLAKE(p) && IS_REVID(p, since, until)) |
2689 | ||
ef712bb4 | 2690 | #define BXT_REVID_A0 0x0 |
fffda3f4 | 2691 | #define BXT_REVID_A1 0x1 |
ef712bb4 JN |
2692 | #define BXT_REVID_B0 0x3 |
2693 | #define BXT_REVID_C0 0x9 | |
6c74c87f | 2694 | |
e87a005d JN |
2695 | #define IS_BXT_REVID(p, since, until) (IS_BROXTON(p) && IS_REVID(p, since, until)) |
2696 | ||
c033a37c MK |
2697 | #define KBL_REVID_A0 0x0 |
2698 | #define KBL_REVID_B0 0x1 | |
fe905819 MK |
2699 | #define KBL_REVID_C0 0x2 |
2700 | #define KBL_REVID_D0 0x3 | |
2701 | #define KBL_REVID_E0 0x4 | |
c033a37c MK |
2702 | |
2703 | #define IS_KBL_REVID(p, since, until) \ | |
2704 | (IS_KABYLAKE(p) && IS_REVID(p, since, until)) | |
2705 | ||
85436696 JB |
2706 | /* |
2707 | * The genX designation typically refers to the render engine, so render | |
2708 | * capability related checks should use IS_GEN, while display and other checks | |
2709 | * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular | |
2710 | * chips, etc.). | |
2711 | */ | |
af1346a0 TU |
2712 | #define IS_GEN2(dev) (!!(INTEL_INFO(dev)->gen_mask & BIT(1))) |
2713 | #define IS_GEN3(dev) (!!(INTEL_INFO(dev)->gen_mask & BIT(2))) | |
2714 | #define IS_GEN4(dev) (!!(INTEL_INFO(dev)->gen_mask & BIT(3))) | |
2715 | #define IS_GEN5(dev) (!!(INTEL_INFO(dev)->gen_mask & BIT(4))) | |
2716 | #define IS_GEN6(dev) (!!(INTEL_INFO(dev)->gen_mask & BIT(5))) | |
2717 | #define IS_GEN7(dev) (!!(INTEL_INFO(dev)->gen_mask & BIT(6))) | |
2718 | #define IS_GEN8(dev) (!!(INTEL_INFO(dev)->gen_mask & BIT(7))) | |
2719 | #define IS_GEN9(dev) (!!(INTEL_INFO(dev)->gen_mask & BIT(8))) | |
cae5852d | 2720 | |
a19d6ff2 TU |
2721 | #define ENGINE_MASK(id) BIT(id) |
2722 | #define RENDER_RING ENGINE_MASK(RCS) | |
2723 | #define BSD_RING ENGINE_MASK(VCS) | |
2724 | #define BLT_RING ENGINE_MASK(BCS) | |
2725 | #define VEBOX_RING ENGINE_MASK(VECS) | |
2726 | #define BSD2_RING ENGINE_MASK(VCS2) | |
2727 | #define ALL_ENGINES (~0) | |
2728 | ||
2729 | #define HAS_ENGINE(dev_priv, id) \ | |
af1346a0 | 2730 | (!!(INTEL_INFO(dev_priv)->ring_mask & ENGINE_MASK(id))) |
a19d6ff2 TU |
2731 | |
2732 | #define HAS_BSD(dev_priv) HAS_ENGINE(dev_priv, VCS) | |
2733 | #define HAS_BSD2(dev_priv) HAS_ENGINE(dev_priv, VCS2) | |
2734 | #define HAS_BLT(dev_priv) HAS_ENGINE(dev_priv, BCS) | |
2735 | #define HAS_VEBOX(dev_priv) HAS_ENGINE(dev_priv, VECS) | |
2736 | ||
63c42e56 | 2737 | #define HAS_LLC(dev) (INTEL_INFO(dev)->has_llc) |
ca377809 | 2738 | #define HAS_SNOOP(dev) (INTEL_INFO(dev)->has_snoop) |
af1346a0 | 2739 | #define HAS_EDRAM(dev) (!!(__I915__(dev)->edram_cap & EDRAM_ENABLED)) |
63c42e56 | 2740 | #define HAS_WT(dev) ((IS_HASWELL(dev) || IS_BROADWELL(dev)) && \ |
3accaf7e | 2741 | HAS_EDRAM(dev)) |
cae5852d ZN |
2742 | #define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws) |
2743 | ||
254f965c | 2744 | #define HAS_HW_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 6) |
d7f621e5 | 2745 | #define HAS_LOGICAL_RING_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 8) |
692ef70c | 2746 | #define USES_PPGTT(dev) (i915.enable_ppgtt) |
81ba8aef MT |
2747 | #define USES_FULL_PPGTT(dev) (i915.enable_ppgtt >= 2) |
2748 | #define USES_FULL_48BIT_PPGTT(dev) (i915.enable_ppgtt == 3) | |
1d2a314c | 2749 | |
05394f39 | 2750 | #define HAS_OVERLAY(dev) (INTEL_INFO(dev)->has_overlay) |
cae5852d ZN |
2751 | #define OVERLAY_NEEDS_PHYSICAL(dev) (INTEL_INFO(dev)->overlay_needs_physical) |
2752 | ||
b45305fc DV |
2753 | /* Early gen2 have a totally busted CS tlb and require pinned batches. */ |
2754 | #define HAS_BROKEN_CS_TLB(dev) (IS_I830(dev) || IS_845G(dev)) | |
06e668ac MK |
2755 | |
2756 | /* WaRsDisableCoarsePowerGating:skl,bxt */ | |
61251512 TU |
2757 | #define NEEDS_WaRsDisableCoarsePowerGating(dev_priv) \ |
2758 | (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1) || \ | |
2759 | IS_SKL_GT3(dev_priv) || \ | |
2760 | IS_SKL_GT4(dev_priv)) | |
185c66e5 | 2761 | |
4e6b788c DV |
2762 | /* |
2763 | * dp aux and gmbus irq on gen4 seems to be able to generate legacy interrupts | |
2764 | * even when in MSI mode. This results in spurious interrupt warnings if the | |
2765 | * legacy irq no. is shared with another device. The kernel then disables that | |
2766 | * interrupt source and so prevents the other device from working properly. | |
2767 | */ | |
2768 | #define HAS_AUX_IRQ(dev) (INTEL_INFO(dev)->gen >= 5) | |
2769 | #define HAS_GMBUS_IRQ(dev) (INTEL_INFO(dev)->gen >= 5) | |
b45305fc | 2770 | |
cae5852d ZN |
2771 | /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte |
2772 | * rows, which changed the alignment requirements and fence programming. | |
2773 | */ | |
2774 | #define HAS_128_BYTE_Y_TILING(dev) (!IS_GEN2(dev) && !(IS_I915G(dev) || \ | |
2775 | IS_I915GM(dev))) | |
cae5852d ZN |
2776 | #define SUPPORTS_TV(dev) (INTEL_INFO(dev)->supports_tv) |
2777 | #define I915_HAS_HOTPLUG(dev) (INTEL_INFO(dev)->has_hotplug) | |
cae5852d ZN |
2778 | |
2779 | #define HAS_FW_BLC(dev) (INTEL_INFO(dev)->gen > 2) | |
2780 | #define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr) | |
3a77c4c4 | 2781 | #define HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc) |
cae5852d | 2782 | |
dbf7786e | 2783 | #define HAS_IPS(dev) (IS_HSW_ULT(dev) || IS_BROADWELL(dev)) |
f5adf94e | 2784 | |
0c9b3715 JN |
2785 | #define HAS_DP_MST(dev) (IS_HASWELL(dev) || IS_BROADWELL(dev) || \ |
2786 | INTEL_INFO(dev)->gen >= 9) | |
2787 | ||
dd93be58 | 2788 | #define HAS_DDI(dev) (INTEL_INFO(dev)->has_ddi) |
30568c45 | 2789 | #define HAS_FPGA_DBG_UNCLAIMED(dev) (INTEL_INFO(dev)->has_fpga_dbg) |
6e3b84d8 | 2790 | #define HAS_PSR(dev) (INTEL_INFO(dev)->has_psr) |
4aa4c23f | 2791 | #define HAS_RUNTIME_PM(dev) (INTEL_INFO(dev)->has_runtime_pm) |
58abf1da | 2792 | #define HAS_RC6(dev) (INTEL_INFO(dev)->gen >= 6) |
7e22dbbb | 2793 | #define HAS_RC6p(dev) (IS_GEN6(dev) || IS_IVYBRIDGE(dev)) |
affa9354 | 2794 | |
3bacde19 | 2795 | #define HAS_CSR(dev) (INTEL_INFO(dev)->has_csr) |
eb805623 | 2796 | |
1a3d1898 DG |
2797 | /* |
2798 | * For now, anything with a GuC requires uCode loading, and then supports | |
2799 | * command submission once loaded. But these are logically independent | |
2800 | * properties, so we have separate macros to test them. | |
2801 | */ | |
6f8be280 | 2802 | #define HAS_GUC(dev) (IS_GEN9(dev)) |
1a3d1898 DG |
2803 | #define HAS_GUC_UCODE(dev) (HAS_GUC(dev)) |
2804 | #define HAS_GUC_SCHED(dev) (HAS_GUC(dev)) | |
33a732f4 | 2805 | |
a9ed33ca AJ |
2806 | #define HAS_RESOURCE_STREAMER(dev) (IS_HASWELL(dev) || \ |
2807 | INTEL_INFO(dev)->gen >= 8) | |
2808 | ||
33e141ed | 2809 | #define HAS_POOLED_EU(dev) (INTEL_INFO(dev)->has_pooled_eu) |
2810 | ||
17a303ec PZ |
2811 | #define INTEL_PCH_DEVICE_ID_MASK 0xff00 |
2812 | #define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00 | |
2813 | #define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00 | |
2814 | #define INTEL_PCH_PPT_DEVICE_ID_TYPE 0x1e00 | |
2815 | #define INTEL_PCH_LPT_DEVICE_ID_TYPE 0x8c00 | |
2816 | #define INTEL_PCH_LPT_LP_DEVICE_ID_TYPE 0x9c00 | |
e7e7ea20 S |
2817 | #define INTEL_PCH_SPT_DEVICE_ID_TYPE 0xA100 |
2818 | #define INTEL_PCH_SPT_LP_DEVICE_ID_TYPE 0x9D00 | |
22dea0be | 2819 | #define INTEL_PCH_KBP_DEVICE_ID_TYPE 0xA200 |
30c964a6 | 2820 | #define INTEL_PCH_P2X_DEVICE_ID_TYPE 0x7100 |
1844a66b | 2821 | #define INTEL_PCH_P3X_DEVICE_ID_TYPE 0x7000 |
39bfcd52 | 2822 | #define INTEL_PCH_QEMU_DEVICE_ID_TYPE 0x2900 /* qemu q35 has 2918 */ |
17a303ec | 2823 | |
f2fbc690 | 2824 | #define INTEL_PCH_TYPE(dev) (__I915__(dev)->pch_type) |
22dea0be | 2825 | #define HAS_PCH_KBP(dev) (INTEL_PCH_TYPE(dev) == PCH_KBP) |
e7e7ea20 | 2826 | #define HAS_PCH_SPT(dev) (INTEL_PCH_TYPE(dev) == PCH_SPT) |
eb877ebf | 2827 | #define HAS_PCH_LPT(dev) (INTEL_PCH_TYPE(dev) == PCH_LPT) |
c2699524 | 2828 | #define HAS_PCH_LPT_LP(dev) (__I915__(dev)->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) |
56f5f700 | 2829 | #define HAS_PCH_LPT_H(dev) (__I915__(dev)->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE) |
cae5852d ZN |
2830 | #define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT) |
2831 | #define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX) | |
40c7ead9 | 2832 | #define HAS_PCH_NOP(dev) (INTEL_PCH_TYPE(dev) == PCH_NOP) |
45e6e3a1 | 2833 | #define HAS_PCH_SPLIT(dev) (INTEL_PCH_TYPE(dev) != PCH_NONE) |
cae5852d | 2834 | |
666a4537 WB |
2835 | #define HAS_GMCH_DISPLAY(dev) (INTEL_INFO(dev)->gen < 5 || \ |
2836 | IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) | |
5fafe292 | 2837 | |
040d2baa BW |
2838 | /* DPF == dynamic parity feature */ |
2839 | #define HAS_L3_DPF(dev) (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) | |
2840 | #define NUM_L3_SLICES(dev) (IS_HSW_GT3(dev) ? 2 : HAS_L3_DPF(dev)) | |
e1ef7cc2 | 2841 | |
c8735b0c | 2842 | #define GT_FREQUENCY_MULTIPLIER 50 |
de43ae9d | 2843 | #define GEN9_FREQ_SCALER 3 |
c8735b0c | 2844 | |
05394f39 CW |
2845 | #include "i915_trace.h" |
2846 | ||
48f112fe CW |
2847 | static inline bool intel_scanout_needs_vtd_wa(struct drm_i915_private *dev_priv) |
2848 | { | |
2849 | #ifdef CONFIG_INTEL_IOMMU | |
2850 | if (INTEL_GEN(dev_priv) >= 6 && intel_iommu_gfx_mapped) | |
2851 | return true; | |
2852 | #endif | |
2853 | return false; | |
2854 | } | |
2855 | ||
1751fcf9 ML |
2856 | extern int i915_suspend_switcheroo(struct drm_device *dev, pm_message_t state); |
2857 | extern int i915_resume_switcheroo(struct drm_device *dev); | |
7c1c2871 | 2858 | |
c033666a | 2859 | int intel_sanitize_enable_ppgtt(struct drm_i915_private *dev_priv, |
351c3b53 | 2860 | int enable_ppgtt); |
0e4ca100 | 2861 | |
39df9190 CW |
2862 | bool intel_sanitize_semaphores(struct drm_i915_private *dev_priv, int value); |
2863 | ||
0673ad47 | 2864 | /* i915_drv.c */ |
d15d7538 ID |
2865 | void __printf(3, 4) |
2866 | __i915_printk(struct drm_i915_private *dev_priv, const char *level, | |
2867 | const char *fmt, ...); | |
2868 | ||
2869 | #define i915_report_error(dev_priv, fmt, ...) \ | |
2870 | __i915_printk(dev_priv, KERN_ERR, fmt, ##__VA_ARGS__) | |
2871 | ||
c43b5634 | 2872 | #ifdef CONFIG_COMPAT |
0d6aa60b DA |
2873 | extern long i915_compat_ioctl(struct file *filp, unsigned int cmd, |
2874 | unsigned long arg); | |
c43b5634 | 2875 | #endif |
dc97997a CW |
2876 | extern int intel_gpu_reset(struct drm_i915_private *dev_priv, u32 engine_mask); |
2877 | extern bool intel_has_gpu_reset(struct drm_i915_private *dev_priv); | |
c033666a | 2878 | extern int i915_reset(struct drm_i915_private *dev_priv); |
6b332fa2 | 2879 | extern int intel_guc_reset(struct drm_i915_private *dev_priv); |
fc0768ce | 2880 | extern void intel_engine_init_hangcheck(struct intel_engine_cs *engine); |
7648fa99 JB |
2881 | extern unsigned long i915_chipset_val(struct drm_i915_private *dev_priv); |
2882 | extern unsigned long i915_mch_val(struct drm_i915_private *dev_priv); | |
2883 | extern unsigned long i915_gfx_val(struct drm_i915_private *dev_priv); | |
2884 | extern void i915_update_gfx_val(struct drm_i915_private *dev_priv); | |
650ad970 | 2885 | int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool on); |
7648fa99 | 2886 | |
77913b39 | 2887 | /* intel_hotplug.c */ |
91d14251 TU |
2888 | void intel_hpd_irq_handler(struct drm_i915_private *dev_priv, |
2889 | u32 pin_mask, u32 long_mask); | |
77913b39 JN |
2890 | void intel_hpd_init(struct drm_i915_private *dev_priv); |
2891 | void intel_hpd_init_work(struct drm_i915_private *dev_priv); | |
2892 | void intel_hpd_cancel_work(struct drm_i915_private *dev_priv); | |
cc24fcdc | 2893 | bool intel_hpd_pin_to_port(enum hpd_pin pin, enum port *port); |
b236d7c8 L |
2894 | bool intel_hpd_disable(struct drm_i915_private *dev_priv, enum hpd_pin pin); |
2895 | void intel_hpd_enable(struct drm_i915_private *dev_priv, enum hpd_pin pin); | |
77913b39 | 2896 | |
1da177e4 | 2897 | /* i915_irq.c */ |
26a02b8f CW |
2898 | static inline void i915_queue_hangcheck(struct drm_i915_private *dev_priv) |
2899 | { | |
2900 | unsigned long delay; | |
2901 | ||
2902 | if (unlikely(!i915.enable_hangcheck)) | |
2903 | return; | |
2904 | ||
2905 | /* Don't continually defer the hangcheck so that it is always run at | |
2906 | * least once after work has been scheduled on any ring. Otherwise, | |
2907 | * we will ignore a hung ring if a second ring is kept busy. | |
2908 | */ | |
2909 | ||
2910 | delay = round_jiffies_up_relative(DRM_I915_HANGCHECK_JIFFIES); | |
2911 | queue_delayed_work(system_long_wq, | |
2912 | &dev_priv->gpu_error.hangcheck_work, delay); | |
2913 | } | |
2914 | ||
58174462 | 2915 | __printf(3, 4) |
c033666a CW |
2916 | void i915_handle_error(struct drm_i915_private *dev_priv, |
2917 | u32 engine_mask, | |
58174462 | 2918 | const char *fmt, ...); |
1da177e4 | 2919 | |
b963291c | 2920 | extern void intel_irq_init(struct drm_i915_private *dev_priv); |
2aeb7d3a DV |
2921 | int intel_irq_install(struct drm_i915_private *dev_priv); |
2922 | void intel_irq_uninstall(struct drm_i915_private *dev_priv); | |
907b28c5 | 2923 | |
dc97997a CW |
2924 | extern void intel_uncore_sanitize(struct drm_i915_private *dev_priv); |
2925 | extern void intel_uncore_early_sanitize(struct drm_i915_private *dev_priv, | |
10018603 | 2926 | bool restore_forcewake); |
dc97997a | 2927 | extern void intel_uncore_init(struct drm_i915_private *dev_priv); |
fc97618b | 2928 | extern bool intel_uncore_unclaimed_mmio(struct drm_i915_private *dev_priv); |
bc3b9346 | 2929 | extern bool intel_uncore_arm_unclaimed_mmio_detection(struct drm_i915_private *dev_priv); |
dc97997a CW |
2930 | extern void intel_uncore_fini(struct drm_i915_private *dev_priv); |
2931 | extern void intel_uncore_forcewake_reset(struct drm_i915_private *dev_priv, | |
2932 | bool restore); | |
48c1026a | 2933 | const char *intel_uncore_forcewake_domain_to_str(const enum forcewake_domain_id id); |
59bad947 | 2934 | void intel_uncore_forcewake_get(struct drm_i915_private *dev_priv, |
48c1026a | 2935 | enum forcewake_domains domains); |
59bad947 | 2936 | void intel_uncore_forcewake_put(struct drm_i915_private *dev_priv, |
48c1026a | 2937 | enum forcewake_domains domains); |
a6111f7b CW |
2938 | /* Like above but the caller must manage the uncore.lock itself. |
2939 | * Must be used with I915_READ_FW and friends. | |
2940 | */ | |
2941 | void intel_uncore_forcewake_get__locked(struct drm_i915_private *dev_priv, | |
2942 | enum forcewake_domains domains); | |
2943 | void intel_uncore_forcewake_put__locked(struct drm_i915_private *dev_priv, | |
2944 | enum forcewake_domains domains); | |
3accaf7e MK |
2945 | u64 intel_uncore_edram_size(struct drm_i915_private *dev_priv); |
2946 | ||
59bad947 | 2947 | void assert_forcewakes_inactive(struct drm_i915_private *dev_priv); |
0ad35fed | 2948 | |
1758b90e CW |
2949 | int intel_wait_for_register(struct drm_i915_private *dev_priv, |
2950 | i915_reg_t reg, | |
2951 | const u32 mask, | |
2952 | const u32 value, | |
2953 | const unsigned long timeout_ms); | |
2954 | int intel_wait_for_register_fw(struct drm_i915_private *dev_priv, | |
2955 | i915_reg_t reg, | |
2956 | const u32 mask, | |
2957 | const u32 value, | |
2958 | const unsigned long timeout_ms); | |
2959 | ||
0ad35fed ZW |
2960 | static inline bool intel_gvt_active(struct drm_i915_private *dev_priv) |
2961 | { | |
2962 | return dev_priv->gvt.initialized; | |
2963 | } | |
2964 | ||
c033666a | 2965 | static inline bool intel_vgpu_active(struct drm_i915_private *dev_priv) |
cf9d2890 | 2966 | { |
c033666a | 2967 | return dev_priv->vgpu.active; |
cf9d2890 | 2968 | } |
b1f14ad0 | 2969 | |
7c463586 | 2970 | void |
50227e1c | 2971 | i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe, |
755e9019 | 2972 | u32 status_mask); |
7c463586 KP |
2973 | |
2974 | void | |
50227e1c | 2975 | i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe, |
755e9019 | 2976 | u32 status_mask); |
7c463586 | 2977 | |
f8b79e58 ID |
2978 | void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv); |
2979 | void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv); | |
0706f17c EE |
2980 | void i915_hotplug_interrupt_update(struct drm_i915_private *dev_priv, |
2981 | uint32_t mask, | |
2982 | uint32_t bits); | |
fbdedaea VS |
2983 | void ilk_update_display_irq(struct drm_i915_private *dev_priv, |
2984 | uint32_t interrupt_mask, | |
2985 | uint32_t enabled_irq_mask); | |
2986 | static inline void | |
2987 | ilk_enable_display_irq(struct drm_i915_private *dev_priv, uint32_t bits) | |
2988 | { | |
2989 | ilk_update_display_irq(dev_priv, bits, bits); | |
2990 | } | |
2991 | static inline void | |
2992 | ilk_disable_display_irq(struct drm_i915_private *dev_priv, uint32_t bits) | |
2993 | { | |
2994 | ilk_update_display_irq(dev_priv, bits, 0); | |
2995 | } | |
013d3752 VS |
2996 | void bdw_update_pipe_irq(struct drm_i915_private *dev_priv, |
2997 | enum pipe pipe, | |
2998 | uint32_t interrupt_mask, | |
2999 | uint32_t enabled_irq_mask); | |
3000 | static inline void bdw_enable_pipe_irq(struct drm_i915_private *dev_priv, | |
3001 | enum pipe pipe, uint32_t bits) | |
3002 | { | |
3003 | bdw_update_pipe_irq(dev_priv, pipe, bits, bits); | |
3004 | } | |
3005 | static inline void bdw_disable_pipe_irq(struct drm_i915_private *dev_priv, | |
3006 | enum pipe pipe, uint32_t bits) | |
3007 | { | |
3008 | bdw_update_pipe_irq(dev_priv, pipe, bits, 0); | |
3009 | } | |
47339cd9 DV |
3010 | void ibx_display_interrupt_update(struct drm_i915_private *dev_priv, |
3011 | uint32_t interrupt_mask, | |
3012 | uint32_t enabled_irq_mask); | |
14443261 VS |
3013 | static inline void |
3014 | ibx_enable_display_interrupt(struct drm_i915_private *dev_priv, uint32_t bits) | |
3015 | { | |
3016 | ibx_display_interrupt_update(dev_priv, bits, bits); | |
3017 | } | |
3018 | static inline void | |
3019 | ibx_disable_display_interrupt(struct drm_i915_private *dev_priv, uint32_t bits) | |
3020 | { | |
3021 | ibx_display_interrupt_update(dev_priv, bits, 0); | |
3022 | } | |
3023 | ||
673a394b | 3024 | /* i915_gem.c */ |
673a394b EA |
3025 | int i915_gem_create_ioctl(struct drm_device *dev, void *data, |
3026 | struct drm_file *file_priv); | |
3027 | int i915_gem_pread_ioctl(struct drm_device *dev, void *data, | |
3028 | struct drm_file *file_priv); | |
3029 | int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data, | |
3030 | struct drm_file *file_priv); | |
3031 | int i915_gem_mmap_ioctl(struct drm_device *dev, void *data, | |
3032 | struct drm_file *file_priv); | |
de151cf6 JB |
3033 | int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data, |
3034 | struct drm_file *file_priv); | |
673a394b EA |
3035 | int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data, |
3036 | struct drm_file *file_priv); | |
3037 | int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data, | |
3038 | struct drm_file *file_priv); | |
3039 | int i915_gem_execbuffer(struct drm_device *dev, void *data, | |
3040 | struct drm_file *file_priv); | |
76446cac JB |
3041 | int i915_gem_execbuffer2(struct drm_device *dev, void *data, |
3042 | struct drm_file *file_priv); | |
673a394b EA |
3043 | int i915_gem_busy_ioctl(struct drm_device *dev, void *data, |
3044 | struct drm_file *file_priv); | |
199adf40 BW |
3045 | int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data, |
3046 | struct drm_file *file); | |
3047 | int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data, | |
3048 | struct drm_file *file); | |
673a394b EA |
3049 | int i915_gem_throttle_ioctl(struct drm_device *dev, void *data, |
3050 | struct drm_file *file_priv); | |
3ef94daa CW |
3051 | int i915_gem_madvise_ioctl(struct drm_device *dev, void *data, |
3052 | struct drm_file *file_priv); | |
673a394b EA |
3053 | int i915_gem_set_tiling(struct drm_device *dev, void *data, |
3054 | struct drm_file *file_priv); | |
3055 | int i915_gem_get_tiling(struct drm_device *dev, void *data, | |
3056 | struct drm_file *file_priv); | |
72778cb2 | 3057 | void i915_gem_init_userptr(struct drm_i915_private *dev_priv); |
5cc9ed4b CW |
3058 | int i915_gem_userptr_ioctl(struct drm_device *dev, void *data, |
3059 | struct drm_file *file); | |
5a125c3c EA |
3060 | int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data, |
3061 | struct drm_file *file_priv); | |
23ba4fd0 BW |
3062 | int i915_gem_wait_ioctl(struct drm_device *dev, void *data, |
3063 | struct drm_file *file_priv); | |
d64aa096 ID |
3064 | void i915_gem_load_init(struct drm_device *dev); |
3065 | void i915_gem_load_cleanup(struct drm_device *dev); | |
40ae4e16 | 3066 | void i915_gem_load_init_fences(struct drm_i915_private *dev_priv); |
461fb99c CW |
3067 | int i915_gem_freeze_late(struct drm_i915_private *dev_priv); |
3068 | ||
42dcedd4 CW |
3069 | void *i915_gem_object_alloc(struct drm_device *dev); |
3070 | void i915_gem_object_free(struct drm_i915_gem_object *obj); | |
37e680a1 CW |
3071 | void i915_gem_object_init(struct drm_i915_gem_object *obj, |
3072 | const struct drm_i915_gem_object_ops *ops); | |
d37cd8a8 | 3073 | struct drm_i915_gem_object *i915_gem_object_create(struct drm_device *dev, |
05394f39 | 3074 | size_t size); |
ea70299d DG |
3075 | struct drm_i915_gem_object *i915_gem_object_create_from_data( |
3076 | struct drm_device *dev, const void *data, size_t size); | |
b1f788c6 | 3077 | void i915_gem_close_object(struct drm_gem_object *gem, struct drm_file *file); |
673a394b | 3078 | void i915_gem_free_object(struct drm_gem_object *obj); |
42dcedd4 | 3079 | |
058d88c4 | 3080 | struct i915_vma * __must_check |
ec7adb6e JL |
3081 | i915_gem_object_ggtt_pin(struct drm_i915_gem_object *obj, |
3082 | const struct i915_ggtt_view *view, | |
91b2db6f | 3083 | u64 size, |
2ffffd0f CW |
3084 | u64 alignment, |
3085 | u64 flags); | |
fe14d5f4 TU |
3086 | |
3087 | int i915_vma_bind(struct i915_vma *vma, enum i915_cache_level cache_level, | |
3088 | u32 flags); | |
d0710abb | 3089 | void __i915_vma_set_map_and_fenceable(struct i915_vma *vma); |
07fe0b12 | 3090 | int __must_check i915_vma_unbind(struct i915_vma *vma); |
b1f788c6 CW |
3091 | void i915_vma_close(struct i915_vma *vma); |
3092 | void i915_vma_destroy(struct i915_vma *vma); | |
aa653a68 CW |
3093 | |
3094 | int i915_gem_object_unbind(struct drm_i915_gem_object *obj); | |
dd624afd | 3095 | int i915_gem_object_put_pages(struct drm_i915_gem_object *obj); |
48018a57 | 3096 | void i915_gem_release_all_mmaps(struct drm_i915_private *dev_priv); |
05394f39 | 3097 | void i915_gem_release_mmap(struct drm_i915_gem_object *obj); |
f787a5f5 | 3098 | |
37e680a1 | 3099 | int __must_check i915_gem_object_get_pages(struct drm_i915_gem_object *obj); |
ee286370 CW |
3100 | |
3101 | static inline int __sg_page_count(struct scatterlist *sg) | |
9da3da66 | 3102 | { |
ee286370 CW |
3103 | return sg->length >> PAGE_SHIFT; |
3104 | } | |
67d5a50c | 3105 | |
033908ae DG |
3106 | struct page * |
3107 | i915_gem_object_get_dirty_page(struct drm_i915_gem_object *obj, int n); | |
3108 | ||
341be1cd CW |
3109 | static inline dma_addr_t |
3110 | i915_gem_object_get_dma_address(struct drm_i915_gem_object *obj, int n) | |
3111 | { | |
3112 | if (n < obj->get_page.last) { | |
3113 | obj->get_page.sg = obj->pages->sgl; | |
3114 | obj->get_page.last = 0; | |
3115 | } | |
3116 | ||
3117 | while (obj->get_page.last + __sg_page_count(obj->get_page.sg) <= n) { | |
3118 | obj->get_page.last += __sg_page_count(obj->get_page.sg++); | |
3119 | if (unlikely(sg_is_chain(obj->get_page.sg))) | |
3120 | obj->get_page.sg = sg_chain_ptr(obj->get_page.sg); | |
3121 | } | |
3122 | ||
3123 | return sg_dma_address(obj->get_page.sg) + ((n - obj->get_page.last) << PAGE_SHIFT); | |
3124 | } | |
3125 | ||
ee286370 CW |
3126 | static inline struct page * |
3127 | i915_gem_object_get_page(struct drm_i915_gem_object *obj, int n) | |
9da3da66 | 3128 | { |
ee286370 CW |
3129 | if (WARN_ON(n >= obj->base.size >> PAGE_SHIFT)) |
3130 | return NULL; | |
67d5a50c | 3131 | |
ee286370 CW |
3132 | if (n < obj->get_page.last) { |
3133 | obj->get_page.sg = obj->pages->sgl; | |
3134 | obj->get_page.last = 0; | |
3135 | } | |
67d5a50c | 3136 | |
ee286370 CW |
3137 | while (obj->get_page.last + __sg_page_count(obj->get_page.sg) <= n) { |
3138 | obj->get_page.last += __sg_page_count(obj->get_page.sg++); | |
3139 | if (unlikely(sg_is_chain(obj->get_page.sg))) | |
3140 | obj->get_page.sg = sg_chain_ptr(obj->get_page.sg); | |
3141 | } | |
67d5a50c | 3142 | |
ee286370 | 3143 | return nth_page(sg_page(obj->get_page.sg), n - obj->get_page.last); |
9da3da66 | 3144 | } |
ee286370 | 3145 | |
a5570178 CW |
3146 | static inline void i915_gem_object_pin_pages(struct drm_i915_gem_object *obj) |
3147 | { | |
3148 | BUG_ON(obj->pages == NULL); | |
3149 | obj->pages_pin_count++; | |
3150 | } | |
0a798eb9 | 3151 | |
a5570178 CW |
3152 | static inline void i915_gem_object_unpin_pages(struct drm_i915_gem_object *obj) |
3153 | { | |
3154 | BUG_ON(obj->pages_pin_count == 0); | |
3155 | obj->pages_pin_count--; | |
3156 | } | |
3157 | ||
d31d7cb1 CW |
3158 | enum i915_map_type { |
3159 | I915_MAP_WB = 0, | |
3160 | I915_MAP_WC, | |
3161 | }; | |
3162 | ||
0a798eb9 CW |
3163 | /** |
3164 | * i915_gem_object_pin_map - return a contiguous mapping of the entire object | |
3165 | * @obj - the object to map into kernel address space | |
d31d7cb1 | 3166 | * @type - the type of mapping, used to select pgprot_t |
0a798eb9 CW |
3167 | * |
3168 | * Calls i915_gem_object_pin_pages() to prevent reaping of the object's | |
3169 | * pages and then returns a contiguous mapping of the backing storage into | |
d31d7cb1 CW |
3170 | * the kernel address space. Based on the @type of mapping, the PTE will be |
3171 | * set to either WriteBack or WriteCombine (via pgprot_t). | |
0a798eb9 | 3172 | * |
8305216f DG |
3173 | * The caller must hold the struct_mutex, and is responsible for calling |
3174 | * i915_gem_object_unpin_map() when the mapping is no longer required. | |
0a798eb9 | 3175 | * |
8305216f DG |
3176 | * Returns the pointer through which to access the mapped object, or an |
3177 | * ERR_PTR() on error. | |
0a798eb9 | 3178 | */ |
d31d7cb1 CW |
3179 | void *__must_check i915_gem_object_pin_map(struct drm_i915_gem_object *obj, |
3180 | enum i915_map_type type); | |
0a798eb9 CW |
3181 | |
3182 | /** | |
3183 | * i915_gem_object_unpin_map - releases an earlier mapping | |
3184 | * @obj - the object to unmap | |
3185 | * | |
3186 | * After pinning the object and mapping its pages, once you are finished | |
3187 | * with your access, call i915_gem_object_unpin_map() to release the pin | |
3188 | * upon the mapping. Once the pin count reaches zero, that mapping may be | |
3189 | * removed. | |
3190 | * | |
3191 | * The caller must hold the struct_mutex. | |
3192 | */ | |
3193 | static inline void i915_gem_object_unpin_map(struct drm_i915_gem_object *obj) | |
3194 | { | |
3195 | lockdep_assert_held(&obj->base.dev->struct_mutex); | |
3196 | i915_gem_object_unpin_pages(obj); | |
3197 | } | |
3198 | ||
43394c7d CW |
3199 | int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object *obj, |
3200 | unsigned int *needs_clflush); | |
3201 | int i915_gem_obj_prepare_shmem_write(struct drm_i915_gem_object *obj, | |
3202 | unsigned int *needs_clflush); | |
3203 | #define CLFLUSH_BEFORE 0x1 | |
3204 | #define CLFLUSH_AFTER 0x2 | |
3205 | #define CLFLUSH_FLAGS (CLFLUSH_BEFORE | CLFLUSH_AFTER) | |
3206 | ||
3207 | static inline void | |
3208 | i915_gem_obj_finish_shmem_access(struct drm_i915_gem_object *obj) | |
3209 | { | |
3210 | i915_gem_object_unpin_pages(obj); | |
3211 | } | |
3212 | ||
54cf91dc | 3213 | int __must_check i915_mutex_lock_interruptible(struct drm_device *dev); |
2911a35b | 3214 | int i915_gem_object_sync(struct drm_i915_gem_object *obj, |
8e637178 | 3215 | struct drm_i915_gem_request *to); |
e2d05a8b | 3216 | void i915_vma_move_to_active(struct i915_vma *vma, |
5cf3d280 CW |
3217 | struct drm_i915_gem_request *req, |
3218 | unsigned int flags); | |
ff72145b DA |
3219 | int i915_gem_dumb_create(struct drm_file *file_priv, |
3220 | struct drm_device *dev, | |
3221 | struct drm_mode_create_dumb *args); | |
da6b51d0 DA |
3222 | int i915_gem_mmap_gtt(struct drm_file *file_priv, struct drm_device *dev, |
3223 | uint32_t handle, uint64_t *offset); | |
4cc69075 | 3224 | int i915_gem_mmap_gtt_version(void); |
85d1225e DG |
3225 | |
3226 | void i915_gem_track_fb(struct drm_i915_gem_object *old, | |
3227 | struct drm_i915_gem_object *new, | |
3228 | unsigned frontbuffer_bits); | |
3229 | ||
fca26bb4 | 3230 | int __must_check i915_gem_set_seqno(struct drm_device *dev, u32 seqno); |
1690e1eb | 3231 | |
8d9fc7fd | 3232 | struct drm_i915_gem_request * |
0bc40be8 | 3233 | i915_gem_find_active_request(struct intel_engine_cs *engine); |
8d9fc7fd | 3234 | |
67d97da3 | 3235 | void i915_gem_retire_requests(struct drm_i915_private *dev_priv); |
84c33a64 | 3236 | |
c19ae989 CW |
3237 | static inline u32 i915_reset_counter(struct i915_gpu_error *error) |
3238 | { | |
3239 | return atomic_read(&error->reset_counter); | |
3240 | } | |
3241 | ||
3242 | static inline bool __i915_reset_in_progress(u32 reset) | |
3243 | { | |
3244 | return unlikely(reset & I915_RESET_IN_PROGRESS_FLAG); | |
3245 | } | |
3246 | ||
3247 | static inline bool __i915_reset_in_progress_or_wedged(u32 reset) | |
3248 | { | |
3249 | return unlikely(reset & (I915_RESET_IN_PROGRESS_FLAG | I915_WEDGED)); | |
3250 | } | |
3251 | ||
3252 | static inline bool __i915_terminally_wedged(u32 reset) | |
3253 | { | |
3254 | return unlikely(reset & I915_WEDGED); | |
3255 | } | |
3256 | ||
1f83fee0 DV |
3257 | static inline bool i915_reset_in_progress(struct i915_gpu_error *error) |
3258 | { | |
c19ae989 CW |
3259 | return __i915_reset_in_progress(i915_reset_counter(error)); |
3260 | } | |
3261 | ||
3262 | static inline bool i915_reset_in_progress_or_wedged(struct i915_gpu_error *error) | |
3263 | { | |
3264 | return __i915_reset_in_progress_or_wedged(i915_reset_counter(error)); | |
1f83fee0 DV |
3265 | } |
3266 | ||
3267 | static inline bool i915_terminally_wedged(struct i915_gpu_error *error) | |
3268 | { | |
c19ae989 | 3269 | return __i915_terminally_wedged(i915_reset_counter(error)); |
2ac0f450 MK |
3270 | } |
3271 | ||
3272 | static inline u32 i915_reset_count(struct i915_gpu_error *error) | |
3273 | { | |
c19ae989 | 3274 | return ((i915_reset_counter(error) & ~I915_WEDGED) + 1) / 2; |
1f83fee0 | 3275 | } |
a71d8d94 | 3276 | |
069efc1d | 3277 | void i915_gem_reset(struct drm_device *dev); |
000433b6 | 3278 | bool i915_gem_clflush_object(struct drm_i915_gem_object *obj, bool force); |
1070a42b | 3279 | int __must_check i915_gem_init(struct drm_device *dev); |
f691e2f4 DV |
3280 | int __must_check i915_gem_init_hw(struct drm_device *dev); |
3281 | void i915_gem_init_swizzling(struct drm_device *dev); | |
117897f4 | 3282 | void i915_gem_cleanup_engines(struct drm_device *dev); |
dcff85c8 CW |
3283 | int __must_check i915_gem_wait_for_idle(struct drm_i915_private *dev_priv, |
3284 | bool interruptible); | |
45c5f202 | 3285 | int __must_check i915_gem_suspend(struct drm_device *dev); |
5ab57c70 | 3286 | void i915_gem_resume(struct drm_device *dev); |
de151cf6 | 3287 | int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf); |
2021746e | 3288 | int __must_check |
2e2f351d CW |
3289 | i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj, |
3290 | bool readonly); | |
3291 | int __must_check | |
2021746e CW |
3292 | i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, |
3293 | bool write); | |
3294 | int __must_check | |
dabdfe02 | 3295 | i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write); |
058d88c4 | 3296 | struct i915_vma * __must_check |
2da3b9b9 CW |
3297 | i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj, |
3298 | u32 alignment, | |
e6617330 | 3299 | const struct i915_ggtt_view *view); |
058d88c4 | 3300 | void i915_gem_object_unpin_from_display_plane(struct i915_vma *vma); |
00731155 | 3301 | int i915_gem_object_attach_phys(struct drm_i915_gem_object *obj, |
6eeefaf3 | 3302 | int align); |
b29c19b6 | 3303 | int i915_gem_open(struct drm_device *dev, struct drm_file *file); |
05394f39 | 3304 | void i915_gem_release(struct drm_device *dev, struct drm_file *file); |
673a394b | 3305 | |
a9f1481f CW |
3306 | u64 i915_gem_get_ggtt_size(struct drm_i915_private *dev_priv, u64 size, |
3307 | int tiling_mode); | |
3308 | u64 i915_gem_get_ggtt_alignment(struct drm_i915_private *dev_priv, u64 size, | |
ad1a7d20 | 3309 | int tiling_mode, bool fenced); |
467cffba | 3310 | |
e4ffd173 CW |
3311 | int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj, |
3312 | enum i915_cache_level cache_level); | |
3313 | ||
1286ff73 DV |
3314 | struct drm_gem_object *i915_gem_prime_import(struct drm_device *dev, |
3315 | struct dma_buf *dma_buf); | |
3316 | ||
3317 | struct dma_buf *i915_gem_prime_export(struct drm_device *dev, | |
3318 | struct drm_gem_object *gem_obj, int flags); | |
3319 | ||
fe14d5f4 | 3320 | struct i915_vma * |
ec7adb6e | 3321 | i915_gem_obj_to_vma(struct drm_i915_gem_object *obj, |
058d88c4 CW |
3322 | struct i915_address_space *vm, |
3323 | const struct i915_ggtt_view *view); | |
fe14d5f4 | 3324 | |
accfef2e BW |
3325 | struct i915_vma * |
3326 | i915_gem_obj_lookup_or_create_vma(struct drm_i915_gem_object *obj, | |
058d88c4 CW |
3327 | struct i915_address_space *vm, |
3328 | const struct i915_ggtt_view *view); | |
5c2abbea | 3329 | |
841cd773 DV |
3330 | static inline struct i915_hw_ppgtt * |
3331 | i915_vm_to_ppgtt(struct i915_address_space *vm) | |
3332 | { | |
841cd773 DV |
3333 | return container_of(vm, struct i915_hw_ppgtt, base); |
3334 | } | |
3335 | ||
058d88c4 CW |
3336 | static inline struct i915_vma * |
3337 | i915_gem_object_to_ggtt(struct drm_i915_gem_object *obj, | |
3338 | const struct i915_ggtt_view *view) | |
a70a3148 | 3339 | { |
058d88c4 | 3340 | return i915_gem_obj_to_vma(obj, &to_i915(obj->base.dev)->ggtt.base, view); |
a70a3148 BW |
3341 | } |
3342 | ||
058d88c4 CW |
3343 | static inline unsigned long |
3344 | i915_gem_object_ggtt_offset(struct drm_i915_gem_object *o, | |
3345 | const struct i915_ggtt_view *view) | |
e6617330 | 3346 | { |
bde13ebd | 3347 | return i915_ggtt_offset(i915_gem_object_to_ggtt(o, view)); |
e6617330 | 3348 | } |
b287110e | 3349 | |
41a36b73 | 3350 | /* i915_gem_fence.c */ |
49ef5294 CW |
3351 | int __must_check i915_vma_get_fence(struct i915_vma *vma); |
3352 | int __must_check i915_vma_put_fence(struct i915_vma *vma); | |
3353 | ||
3354 | /** | |
3355 | * i915_vma_pin_fence - pin fencing state | |
3356 | * @vma: vma to pin fencing for | |
3357 | * | |
3358 | * This pins the fencing state (whether tiled or untiled) to make sure the | |
3359 | * vma (and its object) is ready to be used as a scanout target. Fencing | |
3360 | * status must be synchronize first by calling i915_vma_get_fence(): | |
3361 | * | |
3362 | * The resulting fence pin reference must be released again with | |
3363 | * i915_vma_unpin_fence(). | |
3364 | * | |
3365 | * Returns: | |
3366 | * | |
3367 | * True if the vma has a fence, false otherwise. | |
3368 | */ | |
3369 | static inline bool | |
3370 | i915_vma_pin_fence(struct i915_vma *vma) | |
3371 | { | |
3372 | if (vma->fence) { | |
3373 | vma->fence->pin_count++; | |
3374 | return true; | |
3375 | } else | |
3376 | return false; | |
3377 | } | |
41a36b73 | 3378 | |
49ef5294 CW |
3379 | /** |
3380 | * i915_vma_unpin_fence - unpin fencing state | |
3381 | * @vma: vma to unpin fencing for | |
3382 | * | |
3383 | * This releases the fence pin reference acquired through | |
3384 | * i915_vma_pin_fence. It will handle both objects with and without an | |
3385 | * attached fence correctly, callers do not need to distinguish this. | |
3386 | */ | |
3387 | static inline void | |
3388 | i915_vma_unpin_fence(struct i915_vma *vma) | |
3389 | { | |
3390 | if (vma->fence) { | |
3391 | GEM_BUG_ON(vma->fence->pin_count <= 0); | |
3392 | vma->fence->pin_count--; | |
3393 | } | |
3394 | } | |
41a36b73 DV |
3395 | |
3396 | void i915_gem_restore_fences(struct drm_device *dev); | |
3397 | ||
7f96ecaf DV |
3398 | void i915_gem_detect_bit_6_swizzle(struct drm_device *dev); |
3399 | void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj); | |
3400 | void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj); | |
3401 | ||
254f965c | 3402 | /* i915_gem_context.c */ |
8245be31 | 3403 | int __must_check i915_gem_context_init(struct drm_device *dev); |
b2e862d0 | 3404 | void i915_gem_context_lost(struct drm_i915_private *dev_priv); |
254f965c | 3405 | void i915_gem_context_fini(struct drm_device *dev); |
acce9ffa | 3406 | void i915_gem_context_reset(struct drm_device *dev); |
e422b888 | 3407 | int i915_gem_context_open(struct drm_device *dev, struct drm_file *file); |
254f965c | 3408 | void i915_gem_context_close(struct drm_device *dev, struct drm_file *file); |
ba01cc93 | 3409 | int i915_switch_context(struct drm_i915_gem_request *req); |
945657b4 | 3410 | int i915_gem_switch_to_kernel_context(struct drm_i915_private *dev_priv); |
dce3271b | 3411 | void i915_gem_context_free(struct kref *ctx_ref); |
8c857917 OM |
3412 | struct drm_i915_gem_object * |
3413 | i915_gem_alloc_context_obj(struct drm_device *dev, size_t size); | |
c8c35799 ZW |
3414 | struct i915_gem_context * |
3415 | i915_gem_context_create_gvt(struct drm_device *dev); | |
ca585b5d CW |
3416 | |
3417 | static inline struct i915_gem_context * | |
3418 | i915_gem_context_lookup(struct drm_i915_file_private *file_priv, u32 id) | |
3419 | { | |
3420 | struct i915_gem_context *ctx; | |
3421 | ||
091387c1 | 3422 | lockdep_assert_held(&file_priv->dev_priv->drm.struct_mutex); |
ca585b5d CW |
3423 | |
3424 | ctx = idr_find(&file_priv->context_idr, id); | |
3425 | if (!ctx) | |
3426 | return ERR_PTR(-ENOENT); | |
3427 | ||
3428 | return ctx; | |
3429 | } | |
3430 | ||
9a6feaf0 CW |
3431 | static inline struct i915_gem_context * |
3432 | i915_gem_context_get(struct i915_gem_context *ctx) | |
dce3271b | 3433 | { |
691e6415 | 3434 | kref_get(&ctx->ref); |
9a6feaf0 | 3435 | return ctx; |
dce3271b MK |
3436 | } |
3437 | ||
9a6feaf0 | 3438 | static inline void i915_gem_context_put(struct i915_gem_context *ctx) |
dce3271b | 3439 | { |
091387c1 | 3440 | lockdep_assert_held(&ctx->i915->drm.struct_mutex); |
691e6415 | 3441 | kref_put(&ctx->ref, i915_gem_context_free); |
dce3271b MK |
3442 | } |
3443 | ||
e2efd130 | 3444 | static inline bool i915_gem_context_is_default(const struct i915_gem_context *c) |
3fac8978 | 3445 | { |
821d66dd | 3446 | return c->user_handle == DEFAULT_CONTEXT_HANDLE; |
3fac8978 MK |
3447 | } |
3448 | ||
84624813 BW |
3449 | int i915_gem_context_create_ioctl(struct drm_device *dev, void *data, |
3450 | struct drm_file *file); | |
3451 | int i915_gem_context_destroy_ioctl(struct drm_device *dev, void *data, | |
3452 | struct drm_file *file); | |
c9dc0f35 CW |
3453 | int i915_gem_context_getparam_ioctl(struct drm_device *dev, void *data, |
3454 | struct drm_file *file_priv); | |
3455 | int i915_gem_context_setparam_ioctl(struct drm_device *dev, void *data, | |
3456 | struct drm_file *file_priv); | |
d538704b CW |
3457 | int i915_gem_context_reset_stats_ioctl(struct drm_device *dev, void *data, |
3458 | struct drm_file *file); | |
1286ff73 | 3459 | |
679845ed | 3460 | /* i915_gem_evict.c */ |
e522ac23 | 3461 | int __must_check i915_gem_evict_something(struct i915_address_space *vm, |
2ffffd0f | 3462 | u64 min_size, u64 alignment, |
679845ed | 3463 | unsigned cache_level, |
2ffffd0f | 3464 | u64 start, u64 end, |
1ec9e26d | 3465 | unsigned flags); |
506a8e87 | 3466 | int __must_check i915_gem_evict_for_vma(struct i915_vma *target); |
679845ed | 3467 | int i915_gem_evict_vm(struct i915_address_space *vm, bool do_idle); |
1d2a314c | 3468 | |
0260c420 | 3469 | /* belongs in i915_gem_gtt.h */ |
c033666a | 3470 | static inline void i915_gem_chipset_flush(struct drm_i915_private *dev_priv) |
e76e9aeb | 3471 | { |
600f4368 | 3472 | wmb(); |
c033666a | 3473 | if (INTEL_GEN(dev_priv) < 6) |
e76e9aeb BW |
3474 | intel_gtt_chipset_flush(); |
3475 | } | |
246cbfb5 | 3476 | |
9797fbfb | 3477 | /* i915_gem_stolen.c */ |
d713fd49 PZ |
3478 | int i915_gem_stolen_insert_node(struct drm_i915_private *dev_priv, |
3479 | struct drm_mm_node *node, u64 size, | |
3480 | unsigned alignment); | |
a9da512b PZ |
3481 | int i915_gem_stolen_insert_node_in_range(struct drm_i915_private *dev_priv, |
3482 | struct drm_mm_node *node, u64 size, | |
3483 | unsigned alignment, u64 start, | |
3484 | u64 end); | |
d713fd49 PZ |
3485 | void i915_gem_stolen_remove_node(struct drm_i915_private *dev_priv, |
3486 | struct drm_mm_node *node); | |
9797fbfb CW |
3487 | int i915_gem_init_stolen(struct drm_device *dev); |
3488 | void i915_gem_cleanup_stolen(struct drm_device *dev); | |
0104fdbb CW |
3489 | struct drm_i915_gem_object * |
3490 | i915_gem_object_create_stolen(struct drm_device *dev, u32 size); | |
866d12b4 CW |
3491 | struct drm_i915_gem_object * |
3492 | i915_gem_object_create_stolen_for_preallocated(struct drm_device *dev, | |
3493 | u32 stolen_offset, | |
3494 | u32 gtt_offset, | |
3495 | u32 size); | |
9797fbfb | 3496 | |
be6a0376 DV |
3497 | /* i915_gem_shrinker.c */ |
3498 | unsigned long i915_gem_shrink(struct drm_i915_private *dev_priv, | |
14387540 | 3499 | unsigned long target, |
be6a0376 DV |
3500 | unsigned flags); |
3501 | #define I915_SHRINK_PURGEABLE 0x1 | |
3502 | #define I915_SHRINK_UNBOUND 0x2 | |
3503 | #define I915_SHRINK_BOUND 0x4 | |
5763ff04 | 3504 | #define I915_SHRINK_ACTIVE 0x8 |
eae2c43b | 3505 | #define I915_SHRINK_VMAPS 0x10 |
be6a0376 DV |
3506 | unsigned long i915_gem_shrink_all(struct drm_i915_private *dev_priv); |
3507 | void i915_gem_shrinker_init(struct drm_i915_private *dev_priv); | |
a8a40589 | 3508 | void i915_gem_shrinker_cleanup(struct drm_i915_private *dev_priv); |
be6a0376 DV |
3509 | |
3510 | ||
673a394b | 3511 | /* i915_gem_tiling.c */ |
2c1792a1 | 3512 | static inline bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj) |
e9b73c67 | 3513 | { |
091387c1 | 3514 | struct drm_i915_private *dev_priv = to_i915(obj->base.dev); |
e9b73c67 CW |
3515 | |
3516 | return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 && | |
3e510a8e | 3517 | i915_gem_object_is_tiled(obj); |
e9b73c67 CW |
3518 | } |
3519 | ||
2017263e | 3520 | /* i915_debugfs.c */ |
f8c168fa | 3521 | #ifdef CONFIG_DEBUG_FS |
1dac891c CW |
3522 | int i915_debugfs_register(struct drm_i915_private *dev_priv); |
3523 | void i915_debugfs_unregister(struct drm_i915_private *dev_priv); | |
249e87de | 3524 | int i915_debugfs_connector_add(struct drm_connector *connector); |
36cdd013 | 3525 | void intel_display_crc_init(struct drm_i915_private *dev_priv); |
07144428 | 3526 | #else |
8d35acba CW |
3527 | static inline int i915_debugfs_register(struct drm_i915_private *dev_priv) {return 0;} |
3528 | static inline void i915_debugfs_unregister(struct drm_i915_private *dev_priv) {} | |
101057fa DV |
3529 | static inline int i915_debugfs_connector_add(struct drm_connector *connector) |
3530 | { return 0; } | |
ce5e2ac1 | 3531 | static inline void intel_display_crc_init(struct drm_i915_private *dev_priv) {} |
07144428 | 3532 | #endif |
84734a04 MK |
3533 | |
3534 | /* i915_gpu_error.c */ | |
edc3d884 MK |
3535 | __printf(2, 3) |
3536 | void i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...); | |
fc16b48b MK |
3537 | int i915_error_state_to_str(struct drm_i915_error_state_buf *estr, |
3538 | const struct i915_error_state_file_priv *error); | |
4dc955f7 | 3539 | int i915_error_state_buf_init(struct drm_i915_error_state_buf *eb, |
0a4cd7c8 | 3540 | struct drm_i915_private *i915, |
4dc955f7 MK |
3541 | size_t count, loff_t pos); |
3542 | static inline void i915_error_state_buf_release( | |
3543 | struct drm_i915_error_state_buf *eb) | |
3544 | { | |
3545 | kfree(eb->buf); | |
3546 | } | |
c033666a CW |
3547 | void i915_capture_error_state(struct drm_i915_private *dev_priv, |
3548 | u32 engine_mask, | |
58174462 | 3549 | const char *error_msg); |
84734a04 MK |
3550 | void i915_error_state_get(struct drm_device *dev, |
3551 | struct i915_error_state_file_priv *error_priv); | |
3552 | void i915_error_state_put(struct i915_error_state_file_priv *error_priv); | |
3553 | void i915_destroy_error_state(struct drm_device *dev); | |
3554 | ||
c033666a | 3555 | void i915_get_extra_instdone(struct drm_i915_private *dev_priv, uint32_t *instdone); |
0a4cd7c8 | 3556 | const char *i915_cache_level_str(struct drm_i915_private *i915, int type); |
2017263e | 3557 | |
351e3db2 | 3558 | /* i915_cmd_parser.c */ |
1ca3712c | 3559 | int i915_cmd_parser_get_version(struct drm_i915_private *dev_priv); |
7756e454 | 3560 | void intel_engine_init_cmd_parser(struct intel_engine_cs *engine); |
33a051a5 CW |
3561 | void intel_engine_cleanup_cmd_parser(struct intel_engine_cs *engine); |
3562 | bool intel_engine_needs_cmd_parser(struct intel_engine_cs *engine); | |
3563 | int intel_engine_cmd_parser(struct intel_engine_cs *engine, | |
3564 | struct drm_i915_gem_object *batch_obj, | |
3565 | struct drm_i915_gem_object *shadow_batch_obj, | |
3566 | u32 batch_start_offset, | |
3567 | u32 batch_len, | |
3568 | bool is_master); | |
351e3db2 | 3569 | |
317c35d1 JB |
3570 | /* i915_suspend.c */ |
3571 | extern int i915_save_state(struct drm_device *dev); | |
3572 | extern int i915_restore_state(struct drm_device *dev); | |
0a3e67a4 | 3573 | |
0136db58 | 3574 | /* i915_sysfs.c */ |
694c2828 DW |
3575 | void i915_setup_sysfs(struct drm_i915_private *dev_priv); |
3576 | void i915_teardown_sysfs(struct drm_i915_private *dev_priv); | |
0136db58 | 3577 | |
f899fc64 CW |
3578 | /* intel_i2c.c */ |
3579 | extern int intel_setup_gmbus(struct drm_device *dev); | |
3580 | extern void intel_teardown_gmbus(struct drm_device *dev); | |
88ac7939 JN |
3581 | extern bool intel_gmbus_is_valid_pin(struct drm_i915_private *dev_priv, |
3582 | unsigned int pin); | |
3bd7d909 | 3583 | |
0184df46 JN |
3584 | extern struct i2c_adapter * |
3585 | intel_gmbus_get_adapter(struct drm_i915_private *dev_priv, unsigned int pin); | |
e957d772 CW |
3586 | extern void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed); |
3587 | extern void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit); | |
8f375e10 | 3588 | static inline bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter) |
b8232e90 CW |
3589 | { |
3590 | return container_of(adapter, struct intel_gmbus, adapter)->force_bit; | |
3591 | } | |
f899fc64 CW |
3592 | extern void intel_i2c_reset(struct drm_device *dev); |
3593 | ||
8b8e1a89 | 3594 | /* intel_bios.c */ |
98f3a1dc | 3595 | int intel_bios_init(struct drm_i915_private *dev_priv); |
f0067a31 | 3596 | bool intel_bios_is_valid_vbt(const void *buf, size_t size); |
3bdd14d5 | 3597 | bool intel_bios_is_tv_present(struct drm_i915_private *dev_priv); |
5a69d13d | 3598 | bool intel_bios_is_lvds_present(struct drm_i915_private *dev_priv, u8 *i2c_pin); |
22f35042 | 3599 | bool intel_bios_is_port_present(struct drm_i915_private *dev_priv, enum port port); |
951d9efe | 3600 | bool intel_bios_is_port_edp(struct drm_i915_private *dev_priv, enum port port); |
d6199256 | 3601 | bool intel_bios_is_port_dp_dual_mode(struct drm_i915_private *dev_priv, enum port port); |
7137aec1 | 3602 | bool intel_bios_is_dsi_present(struct drm_i915_private *dev_priv, enum port *port); |
d252bf68 SS |
3603 | bool intel_bios_is_port_hpd_inverted(struct drm_i915_private *dev_priv, |
3604 | enum port port); | |
8b8e1a89 | 3605 | |
3b617967 | 3606 | /* intel_opregion.c */ |
44834a67 | 3607 | #ifdef CONFIG_ACPI |
6f9f4b7a | 3608 | extern int intel_opregion_setup(struct drm_i915_private *dev_priv); |
03d92e47 CW |
3609 | extern void intel_opregion_register(struct drm_i915_private *dev_priv); |
3610 | extern void intel_opregion_unregister(struct drm_i915_private *dev_priv); | |
91d14251 | 3611 | extern void intel_opregion_asle_intr(struct drm_i915_private *dev_priv); |
9c4b0a68 JN |
3612 | extern int intel_opregion_notify_encoder(struct intel_encoder *intel_encoder, |
3613 | bool enable); | |
6f9f4b7a | 3614 | extern int intel_opregion_notify_adapter(struct drm_i915_private *dev_priv, |
ecbc5cf3 | 3615 | pci_power_t state); |
6f9f4b7a | 3616 | extern int intel_opregion_get_panel_type(struct drm_i915_private *dev_priv); |
65e082c9 | 3617 | #else |
6f9f4b7a | 3618 | static inline int intel_opregion_setup(struct drm_i915_private *dev) { return 0; } |
bdaa2dfb RD |
3619 | static inline void intel_opregion_register(struct drm_i915_private *dev_priv) { } |
3620 | static inline void intel_opregion_unregister(struct drm_i915_private *dev_priv) { } | |
91d14251 TU |
3621 | static inline void intel_opregion_asle_intr(struct drm_i915_private *dev_priv) |
3622 | { | |
3623 | } | |
9c4b0a68 JN |
3624 | static inline int |
3625 | intel_opregion_notify_encoder(struct intel_encoder *intel_encoder, bool enable) | |
3626 | { | |
3627 | return 0; | |
3628 | } | |
ecbc5cf3 | 3629 | static inline int |
6f9f4b7a | 3630 | intel_opregion_notify_adapter(struct drm_i915_private *dev, pci_power_t state) |
ecbc5cf3 JN |
3631 | { |
3632 | return 0; | |
3633 | } | |
6f9f4b7a | 3634 | static inline int intel_opregion_get_panel_type(struct drm_i915_private *dev) |
a0562819 VS |
3635 | { |
3636 | return -ENODEV; | |
3637 | } | |
65e082c9 | 3638 | #endif |
8ee1c3db | 3639 | |
723bfd70 JB |
3640 | /* intel_acpi.c */ |
3641 | #ifdef CONFIG_ACPI | |
3642 | extern void intel_register_dsm_handler(void); | |
3643 | extern void intel_unregister_dsm_handler(void); | |
3644 | #else | |
3645 | static inline void intel_register_dsm_handler(void) { return; } | |
3646 | static inline void intel_unregister_dsm_handler(void) { return; } | |
3647 | #endif /* CONFIG_ACPI */ | |
3648 | ||
94b4f3ba CW |
3649 | /* intel_device_info.c */ |
3650 | static inline struct intel_device_info * | |
3651 | mkwrite_device_info(struct drm_i915_private *dev_priv) | |
3652 | { | |
3653 | return (struct intel_device_info *)&dev_priv->info; | |
3654 | } | |
3655 | ||
3656 | void intel_device_info_runtime_init(struct drm_i915_private *dev_priv); | |
3657 | void intel_device_info_dump(struct drm_i915_private *dev_priv); | |
3658 | ||
79e53945 | 3659 | /* modesetting */ |
f817586c | 3660 | extern void intel_modeset_init_hw(struct drm_device *dev); |
79e53945 | 3661 | extern void intel_modeset_init(struct drm_device *dev); |
2c7111db | 3662 | extern void intel_modeset_gem_init(struct drm_device *dev); |
79e53945 | 3663 | extern void intel_modeset_cleanup(struct drm_device *dev); |
1ebaa0b9 | 3664 | extern int intel_connector_register(struct drm_connector *); |
c191eca1 | 3665 | extern void intel_connector_unregister(struct drm_connector *); |
28d52043 | 3666 | extern int intel_modeset_vga_set_state(struct drm_device *dev, bool state); |
043e9bda | 3667 | extern void intel_display_resume(struct drm_device *dev); |
44cec740 | 3668 | extern void i915_redisable_vga(struct drm_device *dev); |
04098753 | 3669 | extern void i915_redisable_vga_power_on(struct drm_device *dev); |
91d14251 | 3670 | extern bool ironlake_set_drps(struct drm_i915_private *dev_priv, u8 val); |
dde86e2d | 3671 | extern void intel_init_pch_refclk(struct drm_device *dev); |
dc97997a | 3672 | extern void intel_set_rps(struct drm_i915_private *dev_priv, u8 val); |
5209b1f4 ID |
3673 | extern void intel_set_memory_cxsr(struct drm_i915_private *dev_priv, |
3674 | bool enable); | |
3bad0781 | 3675 | |
c0c7babc BW |
3676 | int i915_reg_read_ioctl(struct drm_device *dev, void *data, |
3677 | struct drm_file *file); | |
575155a9 | 3678 | |
6ef3d427 | 3679 | /* overlay */ |
c033666a CW |
3680 | extern struct intel_overlay_error_state * |
3681 | intel_overlay_capture_error_state(struct drm_i915_private *dev_priv); | |
edc3d884 MK |
3682 | extern void intel_overlay_print_error_state(struct drm_i915_error_state_buf *e, |
3683 | struct intel_overlay_error_state *error); | |
c4a1d9e4 | 3684 | |
c033666a CW |
3685 | extern struct intel_display_error_state * |
3686 | intel_display_capture_error_state(struct drm_i915_private *dev_priv); | |
edc3d884 | 3687 | extern void intel_display_print_error_state(struct drm_i915_error_state_buf *e, |
c4a1d9e4 CW |
3688 | struct drm_device *dev, |
3689 | struct intel_display_error_state *error); | |
6ef3d427 | 3690 | |
151a49d0 TR |
3691 | int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *val); |
3692 | int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u32 mbox, u32 val); | |
59de0813 JN |
3693 | |
3694 | /* intel_sideband.c */ | |
707b6e3d D |
3695 | u32 vlv_punit_read(struct drm_i915_private *dev_priv, u32 addr); |
3696 | void vlv_punit_write(struct drm_i915_private *dev_priv, u32 addr, u32 val); | |
64936258 | 3697 | u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr); |
dfb19ed2 D |
3698 | u32 vlv_iosf_sb_read(struct drm_i915_private *dev_priv, u8 port, u32 reg); |
3699 | void vlv_iosf_sb_write(struct drm_i915_private *dev_priv, u8 port, u32 reg, u32 val); | |
e9f882a3 JN |
3700 | u32 vlv_cck_read(struct drm_i915_private *dev_priv, u32 reg); |
3701 | void vlv_cck_write(struct drm_i915_private *dev_priv, u32 reg, u32 val); | |
3702 | u32 vlv_ccu_read(struct drm_i915_private *dev_priv, u32 reg); | |
3703 | void vlv_ccu_write(struct drm_i915_private *dev_priv, u32 reg, u32 val); | |
f3419158 JB |
3704 | u32 vlv_bunit_read(struct drm_i915_private *dev_priv, u32 reg); |
3705 | void vlv_bunit_write(struct drm_i915_private *dev_priv, u32 reg, u32 val); | |
5e69f97f CML |
3706 | u32 vlv_dpio_read(struct drm_i915_private *dev_priv, enum pipe pipe, int reg); |
3707 | void vlv_dpio_write(struct drm_i915_private *dev_priv, enum pipe pipe, int reg, u32 val); | |
59de0813 JN |
3708 | u32 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg, |
3709 | enum intel_sbi_destination destination); | |
3710 | void intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value, | |
3711 | enum intel_sbi_destination destination); | |
e9fe51c6 SK |
3712 | u32 vlv_flisdsi_read(struct drm_i915_private *dev_priv, u32 reg); |
3713 | void vlv_flisdsi_write(struct drm_i915_private *dev_priv, u32 reg, u32 val); | |
0a073b84 | 3714 | |
b7fa22d8 ACO |
3715 | /* intel_dpio_phy.c */ |
3716 | void chv_set_phy_signal_level(struct intel_encoder *encoder, | |
3717 | u32 deemph_reg_value, u32 margin_reg_value, | |
3718 | bool uniq_trans_scale); | |
844b2f9a ACO |
3719 | void chv_data_lane_soft_reset(struct intel_encoder *encoder, |
3720 | bool reset); | |
419b1b7a | 3721 | void chv_phy_pre_pll_enable(struct intel_encoder *encoder); |
e7d2a717 ACO |
3722 | void chv_phy_pre_encoder_enable(struct intel_encoder *encoder); |
3723 | void chv_phy_release_cl2_override(struct intel_encoder *encoder); | |
204970b5 | 3724 | void chv_phy_post_pll_disable(struct intel_encoder *encoder); |
b7fa22d8 | 3725 | |
53d98725 ACO |
3726 | void vlv_set_phy_signal_level(struct intel_encoder *encoder, |
3727 | u32 demph_reg_value, u32 preemph_reg_value, | |
3728 | u32 uniqtranscale_reg_value, u32 tx3_demph); | |
6da2e616 | 3729 | void vlv_phy_pre_pll_enable(struct intel_encoder *encoder); |
5f68c275 | 3730 | void vlv_phy_pre_encoder_enable(struct intel_encoder *encoder); |
0f572ebe | 3731 | void vlv_phy_reset_lanes(struct intel_encoder *encoder); |
53d98725 | 3732 | |
616bc820 VS |
3733 | int intel_gpu_freq(struct drm_i915_private *dev_priv, int val); |
3734 | int intel_freq_opcode(struct drm_i915_private *dev_priv, int val); | |
c8d9a590 | 3735 | |
0b274481 BW |
3736 | #define I915_READ8(reg) dev_priv->uncore.funcs.mmio_readb(dev_priv, (reg), true) |
3737 | #define I915_WRITE8(reg, val) dev_priv->uncore.funcs.mmio_writeb(dev_priv, (reg), (val), true) | |
3738 | ||
3739 | #define I915_READ16(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), true) | |
3740 | #define I915_WRITE16(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), true) | |
3741 | #define I915_READ16_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), false) | |
3742 | #define I915_WRITE16_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), false) | |
3743 | ||
3744 | #define I915_READ(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), true) | |
3745 | #define I915_WRITE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), true) | |
3746 | #define I915_READ_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), false) | |
3747 | #define I915_WRITE_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), false) | |
3748 | ||
698b3135 CW |
3749 | /* Be very careful with read/write 64-bit values. On 32-bit machines, they |
3750 | * will be implemented using 2 32-bit writes in an arbitrary order with | |
3751 | * an arbitrary delay between them. This can cause the hardware to | |
3752 | * act upon the intermediate value, possibly leading to corruption and | |
b18c1bb4 CW |
3753 | * machine death. For this reason we do not support I915_WRITE64, or |
3754 | * dev_priv->uncore.funcs.mmio_writeq. | |
3755 | * | |
3756 | * When reading a 64-bit value as two 32-bit values, the delay may cause | |
3757 | * the two reads to mismatch, e.g. a timestamp overflowing. Also note that | |
3758 | * occasionally a 64-bit register does not actualy support a full readq | |
3759 | * and must be read using two 32-bit reads. | |
3760 | * | |
3761 | * You have been warned. | |
698b3135 | 3762 | */ |
0b274481 | 3763 | #define I915_READ64(reg) dev_priv->uncore.funcs.mmio_readq(dev_priv, (reg), true) |
cae5852d | 3764 | |
50877445 | 3765 | #define I915_READ64_2x32(lower_reg, upper_reg) ({ \ |
acd29f7b CW |
3766 | u32 upper, lower, old_upper, loop = 0; \ |
3767 | upper = I915_READ(upper_reg); \ | |
ee0a227b | 3768 | do { \ |
acd29f7b | 3769 | old_upper = upper; \ |
ee0a227b | 3770 | lower = I915_READ(lower_reg); \ |
acd29f7b CW |
3771 | upper = I915_READ(upper_reg); \ |
3772 | } while (upper != old_upper && loop++ < 2); \ | |
ee0a227b | 3773 | (u64)upper << 32 | lower; }) |
50877445 | 3774 | |
cae5852d ZN |
3775 | #define POSTING_READ(reg) (void)I915_READ_NOTRACE(reg) |
3776 | #define POSTING_READ16(reg) (void)I915_READ16_NOTRACE(reg) | |
3777 | ||
75aa3f63 VS |
3778 | #define __raw_read(x, s) \ |
3779 | static inline uint##x##_t __raw_i915_read##x(struct drm_i915_private *dev_priv, \ | |
f0f59a00 | 3780 | i915_reg_t reg) \ |
75aa3f63 | 3781 | { \ |
f0f59a00 | 3782 | return read##s(dev_priv->regs + i915_mmio_reg_offset(reg)); \ |
75aa3f63 VS |
3783 | } |
3784 | ||
3785 | #define __raw_write(x, s) \ | |
3786 | static inline void __raw_i915_write##x(struct drm_i915_private *dev_priv, \ | |
f0f59a00 | 3787 | i915_reg_t reg, uint##x##_t val) \ |
75aa3f63 | 3788 | { \ |
f0f59a00 | 3789 | write##s(val, dev_priv->regs + i915_mmio_reg_offset(reg)); \ |
75aa3f63 VS |
3790 | } |
3791 | __raw_read(8, b) | |
3792 | __raw_read(16, w) | |
3793 | __raw_read(32, l) | |
3794 | __raw_read(64, q) | |
3795 | ||
3796 | __raw_write(8, b) | |
3797 | __raw_write(16, w) | |
3798 | __raw_write(32, l) | |
3799 | __raw_write(64, q) | |
3800 | ||
3801 | #undef __raw_read | |
3802 | #undef __raw_write | |
3803 | ||
a6111f7b | 3804 | /* These are untraced mmio-accessors that are only valid to be used inside |
351c3b53 | 3805 | * critical sections inside IRQ handlers where forcewake is explicitly |
a6111f7b CW |
3806 | * controlled. |
3807 | * Think twice, and think again, before using these. | |
3808 | * Note: Should only be used between intel_uncore_forcewake_irqlock() and | |
3809 | * intel_uncore_forcewake_irqunlock(). | |
3810 | */ | |
75aa3f63 VS |
3811 | #define I915_READ_FW(reg__) __raw_i915_read32(dev_priv, (reg__)) |
3812 | #define I915_WRITE_FW(reg__, val__) __raw_i915_write32(dev_priv, (reg__), (val__)) | |
76f8421f | 3813 | #define I915_WRITE64_FW(reg__, val__) __raw_i915_write64(dev_priv, (reg__), (val__)) |
a6111f7b CW |
3814 | #define POSTING_READ_FW(reg__) (void)I915_READ_FW(reg__) |
3815 | ||
55bc60db VS |
3816 | /* "Broadcast RGB" property */ |
3817 | #define INTEL_BROADCAST_RGB_AUTO 0 | |
3818 | #define INTEL_BROADCAST_RGB_FULL 1 | |
3819 | #define INTEL_BROADCAST_RGB_LIMITED 2 | |
ba4f01a3 | 3820 | |
f0f59a00 | 3821 | static inline i915_reg_t i915_vgacntrl_reg(struct drm_device *dev) |
766aa1c4 | 3822 | { |
666a4537 | 3823 | if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) |
766aa1c4 | 3824 | return VLV_VGACNTRL; |
92e23b99 SJ |
3825 | else if (INTEL_INFO(dev)->gen >= 5) |
3826 | return CPU_VGACNTRL; | |
766aa1c4 VS |
3827 | else |
3828 | return VGACNTRL; | |
3829 | } | |
3830 | ||
df97729f ID |
3831 | static inline unsigned long msecs_to_jiffies_timeout(const unsigned int m) |
3832 | { | |
3833 | unsigned long j = msecs_to_jiffies(m); | |
3834 | ||
3835 | return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1); | |
3836 | } | |
3837 | ||
7bd0e226 DV |
3838 | static inline unsigned long nsecs_to_jiffies_timeout(const u64 n) |
3839 | { | |
3840 | return min_t(u64, MAX_JIFFY_OFFSET, nsecs_to_jiffies64(n) + 1); | |
3841 | } | |
3842 | ||
df97729f ID |
3843 | static inline unsigned long |
3844 | timespec_to_jiffies_timeout(const struct timespec *value) | |
3845 | { | |
3846 | unsigned long j = timespec_to_jiffies(value); | |
3847 | ||
3848 | return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1); | |
3849 | } | |
3850 | ||
dce56b3c PZ |
3851 | /* |
3852 | * If you need to wait X milliseconds between events A and B, but event B | |
3853 | * doesn't happen exactly after event A, you record the timestamp (jiffies) of | |
3854 | * when event A happened, then just before event B you call this function and | |
3855 | * pass the timestamp as the first argument, and X as the second argument. | |
3856 | */ | |
3857 | static inline void | |
3858 | wait_remaining_ms_from_jiffies(unsigned long timestamp_jiffies, int to_wait_ms) | |
3859 | { | |
ec5e0cfb | 3860 | unsigned long target_jiffies, tmp_jiffies, remaining_jiffies; |
dce56b3c PZ |
3861 | |
3862 | /* | |
3863 | * Don't re-read the value of "jiffies" every time since it may change | |
3864 | * behind our back and break the math. | |
3865 | */ | |
3866 | tmp_jiffies = jiffies; | |
3867 | target_jiffies = timestamp_jiffies + | |
3868 | msecs_to_jiffies_timeout(to_wait_ms); | |
3869 | ||
3870 | if (time_after(target_jiffies, tmp_jiffies)) { | |
ec5e0cfb ID |
3871 | remaining_jiffies = target_jiffies - tmp_jiffies; |
3872 | while (remaining_jiffies) | |
3873 | remaining_jiffies = | |
3874 | schedule_timeout_uninterruptible(remaining_jiffies); | |
dce56b3c PZ |
3875 | } |
3876 | } | |
688e6c72 CW |
3877 | static inline bool __i915_request_irq_complete(struct drm_i915_gem_request *req) |
3878 | { | |
f69a02c9 CW |
3879 | struct intel_engine_cs *engine = req->engine; |
3880 | ||
7ec2c73b CW |
3881 | /* Before we do the heavier coherent read of the seqno, |
3882 | * check the value (hopefully) in the CPU cacheline. | |
3883 | */ | |
3884 | if (i915_gem_request_completed(req)) | |
3885 | return true; | |
3886 | ||
688e6c72 CW |
3887 | /* Ensure our read of the seqno is coherent so that we |
3888 | * do not "miss an interrupt" (i.e. if this is the last | |
3889 | * request and the seqno write from the GPU is not visible | |
3890 | * by the time the interrupt fires, we will see that the | |
3891 | * request is incomplete and go back to sleep awaiting | |
3892 | * another interrupt that will never come.) | |
3893 | * | |
3894 | * Strictly, we only need to do this once after an interrupt, | |
3895 | * but it is easier and safer to do it every time the waiter | |
3896 | * is woken. | |
3897 | */ | |
3d5564e9 | 3898 | if (engine->irq_seqno_barrier && |
dbd6ef29 | 3899 | rcu_access_pointer(engine->breadcrumbs.irq_seqno_bh) == current && |
aca34b6e | 3900 | cmpxchg_relaxed(&engine->breadcrumbs.irq_posted, 1, 0)) { |
99fe4a5f CW |
3901 | struct task_struct *tsk; |
3902 | ||
3d5564e9 CW |
3903 | /* The ordering of irq_posted versus applying the barrier |
3904 | * is crucial. The clearing of the current irq_posted must | |
3905 | * be visible before we perform the barrier operation, | |
3906 | * such that if a subsequent interrupt arrives, irq_posted | |
3907 | * is reasserted and our task rewoken (which causes us to | |
3908 | * do another __i915_request_irq_complete() immediately | |
3909 | * and reapply the barrier). Conversely, if the clear | |
3910 | * occurs after the barrier, then an interrupt that arrived | |
3911 | * whilst we waited on the barrier would not trigger a | |
3912 | * barrier on the next pass, and the read may not see the | |
3913 | * seqno update. | |
3914 | */ | |
f69a02c9 | 3915 | engine->irq_seqno_barrier(engine); |
99fe4a5f CW |
3916 | |
3917 | /* If we consume the irq, but we are no longer the bottom-half, | |
3918 | * the real bottom-half may not have serialised their own | |
3919 | * seqno check with the irq-barrier (i.e. may have inspected | |
3920 | * the seqno before we believe it coherent since they see | |
3921 | * irq_posted == false but we are still running). | |
3922 | */ | |
3923 | rcu_read_lock(); | |
dbd6ef29 | 3924 | tsk = rcu_dereference(engine->breadcrumbs.irq_seqno_bh); |
99fe4a5f CW |
3925 | if (tsk && tsk != current) |
3926 | /* Note that if the bottom-half is changed as we | |
3927 | * are sending the wake-up, the new bottom-half will | |
3928 | * be woken by whomever made the change. We only have | |
3929 | * to worry about when we steal the irq-posted for | |
3930 | * ourself. | |
3931 | */ | |
3932 | wake_up_process(tsk); | |
3933 | rcu_read_unlock(); | |
3934 | ||
7ec2c73b CW |
3935 | if (i915_gem_request_completed(req)) |
3936 | return true; | |
3937 | } | |
688e6c72 CW |
3938 | |
3939 | /* We need to check whether any gpu reset happened in between | |
3940 | * the request being submitted and now. If a reset has occurred, | |
3941 | * the seqno will have been advance past ours and our request | |
3942 | * is complete. If we are in the process of handling a reset, | |
3943 | * the request is effectively complete as the rendering will | |
3944 | * be discarded, but we need to return in order to drop the | |
3945 | * struct_mutex. | |
3946 | */ | |
3947 | if (i915_reset_in_progress(&req->i915->gpu_error)) | |
3948 | return true; | |
3949 | ||
3950 | return false; | |
3951 | } | |
3952 | ||
0b1de5d5 CW |
3953 | void i915_memcpy_init_early(struct drm_i915_private *dev_priv); |
3954 | bool i915_memcpy_from_wc(void *dst, const void *src, unsigned long len); | |
3955 | ||
c58305af CW |
3956 | /* i915_mm.c */ |
3957 | int remap_io_mapping(struct vm_area_struct *vma, | |
3958 | unsigned long addr, unsigned long pfn, unsigned long size, | |
3959 | struct io_mapping *iomap); | |
3960 | ||
4b30cb23 CW |
3961 | #define ptr_mask_bits(ptr) ({ \ |
3962 | unsigned long __v = (unsigned long)(ptr); \ | |
3963 | (typeof(ptr))(__v & PAGE_MASK); \ | |
3964 | }) | |
3965 | ||
d31d7cb1 CW |
3966 | #define ptr_unpack_bits(ptr, bits) ({ \ |
3967 | unsigned long __v = (unsigned long)(ptr); \ | |
3968 | (bits) = __v & ~PAGE_MASK; \ | |
3969 | (typeof(ptr))(__v & PAGE_MASK); \ | |
3970 | }) | |
3971 | ||
3972 | #define ptr_pack_bits(ptr, bits) \ | |
3973 | ((typeof(ptr))((unsigned long)(ptr) | (bits))) | |
3974 | ||
78ef2d9a CW |
3975 | #define fetch_and_zero(ptr) ({ \ |
3976 | typeof(*ptr) __T = *(ptr); \ | |
3977 | *(ptr) = (typeof(*ptr))0; \ | |
3978 | __T; \ | |
3979 | }) | |
3980 | ||
1da177e4 | 3981 | #endif |