Commit | Line | Data |
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1da177e4 LT |
1 | /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*- |
2 | */ | |
0d6aa60b | 3 | /* |
bc54fd1a | 4 | * |
1da177e4 LT |
5 | * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. |
6 | * All Rights Reserved. | |
bc54fd1a DA |
7 | * |
8 | * Permission is hereby granted, free of charge, to any person obtaining a | |
9 | * copy of this software and associated documentation files (the | |
10 | * "Software"), to deal in the Software without restriction, including | |
11 | * without limitation the rights to use, copy, modify, merge, publish, | |
12 | * distribute, sub license, and/or sell copies of the Software, and to | |
13 | * permit persons to whom the Software is furnished to do so, subject to | |
14 | * the following conditions: | |
15 | * | |
16 | * The above copyright notice and this permission notice (including the | |
17 | * next paragraph) shall be included in all copies or substantial portions | |
18 | * of the Software. | |
19 | * | |
20 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS | |
21 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
22 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. | |
23 | * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR | |
24 | * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, | |
25 | * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE | |
26 | * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. | |
27 | * | |
0d6aa60b | 28 | */ |
1da177e4 LT |
29 | |
30 | #ifndef _I915_DRV_H_ | |
31 | #define _I915_DRV_H_ | |
32 | ||
585fb111 | 33 | #include "i915_reg.h" |
79e53945 | 34 | #include "intel_bios.h" |
8187a2b7 | 35 | #include "intel_ringbuffer.h" |
0839ccb8 | 36 | #include <linux/io-mapping.h> |
f899fc64 | 37 | #include <linux/i2c.h> |
c167a6fc | 38 | #include <linux/i2c-algo-bit.h> |
0ade6386 | 39 | #include <drm/intel-gtt.h> |
aaa6fd2a | 40 | #include <linux/backlight.h> |
2911a35b | 41 | #include <linux/intel-iommu.h> |
585fb111 | 42 | |
1da177e4 LT |
43 | /* General customization: |
44 | */ | |
45 | ||
46 | #define DRIVER_AUTHOR "Tungsten Graphics, Inc." | |
47 | ||
48 | #define DRIVER_NAME "i915" | |
49 | #define DRIVER_DESC "Intel Graphics" | |
673a394b | 50 | #define DRIVER_DATE "20080730" |
1da177e4 | 51 | |
317c35d1 JB |
52 | enum pipe { |
53 | PIPE_A = 0, | |
54 | PIPE_B, | |
9db4a9c7 JB |
55 | PIPE_C, |
56 | I915_MAX_PIPES | |
317c35d1 | 57 | }; |
9db4a9c7 | 58 | #define pipe_name(p) ((p) + 'A') |
317c35d1 | 59 | |
80824003 JB |
60 | enum plane { |
61 | PLANE_A = 0, | |
62 | PLANE_B, | |
9db4a9c7 | 63 | PLANE_C, |
80824003 | 64 | }; |
9db4a9c7 | 65 | #define plane_name(p) ((p) + 'A') |
52440211 | 66 | |
2b139522 ED |
67 | enum port { |
68 | PORT_A = 0, | |
69 | PORT_B, | |
70 | PORT_C, | |
71 | PORT_D, | |
72 | PORT_E, | |
73 | I915_MAX_PORTS | |
74 | }; | |
75 | #define port_name(p) ((p) + 'A') | |
76 | ||
62fdfeaf EA |
77 | #define I915_GEM_GPU_DOMAINS (~(I915_GEM_DOMAIN_CPU | I915_GEM_DOMAIN_GTT)) |
78 | ||
9db4a9c7 JB |
79 | #define for_each_pipe(p) for ((p) = 0; (p) < dev_priv->num_pipe; (p)++) |
80 | ||
ee7b9f93 JB |
81 | struct intel_pch_pll { |
82 | int refcount; /* count of number of CRTCs sharing this PLL */ | |
83 | int active; /* count of number of active CRTCs (i.e. DPMS on) */ | |
84 | bool on; /* is the PLL actually active? Disabled during modeset */ | |
85 | int pll_reg; | |
86 | int fp0_reg; | |
87 | int fp1_reg; | |
88 | }; | |
89 | #define I915_NUM_PLLS 2 | |
90 | ||
1da177e4 LT |
91 | /* Interface history: |
92 | * | |
93 | * 1.1: Original. | |
0d6aa60b DA |
94 | * 1.2: Add Power Management |
95 | * 1.3: Add vblank support | |
de227f5f | 96 | * 1.4: Fix cmdbuffer path, add heap destroy |
702880f2 | 97 | * 1.5: Add vblank pipe configuration |
2228ed67 MCA |
98 | * 1.6: - New ioctl for scheduling buffer swaps on vertical blank |
99 | * - Support vertical blank on secondary display pipe | |
1da177e4 LT |
100 | */ |
101 | #define DRIVER_MAJOR 1 | |
2228ed67 | 102 | #define DRIVER_MINOR 6 |
1da177e4 LT |
103 | #define DRIVER_PATCHLEVEL 0 |
104 | ||
673a394b | 105 | #define WATCH_COHERENCY 0 |
23bc5982 | 106 | #define WATCH_LISTS 0 |
673a394b | 107 | |
71acb5eb DA |
108 | #define I915_GEM_PHYS_CURSOR_0 1 |
109 | #define I915_GEM_PHYS_CURSOR_1 2 | |
110 | #define I915_GEM_PHYS_OVERLAY_REGS 3 | |
111 | #define I915_MAX_PHYS_OBJECT (I915_GEM_PHYS_OVERLAY_REGS) | |
112 | ||
113 | struct drm_i915_gem_phys_object { | |
114 | int id; | |
115 | struct page **page_list; | |
116 | drm_dma_handle_t *handle; | |
05394f39 | 117 | struct drm_i915_gem_object *cur_obj; |
71acb5eb DA |
118 | }; |
119 | ||
1da177e4 LT |
120 | struct mem_block { |
121 | struct mem_block *next; | |
122 | struct mem_block *prev; | |
123 | int start; | |
124 | int size; | |
6c340eac | 125 | struct drm_file *file_priv; /* NULL: free, -1: heap, other: real files */ |
1da177e4 LT |
126 | }; |
127 | ||
0a3e67a4 JB |
128 | struct opregion_header; |
129 | struct opregion_acpi; | |
130 | struct opregion_swsci; | |
131 | struct opregion_asle; | |
8d715f00 | 132 | struct drm_i915_private; |
0a3e67a4 | 133 | |
8ee1c3db | 134 | struct intel_opregion { |
5bc4418b BW |
135 | struct opregion_header __iomem *header; |
136 | struct opregion_acpi __iomem *acpi; | |
137 | struct opregion_swsci __iomem *swsci; | |
138 | struct opregion_asle __iomem *asle; | |
139 | void __iomem *vbt; | |
01fe9dbd | 140 | u32 __iomem *lid_state; |
8ee1c3db | 141 | }; |
44834a67 | 142 | #define OPREGION_SIZE (8*1024) |
8ee1c3db | 143 | |
6ef3d427 CW |
144 | struct intel_overlay; |
145 | struct intel_overlay_error_state; | |
146 | ||
7c1c2871 DA |
147 | struct drm_i915_master_private { |
148 | drm_local_map_t *sarea; | |
149 | struct _drm_i915_sarea *sarea_priv; | |
150 | }; | |
de151cf6 | 151 | #define I915_FENCE_REG_NONE -1 |
4b9de737 DV |
152 | #define I915_MAX_NUM_FENCES 16 |
153 | /* 16 fences + sign bit for FENCE_REG_NONE */ | |
154 | #define I915_MAX_NUM_FENCE_BITS 5 | |
de151cf6 JB |
155 | |
156 | struct drm_i915_fence_reg { | |
007cc8ac | 157 | struct list_head lru_list; |
caea7476 | 158 | struct drm_i915_gem_object *obj; |
1690e1eb | 159 | int pin_count; |
de151cf6 | 160 | }; |
7c1c2871 | 161 | |
9b9d172d | 162 | struct sdvo_device_mapping { |
e957d772 | 163 | u8 initialized; |
9b9d172d | 164 | u8 dvo_port; |
165 | u8 slave_addr; | |
166 | u8 dvo_wiring; | |
e957d772 | 167 | u8 i2c_pin; |
b1083333 | 168 | u8 ddc_pin; |
9b9d172d | 169 | }; |
170 | ||
c4a1d9e4 CW |
171 | struct intel_display_error_state; |
172 | ||
63eeaf38 JB |
173 | struct drm_i915_error_state { |
174 | u32 eir; | |
175 | u32 pgtbl_er; | |
9db4a9c7 | 176 | u32 pipestat[I915_MAX_PIPES]; |
c1cd90ed DV |
177 | u32 tail[I915_NUM_RINGS]; |
178 | u32 head[I915_NUM_RINGS]; | |
d27b1e0e DV |
179 | u32 ipeir[I915_NUM_RINGS]; |
180 | u32 ipehr[I915_NUM_RINGS]; | |
181 | u32 instdone[I915_NUM_RINGS]; | |
182 | u32 acthd[I915_NUM_RINGS]; | |
7e3b8737 DV |
183 | u32 semaphore_mboxes[I915_NUM_RINGS][I915_NUM_RINGS - 1]; |
184 | /* our own tracking of ring head and tail */ | |
185 | u32 cpu_ring_head[I915_NUM_RINGS]; | |
186 | u32 cpu_ring_tail[I915_NUM_RINGS]; | |
1d8f38f4 | 187 | u32 error; /* gen6+ */ |
c1cd90ed DV |
188 | u32 instpm[I915_NUM_RINGS]; |
189 | u32 instps[I915_NUM_RINGS]; | |
63eeaf38 | 190 | u32 instdone1; |
d27b1e0e | 191 | u32 seqno[I915_NUM_RINGS]; |
9df30794 | 192 | u64 bbaddr; |
33f3f518 DV |
193 | u32 fault_reg[I915_NUM_RINGS]; |
194 | u32 done_reg; | |
c1cd90ed | 195 | u32 faddr[I915_NUM_RINGS]; |
4b9de737 | 196 | u64 fence[I915_MAX_NUM_FENCES]; |
63eeaf38 | 197 | struct timeval time; |
52d39a21 CW |
198 | struct drm_i915_error_ring { |
199 | struct drm_i915_error_object { | |
200 | int page_count; | |
201 | u32 gtt_offset; | |
202 | u32 *pages[0]; | |
203 | } *ringbuffer, *batchbuffer; | |
204 | struct drm_i915_error_request { | |
205 | long jiffies; | |
206 | u32 seqno; | |
ee4f42b1 | 207 | u32 tail; |
52d39a21 CW |
208 | } *requests; |
209 | int num_requests; | |
210 | } ring[I915_NUM_RINGS]; | |
9df30794 | 211 | struct drm_i915_error_buffer { |
a779e5ab | 212 | u32 size; |
9df30794 CW |
213 | u32 name; |
214 | u32 seqno; | |
215 | u32 gtt_offset; | |
216 | u32 read_domains; | |
217 | u32 write_domain; | |
4b9de737 | 218 | s32 fence_reg:I915_MAX_NUM_FENCE_BITS; |
9df30794 CW |
219 | s32 pinned:2; |
220 | u32 tiling:2; | |
221 | u32 dirty:1; | |
222 | u32 purgeable:1; | |
5d1333fc | 223 | s32 ring:4; |
93dfb40c | 224 | u32 cache_level:2; |
c724e8a9 CW |
225 | } *active_bo, *pinned_bo; |
226 | u32 active_bo_count, pinned_bo_count; | |
6ef3d427 | 227 | struct intel_overlay_error_state *overlay; |
c4a1d9e4 | 228 | struct intel_display_error_state *display; |
63eeaf38 JB |
229 | }; |
230 | ||
e70236a8 JB |
231 | struct drm_i915_display_funcs { |
232 | void (*dpms)(struct drm_crtc *crtc, int mode); | |
ee5382ae | 233 | bool (*fbc_enabled)(struct drm_device *dev); |
e70236a8 JB |
234 | void (*enable_fbc)(struct drm_crtc *crtc, unsigned long interval); |
235 | void (*disable_fbc)(struct drm_device *dev); | |
236 | int (*get_display_clock_speed)(struct drm_device *dev); | |
237 | int (*get_fifo_size)(struct drm_device *dev, int plane); | |
d210246a | 238 | void (*update_wm)(struct drm_device *dev); |
b840d907 JB |
239 | void (*update_sprite_wm)(struct drm_device *dev, int pipe, |
240 | uint32_t sprite_width, int pixel_size); | |
f564048e EA |
241 | int (*crtc_mode_set)(struct drm_crtc *crtc, |
242 | struct drm_display_mode *mode, | |
243 | struct drm_display_mode *adjusted_mode, | |
244 | int x, int y, | |
245 | struct drm_framebuffer *old_fb); | |
ee7b9f93 | 246 | void (*off)(struct drm_crtc *crtc); |
e0dac65e WF |
247 | void (*write_eld)(struct drm_connector *connector, |
248 | struct drm_crtc *crtc); | |
674cf967 | 249 | void (*fdi_link_train)(struct drm_crtc *crtc); |
6067aaea | 250 | void (*init_clock_gating)(struct drm_device *dev); |
645c62a5 | 251 | void (*init_pch_clock_gating)(struct drm_device *dev); |
8c9f3aaf JB |
252 | int (*queue_flip)(struct drm_device *dev, struct drm_crtc *crtc, |
253 | struct drm_framebuffer *fb, | |
254 | struct drm_i915_gem_object *obj); | |
17638cd6 JB |
255 | int (*update_plane)(struct drm_crtc *crtc, struct drm_framebuffer *fb, |
256 | int x, int y); | |
8d715f00 KP |
257 | void (*force_wake_get)(struct drm_i915_private *dev_priv); |
258 | void (*force_wake_put)(struct drm_i915_private *dev_priv); | |
e70236a8 JB |
259 | /* clock updates for mode set */ |
260 | /* cursor updates */ | |
261 | /* render clock increase/decrease */ | |
262 | /* display clock increase/decrease */ | |
263 | /* pll clock increase/decrease */ | |
e70236a8 JB |
264 | }; |
265 | ||
cfdf1fa2 | 266 | struct intel_device_info { |
c96c3a8c | 267 | u8 gen; |
0206e353 AJ |
268 | u8 is_mobile:1; |
269 | u8 is_i85x:1; | |
270 | u8 is_i915g:1; | |
271 | u8 is_i945gm:1; | |
272 | u8 is_g33:1; | |
273 | u8 need_gfx_hws:1; | |
274 | u8 is_g4x:1; | |
275 | u8 is_pineview:1; | |
276 | u8 is_broadwater:1; | |
277 | u8 is_crestline:1; | |
278 | u8 is_ivybridge:1; | |
70a3eb7a | 279 | u8 is_valleyview:1; |
7e508a27 | 280 | u8 has_pch_split:1; |
4cae9ae0 | 281 | u8 is_haswell:1; |
0206e353 AJ |
282 | u8 has_fbc:1; |
283 | u8 has_pipe_cxsr:1; | |
284 | u8 has_hotplug:1; | |
285 | u8 cursor_needs_physical:1; | |
286 | u8 has_overlay:1; | |
287 | u8 overlay_needs_physical:1; | |
288 | u8 supports_tv:1; | |
289 | u8 has_bsd_ring:1; | |
290 | u8 has_blt_ring:1; | |
3d29b842 | 291 | u8 has_llc:1; |
cfdf1fa2 KH |
292 | }; |
293 | ||
1d2a314c DV |
294 | #define I915_PPGTT_PD_ENTRIES 512 |
295 | #define I915_PPGTT_PT_ENTRIES 1024 | |
296 | struct i915_hw_ppgtt { | |
297 | unsigned num_pd_entries; | |
298 | struct page **pt_pages; | |
299 | uint32_t pd_offset; | |
300 | dma_addr_t *pt_dma_addr; | |
301 | dma_addr_t scratch_page_dma_addr; | |
302 | }; | |
303 | ||
b5e50c3f | 304 | enum no_fbc_reason { |
bed4a673 | 305 | FBC_NO_OUTPUT, /* no outputs enabled to compress */ |
b5e50c3f JB |
306 | FBC_STOLEN_TOO_SMALL, /* not enough space to hold compressed buffers */ |
307 | FBC_UNSUPPORTED_MODE, /* interlace or doublescanned mode */ | |
308 | FBC_MODE_TOO_LARGE, /* mode too large for compression */ | |
309 | FBC_BAD_PLANE, /* fbc not supported on plane */ | |
310 | FBC_NOT_TILED, /* buffer not tiled */ | |
9c928d16 | 311 | FBC_MULTIPLE_PIPES, /* more than one pipe active */ |
c1a9f047 | 312 | FBC_MODULE_PARAM, |
b5e50c3f JB |
313 | }; |
314 | ||
3bad0781 ZW |
315 | enum intel_pch { |
316 | PCH_IBX, /* Ibexpeak PCH */ | |
317 | PCH_CPT, /* Cougarpoint PCH */ | |
eb877ebf | 318 | PCH_LPT, /* Lynxpoint PCH */ |
3bad0781 ZW |
319 | }; |
320 | ||
b690e96c | 321 | #define QUIRK_PIPEA_FORCE (1<<0) |
435793df | 322 | #define QUIRK_LVDS_SSC_DISABLE (1<<1) |
4dca20ef | 323 | #define QUIRK_INVERT_BRIGHTNESS (1<<2) |
b690e96c | 324 | |
8be48d92 | 325 | struct intel_fbdev; |
1630fe75 | 326 | struct intel_fbc_work; |
38651674 | 327 | |
c2b9152f DV |
328 | struct intel_gmbus { |
329 | struct i2c_adapter adapter; | |
f6f808c8 | 330 | bool force_bit; |
c2b9152f | 331 | u32 reg0; |
36c785f0 | 332 | u32 gpio_reg; |
c167a6fc | 333 | struct i2c_algo_bit_data bit_algo; |
c2b9152f DV |
334 | struct drm_i915_private *dev_priv; |
335 | }; | |
336 | ||
1da177e4 | 337 | typedef struct drm_i915_private { |
673a394b EA |
338 | struct drm_device *dev; |
339 | ||
cfdf1fa2 KH |
340 | const struct intel_device_info *info; |
341 | ||
72bfa19c | 342 | int relative_constants_mode; |
ac5c4e76 | 343 | |
3043c60c | 344 | void __iomem *regs; |
9f1f46a4 DV |
345 | /** gt_fifo_count and the subsequent register write are synchronized |
346 | * with dev->struct_mutex. */ | |
347 | unsigned gt_fifo_count; | |
348 | /** forcewake_count is protected by gt_lock */ | |
349 | unsigned forcewake_count; | |
350 | /** gt_lock is also taken in irq contexts. */ | |
351 | struct spinlock gt_lock; | |
1da177e4 | 352 | |
f2c9677b | 353 | struct intel_gmbus gmbus[GMBUS_NUM_PORTS]; |
f899fc64 | 354 | |
8a8ed1f5 YS |
355 | /** gmbus_mutex protects against concurrent usage of the single hw gmbus |
356 | * controller on different i2c buses. */ | |
357 | struct mutex gmbus_mutex; | |
358 | ||
110447fc DV |
359 | /** |
360 | * Base address of the gmbus and gpio block. | |
361 | */ | |
362 | uint32_t gpio_mmio_base; | |
363 | ||
ec2a4c3f | 364 | struct pci_dev *bridge_dev; |
1ec14ad3 | 365 | struct intel_ring_buffer ring[I915_NUM_RINGS]; |
6f392d54 | 366 | uint32_t next_seqno; |
1da177e4 | 367 | |
9c8da5eb | 368 | drm_dma_handle_t *status_page_dmah; |
0a3e67a4 | 369 | uint32_t counter; |
dc7a9319 | 370 | drm_local_map_t hws_map; |
05394f39 CW |
371 | struct drm_i915_gem_object *pwrctx; |
372 | struct drm_i915_gem_object *renderctx; | |
1da177e4 | 373 | |
d7658989 JB |
374 | struct resource mch_res; |
375 | ||
a6b54f3f | 376 | unsigned int cpp; |
1da177e4 LT |
377 | int back_offset; |
378 | int front_offset; | |
379 | int current_page; | |
380 | int page_flipping; | |
1da177e4 | 381 | |
1da177e4 | 382 | atomic_t irq_received; |
1ec14ad3 CW |
383 | |
384 | /* protects the irq masks */ | |
385 | spinlock_t irq_lock; | |
57f350b6 JB |
386 | |
387 | /* DPIO indirect register protection */ | |
388 | spinlock_t dpio_lock; | |
389 | ||
ed4cb414 | 390 | /** Cached value of IMR to avoid reads in updating the bitfield */ |
7c463586 | 391 | u32 pipestat[2]; |
1ec14ad3 CW |
392 | u32 irq_mask; |
393 | u32 gt_irq_mask; | |
394 | u32 pch_irq_mask; | |
1da177e4 | 395 | |
5ca58282 JB |
396 | u32 hotplug_supported_mask; |
397 | struct work_struct hotplug_work; | |
398 | ||
1da177e4 LT |
399 | int tex_lru_log_granularity; |
400 | int allow_batchbuffer; | |
0d6aa60b | 401 | unsigned int sr01, adpa, ppcr, dvob, dvoc, lvds; |
702880f2 | 402 | int vblank_pipe; |
a3524f1b | 403 | int num_pipe; |
ee7b9f93 | 404 | int num_pch_pll; |
a6b54f3f | 405 | |
f65d9421 | 406 | /* For hangcheck timer */ |
576ae4b8 | 407 | #define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */ |
f65d9421 BG |
408 | struct timer_list hangcheck_timer; |
409 | int hangcheck_count; | |
410 | uint32_t last_acthd; | |
097354eb DV |
411 | uint32_t last_acthd_bsd; |
412 | uint32_t last_acthd_blt; | |
cbb465e7 CW |
413 | uint32_t last_instdone; |
414 | uint32_t last_instdone1; | |
f65d9421 | 415 | |
80824003 | 416 | unsigned long cfb_size; |
016b9b61 CW |
417 | unsigned int cfb_fb; |
418 | enum plane cfb_plane; | |
bed4a673 | 419 | int cfb_y; |
1630fe75 | 420 | struct intel_fbc_work *fbc_work; |
80824003 | 421 | |
8ee1c3db MG |
422 | struct intel_opregion opregion; |
423 | ||
02e792fb DV |
424 | /* overlay */ |
425 | struct intel_overlay *overlay; | |
b840d907 | 426 | bool sprite_scaling_enabled; |
02e792fb | 427 | |
79e53945 | 428 | /* LVDS info */ |
a9573556 | 429 | int backlight_level; /* restore backlight to this value */ |
47356eb6 | 430 | bool backlight_enabled; |
88631706 ML |
431 | struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */ |
432 | struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */ | |
79e53945 JB |
433 | |
434 | /* Feature bits from the VBIOS */ | |
95281e35 HE |
435 | unsigned int int_tv_support:1; |
436 | unsigned int lvds_dither:1; | |
437 | unsigned int lvds_vbt:1; | |
438 | unsigned int int_crt_support:1; | |
43565a06 | 439 | unsigned int lvds_use_ssc:1; |
abd06860 | 440 | unsigned int display_clock_mode:1; |
43565a06 | 441 | int lvds_ssc_freq; |
b0354385 TI |
442 | unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */ |
443 | unsigned int lvds_val; /* used for checking LVDS channel mode */ | |
5ceb0f9b | 444 | struct { |
9f0e7ff4 JB |
445 | int rate; |
446 | int lanes; | |
447 | int preemphasis; | |
448 | int vswing; | |
449 | ||
450 | bool initialized; | |
451 | bool support; | |
452 | int bpp; | |
453 | struct edp_power_seq pps; | |
5ceb0f9b | 454 | } edp; |
89667383 | 455 | bool no_aux_handshake; |
79e53945 | 456 | |
c1c7af60 JB |
457 | struct notifier_block lid_notifier; |
458 | ||
f899fc64 | 459 | int crt_ddc_pin; |
4b9de737 | 460 | struct drm_i915_fence_reg fence_regs[I915_MAX_NUM_FENCES]; /* assume 965 */ |
de151cf6 JB |
461 | int fence_reg_start; /* 4 if userland hasn't ioctl'd us yet */ |
462 | int num_fence_regs; /* 8 on pre-965, 16 otherwise */ | |
463 | ||
95534263 | 464 | unsigned int fsb_freq, mem_freq, is_ddr3; |
7662c8bd | 465 | |
63eeaf38 JB |
466 | spinlock_t error_lock; |
467 | struct drm_i915_error_state *first_error; | |
8a905236 | 468 | struct work_struct error_work; |
30dbf0c0 | 469 | struct completion error_completion; |
9c9fe1f8 | 470 | struct workqueue_struct *wq; |
63eeaf38 | 471 | |
e70236a8 JB |
472 | /* Display functions */ |
473 | struct drm_i915_display_funcs display; | |
474 | ||
3bad0781 ZW |
475 | /* PCH chipset type */ |
476 | enum intel_pch pch_type; | |
477 | ||
b690e96c JB |
478 | unsigned long quirks; |
479 | ||
ba8bbcf6 | 480 | /* Register state */ |
c9354c85 | 481 | bool modeset_on_lid; |
ba8bbcf6 JB |
482 | u8 saveLBB; |
483 | u32 saveDSPACNTR; | |
484 | u32 saveDSPBCNTR; | |
e948e994 | 485 | u32 saveDSPARB; |
968b503e | 486 | u32 saveHWS; |
ba8bbcf6 JB |
487 | u32 savePIPEACONF; |
488 | u32 savePIPEBCONF; | |
489 | u32 savePIPEASRC; | |
490 | u32 savePIPEBSRC; | |
491 | u32 saveFPA0; | |
492 | u32 saveFPA1; | |
493 | u32 saveDPLL_A; | |
494 | u32 saveDPLL_A_MD; | |
495 | u32 saveHTOTAL_A; | |
496 | u32 saveHBLANK_A; | |
497 | u32 saveHSYNC_A; | |
498 | u32 saveVTOTAL_A; | |
499 | u32 saveVBLANK_A; | |
500 | u32 saveVSYNC_A; | |
501 | u32 saveBCLRPAT_A; | |
5586c8bc | 502 | u32 saveTRANSACONF; |
42048781 ZW |
503 | u32 saveTRANS_HTOTAL_A; |
504 | u32 saveTRANS_HBLANK_A; | |
505 | u32 saveTRANS_HSYNC_A; | |
506 | u32 saveTRANS_VTOTAL_A; | |
507 | u32 saveTRANS_VBLANK_A; | |
508 | u32 saveTRANS_VSYNC_A; | |
0da3ea12 | 509 | u32 savePIPEASTAT; |
ba8bbcf6 JB |
510 | u32 saveDSPASTRIDE; |
511 | u32 saveDSPASIZE; | |
512 | u32 saveDSPAPOS; | |
585fb111 | 513 | u32 saveDSPAADDR; |
ba8bbcf6 JB |
514 | u32 saveDSPASURF; |
515 | u32 saveDSPATILEOFF; | |
516 | u32 savePFIT_PGM_RATIOS; | |
0eb96d6e | 517 | u32 saveBLC_HIST_CTL; |
ba8bbcf6 JB |
518 | u32 saveBLC_PWM_CTL; |
519 | u32 saveBLC_PWM_CTL2; | |
42048781 ZW |
520 | u32 saveBLC_CPU_PWM_CTL; |
521 | u32 saveBLC_CPU_PWM_CTL2; | |
ba8bbcf6 JB |
522 | u32 saveFPB0; |
523 | u32 saveFPB1; | |
524 | u32 saveDPLL_B; | |
525 | u32 saveDPLL_B_MD; | |
526 | u32 saveHTOTAL_B; | |
527 | u32 saveHBLANK_B; | |
528 | u32 saveHSYNC_B; | |
529 | u32 saveVTOTAL_B; | |
530 | u32 saveVBLANK_B; | |
531 | u32 saveVSYNC_B; | |
532 | u32 saveBCLRPAT_B; | |
5586c8bc | 533 | u32 saveTRANSBCONF; |
42048781 ZW |
534 | u32 saveTRANS_HTOTAL_B; |
535 | u32 saveTRANS_HBLANK_B; | |
536 | u32 saveTRANS_HSYNC_B; | |
537 | u32 saveTRANS_VTOTAL_B; | |
538 | u32 saveTRANS_VBLANK_B; | |
539 | u32 saveTRANS_VSYNC_B; | |
0da3ea12 | 540 | u32 savePIPEBSTAT; |
ba8bbcf6 JB |
541 | u32 saveDSPBSTRIDE; |
542 | u32 saveDSPBSIZE; | |
543 | u32 saveDSPBPOS; | |
585fb111 | 544 | u32 saveDSPBADDR; |
ba8bbcf6 JB |
545 | u32 saveDSPBSURF; |
546 | u32 saveDSPBTILEOFF; | |
585fb111 JB |
547 | u32 saveVGA0; |
548 | u32 saveVGA1; | |
549 | u32 saveVGA_PD; | |
ba8bbcf6 JB |
550 | u32 saveVGACNTRL; |
551 | u32 saveADPA; | |
552 | u32 saveLVDS; | |
585fb111 JB |
553 | u32 savePP_ON_DELAYS; |
554 | u32 savePP_OFF_DELAYS; | |
ba8bbcf6 JB |
555 | u32 saveDVOA; |
556 | u32 saveDVOB; | |
557 | u32 saveDVOC; | |
558 | u32 savePP_ON; | |
559 | u32 savePP_OFF; | |
560 | u32 savePP_CONTROL; | |
585fb111 | 561 | u32 savePP_DIVISOR; |
ba8bbcf6 JB |
562 | u32 savePFIT_CONTROL; |
563 | u32 save_palette_a[256]; | |
564 | u32 save_palette_b[256]; | |
06027f91 | 565 | u32 saveDPFC_CB_BASE; |
ba8bbcf6 JB |
566 | u32 saveFBC_CFB_BASE; |
567 | u32 saveFBC_LL_BASE; | |
568 | u32 saveFBC_CONTROL; | |
569 | u32 saveFBC_CONTROL2; | |
0da3ea12 JB |
570 | u32 saveIER; |
571 | u32 saveIIR; | |
572 | u32 saveIMR; | |
42048781 ZW |
573 | u32 saveDEIER; |
574 | u32 saveDEIMR; | |
575 | u32 saveGTIER; | |
576 | u32 saveGTIMR; | |
577 | u32 saveFDI_RXA_IMR; | |
578 | u32 saveFDI_RXB_IMR; | |
1f84e550 | 579 | u32 saveCACHE_MODE_0; |
1f84e550 | 580 | u32 saveMI_ARB_STATE; |
ba8bbcf6 JB |
581 | u32 saveSWF0[16]; |
582 | u32 saveSWF1[16]; | |
583 | u32 saveSWF2[3]; | |
584 | u8 saveMSR; | |
585 | u8 saveSR[8]; | |
123f794f | 586 | u8 saveGR[25]; |
ba8bbcf6 | 587 | u8 saveAR_INDEX; |
a59e122a | 588 | u8 saveAR[21]; |
ba8bbcf6 | 589 | u8 saveDACMASK; |
a59e122a | 590 | u8 saveCR[37]; |
4b9de737 | 591 | uint64_t saveFENCE[I915_MAX_NUM_FENCES]; |
1fd1c624 EA |
592 | u32 saveCURACNTR; |
593 | u32 saveCURAPOS; | |
594 | u32 saveCURABASE; | |
595 | u32 saveCURBCNTR; | |
596 | u32 saveCURBPOS; | |
597 | u32 saveCURBBASE; | |
598 | u32 saveCURSIZE; | |
a4fc5ed6 KP |
599 | u32 saveDP_B; |
600 | u32 saveDP_C; | |
601 | u32 saveDP_D; | |
602 | u32 savePIPEA_GMCH_DATA_M; | |
603 | u32 savePIPEB_GMCH_DATA_M; | |
604 | u32 savePIPEA_GMCH_DATA_N; | |
605 | u32 savePIPEB_GMCH_DATA_N; | |
606 | u32 savePIPEA_DP_LINK_M; | |
607 | u32 savePIPEB_DP_LINK_M; | |
608 | u32 savePIPEA_DP_LINK_N; | |
609 | u32 savePIPEB_DP_LINK_N; | |
42048781 ZW |
610 | u32 saveFDI_RXA_CTL; |
611 | u32 saveFDI_TXA_CTL; | |
612 | u32 saveFDI_RXB_CTL; | |
613 | u32 saveFDI_TXB_CTL; | |
614 | u32 savePFA_CTL_1; | |
615 | u32 savePFB_CTL_1; | |
616 | u32 savePFA_WIN_SZ; | |
617 | u32 savePFB_WIN_SZ; | |
618 | u32 savePFA_WIN_POS; | |
619 | u32 savePFB_WIN_POS; | |
5586c8bc ZW |
620 | u32 savePCH_DREF_CONTROL; |
621 | u32 saveDISP_ARB_CTL; | |
622 | u32 savePIPEA_DATA_M1; | |
623 | u32 savePIPEA_DATA_N1; | |
624 | u32 savePIPEA_LINK_M1; | |
625 | u32 savePIPEA_LINK_N1; | |
626 | u32 savePIPEB_DATA_M1; | |
627 | u32 savePIPEB_DATA_N1; | |
628 | u32 savePIPEB_LINK_M1; | |
629 | u32 savePIPEB_LINK_N1; | |
b5b72e89 | 630 | u32 saveMCHBAR_RENDER_STANDBY; |
cda2bb78 | 631 | u32 savePCH_PORT_HOTPLUG; |
673a394b EA |
632 | |
633 | struct { | |
19966754 | 634 | /** Bridge to intel-gtt-ko */ |
c64f7ba5 | 635 | const struct intel_gtt *gtt; |
19966754 | 636 | /** Memory allocator for GTT stolen memory */ |
fe669bf8 | 637 | struct drm_mm stolen; |
19966754 | 638 | /** Memory allocator for GTT */ |
673a394b | 639 | struct drm_mm gtt_space; |
93a37f20 DV |
640 | /** List of all objects in gtt_space. Used to restore gtt |
641 | * mappings on resume */ | |
642 | struct list_head gtt_list; | |
bee4a186 CW |
643 | |
644 | /** Usable portion of the GTT for GEM */ | |
645 | unsigned long gtt_start; | |
a6e0aa42 | 646 | unsigned long gtt_mappable_end; |
bee4a186 | 647 | unsigned long gtt_end; |
673a394b | 648 | |
0839ccb8 | 649 | struct io_mapping *gtt_mapping; |
ab657db1 | 650 | int gtt_mtrr; |
0839ccb8 | 651 | |
1d2a314c DV |
652 | /** PPGTT used for aliasing the PPGTT with the GTT */ |
653 | struct i915_hw_ppgtt *aliasing_ppgtt; | |
654 | ||
17250b71 | 655 | struct shrinker inactive_shrinker; |
31169714 | 656 | |
69dc4987 CW |
657 | /** |
658 | * List of objects currently involved in rendering. | |
659 | * | |
660 | * Includes buffers having the contents of their GPU caches | |
661 | * flushed, not necessarily primitives. last_rendering_seqno | |
662 | * represents when the rendering involved will be completed. | |
663 | * | |
664 | * A reference is held on the buffer while on this list. | |
665 | */ | |
666 | struct list_head active_list; | |
667 | ||
673a394b EA |
668 | /** |
669 | * List of objects which are not in the ringbuffer but which | |
670 | * still have a write_domain which needs to be flushed before | |
671 | * unbinding. | |
672 | * | |
ce44b0ea EA |
673 | * last_rendering_seqno is 0 while an object is in this list. |
674 | * | |
673a394b EA |
675 | * A reference is held on the buffer while on this list. |
676 | */ | |
677 | struct list_head flushing_list; | |
678 | ||
679 | /** | |
680 | * LRU list of objects which are not in the ringbuffer and | |
681 | * are ready to unbind, but are still in the GTT. | |
682 | * | |
ce44b0ea EA |
683 | * last_rendering_seqno is 0 while an object is in this list. |
684 | * | |
673a394b EA |
685 | * A reference is not held on the buffer while on this list, |
686 | * as merely being GTT-bound shouldn't prevent its being | |
687 | * freed, and we'll pull it off the list in the free path. | |
688 | */ | |
689 | struct list_head inactive_list; | |
690 | ||
a09ba7fa EA |
691 | /** LRU list of objects with fence regs on them. */ |
692 | struct list_head fence_list; | |
693 | ||
673a394b EA |
694 | /** |
695 | * We leave the user IRQ off as much as possible, | |
696 | * but this means that requests will finish and never | |
697 | * be retired once the system goes idle. Set a timer to | |
698 | * fire periodically while the ring is running. When it | |
699 | * fires, go retire requests. | |
700 | */ | |
701 | struct delayed_work retire_work; | |
702 | ||
ce453d81 CW |
703 | /** |
704 | * Are we in a non-interruptible section of code like | |
705 | * modesetting? | |
706 | */ | |
707 | bool interruptible; | |
708 | ||
673a394b EA |
709 | /** |
710 | * Flag if the X Server, and thus DRM, is not currently in | |
711 | * control of the device. | |
712 | * | |
713 | * This is set between LeaveVT and EnterVT. It needs to be | |
714 | * replaced with a semaphore. It also needs to be | |
715 | * transitioned away from for kernel modesetting. | |
716 | */ | |
717 | int suspended; | |
718 | ||
719 | /** | |
720 | * Flag if the hardware appears to be wedged. | |
721 | * | |
722 | * This is set when attempts to idle the device timeout. | |
25985edc | 723 | * It prevents command submission from occurring and makes |
673a394b EA |
724 | * every pending request fail |
725 | */ | |
ba1234d1 | 726 | atomic_t wedged; |
673a394b EA |
727 | |
728 | /** Bit 6 swizzling required for X tiling */ | |
729 | uint32_t bit_6_swizzle_x; | |
730 | /** Bit 6 swizzling required for Y tiling */ | |
731 | uint32_t bit_6_swizzle_y; | |
71acb5eb DA |
732 | |
733 | /* storage for physical objects */ | |
734 | struct drm_i915_gem_phys_object *phys_objs[I915_MAX_PHYS_OBJECT]; | |
9220434a | 735 | |
73aa808f | 736 | /* accounting, useful for userland debugging */ |
73aa808f | 737 | size_t gtt_total; |
6299f992 CW |
738 | size_t mappable_gtt_total; |
739 | size_t object_memory; | |
73aa808f | 740 | u32 object_count; |
673a394b | 741 | } mm; |
9b9d172d | 742 | struct sdvo_device_mapping sdvo_mappings[2]; |
a3e17eb8 ZY |
743 | /* indicate whether the LVDS_BORDER should be enabled or not */ |
744 | unsigned int lvds_border_bits; | |
1d8e1c75 CW |
745 | /* Panel fitter placement and size for Ironlake+ */ |
746 | u32 pch_pf_pos, pch_pf_size; | |
652c393a | 747 | |
27f8227b JB |
748 | struct drm_crtc *plane_to_crtc_mapping[3]; |
749 | struct drm_crtc *pipe_to_crtc_mapping[3]; | |
6b95a207 KH |
750 | wait_queue_head_t pending_flip_queue; |
751 | ||
ee7b9f93 JB |
752 | struct intel_pch_pll pch_plls[I915_NUM_PLLS]; |
753 | ||
652c393a JB |
754 | /* Reclocking support */ |
755 | bool render_reclock_avail; | |
756 | bool lvds_downclock_avail; | |
18f9ed12 ZY |
757 | /* indicates the reduced downclock for LVDS*/ |
758 | int lvds_downclock; | |
652c393a JB |
759 | struct work_struct idle_work; |
760 | struct timer_list idle_timer; | |
761 | bool busy; | |
762 | u16 orig_clock; | |
6363ee6f ZY |
763 | int child_dev_num; |
764 | struct child_device_config *child_dev; | |
a2565377 | 765 | struct drm_connector *int_lvds_connector; |
aaa6fd2a | 766 | struct drm_connector *int_edp_connector; |
f97108d1 | 767 | |
c4804411 | 768 | bool mchbar_need_disable; |
f97108d1 | 769 | |
4912d041 BW |
770 | struct work_struct rps_work; |
771 | spinlock_t rps_lock; | |
772 | u32 pm_iir; | |
773 | ||
f97108d1 JB |
774 | u8 cur_delay; |
775 | u8 min_delay; | |
776 | u8 max_delay; | |
7648fa99 JB |
777 | u8 fmax; |
778 | u8 fstart; | |
779 | ||
05394f39 CW |
780 | u64 last_count1; |
781 | unsigned long last_time1; | |
4ed0b577 | 782 | unsigned long chipset_power; |
05394f39 CW |
783 | u64 last_count2; |
784 | struct timespec last_time2; | |
785 | unsigned long gfx_power; | |
786 | int c_m; | |
787 | int r_t; | |
788 | u8 corr; | |
7648fa99 | 789 | spinlock_t *mchdev_lock; |
b5e50c3f JB |
790 | |
791 | enum no_fbc_reason no_fbc_reason; | |
38651674 | 792 | |
20bf377e JB |
793 | struct drm_mm_node *compressed_fb; |
794 | struct drm_mm_node *compressed_llb; | |
34dc4d44 | 795 | |
ae681d96 CW |
796 | unsigned long last_gpu_reset; |
797 | ||
8be48d92 DA |
798 | /* list of fbdev register on this device */ |
799 | struct intel_fbdev *fbdev; | |
e953fd7b | 800 | |
aaa6fd2a MG |
801 | struct backlight_device *backlight; |
802 | ||
e953fd7b | 803 | struct drm_property *broadcast_rgb_property; |
3f43c48d | 804 | struct drm_property *force_audio_property; |
1da177e4 LT |
805 | } drm_i915_private_t; |
806 | ||
b1d7e4b4 WF |
807 | enum hdmi_force_audio { |
808 | HDMI_AUDIO_OFF_DVI = -2, /* no aux data for HDMI-DVI converter */ | |
809 | HDMI_AUDIO_OFF, /* force turn off HDMI audio */ | |
810 | HDMI_AUDIO_AUTO, /* trust EDID */ | |
811 | HDMI_AUDIO_ON, /* force turn on HDMI audio */ | |
812 | }; | |
813 | ||
93dfb40c CW |
814 | enum i915_cache_level { |
815 | I915_CACHE_NONE, | |
816 | I915_CACHE_LLC, | |
817 | I915_CACHE_LLC_MLC, /* gen6+ */ | |
818 | }; | |
819 | ||
673a394b | 820 | struct drm_i915_gem_object { |
c397b908 | 821 | struct drm_gem_object base; |
673a394b EA |
822 | |
823 | /** Current space allocated to this object in the GTT, if any. */ | |
824 | struct drm_mm_node *gtt_space; | |
93a37f20 | 825 | struct list_head gtt_list; |
673a394b EA |
826 | |
827 | /** This object's place on the active/flushing/inactive lists */ | |
69dc4987 CW |
828 | struct list_head ring_list; |
829 | struct list_head mm_list; | |
99fcb766 DV |
830 | /** This object's place on GPU write list */ |
831 | struct list_head gpu_write_list; | |
432e58ed CW |
832 | /** This object's place in the batchbuffer or on the eviction list */ |
833 | struct list_head exec_list; | |
673a394b EA |
834 | |
835 | /** | |
836 | * This is set if the object is on the active or flushing lists | |
837 | * (has pending rendering), and is not set if it's on inactive (ready | |
838 | * to be unbound). | |
839 | */ | |
0206e353 | 840 | unsigned int active:1; |
673a394b EA |
841 | |
842 | /** | |
843 | * This is set if the object has been written to since last bound | |
844 | * to the GTT | |
845 | */ | |
0206e353 | 846 | unsigned int dirty:1; |
778c3544 | 847 | |
87ca9c8a CW |
848 | /** |
849 | * This is set if the object has been written to since the last | |
850 | * GPU flush. | |
851 | */ | |
0206e353 | 852 | unsigned int pending_gpu_write:1; |
87ca9c8a | 853 | |
778c3544 DV |
854 | /** |
855 | * Fence register bits (if any) for this object. Will be set | |
856 | * as needed when mapped into the GTT. | |
857 | * Protected by dev->struct_mutex. | |
778c3544 | 858 | */ |
4b9de737 | 859 | signed int fence_reg:I915_MAX_NUM_FENCE_BITS; |
778c3544 | 860 | |
778c3544 DV |
861 | /** |
862 | * Advice: are the backing pages purgeable? | |
863 | */ | |
0206e353 | 864 | unsigned int madv:2; |
778c3544 | 865 | |
778c3544 DV |
866 | /** |
867 | * Current tiling mode for the object. | |
868 | */ | |
0206e353 | 869 | unsigned int tiling_mode:2; |
5d82e3e6 CW |
870 | /** |
871 | * Whether the tiling parameters for the currently associated fence | |
872 | * register have changed. Note that for the purposes of tracking | |
873 | * tiling changes we also treat the unfenced register, the register | |
874 | * slot that the object occupies whilst it executes a fenced | |
875 | * command (such as BLT on gen2/3), as a "fence". | |
876 | */ | |
877 | unsigned int fence_dirty:1; | |
778c3544 DV |
878 | |
879 | /** How many users have pinned this object in GTT space. The following | |
880 | * users can each hold at most one reference: pwrite/pread, pin_ioctl | |
881 | * (via user_pin_count), execbuffer (objects are not allowed multiple | |
882 | * times for the same batchbuffer), and the framebuffer code. When | |
883 | * switching/pageflipping, the framebuffer code has at most two buffers | |
884 | * pinned per crtc. | |
885 | * | |
886 | * In the worst case this is 1 + 1 + 1 + 2*2 = 7. That would fit into 3 | |
887 | * bits with absolutely no headroom. So use 4 bits. */ | |
0206e353 | 888 | unsigned int pin_count:4; |
778c3544 | 889 | #define DRM_I915_GEM_OBJECT_MAX_PIN_COUNT 0xf |
673a394b | 890 | |
75e9e915 DV |
891 | /** |
892 | * Is the object at the current location in the gtt mappable and | |
893 | * fenceable? Used to avoid costly recalculations. | |
894 | */ | |
0206e353 | 895 | unsigned int map_and_fenceable:1; |
75e9e915 | 896 | |
fb7d516a DV |
897 | /** |
898 | * Whether the current gtt mapping needs to be mappable (and isn't just | |
899 | * mappable by accident). Track pin and fault separate for a more | |
900 | * accurate mappable working set. | |
901 | */ | |
0206e353 AJ |
902 | unsigned int fault_mappable:1; |
903 | unsigned int pin_mappable:1; | |
fb7d516a | 904 | |
caea7476 CW |
905 | /* |
906 | * Is the GPU currently using a fence to access this buffer, | |
907 | */ | |
908 | unsigned int pending_fenced_gpu_access:1; | |
909 | unsigned int fenced_gpu_access:1; | |
910 | ||
93dfb40c CW |
911 | unsigned int cache_level:2; |
912 | ||
7bddb01f | 913 | unsigned int has_aliasing_ppgtt_mapping:1; |
74898d7e | 914 | unsigned int has_global_gtt_mapping:1; |
7bddb01f | 915 | |
856fa198 | 916 | struct page **pages; |
673a394b | 917 | |
185cbcb3 DV |
918 | /** |
919 | * DMAR support | |
920 | */ | |
921 | struct scatterlist *sg_list; | |
922 | int num_sg; | |
923 | ||
67731b87 CW |
924 | /** |
925 | * Used for performing relocations during execbuffer insertion. | |
926 | */ | |
927 | struct hlist_node exec_node; | |
928 | unsigned long exec_handle; | |
6fe4f140 | 929 | struct drm_i915_gem_exec_object2 *exec_entry; |
67731b87 | 930 | |
673a394b EA |
931 | /** |
932 | * Current offset of the object in GTT space. | |
933 | * | |
934 | * This is the same as gtt_space->start | |
935 | */ | |
936 | uint32_t gtt_offset; | |
e67b8ce1 | 937 | |
caea7476 CW |
938 | struct intel_ring_buffer *ring; |
939 | ||
1c293ea3 CW |
940 | /** Breadcrumb of last rendering to the buffer. */ |
941 | uint32_t last_rendering_seqno; | |
caea7476 CW |
942 | /** Breadcrumb of last fenced GPU access to the buffer. */ |
943 | uint32_t last_fenced_seqno; | |
673a394b | 944 | |
778c3544 | 945 | /** Current tiling stride for the object, if it's tiled. */ |
de151cf6 | 946 | uint32_t stride; |
673a394b | 947 | |
280b713b | 948 | /** Record of address bit 17 of each page at last unbind. */ |
d312ec25 | 949 | unsigned long *bit_17; |
280b713b | 950 | |
79e53945 JB |
951 | /** User space pin count and filp owning the pin */ |
952 | uint32_t user_pin_count; | |
953 | struct drm_file *pin_filp; | |
71acb5eb DA |
954 | |
955 | /** for phy allocated objects */ | |
956 | struct drm_i915_gem_phys_object *phys_obj; | |
b70d11da | 957 | |
6b95a207 KH |
958 | /** |
959 | * Number of crtcs where this object is currently the fb, but | |
960 | * will be page flipped away on the next vblank. When it | |
961 | * reaches 0, dev_priv->pending_flip_queue will be woken up. | |
962 | */ | |
963 | atomic_t pending_flip; | |
673a394b EA |
964 | }; |
965 | ||
62b8b215 | 966 | #define to_intel_bo(x) container_of(x, struct drm_i915_gem_object, base) |
23010e43 | 967 | |
673a394b EA |
968 | /** |
969 | * Request queue structure. | |
970 | * | |
971 | * The request queue allows us to note sequence numbers that have been emitted | |
972 | * and may be associated with active buffers to be retired. | |
973 | * | |
974 | * By keeping this list, we can avoid having to do questionable | |
975 | * sequence-number comparisons on buffer last_rendering_seqnos, and associate | |
976 | * an emission time with seqnos for tracking how far ahead of the GPU we are. | |
977 | */ | |
978 | struct drm_i915_gem_request { | |
852835f3 ZN |
979 | /** On Which ring this request was generated */ |
980 | struct intel_ring_buffer *ring; | |
981 | ||
673a394b EA |
982 | /** GEM sequence number associated with this request. */ |
983 | uint32_t seqno; | |
984 | ||
a71d8d94 CW |
985 | /** Postion in the ringbuffer of the end of the request */ |
986 | u32 tail; | |
987 | ||
673a394b EA |
988 | /** Time at which this request was emitted, in jiffies. */ |
989 | unsigned long emitted_jiffies; | |
990 | ||
b962442e | 991 | /** global list entry for this request */ |
673a394b | 992 | struct list_head list; |
b962442e | 993 | |
f787a5f5 | 994 | struct drm_i915_file_private *file_priv; |
b962442e EA |
995 | /** file_priv list entry for this request */ |
996 | struct list_head client_list; | |
673a394b EA |
997 | }; |
998 | ||
999 | struct drm_i915_file_private { | |
1000 | struct { | |
1c25595f | 1001 | struct spinlock lock; |
b962442e | 1002 | struct list_head request_list; |
673a394b EA |
1003 | } mm; |
1004 | }; | |
1005 | ||
cae5852d ZN |
1006 | #define INTEL_INFO(dev) (((struct drm_i915_private *) (dev)->dev_private)->info) |
1007 | ||
1008 | #define IS_I830(dev) ((dev)->pci_device == 0x3577) | |
1009 | #define IS_845G(dev) ((dev)->pci_device == 0x2562) | |
1010 | #define IS_I85X(dev) (INTEL_INFO(dev)->is_i85x) | |
1011 | #define IS_I865G(dev) ((dev)->pci_device == 0x2572) | |
1012 | #define IS_I915G(dev) (INTEL_INFO(dev)->is_i915g) | |
1013 | #define IS_I915GM(dev) ((dev)->pci_device == 0x2592) | |
1014 | #define IS_I945G(dev) ((dev)->pci_device == 0x2772) | |
1015 | #define IS_I945GM(dev) (INTEL_INFO(dev)->is_i945gm) | |
1016 | #define IS_BROADWATER(dev) (INTEL_INFO(dev)->is_broadwater) | |
1017 | #define IS_CRESTLINE(dev) (INTEL_INFO(dev)->is_crestline) | |
1018 | #define IS_GM45(dev) ((dev)->pci_device == 0x2A42) | |
1019 | #define IS_G4X(dev) (INTEL_INFO(dev)->is_g4x) | |
1020 | #define IS_PINEVIEW_G(dev) ((dev)->pci_device == 0xa001) | |
1021 | #define IS_PINEVIEW_M(dev) ((dev)->pci_device == 0xa011) | |
1022 | #define IS_PINEVIEW(dev) (INTEL_INFO(dev)->is_pineview) | |
1023 | #define IS_G33(dev) (INTEL_INFO(dev)->is_g33) | |
1024 | #define IS_IRONLAKE_D(dev) ((dev)->pci_device == 0x0042) | |
1025 | #define IS_IRONLAKE_M(dev) ((dev)->pci_device == 0x0046) | |
4b65177b | 1026 | #define IS_IVYBRIDGE(dev) (INTEL_INFO(dev)->is_ivybridge) |
70a3eb7a | 1027 | #define IS_VALLEYVIEW(dev) (INTEL_INFO(dev)->is_valleyview) |
4cae9ae0 | 1028 | #define IS_HASWELL(dev) (INTEL_INFO(dev)->is_haswell) |
cae5852d ZN |
1029 | #define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile) |
1030 | ||
85436696 JB |
1031 | /* |
1032 | * The genX designation typically refers to the render engine, so render | |
1033 | * capability related checks should use IS_GEN, while display and other checks | |
1034 | * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular | |
1035 | * chips, etc.). | |
1036 | */ | |
cae5852d ZN |
1037 | #define IS_GEN2(dev) (INTEL_INFO(dev)->gen == 2) |
1038 | #define IS_GEN3(dev) (INTEL_INFO(dev)->gen == 3) | |
1039 | #define IS_GEN4(dev) (INTEL_INFO(dev)->gen == 4) | |
1040 | #define IS_GEN5(dev) (INTEL_INFO(dev)->gen == 5) | |
1041 | #define IS_GEN6(dev) (INTEL_INFO(dev)->gen == 6) | |
85436696 | 1042 | #define IS_GEN7(dev) (INTEL_INFO(dev)->gen == 7) |
cae5852d ZN |
1043 | |
1044 | #define HAS_BSD(dev) (INTEL_INFO(dev)->has_bsd_ring) | |
1045 | #define HAS_BLT(dev) (INTEL_INFO(dev)->has_blt_ring) | |
3d29b842 | 1046 | #define HAS_LLC(dev) (INTEL_INFO(dev)->has_llc) |
cae5852d ZN |
1047 | #define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws) |
1048 | ||
1d2a314c DV |
1049 | #define HAS_ALIASING_PPGTT(dev) (INTEL_INFO(dev)->gen >=6) |
1050 | ||
05394f39 | 1051 | #define HAS_OVERLAY(dev) (INTEL_INFO(dev)->has_overlay) |
cae5852d ZN |
1052 | #define OVERLAY_NEEDS_PHYSICAL(dev) (INTEL_INFO(dev)->overlay_needs_physical) |
1053 | ||
1054 | /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte | |
1055 | * rows, which changed the alignment requirements and fence programming. | |
1056 | */ | |
1057 | #define HAS_128_BYTE_Y_TILING(dev) (!IS_GEN2(dev) && !(IS_I915G(dev) || \ | |
1058 | IS_I915GM(dev))) | |
1059 | #define SUPPORTS_DIGITAL_OUTPUTS(dev) (!IS_GEN2(dev) && !IS_PINEVIEW(dev)) | |
1060 | #define SUPPORTS_INTEGRATED_HDMI(dev) (IS_G4X(dev) || IS_GEN5(dev)) | |
1061 | #define SUPPORTS_INTEGRATED_DP(dev) (IS_G4X(dev) || IS_GEN5(dev)) | |
1062 | #define SUPPORTS_EDP(dev) (IS_IRONLAKE_M(dev)) | |
1063 | #define SUPPORTS_TV(dev) (INTEL_INFO(dev)->supports_tv) | |
1064 | #define I915_HAS_HOTPLUG(dev) (INTEL_INFO(dev)->has_hotplug) | |
1065 | /* dsparb controlled by hw only */ | |
1066 | #define DSPARB_HWCONTROL(dev) (IS_G4X(dev) || IS_IRONLAKE(dev)) | |
1067 | ||
1068 | #define HAS_FW_BLC(dev) (INTEL_INFO(dev)->gen > 2) | |
1069 | #define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr) | |
1070 | #define I915_HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc) | |
cae5852d | 1071 | |
7e508a27 | 1072 | #define HAS_PCH_SPLIT(dev) (INTEL_INFO(dev)->has_pch_split) |
eceae481 | 1073 | #define HAS_PIPE_CONTROL(dev) (INTEL_INFO(dev)->gen >= 5) |
cae5852d ZN |
1074 | |
1075 | #define INTEL_PCH_TYPE(dev) (((struct drm_i915_private *)(dev)->dev_private)->pch_type) | |
eb877ebf | 1076 | #define HAS_PCH_LPT(dev) (INTEL_PCH_TYPE(dev) == PCH_LPT) |
cae5852d ZN |
1077 | #define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT) |
1078 | #define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX) | |
1079 | ||
05394f39 CW |
1080 | #include "i915_trace.h" |
1081 | ||
83b7f9ac ED |
1082 | /** |
1083 | * RC6 is a special power stage which allows the GPU to enter an very | |
1084 | * low-voltage mode when idle, using down to 0V while at this stage. This | |
1085 | * stage is entered automatically when the GPU is idle when RC6 support is | |
1086 | * enabled, and as soon as new workload arises GPU wakes up automatically as well. | |
1087 | * | |
1088 | * There are different RC6 modes available in Intel GPU, which differentiate | |
1089 | * among each other with the latency required to enter and leave RC6 and | |
1090 | * voltage consumed by the GPU in different states. | |
1091 | * | |
1092 | * The combination of the following flags define which states GPU is allowed | |
1093 | * to enter, while RC6 is the normal RC6 state, RC6p is the deep RC6, and | |
1094 | * RC6pp is deepest RC6. Their support by hardware varies according to the | |
1095 | * GPU, BIOS, chipset and platform. RC6 is usually the safest one and the one | |
1096 | * which brings the most power savings; deeper states save more power, but | |
1097 | * require higher latency to switch to and wake up. | |
1098 | */ | |
1099 | #define INTEL_RC6_ENABLE (1<<0) | |
1100 | #define INTEL_RC6p_ENABLE (1<<1) | |
1101 | #define INTEL_RC6pp_ENABLE (1<<2) | |
1102 | ||
c153f45f | 1103 | extern struct drm_ioctl_desc i915_ioctls[]; |
b3a83639 | 1104 | extern int i915_max_ioctl; |
a35d9d3c BW |
1105 | extern unsigned int i915_fbpercrtc __always_unused; |
1106 | extern int i915_panel_ignore_lid __read_mostly; | |
1107 | extern unsigned int i915_powersave __read_mostly; | |
f45b5557 | 1108 | extern int i915_semaphores __read_mostly; |
a35d9d3c | 1109 | extern unsigned int i915_lvds_downclock __read_mostly; |
121d527a | 1110 | extern int i915_lvds_channel_mode __read_mostly; |
4415e63b | 1111 | extern int i915_panel_use_ssc __read_mostly; |
a35d9d3c | 1112 | extern int i915_vbt_sdvo_panel_type __read_mostly; |
c0f372b3 | 1113 | extern int i915_enable_rc6 __read_mostly; |
4415e63b | 1114 | extern int i915_enable_fbc __read_mostly; |
a35d9d3c | 1115 | extern bool i915_enable_hangcheck __read_mostly; |
650dc07e | 1116 | extern int i915_enable_ppgtt __read_mostly; |
b3a83639 | 1117 | |
6a9ee8af DA |
1118 | extern int i915_suspend(struct drm_device *dev, pm_message_t state); |
1119 | extern int i915_resume(struct drm_device *dev); | |
7c1c2871 DA |
1120 | extern int i915_master_create(struct drm_device *dev, struct drm_master *master); |
1121 | extern void i915_master_destroy(struct drm_device *dev, struct drm_master *master); | |
1122 | ||
1da177e4 | 1123 | /* i915_dma.c */ |
84b1fd10 | 1124 | extern void i915_kernel_lost_context(struct drm_device * dev); |
22eae947 | 1125 | extern int i915_driver_load(struct drm_device *, unsigned long flags); |
ba8bbcf6 | 1126 | extern int i915_driver_unload(struct drm_device *); |
673a394b | 1127 | extern int i915_driver_open(struct drm_device *dev, struct drm_file *file_priv); |
84b1fd10 | 1128 | extern void i915_driver_lastclose(struct drm_device * dev); |
6c340eac EA |
1129 | extern void i915_driver_preclose(struct drm_device *dev, |
1130 | struct drm_file *file_priv); | |
673a394b EA |
1131 | extern void i915_driver_postclose(struct drm_device *dev, |
1132 | struct drm_file *file_priv); | |
84b1fd10 | 1133 | extern int i915_driver_device_is_agp(struct drm_device * dev); |
c43b5634 | 1134 | #ifdef CONFIG_COMPAT |
0d6aa60b DA |
1135 | extern long i915_compat_ioctl(struct file *filp, unsigned int cmd, |
1136 | unsigned long arg); | |
c43b5634 | 1137 | #endif |
673a394b | 1138 | extern int i915_emit_box(struct drm_device *dev, |
c4e7a414 CW |
1139 | struct drm_clip_rect *box, |
1140 | int DR1, int DR4); | |
f803aa55 | 1141 | extern int i915_reset(struct drm_device *dev, u8 flags); |
7648fa99 JB |
1142 | extern unsigned long i915_chipset_val(struct drm_i915_private *dev_priv); |
1143 | extern unsigned long i915_mch_val(struct drm_i915_private *dev_priv); | |
1144 | extern unsigned long i915_gfx_val(struct drm_i915_private *dev_priv); | |
1145 | extern void i915_update_gfx_val(struct drm_i915_private *dev_priv); | |
1146 | ||
af6061af | 1147 | |
1da177e4 | 1148 | /* i915_irq.c */ |
f65d9421 | 1149 | void i915_hangcheck_elapsed(unsigned long data); |
527f9e90 | 1150 | void i915_handle_error(struct drm_device *dev, bool wedged); |
c153f45f EA |
1151 | extern int i915_irq_emit(struct drm_device *dev, void *data, |
1152 | struct drm_file *file_priv); | |
1153 | extern int i915_irq_wait(struct drm_device *dev, void *data, | |
1154 | struct drm_file *file_priv); | |
1da177e4 | 1155 | |
f71d4af4 | 1156 | extern void intel_irq_init(struct drm_device *dev); |
b1f14ad0 | 1157 | |
c153f45f EA |
1158 | extern int i915_vblank_pipe_set(struct drm_device *dev, void *data, |
1159 | struct drm_file *file_priv); | |
1160 | extern int i915_vblank_pipe_get(struct drm_device *dev, void *data, | |
1161 | struct drm_file *file_priv); | |
1162 | extern int i915_vblank_swap(struct drm_device *dev, void *data, | |
1163 | struct drm_file *file_priv); | |
1da177e4 | 1164 | |
7c463586 KP |
1165 | void |
1166 | i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask); | |
1167 | ||
1168 | void | |
1169 | i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask); | |
1170 | ||
0206e353 | 1171 | void intel_enable_asle(struct drm_device *dev); |
01c66889 | 1172 | |
3bd3c932 CW |
1173 | #ifdef CONFIG_DEBUG_FS |
1174 | extern void i915_destroy_error_state(struct drm_device *dev); | |
1175 | #else | |
1176 | #define i915_destroy_error_state(x) | |
1177 | #endif | |
1178 | ||
7c463586 | 1179 | |
673a394b EA |
1180 | /* i915_gem.c */ |
1181 | int i915_gem_init_ioctl(struct drm_device *dev, void *data, | |
1182 | struct drm_file *file_priv); | |
1183 | int i915_gem_create_ioctl(struct drm_device *dev, void *data, | |
1184 | struct drm_file *file_priv); | |
1185 | int i915_gem_pread_ioctl(struct drm_device *dev, void *data, | |
1186 | struct drm_file *file_priv); | |
1187 | int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data, | |
1188 | struct drm_file *file_priv); | |
1189 | int i915_gem_mmap_ioctl(struct drm_device *dev, void *data, | |
1190 | struct drm_file *file_priv); | |
de151cf6 JB |
1191 | int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data, |
1192 | struct drm_file *file_priv); | |
673a394b EA |
1193 | int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data, |
1194 | struct drm_file *file_priv); | |
1195 | int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data, | |
1196 | struct drm_file *file_priv); | |
1197 | int i915_gem_execbuffer(struct drm_device *dev, void *data, | |
1198 | struct drm_file *file_priv); | |
76446cac JB |
1199 | int i915_gem_execbuffer2(struct drm_device *dev, void *data, |
1200 | struct drm_file *file_priv); | |
673a394b EA |
1201 | int i915_gem_pin_ioctl(struct drm_device *dev, void *data, |
1202 | struct drm_file *file_priv); | |
1203 | int i915_gem_unpin_ioctl(struct drm_device *dev, void *data, | |
1204 | struct drm_file *file_priv); | |
1205 | int i915_gem_busy_ioctl(struct drm_device *dev, void *data, | |
1206 | struct drm_file *file_priv); | |
1207 | int i915_gem_throttle_ioctl(struct drm_device *dev, void *data, | |
1208 | struct drm_file *file_priv); | |
3ef94daa CW |
1209 | int i915_gem_madvise_ioctl(struct drm_device *dev, void *data, |
1210 | struct drm_file *file_priv); | |
673a394b EA |
1211 | int i915_gem_entervt_ioctl(struct drm_device *dev, void *data, |
1212 | struct drm_file *file_priv); | |
1213 | int i915_gem_leavevt_ioctl(struct drm_device *dev, void *data, | |
1214 | struct drm_file *file_priv); | |
1215 | int i915_gem_set_tiling(struct drm_device *dev, void *data, | |
1216 | struct drm_file *file_priv); | |
1217 | int i915_gem_get_tiling(struct drm_device *dev, void *data, | |
1218 | struct drm_file *file_priv); | |
5a125c3c EA |
1219 | int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data, |
1220 | struct drm_file *file_priv); | |
673a394b | 1221 | void i915_gem_load(struct drm_device *dev); |
673a394b | 1222 | int i915_gem_init_object(struct drm_gem_object *obj); |
db53a302 | 1223 | int __must_check i915_gem_flush_ring(struct intel_ring_buffer *ring, |
88241785 CW |
1224 | uint32_t invalidate_domains, |
1225 | uint32_t flush_domains); | |
05394f39 CW |
1226 | struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev, |
1227 | size_t size); | |
673a394b | 1228 | void i915_gem_free_object(struct drm_gem_object *obj); |
2021746e CW |
1229 | int __must_check i915_gem_object_pin(struct drm_i915_gem_object *obj, |
1230 | uint32_t alignment, | |
1231 | bool map_and_fenceable); | |
05394f39 | 1232 | void i915_gem_object_unpin(struct drm_i915_gem_object *obj); |
2021746e | 1233 | int __must_check i915_gem_object_unbind(struct drm_i915_gem_object *obj); |
05394f39 | 1234 | void i915_gem_release_mmap(struct drm_i915_gem_object *obj); |
673a394b | 1235 | void i915_gem_lastclose(struct drm_device *dev); |
f787a5f5 | 1236 | |
54cf91dc | 1237 | int __must_check i915_mutex_lock_interruptible(struct drm_device *dev); |
ce453d81 | 1238 | int __must_check i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj); |
2911a35b BW |
1239 | int i915_gem_object_sync(struct drm_i915_gem_object *obj, |
1240 | struct intel_ring_buffer *to); | |
54cf91dc | 1241 | void i915_gem_object_move_to_active(struct drm_i915_gem_object *obj, |
1ec14ad3 CW |
1242 | struct intel_ring_buffer *ring, |
1243 | u32 seqno); | |
54cf91dc | 1244 | |
ff72145b DA |
1245 | int i915_gem_dumb_create(struct drm_file *file_priv, |
1246 | struct drm_device *dev, | |
1247 | struct drm_mode_create_dumb *args); | |
1248 | int i915_gem_mmap_gtt(struct drm_file *file_priv, struct drm_device *dev, | |
1249 | uint32_t handle, uint64_t *offset); | |
1250 | int i915_gem_dumb_destroy(struct drm_file *file_priv, struct drm_device *dev, | |
0206e353 | 1251 | uint32_t handle); |
f787a5f5 CW |
1252 | /** |
1253 | * Returns true if seq1 is later than seq2. | |
1254 | */ | |
1255 | static inline bool | |
1256 | i915_seqno_passed(uint32_t seq1, uint32_t seq2) | |
1257 | { | |
1258 | return (int32_t)(seq1 - seq2) >= 0; | |
1259 | } | |
1260 | ||
53d227f2 | 1261 | u32 i915_gem_next_request_seqno(struct intel_ring_buffer *ring); |
54cf91dc | 1262 | |
06d98131 | 1263 | int __must_check i915_gem_object_get_fence(struct drm_i915_gem_object *obj); |
d9e86c0e | 1264 | int __must_check i915_gem_object_put_fence(struct drm_i915_gem_object *obj); |
2021746e | 1265 | |
9a5a53b3 | 1266 | static inline bool |
1690e1eb CW |
1267 | i915_gem_object_pin_fence(struct drm_i915_gem_object *obj) |
1268 | { | |
1269 | if (obj->fence_reg != I915_FENCE_REG_NONE) { | |
1270 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; | |
1271 | dev_priv->fence_regs[obj->fence_reg].pin_count++; | |
9a5a53b3 CW |
1272 | return true; |
1273 | } else | |
1274 | return false; | |
1690e1eb CW |
1275 | } |
1276 | ||
1277 | static inline void | |
1278 | i915_gem_object_unpin_fence(struct drm_i915_gem_object *obj) | |
1279 | { | |
1280 | if (obj->fence_reg != I915_FENCE_REG_NONE) { | |
1281 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; | |
1282 | dev_priv->fence_regs[obj->fence_reg].pin_count--; | |
1283 | } | |
1284 | } | |
1285 | ||
b09a1fec | 1286 | void i915_gem_retire_requests(struct drm_device *dev); |
a71d8d94 CW |
1287 | void i915_gem_retire_requests_ring(struct intel_ring_buffer *ring); |
1288 | ||
069efc1d | 1289 | void i915_gem_reset(struct drm_device *dev); |
05394f39 | 1290 | void i915_gem_clflush_object(struct drm_i915_gem_object *obj); |
2021746e CW |
1291 | int __must_check i915_gem_object_set_domain(struct drm_i915_gem_object *obj, |
1292 | uint32_t read_domains, | |
1293 | uint32_t write_domain); | |
a8198eea | 1294 | int __must_check i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj); |
1070a42b | 1295 | int __must_check i915_gem_init(struct drm_device *dev); |
f691e2f4 DV |
1296 | int __must_check i915_gem_init_hw(struct drm_device *dev); |
1297 | void i915_gem_init_swizzling(struct drm_device *dev); | |
e21af88d | 1298 | void i915_gem_init_ppgtt(struct drm_device *dev); |
79e53945 | 1299 | void i915_gem_cleanup_ringbuffer(struct drm_device *dev); |
b2da9fe5 | 1300 | int __must_check i915_gpu_idle(struct drm_device *dev); |
2021746e | 1301 | int __must_check i915_gem_idle(struct drm_device *dev); |
db53a302 CW |
1302 | int __must_check i915_add_request(struct intel_ring_buffer *ring, |
1303 | struct drm_file *file, | |
1304 | struct drm_i915_gem_request *request); | |
1305 | int __must_check i915_wait_request(struct intel_ring_buffer *ring, | |
b2da9fe5 | 1306 | uint32_t seqno); |
de151cf6 | 1307 | int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf); |
2021746e CW |
1308 | int __must_check |
1309 | i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, | |
1310 | bool write); | |
1311 | int __must_check | |
dabdfe02 CW |
1312 | i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write); |
1313 | int __must_check | |
2da3b9b9 CW |
1314 | i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj, |
1315 | u32 alignment, | |
2021746e | 1316 | struct intel_ring_buffer *pipelined); |
71acb5eb | 1317 | int i915_gem_attach_phys_object(struct drm_device *dev, |
05394f39 | 1318 | struct drm_i915_gem_object *obj, |
6eeefaf3 CW |
1319 | int id, |
1320 | int align); | |
71acb5eb | 1321 | void i915_gem_detach_phys_object(struct drm_device *dev, |
05394f39 | 1322 | struct drm_i915_gem_object *obj); |
71acb5eb | 1323 | void i915_gem_free_all_phys_object(struct drm_device *dev); |
05394f39 | 1324 | void i915_gem_release(struct drm_device *dev, struct drm_file *file); |
673a394b | 1325 | |
467cffba | 1326 | uint32_t |
e28f8711 CW |
1327 | i915_gem_get_unfenced_gtt_alignment(struct drm_device *dev, |
1328 | uint32_t size, | |
1329 | int tiling_mode); | |
467cffba | 1330 | |
e4ffd173 CW |
1331 | int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj, |
1332 | enum i915_cache_level cache_level); | |
1333 | ||
76aaf220 | 1334 | /* i915_gem_gtt.c */ |
1d2a314c DV |
1335 | int __must_check i915_gem_init_aliasing_ppgtt(struct drm_device *dev); |
1336 | void i915_gem_cleanup_aliasing_ppgtt(struct drm_device *dev); | |
7bddb01f DV |
1337 | void i915_ppgtt_bind_object(struct i915_hw_ppgtt *ppgtt, |
1338 | struct drm_i915_gem_object *obj, | |
1339 | enum i915_cache_level cache_level); | |
1340 | void i915_ppgtt_unbind_object(struct i915_hw_ppgtt *ppgtt, | |
1341 | struct drm_i915_gem_object *obj); | |
1d2a314c | 1342 | |
76aaf220 | 1343 | void i915_gem_restore_gtt_mappings(struct drm_device *dev); |
74163907 DV |
1344 | int __must_check i915_gem_gtt_prepare_object(struct drm_i915_gem_object *obj); |
1345 | void i915_gem_gtt_bind_object(struct drm_i915_gem_object *obj, | |
e4ffd173 | 1346 | enum i915_cache_level cache_level); |
05394f39 | 1347 | void i915_gem_gtt_unbind_object(struct drm_i915_gem_object *obj); |
74163907 | 1348 | void i915_gem_gtt_finish_object(struct drm_i915_gem_object *obj); |
644ec02b DV |
1349 | void i915_gem_init_global_gtt(struct drm_device *dev, |
1350 | unsigned long start, | |
1351 | unsigned long mappable_end, | |
1352 | unsigned long end); | |
76aaf220 | 1353 | |
b47eb4a2 | 1354 | /* i915_gem_evict.c */ |
2021746e CW |
1355 | int __must_check i915_gem_evict_something(struct drm_device *dev, int min_size, |
1356 | unsigned alignment, bool mappable); | |
a39d7efc | 1357 | int i915_gem_evict_everything(struct drm_device *dev, bool purgeable_only); |
b47eb4a2 | 1358 | |
9797fbfb CW |
1359 | /* i915_gem_stolen.c */ |
1360 | int i915_gem_init_stolen(struct drm_device *dev); | |
1361 | void i915_gem_cleanup_stolen(struct drm_device *dev); | |
1362 | ||
673a394b EA |
1363 | /* i915_gem_tiling.c */ |
1364 | void i915_gem_detect_bit_6_swizzle(struct drm_device *dev); | |
05394f39 CW |
1365 | void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj); |
1366 | void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj); | |
673a394b EA |
1367 | |
1368 | /* i915_gem_debug.c */ | |
05394f39 | 1369 | void i915_gem_dump_object(struct drm_i915_gem_object *obj, int len, |
673a394b | 1370 | const char *where, uint32_t mark); |
23bc5982 CW |
1371 | #if WATCH_LISTS |
1372 | int i915_verify_lists(struct drm_device *dev); | |
673a394b | 1373 | #else |
23bc5982 | 1374 | #define i915_verify_lists(dev) 0 |
673a394b | 1375 | #endif |
05394f39 CW |
1376 | void i915_gem_object_check_coherency(struct drm_i915_gem_object *obj, |
1377 | int handle); | |
1378 | void i915_gem_dump_object(struct drm_i915_gem_object *obj, int len, | |
673a394b | 1379 | const char *where, uint32_t mark); |
1da177e4 | 1380 | |
2017263e | 1381 | /* i915_debugfs.c */ |
27c202ad BG |
1382 | int i915_debugfs_init(struct drm_minor *minor); |
1383 | void i915_debugfs_cleanup(struct drm_minor *minor); | |
2017263e | 1384 | |
317c35d1 JB |
1385 | /* i915_suspend.c */ |
1386 | extern int i915_save_state(struct drm_device *dev); | |
1387 | extern int i915_restore_state(struct drm_device *dev); | |
0a3e67a4 JB |
1388 | |
1389 | /* i915_suspend.c */ | |
1390 | extern int i915_save_state(struct drm_device *dev); | |
1391 | extern int i915_restore_state(struct drm_device *dev); | |
317c35d1 | 1392 | |
0136db58 BW |
1393 | /* i915_sysfs.c */ |
1394 | void i915_setup_sysfs(struct drm_device *dev_priv); | |
1395 | void i915_teardown_sysfs(struct drm_device *dev_priv); | |
1396 | ||
f899fc64 CW |
1397 | /* intel_i2c.c */ |
1398 | extern int intel_setup_gmbus(struct drm_device *dev); | |
1399 | extern void intel_teardown_gmbus(struct drm_device *dev); | |
3bd7d909 DK |
1400 | extern inline bool intel_gmbus_is_port_valid(unsigned port) |
1401 | { | |
2ed06c93 | 1402 | return (port >= GMBUS_PORT_SSC && port <= GMBUS_PORT_DPD); |
3bd7d909 DK |
1403 | } |
1404 | ||
1405 | extern struct i2c_adapter *intel_gmbus_get_adapter( | |
1406 | struct drm_i915_private *dev_priv, unsigned port); | |
e957d772 CW |
1407 | extern void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed); |
1408 | extern void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit); | |
b8232e90 CW |
1409 | extern inline bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter) |
1410 | { | |
1411 | return container_of(adapter, struct intel_gmbus, adapter)->force_bit; | |
1412 | } | |
f899fc64 CW |
1413 | extern void intel_i2c_reset(struct drm_device *dev); |
1414 | ||
3b617967 | 1415 | /* intel_opregion.c */ |
44834a67 CW |
1416 | extern int intel_opregion_setup(struct drm_device *dev); |
1417 | #ifdef CONFIG_ACPI | |
1418 | extern void intel_opregion_init(struct drm_device *dev); | |
1419 | extern void intel_opregion_fini(struct drm_device *dev); | |
3b617967 CW |
1420 | extern void intel_opregion_asle_intr(struct drm_device *dev); |
1421 | extern void intel_opregion_gse_intr(struct drm_device *dev); | |
1422 | extern void intel_opregion_enable_asle(struct drm_device *dev); | |
65e082c9 | 1423 | #else |
44834a67 CW |
1424 | static inline void intel_opregion_init(struct drm_device *dev) { return; } |
1425 | static inline void intel_opregion_fini(struct drm_device *dev) { return; } | |
3b617967 CW |
1426 | static inline void intel_opregion_asle_intr(struct drm_device *dev) { return; } |
1427 | static inline void intel_opregion_gse_intr(struct drm_device *dev) { return; } | |
1428 | static inline void intel_opregion_enable_asle(struct drm_device *dev) { return; } | |
65e082c9 | 1429 | #endif |
8ee1c3db | 1430 | |
723bfd70 JB |
1431 | /* intel_acpi.c */ |
1432 | #ifdef CONFIG_ACPI | |
1433 | extern void intel_register_dsm_handler(void); | |
1434 | extern void intel_unregister_dsm_handler(void); | |
1435 | #else | |
1436 | static inline void intel_register_dsm_handler(void) { return; } | |
1437 | static inline void intel_unregister_dsm_handler(void) { return; } | |
1438 | #endif /* CONFIG_ACPI */ | |
1439 | ||
79e53945 | 1440 | /* modesetting */ |
f817586c | 1441 | extern void intel_modeset_init_hw(struct drm_device *dev); |
79e53945 | 1442 | extern void intel_modeset_init(struct drm_device *dev); |
2c7111db | 1443 | extern void intel_modeset_gem_init(struct drm_device *dev); |
79e53945 | 1444 | extern void intel_modeset_cleanup(struct drm_device *dev); |
28d52043 | 1445 | extern int intel_modeset_vga_set_state(struct drm_device *dev, bool state); |
ee5382ae | 1446 | extern bool intel_fbc_enabled(struct drm_device *dev); |
43a9539f | 1447 | extern void intel_disable_fbc(struct drm_device *dev); |
7648fa99 | 1448 | extern bool ironlake_set_drps(struct drm_device *dev, u8 val); |
9fb526db | 1449 | extern void ironlake_init_pch_refclk(struct drm_device *dev); |
d5bb081b | 1450 | extern void ironlake_enable_rc6(struct drm_device *dev); |
3b8d8d91 | 1451 | extern void gen6_set_rps(struct drm_device *dev, u8 val); |
0206e353 AJ |
1452 | extern void intel_detect_pch(struct drm_device *dev); |
1453 | extern int intel_trans_dp_port_sel(struct drm_crtc *crtc); | |
0136db58 | 1454 | extern int intel_enable_rc6(const struct drm_device *dev); |
3bad0781 | 1455 | |
2911a35b | 1456 | extern bool i915_semaphore_is_enabled(struct drm_device *dev); |
8d715f00 KP |
1457 | extern void __gen6_gt_force_wake_get(struct drm_i915_private *dev_priv); |
1458 | extern void __gen6_gt_force_wake_mt_get(struct drm_i915_private *dev_priv); | |
1459 | extern void __gen6_gt_force_wake_put(struct drm_i915_private *dev_priv); | |
1460 | extern void __gen6_gt_force_wake_mt_put(struct drm_i915_private *dev_priv); | |
1461 | ||
575155a9 JB |
1462 | extern void vlv_force_wake_get(struct drm_i915_private *dev_priv); |
1463 | extern void vlv_force_wake_put(struct drm_i915_private *dev_priv); | |
1464 | ||
6ef3d427 | 1465 | /* overlay */ |
3bd3c932 | 1466 | #ifdef CONFIG_DEBUG_FS |
6ef3d427 CW |
1467 | extern struct intel_overlay_error_state *intel_overlay_capture_error_state(struct drm_device *dev); |
1468 | extern void intel_overlay_print_error_state(struct seq_file *m, struct intel_overlay_error_state *error); | |
c4a1d9e4 CW |
1469 | |
1470 | extern struct intel_display_error_state *intel_display_capture_error_state(struct drm_device *dev); | |
1471 | extern void intel_display_print_error_state(struct seq_file *m, | |
1472 | struct drm_device *dev, | |
1473 | struct intel_display_error_state *error); | |
3bd3c932 | 1474 | #endif |
6ef3d427 | 1475 | |
1ec14ad3 CW |
1476 | #define LP_RING(d) (&((struct drm_i915_private *)(d))->ring[RCS]) |
1477 | ||
1478 | #define BEGIN_LP_RING(n) \ | |
1479 | intel_ring_begin(LP_RING(dev_priv), (n)) | |
1480 | ||
1481 | #define OUT_RING(x) \ | |
1482 | intel_ring_emit(LP_RING(dev_priv), x) | |
1483 | ||
1484 | #define ADVANCE_LP_RING() \ | |
1485 | intel_ring_advance(LP_RING(dev_priv)) | |
1486 | ||
546b0974 EA |
1487 | /** |
1488 | * Lock test for when it's just for synchronization of ring access. | |
1489 | * | |
1490 | * In that case, we don't need to do it when GEM is initialized as nobody else | |
1491 | * has access to the ring. | |
1492 | */ | |
05394f39 | 1493 | #define RING_LOCK_TEST_WITH_RETURN(dev, file) do { \ |
1ec14ad3 | 1494 | if (LP_RING(dev->dev_private)->obj == NULL) \ |
05394f39 | 1495 | LOCK_TEST_WITH_RETURN(dev, file); \ |
546b0974 EA |
1496 | } while (0) |
1497 | ||
b7287d80 BW |
1498 | /* On SNB platform, before reading ring registers forcewake bit |
1499 | * must be set to prevent GT core from power down and stale values being | |
1500 | * returned. | |
1501 | */ | |
fcca7926 BW |
1502 | void gen6_gt_force_wake_get(struct drm_i915_private *dev_priv); |
1503 | void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv); | |
67a3744f | 1504 | int __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv); |
b7287d80 | 1505 | |
5f75377d | 1506 | #define __i915_read(x, y) \ |
f7000883 | 1507 | u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg); |
fcca7926 | 1508 | |
5f75377d KP |
1509 | __i915_read(8, b) |
1510 | __i915_read(16, w) | |
1511 | __i915_read(32, l) | |
1512 | __i915_read(64, q) | |
1513 | #undef __i915_read | |
1514 | ||
1515 | #define __i915_write(x, y) \ | |
f7000883 AK |
1516 | void i915_write##x(struct drm_i915_private *dev_priv, u32 reg, u##x val); |
1517 | ||
5f75377d KP |
1518 | __i915_write(8, b) |
1519 | __i915_write(16, w) | |
1520 | __i915_write(32, l) | |
1521 | __i915_write(64, q) | |
1522 | #undef __i915_write | |
1523 | ||
1524 | #define I915_READ8(reg) i915_read8(dev_priv, (reg)) | |
1525 | #define I915_WRITE8(reg, val) i915_write8(dev_priv, (reg), (val)) | |
1526 | ||
1527 | #define I915_READ16(reg) i915_read16(dev_priv, (reg)) | |
1528 | #define I915_WRITE16(reg, val) i915_write16(dev_priv, (reg), (val)) | |
1529 | #define I915_READ16_NOTRACE(reg) readw(dev_priv->regs + (reg)) | |
1530 | #define I915_WRITE16_NOTRACE(reg, val) writew(val, dev_priv->regs + (reg)) | |
1531 | ||
1532 | #define I915_READ(reg) i915_read32(dev_priv, (reg)) | |
1533 | #define I915_WRITE(reg, val) i915_write32(dev_priv, (reg), (val)) | |
cae5852d ZN |
1534 | #define I915_READ_NOTRACE(reg) readl(dev_priv->regs + (reg)) |
1535 | #define I915_WRITE_NOTRACE(reg, val) writel(val, dev_priv->regs + (reg)) | |
5f75377d KP |
1536 | |
1537 | #define I915_WRITE64(reg, val) i915_write64(dev_priv, (reg), (val)) | |
1538 | #define I915_READ64(reg) i915_read64(dev_priv, (reg)) | |
cae5852d ZN |
1539 | |
1540 | #define POSTING_READ(reg) (void)I915_READ_NOTRACE(reg) | |
1541 | #define POSTING_READ16(reg) (void)I915_READ16_NOTRACE(reg) | |
1542 | ||
ba4f01a3 | 1543 | |
1da177e4 | 1544 | #endif |