Commit | Line | Data |
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1da177e4 LT |
1 | /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*- |
2 | */ | |
0d6aa60b | 3 | /* |
bc54fd1a | 4 | * |
1da177e4 LT |
5 | * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. |
6 | * All Rights Reserved. | |
bc54fd1a DA |
7 | * |
8 | * Permission is hereby granted, free of charge, to any person obtaining a | |
9 | * copy of this software and associated documentation files (the | |
10 | * "Software"), to deal in the Software without restriction, including | |
11 | * without limitation the rights to use, copy, modify, merge, publish, | |
12 | * distribute, sub license, and/or sell copies of the Software, and to | |
13 | * permit persons to whom the Software is furnished to do so, subject to | |
14 | * the following conditions: | |
15 | * | |
16 | * The above copyright notice and this permission notice (including the | |
17 | * next paragraph) shall be included in all copies or substantial portions | |
18 | * of the Software. | |
19 | * | |
20 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS | |
21 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
22 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. | |
23 | * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR | |
24 | * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, | |
25 | * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE | |
26 | * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. | |
27 | * | |
0d6aa60b | 28 | */ |
1da177e4 LT |
29 | |
30 | #ifndef _I915_DRV_H_ | |
31 | #define _I915_DRV_H_ | |
32 | ||
e9b73c67 | 33 | #include <uapi/drm/i915_drm.h> |
93b81f51 | 34 | #include <uapi/drm/drm_fourcc.h> |
e9b73c67 | 35 | |
e23ceb83 | 36 | #include <drm/drmP.h> |
c838d719 | 37 | #include "i915_params.h" |
585fb111 | 38 | #include "i915_reg.h" |
79e53945 | 39 | #include "intel_bios.h" |
8187a2b7 | 40 | #include "intel_ringbuffer.h" |
b20385f1 | 41 | #include "intel_lrc.h" |
0260c420 | 42 | #include "i915_gem_gtt.h" |
564ddb2f | 43 | #include "i915_gem_render_state.h" |
0839ccb8 | 44 | #include <linux/io-mapping.h> |
f899fc64 | 45 | #include <linux/i2c.h> |
c167a6fc | 46 | #include <linux/i2c-algo-bit.h> |
0ade6386 | 47 | #include <drm/intel-gtt.h> |
ba8286fa | 48 | #include <drm/drm_legacy.h> /* for struct drm_dma_handle */ |
d9fc9413 | 49 | #include <drm/drm_gem.h> |
aaa6fd2a | 50 | #include <linux/backlight.h> |
5cc9ed4b | 51 | #include <linux/hashtable.h> |
2911a35b | 52 | #include <linux/intel-iommu.h> |
742cbee8 | 53 | #include <linux/kref.h> |
9ee32fea | 54 | #include <linux/pm_qos.h> |
33a732f4 | 55 | #include "intel_guc.h" |
585fb111 | 56 | |
1da177e4 LT |
57 | /* General customization: |
58 | */ | |
59 | ||
1da177e4 LT |
60 | #define DRIVER_NAME "i915" |
61 | #define DRIVER_DESC "Intel Graphics" | |
7447a2b2 | 62 | #define DRIVER_DATE "20151218" |
1da177e4 | 63 | |
c883ef1b | 64 | #undef WARN_ON |
5f77eeb0 DV |
65 | /* Many gcc seem to no see through this and fall over :( */ |
66 | #if 0 | |
67 | #define WARN_ON(x) ({ \ | |
68 | bool __i915_warn_cond = (x); \ | |
69 | if (__builtin_constant_p(__i915_warn_cond)) \ | |
70 | BUILD_BUG_ON(__i915_warn_cond); \ | |
71 | WARN(__i915_warn_cond, "WARN_ON(" #x ")"); }) | |
72 | #else | |
152b2262 | 73 | #define WARN_ON(x) WARN((x), "%s", "WARN_ON(" __stringify(x) ")") |
5f77eeb0 DV |
74 | #endif |
75 | ||
cd9bfacb | 76 | #undef WARN_ON_ONCE |
152b2262 | 77 | #define WARN_ON_ONCE(x) WARN_ONCE((x), "%s", "WARN_ON_ONCE(" __stringify(x) ")") |
cd9bfacb | 78 | |
5f77eeb0 DV |
79 | #define MISSING_CASE(x) WARN(1, "Missing switch case (%lu) in %s\n", \ |
80 | (long) (x), __func__); | |
c883ef1b | 81 | |
e2c719b7 RC |
82 | /* Use I915_STATE_WARN(x) and I915_STATE_WARN_ON() (rather than WARN() and |
83 | * WARN_ON()) for hw state sanity checks to check for unexpected conditions | |
84 | * which may not necessarily be a user visible problem. This will either | |
85 | * WARN() or DRM_ERROR() depending on the verbose_checks moduleparam, to | |
86 | * enable distros and users to tailor their preferred amount of i915 abrt | |
87 | * spam. | |
88 | */ | |
89 | #define I915_STATE_WARN(condition, format...) ({ \ | |
90 | int __ret_warn_on = !!(condition); \ | |
32753cb8 JL |
91 | if (unlikely(__ret_warn_on)) \ |
92 | if (!WARN(i915.verbose_state_checks, format)) \ | |
e2c719b7 | 93 | DRM_ERROR(format); \ |
e2c719b7 RC |
94 | unlikely(__ret_warn_on); \ |
95 | }) | |
96 | ||
152b2262 JL |
97 | #define I915_STATE_WARN_ON(x) \ |
98 | I915_STATE_WARN((x), "%s", "WARN_ON(" __stringify(x) ")") | |
c883ef1b | 99 | |
42a8ca4c JN |
100 | static inline const char *yesno(bool v) |
101 | { | |
102 | return v ? "yes" : "no"; | |
103 | } | |
104 | ||
317c35d1 | 105 | enum pipe { |
752aa88a | 106 | INVALID_PIPE = -1, |
317c35d1 JB |
107 | PIPE_A = 0, |
108 | PIPE_B, | |
9db4a9c7 | 109 | PIPE_C, |
a57c774a AK |
110 | _PIPE_EDP, |
111 | I915_MAX_PIPES = _PIPE_EDP | |
317c35d1 | 112 | }; |
9db4a9c7 | 113 | #define pipe_name(p) ((p) + 'A') |
317c35d1 | 114 | |
a5c961d1 PZ |
115 | enum transcoder { |
116 | TRANSCODER_A = 0, | |
117 | TRANSCODER_B, | |
118 | TRANSCODER_C, | |
a57c774a AK |
119 | TRANSCODER_EDP, |
120 | I915_MAX_TRANSCODERS | |
a5c961d1 PZ |
121 | }; |
122 | #define transcoder_name(t) ((t) + 'A') | |
123 | ||
84139d1e | 124 | /* |
31409e97 MR |
125 | * I915_MAX_PLANES in the enum below is the maximum (across all platforms) |
126 | * number of planes per CRTC. Not all platforms really have this many planes, | |
127 | * which means some arrays of size I915_MAX_PLANES may have unused entries | |
128 | * between the topmost sprite plane and the cursor plane. | |
84139d1e | 129 | */ |
80824003 JB |
130 | enum plane { |
131 | PLANE_A = 0, | |
132 | PLANE_B, | |
9db4a9c7 | 133 | PLANE_C, |
31409e97 MR |
134 | PLANE_CURSOR, |
135 | I915_MAX_PLANES, | |
80824003 | 136 | }; |
9db4a9c7 | 137 | #define plane_name(p) ((p) + 'A') |
52440211 | 138 | |
d615a166 | 139 | #define sprite_name(p, s) ((p) * INTEL_INFO(dev)->num_sprites[(p)] + (s) + 'A') |
06da8da2 | 140 | |
2b139522 ED |
141 | enum port { |
142 | PORT_A = 0, | |
143 | PORT_B, | |
144 | PORT_C, | |
145 | PORT_D, | |
146 | PORT_E, | |
147 | I915_MAX_PORTS | |
148 | }; | |
149 | #define port_name(p) ((p) + 'A') | |
150 | ||
a09caddd | 151 | #define I915_NUM_PHYS_VLV 2 |
e4607fcf CML |
152 | |
153 | enum dpio_channel { | |
154 | DPIO_CH0, | |
155 | DPIO_CH1 | |
156 | }; | |
157 | ||
158 | enum dpio_phy { | |
159 | DPIO_PHY0, | |
160 | DPIO_PHY1 | |
161 | }; | |
162 | ||
b97186f0 PZ |
163 | enum intel_display_power_domain { |
164 | POWER_DOMAIN_PIPE_A, | |
165 | POWER_DOMAIN_PIPE_B, | |
166 | POWER_DOMAIN_PIPE_C, | |
167 | POWER_DOMAIN_PIPE_A_PANEL_FITTER, | |
168 | POWER_DOMAIN_PIPE_B_PANEL_FITTER, | |
169 | POWER_DOMAIN_PIPE_C_PANEL_FITTER, | |
170 | POWER_DOMAIN_TRANSCODER_A, | |
171 | POWER_DOMAIN_TRANSCODER_B, | |
172 | POWER_DOMAIN_TRANSCODER_C, | |
f52e353e | 173 | POWER_DOMAIN_TRANSCODER_EDP, |
6331a704 PJ |
174 | POWER_DOMAIN_PORT_DDI_A_LANES, |
175 | POWER_DOMAIN_PORT_DDI_B_LANES, | |
176 | POWER_DOMAIN_PORT_DDI_C_LANES, | |
177 | POWER_DOMAIN_PORT_DDI_D_LANES, | |
178 | POWER_DOMAIN_PORT_DDI_E_LANES, | |
319be8ae ID |
179 | POWER_DOMAIN_PORT_DSI, |
180 | POWER_DOMAIN_PORT_CRT, | |
181 | POWER_DOMAIN_PORT_OTHER, | |
cdf8dd7f | 182 | POWER_DOMAIN_VGA, |
fbeeaa23 | 183 | POWER_DOMAIN_AUDIO, |
bd2bb1b9 | 184 | POWER_DOMAIN_PLLS, |
1407121a S |
185 | POWER_DOMAIN_AUX_A, |
186 | POWER_DOMAIN_AUX_B, | |
187 | POWER_DOMAIN_AUX_C, | |
188 | POWER_DOMAIN_AUX_D, | |
f0ab43e6 | 189 | POWER_DOMAIN_GMBUS, |
dfa57627 | 190 | POWER_DOMAIN_MODESET, |
baa70707 | 191 | POWER_DOMAIN_INIT, |
bddc7645 ID |
192 | |
193 | POWER_DOMAIN_NUM, | |
b97186f0 PZ |
194 | }; |
195 | ||
196 | #define POWER_DOMAIN_PIPE(pipe) ((pipe) + POWER_DOMAIN_PIPE_A) | |
197 | #define POWER_DOMAIN_PIPE_PANEL_FITTER(pipe) \ | |
198 | ((pipe) + POWER_DOMAIN_PIPE_A_PANEL_FITTER) | |
f52e353e ID |
199 | #define POWER_DOMAIN_TRANSCODER(tran) \ |
200 | ((tran) == TRANSCODER_EDP ? POWER_DOMAIN_TRANSCODER_EDP : \ | |
201 | (tran) + POWER_DOMAIN_TRANSCODER_A) | |
b97186f0 | 202 | |
1d843f9d EE |
203 | enum hpd_pin { |
204 | HPD_NONE = 0, | |
1d843f9d EE |
205 | HPD_TV = HPD_NONE, /* TV is known to be unreliable */ |
206 | HPD_CRT, | |
207 | HPD_SDVO_B, | |
208 | HPD_SDVO_C, | |
cc24fcdc | 209 | HPD_PORT_A, |
1d843f9d EE |
210 | HPD_PORT_B, |
211 | HPD_PORT_C, | |
212 | HPD_PORT_D, | |
26951caf | 213 | HPD_PORT_E, |
1d843f9d EE |
214 | HPD_NUM_PINS |
215 | }; | |
216 | ||
c91711f9 JN |
217 | #define for_each_hpd_pin(__pin) \ |
218 | for ((__pin) = (HPD_NONE + 1); (__pin) < HPD_NUM_PINS; (__pin)++) | |
219 | ||
5fcece80 JN |
220 | struct i915_hotplug { |
221 | struct work_struct hotplug_work; | |
222 | ||
223 | struct { | |
224 | unsigned long last_jiffies; | |
225 | int count; | |
226 | enum { | |
227 | HPD_ENABLED = 0, | |
228 | HPD_DISABLED = 1, | |
229 | HPD_MARK_DISABLED = 2 | |
230 | } state; | |
231 | } stats[HPD_NUM_PINS]; | |
232 | u32 event_bits; | |
233 | struct delayed_work reenable_work; | |
234 | ||
235 | struct intel_digital_port *irq_port[I915_MAX_PORTS]; | |
236 | u32 long_port_mask; | |
237 | u32 short_port_mask; | |
238 | struct work_struct dig_port_work; | |
239 | ||
240 | /* | |
241 | * if we get a HPD irq from DP and a HPD irq from non-DP | |
242 | * the non-DP HPD could block the workqueue on a mode config | |
243 | * mutex getting, that userspace may have taken. However | |
244 | * userspace is waiting on the DP workqueue to run which is | |
245 | * blocked behind the non-DP one. | |
246 | */ | |
247 | struct workqueue_struct *dp_wq; | |
248 | }; | |
249 | ||
2a2d5482 CW |
250 | #define I915_GEM_GPU_DOMAINS \ |
251 | (I915_GEM_DOMAIN_RENDER | \ | |
252 | I915_GEM_DOMAIN_SAMPLER | \ | |
253 | I915_GEM_DOMAIN_COMMAND | \ | |
254 | I915_GEM_DOMAIN_INSTRUCTION | \ | |
255 | I915_GEM_DOMAIN_VERTEX) | |
62fdfeaf | 256 | |
055e393f DL |
257 | #define for_each_pipe(__dev_priv, __p) \ |
258 | for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes; (__p)++) | |
dd740780 DL |
259 | #define for_each_plane(__dev_priv, __pipe, __p) \ |
260 | for ((__p) = 0; \ | |
261 | (__p) < INTEL_INFO(__dev_priv)->num_sprites[(__pipe)] + 1; \ | |
262 | (__p)++) | |
3bdcfc0c DL |
263 | #define for_each_sprite(__dev_priv, __p, __s) \ |
264 | for ((__s) = 0; \ | |
265 | (__s) < INTEL_INFO(__dev_priv)->num_sprites[(__p)]; \ | |
266 | (__s)++) | |
9db4a9c7 | 267 | |
d79b814d DL |
268 | #define for_each_crtc(dev, crtc) \ |
269 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) | |
270 | ||
27321ae8 ML |
271 | #define for_each_intel_plane(dev, intel_plane) \ |
272 | list_for_each_entry(intel_plane, \ | |
273 | &dev->mode_config.plane_list, \ | |
274 | base.head) | |
275 | ||
262cd2e1 VS |
276 | #define for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) \ |
277 | list_for_each_entry(intel_plane, \ | |
278 | &(dev)->mode_config.plane_list, \ | |
279 | base.head) \ | |
95150bdf | 280 | for_each_if ((intel_plane)->pipe == (intel_crtc)->pipe) |
262cd2e1 | 281 | |
d063ae48 DL |
282 | #define for_each_intel_crtc(dev, intel_crtc) \ |
283 | list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list, base.head) | |
284 | ||
b2784e15 DL |
285 | #define for_each_intel_encoder(dev, intel_encoder) \ |
286 | list_for_each_entry(intel_encoder, \ | |
287 | &(dev)->mode_config.encoder_list, \ | |
288 | base.head) | |
289 | ||
3a3371ff ACO |
290 | #define for_each_intel_connector(dev, intel_connector) \ |
291 | list_for_each_entry(intel_connector, \ | |
292 | &dev->mode_config.connector_list, \ | |
293 | base.head) | |
294 | ||
6c2b7c12 DV |
295 | #define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \ |
296 | list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \ | |
95150bdf | 297 | for_each_if ((intel_encoder)->base.crtc == (__crtc)) |
6c2b7c12 | 298 | |
53f5e3ca JB |
299 | #define for_each_connector_on_encoder(dev, __encoder, intel_connector) \ |
300 | list_for_each_entry((intel_connector), &(dev)->mode_config.connector_list, base.head) \ | |
95150bdf | 301 | for_each_if ((intel_connector)->base.encoder == (__encoder)) |
53f5e3ca | 302 | |
b04c5bd6 BF |
303 | #define for_each_power_domain(domain, mask) \ |
304 | for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \ | |
95150bdf | 305 | for_each_if ((1 << (domain)) & (mask)) |
b04c5bd6 | 306 | |
e7b903d2 | 307 | struct drm_i915_private; |
ad46cb53 | 308 | struct i915_mm_struct; |
5cc9ed4b | 309 | struct i915_mmu_object; |
e7b903d2 | 310 | |
a6f766f3 CW |
311 | struct drm_i915_file_private { |
312 | struct drm_i915_private *dev_priv; | |
313 | struct drm_file *file; | |
314 | ||
315 | struct { | |
316 | spinlock_t lock; | |
317 | struct list_head request_list; | |
d0bc54f2 CW |
318 | /* 20ms is a fairly arbitrary limit (greater than the average frame time) |
319 | * chosen to prevent the CPU getting more than a frame ahead of the GPU | |
320 | * (when using lax throttling for the frontbuffer). We also use it to | |
321 | * offer free GPU waitboosts for severely congested workloads. | |
322 | */ | |
323 | #define DRM_I915_THROTTLE_JIFFIES msecs_to_jiffies(20) | |
a6f766f3 CW |
324 | } mm; |
325 | struct idr context_idr; | |
326 | ||
2e1b8730 CW |
327 | struct intel_rps_client { |
328 | struct list_head link; | |
329 | unsigned boosts; | |
330 | } rps; | |
a6f766f3 | 331 | |
2e1b8730 | 332 | struct intel_engine_cs *bsd_ring; |
a6f766f3 CW |
333 | }; |
334 | ||
46edb027 DV |
335 | enum intel_dpll_id { |
336 | DPLL_ID_PRIVATE = -1, /* non-shared dpll in use */ | |
337 | /* real shared dpll ids must be >= 0 */ | |
9cd86933 DV |
338 | DPLL_ID_PCH_PLL_A = 0, |
339 | DPLL_ID_PCH_PLL_B = 1, | |
429d47d5 | 340 | /* hsw/bdw */ |
9cd86933 DV |
341 | DPLL_ID_WRPLL1 = 0, |
342 | DPLL_ID_WRPLL2 = 1, | |
00490c22 ML |
343 | DPLL_ID_SPLL = 2, |
344 | ||
429d47d5 S |
345 | /* skl */ |
346 | DPLL_ID_SKL_DPLL1 = 0, | |
347 | DPLL_ID_SKL_DPLL2 = 1, | |
348 | DPLL_ID_SKL_DPLL3 = 2, | |
46edb027 | 349 | }; |
429d47d5 | 350 | #define I915_NUM_PLLS 3 |
46edb027 | 351 | |
5358901f | 352 | struct intel_dpll_hw_state { |
dcfc3552 | 353 | /* i9xx, pch plls */ |
66e985c0 | 354 | uint32_t dpll; |
8bcc2795 | 355 | uint32_t dpll_md; |
66e985c0 DV |
356 | uint32_t fp0; |
357 | uint32_t fp1; | |
dcfc3552 DL |
358 | |
359 | /* hsw, bdw */ | |
d452c5b6 | 360 | uint32_t wrpll; |
00490c22 | 361 | uint32_t spll; |
d1a2dc78 S |
362 | |
363 | /* skl */ | |
364 | /* | |
365 | * DPLL_CTRL1 has 6 bits for each each this DPLL. We store those in | |
71cd8423 | 366 | * lower part of ctrl1 and they get shifted into position when writing |
d1a2dc78 S |
367 | * the register. This allows us to easily compare the state to share |
368 | * the DPLL. | |
369 | */ | |
370 | uint32_t ctrl1; | |
371 | /* HDMI only, 0 when used for DP */ | |
372 | uint32_t cfgcr1, cfgcr2; | |
dfb82408 S |
373 | |
374 | /* bxt */ | |
05712c15 ID |
375 | uint32_t ebb0, ebb4, pll0, pll1, pll2, pll3, pll6, pll8, pll9, pll10, |
376 | pcsdw12; | |
5358901f DV |
377 | }; |
378 | ||
3e369b76 | 379 | struct intel_shared_dpll_config { |
1e6f2ddc | 380 | unsigned crtc_mask; /* mask of CRTCs sharing this PLL */ |
3e369b76 ACO |
381 | struct intel_dpll_hw_state hw_state; |
382 | }; | |
383 | ||
384 | struct intel_shared_dpll { | |
385 | struct intel_shared_dpll_config config; | |
8bd31e67 | 386 | |
ee7b9f93 JB |
387 | int active; /* count of number of active CRTCs (i.e. DPMS on) */ |
388 | bool on; /* is the PLL actually active? Disabled during modeset */ | |
46edb027 DV |
389 | const char *name; |
390 | /* should match the index in the dev_priv->shared_dplls array */ | |
391 | enum intel_dpll_id id; | |
96f6128c DV |
392 | /* The mode_set hook is optional and should be used together with the |
393 | * intel_prepare_shared_dpll function. */ | |
15bdd4cf DV |
394 | void (*mode_set)(struct drm_i915_private *dev_priv, |
395 | struct intel_shared_dpll *pll); | |
e7b903d2 DV |
396 | void (*enable)(struct drm_i915_private *dev_priv, |
397 | struct intel_shared_dpll *pll); | |
398 | void (*disable)(struct drm_i915_private *dev_priv, | |
399 | struct intel_shared_dpll *pll); | |
5358901f DV |
400 | bool (*get_hw_state)(struct drm_i915_private *dev_priv, |
401 | struct intel_shared_dpll *pll, | |
402 | struct intel_dpll_hw_state *hw_state); | |
ee7b9f93 | 403 | }; |
ee7b9f93 | 404 | |
429d47d5 S |
405 | #define SKL_DPLL0 0 |
406 | #define SKL_DPLL1 1 | |
407 | #define SKL_DPLL2 2 | |
408 | #define SKL_DPLL3 3 | |
409 | ||
e69d0bc1 DV |
410 | /* Used by dp and fdi links */ |
411 | struct intel_link_m_n { | |
412 | uint32_t tu; | |
413 | uint32_t gmch_m; | |
414 | uint32_t gmch_n; | |
415 | uint32_t link_m; | |
416 | uint32_t link_n; | |
417 | }; | |
418 | ||
419 | void intel_link_compute_m_n(int bpp, int nlanes, | |
420 | int pixel_clock, int link_clock, | |
421 | struct intel_link_m_n *m_n); | |
422 | ||
1da177e4 LT |
423 | /* Interface history: |
424 | * | |
425 | * 1.1: Original. | |
0d6aa60b DA |
426 | * 1.2: Add Power Management |
427 | * 1.3: Add vblank support | |
de227f5f | 428 | * 1.4: Fix cmdbuffer path, add heap destroy |
702880f2 | 429 | * 1.5: Add vblank pipe configuration |
2228ed67 MCA |
430 | * 1.6: - New ioctl for scheduling buffer swaps on vertical blank |
431 | * - Support vertical blank on secondary display pipe | |
1da177e4 LT |
432 | */ |
433 | #define DRIVER_MAJOR 1 | |
2228ed67 | 434 | #define DRIVER_MINOR 6 |
1da177e4 LT |
435 | #define DRIVER_PATCHLEVEL 0 |
436 | ||
23bc5982 | 437 | #define WATCH_LISTS 0 |
673a394b | 438 | |
0a3e67a4 JB |
439 | struct opregion_header; |
440 | struct opregion_acpi; | |
441 | struct opregion_swsci; | |
442 | struct opregion_asle; | |
443 | ||
8ee1c3db | 444 | struct intel_opregion { |
115719fc WD |
445 | struct opregion_header *header; |
446 | struct opregion_acpi *acpi; | |
447 | struct opregion_swsci *swsci; | |
ebde53c7 JN |
448 | u32 swsci_gbda_sub_functions; |
449 | u32 swsci_sbcb_sub_functions; | |
115719fc | 450 | struct opregion_asle *asle; |
04ebaadb | 451 | void *rvda; |
82730385 | 452 | const void *vbt; |
ada8f955 | 453 | u32 vbt_size; |
115719fc | 454 | u32 *lid_state; |
91a60f20 | 455 | struct work_struct asle_work; |
8ee1c3db | 456 | }; |
44834a67 | 457 | #define OPREGION_SIZE (8*1024) |
8ee1c3db | 458 | |
6ef3d427 CW |
459 | struct intel_overlay; |
460 | struct intel_overlay_error_state; | |
461 | ||
de151cf6 | 462 | #define I915_FENCE_REG_NONE -1 |
42b5aeab VS |
463 | #define I915_MAX_NUM_FENCES 32 |
464 | /* 32 fences + sign bit for FENCE_REG_NONE */ | |
465 | #define I915_MAX_NUM_FENCE_BITS 6 | |
de151cf6 JB |
466 | |
467 | struct drm_i915_fence_reg { | |
007cc8ac | 468 | struct list_head lru_list; |
caea7476 | 469 | struct drm_i915_gem_object *obj; |
1690e1eb | 470 | int pin_count; |
de151cf6 | 471 | }; |
7c1c2871 | 472 | |
9b9d172d | 473 | struct sdvo_device_mapping { |
e957d772 | 474 | u8 initialized; |
9b9d172d | 475 | u8 dvo_port; |
476 | u8 slave_addr; | |
477 | u8 dvo_wiring; | |
e957d772 | 478 | u8 i2c_pin; |
b1083333 | 479 | u8 ddc_pin; |
9b9d172d | 480 | }; |
481 | ||
c4a1d9e4 CW |
482 | struct intel_display_error_state; |
483 | ||
63eeaf38 | 484 | struct drm_i915_error_state { |
742cbee8 | 485 | struct kref ref; |
585b0288 BW |
486 | struct timeval time; |
487 | ||
cb383002 | 488 | char error_msg[128]; |
eb5be9d0 | 489 | int iommu; |
48b031e3 | 490 | u32 reset_count; |
62d5d69b | 491 | u32 suspend_count; |
cb383002 | 492 | |
585b0288 | 493 | /* Generic register state */ |
63eeaf38 JB |
494 | u32 eir; |
495 | u32 pgtbl_er; | |
be998e2e | 496 | u32 ier; |
885ea5a8 | 497 | u32 gtier[4]; |
b9a3906b | 498 | u32 ccid; |
0f3b6849 CW |
499 | u32 derrmr; |
500 | u32 forcewake; | |
585b0288 BW |
501 | u32 error; /* gen6+ */ |
502 | u32 err_int; /* gen7 */ | |
6c826f34 MK |
503 | u32 fault_data0; /* gen8, gen9 */ |
504 | u32 fault_data1; /* gen8, gen9 */ | |
585b0288 | 505 | u32 done_reg; |
91ec5d11 BW |
506 | u32 gac_eco; |
507 | u32 gam_ecochk; | |
508 | u32 gab_ctl; | |
509 | u32 gfx_mode; | |
585b0288 | 510 | u32 extra_instdone[I915_NUM_INSTDONE_REG]; |
585b0288 BW |
511 | u64 fence[I915_MAX_NUM_FENCES]; |
512 | struct intel_overlay_error_state *overlay; | |
513 | struct intel_display_error_state *display; | |
0ca36d78 | 514 | struct drm_i915_error_object *semaphore_obj; |
585b0288 | 515 | |
52d39a21 | 516 | struct drm_i915_error_ring { |
372fbb8e | 517 | bool valid; |
362b8af7 BW |
518 | /* Software tracked state */ |
519 | bool waiting; | |
520 | int hangcheck_score; | |
521 | enum intel_ring_hangcheck_action hangcheck_action; | |
522 | int num_requests; | |
523 | ||
524 | /* our own tracking of ring head and tail */ | |
525 | u32 cpu_ring_head; | |
526 | u32 cpu_ring_tail; | |
527 | ||
528 | u32 semaphore_seqno[I915_NUM_RINGS - 1]; | |
529 | ||
530 | /* Register state */ | |
94f8cf10 | 531 | u32 start; |
362b8af7 BW |
532 | u32 tail; |
533 | u32 head; | |
534 | u32 ctl; | |
535 | u32 hws; | |
536 | u32 ipeir; | |
537 | u32 ipehr; | |
538 | u32 instdone; | |
362b8af7 BW |
539 | u32 bbstate; |
540 | u32 instpm; | |
541 | u32 instps; | |
542 | u32 seqno; | |
543 | u64 bbaddr; | |
50877445 | 544 | u64 acthd; |
362b8af7 | 545 | u32 fault_reg; |
13ffadd1 | 546 | u64 faddr; |
362b8af7 BW |
547 | u32 rc_psmi; /* sleep state */ |
548 | u32 semaphore_mboxes[I915_NUM_RINGS - 1]; | |
549 | ||
52d39a21 CW |
550 | struct drm_i915_error_object { |
551 | int page_count; | |
e1f12325 | 552 | u64 gtt_offset; |
52d39a21 | 553 | u32 *pages[0]; |
ab0e7ff9 | 554 | } *ringbuffer, *batchbuffer, *wa_batchbuffer, *ctx, *hws_page; |
362b8af7 | 555 | |
52d39a21 CW |
556 | struct drm_i915_error_request { |
557 | long jiffies; | |
558 | u32 seqno; | |
ee4f42b1 | 559 | u32 tail; |
52d39a21 | 560 | } *requests; |
6c7a01ec BW |
561 | |
562 | struct { | |
563 | u32 gfx_mode; | |
564 | union { | |
565 | u64 pdp[4]; | |
566 | u32 pp_dir_base; | |
567 | }; | |
568 | } vm_info; | |
ab0e7ff9 CW |
569 | |
570 | pid_t pid; | |
571 | char comm[TASK_COMM_LEN]; | |
52d39a21 | 572 | } ring[I915_NUM_RINGS]; |
3a448734 | 573 | |
9df30794 | 574 | struct drm_i915_error_buffer { |
a779e5ab | 575 | u32 size; |
9df30794 | 576 | u32 name; |
b4716185 | 577 | u32 rseqno[I915_NUM_RINGS], wseqno; |
e1f12325 | 578 | u64 gtt_offset; |
9df30794 CW |
579 | u32 read_domains; |
580 | u32 write_domain; | |
4b9de737 | 581 | s32 fence_reg:I915_MAX_NUM_FENCE_BITS; |
9df30794 CW |
582 | s32 pinned:2; |
583 | u32 tiling:2; | |
584 | u32 dirty:1; | |
585 | u32 purgeable:1; | |
5cc9ed4b | 586 | u32 userptr:1; |
5d1333fc | 587 | s32 ring:4; |
f56383cb | 588 | u32 cache_level:3; |
95f5301d | 589 | } **active_bo, **pinned_bo; |
6c7a01ec | 590 | |
95f5301d | 591 | u32 *active_bo_count, *pinned_bo_count; |
3a448734 | 592 | u32 vm_count; |
63eeaf38 JB |
593 | }; |
594 | ||
7bd688cd | 595 | struct intel_connector; |
820d2d77 | 596 | struct intel_encoder; |
5cec258b | 597 | struct intel_crtc_state; |
5724dbd1 | 598 | struct intel_initial_plane_config; |
0e8ffe1b | 599 | struct intel_crtc; |
ee9300bb DV |
600 | struct intel_limit; |
601 | struct dpll; | |
b8cecdf5 | 602 | |
e70236a8 | 603 | struct drm_i915_display_funcs { |
e70236a8 JB |
604 | int (*get_display_clock_speed)(struct drm_device *dev); |
605 | int (*get_fifo_size)(struct drm_device *dev, int plane); | |
ee9300bb DV |
606 | /** |
607 | * find_dpll() - Find the best values for the PLL | |
608 | * @limit: limits for the PLL | |
609 | * @crtc: current CRTC | |
610 | * @target: target frequency in kHz | |
611 | * @refclk: reference clock frequency in kHz | |
612 | * @match_clock: if provided, @best_clock P divider must | |
613 | * match the P divider from @match_clock | |
614 | * used for LVDS downclocking | |
615 | * @best_clock: best PLL values found | |
616 | * | |
617 | * Returns true on success, false on failure. | |
618 | */ | |
619 | bool (*find_dpll)(const struct intel_limit *limit, | |
a93e255f | 620 | struct intel_crtc_state *crtc_state, |
ee9300bb DV |
621 | int target, int refclk, |
622 | struct dpll *match_clock, | |
623 | struct dpll *best_clock); | |
86c8bbbe MR |
624 | int (*compute_pipe_wm)(struct intel_crtc *crtc, |
625 | struct drm_atomic_state *state); | |
46ba614c | 626 | void (*update_wm)(struct drm_crtc *crtc); |
27c329ed ML |
627 | int (*modeset_calc_cdclk)(struct drm_atomic_state *state); |
628 | void (*modeset_commit_cdclk)(struct drm_atomic_state *state); | |
0e8ffe1b DV |
629 | /* Returns the active state of the crtc, and if the crtc is active, |
630 | * fills out the pipe-config with the hw state. */ | |
631 | bool (*get_pipe_config)(struct intel_crtc *, | |
5cec258b | 632 | struct intel_crtc_state *); |
5724dbd1 DL |
633 | void (*get_initial_plane_config)(struct intel_crtc *, |
634 | struct intel_initial_plane_config *); | |
190f68c5 ACO |
635 | int (*crtc_compute_clock)(struct intel_crtc *crtc, |
636 | struct intel_crtc_state *crtc_state); | |
76e5a89c DV |
637 | void (*crtc_enable)(struct drm_crtc *crtc); |
638 | void (*crtc_disable)(struct drm_crtc *crtc); | |
69bfe1a9 JN |
639 | void (*audio_codec_enable)(struct drm_connector *connector, |
640 | struct intel_encoder *encoder, | |
5e7234c9 | 641 | const struct drm_display_mode *adjusted_mode); |
69bfe1a9 | 642 | void (*audio_codec_disable)(struct intel_encoder *encoder); |
674cf967 | 643 | void (*fdi_link_train)(struct drm_crtc *crtc); |
6067aaea | 644 | void (*init_clock_gating)(struct drm_device *dev); |
8c9f3aaf JB |
645 | int (*queue_flip)(struct drm_device *dev, struct drm_crtc *crtc, |
646 | struct drm_framebuffer *fb, | |
ed8d1975 | 647 | struct drm_i915_gem_object *obj, |
6258fbe2 | 648 | struct drm_i915_gem_request *req, |
ed8d1975 | 649 | uint32_t flags); |
29b9bde6 DV |
650 | void (*update_primary_plane)(struct drm_crtc *crtc, |
651 | struct drm_framebuffer *fb, | |
652 | int x, int y); | |
20afbda2 | 653 | void (*hpd_irq_setup)(struct drm_device *dev); |
e70236a8 JB |
654 | /* clock updates for mode set */ |
655 | /* cursor updates */ | |
656 | /* render clock increase/decrease */ | |
657 | /* display clock increase/decrease */ | |
658 | /* pll clock increase/decrease */ | |
e70236a8 JB |
659 | }; |
660 | ||
48c1026a MK |
661 | enum forcewake_domain_id { |
662 | FW_DOMAIN_ID_RENDER = 0, | |
663 | FW_DOMAIN_ID_BLITTER, | |
664 | FW_DOMAIN_ID_MEDIA, | |
665 | ||
666 | FW_DOMAIN_ID_COUNT | |
667 | }; | |
668 | ||
669 | enum forcewake_domains { | |
670 | FORCEWAKE_RENDER = (1 << FW_DOMAIN_ID_RENDER), | |
671 | FORCEWAKE_BLITTER = (1 << FW_DOMAIN_ID_BLITTER), | |
672 | FORCEWAKE_MEDIA = (1 << FW_DOMAIN_ID_MEDIA), | |
673 | FORCEWAKE_ALL = (FORCEWAKE_RENDER | | |
674 | FORCEWAKE_BLITTER | | |
675 | FORCEWAKE_MEDIA) | |
676 | }; | |
677 | ||
907b28c5 | 678 | struct intel_uncore_funcs { |
c8d9a590 | 679 | void (*force_wake_get)(struct drm_i915_private *dev_priv, |
48c1026a | 680 | enum forcewake_domains domains); |
c8d9a590 | 681 | void (*force_wake_put)(struct drm_i915_private *dev_priv, |
48c1026a | 682 | enum forcewake_domains domains); |
0b274481 | 683 | |
f0f59a00 VS |
684 | uint8_t (*mmio_readb)(struct drm_i915_private *dev_priv, i915_reg_t r, bool trace); |
685 | uint16_t (*mmio_readw)(struct drm_i915_private *dev_priv, i915_reg_t r, bool trace); | |
686 | uint32_t (*mmio_readl)(struct drm_i915_private *dev_priv, i915_reg_t r, bool trace); | |
687 | uint64_t (*mmio_readq)(struct drm_i915_private *dev_priv, i915_reg_t r, bool trace); | |
0b274481 | 688 | |
f0f59a00 | 689 | void (*mmio_writeb)(struct drm_i915_private *dev_priv, i915_reg_t r, |
0b274481 | 690 | uint8_t val, bool trace); |
f0f59a00 | 691 | void (*mmio_writew)(struct drm_i915_private *dev_priv, i915_reg_t r, |
0b274481 | 692 | uint16_t val, bool trace); |
f0f59a00 | 693 | void (*mmio_writel)(struct drm_i915_private *dev_priv, i915_reg_t r, |
0b274481 | 694 | uint32_t val, bool trace); |
f0f59a00 | 695 | void (*mmio_writeq)(struct drm_i915_private *dev_priv, i915_reg_t r, |
0b274481 | 696 | uint64_t val, bool trace); |
990bbdad CW |
697 | }; |
698 | ||
907b28c5 CW |
699 | struct intel_uncore { |
700 | spinlock_t lock; /** lock is also taken in irq contexts. */ | |
701 | ||
702 | struct intel_uncore_funcs funcs; | |
703 | ||
704 | unsigned fifo_count; | |
48c1026a | 705 | enum forcewake_domains fw_domains; |
b2cff0db CW |
706 | |
707 | struct intel_uncore_forcewake_domain { | |
708 | struct drm_i915_private *i915; | |
48c1026a | 709 | enum forcewake_domain_id id; |
b2cff0db CW |
710 | unsigned wake_count; |
711 | struct timer_list timer; | |
f0f59a00 | 712 | i915_reg_t reg_set; |
05a2fb15 MK |
713 | u32 val_set; |
714 | u32 val_clear; | |
f0f59a00 VS |
715 | i915_reg_t reg_ack; |
716 | i915_reg_t reg_post; | |
05a2fb15 | 717 | u32 val_reset; |
b2cff0db | 718 | } fw_domain[FW_DOMAIN_ID_COUNT]; |
b2cff0db CW |
719 | }; |
720 | ||
721 | /* Iterate over initialised fw domains */ | |
722 | #define for_each_fw_domain_mask(domain__, mask__, dev_priv__, i__) \ | |
723 | for ((i__) = 0, (domain__) = &(dev_priv__)->uncore.fw_domain[0]; \ | |
724 | (i__) < FW_DOMAIN_ID_COUNT; \ | |
725 | (i__)++, (domain__) = &(dev_priv__)->uncore.fw_domain[i__]) \ | |
95150bdf | 726 | for_each_if (((mask__) & (dev_priv__)->uncore.fw_domains) & (1 << (i__))) |
b2cff0db CW |
727 | |
728 | #define for_each_fw_domain(domain__, dev_priv__, i__) \ | |
729 | for_each_fw_domain_mask(domain__, FORCEWAKE_ALL, dev_priv__, i__) | |
907b28c5 | 730 | |
b6e7d894 DL |
731 | #define CSR_VERSION(major, minor) ((major) << 16 | (minor)) |
732 | #define CSR_VERSION_MAJOR(version) ((version) >> 16) | |
733 | #define CSR_VERSION_MINOR(version) ((version) & 0xffff) | |
734 | ||
eb805623 | 735 | struct intel_csr { |
8144ac59 | 736 | struct work_struct work; |
eb805623 | 737 | const char *fw_path; |
a7f749f9 | 738 | uint32_t *dmc_payload; |
eb805623 | 739 | uint32_t dmc_fw_size; |
b6e7d894 | 740 | uint32_t version; |
eb805623 | 741 | uint32_t mmio_count; |
f0f59a00 | 742 | i915_reg_t mmioaddr[8]; |
eb805623 DV |
743 | uint32_t mmiodata[8]; |
744 | }; | |
745 | ||
79fc46df DL |
746 | #define DEV_INFO_FOR_EACH_FLAG(func, sep) \ |
747 | func(is_mobile) sep \ | |
748 | func(is_i85x) sep \ | |
749 | func(is_i915g) sep \ | |
750 | func(is_i945gm) sep \ | |
751 | func(is_g33) sep \ | |
752 | func(need_gfx_hws) sep \ | |
753 | func(is_g4x) sep \ | |
754 | func(is_pineview) sep \ | |
755 | func(is_broadwater) sep \ | |
756 | func(is_crestline) sep \ | |
757 | func(is_ivybridge) sep \ | |
758 | func(is_valleyview) sep \ | |
666a4537 | 759 | func(is_cherryview) sep \ |
79fc46df | 760 | func(is_haswell) sep \ |
7201c0b3 | 761 | func(is_skylake) sep \ |
7526ac19 | 762 | func(is_broxton) sep \ |
ef11bdb3 | 763 | func(is_kabylake) sep \ |
b833d685 | 764 | func(is_preliminary) sep \ |
79fc46df DL |
765 | func(has_fbc) sep \ |
766 | func(has_pipe_cxsr) sep \ | |
767 | func(has_hotplug) sep \ | |
768 | func(cursor_needs_physical) sep \ | |
769 | func(has_overlay) sep \ | |
770 | func(overlay_needs_physical) sep \ | |
771 | func(supports_tv) sep \ | |
dd93be58 | 772 | func(has_llc) sep \ |
30568c45 DL |
773 | func(has_ddi) sep \ |
774 | func(has_fpga_dbg) | |
c96ea64e | 775 | |
a587f779 DL |
776 | #define DEFINE_FLAG(name) u8 name:1 |
777 | #define SEP_SEMICOLON ; | |
c96ea64e | 778 | |
cfdf1fa2 | 779 | struct intel_device_info { |
10fce67a | 780 | u32 display_mmio_offset; |
87f1f465 | 781 | u16 device_id; |
7eb552ae | 782 | u8 num_pipes:3; |
d615a166 | 783 | u8 num_sprites[I915_MAX_PIPES]; |
c96c3a8c | 784 | u8 gen; |
73ae478c | 785 | u8 ring_mask; /* Rings supported by the HW */ |
a587f779 | 786 | DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG, SEP_SEMICOLON); |
a57c774a AK |
787 | /* Register offsets for the various display pipes and transcoders */ |
788 | int pipe_offsets[I915_MAX_TRANSCODERS]; | |
789 | int trans_offsets[I915_MAX_TRANSCODERS]; | |
a57c774a | 790 | int palette_offsets[I915_MAX_PIPES]; |
5efb3e28 | 791 | int cursor_offsets[I915_MAX_PIPES]; |
3873218f JM |
792 | |
793 | /* Slice/subslice/EU info */ | |
794 | u8 slice_total; | |
795 | u8 subslice_total; | |
796 | u8 subslice_per_slice; | |
797 | u8 eu_total; | |
798 | u8 eu_per_subslice; | |
b7668791 DL |
799 | /* For each slice, which subslice(s) has(have) 7 EUs (bitfield)? */ |
800 | u8 subslice_7eu[3]; | |
3873218f JM |
801 | u8 has_slice_pg:1; |
802 | u8 has_subslice_pg:1; | |
803 | u8 has_eu_pg:1; | |
cfdf1fa2 KH |
804 | }; |
805 | ||
a587f779 DL |
806 | #undef DEFINE_FLAG |
807 | #undef SEP_SEMICOLON | |
808 | ||
7faf1ab2 DV |
809 | enum i915_cache_level { |
810 | I915_CACHE_NONE = 0, | |
350ec881 CW |
811 | I915_CACHE_LLC, /* also used for snoopable memory on non-LLC */ |
812 | I915_CACHE_L3_LLC, /* gen7+, L3 sits between the domain specifc | |
813 | caches, eg sampler/render caches, and the | |
814 | large Last-Level-Cache. LLC is coherent with | |
815 | the CPU, but L3 is only visible to the GPU. */ | |
651d794f | 816 | I915_CACHE_WT, /* hsw:gt3e WriteThrough for scanouts */ |
7faf1ab2 DV |
817 | }; |
818 | ||
e59ec13d MK |
819 | struct i915_ctx_hang_stats { |
820 | /* This context had batch pending when hang was declared */ | |
821 | unsigned batch_pending; | |
822 | ||
823 | /* This context had batch active when hang was declared */ | |
824 | unsigned batch_active; | |
be62acb4 MK |
825 | |
826 | /* Time when this context was last blamed for a GPU reset */ | |
827 | unsigned long guilty_ts; | |
828 | ||
676fa572 CW |
829 | /* If the contexts causes a second GPU hang within this time, |
830 | * it is permanently banned from submitting any more work. | |
831 | */ | |
832 | unsigned long ban_period_seconds; | |
833 | ||
be62acb4 MK |
834 | /* This context is banned to submit more work */ |
835 | bool banned; | |
e59ec13d | 836 | }; |
40521054 BW |
837 | |
838 | /* This must match up with the value previously used for execbuf2.rsvd1. */ | |
821d66dd | 839 | #define DEFAULT_CONTEXT_HANDLE 0 |
b1b38278 DW |
840 | |
841 | #define CONTEXT_NO_ZEROMAP (1<<0) | |
31b7a88d OM |
842 | /** |
843 | * struct intel_context - as the name implies, represents a context. | |
844 | * @ref: reference count. | |
845 | * @user_handle: userspace tracking identity for this context. | |
846 | * @remap_slice: l3 row remapping information. | |
b1b38278 DW |
847 | * @flags: context specific flags: |
848 | * CONTEXT_NO_ZEROMAP: do not allow mapping things to page 0. | |
31b7a88d OM |
849 | * @file_priv: filp associated with this context (NULL for global default |
850 | * context). | |
851 | * @hang_stats: information about the role of this context in possible GPU | |
852 | * hangs. | |
7df113e4 | 853 | * @ppgtt: virtual memory space used by this context. |
31b7a88d OM |
854 | * @legacy_hw_ctx: render context backing object and whether it is correctly |
855 | * initialized (legacy ring submission mechanism only). | |
856 | * @link: link in the global list of contexts. | |
857 | * | |
858 | * Contexts are memory images used by the hardware to store copies of their | |
859 | * internal state. | |
860 | */ | |
273497e5 | 861 | struct intel_context { |
dce3271b | 862 | struct kref ref; |
821d66dd | 863 | int user_handle; |
3ccfd19d | 864 | uint8_t remap_slice; |
9ea4feec | 865 | struct drm_i915_private *i915; |
b1b38278 | 866 | int flags; |
40521054 | 867 | struct drm_i915_file_private *file_priv; |
e59ec13d | 868 | struct i915_ctx_hang_stats hang_stats; |
ae6c4806 | 869 | struct i915_hw_ppgtt *ppgtt; |
a33afea5 | 870 | |
c9e003af | 871 | /* Legacy ring buffer submission */ |
ea0c76f8 OM |
872 | struct { |
873 | struct drm_i915_gem_object *rcs_state; | |
874 | bool initialized; | |
875 | } legacy_hw_ctx; | |
876 | ||
c9e003af OM |
877 | /* Execlists */ |
878 | struct { | |
879 | struct drm_i915_gem_object *state; | |
84c2377f | 880 | struct intel_ringbuffer *ringbuf; |
a7cbedec | 881 | int pin_count; |
c9e003af OM |
882 | } engine[I915_NUM_RINGS]; |
883 | ||
a33afea5 | 884 | struct list_head link; |
40521054 BW |
885 | }; |
886 | ||
a4001f1b PZ |
887 | enum fb_op_origin { |
888 | ORIGIN_GTT, | |
889 | ORIGIN_CPU, | |
890 | ORIGIN_CS, | |
891 | ORIGIN_FLIP, | |
74b4ea1e | 892 | ORIGIN_DIRTYFB, |
a4001f1b PZ |
893 | }; |
894 | ||
5c3fe8b0 | 895 | struct i915_fbc { |
25ad93fd PZ |
896 | /* This is always the inner lock when overlapping with struct_mutex and |
897 | * it's the outer lock when overlapping with stolen_lock. */ | |
898 | struct mutex lock; | |
5e59f717 | 899 | unsigned threshold; |
5c3fe8b0 | 900 | unsigned int fb_id; |
dbef0f15 PZ |
901 | unsigned int possible_framebuffer_bits; |
902 | unsigned int busy_bits; | |
e35fef21 | 903 | struct intel_crtc *crtc; |
5c3fe8b0 BW |
904 | int y; |
905 | ||
c4213885 | 906 | struct drm_mm_node compressed_fb; |
5c3fe8b0 BW |
907 | struct drm_mm_node *compressed_llb; |
908 | ||
da46f936 RV |
909 | bool false_color; |
910 | ||
d029bcad | 911 | bool enabled; |
0e631adc | 912 | bool active; |
9adccc60 | 913 | |
5c3fe8b0 | 914 | struct intel_fbc_work { |
128d7356 PZ |
915 | bool scheduled; |
916 | struct work_struct work; | |
5c3fe8b0 | 917 | struct drm_framebuffer *fb; |
128d7356 PZ |
918 | unsigned long enable_jiffies; |
919 | } work; | |
5c3fe8b0 | 920 | |
bf6189c6 | 921 | const char *no_fbc_reason; |
ff2a3117 | 922 | |
0e631adc PZ |
923 | bool (*is_active)(struct drm_i915_private *dev_priv); |
924 | void (*activate)(struct intel_crtc *crtc); | |
925 | void (*deactivate)(struct drm_i915_private *dev_priv); | |
b5e50c3f JB |
926 | }; |
927 | ||
96178eeb VK |
928 | /** |
929 | * HIGH_RR is the highest eDP panel refresh rate read from EDID | |
930 | * LOW_RR is the lowest eDP panel refresh rate found from EDID | |
931 | * parsing for same resolution. | |
932 | */ | |
933 | enum drrs_refresh_rate_type { | |
934 | DRRS_HIGH_RR, | |
935 | DRRS_LOW_RR, | |
936 | DRRS_MAX_RR, /* RR count */ | |
937 | }; | |
938 | ||
939 | enum drrs_support_type { | |
940 | DRRS_NOT_SUPPORTED = 0, | |
941 | STATIC_DRRS_SUPPORT = 1, | |
942 | SEAMLESS_DRRS_SUPPORT = 2 | |
439d7ac0 PB |
943 | }; |
944 | ||
2807cf69 | 945 | struct intel_dp; |
96178eeb VK |
946 | struct i915_drrs { |
947 | struct mutex mutex; | |
948 | struct delayed_work work; | |
949 | struct intel_dp *dp; | |
950 | unsigned busy_frontbuffer_bits; | |
951 | enum drrs_refresh_rate_type refresh_rate_type; | |
952 | enum drrs_support_type type; | |
953 | }; | |
954 | ||
a031d709 | 955 | struct i915_psr { |
f0355c4a | 956 | struct mutex lock; |
a031d709 RV |
957 | bool sink_support; |
958 | bool source_ok; | |
2807cf69 | 959 | struct intel_dp *enabled; |
7c8f8a70 RV |
960 | bool active; |
961 | struct delayed_work work; | |
9ca15301 | 962 | unsigned busy_frontbuffer_bits; |
474d1ec4 SJ |
963 | bool psr2_support; |
964 | bool aux_frame_sync; | |
3f51e471 | 965 | }; |
5c3fe8b0 | 966 | |
3bad0781 | 967 | enum intel_pch { |
f0350830 | 968 | PCH_NONE = 0, /* No PCH present */ |
3bad0781 ZW |
969 | PCH_IBX, /* Ibexpeak PCH */ |
970 | PCH_CPT, /* Cougarpoint PCH */ | |
eb877ebf | 971 | PCH_LPT, /* Lynxpoint PCH */ |
e7e7ea20 | 972 | PCH_SPT, /* Sunrisepoint PCH */ |
40c7ead9 | 973 | PCH_NOP, |
3bad0781 ZW |
974 | }; |
975 | ||
988d6ee8 PZ |
976 | enum intel_sbi_destination { |
977 | SBI_ICLK, | |
978 | SBI_MPHY, | |
979 | }; | |
980 | ||
b690e96c | 981 | #define QUIRK_PIPEA_FORCE (1<<0) |
435793df | 982 | #define QUIRK_LVDS_SSC_DISABLE (1<<1) |
4dca20ef | 983 | #define QUIRK_INVERT_BRIGHTNESS (1<<2) |
9c72cc6f | 984 | #define QUIRK_BACKLIGHT_PRESENT (1<<3) |
b6b5d049 | 985 | #define QUIRK_PIPEB_FORCE (1<<4) |
656bfa3a | 986 | #define QUIRK_PIN_SWIZZLED_PAGES (1<<5) |
b690e96c | 987 | |
8be48d92 | 988 | struct intel_fbdev; |
1630fe75 | 989 | struct intel_fbc_work; |
38651674 | 990 | |
c2b9152f DV |
991 | struct intel_gmbus { |
992 | struct i2c_adapter adapter; | |
f2ce9faf | 993 | u32 force_bit; |
c2b9152f | 994 | u32 reg0; |
f0f59a00 | 995 | i915_reg_t gpio_reg; |
c167a6fc | 996 | struct i2c_algo_bit_data bit_algo; |
c2b9152f DV |
997 | struct drm_i915_private *dev_priv; |
998 | }; | |
999 | ||
f4c956ad | 1000 | struct i915_suspend_saved_registers { |
e948e994 | 1001 | u32 saveDSPARB; |
ba8bbcf6 | 1002 | u32 saveLVDS; |
585fb111 JB |
1003 | u32 savePP_ON_DELAYS; |
1004 | u32 savePP_OFF_DELAYS; | |
ba8bbcf6 JB |
1005 | u32 savePP_ON; |
1006 | u32 savePP_OFF; | |
1007 | u32 savePP_CONTROL; | |
585fb111 | 1008 | u32 savePP_DIVISOR; |
ba8bbcf6 | 1009 | u32 saveFBC_CONTROL; |
1f84e550 | 1010 | u32 saveCACHE_MODE_0; |
1f84e550 | 1011 | u32 saveMI_ARB_STATE; |
ba8bbcf6 JB |
1012 | u32 saveSWF0[16]; |
1013 | u32 saveSWF1[16]; | |
85fa792b | 1014 | u32 saveSWF3[3]; |
4b9de737 | 1015 | uint64_t saveFENCE[I915_MAX_NUM_FENCES]; |
cda2bb78 | 1016 | u32 savePCH_PORT_HOTPLUG; |
9f49c376 | 1017 | u16 saveGCDGMBUS; |
f4c956ad | 1018 | }; |
c85aa885 | 1019 | |
ddeea5b0 ID |
1020 | struct vlv_s0ix_state { |
1021 | /* GAM */ | |
1022 | u32 wr_watermark; | |
1023 | u32 gfx_prio_ctrl; | |
1024 | u32 arb_mode; | |
1025 | u32 gfx_pend_tlb0; | |
1026 | u32 gfx_pend_tlb1; | |
1027 | u32 lra_limits[GEN7_LRA_LIMITS_REG_NUM]; | |
1028 | u32 media_max_req_count; | |
1029 | u32 gfx_max_req_count; | |
1030 | u32 render_hwsp; | |
1031 | u32 ecochk; | |
1032 | u32 bsd_hwsp; | |
1033 | u32 blt_hwsp; | |
1034 | u32 tlb_rd_addr; | |
1035 | ||
1036 | /* MBC */ | |
1037 | u32 g3dctl; | |
1038 | u32 gsckgctl; | |
1039 | u32 mbctl; | |
1040 | ||
1041 | /* GCP */ | |
1042 | u32 ucgctl1; | |
1043 | u32 ucgctl3; | |
1044 | u32 rcgctl1; | |
1045 | u32 rcgctl2; | |
1046 | u32 rstctl; | |
1047 | u32 misccpctl; | |
1048 | ||
1049 | /* GPM */ | |
1050 | u32 gfxpause; | |
1051 | u32 rpdeuhwtc; | |
1052 | u32 rpdeuc; | |
1053 | u32 ecobus; | |
1054 | u32 pwrdwnupctl; | |
1055 | u32 rp_down_timeout; | |
1056 | u32 rp_deucsw; | |
1057 | u32 rcubmabdtmr; | |
1058 | u32 rcedata; | |
1059 | u32 spare2gh; | |
1060 | ||
1061 | /* Display 1 CZ domain */ | |
1062 | u32 gt_imr; | |
1063 | u32 gt_ier; | |
1064 | u32 pm_imr; | |
1065 | u32 pm_ier; | |
1066 | u32 gt_scratch[GEN7_GT_SCRATCH_REG_NUM]; | |
1067 | ||
1068 | /* GT SA CZ domain */ | |
1069 | u32 tilectl; | |
1070 | u32 gt_fifoctl; | |
1071 | u32 gtlc_wake_ctrl; | |
1072 | u32 gtlc_survive; | |
1073 | u32 pmwgicz; | |
1074 | ||
1075 | /* Display 2 CZ domain */ | |
1076 | u32 gu_ctl0; | |
1077 | u32 gu_ctl1; | |
9c25210f | 1078 | u32 pcbr; |
ddeea5b0 ID |
1079 | u32 clock_gate_dis2; |
1080 | }; | |
1081 | ||
bf225f20 CW |
1082 | struct intel_rps_ei { |
1083 | u32 cz_clock; | |
1084 | u32 render_c0; | |
1085 | u32 media_c0; | |
31685c25 D |
1086 | }; |
1087 | ||
c85aa885 | 1088 | struct intel_gen6_power_mgmt { |
d4d70aa5 ID |
1089 | /* |
1090 | * work, interrupts_enabled and pm_iir are protected by | |
1091 | * dev_priv->irq_lock | |
1092 | */ | |
c85aa885 | 1093 | struct work_struct work; |
d4d70aa5 | 1094 | bool interrupts_enabled; |
c85aa885 | 1095 | u32 pm_iir; |
59cdb63d | 1096 | |
b39fb297 BW |
1097 | /* Frequencies are stored in potentially platform dependent multiples. |
1098 | * In other words, *_freq needs to be multiplied by X to be interesting. | |
1099 | * Soft limits are those which are used for the dynamic reclocking done | |
1100 | * by the driver (raise frequencies under heavy loads, and lower for | |
1101 | * lighter loads). Hard limits are those imposed by the hardware. | |
1102 | * | |
1103 | * A distinction is made for overclocking, which is never enabled by | |
1104 | * default, and is considered to be above the hard limit if it's | |
1105 | * possible at all. | |
1106 | */ | |
1107 | u8 cur_freq; /* Current frequency (cached, may not == HW) */ | |
1108 | u8 min_freq_softlimit; /* Minimum frequency permitted by the driver */ | |
1109 | u8 max_freq_softlimit; /* Max frequency permitted by the driver */ | |
1110 | u8 max_freq; /* Maximum frequency, RP0 if not overclocking */ | |
1111 | u8 min_freq; /* AKA RPn. Minimum frequency */ | |
aed242ff | 1112 | u8 idle_freq; /* Frequency to request when we are idle */ |
b39fb297 BW |
1113 | u8 efficient_freq; /* AKA RPe. Pre-determined balanced frequency */ |
1114 | u8 rp1_freq; /* "less than" RP0 power/freqency */ | |
1115 | u8 rp0_freq; /* Non-overclocked max frequency. */ | |
1a01ab3b | 1116 | |
8fb55197 CW |
1117 | u8 up_threshold; /* Current %busy required to uplock */ |
1118 | u8 down_threshold; /* Current %busy required to downclock */ | |
1119 | ||
dd75fdc8 CW |
1120 | int last_adj; |
1121 | enum { LOW_POWER, BETWEEN, HIGH_POWER } power; | |
1122 | ||
8d3afd7d CW |
1123 | spinlock_t client_lock; |
1124 | struct list_head clients; | |
1125 | bool client_boost; | |
1126 | ||
c0951f0c | 1127 | bool enabled; |
1a01ab3b | 1128 | struct delayed_work delayed_resume_work; |
1854d5ca | 1129 | unsigned boosts; |
4fc688ce | 1130 | |
2e1b8730 | 1131 | struct intel_rps_client semaphores, mmioflips; |
a6f766f3 | 1132 | |
bf225f20 CW |
1133 | /* manual wa residency calculations */ |
1134 | struct intel_rps_ei up_ei, down_ei; | |
1135 | ||
4fc688ce JB |
1136 | /* |
1137 | * Protects RPS/RC6 register access and PCU communication. | |
8d3afd7d CW |
1138 | * Must be taken after struct_mutex if nested. Note that |
1139 | * this lock may be held for long periods of time when | |
1140 | * talking to hw - so only take it when talking to hw! | |
4fc688ce JB |
1141 | */ |
1142 | struct mutex hw_lock; | |
c85aa885 DV |
1143 | }; |
1144 | ||
1a240d4d DV |
1145 | /* defined intel_pm.c */ |
1146 | extern spinlock_t mchdev_lock; | |
1147 | ||
c85aa885 DV |
1148 | struct intel_ilk_power_mgmt { |
1149 | u8 cur_delay; | |
1150 | u8 min_delay; | |
1151 | u8 max_delay; | |
1152 | u8 fmax; | |
1153 | u8 fstart; | |
1154 | ||
1155 | u64 last_count1; | |
1156 | unsigned long last_time1; | |
1157 | unsigned long chipset_power; | |
1158 | u64 last_count2; | |
5ed0bdf2 | 1159 | u64 last_time2; |
c85aa885 DV |
1160 | unsigned long gfx_power; |
1161 | u8 corr; | |
1162 | ||
1163 | int c_m; | |
1164 | int r_t; | |
1165 | }; | |
1166 | ||
c6cb582e ID |
1167 | struct drm_i915_private; |
1168 | struct i915_power_well; | |
1169 | ||
1170 | struct i915_power_well_ops { | |
1171 | /* | |
1172 | * Synchronize the well's hw state to match the current sw state, for | |
1173 | * example enable/disable it based on the current refcount. Called | |
1174 | * during driver init and resume time, possibly after first calling | |
1175 | * the enable/disable handlers. | |
1176 | */ | |
1177 | void (*sync_hw)(struct drm_i915_private *dev_priv, | |
1178 | struct i915_power_well *power_well); | |
1179 | /* | |
1180 | * Enable the well and resources that depend on it (for example | |
1181 | * interrupts located on the well). Called after the 0->1 refcount | |
1182 | * transition. | |
1183 | */ | |
1184 | void (*enable)(struct drm_i915_private *dev_priv, | |
1185 | struct i915_power_well *power_well); | |
1186 | /* | |
1187 | * Disable the well and resources that depend on it. Called after | |
1188 | * the 1->0 refcount transition. | |
1189 | */ | |
1190 | void (*disable)(struct drm_i915_private *dev_priv, | |
1191 | struct i915_power_well *power_well); | |
1192 | /* Returns the hw enabled state. */ | |
1193 | bool (*is_enabled)(struct drm_i915_private *dev_priv, | |
1194 | struct i915_power_well *power_well); | |
1195 | }; | |
1196 | ||
a38911a3 WX |
1197 | /* Power well structure for haswell */ |
1198 | struct i915_power_well { | |
c1ca727f | 1199 | const char *name; |
6f3ef5dd | 1200 | bool always_on; |
a38911a3 WX |
1201 | /* power well enable/disable usage count */ |
1202 | int count; | |
bfafe93a ID |
1203 | /* cached hw enabled state */ |
1204 | bool hw_enabled; | |
c1ca727f | 1205 | unsigned long domains; |
77961eb9 | 1206 | unsigned long data; |
c6cb582e | 1207 | const struct i915_power_well_ops *ops; |
a38911a3 WX |
1208 | }; |
1209 | ||
83c00f55 | 1210 | struct i915_power_domains { |
baa70707 ID |
1211 | /* |
1212 | * Power wells needed for initialization at driver init and suspend | |
1213 | * time are on. They are kept on until after the first modeset. | |
1214 | */ | |
1215 | bool init_power_on; | |
0d116a29 | 1216 | bool initializing; |
c1ca727f | 1217 | int power_well_count; |
baa70707 | 1218 | |
83c00f55 | 1219 | struct mutex lock; |
1da51581 | 1220 | int domain_use_count[POWER_DOMAIN_NUM]; |
c1ca727f | 1221 | struct i915_power_well *power_wells; |
83c00f55 ID |
1222 | }; |
1223 | ||
35a85ac6 | 1224 | #define MAX_L3_SLICES 2 |
a4da4fa4 | 1225 | struct intel_l3_parity { |
35a85ac6 | 1226 | u32 *remap_info[MAX_L3_SLICES]; |
a4da4fa4 | 1227 | struct work_struct error_work; |
35a85ac6 | 1228 | int which_slice; |
a4da4fa4 DV |
1229 | }; |
1230 | ||
4b5aed62 | 1231 | struct i915_gem_mm { |
4b5aed62 DV |
1232 | /** Memory allocator for GTT stolen memory */ |
1233 | struct drm_mm stolen; | |
92e97d2f PZ |
1234 | /** Protects the usage of the GTT stolen memory allocator. This is |
1235 | * always the inner lock when overlapping with struct_mutex. */ | |
1236 | struct mutex stolen_lock; | |
1237 | ||
4b5aed62 DV |
1238 | /** List of all objects in gtt_space. Used to restore gtt |
1239 | * mappings on resume */ | |
1240 | struct list_head bound_list; | |
1241 | /** | |
1242 | * List of objects which are not bound to the GTT (thus | |
1243 | * are idle and not used by the GPU) but still have | |
1244 | * (presumably uncached) pages still attached. | |
1245 | */ | |
1246 | struct list_head unbound_list; | |
1247 | ||
1248 | /** Usable portion of the GTT for GEM */ | |
1249 | unsigned long stolen_base; /* limited to low memory (32-bit) */ | |
1250 | ||
4b5aed62 DV |
1251 | /** PPGTT used for aliasing the PPGTT with the GTT */ |
1252 | struct i915_hw_ppgtt *aliasing_ppgtt; | |
1253 | ||
2cfcd32a | 1254 | struct notifier_block oom_notifier; |
ceabbba5 | 1255 | struct shrinker shrinker; |
4b5aed62 DV |
1256 | bool shrinker_no_lock_stealing; |
1257 | ||
4b5aed62 DV |
1258 | /** LRU list of objects with fence regs on them. */ |
1259 | struct list_head fence_list; | |
1260 | ||
1261 | /** | |
1262 | * We leave the user IRQ off as much as possible, | |
1263 | * but this means that requests will finish and never | |
1264 | * be retired once the system goes idle. Set a timer to | |
1265 | * fire periodically while the ring is running. When it | |
1266 | * fires, go retire requests. | |
1267 | */ | |
1268 | struct delayed_work retire_work; | |
1269 | ||
b29c19b6 CW |
1270 | /** |
1271 | * When we detect an idle GPU, we want to turn on | |
1272 | * powersaving features. So once we see that there | |
1273 | * are no more requests outstanding and no more | |
1274 | * arrive within a small period of time, we fire | |
1275 | * off the idle_work. | |
1276 | */ | |
1277 | struct delayed_work idle_work; | |
1278 | ||
4b5aed62 DV |
1279 | /** |
1280 | * Are we in a non-interruptible section of code like | |
1281 | * modesetting? | |
1282 | */ | |
1283 | bool interruptible; | |
1284 | ||
f62a0076 CW |
1285 | /** |
1286 | * Is the GPU currently considered idle, or busy executing userspace | |
1287 | * requests? Whilst idle, we attempt to power down the hardware and | |
1288 | * display clocks. In order to reduce the effect on performance, there | |
1289 | * is a slight delay before we do so. | |
1290 | */ | |
1291 | bool busy; | |
1292 | ||
bdf1e7e3 DV |
1293 | /* the indicator for dispatch video commands on two BSD rings */ |
1294 | int bsd_ring_dispatch_index; | |
1295 | ||
4b5aed62 DV |
1296 | /** Bit 6 swizzling required for X tiling */ |
1297 | uint32_t bit_6_swizzle_x; | |
1298 | /** Bit 6 swizzling required for Y tiling */ | |
1299 | uint32_t bit_6_swizzle_y; | |
1300 | ||
4b5aed62 | 1301 | /* accounting, useful for userland debugging */ |
c20e8355 | 1302 | spinlock_t object_stat_lock; |
4b5aed62 DV |
1303 | size_t object_memory; |
1304 | u32 object_count; | |
1305 | }; | |
1306 | ||
edc3d884 | 1307 | struct drm_i915_error_state_buf { |
0a4cd7c8 | 1308 | struct drm_i915_private *i915; |
edc3d884 MK |
1309 | unsigned bytes; |
1310 | unsigned size; | |
1311 | int err; | |
1312 | u8 *buf; | |
1313 | loff_t start; | |
1314 | loff_t pos; | |
1315 | }; | |
1316 | ||
fc16b48b MK |
1317 | struct i915_error_state_file_priv { |
1318 | struct drm_device *dev; | |
1319 | struct drm_i915_error_state *error; | |
1320 | }; | |
1321 | ||
99584db3 DV |
1322 | struct i915_gpu_error { |
1323 | /* For hangcheck timer */ | |
1324 | #define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */ | |
1325 | #define DRM_I915_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD) | |
be62acb4 MK |
1326 | /* Hang gpu twice in this window and your context gets banned */ |
1327 | #define DRM_I915_CTX_BAN_PERIOD DIV_ROUND_UP(8*DRM_I915_HANGCHECK_PERIOD, 1000) | |
1328 | ||
737b1506 CW |
1329 | struct workqueue_struct *hangcheck_wq; |
1330 | struct delayed_work hangcheck_work; | |
99584db3 DV |
1331 | |
1332 | /* For reset and error_state handling. */ | |
1333 | spinlock_t lock; | |
1334 | /* Protected by the above dev->gpu_error.lock. */ | |
1335 | struct drm_i915_error_state *first_error; | |
094f9a54 CW |
1336 | |
1337 | unsigned long missed_irq_rings; | |
1338 | ||
1f83fee0 | 1339 | /** |
2ac0f450 | 1340 | * State variable controlling the reset flow and count |
1f83fee0 | 1341 | * |
2ac0f450 MK |
1342 | * This is a counter which gets incremented when reset is triggered, |
1343 | * and again when reset has been handled. So odd values (lowest bit set) | |
1344 | * means that reset is in progress and even values that | |
1345 | * (reset_counter >> 1):th reset was successfully completed. | |
1346 | * | |
1347 | * If reset is not completed succesfully, the I915_WEDGE bit is | |
1348 | * set meaning that hardware is terminally sour and there is no | |
1349 | * recovery. All waiters on the reset_queue will be woken when | |
1350 | * that happens. | |
1351 | * | |
1352 | * This counter is used by the wait_seqno code to notice that reset | |
1353 | * event happened and it needs to restart the entire ioctl (since most | |
1354 | * likely the seqno it waited for won't ever signal anytime soon). | |
f69061be DV |
1355 | * |
1356 | * This is important for lock-free wait paths, where no contended lock | |
1357 | * naturally enforces the correct ordering between the bail-out of the | |
1358 | * waiter and the gpu reset work code. | |
1f83fee0 DV |
1359 | */ |
1360 | atomic_t reset_counter; | |
1361 | ||
1f83fee0 | 1362 | #define I915_RESET_IN_PROGRESS_FLAG 1 |
2ac0f450 | 1363 | #define I915_WEDGED (1 << 31) |
1f83fee0 DV |
1364 | |
1365 | /** | |
1366 | * Waitqueue to signal when the reset has completed. Used by clients | |
1367 | * that wait for dev_priv->mm.wedged to settle. | |
1368 | */ | |
1369 | wait_queue_head_t reset_queue; | |
33196ded | 1370 | |
88b4aa87 MK |
1371 | /* Userspace knobs for gpu hang simulation; |
1372 | * combines both a ring mask, and extra flags | |
1373 | */ | |
1374 | u32 stop_rings; | |
1375 | #define I915_STOP_RING_ALLOW_BAN (1 << 31) | |
1376 | #define I915_STOP_RING_ALLOW_WARN (1 << 30) | |
094f9a54 CW |
1377 | |
1378 | /* For missed irq/seqno simulation. */ | |
1379 | unsigned int test_irq_rings; | |
6689c167 MA |
1380 | |
1381 | /* Used to prevent gem_check_wedged returning -EAGAIN during gpu reset */ | |
1382 | bool reload_in_reset; | |
99584db3 DV |
1383 | }; |
1384 | ||
b8efb17b ZR |
1385 | enum modeset_restore { |
1386 | MODESET_ON_LID_OPEN, | |
1387 | MODESET_DONE, | |
1388 | MODESET_SUSPENDED, | |
1389 | }; | |
1390 | ||
500ea70d RV |
1391 | #define DP_AUX_A 0x40 |
1392 | #define DP_AUX_B 0x10 | |
1393 | #define DP_AUX_C 0x20 | |
1394 | #define DP_AUX_D 0x30 | |
1395 | ||
11c1b657 XZ |
1396 | #define DDC_PIN_B 0x05 |
1397 | #define DDC_PIN_C 0x04 | |
1398 | #define DDC_PIN_D 0x06 | |
1399 | ||
6acab15a | 1400 | struct ddi_vbt_port_info { |
ce4dd49e DL |
1401 | /* |
1402 | * This is an index in the HDMI/DVI DDI buffer translation table. | |
1403 | * The special value HDMI_LEVEL_SHIFT_UNKNOWN means the VBT didn't | |
1404 | * populate this field. | |
1405 | */ | |
1406 | #define HDMI_LEVEL_SHIFT_UNKNOWN 0xff | |
6acab15a | 1407 | uint8_t hdmi_level_shift; |
311a2094 PZ |
1408 | |
1409 | uint8_t supports_dvi:1; | |
1410 | uint8_t supports_hdmi:1; | |
1411 | uint8_t supports_dp:1; | |
500ea70d RV |
1412 | |
1413 | uint8_t alternate_aux_channel; | |
11c1b657 | 1414 | uint8_t alternate_ddc_pin; |
75067dde AK |
1415 | |
1416 | uint8_t dp_boost_level; | |
1417 | uint8_t hdmi_boost_level; | |
6acab15a PZ |
1418 | }; |
1419 | ||
bfd7ebda RV |
1420 | enum psr_lines_to_wait { |
1421 | PSR_0_LINES_TO_WAIT = 0, | |
1422 | PSR_1_LINE_TO_WAIT, | |
1423 | PSR_4_LINES_TO_WAIT, | |
1424 | PSR_8_LINES_TO_WAIT | |
83a7280e PB |
1425 | }; |
1426 | ||
41aa3448 RV |
1427 | struct intel_vbt_data { |
1428 | struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */ | |
1429 | struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */ | |
1430 | ||
1431 | /* Feature bits */ | |
1432 | unsigned int int_tv_support:1; | |
1433 | unsigned int lvds_dither:1; | |
1434 | unsigned int lvds_vbt:1; | |
1435 | unsigned int int_crt_support:1; | |
1436 | unsigned int lvds_use_ssc:1; | |
1437 | unsigned int display_clock_mode:1; | |
1438 | unsigned int fdi_rx_polarity_inverted:1; | |
3e6bd011 | 1439 | unsigned int has_mipi:1; |
41aa3448 RV |
1440 | int lvds_ssc_freq; |
1441 | unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */ | |
1442 | ||
83a7280e PB |
1443 | enum drrs_support_type drrs_type; |
1444 | ||
41aa3448 RV |
1445 | /* eDP */ |
1446 | int edp_rate; | |
1447 | int edp_lanes; | |
1448 | int edp_preemphasis; | |
1449 | int edp_vswing; | |
1450 | bool edp_initialized; | |
1451 | bool edp_support; | |
1452 | int edp_bpp; | |
1453 | struct edp_power_seq edp_pps; | |
1454 | ||
bfd7ebda RV |
1455 | struct { |
1456 | bool full_link; | |
1457 | bool require_aux_wakeup; | |
1458 | int idle_frames; | |
1459 | enum psr_lines_to_wait lines_to_wait; | |
1460 | int tp1_wakeup_time; | |
1461 | int tp2_tp3_wakeup_time; | |
1462 | } psr; | |
1463 | ||
f00076d2 JN |
1464 | struct { |
1465 | u16 pwm_freq_hz; | |
39fbc9c8 | 1466 | bool present; |
f00076d2 | 1467 | bool active_low_pwm; |
1de6068e | 1468 | u8 min_brightness; /* min_brightness/255 of max */ |
f00076d2 JN |
1469 | } backlight; |
1470 | ||
d17c5443 SK |
1471 | /* MIPI DSI */ |
1472 | struct { | |
3e6bd011 | 1473 | u16 port; |
d17c5443 | 1474 | u16 panel_id; |
d3b542fc SK |
1475 | struct mipi_config *config; |
1476 | struct mipi_pps_data *pps; | |
1477 | u8 seq_version; | |
1478 | u32 size; | |
1479 | u8 *data; | |
1480 | u8 *sequence[MIPI_SEQ_MAX]; | |
d17c5443 SK |
1481 | } dsi; |
1482 | ||
41aa3448 RV |
1483 | int crt_ddc_pin; |
1484 | ||
1485 | int child_dev_num; | |
768f69c9 | 1486 | union child_device_config *child_dev; |
6acab15a PZ |
1487 | |
1488 | struct ddi_vbt_port_info ddi_port_info[I915_MAX_PORTS]; | |
41aa3448 RV |
1489 | }; |
1490 | ||
77c122bc VS |
1491 | enum intel_ddb_partitioning { |
1492 | INTEL_DDB_PART_1_2, | |
1493 | INTEL_DDB_PART_5_6, /* IVB+ */ | |
1494 | }; | |
1495 | ||
1fd527cc VS |
1496 | struct intel_wm_level { |
1497 | bool enable; | |
1498 | uint32_t pri_val; | |
1499 | uint32_t spr_val; | |
1500 | uint32_t cur_val; | |
1501 | uint32_t fbc_val; | |
1502 | }; | |
1503 | ||
820c1980 | 1504 | struct ilk_wm_values { |
609cedef VS |
1505 | uint32_t wm_pipe[3]; |
1506 | uint32_t wm_lp[3]; | |
1507 | uint32_t wm_lp_spr[3]; | |
1508 | uint32_t wm_linetime[3]; | |
1509 | bool enable_fbc_wm; | |
1510 | enum intel_ddb_partitioning partitioning; | |
1511 | }; | |
1512 | ||
262cd2e1 VS |
1513 | struct vlv_pipe_wm { |
1514 | uint16_t primary; | |
1515 | uint16_t sprite[2]; | |
1516 | uint8_t cursor; | |
1517 | }; | |
ae80152d | 1518 | |
262cd2e1 VS |
1519 | struct vlv_sr_wm { |
1520 | uint16_t plane; | |
1521 | uint8_t cursor; | |
1522 | }; | |
ae80152d | 1523 | |
262cd2e1 VS |
1524 | struct vlv_wm_values { |
1525 | struct vlv_pipe_wm pipe[3]; | |
1526 | struct vlv_sr_wm sr; | |
0018fda1 VS |
1527 | struct { |
1528 | uint8_t cursor; | |
1529 | uint8_t sprite[2]; | |
1530 | uint8_t primary; | |
1531 | } ddl[3]; | |
6eb1a681 VS |
1532 | uint8_t level; |
1533 | bool cxsr; | |
0018fda1 VS |
1534 | }; |
1535 | ||
c193924e | 1536 | struct skl_ddb_entry { |
16160e3d | 1537 | uint16_t start, end; /* in number of blocks, 'end' is exclusive */ |
c193924e DL |
1538 | }; |
1539 | ||
1540 | static inline uint16_t skl_ddb_entry_size(const struct skl_ddb_entry *entry) | |
1541 | { | |
16160e3d | 1542 | return entry->end - entry->start; |
c193924e DL |
1543 | } |
1544 | ||
08db6652 DL |
1545 | static inline bool skl_ddb_entry_equal(const struct skl_ddb_entry *e1, |
1546 | const struct skl_ddb_entry *e2) | |
1547 | { | |
1548 | if (e1->start == e2->start && e1->end == e2->end) | |
1549 | return true; | |
1550 | ||
1551 | return false; | |
1552 | } | |
1553 | ||
c193924e | 1554 | struct skl_ddb_allocation { |
34bb56af | 1555 | struct skl_ddb_entry pipe[I915_MAX_PIPES]; |
2cd601c6 | 1556 | struct skl_ddb_entry plane[I915_MAX_PIPES][I915_MAX_PLANES]; /* packed/uv */ |
4969d33e | 1557 | struct skl_ddb_entry y_plane[I915_MAX_PIPES][I915_MAX_PLANES]; |
c193924e DL |
1558 | }; |
1559 | ||
2ac96d2a PB |
1560 | struct skl_wm_values { |
1561 | bool dirty[I915_MAX_PIPES]; | |
c193924e | 1562 | struct skl_ddb_allocation ddb; |
2ac96d2a PB |
1563 | uint32_t wm_linetime[I915_MAX_PIPES]; |
1564 | uint32_t plane[I915_MAX_PIPES][I915_MAX_PLANES][8]; | |
2ac96d2a | 1565 | uint32_t plane_trans[I915_MAX_PIPES][I915_MAX_PLANES]; |
2ac96d2a PB |
1566 | }; |
1567 | ||
1568 | struct skl_wm_level { | |
1569 | bool plane_en[I915_MAX_PLANES]; | |
1570 | uint16_t plane_res_b[I915_MAX_PLANES]; | |
1571 | uint8_t plane_res_l[I915_MAX_PLANES]; | |
2ac96d2a PB |
1572 | }; |
1573 | ||
c67a470b | 1574 | /* |
765dab67 PZ |
1575 | * This struct helps tracking the state needed for runtime PM, which puts the |
1576 | * device in PCI D3 state. Notice that when this happens, nothing on the | |
1577 | * graphics device works, even register access, so we don't get interrupts nor | |
1578 | * anything else. | |
c67a470b | 1579 | * |
765dab67 PZ |
1580 | * Every piece of our code that needs to actually touch the hardware needs to |
1581 | * either call intel_runtime_pm_get or call intel_display_power_get with the | |
1582 | * appropriate power domain. | |
a8a8bd54 | 1583 | * |
765dab67 PZ |
1584 | * Our driver uses the autosuspend delay feature, which means we'll only really |
1585 | * suspend if we stay with zero refcount for a certain amount of time. The | |
f458ebbc | 1586 | * default value is currently very conservative (see intel_runtime_pm_enable), but |
765dab67 | 1587 | * it can be changed with the standard runtime PM files from sysfs. |
c67a470b PZ |
1588 | * |
1589 | * The irqs_disabled variable becomes true exactly after we disable the IRQs and | |
1590 | * goes back to false exactly before we reenable the IRQs. We use this variable | |
1591 | * to check if someone is trying to enable/disable IRQs while they're supposed | |
1592 | * to be disabled. This shouldn't happen and we'll print some error messages in | |
730488b2 | 1593 | * case it happens. |
c67a470b | 1594 | * |
765dab67 | 1595 | * For more, read the Documentation/power/runtime_pm.txt. |
c67a470b | 1596 | */ |
5d584b2e | 1597 | struct i915_runtime_pm { |
1f814dac | 1598 | atomic_t wakeref_count; |
2b19efeb | 1599 | atomic_t atomic_seq; |
5d584b2e | 1600 | bool suspended; |
2aeb7d3a | 1601 | bool irqs_enabled; |
c67a470b PZ |
1602 | }; |
1603 | ||
926321d5 DV |
1604 | enum intel_pipe_crc_source { |
1605 | INTEL_PIPE_CRC_SOURCE_NONE, | |
1606 | INTEL_PIPE_CRC_SOURCE_PLANE1, | |
1607 | INTEL_PIPE_CRC_SOURCE_PLANE2, | |
1608 | INTEL_PIPE_CRC_SOURCE_PF, | |
5b3a856b | 1609 | INTEL_PIPE_CRC_SOURCE_PIPE, |
3d099a05 DV |
1610 | /* TV/DP on pre-gen5/vlv can't use the pipe source. */ |
1611 | INTEL_PIPE_CRC_SOURCE_TV, | |
1612 | INTEL_PIPE_CRC_SOURCE_DP_B, | |
1613 | INTEL_PIPE_CRC_SOURCE_DP_C, | |
1614 | INTEL_PIPE_CRC_SOURCE_DP_D, | |
46a19188 | 1615 | INTEL_PIPE_CRC_SOURCE_AUTO, |
926321d5 DV |
1616 | INTEL_PIPE_CRC_SOURCE_MAX, |
1617 | }; | |
1618 | ||
8bf1e9f1 | 1619 | struct intel_pipe_crc_entry { |
ac2300d4 | 1620 | uint32_t frame; |
8bf1e9f1 SH |
1621 | uint32_t crc[5]; |
1622 | }; | |
1623 | ||
b2c88f5b | 1624 | #define INTEL_PIPE_CRC_ENTRIES_NR 128 |
8bf1e9f1 | 1625 | struct intel_pipe_crc { |
d538bbdf DL |
1626 | spinlock_t lock; |
1627 | bool opened; /* exclusive access to the result file */ | |
e5f75aca | 1628 | struct intel_pipe_crc_entry *entries; |
926321d5 | 1629 | enum intel_pipe_crc_source source; |
d538bbdf | 1630 | int head, tail; |
07144428 | 1631 | wait_queue_head_t wq; |
8bf1e9f1 SH |
1632 | }; |
1633 | ||
f99d7069 DV |
1634 | struct i915_frontbuffer_tracking { |
1635 | struct mutex lock; | |
1636 | ||
1637 | /* | |
1638 | * Tracking bits for delayed frontbuffer flushing du to gpu activity or | |
1639 | * scheduled flips. | |
1640 | */ | |
1641 | unsigned busy_bits; | |
1642 | unsigned flip_bits; | |
1643 | }; | |
1644 | ||
7225342a | 1645 | struct i915_wa_reg { |
f0f59a00 | 1646 | i915_reg_t addr; |
7225342a MK |
1647 | u32 value; |
1648 | /* bitmask representing WA bits */ | |
1649 | u32 mask; | |
1650 | }; | |
1651 | ||
1652 | #define I915_MAX_WA_REGS 16 | |
1653 | ||
1654 | struct i915_workarounds { | |
1655 | struct i915_wa_reg reg[I915_MAX_WA_REGS]; | |
1656 | u32 count; | |
1657 | }; | |
1658 | ||
cf9d2890 YZ |
1659 | struct i915_virtual_gpu { |
1660 | bool active; | |
1661 | }; | |
1662 | ||
5f19e2bf JH |
1663 | struct i915_execbuffer_params { |
1664 | struct drm_device *dev; | |
1665 | struct drm_file *file; | |
1666 | uint32_t dispatch_flags; | |
1667 | uint32_t args_batch_start_offset; | |
af98714e | 1668 | uint64_t batch_obj_vm_offset; |
5f19e2bf JH |
1669 | struct intel_engine_cs *ring; |
1670 | struct drm_i915_gem_object *batch_obj; | |
1671 | struct intel_context *ctx; | |
6a6ae79a | 1672 | struct drm_i915_gem_request *request; |
5f19e2bf JH |
1673 | }; |
1674 | ||
aa363136 MR |
1675 | /* used in computing the new watermarks state */ |
1676 | struct intel_wm_config { | |
1677 | unsigned int num_pipes_active; | |
1678 | bool sprites_enabled; | |
1679 | bool sprites_scaled; | |
1680 | }; | |
1681 | ||
77fec556 | 1682 | struct drm_i915_private { |
f4c956ad | 1683 | struct drm_device *dev; |
efab6d8d | 1684 | struct kmem_cache *objects; |
e20d2ab7 | 1685 | struct kmem_cache *vmas; |
efab6d8d | 1686 | struct kmem_cache *requests; |
f4c956ad | 1687 | |
5c969aa7 | 1688 | const struct intel_device_info info; |
f4c956ad DV |
1689 | |
1690 | int relative_constants_mode; | |
1691 | ||
1692 | void __iomem *regs; | |
1693 | ||
907b28c5 | 1694 | struct intel_uncore uncore; |
f4c956ad | 1695 | |
cf9d2890 YZ |
1696 | struct i915_virtual_gpu vgpu; |
1697 | ||
33a732f4 AD |
1698 | struct intel_guc guc; |
1699 | ||
eb805623 DV |
1700 | struct intel_csr csr; |
1701 | ||
5ea6e5e3 | 1702 | struct intel_gmbus gmbus[GMBUS_NUM_PINS]; |
28c70f16 | 1703 | |
f4c956ad DV |
1704 | /** gmbus_mutex protects against concurrent usage of the single hw gmbus |
1705 | * controller on different i2c buses. */ | |
1706 | struct mutex gmbus_mutex; | |
1707 | ||
1708 | /** | |
1709 | * Base address of the gmbus and gpio block. | |
1710 | */ | |
1711 | uint32_t gpio_mmio_base; | |
1712 | ||
b6fdd0f2 SS |
1713 | /* MMIO base address for MIPI regs */ |
1714 | uint32_t mipi_mmio_base; | |
1715 | ||
443a389f VS |
1716 | uint32_t psr_mmio_base; |
1717 | ||
28c70f16 DV |
1718 | wait_queue_head_t gmbus_wait_queue; |
1719 | ||
f4c956ad | 1720 | struct pci_dev *bridge_dev; |
a4872ba6 | 1721 | struct intel_engine_cs ring[I915_NUM_RINGS]; |
3e78998a | 1722 | struct drm_i915_gem_object *semaphore_obj; |
f72b3435 | 1723 | uint32_t last_seqno, next_seqno; |
f4c956ad | 1724 | |
ba8286fa | 1725 | struct drm_dma_handle *status_page_dmah; |
f4c956ad DV |
1726 | struct resource mch_res; |
1727 | ||
f4c956ad DV |
1728 | /* protects the irq masks */ |
1729 | spinlock_t irq_lock; | |
1730 | ||
84c33a64 SG |
1731 | /* protects the mmio flip data */ |
1732 | spinlock_t mmio_flip_lock; | |
1733 | ||
f8b79e58 ID |
1734 | bool display_irqs_enabled; |
1735 | ||
9ee32fea DV |
1736 | /* To control wakeup latency, e.g. for irq-driven dp aux transfers. */ |
1737 | struct pm_qos_request pm_qos; | |
1738 | ||
a580516d VS |
1739 | /* Sideband mailbox protection */ |
1740 | struct mutex sb_lock; | |
f4c956ad DV |
1741 | |
1742 | /** Cached value of IMR to avoid reads in updating the bitfield */ | |
abd58f01 BW |
1743 | union { |
1744 | u32 irq_mask; | |
1745 | u32 de_irq_mask[I915_MAX_PIPES]; | |
1746 | }; | |
f4c956ad | 1747 | u32 gt_irq_mask; |
605cd25b | 1748 | u32 pm_irq_mask; |
a6706b45 | 1749 | u32 pm_rps_events; |
91d181dd | 1750 | u32 pipestat_irq_mask[I915_MAX_PIPES]; |
f4c956ad | 1751 | |
5fcece80 | 1752 | struct i915_hotplug hotplug; |
5c3fe8b0 | 1753 | struct i915_fbc fbc; |
439d7ac0 | 1754 | struct i915_drrs drrs; |
f4c956ad | 1755 | struct intel_opregion opregion; |
41aa3448 | 1756 | struct intel_vbt_data vbt; |
f4c956ad | 1757 | |
d9ceb816 JB |
1758 | bool preserve_bios_swizzle; |
1759 | ||
f4c956ad DV |
1760 | /* overlay */ |
1761 | struct intel_overlay *overlay; | |
f4c956ad | 1762 | |
58c68779 | 1763 | /* backlight registers and fields in struct intel_panel */ |
07f11d49 | 1764 | struct mutex backlight_lock; |
31ad8ec6 | 1765 | |
f4c956ad | 1766 | /* LVDS info */ |
f4c956ad DV |
1767 | bool no_aux_handshake; |
1768 | ||
e39b999a VS |
1769 | /* protects panel power sequencer state */ |
1770 | struct mutex pps_mutex; | |
1771 | ||
f4c956ad | 1772 | struct drm_i915_fence_reg fence_regs[I915_MAX_NUM_FENCES]; /* assume 965 */ |
f4c956ad DV |
1773 | int num_fence_regs; /* 8 on pre-965, 16 otherwise */ |
1774 | ||
1775 | unsigned int fsb_freq, mem_freq, is_ddr3; | |
5d96d8af | 1776 | unsigned int skl_boot_cdclk; |
44913155 | 1777 | unsigned int cdclk_freq, max_cdclk_freq; |
adafdc6f | 1778 | unsigned int max_dotclk_freq; |
6bcda4f0 | 1779 | unsigned int hpll_freq; |
bfa7df01 | 1780 | unsigned int czclk_freq; |
f4c956ad | 1781 | |
645416f5 DV |
1782 | /** |
1783 | * wq - Driver workqueue for GEM. | |
1784 | * | |
1785 | * NOTE: Work items scheduled here are not allowed to grab any modeset | |
1786 | * locks, for otherwise the flushing done in the pageflip code will | |
1787 | * result in deadlocks. | |
1788 | */ | |
f4c956ad DV |
1789 | struct workqueue_struct *wq; |
1790 | ||
1791 | /* Display functions */ | |
1792 | struct drm_i915_display_funcs display; | |
1793 | ||
1794 | /* PCH chipset type */ | |
1795 | enum intel_pch pch_type; | |
17a303ec | 1796 | unsigned short pch_id; |
f4c956ad DV |
1797 | |
1798 | unsigned long quirks; | |
1799 | ||
b8efb17b ZR |
1800 | enum modeset_restore modeset_restore; |
1801 | struct mutex modeset_restore_lock; | |
673a394b | 1802 | |
a7bbbd63 | 1803 | struct list_head vm_list; /* Global list of all address spaces */ |
0260c420 | 1804 | struct i915_gtt gtt; /* VM representing the global address space */ |
5d4545ae | 1805 | |
4b5aed62 | 1806 | struct i915_gem_mm mm; |
ad46cb53 CW |
1807 | DECLARE_HASHTABLE(mm_structs, 7); |
1808 | struct mutex mm_lock; | |
8781342d | 1809 | |
8781342d DV |
1810 | /* Kernel Modesetting */ |
1811 | ||
9b9d172d | 1812 | struct sdvo_device_mapping sdvo_mappings[2]; |
652c393a | 1813 | |
76c4ac04 DL |
1814 | struct drm_crtc *plane_to_crtc_mapping[I915_MAX_PIPES]; |
1815 | struct drm_crtc *pipe_to_crtc_mapping[I915_MAX_PIPES]; | |
6b95a207 KH |
1816 | wait_queue_head_t pending_flip_queue; |
1817 | ||
c4597872 DV |
1818 | #ifdef CONFIG_DEBUG_FS |
1819 | struct intel_pipe_crc pipe_crc[I915_MAX_PIPES]; | |
1820 | #endif | |
1821 | ||
e72f9fbf DV |
1822 | int num_shared_dpll; |
1823 | struct intel_shared_dpll shared_dplls[I915_NUM_PLLS]; | |
e4607fcf | 1824 | int dpio_phy_iosf_port[I915_NUM_PHYS_VLV]; |
ee7b9f93 | 1825 | |
7225342a | 1826 | struct i915_workarounds workarounds; |
888b5995 | 1827 | |
652c393a JB |
1828 | /* Reclocking support */ |
1829 | bool render_reclock_avail; | |
f99d7069 DV |
1830 | |
1831 | struct i915_frontbuffer_tracking fb_tracking; | |
1832 | ||
652c393a | 1833 | u16 orig_clock; |
f97108d1 | 1834 | |
c4804411 | 1835 | bool mchbar_need_disable; |
f97108d1 | 1836 | |
a4da4fa4 DV |
1837 | struct intel_l3_parity l3_parity; |
1838 | ||
59124506 BW |
1839 | /* Cannot be determined by PCIID. You must always read a register. */ |
1840 | size_t ellc_size; | |
1841 | ||
c6a828d3 | 1842 | /* gen6+ rps state */ |
c85aa885 | 1843 | struct intel_gen6_power_mgmt rps; |
c6a828d3 | 1844 | |
20e4d407 DV |
1845 | /* ilk-only ips/rps state. Everything in here is protected by the global |
1846 | * mchdev_lock in intel_pm.c */ | |
c85aa885 | 1847 | struct intel_ilk_power_mgmt ips; |
b5e50c3f | 1848 | |
83c00f55 | 1849 | struct i915_power_domains power_domains; |
a38911a3 | 1850 | |
a031d709 | 1851 | struct i915_psr psr; |
3f51e471 | 1852 | |
99584db3 | 1853 | struct i915_gpu_error gpu_error; |
ae681d96 | 1854 | |
c9cddffc JB |
1855 | struct drm_i915_gem_object *vlv_pctx; |
1856 | ||
0695726e | 1857 | #ifdef CONFIG_DRM_FBDEV_EMULATION |
8be48d92 DA |
1858 | /* list of fbdev register on this device */ |
1859 | struct intel_fbdev *fbdev; | |
82e3b8c1 | 1860 | struct work_struct fbdev_suspend_work; |
4520f53a | 1861 | #endif |
e953fd7b CW |
1862 | |
1863 | struct drm_property *broadcast_rgb_property; | |
3f43c48d | 1864 | struct drm_property *force_audio_property; |
e3689190 | 1865 | |
58fddc28 | 1866 | /* hda/i915 audio component */ |
51e1d83c | 1867 | struct i915_audio_component *audio_component; |
58fddc28 | 1868 | bool audio_component_registered; |
4a21ef7d LY |
1869 | /** |
1870 | * av_mutex - mutex for audio/video sync | |
1871 | * | |
1872 | */ | |
1873 | struct mutex av_mutex; | |
58fddc28 | 1874 | |
254f965c | 1875 | uint32_t hw_context_size; |
a33afea5 | 1876 | struct list_head context_list; |
f4c956ad | 1877 | |
3e68320e | 1878 | u32 fdi_rx_config; |
68d18ad7 | 1879 | |
70722468 VS |
1880 | u32 chv_phy_control; |
1881 | ||
842f1c8b | 1882 | u32 suspend_count; |
bc87229f | 1883 | bool suspended_to_idle; |
f4c956ad | 1884 | struct i915_suspend_saved_registers regfile; |
ddeea5b0 | 1885 | struct vlv_s0ix_state vlv_s0ix_state; |
231f42a4 | 1886 | |
53615a5e VS |
1887 | struct { |
1888 | /* | |
1889 | * Raw watermark latency values: | |
1890 | * in 0.1us units for WM0, | |
1891 | * in 0.5us units for WM1+. | |
1892 | */ | |
1893 | /* primary */ | |
1894 | uint16_t pri_latency[5]; | |
1895 | /* sprite */ | |
1896 | uint16_t spr_latency[5]; | |
1897 | /* cursor */ | |
1898 | uint16_t cur_latency[5]; | |
2af30a5c PB |
1899 | /* |
1900 | * Raw watermark memory latency values | |
1901 | * for SKL for all 8 levels | |
1902 | * in 1us units. | |
1903 | */ | |
1904 | uint16_t skl_latency[8]; | |
609cedef | 1905 | |
aa363136 MR |
1906 | /* Committed wm config */ |
1907 | struct intel_wm_config config; | |
1908 | ||
2d41c0b5 PB |
1909 | /* |
1910 | * The skl_wm_values structure is a bit too big for stack | |
1911 | * allocation, so we keep the staging struct where we store | |
1912 | * intermediate results here instead. | |
1913 | */ | |
1914 | struct skl_wm_values skl_results; | |
1915 | ||
609cedef | 1916 | /* current hardware state */ |
2d41c0b5 PB |
1917 | union { |
1918 | struct ilk_wm_values hw; | |
1919 | struct skl_wm_values skl_hw; | |
0018fda1 | 1920 | struct vlv_wm_values vlv; |
2d41c0b5 | 1921 | }; |
58590c14 VS |
1922 | |
1923 | uint8_t max_level; | |
53615a5e VS |
1924 | } wm; |
1925 | ||
8a187455 PZ |
1926 | struct i915_runtime_pm pm; |
1927 | ||
a83014d3 OM |
1928 | /* Abstract the submission mechanism (legacy ringbuffer or execlists) away */ |
1929 | struct { | |
5f19e2bf | 1930 | int (*execbuf_submit)(struct i915_execbuffer_params *params, |
f3dc74c0 | 1931 | struct drm_i915_gem_execbuffer2 *args, |
5f19e2bf | 1932 | struct list_head *vmas); |
a83014d3 OM |
1933 | int (*init_rings)(struct drm_device *dev); |
1934 | void (*cleanup_ring)(struct intel_engine_cs *ring); | |
1935 | void (*stop_ring)(struct intel_engine_cs *ring); | |
1936 | } gt; | |
1937 | ||
9e458034 SJ |
1938 | bool edp_low_vswing; |
1939 | ||
3be60de9 VS |
1940 | /* perform PHY state sanity checks? */ |
1941 | bool chv_phy_assert[2]; | |
1942 | ||
0bdf5a05 TI |
1943 | struct intel_encoder *dig_port_map[I915_MAX_PORTS]; |
1944 | ||
bdf1e7e3 DV |
1945 | /* |
1946 | * NOTE: This is the dri1/ums dungeon, don't add stuff here. Your patch | |
1947 | * will be rejected. Instead look for a better place. | |
1948 | */ | |
77fec556 | 1949 | }; |
1da177e4 | 1950 | |
2c1792a1 CW |
1951 | static inline struct drm_i915_private *to_i915(const struct drm_device *dev) |
1952 | { | |
1953 | return dev->dev_private; | |
1954 | } | |
1955 | ||
888d0d42 ID |
1956 | static inline struct drm_i915_private *dev_to_i915(struct device *dev) |
1957 | { | |
1958 | return to_i915(dev_get_drvdata(dev)); | |
1959 | } | |
1960 | ||
33a732f4 AD |
1961 | static inline struct drm_i915_private *guc_to_i915(struct intel_guc *guc) |
1962 | { | |
1963 | return container_of(guc, struct drm_i915_private, guc); | |
1964 | } | |
1965 | ||
b4519513 CW |
1966 | /* Iterate over initialised rings */ |
1967 | #define for_each_ring(ring__, dev_priv__, i__) \ | |
1968 | for ((i__) = 0; (i__) < I915_NUM_RINGS; (i__)++) \ | |
95150bdf | 1969 | for_each_if ((((ring__) = &(dev_priv__)->ring[(i__)]), intel_ring_initialized((ring__)))) |
b4519513 | 1970 | |
b1d7e4b4 WF |
1971 | enum hdmi_force_audio { |
1972 | HDMI_AUDIO_OFF_DVI = -2, /* no aux data for HDMI-DVI converter */ | |
1973 | HDMI_AUDIO_OFF, /* force turn off HDMI audio */ | |
1974 | HDMI_AUDIO_AUTO, /* trust EDID */ | |
1975 | HDMI_AUDIO_ON, /* force turn on HDMI audio */ | |
1976 | }; | |
1977 | ||
190d6cd5 | 1978 | #define I915_GTT_OFFSET_NONE ((u32)-1) |
ed2f3452 | 1979 | |
37e680a1 CW |
1980 | struct drm_i915_gem_object_ops { |
1981 | /* Interface between the GEM object and its backing storage. | |
1982 | * get_pages() is called once prior to the use of the associated set | |
1983 | * of pages before to binding them into the GTT, and put_pages() is | |
1984 | * called after we no longer need them. As we expect there to be | |
1985 | * associated cost with migrating pages between the backing storage | |
1986 | * and making them available for the GPU (e.g. clflush), we may hold | |
1987 | * onto the pages after they are no longer referenced by the GPU | |
1988 | * in case they may be used again shortly (for example migrating the | |
1989 | * pages to a different memory domain within the GTT). put_pages() | |
1990 | * will therefore most likely be called when the object itself is | |
1991 | * being released or under memory pressure (where we attempt to | |
1992 | * reap pages for the shrinker). | |
1993 | */ | |
1994 | int (*get_pages)(struct drm_i915_gem_object *); | |
1995 | void (*put_pages)(struct drm_i915_gem_object *); | |
5cc9ed4b CW |
1996 | int (*dmabuf_export)(struct drm_i915_gem_object *); |
1997 | void (*release)(struct drm_i915_gem_object *); | |
37e680a1 CW |
1998 | }; |
1999 | ||
a071fa00 DV |
2000 | /* |
2001 | * Frontbuffer tracking bits. Set in obj->frontbuffer_bits while a gem bo is | |
d1b9d039 | 2002 | * considered to be the frontbuffer for the given plane interface-wise. This |
a071fa00 DV |
2003 | * doesn't mean that the hw necessarily already scans it out, but that any |
2004 | * rendering (by the cpu or gpu) will land in the frontbuffer eventually. | |
2005 | * | |
2006 | * We have one bit per pipe and per scanout plane type. | |
2007 | */ | |
d1b9d039 SAK |
2008 | #define INTEL_MAX_SPRITE_BITS_PER_PIPE 5 |
2009 | #define INTEL_FRONTBUFFER_BITS_PER_PIPE 8 | |
a071fa00 DV |
2010 | #define INTEL_FRONTBUFFER_BITS \ |
2011 | (INTEL_FRONTBUFFER_BITS_PER_PIPE * I915_MAX_PIPES) | |
2012 | #define INTEL_FRONTBUFFER_PRIMARY(pipe) \ | |
2013 | (1 << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))) | |
2014 | #define INTEL_FRONTBUFFER_CURSOR(pipe) \ | |
d1b9d039 SAK |
2015 | (1 << (1 + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))) |
2016 | #define INTEL_FRONTBUFFER_SPRITE(pipe, plane) \ | |
2017 | (1 << (2 + plane + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))) | |
a071fa00 | 2018 | #define INTEL_FRONTBUFFER_OVERLAY(pipe) \ |
d1b9d039 | 2019 | (1 << (2 + INTEL_MAX_SPRITE_BITS_PER_PIPE + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))) |
cc36513c | 2020 | #define INTEL_FRONTBUFFER_ALL_MASK(pipe) \ |
d1b9d039 | 2021 | (0xff << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))) |
a071fa00 | 2022 | |
673a394b | 2023 | struct drm_i915_gem_object { |
c397b908 | 2024 | struct drm_gem_object base; |
673a394b | 2025 | |
37e680a1 CW |
2026 | const struct drm_i915_gem_object_ops *ops; |
2027 | ||
2f633156 BW |
2028 | /** List of VMAs backed by this object */ |
2029 | struct list_head vma_list; | |
2030 | ||
c1ad11fc CW |
2031 | /** Stolen memory for this object, instead of being backed by shmem. */ |
2032 | struct drm_mm_node *stolen; | |
35c20a60 | 2033 | struct list_head global_list; |
673a394b | 2034 | |
b4716185 | 2035 | struct list_head ring_list[I915_NUM_RINGS]; |
b25cb2f8 BW |
2036 | /** Used in execbuf to temporarily hold a ref */ |
2037 | struct list_head obj_exec_link; | |
673a394b | 2038 | |
8d9d5744 | 2039 | struct list_head batch_pool_link; |
493018dc | 2040 | |
673a394b | 2041 | /** |
65ce3027 CW |
2042 | * This is set if the object is on the active lists (has pending |
2043 | * rendering and so a non-zero seqno), and is not set if it i s on | |
2044 | * inactive (ready to be unbound) list. | |
673a394b | 2045 | */ |
b4716185 | 2046 | unsigned int active:I915_NUM_RINGS; |
673a394b EA |
2047 | |
2048 | /** | |
2049 | * This is set if the object has been written to since last bound | |
2050 | * to the GTT | |
2051 | */ | |
0206e353 | 2052 | unsigned int dirty:1; |
778c3544 DV |
2053 | |
2054 | /** | |
2055 | * Fence register bits (if any) for this object. Will be set | |
2056 | * as needed when mapped into the GTT. | |
2057 | * Protected by dev->struct_mutex. | |
778c3544 | 2058 | */ |
4b9de737 | 2059 | signed int fence_reg:I915_MAX_NUM_FENCE_BITS; |
778c3544 | 2060 | |
778c3544 DV |
2061 | /** |
2062 | * Advice: are the backing pages purgeable? | |
2063 | */ | |
0206e353 | 2064 | unsigned int madv:2; |
778c3544 | 2065 | |
778c3544 DV |
2066 | /** |
2067 | * Current tiling mode for the object. | |
2068 | */ | |
0206e353 | 2069 | unsigned int tiling_mode:2; |
5d82e3e6 CW |
2070 | /** |
2071 | * Whether the tiling parameters for the currently associated fence | |
2072 | * register have changed. Note that for the purposes of tracking | |
2073 | * tiling changes we also treat the unfenced register, the register | |
2074 | * slot that the object occupies whilst it executes a fenced | |
2075 | * command (such as BLT on gen2/3), as a "fence". | |
2076 | */ | |
2077 | unsigned int fence_dirty:1; | |
778c3544 | 2078 | |
75e9e915 DV |
2079 | /** |
2080 | * Is the object at the current location in the gtt mappable and | |
2081 | * fenceable? Used to avoid costly recalculations. | |
2082 | */ | |
0206e353 | 2083 | unsigned int map_and_fenceable:1; |
75e9e915 | 2084 | |
fb7d516a DV |
2085 | /** |
2086 | * Whether the current gtt mapping needs to be mappable (and isn't just | |
2087 | * mappable by accident). Track pin and fault separate for a more | |
2088 | * accurate mappable working set. | |
2089 | */ | |
0206e353 | 2090 | unsigned int fault_mappable:1; |
fb7d516a | 2091 | |
24f3a8cf AG |
2092 | /* |
2093 | * Is the object to be mapped as read-only to the GPU | |
2094 | * Only honoured if hardware has relevant pte bit | |
2095 | */ | |
2096 | unsigned long gt_ro:1; | |
651d794f | 2097 | unsigned int cache_level:3; |
0f71979a | 2098 | unsigned int cache_dirty:1; |
93dfb40c | 2099 | |
a071fa00 DV |
2100 | unsigned int frontbuffer_bits:INTEL_FRONTBUFFER_BITS; |
2101 | ||
8a0c39b1 TU |
2102 | unsigned int pin_display; |
2103 | ||
9da3da66 | 2104 | struct sg_table *pages; |
a5570178 | 2105 | int pages_pin_count; |
ee286370 CW |
2106 | struct get_page { |
2107 | struct scatterlist *sg; | |
2108 | int last; | |
2109 | } get_page; | |
673a394b | 2110 | |
1286ff73 | 2111 | /* prime dma-buf support */ |
9a70cc2a DA |
2112 | void *dma_buf_vmapping; |
2113 | int vmapping_count; | |
2114 | ||
b4716185 CW |
2115 | /** Breadcrumb of last rendering to the buffer. |
2116 | * There can only be one writer, but we allow for multiple readers. | |
2117 | * If there is a writer that necessarily implies that all other | |
2118 | * read requests are complete - but we may only be lazily clearing | |
2119 | * the read requests. A read request is naturally the most recent | |
2120 | * request on a ring, so we may have two different write and read | |
2121 | * requests on one ring where the write request is older than the | |
2122 | * read request. This allows for the CPU to read from an active | |
2123 | * buffer by only waiting for the write to complete. | |
2124 | * */ | |
2125 | struct drm_i915_gem_request *last_read_req[I915_NUM_RINGS]; | |
97b2a6a1 | 2126 | struct drm_i915_gem_request *last_write_req; |
caea7476 | 2127 | /** Breadcrumb of last fenced GPU access to the buffer. */ |
97b2a6a1 | 2128 | struct drm_i915_gem_request *last_fenced_req; |
673a394b | 2129 | |
778c3544 | 2130 | /** Current tiling stride for the object, if it's tiled. */ |
de151cf6 | 2131 | uint32_t stride; |
673a394b | 2132 | |
80075d49 DV |
2133 | /** References from framebuffers, locks out tiling changes. */ |
2134 | unsigned long framebuffer_references; | |
2135 | ||
280b713b | 2136 | /** Record of address bit 17 of each page at last unbind. */ |
d312ec25 | 2137 | unsigned long *bit_17; |
280b713b | 2138 | |
5cc9ed4b | 2139 | union { |
6a2c4232 CW |
2140 | /** for phy allocated objects */ |
2141 | struct drm_dma_handle *phys_handle; | |
2142 | ||
5cc9ed4b CW |
2143 | struct i915_gem_userptr { |
2144 | uintptr_t ptr; | |
2145 | unsigned read_only :1; | |
2146 | unsigned workers :4; | |
2147 | #define I915_GEM_USERPTR_MAX_WORKERS 15 | |
2148 | ||
ad46cb53 CW |
2149 | struct i915_mm_struct *mm; |
2150 | struct i915_mmu_object *mmu_object; | |
5cc9ed4b CW |
2151 | struct work_struct *work; |
2152 | } userptr; | |
2153 | }; | |
2154 | }; | |
62b8b215 | 2155 | #define to_intel_bo(x) container_of(x, struct drm_i915_gem_object, base) |
23010e43 | 2156 | |
a071fa00 DV |
2157 | void i915_gem_track_fb(struct drm_i915_gem_object *old, |
2158 | struct drm_i915_gem_object *new, | |
2159 | unsigned frontbuffer_bits); | |
2160 | ||
673a394b EA |
2161 | /** |
2162 | * Request queue structure. | |
2163 | * | |
2164 | * The request queue allows us to note sequence numbers that have been emitted | |
2165 | * and may be associated with active buffers to be retired. | |
2166 | * | |
97b2a6a1 JH |
2167 | * By keeping this list, we can avoid having to do questionable sequence |
2168 | * number comparisons on buffer last_read|write_seqno. It also allows an | |
2169 | * emission time to be associated with the request for tracking how far ahead | |
2170 | * of the GPU the submission is. | |
b3a38998 NH |
2171 | * |
2172 | * The requests are reference counted, so upon creation they should have an | |
2173 | * initial reference taken using kref_init | |
673a394b EA |
2174 | */ |
2175 | struct drm_i915_gem_request { | |
abfe262a JH |
2176 | struct kref ref; |
2177 | ||
852835f3 | 2178 | /** On Which ring this request was generated */ |
efab6d8d | 2179 | struct drm_i915_private *i915; |
a4872ba6 | 2180 | struct intel_engine_cs *ring; |
852835f3 | 2181 | |
821485dc CW |
2182 | /** GEM sequence number associated with the previous request, |
2183 | * when the HWS breadcrumb is equal to this the GPU is processing | |
2184 | * this request. | |
2185 | */ | |
2186 | u32 previous_seqno; | |
2187 | ||
2188 | /** GEM sequence number associated with this request, | |
2189 | * when the HWS breadcrumb is equal or greater than this the GPU | |
2190 | * has finished processing this request. | |
2191 | */ | |
2192 | u32 seqno; | |
673a394b | 2193 | |
7d736f4f MK |
2194 | /** Position in the ringbuffer of the start of the request */ |
2195 | u32 head; | |
2196 | ||
72f95afa NH |
2197 | /** |
2198 | * Position in the ringbuffer of the start of the postfix. | |
2199 | * This is required to calculate the maximum available ringbuffer | |
2200 | * space without overwriting the postfix. | |
2201 | */ | |
2202 | u32 postfix; | |
2203 | ||
2204 | /** Position in the ringbuffer of the end of the whole request */ | |
a71d8d94 CW |
2205 | u32 tail; |
2206 | ||
b3a38998 | 2207 | /** |
a8c6ecb3 | 2208 | * Context and ring buffer related to this request |
b3a38998 NH |
2209 | * Contexts are refcounted, so when this request is associated with a |
2210 | * context, we must increment the context's refcount, to guarantee that | |
2211 | * it persists while any request is linked to it. Requests themselves | |
2212 | * are also refcounted, so the request will only be freed when the last | |
2213 | * reference to it is dismissed, and the code in | |
2214 | * i915_gem_request_free() will then decrement the refcount on the | |
2215 | * context. | |
2216 | */ | |
273497e5 | 2217 | struct intel_context *ctx; |
98e1bd4a | 2218 | struct intel_ringbuffer *ringbuf; |
0e50e96b | 2219 | |
dc4be607 JH |
2220 | /** Batch buffer related to this request if any (used for |
2221 | error state dump only) */ | |
7d736f4f MK |
2222 | struct drm_i915_gem_object *batch_obj; |
2223 | ||
673a394b EA |
2224 | /** Time at which this request was emitted, in jiffies. */ |
2225 | unsigned long emitted_jiffies; | |
2226 | ||
b962442e | 2227 | /** global list entry for this request */ |
673a394b | 2228 | struct list_head list; |
b962442e | 2229 | |
f787a5f5 | 2230 | struct drm_i915_file_private *file_priv; |
b962442e EA |
2231 | /** file_priv list entry for this request */ |
2232 | struct list_head client_list; | |
67e2937b | 2233 | |
071c92de MK |
2234 | /** process identifier submitting this request */ |
2235 | struct pid *pid; | |
2236 | ||
6d3d8274 NH |
2237 | /** |
2238 | * The ELSP only accepts two elements at a time, so we queue | |
2239 | * context/tail pairs on a given queue (ring->execlist_queue) until the | |
2240 | * hardware is available. The queue serves a double purpose: we also use | |
2241 | * it to keep track of the up to 2 contexts currently in the hardware | |
2242 | * (usually one in execution and the other queued up by the GPU): We | |
2243 | * only remove elements from the head of the queue when the hardware | |
2244 | * informs us that an element has been completed. | |
2245 | * | |
2246 | * All accesses to the queue are mediated by a spinlock | |
2247 | * (ring->execlist_lock). | |
2248 | */ | |
2249 | ||
2250 | /** Execlist link in the submission queue.*/ | |
2251 | struct list_head execlist_link; | |
2252 | ||
2253 | /** Execlists no. of times this request has been sent to the ELSP */ | |
2254 | int elsp_submitted; | |
2255 | ||
673a394b EA |
2256 | }; |
2257 | ||
6689cb2b | 2258 | int i915_gem_request_alloc(struct intel_engine_cs *ring, |
217e46b5 JH |
2259 | struct intel_context *ctx, |
2260 | struct drm_i915_gem_request **req_out); | |
29b1b415 | 2261 | void i915_gem_request_cancel(struct drm_i915_gem_request *req); |
abfe262a | 2262 | void i915_gem_request_free(struct kref *req_ref); |
fcfa423c JH |
2263 | int i915_gem_request_add_to_client(struct drm_i915_gem_request *req, |
2264 | struct drm_file *file); | |
abfe262a | 2265 | |
b793a00a JH |
2266 | static inline uint32_t |
2267 | i915_gem_request_get_seqno(struct drm_i915_gem_request *req) | |
2268 | { | |
2269 | return req ? req->seqno : 0; | |
2270 | } | |
2271 | ||
2272 | static inline struct intel_engine_cs * | |
2273 | i915_gem_request_get_ring(struct drm_i915_gem_request *req) | |
2274 | { | |
2275 | return req ? req->ring : NULL; | |
2276 | } | |
2277 | ||
b2cfe0ab | 2278 | static inline struct drm_i915_gem_request * |
abfe262a JH |
2279 | i915_gem_request_reference(struct drm_i915_gem_request *req) |
2280 | { | |
b2cfe0ab CW |
2281 | if (req) |
2282 | kref_get(&req->ref); | |
2283 | return req; | |
abfe262a JH |
2284 | } |
2285 | ||
2286 | static inline void | |
2287 | i915_gem_request_unreference(struct drm_i915_gem_request *req) | |
2288 | { | |
f245860e | 2289 | WARN_ON(!mutex_is_locked(&req->ring->dev->struct_mutex)); |
abfe262a JH |
2290 | kref_put(&req->ref, i915_gem_request_free); |
2291 | } | |
2292 | ||
41037f9f CW |
2293 | static inline void |
2294 | i915_gem_request_unreference__unlocked(struct drm_i915_gem_request *req) | |
2295 | { | |
b833bb61 ML |
2296 | struct drm_device *dev; |
2297 | ||
2298 | if (!req) | |
2299 | return; | |
41037f9f | 2300 | |
b833bb61 ML |
2301 | dev = req->ring->dev; |
2302 | if (kref_put_mutex(&req->ref, i915_gem_request_free, &dev->struct_mutex)) | |
41037f9f | 2303 | mutex_unlock(&dev->struct_mutex); |
41037f9f CW |
2304 | } |
2305 | ||
abfe262a JH |
2306 | static inline void i915_gem_request_assign(struct drm_i915_gem_request **pdst, |
2307 | struct drm_i915_gem_request *src) | |
2308 | { | |
2309 | if (src) | |
2310 | i915_gem_request_reference(src); | |
2311 | ||
2312 | if (*pdst) | |
2313 | i915_gem_request_unreference(*pdst); | |
2314 | ||
2315 | *pdst = src; | |
2316 | } | |
2317 | ||
1b5a433a JH |
2318 | /* |
2319 | * XXX: i915_gem_request_completed should be here but currently needs the | |
2320 | * definition of i915_seqno_passed() which is below. It will be moved in | |
2321 | * a later patch when the call to i915_seqno_passed() is obsoleted... | |
2322 | */ | |
2323 | ||
351e3db2 BV |
2324 | /* |
2325 | * A command that requires special handling by the command parser. | |
2326 | */ | |
2327 | struct drm_i915_cmd_descriptor { | |
2328 | /* | |
2329 | * Flags describing how the command parser processes the command. | |
2330 | * | |
2331 | * CMD_DESC_FIXED: The command has a fixed length if this is set, | |
2332 | * a length mask if not set | |
2333 | * CMD_DESC_SKIP: The command is allowed but does not follow the | |
2334 | * standard length encoding for the opcode range in | |
2335 | * which it falls | |
2336 | * CMD_DESC_REJECT: The command is never allowed | |
2337 | * CMD_DESC_REGISTER: The command should be checked against the | |
2338 | * register whitelist for the appropriate ring | |
2339 | * CMD_DESC_MASTER: The command is allowed if the submitting process | |
2340 | * is the DRM master | |
2341 | */ | |
2342 | u32 flags; | |
2343 | #define CMD_DESC_FIXED (1<<0) | |
2344 | #define CMD_DESC_SKIP (1<<1) | |
2345 | #define CMD_DESC_REJECT (1<<2) | |
2346 | #define CMD_DESC_REGISTER (1<<3) | |
2347 | #define CMD_DESC_BITMASK (1<<4) | |
2348 | #define CMD_DESC_MASTER (1<<5) | |
2349 | ||
2350 | /* | |
2351 | * The command's unique identification bits and the bitmask to get them. | |
2352 | * This isn't strictly the opcode field as defined in the spec and may | |
2353 | * also include type, subtype, and/or subop fields. | |
2354 | */ | |
2355 | struct { | |
2356 | u32 value; | |
2357 | u32 mask; | |
2358 | } cmd; | |
2359 | ||
2360 | /* | |
2361 | * The command's length. The command is either fixed length (i.e. does | |
2362 | * not include a length field) or has a length field mask. The flag | |
2363 | * CMD_DESC_FIXED indicates a fixed length. Otherwise, the command has | |
2364 | * a length mask. All command entries in a command table must include | |
2365 | * length information. | |
2366 | */ | |
2367 | union { | |
2368 | u32 fixed; | |
2369 | u32 mask; | |
2370 | } length; | |
2371 | ||
2372 | /* | |
2373 | * Describes where to find a register address in the command to check | |
2374 | * against the ring's register whitelist. Only valid if flags has the | |
2375 | * CMD_DESC_REGISTER bit set. | |
6a65c5b9 FJ |
2376 | * |
2377 | * A non-zero step value implies that the command may access multiple | |
2378 | * registers in sequence (e.g. LRI), in that case step gives the | |
2379 | * distance in dwords between individual offset fields. | |
351e3db2 BV |
2380 | */ |
2381 | struct { | |
2382 | u32 offset; | |
2383 | u32 mask; | |
6a65c5b9 | 2384 | u32 step; |
351e3db2 BV |
2385 | } reg; |
2386 | ||
2387 | #define MAX_CMD_DESC_BITMASKS 3 | |
2388 | /* | |
2389 | * Describes command checks where a particular dword is masked and | |
2390 | * compared against an expected value. If the command does not match | |
2391 | * the expected value, the parser rejects it. Only valid if flags has | |
2392 | * the CMD_DESC_BITMASK bit set. Only entries where mask is non-zero | |
2393 | * are valid. | |
d4d48035 BV |
2394 | * |
2395 | * If the check specifies a non-zero condition_mask then the parser | |
2396 | * only performs the check when the bits specified by condition_mask | |
2397 | * are non-zero. | |
351e3db2 BV |
2398 | */ |
2399 | struct { | |
2400 | u32 offset; | |
2401 | u32 mask; | |
2402 | u32 expected; | |
d4d48035 BV |
2403 | u32 condition_offset; |
2404 | u32 condition_mask; | |
351e3db2 BV |
2405 | } bits[MAX_CMD_DESC_BITMASKS]; |
2406 | }; | |
2407 | ||
2408 | /* | |
2409 | * A table of commands requiring special handling by the command parser. | |
2410 | * | |
2411 | * Each ring has an array of tables. Each table consists of an array of command | |
2412 | * descriptors, which must be sorted with command opcodes in ascending order. | |
2413 | */ | |
2414 | struct drm_i915_cmd_table { | |
2415 | const struct drm_i915_cmd_descriptor *table; | |
2416 | int count; | |
2417 | }; | |
2418 | ||
dbbe9127 | 2419 | /* Note that the (struct drm_i915_private *) cast is just to shut up gcc. */ |
7312e2dd CW |
2420 | #define __I915__(p) ({ \ |
2421 | struct drm_i915_private *__p; \ | |
2422 | if (__builtin_types_compatible_p(typeof(*p), struct drm_i915_private)) \ | |
2423 | __p = (struct drm_i915_private *)p; \ | |
2424 | else if (__builtin_types_compatible_p(typeof(*p), struct drm_device)) \ | |
2425 | __p = to_i915((struct drm_device *)p); \ | |
2426 | else \ | |
2427 | BUILD_BUG(); \ | |
2428 | __p; \ | |
2429 | }) | |
dbbe9127 | 2430 | #define INTEL_INFO(p) (&__I915__(p)->info) |
87f1f465 | 2431 | #define INTEL_DEVID(p) (INTEL_INFO(p)->device_id) |
e90a21d4 | 2432 | #define INTEL_REVID(p) (__I915__(p)->dev->pdev->revision) |
cae5852d | 2433 | |
e87a005d JN |
2434 | #define REVID_FOREVER 0xff |
2435 | /* | |
2436 | * Return true if revision is in range [since,until] inclusive. | |
2437 | * | |
2438 | * Use 0 for open-ended since, and REVID_FOREVER for open-ended until. | |
2439 | */ | |
2440 | #define IS_REVID(p, since, until) \ | |
2441 | (INTEL_REVID(p) >= (since) && INTEL_REVID(p) <= (until)) | |
2442 | ||
87f1f465 CW |
2443 | #define IS_I830(dev) (INTEL_DEVID(dev) == 0x3577) |
2444 | #define IS_845G(dev) (INTEL_DEVID(dev) == 0x2562) | |
cae5852d | 2445 | #define IS_I85X(dev) (INTEL_INFO(dev)->is_i85x) |
87f1f465 | 2446 | #define IS_I865G(dev) (INTEL_DEVID(dev) == 0x2572) |
cae5852d | 2447 | #define IS_I915G(dev) (INTEL_INFO(dev)->is_i915g) |
87f1f465 CW |
2448 | #define IS_I915GM(dev) (INTEL_DEVID(dev) == 0x2592) |
2449 | #define IS_I945G(dev) (INTEL_DEVID(dev) == 0x2772) | |
cae5852d ZN |
2450 | #define IS_I945GM(dev) (INTEL_INFO(dev)->is_i945gm) |
2451 | #define IS_BROADWATER(dev) (INTEL_INFO(dev)->is_broadwater) | |
2452 | #define IS_CRESTLINE(dev) (INTEL_INFO(dev)->is_crestline) | |
87f1f465 | 2453 | #define IS_GM45(dev) (INTEL_DEVID(dev) == 0x2A42) |
cae5852d | 2454 | #define IS_G4X(dev) (INTEL_INFO(dev)->is_g4x) |
87f1f465 CW |
2455 | #define IS_PINEVIEW_G(dev) (INTEL_DEVID(dev) == 0xa001) |
2456 | #define IS_PINEVIEW_M(dev) (INTEL_DEVID(dev) == 0xa011) | |
cae5852d ZN |
2457 | #define IS_PINEVIEW(dev) (INTEL_INFO(dev)->is_pineview) |
2458 | #define IS_G33(dev) (INTEL_INFO(dev)->is_g33) | |
87f1f465 | 2459 | #define IS_IRONLAKE_M(dev) (INTEL_DEVID(dev) == 0x0046) |
4b65177b | 2460 | #define IS_IVYBRIDGE(dev) (INTEL_INFO(dev)->is_ivybridge) |
87f1f465 CW |
2461 | #define IS_IVB_GT1(dev) (INTEL_DEVID(dev) == 0x0156 || \ |
2462 | INTEL_DEVID(dev) == 0x0152 || \ | |
2463 | INTEL_DEVID(dev) == 0x015a) | |
70a3eb7a | 2464 | #define IS_VALLEYVIEW(dev) (INTEL_INFO(dev)->is_valleyview) |
666a4537 | 2465 | #define IS_CHERRYVIEW(dev) (INTEL_INFO(dev)->is_cherryview) |
4cae9ae0 | 2466 | #define IS_HASWELL(dev) (INTEL_INFO(dev)->is_haswell) |
666a4537 | 2467 | #define IS_BROADWELL(dev) (!INTEL_INFO(dev)->is_cherryview && IS_GEN8(dev)) |
7201c0b3 | 2468 | #define IS_SKYLAKE(dev) (INTEL_INFO(dev)->is_skylake) |
7526ac19 | 2469 | #define IS_BROXTON(dev) (INTEL_INFO(dev)->is_broxton) |
ef11bdb3 | 2470 | #define IS_KABYLAKE(dev) (INTEL_INFO(dev)->is_kabylake) |
cae5852d | 2471 | #define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile) |
ed1c9e2c | 2472 | #define IS_HSW_EARLY_SDV(dev) (IS_HASWELL(dev) && \ |
87f1f465 | 2473 | (INTEL_DEVID(dev) & 0xFF00) == 0x0C00) |
5dd8c4c3 | 2474 | #define IS_BDW_ULT(dev) (IS_BROADWELL(dev) && \ |
6b96d705 | 2475 | ((INTEL_DEVID(dev) & 0xf) == 0x6 || \ |
0dc6f20b | 2476 | (INTEL_DEVID(dev) & 0xf) == 0xb || \ |
87f1f465 | 2477 | (INTEL_DEVID(dev) & 0xf) == 0xe)) |
ebb72aad VS |
2478 | /* ULX machines are also considered ULT. */ |
2479 | #define IS_BDW_ULX(dev) (IS_BROADWELL(dev) && \ | |
2480 | (INTEL_DEVID(dev) & 0xf) == 0xe) | |
a0fcbd95 RV |
2481 | #define IS_BDW_GT3(dev) (IS_BROADWELL(dev) && \ |
2482 | (INTEL_DEVID(dev) & 0x00F0) == 0x0020) | |
5dd8c4c3 | 2483 | #define IS_HSW_ULT(dev) (IS_HASWELL(dev) && \ |
87f1f465 | 2484 | (INTEL_DEVID(dev) & 0xFF00) == 0x0A00) |
9435373e | 2485 | #define IS_HSW_GT3(dev) (IS_HASWELL(dev) && \ |
87f1f465 | 2486 | (INTEL_DEVID(dev) & 0x00F0) == 0x0020) |
9bbfd20a | 2487 | /* ULX machines are also considered ULT. */ |
87f1f465 CW |
2488 | #define IS_HSW_ULX(dev) (INTEL_DEVID(dev) == 0x0A0E || \ |
2489 | INTEL_DEVID(dev) == 0x0A1E) | |
f8896f5d DW |
2490 | #define IS_SKL_ULT(dev) (INTEL_DEVID(dev) == 0x1906 || \ |
2491 | INTEL_DEVID(dev) == 0x1913 || \ | |
2492 | INTEL_DEVID(dev) == 0x1916 || \ | |
2493 | INTEL_DEVID(dev) == 0x1921 || \ | |
2494 | INTEL_DEVID(dev) == 0x1926) | |
2495 | #define IS_SKL_ULX(dev) (INTEL_DEVID(dev) == 0x190E || \ | |
2496 | INTEL_DEVID(dev) == 0x1915 || \ | |
2497 | INTEL_DEVID(dev) == 0x191E) | |
a5b7991c RV |
2498 | #define IS_KBL_ULT(dev) (INTEL_DEVID(dev) == 0x5906 || \ |
2499 | INTEL_DEVID(dev) == 0x5913 || \ | |
2500 | INTEL_DEVID(dev) == 0x5916 || \ | |
2501 | INTEL_DEVID(dev) == 0x5921 || \ | |
2502 | INTEL_DEVID(dev) == 0x5926) | |
2503 | #define IS_KBL_ULX(dev) (INTEL_DEVID(dev) == 0x590E || \ | |
2504 | INTEL_DEVID(dev) == 0x5915 || \ | |
2505 | INTEL_DEVID(dev) == 0x591E) | |
7a58bad0 SAK |
2506 | #define IS_SKL_GT3(dev) (IS_SKYLAKE(dev) && \ |
2507 | (INTEL_DEVID(dev) & 0x00F0) == 0x0020) | |
2508 | #define IS_SKL_GT4(dev) (IS_SKYLAKE(dev) && \ | |
2509 | (INTEL_DEVID(dev) & 0x00F0) == 0x0030) | |
2510 | ||
b833d685 | 2511 | #define IS_PRELIMINARY_HW(intel_info) ((intel_info)->is_preliminary) |
cae5852d | 2512 | |
ef712bb4 JN |
2513 | #define SKL_REVID_A0 0x0 |
2514 | #define SKL_REVID_B0 0x1 | |
2515 | #define SKL_REVID_C0 0x2 | |
2516 | #define SKL_REVID_D0 0x3 | |
2517 | #define SKL_REVID_E0 0x4 | |
2518 | #define SKL_REVID_F0 0x5 | |
2519 | ||
e87a005d JN |
2520 | #define IS_SKL_REVID(p, since, until) (IS_SKYLAKE(p) && IS_REVID(p, since, until)) |
2521 | ||
ef712bb4 | 2522 | #define BXT_REVID_A0 0x0 |
fffda3f4 | 2523 | #define BXT_REVID_A1 0x1 |
ef712bb4 JN |
2524 | #define BXT_REVID_B0 0x3 |
2525 | #define BXT_REVID_C0 0x9 | |
6c74c87f | 2526 | |
e87a005d JN |
2527 | #define IS_BXT_REVID(p, since, until) (IS_BROXTON(p) && IS_REVID(p, since, until)) |
2528 | ||
85436696 JB |
2529 | /* |
2530 | * The genX designation typically refers to the render engine, so render | |
2531 | * capability related checks should use IS_GEN, while display and other checks | |
2532 | * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular | |
2533 | * chips, etc.). | |
2534 | */ | |
cae5852d ZN |
2535 | #define IS_GEN2(dev) (INTEL_INFO(dev)->gen == 2) |
2536 | #define IS_GEN3(dev) (INTEL_INFO(dev)->gen == 3) | |
2537 | #define IS_GEN4(dev) (INTEL_INFO(dev)->gen == 4) | |
2538 | #define IS_GEN5(dev) (INTEL_INFO(dev)->gen == 5) | |
2539 | #define IS_GEN6(dev) (INTEL_INFO(dev)->gen == 6) | |
85436696 | 2540 | #define IS_GEN7(dev) (INTEL_INFO(dev)->gen == 7) |
d2980845 | 2541 | #define IS_GEN8(dev) (INTEL_INFO(dev)->gen == 8) |
b71252dc | 2542 | #define IS_GEN9(dev) (INTEL_INFO(dev)->gen == 9) |
cae5852d | 2543 | |
73ae478c BW |
2544 | #define RENDER_RING (1<<RCS) |
2545 | #define BSD_RING (1<<VCS) | |
2546 | #define BLT_RING (1<<BCS) | |
2547 | #define VEBOX_RING (1<<VECS) | |
845f74a7 | 2548 | #define BSD2_RING (1<<VCS2) |
63c42e56 | 2549 | #define HAS_BSD(dev) (INTEL_INFO(dev)->ring_mask & BSD_RING) |
845f74a7 | 2550 | #define HAS_BSD2(dev) (INTEL_INFO(dev)->ring_mask & BSD2_RING) |
63c42e56 BW |
2551 | #define HAS_BLT(dev) (INTEL_INFO(dev)->ring_mask & BLT_RING) |
2552 | #define HAS_VEBOX(dev) (INTEL_INFO(dev)->ring_mask & VEBOX_RING) | |
2553 | #define HAS_LLC(dev) (INTEL_INFO(dev)->has_llc) | |
2554 | #define HAS_WT(dev) ((IS_HASWELL(dev) || IS_BROADWELL(dev)) && \ | |
f2fbc690 | 2555 | __I915__(dev)->ellc_size) |
cae5852d ZN |
2556 | #define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws) |
2557 | ||
254f965c | 2558 | #define HAS_HW_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 6) |
d7f621e5 | 2559 | #define HAS_LOGICAL_RING_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 8) |
692ef70c | 2560 | #define USES_PPGTT(dev) (i915.enable_ppgtt) |
81ba8aef MT |
2561 | #define USES_FULL_PPGTT(dev) (i915.enable_ppgtt >= 2) |
2562 | #define USES_FULL_48BIT_PPGTT(dev) (i915.enable_ppgtt == 3) | |
1d2a314c | 2563 | |
05394f39 | 2564 | #define HAS_OVERLAY(dev) (INTEL_INFO(dev)->has_overlay) |
cae5852d ZN |
2565 | #define OVERLAY_NEEDS_PHYSICAL(dev) (INTEL_INFO(dev)->overlay_needs_physical) |
2566 | ||
b45305fc DV |
2567 | /* Early gen2 have a totally busted CS tlb and require pinned batches. */ |
2568 | #define HAS_BROKEN_CS_TLB(dev) (IS_I830(dev) || IS_845G(dev)) | |
06e668ac MK |
2569 | |
2570 | /* WaRsDisableCoarsePowerGating:skl,bxt */ | |
2571 | #define NEEDS_WaRsDisableCoarsePowerGating(dev) (IS_BXT_REVID(dev, 0, BXT_REVID_A1) || \ | |
2572 | ((IS_SKL_GT3(dev) || IS_SKL_GT4(dev)) && \ | |
2573 | IS_SKL_REVID(dev, 0, SKL_REVID_F0))) | |
4e6b788c DV |
2574 | /* |
2575 | * dp aux and gmbus irq on gen4 seems to be able to generate legacy interrupts | |
2576 | * even when in MSI mode. This results in spurious interrupt warnings if the | |
2577 | * legacy irq no. is shared with another device. The kernel then disables that | |
2578 | * interrupt source and so prevents the other device from working properly. | |
2579 | */ | |
2580 | #define HAS_AUX_IRQ(dev) (INTEL_INFO(dev)->gen >= 5) | |
2581 | #define HAS_GMBUS_IRQ(dev) (INTEL_INFO(dev)->gen >= 5) | |
b45305fc | 2582 | |
cae5852d ZN |
2583 | /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte |
2584 | * rows, which changed the alignment requirements and fence programming. | |
2585 | */ | |
2586 | #define HAS_128_BYTE_Y_TILING(dev) (!IS_GEN2(dev) && !(IS_I915G(dev) || \ | |
2587 | IS_I915GM(dev))) | |
cae5852d ZN |
2588 | #define SUPPORTS_TV(dev) (INTEL_INFO(dev)->supports_tv) |
2589 | #define I915_HAS_HOTPLUG(dev) (INTEL_INFO(dev)->has_hotplug) | |
cae5852d ZN |
2590 | |
2591 | #define HAS_FW_BLC(dev) (INTEL_INFO(dev)->gen > 2) | |
2592 | #define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr) | |
3a77c4c4 | 2593 | #define HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc) |
cae5852d | 2594 | |
dbf7786e | 2595 | #define HAS_IPS(dev) (IS_HSW_ULT(dev) || IS_BROADWELL(dev)) |
f5adf94e | 2596 | |
0c9b3715 JN |
2597 | #define HAS_DP_MST(dev) (IS_HASWELL(dev) || IS_BROADWELL(dev) || \ |
2598 | INTEL_INFO(dev)->gen >= 9) | |
2599 | ||
dd93be58 | 2600 | #define HAS_DDI(dev) (INTEL_INFO(dev)->has_ddi) |
30568c45 | 2601 | #define HAS_FPGA_DBG_UNCLAIMED(dev) (INTEL_INFO(dev)->has_fpga_dbg) |
b32c6f48 | 2602 | #define HAS_PSR(dev) (IS_HASWELL(dev) || IS_BROADWELL(dev) || \ |
e3d99845 | 2603 | IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev) || \ |
ef11bdb3 | 2604 | IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) |
6157d3c8 | 2605 | #define HAS_RUNTIME_PM(dev) (IS_GEN6(dev) || IS_HASWELL(dev) || \ |
00776511 | 2606 | IS_BROADWELL(dev) || IS_VALLEYVIEW(dev) || \ |
666a4537 WB |
2607 | IS_CHERRYVIEW(dev) || IS_SKYLAKE(dev) || \ |
2608 | IS_KABYLAKE(dev)) | |
58abf1da RV |
2609 | #define HAS_RC6(dev) (INTEL_INFO(dev)->gen >= 6) |
2610 | #define HAS_RC6p(dev) (INTEL_INFO(dev)->gen == 6 || IS_IVYBRIDGE(dev)) | |
affa9354 | 2611 | |
7b403ffb | 2612 | #define HAS_CSR(dev) (IS_GEN9(dev)) |
eb805623 | 2613 | |
2b81b844 RV |
2614 | #define HAS_GUC_UCODE(dev) (IS_GEN9(dev) && !IS_KABYLAKE(dev)) |
2615 | #define HAS_GUC_SCHED(dev) (IS_GEN9(dev) && !IS_KABYLAKE(dev)) | |
33a732f4 | 2616 | |
a9ed33ca AJ |
2617 | #define HAS_RESOURCE_STREAMER(dev) (IS_HASWELL(dev) || \ |
2618 | INTEL_INFO(dev)->gen >= 8) | |
2619 | ||
97d3308a | 2620 | #define HAS_CORE_RING_FREQ(dev) (INTEL_INFO(dev)->gen >= 6 && \ |
666a4537 WB |
2621 | !IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) && \ |
2622 | !IS_BROXTON(dev)) | |
97d3308a | 2623 | |
17a303ec PZ |
2624 | #define INTEL_PCH_DEVICE_ID_MASK 0xff00 |
2625 | #define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00 | |
2626 | #define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00 | |
2627 | #define INTEL_PCH_PPT_DEVICE_ID_TYPE 0x1e00 | |
2628 | #define INTEL_PCH_LPT_DEVICE_ID_TYPE 0x8c00 | |
2629 | #define INTEL_PCH_LPT_LP_DEVICE_ID_TYPE 0x9c00 | |
e7e7ea20 S |
2630 | #define INTEL_PCH_SPT_DEVICE_ID_TYPE 0xA100 |
2631 | #define INTEL_PCH_SPT_LP_DEVICE_ID_TYPE 0x9D00 | |
30c964a6 | 2632 | #define INTEL_PCH_P2X_DEVICE_ID_TYPE 0x7100 |
39bfcd52 | 2633 | #define INTEL_PCH_QEMU_DEVICE_ID_TYPE 0x2900 /* qemu q35 has 2918 */ |
17a303ec | 2634 | |
f2fbc690 | 2635 | #define INTEL_PCH_TYPE(dev) (__I915__(dev)->pch_type) |
e7e7ea20 | 2636 | #define HAS_PCH_SPT(dev) (INTEL_PCH_TYPE(dev) == PCH_SPT) |
eb877ebf | 2637 | #define HAS_PCH_LPT(dev) (INTEL_PCH_TYPE(dev) == PCH_LPT) |
c2699524 | 2638 | #define HAS_PCH_LPT_LP(dev) (__I915__(dev)->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) |
56f5f700 | 2639 | #define HAS_PCH_LPT_H(dev) (__I915__(dev)->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE) |
cae5852d ZN |
2640 | #define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT) |
2641 | #define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX) | |
40c7ead9 | 2642 | #define HAS_PCH_NOP(dev) (INTEL_PCH_TYPE(dev) == PCH_NOP) |
45e6e3a1 | 2643 | #define HAS_PCH_SPLIT(dev) (INTEL_PCH_TYPE(dev) != PCH_NONE) |
cae5852d | 2644 | |
666a4537 WB |
2645 | #define HAS_GMCH_DISPLAY(dev) (INTEL_INFO(dev)->gen < 5 || \ |
2646 | IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) | |
5fafe292 | 2647 | |
040d2baa BW |
2648 | /* DPF == dynamic parity feature */ |
2649 | #define HAS_L3_DPF(dev) (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) | |
2650 | #define NUM_L3_SLICES(dev) (IS_HSW_GT3(dev) ? 2 : HAS_L3_DPF(dev)) | |
e1ef7cc2 | 2651 | |
c8735b0c | 2652 | #define GT_FREQUENCY_MULTIPLIER 50 |
de43ae9d | 2653 | #define GEN9_FREQ_SCALER 3 |
c8735b0c | 2654 | |
05394f39 CW |
2655 | #include "i915_trace.h" |
2656 | ||
baa70943 | 2657 | extern const struct drm_ioctl_desc i915_ioctls[]; |
b3a83639 DA |
2658 | extern int i915_max_ioctl; |
2659 | ||
1751fcf9 ML |
2660 | extern int i915_suspend_switcheroo(struct drm_device *dev, pm_message_t state); |
2661 | extern int i915_resume_switcheroo(struct drm_device *dev); | |
7c1c2871 | 2662 | |
c838d719 | 2663 | /* i915_dma.c */ |
22eae947 | 2664 | extern int i915_driver_load(struct drm_device *, unsigned long flags); |
ba8bbcf6 | 2665 | extern int i915_driver_unload(struct drm_device *); |
2885f6ac | 2666 | extern int i915_driver_open(struct drm_device *dev, struct drm_file *file); |
84b1fd10 | 2667 | extern void i915_driver_lastclose(struct drm_device * dev); |
6c340eac | 2668 | extern void i915_driver_preclose(struct drm_device *dev, |
2885f6ac | 2669 | struct drm_file *file); |
673a394b | 2670 | extern void i915_driver_postclose(struct drm_device *dev, |
2885f6ac | 2671 | struct drm_file *file); |
c43b5634 | 2672 | #ifdef CONFIG_COMPAT |
0d6aa60b DA |
2673 | extern long i915_compat_ioctl(struct file *filp, unsigned int cmd, |
2674 | unsigned long arg); | |
c43b5634 | 2675 | #endif |
8e96d9c4 | 2676 | extern int intel_gpu_reset(struct drm_device *dev); |
49e4d842 | 2677 | extern bool intel_has_gpu_reset(struct drm_device *dev); |
d4b8bb2a | 2678 | extern int i915_reset(struct drm_device *dev); |
7648fa99 JB |
2679 | extern unsigned long i915_chipset_val(struct drm_i915_private *dev_priv); |
2680 | extern unsigned long i915_mch_val(struct drm_i915_private *dev_priv); | |
2681 | extern unsigned long i915_gfx_val(struct drm_i915_private *dev_priv); | |
2682 | extern void i915_update_gfx_val(struct drm_i915_private *dev_priv); | |
650ad970 | 2683 | int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool on); |
7648fa99 | 2684 | |
77913b39 JN |
2685 | /* intel_hotplug.c */ |
2686 | void intel_hpd_irq_handler(struct drm_device *dev, u32 pin_mask, u32 long_mask); | |
2687 | void intel_hpd_init(struct drm_i915_private *dev_priv); | |
2688 | void intel_hpd_init_work(struct drm_i915_private *dev_priv); | |
2689 | void intel_hpd_cancel_work(struct drm_i915_private *dev_priv); | |
cc24fcdc | 2690 | bool intel_hpd_pin_to_port(enum hpd_pin pin, enum port *port); |
77913b39 | 2691 | |
1da177e4 | 2692 | /* i915_irq.c */ |
10cd45b6 | 2693 | void i915_queue_hangcheck(struct drm_device *dev); |
58174462 MK |
2694 | __printf(3, 4) |
2695 | void i915_handle_error(struct drm_device *dev, bool wedged, | |
2696 | const char *fmt, ...); | |
1da177e4 | 2697 | |
b963291c | 2698 | extern void intel_irq_init(struct drm_i915_private *dev_priv); |
2aeb7d3a DV |
2699 | int intel_irq_install(struct drm_i915_private *dev_priv); |
2700 | void intel_irq_uninstall(struct drm_i915_private *dev_priv); | |
907b28c5 CW |
2701 | |
2702 | extern void intel_uncore_sanitize(struct drm_device *dev); | |
10018603 ID |
2703 | extern void intel_uncore_early_sanitize(struct drm_device *dev, |
2704 | bool restore_forcewake); | |
907b28c5 | 2705 | extern void intel_uncore_init(struct drm_device *dev); |
907b28c5 | 2706 | extern void intel_uncore_check_errors(struct drm_device *dev); |
aec347ab | 2707 | extern void intel_uncore_fini(struct drm_device *dev); |
156c7ca0 | 2708 | extern void intel_uncore_forcewake_reset(struct drm_device *dev, bool restore); |
48c1026a | 2709 | const char *intel_uncore_forcewake_domain_to_str(const enum forcewake_domain_id id); |
59bad947 | 2710 | void intel_uncore_forcewake_get(struct drm_i915_private *dev_priv, |
48c1026a | 2711 | enum forcewake_domains domains); |
59bad947 | 2712 | void intel_uncore_forcewake_put(struct drm_i915_private *dev_priv, |
48c1026a | 2713 | enum forcewake_domains domains); |
a6111f7b CW |
2714 | /* Like above but the caller must manage the uncore.lock itself. |
2715 | * Must be used with I915_READ_FW and friends. | |
2716 | */ | |
2717 | void intel_uncore_forcewake_get__locked(struct drm_i915_private *dev_priv, | |
2718 | enum forcewake_domains domains); | |
2719 | void intel_uncore_forcewake_put__locked(struct drm_i915_private *dev_priv, | |
2720 | enum forcewake_domains domains); | |
59bad947 | 2721 | void assert_forcewakes_inactive(struct drm_i915_private *dev_priv); |
cf9d2890 YZ |
2722 | static inline bool intel_vgpu_active(struct drm_device *dev) |
2723 | { | |
2724 | return to_i915(dev)->vgpu.active; | |
2725 | } | |
b1f14ad0 | 2726 | |
7c463586 | 2727 | void |
50227e1c | 2728 | i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe, |
755e9019 | 2729 | u32 status_mask); |
7c463586 KP |
2730 | |
2731 | void | |
50227e1c | 2732 | i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe, |
755e9019 | 2733 | u32 status_mask); |
7c463586 | 2734 | |
f8b79e58 ID |
2735 | void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv); |
2736 | void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv); | |
0706f17c EE |
2737 | void i915_hotplug_interrupt_update(struct drm_i915_private *dev_priv, |
2738 | uint32_t mask, | |
2739 | uint32_t bits); | |
fbdedaea VS |
2740 | void ilk_update_display_irq(struct drm_i915_private *dev_priv, |
2741 | uint32_t interrupt_mask, | |
2742 | uint32_t enabled_irq_mask); | |
2743 | static inline void | |
2744 | ilk_enable_display_irq(struct drm_i915_private *dev_priv, uint32_t bits) | |
2745 | { | |
2746 | ilk_update_display_irq(dev_priv, bits, bits); | |
2747 | } | |
2748 | static inline void | |
2749 | ilk_disable_display_irq(struct drm_i915_private *dev_priv, uint32_t bits) | |
2750 | { | |
2751 | ilk_update_display_irq(dev_priv, bits, 0); | |
2752 | } | |
013d3752 VS |
2753 | void bdw_update_pipe_irq(struct drm_i915_private *dev_priv, |
2754 | enum pipe pipe, | |
2755 | uint32_t interrupt_mask, | |
2756 | uint32_t enabled_irq_mask); | |
2757 | static inline void bdw_enable_pipe_irq(struct drm_i915_private *dev_priv, | |
2758 | enum pipe pipe, uint32_t bits) | |
2759 | { | |
2760 | bdw_update_pipe_irq(dev_priv, pipe, bits, bits); | |
2761 | } | |
2762 | static inline void bdw_disable_pipe_irq(struct drm_i915_private *dev_priv, | |
2763 | enum pipe pipe, uint32_t bits) | |
2764 | { | |
2765 | bdw_update_pipe_irq(dev_priv, pipe, bits, 0); | |
2766 | } | |
47339cd9 DV |
2767 | void ibx_display_interrupt_update(struct drm_i915_private *dev_priv, |
2768 | uint32_t interrupt_mask, | |
2769 | uint32_t enabled_irq_mask); | |
14443261 VS |
2770 | static inline void |
2771 | ibx_enable_display_interrupt(struct drm_i915_private *dev_priv, uint32_t bits) | |
2772 | { | |
2773 | ibx_display_interrupt_update(dev_priv, bits, bits); | |
2774 | } | |
2775 | static inline void | |
2776 | ibx_disable_display_interrupt(struct drm_i915_private *dev_priv, uint32_t bits) | |
2777 | { | |
2778 | ibx_display_interrupt_update(dev_priv, bits, 0); | |
2779 | } | |
2780 | ||
f8b79e58 | 2781 | |
673a394b | 2782 | /* i915_gem.c */ |
673a394b EA |
2783 | int i915_gem_create_ioctl(struct drm_device *dev, void *data, |
2784 | struct drm_file *file_priv); | |
2785 | int i915_gem_pread_ioctl(struct drm_device *dev, void *data, | |
2786 | struct drm_file *file_priv); | |
2787 | int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data, | |
2788 | struct drm_file *file_priv); | |
2789 | int i915_gem_mmap_ioctl(struct drm_device *dev, void *data, | |
2790 | struct drm_file *file_priv); | |
de151cf6 JB |
2791 | int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data, |
2792 | struct drm_file *file_priv); | |
673a394b EA |
2793 | int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data, |
2794 | struct drm_file *file_priv); | |
2795 | int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data, | |
2796 | struct drm_file *file_priv); | |
ba8b7ccb | 2797 | void i915_gem_execbuffer_move_to_active(struct list_head *vmas, |
8a8edb59 | 2798 | struct drm_i915_gem_request *req); |
adeca76d | 2799 | void i915_gem_execbuffer_retire_commands(struct i915_execbuffer_params *params); |
5f19e2bf | 2800 | int i915_gem_ringbuffer_submission(struct i915_execbuffer_params *params, |
a83014d3 | 2801 | struct drm_i915_gem_execbuffer2 *args, |
5f19e2bf | 2802 | struct list_head *vmas); |
673a394b EA |
2803 | int i915_gem_execbuffer(struct drm_device *dev, void *data, |
2804 | struct drm_file *file_priv); | |
76446cac JB |
2805 | int i915_gem_execbuffer2(struct drm_device *dev, void *data, |
2806 | struct drm_file *file_priv); | |
673a394b EA |
2807 | int i915_gem_busy_ioctl(struct drm_device *dev, void *data, |
2808 | struct drm_file *file_priv); | |
199adf40 BW |
2809 | int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data, |
2810 | struct drm_file *file); | |
2811 | int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data, | |
2812 | struct drm_file *file); | |
673a394b EA |
2813 | int i915_gem_throttle_ioctl(struct drm_device *dev, void *data, |
2814 | struct drm_file *file_priv); | |
3ef94daa CW |
2815 | int i915_gem_madvise_ioctl(struct drm_device *dev, void *data, |
2816 | struct drm_file *file_priv); | |
673a394b EA |
2817 | int i915_gem_set_tiling(struct drm_device *dev, void *data, |
2818 | struct drm_file *file_priv); | |
2819 | int i915_gem_get_tiling(struct drm_device *dev, void *data, | |
2820 | struct drm_file *file_priv); | |
5cc9ed4b CW |
2821 | int i915_gem_init_userptr(struct drm_device *dev); |
2822 | int i915_gem_userptr_ioctl(struct drm_device *dev, void *data, | |
2823 | struct drm_file *file); | |
5a125c3c EA |
2824 | int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data, |
2825 | struct drm_file *file_priv); | |
23ba4fd0 BW |
2826 | int i915_gem_wait_ioctl(struct drm_device *dev, void *data, |
2827 | struct drm_file *file_priv); | |
673a394b | 2828 | void i915_gem_load(struct drm_device *dev); |
42dcedd4 CW |
2829 | void *i915_gem_object_alloc(struct drm_device *dev); |
2830 | void i915_gem_object_free(struct drm_i915_gem_object *obj); | |
37e680a1 CW |
2831 | void i915_gem_object_init(struct drm_i915_gem_object *obj, |
2832 | const struct drm_i915_gem_object_ops *ops); | |
05394f39 CW |
2833 | struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev, |
2834 | size_t size); | |
ea70299d DG |
2835 | struct drm_i915_gem_object *i915_gem_object_create_from_data( |
2836 | struct drm_device *dev, const void *data, size_t size); | |
673a394b | 2837 | void i915_gem_free_object(struct drm_gem_object *obj); |
2f633156 | 2838 | void i915_gem_vma_destroy(struct i915_vma *vma); |
42dcedd4 | 2839 | |
0875546c DV |
2840 | /* Flags used by pin/bind&friends. */ |
2841 | #define PIN_MAPPABLE (1<<0) | |
2842 | #define PIN_NONBLOCK (1<<1) | |
2843 | #define PIN_GLOBAL (1<<2) | |
2844 | #define PIN_OFFSET_BIAS (1<<3) | |
2845 | #define PIN_USER (1<<4) | |
2846 | #define PIN_UPDATE (1<<5) | |
101b506a MT |
2847 | #define PIN_ZONE_4G (1<<6) |
2848 | #define PIN_HIGH (1<<7) | |
506a8e87 | 2849 | #define PIN_OFFSET_FIXED (1<<8) |
d23db88c | 2850 | #define PIN_OFFSET_MASK (~4095) |
ec7adb6e JL |
2851 | int __must_check |
2852 | i915_gem_object_pin(struct drm_i915_gem_object *obj, | |
2853 | struct i915_address_space *vm, | |
2854 | uint32_t alignment, | |
2855 | uint64_t flags); | |
2856 | int __must_check | |
2857 | i915_gem_object_ggtt_pin(struct drm_i915_gem_object *obj, | |
2858 | const struct i915_ggtt_view *view, | |
2859 | uint32_t alignment, | |
2860 | uint64_t flags); | |
fe14d5f4 TU |
2861 | |
2862 | int i915_vma_bind(struct i915_vma *vma, enum i915_cache_level cache_level, | |
2863 | u32 flags); | |
d0710abb | 2864 | void __i915_vma_set_map_and_fenceable(struct i915_vma *vma); |
07fe0b12 | 2865 | int __must_check i915_vma_unbind(struct i915_vma *vma); |
e9f24d5f TU |
2866 | /* |
2867 | * BEWARE: Do not use the function below unless you can _absolutely_ | |
2868 | * _guarantee_ VMA in question is _not in use_ anywhere. | |
2869 | */ | |
2870 | int __must_check __i915_vma_unbind_no_wait(struct i915_vma *vma); | |
dd624afd | 2871 | int i915_gem_object_put_pages(struct drm_i915_gem_object *obj); |
48018a57 | 2872 | void i915_gem_release_all_mmaps(struct drm_i915_private *dev_priv); |
05394f39 | 2873 | void i915_gem_release_mmap(struct drm_i915_gem_object *obj); |
f787a5f5 | 2874 | |
4c914c0c BV |
2875 | int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object *obj, |
2876 | int *needs_clflush); | |
2877 | ||
37e680a1 | 2878 | int __must_check i915_gem_object_get_pages(struct drm_i915_gem_object *obj); |
ee286370 CW |
2879 | |
2880 | static inline int __sg_page_count(struct scatterlist *sg) | |
9da3da66 | 2881 | { |
ee286370 CW |
2882 | return sg->length >> PAGE_SHIFT; |
2883 | } | |
67d5a50c | 2884 | |
033908ae DG |
2885 | struct page * |
2886 | i915_gem_object_get_dirty_page(struct drm_i915_gem_object *obj, int n); | |
2887 | ||
ee286370 CW |
2888 | static inline struct page * |
2889 | i915_gem_object_get_page(struct drm_i915_gem_object *obj, int n) | |
9da3da66 | 2890 | { |
ee286370 CW |
2891 | if (WARN_ON(n >= obj->base.size >> PAGE_SHIFT)) |
2892 | return NULL; | |
67d5a50c | 2893 | |
ee286370 CW |
2894 | if (n < obj->get_page.last) { |
2895 | obj->get_page.sg = obj->pages->sgl; | |
2896 | obj->get_page.last = 0; | |
2897 | } | |
67d5a50c | 2898 | |
ee286370 CW |
2899 | while (obj->get_page.last + __sg_page_count(obj->get_page.sg) <= n) { |
2900 | obj->get_page.last += __sg_page_count(obj->get_page.sg++); | |
2901 | if (unlikely(sg_is_chain(obj->get_page.sg))) | |
2902 | obj->get_page.sg = sg_chain_ptr(obj->get_page.sg); | |
2903 | } | |
67d5a50c | 2904 | |
ee286370 | 2905 | return nth_page(sg_page(obj->get_page.sg), n - obj->get_page.last); |
9da3da66 | 2906 | } |
ee286370 | 2907 | |
a5570178 CW |
2908 | static inline void i915_gem_object_pin_pages(struct drm_i915_gem_object *obj) |
2909 | { | |
2910 | BUG_ON(obj->pages == NULL); | |
2911 | obj->pages_pin_count++; | |
2912 | } | |
2913 | static inline void i915_gem_object_unpin_pages(struct drm_i915_gem_object *obj) | |
2914 | { | |
2915 | BUG_ON(obj->pages_pin_count == 0); | |
2916 | obj->pages_pin_count--; | |
2917 | } | |
2918 | ||
54cf91dc | 2919 | int __must_check i915_mutex_lock_interruptible(struct drm_device *dev); |
2911a35b | 2920 | int i915_gem_object_sync(struct drm_i915_gem_object *obj, |
91af127f JH |
2921 | struct intel_engine_cs *to, |
2922 | struct drm_i915_gem_request **to_req); | |
e2d05a8b | 2923 | void i915_vma_move_to_active(struct i915_vma *vma, |
b2af0376 | 2924 | struct drm_i915_gem_request *req); |
ff72145b DA |
2925 | int i915_gem_dumb_create(struct drm_file *file_priv, |
2926 | struct drm_device *dev, | |
2927 | struct drm_mode_create_dumb *args); | |
da6b51d0 DA |
2928 | int i915_gem_mmap_gtt(struct drm_file *file_priv, struct drm_device *dev, |
2929 | uint32_t handle, uint64_t *offset); | |
f787a5f5 CW |
2930 | /** |
2931 | * Returns true if seq1 is later than seq2. | |
2932 | */ | |
2933 | static inline bool | |
2934 | i915_seqno_passed(uint32_t seq1, uint32_t seq2) | |
2935 | { | |
2936 | return (int32_t)(seq1 - seq2) >= 0; | |
2937 | } | |
2938 | ||
821485dc CW |
2939 | static inline bool i915_gem_request_started(struct drm_i915_gem_request *req, |
2940 | bool lazy_coherency) | |
2941 | { | |
2942 | u32 seqno = req->ring->get_seqno(req->ring, lazy_coherency); | |
2943 | return i915_seqno_passed(seqno, req->previous_seqno); | |
2944 | } | |
2945 | ||
1b5a433a JH |
2946 | static inline bool i915_gem_request_completed(struct drm_i915_gem_request *req, |
2947 | bool lazy_coherency) | |
2948 | { | |
821485dc | 2949 | u32 seqno = req->ring->get_seqno(req->ring, lazy_coherency); |
1b5a433a JH |
2950 | return i915_seqno_passed(seqno, req->seqno); |
2951 | } | |
2952 | ||
fca26bb4 MK |
2953 | int __must_check i915_gem_get_seqno(struct drm_device *dev, u32 *seqno); |
2954 | int __must_check i915_gem_set_seqno(struct drm_device *dev, u32 seqno); | |
1690e1eb | 2955 | |
8d9fc7fd | 2956 | struct drm_i915_gem_request * |
a4872ba6 | 2957 | i915_gem_find_active_request(struct intel_engine_cs *ring); |
8d9fc7fd | 2958 | |
b29c19b6 | 2959 | bool i915_gem_retire_requests(struct drm_device *dev); |
a4872ba6 | 2960 | void i915_gem_retire_requests_ring(struct intel_engine_cs *ring); |
33196ded | 2961 | int __must_check i915_gem_check_wedge(struct i915_gpu_error *error, |
d6b2c790 | 2962 | bool interruptible); |
84c33a64 | 2963 | |
1f83fee0 DV |
2964 | static inline bool i915_reset_in_progress(struct i915_gpu_error *error) |
2965 | { | |
2966 | return unlikely(atomic_read(&error->reset_counter) | |
2ac0f450 | 2967 | & (I915_RESET_IN_PROGRESS_FLAG | I915_WEDGED)); |
1f83fee0 DV |
2968 | } |
2969 | ||
2970 | static inline bool i915_terminally_wedged(struct i915_gpu_error *error) | |
2971 | { | |
2ac0f450 MK |
2972 | return atomic_read(&error->reset_counter) & I915_WEDGED; |
2973 | } | |
2974 | ||
2975 | static inline u32 i915_reset_count(struct i915_gpu_error *error) | |
2976 | { | |
2977 | return ((atomic_read(&error->reset_counter) & ~I915_WEDGED) + 1) / 2; | |
1f83fee0 | 2978 | } |
a71d8d94 | 2979 | |
88b4aa87 MK |
2980 | static inline bool i915_stop_ring_allow_ban(struct drm_i915_private *dev_priv) |
2981 | { | |
2982 | return dev_priv->gpu_error.stop_rings == 0 || | |
2983 | dev_priv->gpu_error.stop_rings & I915_STOP_RING_ALLOW_BAN; | |
2984 | } | |
2985 | ||
2986 | static inline bool i915_stop_ring_allow_warn(struct drm_i915_private *dev_priv) | |
2987 | { | |
2988 | return dev_priv->gpu_error.stop_rings == 0 || | |
2989 | dev_priv->gpu_error.stop_rings & I915_STOP_RING_ALLOW_WARN; | |
2990 | } | |
2991 | ||
069efc1d | 2992 | void i915_gem_reset(struct drm_device *dev); |
000433b6 | 2993 | bool i915_gem_clflush_object(struct drm_i915_gem_object *obj, bool force); |
1070a42b | 2994 | int __must_check i915_gem_init(struct drm_device *dev); |
a83014d3 | 2995 | int i915_gem_init_rings(struct drm_device *dev); |
f691e2f4 | 2996 | int __must_check i915_gem_init_hw(struct drm_device *dev); |
6909a666 | 2997 | int i915_gem_l3_remap(struct drm_i915_gem_request *req, int slice); |
f691e2f4 | 2998 | void i915_gem_init_swizzling(struct drm_device *dev); |
79e53945 | 2999 | void i915_gem_cleanup_ringbuffer(struct drm_device *dev); |
b2da9fe5 | 3000 | int __must_check i915_gpu_idle(struct drm_device *dev); |
45c5f202 | 3001 | int __must_check i915_gem_suspend(struct drm_device *dev); |
75289874 | 3002 | void __i915_add_request(struct drm_i915_gem_request *req, |
5b4a60c2 JH |
3003 | struct drm_i915_gem_object *batch_obj, |
3004 | bool flush_caches); | |
75289874 | 3005 | #define i915_add_request(req) \ |
fcfa423c | 3006 | __i915_add_request(req, NULL, true) |
75289874 | 3007 | #define i915_add_request_no_flush(req) \ |
fcfa423c | 3008 | __i915_add_request(req, NULL, false) |
9c654818 | 3009 | int __i915_wait_request(struct drm_i915_gem_request *req, |
16e9a21f ACO |
3010 | unsigned reset_counter, |
3011 | bool interruptible, | |
3012 | s64 *timeout, | |
2e1b8730 | 3013 | struct intel_rps_client *rps); |
a4b3a571 | 3014 | int __must_check i915_wait_request(struct drm_i915_gem_request *req); |
de151cf6 | 3015 | int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf); |
2021746e | 3016 | int __must_check |
2e2f351d CW |
3017 | i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj, |
3018 | bool readonly); | |
3019 | int __must_check | |
2021746e CW |
3020 | i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, |
3021 | bool write); | |
3022 | int __must_check | |
dabdfe02 CW |
3023 | i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write); |
3024 | int __must_check | |
2da3b9b9 CW |
3025 | i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj, |
3026 | u32 alignment, | |
e6617330 TU |
3027 | const struct i915_ggtt_view *view); |
3028 | void i915_gem_object_unpin_from_display_plane(struct drm_i915_gem_object *obj, | |
3029 | const struct i915_ggtt_view *view); | |
00731155 | 3030 | int i915_gem_object_attach_phys(struct drm_i915_gem_object *obj, |
6eeefaf3 | 3031 | int align); |
b29c19b6 | 3032 | int i915_gem_open(struct drm_device *dev, struct drm_file *file); |
05394f39 | 3033 | void i915_gem_release(struct drm_device *dev, struct drm_file *file); |
673a394b | 3034 | |
0fa87796 ID |
3035 | uint32_t |
3036 | i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode); | |
467cffba | 3037 | uint32_t |
d865110c ID |
3038 | i915_gem_get_gtt_alignment(struct drm_device *dev, uint32_t size, |
3039 | int tiling_mode, bool fenced); | |
467cffba | 3040 | |
e4ffd173 CW |
3041 | int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj, |
3042 | enum i915_cache_level cache_level); | |
3043 | ||
1286ff73 DV |
3044 | struct drm_gem_object *i915_gem_prime_import(struct drm_device *dev, |
3045 | struct dma_buf *dma_buf); | |
3046 | ||
3047 | struct dma_buf *i915_gem_prime_export(struct drm_device *dev, | |
3048 | struct drm_gem_object *gem_obj, int flags); | |
3049 | ||
088e0df4 MT |
3050 | u64 i915_gem_obj_ggtt_offset_view(struct drm_i915_gem_object *o, |
3051 | const struct i915_ggtt_view *view); | |
3052 | u64 i915_gem_obj_offset(struct drm_i915_gem_object *o, | |
3053 | struct i915_address_space *vm); | |
3054 | static inline u64 | |
ec7adb6e | 3055 | i915_gem_obj_ggtt_offset(struct drm_i915_gem_object *o) |
fe14d5f4 | 3056 | { |
9abc4648 | 3057 | return i915_gem_obj_ggtt_offset_view(o, &i915_ggtt_view_normal); |
fe14d5f4 | 3058 | } |
ec7adb6e | 3059 | |
a70a3148 | 3060 | bool i915_gem_obj_bound_any(struct drm_i915_gem_object *o); |
ec7adb6e | 3061 | bool i915_gem_obj_ggtt_bound_view(struct drm_i915_gem_object *o, |
9abc4648 | 3062 | const struct i915_ggtt_view *view); |
a70a3148 | 3063 | bool i915_gem_obj_bound(struct drm_i915_gem_object *o, |
ec7adb6e | 3064 | struct i915_address_space *vm); |
fe14d5f4 | 3065 | |
a70a3148 BW |
3066 | unsigned long i915_gem_obj_size(struct drm_i915_gem_object *o, |
3067 | struct i915_address_space *vm); | |
fe14d5f4 | 3068 | struct i915_vma * |
ec7adb6e JL |
3069 | i915_gem_obj_to_vma(struct drm_i915_gem_object *obj, |
3070 | struct i915_address_space *vm); | |
3071 | struct i915_vma * | |
3072 | i915_gem_obj_to_ggtt_view(struct drm_i915_gem_object *obj, | |
3073 | const struct i915_ggtt_view *view); | |
fe14d5f4 | 3074 | |
accfef2e BW |
3075 | struct i915_vma * |
3076 | i915_gem_obj_lookup_or_create_vma(struct drm_i915_gem_object *obj, | |
ec7adb6e JL |
3077 | struct i915_address_space *vm); |
3078 | struct i915_vma * | |
3079 | i915_gem_obj_lookup_or_create_ggtt_vma(struct drm_i915_gem_object *obj, | |
3080 | const struct i915_ggtt_view *view); | |
5c2abbea | 3081 | |
ec7adb6e JL |
3082 | static inline struct i915_vma * |
3083 | i915_gem_obj_to_ggtt(struct drm_i915_gem_object *obj) | |
3084 | { | |
3085 | return i915_gem_obj_to_ggtt_view(obj, &i915_ggtt_view_normal); | |
d7f46fc4 | 3086 | } |
ec7adb6e | 3087 | bool i915_gem_obj_is_pinned(struct drm_i915_gem_object *obj); |
5c2abbea | 3088 | |
a70a3148 | 3089 | /* Some GGTT VM helpers */ |
5dc383b0 | 3090 | #define i915_obj_to_ggtt(obj) \ |
a70a3148 BW |
3091 | (&((struct drm_i915_private *)(obj)->base.dev->dev_private)->gtt.base) |
3092 | static inline bool i915_is_ggtt(struct i915_address_space *vm) | |
3093 | { | |
3094 | struct i915_address_space *ggtt = | |
3095 | &((struct drm_i915_private *)(vm)->dev->dev_private)->gtt.base; | |
3096 | return vm == ggtt; | |
3097 | } | |
3098 | ||
841cd773 DV |
3099 | static inline struct i915_hw_ppgtt * |
3100 | i915_vm_to_ppgtt(struct i915_address_space *vm) | |
3101 | { | |
3102 | WARN_ON(i915_is_ggtt(vm)); | |
3103 | ||
3104 | return container_of(vm, struct i915_hw_ppgtt, base); | |
3105 | } | |
3106 | ||
3107 | ||
a70a3148 BW |
3108 | static inline bool i915_gem_obj_ggtt_bound(struct drm_i915_gem_object *obj) |
3109 | { | |
9abc4648 | 3110 | return i915_gem_obj_ggtt_bound_view(obj, &i915_ggtt_view_normal); |
a70a3148 BW |
3111 | } |
3112 | ||
3113 | static inline unsigned long | |
3114 | i915_gem_obj_ggtt_size(struct drm_i915_gem_object *obj) | |
3115 | { | |
5dc383b0 | 3116 | return i915_gem_obj_size(obj, i915_obj_to_ggtt(obj)); |
a70a3148 | 3117 | } |
c37e2204 BW |
3118 | |
3119 | static inline int __must_check | |
3120 | i915_gem_obj_ggtt_pin(struct drm_i915_gem_object *obj, | |
3121 | uint32_t alignment, | |
1ec9e26d | 3122 | unsigned flags) |
c37e2204 | 3123 | { |
5dc383b0 DV |
3124 | return i915_gem_object_pin(obj, i915_obj_to_ggtt(obj), |
3125 | alignment, flags | PIN_GLOBAL); | |
c37e2204 | 3126 | } |
a70a3148 | 3127 | |
b287110e DV |
3128 | static inline int |
3129 | i915_gem_object_ggtt_unbind(struct drm_i915_gem_object *obj) | |
3130 | { | |
3131 | return i915_vma_unbind(i915_gem_obj_to_ggtt(obj)); | |
3132 | } | |
3133 | ||
e6617330 TU |
3134 | void i915_gem_object_ggtt_unpin_view(struct drm_i915_gem_object *obj, |
3135 | const struct i915_ggtt_view *view); | |
3136 | static inline void | |
3137 | i915_gem_object_ggtt_unpin(struct drm_i915_gem_object *obj) | |
3138 | { | |
3139 | i915_gem_object_ggtt_unpin_view(obj, &i915_ggtt_view_normal); | |
3140 | } | |
b287110e | 3141 | |
41a36b73 DV |
3142 | /* i915_gem_fence.c */ |
3143 | int __must_check i915_gem_object_get_fence(struct drm_i915_gem_object *obj); | |
3144 | int __must_check i915_gem_object_put_fence(struct drm_i915_gem_object *obj); | |
3145 | ||
3146 | bool i915_gem_object_pin_fence(struct drm_i915_gem_object *obj); | |
3147 | void i915_gem_object_unpin_fence(struct drm_i915_gem_object *obj); | |
3148 | ||
3149 | void i915_gem_restore_fences(struct drm_device *dev); | |
3150 | ||
7f96ecaf DV |
3151 | void i915_gem_detect_bit_6_swizzle(struct drm_device *dev); |
3152 | void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj); | |
3153 | void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj); | |
3154 | ||
254f965c | 3155 | /* i915_gem_context.c */ |
8245be31 | 3156 | int __must_check i915_gem_context_init(struct drm_device *dev); |
254f965c | 3157 | void i915_gem_context_fini(struct drm_device *dev); |
acce9ffa | 3158 | void i915_gem_context_reset(struct drm_device *dev); |
e422b888 | 3159 | int i915_gem_context_open(struct drm_device *dev, struct drm_file *file); |
b3dd6b96 | 3160 | int i915_gem_context_enable(struct drm_i915_gem_request *req); |
254f965c | 3161 | void i915_gem_context_close(struct drm_device *dev, struct drm_file *file); |
ba01cc93 | 3162 | int i915_switch_context(struct drm_i915_gem_request *req); |
273497e5 | 3163 | struct intel_context * |
41bde553 | 3164 | i915_gem_context_get(struct drm_i915_file_private *file_priv, u32 id); |
dce3271b | 3165 | void i915_gem_context_free(struct kref *ctx_ref); |
8c857917 OM |
3166 | struct drm_i915_gem_object * |
3167 | i915_gem_alloc_context_obj(struct drm_device *dev, size_t size); | |
273497e5 | 3168 | static inline void i915_gem_context_reference(struct intel_context *ctx) |
dce3271b | 3169 | { |
691e6415 | 3170 | kref_get(&ctx->ref); |
dce3271b MK |
3171 | } |
3172 | ||
273497e5 | 3173 | static inline void i915_gem_context_unreference(struct intel_context *ctx) |
dce3271b | 3174 | { |
691e6415 | 3175 | kref_put(&ctx->ref, i915_gem_context_free); |
dce3271b MK |
3176 | } |
3177 | ||
273497e5 | 3178 | static inline bool i915_gem_context_is_default(const struct intel_context *c) |
3fac8978 | 3179 | { |
821d66dd | 3180 | return c->user_handle == DEFAULT_CONTEXT_HANDLE; |
3fac8978 MK |
3181 | } |
3182 | ||
84624813 BW |
3183 | int i915_gem_context_create_ioctl(struct drm_device *dev, void *data, |
3184 | struct drm_file *file); | |
3185 | int i915_gem_context_destroy_ioctl(struct drm_device *dev, void *data, | |
3186 | struct drm_file *file); | |
c9dc0f35 CW |
3187 | int i915_gem_context_getparam_ioctl(struct drm_device *dev, void *data, |
3188 | struct drm_file *file_priv); | |
3189 | int i915_gem_context_setparam_ioctl(struct drm_device *dev, void *data, | |
3190 | struct drm_file *file_priv); | |
1286ff73 | 3191 | |
679845ed BW |
3192 | /* i915_gem_evict.c */ |
3193 | int __must_check i915_gem_evict_something(struct drm_device *dev, | |
3194 | struct i915_address_space *vm, | |
3195 | int min_size, | |
3196 | unsigned alignment, | |
3197 | unsigned cache_level, | |
d23db88c CW |
3198 | unsigned long start, |
3199 | unsigned long end, | |
1ec9e26d | 3200 | unsigned flags); |
506a8e87 | 3201 | int __must_check i915_gem_evict_for_vma(struct i915_vma *target); |
679845ed | 3202 | int i915_gem_evict_vm(struct i915_address_space *vm, bool do_idle); |
1d2a314c | 3203 | |
0260c420 | 3204 | /* belongs in i915_gem_gtt.h */ |
d09105c6 | 3205 | static inline void i915_gem_chipset_flush(struct drm_device *dev) |
e76e9aeb BW |
3206 | { |
3207 | if (INTEL_INFO(dev)->gen < 6) | |
3208 | intel_gtt_chipset_flush(); | |
3209 | } | |
246cbfb5 | 3210 | |
9797fbfb | 3211 | /* i915_gem_stolen.c */ |
d713fd49 PZ |
3212 | int i915_gem_stolen_insert_node(struct drm_i915_private *dev_priv, |
3213 | struct drm_mm_node *node, u64 size, | |
3214 | unsigned alignment); | |
a9da512b PZ |
3215 | int i915_gem_stolen_insert_node_in_range(struct drm_i915_private *dev_priv, |
3216 | struct drm_mm_node *node, u64 size, | |
3217 | unsigned alignment, u64 start, | |
3218 | u64 end); | |
d713fd49 PZ |
3219 | void i915_gem_stolen_remove_node(struct drm_i915_private *dev_priv, |
3220 | struct drm_mm_node *node); | |
9797fbfb CW |
3221 | int i915_gem_init_stolen(struct drm_device *dev); |
3222 | void i915_gem_cleanup_stolen(struct drm_device *dev); | |
0104fdbb CW |
3223 | struct drm_i915_gem_object * |
3224 | i915_gem_object_create_stolen(struct drm_device *dev, u32 size); | |
866d12b4 CW |
3225 | struct drm_i915_gem_object * |
3226 | i915_gem_object_create_stolen_for_preallocated(struct drm_device *dev, | |
3227 | u32 stolen_offset, | |
3228 | u32 gtt_offset, | |
3229 | u32 size); | |
9797fbfb | 3230 | |
be6a0376 DV |
3231 | /* i915_gem_shrinker.c */ |
3232 | unsigned long i915_gem_shrink(struct drm_i915_private *dev_priv, | |
14387540 | 3233 | unsigned long target, |
be6a0376 DV |
3234 | unsigned flags); |
3235 | #define I915_SHRINK_PURGEABLE 0x1 | |
3236 | #define I915_SHRINK_UNBOUND 0x2 | |
3237 | #define I915_SHRINK_BOUND 0x4 | |
5763ff04 | 3238 | #define I915_SHRINK_ACTIVE 0x8 |
be6a0376 DV |
3239 | unsigned long i915_gem_shrink_all(struct drm_i915_private *dev_priv); |
3240 | void i915_gem_shrinker_init(struct drm_i915_private *dev_priv); | |
3241 | ||
3242 | ||
673a394b | 3243 | /* i915_gem_tiling.c */ |
2c1792a1 | 3244 | static inline bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj) |
e9b73c67 | 3245 | { |
50227e1c | 3246 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
e9b73c67 CW |
3247 | |
3248 | return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 && | |
3249 | obj->tiling_mode != I915_TILING_NONE; | |
3250 | } | |
3251 | ||
673a394b | 3252 | /* i915_gem_debug.c */ |
23bc5982 CW |
3253 | #if WATCH_LISTS |
3254 | int i915_verify_lists(struct drm_device *dev); | |
673a394b | 3255 | #else |
23bc5982 | 3256 | #define i915_verify_lists(dev) 0 |
673a394b | 3257 | #endif |
1da177e4 | 3258 | |
2017263e | 3259 | /* i915_debugfs.c */ |
27c202ad BG |
3260 | int i915_debugfs_init(struct drm_minor *minor); |
3261 | void i915_debugfs_cleanup(struct drm_minor *minor); | |
f8c168fa | 3262 | #ifdef CONFIG_DEBUG_FS |
249e87de | 3263 | int i915_debugfs_connector_add(struct drm_connector *connector); |
07144428 DL |
3264 | void intel_display_crc_init(struct drm_device *dev); |
3265 | #else | |
101057fa DV |
3266 | static inline int i915_debugfs_connector_add(struct drm_connector *connector) |
3267 | { return 0; } | |
f8c168fa | 3268 | static inline void intel_display_crc_init(struct drm_device *dev) {} |
07144428 | 3269 | #endif |
84734a04 MK |
3270 | |
3271 | /* i915_gpu_error.c */ | |
edc3d884 MK |
3272 | __printf(2, 3) |
3273 | void i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...); | |
fc16b48b MK |
3274 | int i915_error_state_to_str(struct drm_i915_error_state_buf *estr, |
3275 | const struct i915_error_state_file_priv *error); | |
4dc955f7 | 3276 | int i915_error_state_buf_init(struct drm_i915_error_state_buf *eb, |
0a4cd7c8 | 3277 | struct drm_i915_private *i915, |
4dc955f7 MK |
3278 | size_t count, loff_t pos); |
3279 | static inline void i915_error_state_buf_release( | |
3280 | struct drm_i915_error_state_buf *eb) | |
3281 | { | |
3282 | kfree(eb->buf); | |
3283 | } | |
58174462 MK |
3284 | void i915_capture_error_state(struct drm_device *dev, bool wedge, |
3285 | const char *error_msg); | |
84734a04 MK |
3286 | void i915_error_state_get(struct drm_device *dev, |
3287 | struct i915_error_state_file_priv *error_priv); | |
3288 | void i915_error_state_put(struct i915_error_state_file_priv *error_priv); | |
3289 | void i915_destroy_error_state(struct drm_device *dev); | |
3290 | ||
3291 | void i915_get_extra_instdone(struct drm_device *dev, uint32_t *instdone); | |
0a4cd7c8 | 3292 | const char *i915_cache_level_str(struct drm_i915_private *i915, int type); |
2017263e | 3293 | |
351e3db2 | 3294 | /* i915_cmd_parser.c */ |
d728c8ef | 3295 | int i915_cmd_parser_get_version(void); |
a4872ba6 OM |
3296 | int i915_cmd_parser_init_ring(struct intel_engine_cs *ring); |
3297 | void i915_cmd_parser_fini_ring(struct intel_engine_cs *ring); | |
3298 | bool i915_needs_cmd_parser(struct intel_engine_cs *ring); | |
3299 | int i915_parse_cmds(struct intel_engine_cs *ring, | |
351e3db2 | 3300 | struct drm_i915_gem_object *batch_obj, |
78a42377 | 3301 | struct drm_i915_gem_object *shadow_batch_obj, |
351e3db2 | 3302 | u32 batch_start_offset, |
b9ffd80e | 3303 | u32 batch_len, |
351e3db2 BV |
3304 | bool is_master); |
3305 | ||
317c35d1 JB |
3306 | /* i915_suspend.c */ |
3307 | extern int i915_save_state(struct drm_device *dev); | |
3308 | extern int i915_restore_state(struct drm_device *dev); | |
0a3e67a4 | 3309 | |
0136db58 BW |
3310 | /* i915_sysfs.c */ |
3311 | void i915_setup_sysfs(struct drm_device *dev_priv); | |
3312 | void i915_teardown_sysfs(struct drm_device *dev_priv); | |
3313 | ||
f899fc64 CW |
3314 | /* intel_i2c.c */ |
3315 | extern int intel_setup_gmbus(struct drm_device *dev); | |
3316 | extern void intel_teardown_gmbus(struct drm_device *dev); | |
88ac7939 JN |
3317 | extern bool intel_gmbus_is_valid_pin(struct drm_i915_private *dev_priv, |
3318 | unsigned int pin); | |
3bd7d909 | 3319 | |
0184df46 JN |
3320 | extern struct i2c_adapter * |
3321 | intel_gmbus_get_adapter(struct drm_i915_private *dev_priv, unsigned int pin); | |
e957d772 CW |
3322 | extern void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed); |
3323 | extern void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit); | |
8f375e10 | 3324 | static inline bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter) |
b8232e90 CW |
3325 | { |
3326 | return container_of(adapter, struct intel_gmbus, adapter)->force_bit; | |
3327 | } | |
f899fc64 CW |
3328 | extern void intel_i2c_reset(struct drm_device *dev); |
3329 | ||
8b8e1a89 | 3330 | /* intel_bios.c */ |
98f3a1dc | 3331 | int intel_bios_init(struct drm_i915_private *dev_priv); |
f0067a31 | 3332 | bool intel_bios_is_valid_vbt(const void *buf, size_t size); |
8b8e1a89 | 3333 | |
3b617967 | 3334 | /* intel_opregion.c */ |
44834a67 | 3335 | #ifdef CONFIG_ACPI |
27d50c82 | 3336 | extern int intel_opregion_setup(struct drm_device *dev); |
44834a67 CW |
3337 | extern void intel_opregion_init(struct drm_device *dev); |
3338 | extern void intel_opregion_fini(struct drm_device *dev); | |
3b617967 | 3339 | extern void intel_opregion_asle_intr(struct drm_device *dev); |
9c4b0a68 JN |
3340 | extern int intel_opregion_notify_encoder(struct intel_encoder *intel_encoder, |
3341 | bool enable); | |
ecbc5cf3 JN |
3342 | extern int intel_opregion_notify_adapter(struct drm_device *dev, |
3343 | pci_power_t state); | |
65e082c9 | 3344 | #else |
27d50c82 | 3345 | static inline int intel_opregion_setup(struct drm_device *dev) { return 0; } |
44834a67 CW |
3346 | static inline void intel_opregion_init(struct drm_device *dev) { return; } |
3347 | static inline void intel_opregion_fini(struct drm_device *dev) { return; } | |
3b617967 | 3348 | static inline void intel_opregion_asle_intr(struct drm_device *dev) { return; } |
9c4b0a68 JN |
3349 | static inline int |
3350 | intel_opregion_notify_encoder(struct intel_encoder *intel_encoder, bool enable) | |
3351 | { | |
3352 | return 0; | |
3353 | } | |
ecbc5cf3 JN |
3354 | static inline int |
3355 | intel_opregion_notify_adapter(struct drm_device *dev, pci_power_t state) | |
3356 | { | |
3357 | return 0; | |
3358 | } | |
65e082c9 | 3359 | #endif |
8ee1c3db | 3360 | |
723bfd70 JB |
3361 | /* intel_acpi.c */ |
3362 | #ifdef CONFIG_ACPI | |
3363 | extern void intel_register_dsm_handler(void); | |
3364 | extern void intel_unregister_dsm_handler(void); | |
3365 | #else | |
3366 | static inline void intel_register_dsm_handler(void) { return; } | |
3367 | static inline void intel_unregister_dsm_handler(void) { return; } | |
3368 | #endif /* CONFIG_ACPI */ | |
3369 | ||
79e53945 | 3370 | /* modesetting */ |
f817586c | 3371 | extern void intel_modeset_init_hw(struct drm_device *dev); |
79e53945 | 3372 | extern void intel_modeset_init(struct drm_device *dev); |
2c7111db | 3373 | extern void intel_modeset_gem_init(struct drm_device *dev); |
79e53945 | 3374 | extern void intel_modeset_cleanup(struct drm_device *dev); |
4932e2c3 | 3375 | extern void intel_connector_unregister(struct intel_connector *); |
28d52043 | 3376 | extern int intel_modeset_vga_set_state(struct drm_device *dev, bool state); |
043e9bda | 3377 | extern void intel_display_resume(struct drm_device *dev); |
44cec740 | 3378 | extern void i915_redisable_vga(struct drm_device *dev); |
04098753 | 3379 | extern void i915_redisable_vga_power_on(struct drm_device *dev); |
7648fa99 | 3380 | extern bool ironlake_set_drps(struct drm_device *dev, u8 val); |
dde86e2d | 3381 | extern void intel_init_pch_refclk(struct drm_device *dev); |
ffe02b40 | 3382 | extern void intel_set_rps(struct drm_device *dev, u8 val); |
5209b1f4 ID |
3383 | extern void intel_set_memory_cxsr(struct drm_i915_private *dev_priv, |
3384 | bool enable); | |
0206e353 | 3385 | extern void intel_detect_pch(struct drm_device *dev); |
0136db58 | 3386 | extern int intel_enable_rc6(const struct drm_device *dev); |
3bad0781 | 3387 | |
2911a35b | 3388 | extern bool i915_semaphore_is_enabled(struct drm_device *dev); |
c0c7babc BW |
3389 | int i915_reg_read_ioctl(struct drm_device *dev, void *data, |
3390 | struct drm_file *file); | |
b6359918 MK |
3391 | int i915_get_reset_stats_ioctl(struct drm_device *dev, void *data, |
3392 | struct drm_file *file); | |
575155a9 | 3393 | |
6ef3d427 CW |
3394 | /* overlay */ |
3395 | extern struct intel_overlay_error_state *intel_overlay_capture_error_state(struct drm_device *dev); | |
edc3d884 MK |
3396 | extern void intel_overlay_print_error_state(struct drm_i915_error_state_buf *e, |
3397 | struct intel_overlay_error_state *error); | |
c4a1d9e4 CW |
3398 | |
3399 | extern struct intel_display_error_state *intel_display_capture_error_state(struct drm_device *dev); | |
edc3d884 | 3400 | extern void intel_display_print_error_state(struct drm_i915_error_state_buf *e, |
c4a1d9e4 CW |
3401 | struct drm_device *dev, |
3402 | struct intel_display_error_state *error); | |
6ef3d427 | 3403 | |
151a49d0 TR |
3404 | int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *val); |
3405 | int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u32 mbox, u32 val); | |
59de0813 JN |
3406 | |
3407 | /* intel_sideband.c */ | |
707b6e3d D |
3408 | u32 vlv_punit_read(struct drm_i915_private *dev_priv, u32 addr); |
3409 | void vlv_punit_write(struct drm_i915_private *dev_priv, u32 addr, u32 val); | |
64936258 | 3410 | u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr); |
e9f882a3 JN |
3411 | u32 vlv_gpio_nc_read(struct drm_i915_private *dev_priv, u32 reg); |
3412 | void vlv_gpio_nc_write(struct drm_i915_private *dev_priv, u32 reg, u32 val); | |
3413 | u32 vlv_cck_read(struct drm_i915_private *dev_priv, u32 reg); | |
3414 | void vlv_cck_write(struct drm_i915_private *dev_priv, u32 reg, u32 val); | |
3415 | u32 vlv_ccu_read(struct drm_i915_private *dev_priv, u32 reg); | |
3416 | void vlv_ccu_write(struct drm_i915_private *dev_priv, u32 reg, u32 val); | |
f3419158 JB |
3417 | u32 vlv_bunit_read(struct drm_i915_private *dev_priv, u32 reg); |
3418 | void vlv_bunit_write(struct drm_i915_private *dev_priv, u32 reg, u32 val); | |
e9f882a3 JN |
3419 | u32 vlv_gps_core_read(struct drm_i915_private *dev_priv, u32 reg); |
3420 | void vlv_gps_core_write(struct drm_i915_private *dev_priv, u32 reg, u32 val); | |
5e69f97f CML |
3421 | u32 vlv_dpio_read(struct drm_i915_private *dev_priv, enum pipe pipe, int reg); |
3422 | void vlv_dpio_write(struct drm_i915_private *dev_priv, enum pipe pipe, int reg, u32 val); | |
59de0813 JN |
3423 | u32 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg, |
3424 | enum intel_sbi_destination destination); | |
3425 | void intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value, | |
3426 | enum intel_sbi_destination destination); | |
e9fe51c6 SK |
3427 | u32 vlv_flisdsi_read(struct drm_i915_private *dev_priv, u32 reg); |
3428 | void vlv_flisdsi_write(struct drm_i915_private *dev_priv, u32 reg, u32 val); | |
0a073b84 | 3429 | |
616bc820 VS |
3430 | int intel_gpu_freq(struct drm_i915_private *dev_priv, int val); |
3431 | int intel_freq_opcode(struct drm_i915_private *dev_priv, int val); | |
c8d9a590 | 3432 | |
0b274481 BW |
3433 | #define I915_READ8(reg) dev_priv->uncore.funcs.mmio_readb(dev_priv, (reg), true) |
3434 | #define I915_WRITE8(reg, val) dev_priv->uncore.funcs.mmio_writeb(dev_priv, (reg), (val), true) | |
3435 | ||
3436 | #define I915_READ16(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), true) | |
3437 | #define I915_WRITE16(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), true) | |
3438 | #define I915_READ16_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), false) | |
3439 | #define I915_WRITE16_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), false) | |
3440 | ||
3441 | #define I915_READ(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), true) | |
3442 | #define I915_WRITE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), true) | |
3443 | #define I915_READ_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), false) | |
3444 | #define I915_WRITE_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), false) | |
3445 | ||
698b3135 CW |
3446 | /* Be very careful with read/write 64-bit values. On 32-bit machines, they |
3447 | * will be implemented using 2 32-bit writes in an arbitrary order with | |
3448 | * an arbitrary delay between them. This can cause the hardware to | |
3449 | * act upon the intermediate value, possibly leading to corruption and | |
3450 | * machine death. You have been warned. | |
3451 | */ | |
0b274481 BW |
3452 | #define I915_WRITE64(reg, val) dev_priv->uncore.funcs.mmio_writeq(dev_priv, (reg), (val), true) |
3453 | #define I915_READ64(reg) dev_priv->uncore.funcs.mmio_readq(dev_priv, (reg), true) | |
cae5852d | 3454 | |
50877445 | 3455 | #define I915_READ64_2x32(lower_reg, upper_reg) ({ \ |
acd29f7b CW |
3456 | u32 upper, lower, old_upper, loop = 0; \ |
3457 | upper = I915_READ(upper_reg); \ | |
ee0a227b | 3458 | do { \ |
acd29f7b | 3459 | old_upper = upper; \ |
ee0a227b | 3460 | lower = I915_READ(lower_reg); \ |
acd29f7b CW |
3461 | upper = I915_READ(upper_reg); \ |
3462 | } while (upper != old_upper && loop++ < 2); \ | |
ee0a227b | 3463 | (u64)upper << 32 | lower; }) |
50877445 | 3464 | |
cae5852d ZN |
3465 | #define POSTING_READ(reg) (void)I915_READ_NOTRACE(reg) |
3466 | #define POSTING_READ16(reg) (void)I915_READ16_NOTRACE(reg) | |
3467 | ||
75aa3f63 VS |
3468 | #define __raw_read(x, s) \ |
3469 | static inline uint##x##_t __raw_i915_read##x(struct drm_i915_private *dev_priv, \ | |
f0f59a00 | 3470 | i915_reg_t reg) \ |
75aa3f63 | 3471 | { \ |
f0f59a00 | 3472 | return read##s(dev_priv->regs + i915_mmio_reg_offset(reg)); \ |
75aa3f63 VS |
3473 | } |
3474 | ||
3475 | #define __raw_write(x, s) \ | |
3476 | static inline void __raw_i915_write##x(struct drm_i915_private *dev_priv, \ | |
f0f59a00 | 3477 | i915_reg_t reg, uint##x##_t val) \ |
75aa3f63 | 3478 | { \ |
f0f59a00 | 3479 | write##s(val, dev_priv->regs + i915_mmio_reg_offset(reg)); \ |
75aa3f63 VS |
3480 | } |
3481 | __raw_read(8, b) | |
3482 | __raw_read(16, w) | |
3483 | __raw_read(32, l) | |
3484 | __raw_read(64, q) | |
3485 | ||
3486 | __raw_write(8, b) | |
3487 | __raw_write(16, w) | |
3488 | __raw_write(32, l) | |
3489 | __raw_write(64, q) | |
3490 | ||
3491 | #undef __raw_read | |
3492 | #undef __raw_write | |
3493 | ||
a6111f7b CW |
3494 | /* These are untraced mmio-accessors that are only valid to be used inside |
3495 | * criticial sections inside IRQ handlers where forcewake is explicitly | |
3496 | * controlled. | |
3497 | * Think twice, and think again, before using these. | |
3498 | * Note: Should only be used between intel_uncore_forcewake_irqlock() and | |
3499 | * intel_uncore_forcewake_irqunlock(). | |
3500 | */ | |
75aa3f63 VS |
3501 | #define I915_READ_FW(reg__) __raw_i915_read32(dev_priv, (reg__)) |
3502 | #define I915_WRITE_FW(reg__, val__) __raw_i915_write32(dev_priv, (reg__), (val__)) | |
a6111f7b CW |
3503 | #define POSTING_READ_FW(reg__) (void)I915_READ_FW(reg__) |
3504 | ||
55bc60db VS |
3505 | /* "Broadcast RGB" property */ |
3506 | #define INTEL_BROADCAST_RGB_AUTO 0 | |
3507 | #define INTEL_BROADCAST_RGB_FULL 1 | |
3508 | #define INTEL_BROADCAST_RGB_LIMITED 2 | |
ba4f01a3 | 3509 | |
f0f59a00 | 3510 | static inline i915_reg_t i915_vgacntrl_reg(struct drm_device *dev) |
766aa1c4 | 3511 | { |
666a4537 | 3512 | if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) |
766aa1c4 | 3513 | return VLV_VGACNTRL; |
92e23b99 SJ |
3514 | else if (INTEL_INFO(dev)->gen >= 5) |
3515 | return CPU_VGACNTRL; | |
766aa1c4 VS |
3516 | else |
3517 | return VGACNTRL; | |
3518 | } | |
3519 | ||
2bb4629a VS |
3520 | static inline void __user *to_user_ptr(u64 address) |
3521 | { | |
3522 | return (void __user *)(uintptr_t)address; | |
3523 | } | |
3524 | ||
df97729f ID |
3525 | static inline unsigned long msecs_to_jiffies_timeout(const unsigned int m) |
3526 | { | |
3527 | unsigned long j = msecs_to_jiffies(m); | |
3528 | ||
3529 | return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1); | |
3530 | } | |
3531 | ||
7bd0e226 DV |
3532 | static inline unsigned long nsecs_to_jiffies_timeout(const u64 n) |
3533 | { | |
3534 | return min_t(u64, MAX_JIFFY_OFFSET, nsecs_to_jiffies64(n) + 1); | |
3535 | } | |
3536 | ||
df97729f ID |
3537 | static inline unsigned long |
3538 | timespec_to_jiffies_timeout(const struct timespec *value) | |
3539 | { | |
3540 | unsigned long j = timespec_to_jiffies(value); | |
3541 | ||
3542 | return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1); | |
3543 | } | |
3544 | ||
dce56b3c PZ |
3545 | /* |
3546 | * If you need to wait X milliseconds between events A and B, but event B | |
3547 | * doesn't happen exactly after event A, you record the timestamp (jiffies) of | |
3548 | * when event A happened, then just before event B you call this function and | |
3549 | * pass the timestamp as the first argument, and X as the second argument. | |
3550 | */ | |
3551 | static inline void | |
3552 | wait_remaining_ms_from_jiffies(unsigned long timestamp_jiffies, int to_wait_ms) | |
3553 | { | |
ec5e0cfb | 3554 | unsigned long target_jiffies, tmp_jiffies, remaining_jiffies; |
dce56b3c PZ |
3555 | |
3556 | /* | |
3557 | * Don't re-read the value of "jiffies" every time since it may change | |
3558 | * behind our back and break the math. | |
3559 | */ | |
3560 | tmp_jiffies = jiffies; | |
3561 | target_jiffies = timestamp_jiffies + | |
3562 | msecs_to_jiffies_timeout(to_wait_ms); | |
3563 | ||
3564 | if (time_after(target_jiffies, tmp_jiffies)) { | |
ec5e0cfb ID |
3565 | remaining_jiffies = target_jiffies - tmp_jiffies; |
3566 | while (remaining_jiffies) | |
3567 | remaining_jiffies = | |
3568 | schedule_timeout_uninterruptible(remaining_jiffies); | |
dce56b3c PZ |
3569 | } |
3570 | } | |
3571 | ||
581c26e8 JH |
3572 | static inline void i915_trace_irq_get(struct intel_engine_cs *ring, |
3573 | struct drm_i915_gem_request *req) | |
3574 | { | |
3575 | if (ring->trace_irq_req == NULL && ring->irq_get(ring)) | |
3576 | i915_gem_request_assign(&ring->trace_irq_req, req); | |
3577 | } | |
3578 | ||
1da177e4 | 3579 | #endif |