Commit | Line | Data |
---|---|---|
673a394b | 1 | /* |
be6a0376 | 2 | * Copyright © 2008-2015 Intel Corporation |
673a394b EA |
3 | * |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | * | |
26 | */ | |
27 | ||
760285e7 | 28 | #include <drm/drmP.h> |
0de23977 | 29 | #include <drm/drm_vma_manager.h> |
760285e7 | 30 | #include <drm/i915_drm.h> |
673a394b | 31 | #include "i915_drv.h" |
eb82289a | 32 | #include "i915_vgpu.h" |
1c5d22f7 | 33 | #include "i915_trace.h" |
652c393a | 34 | #include "intel_drv.h" |
5949eac4 | 35 | #include <linux/shmem_fs.h> |
5a0e3ad6 | 36 | #include <linux/slab.h> |
673a394b | 37 | #include <linux/swap.h> |
79e53945 | 38 | #include <linux/pci.h> |
1286ff73 | 39 | #include <linux/dma-buf.h> |
673a394b | 40 | |
b4716185 CW |
41 | #define RQ_BUG_ON(expr) |
42 | ||
05394f39 | 43 | static void i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj); |
e62b59e4 | 44 | static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj); |
c8725f3d | 45 | static void |
b4716185 CW |
46 | i915_gem_object_retire__write(struct drm_i915_gem_object *obj); |
47 | static void | |
48 | i915_gem_object_retire__read(struct drm_i915_gem_object *obj, int ring); | |
61050808 CW |
49 | static void i915_gem_write_fence(struct drm_device *dev, int reg, |
50 | struct drm_i915_gem_object *obj); | |
51 | static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj, | |
52 | struct drm_i915_fence_reg *fence, | |
53 | bool enable); | |
54 | ||
c76ce038 CW |
55 | static bool cpu_cache_is_coherent(struct drm_device *dev, |
56 | enum i915_cache_level level) | |
57 | { | |
58 | return HAS_LLC(dev) || level != I915_CACHE_NONE; | |
59 | } | |
60 | ||
2c22569b CW |
61 | static bool cpu_write_needs_clflush(struct drm_i915_gem_object *obj) |
62 | { | |
63 | if (!cpu_cache_is_coherent(obj->base.dev, obj->cache_level)) | |
64 | return true; | |
65 | ||
66 | return obj->pin_display; | |
67 | } | |
68 | ||
61050808 CW |
69 | static inline void i915_gem_object_fence_lost(struct drm_i915_gem_object *obj) |
70 | { | |
71 | if (obj->tiling_mode) | |
72 | i915_gem_release_mmap(obj); | |
73 | ||
74 | /* As we do not have an associated fence register, we will force | |
75 | * a tiling change if we ever need to acquire one. | |
76 | */ | |
5d82e3e6 | 77 | obj->fence_dirty = false; |
61050808 CW |
78 | obj->fence_reg = I915_FENCE_REG_NONE; |
79 | } | |
80 | ||
73aa808f CW |
81 | /* some bookkeeping */ |
82 | static void i915_gem_info_add_obj(struct drm_i915_private *dev_priv, | |
83 | size_t size) | |
84 | { | |
c20e8355 | 85 | spin_lock(&dev_priv->mm.object_stat_lock); |
73aa808f CW |
86 | dev_priv->mm.object_count++; |
87 | dev_priv->mm.object_memory += size; | |
c20e8355 | 88 | spin_unlock(&dev_priv->mm.object_stat_lock); |
73aa808f CW |
89 | } |
90 | ||
91 | static void i915_gem_info_remove_obj(struct drm_i915_private *dev_priv, | |
92 | size_t size) | |
93 | { | |
c20e8355 | 94 | spin_lock(&dev_priv->mm.object_stat_lock); |
73aa808f CW |
95 | dev_priv->mm.object_count--; |
96 | dev_priv->mm.object_memory -= size; | |
c20e8355 | 97 | spin_unlock(&dev_priv->mm.object_stat_lock); |
73aa808f CW |
98 | } |
99 | ||
21dd3734 | 100 | static int |
33196ded | 101 | i915_gem_wait_for_error(struct i915_gpu_error *error) |
30dbf0c0 | 102 | { |
30dbf0c0 CW |
103 | int ret; |
104 | ||
7abb690a DV |
105 | #define EXIT_COND (!i915_reset_in_progress(error) || \ |
106 | i915_terminally_wedged(error)) | |
1f83fee0 | 107 | if (EXIT_COND) |
30dbf0c0 CW |
108 | return 0; |
109 | ||
0a6759c6 DV |
110 | /* |
111 | * Only wait 10 seconds for the gpu reset to complete to avoid hanging | |
112 | * userspace. If it takes that long something really bad is going on and | |
113 | * we should simply try to bail out and fail as gracefully as possible. | |
114 | */ | |
1f83fee0 DV |
115 | ret = wait_event_interruptible_timeout(error->reset_queue, |
116 | EXIT_COND, | |
117 | 10*HZ); | |
0a6759c6 DV |
118 | if (ret == 0) { |
119 | DRM_ERROR("Timed out waiting for the gpu reset to complete\n"); | |
120 | return -EIO; | |
121 | } else if (ret < 0) { | |
30dbf0c0 | 122 | return ret; |
0a6759c6 | 123 | } |
1f83fee0 | 124 | #undef EXIT_COND |
30dbf0c0 | 125 | |
21dd3734 | 126 | return 0; |
30dbf0c0 CW |
127 | } |
128 | ||
54cf91dc | 129 | int i915_mutex_lock_interruptible(struct drm_device *dev) |
76c1dec1 | 130 | { |
33196ded | 131 | struct drm_i915_private *dev_priv = dev->dev_private; |
76c1dec1 CW |
132 | int ret; |
133 | ||
33196ded | 134 | ret = i915_gem_wait_for_error(&dev_priv->gpu_error); |
76c1dec1 CW |
135 | if (ret) |
136 | return ret; | |
137 | ||
138 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
139 | if (ret) | |
140 | return ret; | |
141 | ||
23bc5982 | 142 | WARN_ON(i915_verify_lists(dev)); |
76c1dec1 CW |
143 | return 0; |
144 | } | |
30dbf0c0 | 145 | |
5a125c3c EA |
146 | int |
147 | i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 148 | struct drm_file *file) |
5a125c3c | 149 | { |
73aa808f | 150 | struct drm_i915_private *dev_priv = dev->dev_private; |
5a125c3c | 151 | struct drm_i915_gem_get_aperture *args = data; |
6299f992 CW |
152 | struct drm_i915_gem_object *obj; |
153 | size_t pinned; | |
5a125c3c | 154 | |
6299f992 | 155 | pinned = 0; |
73aa808f | 156 | mutex_lock(&dev->struct_mutex); |
35c20a60 | 157 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) |
d7f46fc4 | 158 | if (i915_gem_obj_is_pinned(obj)) |
f343c5f6 | 159 | pinned += i915_gem_obj_ggtt_size(obj); |
73aa808f | 160 | mutex_unlock(&dev->struct_mutex); |
5a125c3c | 161 | |
853ba5d2 | 162 | args->aper_size = dev_priv->gtt.base.total; |
0206e353 | 163 | args->aper_available_size = args->aper_size - pinned; |
6299f992 | 164 | |
5a125c3c EA |
165 | return 0; |
166 | } | |
167 | ||
6a2c4232 CW |
168 | static int |
169 | i915_gem_object_get_pages_phys(struct drm_i915_gem_object *obj) | |
00731155 | 170 | { |
6a2c4232 CW |
171 | struct address_space *mapping = file_inode(obj->base.filp)->i_mapping; |
172 | char *vaddr = obj->phys_handle->vaddr; | |
173 | struct sg_table *st; | |
174 | struct scatterlist *sg; | |
175 | int i; | |
00731155 | 176 | |
6a2c4232 CW |
177 | if (WARN_ON(i915_gem_object_needs_bit17_swizzle(obj))) |
178 | return -EINVAL; | |
179 | ||
180 | for (i = 0; i < obj->base.size / PAGE_SIZE; i++) { | |
181 | struct page *page; | |
182 | char *src; | |
183 | ||
184 | page = shmem_read_mapping_page(mapping, i); | |
185 | if (IS_ERR(page)) | |
186 | return PTR_ERR(page); | |
187 | ||
188 | src = kmap_atomic(page); | |
189 | memcpy(vaddr, src, PAGE_SIZE); | |
190 | drm_clflush_virt_range(vaddr, PAGE_SIZE); | |
191 | kunmap_atomic(src); | |
192 | ||
193 | page_cache_release(page); | |
194 | vaddr += PAGE_SIZE; | |
195 | } | |
196 | ||
197 | i915_gem_chipset_flush(obj->base.dev); | |
198 | ||
199 | st = kmalloc(sizeof(*st), GFP_KERNEL); | |
200 | if (st == NULL) | |
201 | return -ENOMEM; | |
202 | ||
203 | if (sg_alloc_table(st, 1, GFP_KERNEL)) { | |
204 | kfree(st); | |
205 | return -ENOMEM; | |
206 | } | |
207 | ||
208 | sg = st->sgl; | |
209 | sg->offset = 0; | |
210 | sg->length = obj->base.size; | |
00731155 | 211 | |
6a2c4232 CW |
212 | sg_dma_address(sg) = obj->phys_handle->busaddr; |
213 | sg_dma_len(sg) = obj->base.size; | |
214 | ||
215 | obj->pages = st; | |
216 | obj->has_dma_mapping = true; | |
217 | return 0; | |
218 | } | |
219 | ||
220 | static void | |
221 | i915_gem_object_put_pages_phys(struct drm_i915_gem_object *obj) | |
222 | { | |
223 | int ret; | |
224 | ||
225 | BUG_ON(obj->madv == __I915_MADV_PURGED); | |
00731155 | 226 | |
6a2c4232 CW |
227 | ret = i915_gem_object_set_to_cpu_domain(obj, true); |
228 | if (ret) { | |
229 | /* In the event of a disaster, abandon all caches and | |
230 | * hope for the best. | |
231 | */ | |
232 | WARN_ON(ret != -EIO); | |
233 | obj->base.read_domains = obj->base.write_domain = I915_GEM_DOMAIN_CPU; | |
234 | } | |
235 | ||
236 | if (obj->madv == I915_MADV_DONTNEED) | |
237 | obj->dirty = 0; | |
238 | ||
239 | if (obj->dirty) { | |
00731155 | 240 | struct address_space *mapping = file_inode(obj->base.filp)->i_mapping; |
6a2c4232 | 241 | char *vaddr = obj->phys_handle->vaddr; |
00731155 CW |
242 | int i; |
243 | ||
244 | for (i = 0; i < obj->base.size / PAGE_SIZE; i++) { | |
6a2c4232 CW |
245 | struct page *page; |
246 | char *dst; | |
247 | ||
248 | page = shmem_read_mapping_page(mapping, i); | |
249 | if (IS_ERR(page)) | |
250 | continue; | |
251 | ||
252 | dst = kmap_atomic(page); | |
253 | drm_clflush_virt_range(vaddr, PAGE_SIZE); | |
254 | memcpy(dst, vaddr, PAGE_SIZE); | |
255 | kunmap_atomic(dst); | |
256 | ||
257 | set_page_dirty(page); | |
258 | if (obj->madv == I915_MADV_WILLNEED) | |
00731155 | 259 | mark_page_accessed(page); |
6a2c4232 | 260 | page_cache_release(page); |
00731155 CW |
261 | vaddr += PAGE_SIZE; |
262 | } | |
6a2c4232 | 263 | obj->dirty = 0; |
00731155 CW |
264 | } |
265 | ||
6a2c4232 CW |
266 | sg_free_table(obj->pages); |
267 | kfree(obj->pages); | |
268 | ||
269 | obj->has_dma_mapping = false; | |
270 | } | |
271 | ||
272 | static void | |
273 | i915_gem_object_release_phys(struct drm_i915_gem_object *obj) | |
274 | { | |
275 | drm_pci_free(obj->base.dev, obj->phys_handle); | |
276 | } | |
277 | ||
278 | static const struct drm_i915_gem_object_ops i915_gem_phys_ops = { | |
279 | .get_pages = i915_gem_object_get_pages_phys, | |
280 | .put_pages = i915_gem_object_put_pages_phys, | |
281 | .release = i915_gem_object_release_phys, | |
282 | }; | |
283 | ||
284 | static int | |
285 | drop_pages(struct drm_i915_gem_object *obj) | |
286 | { | |
287 | struct i915_vma *vma, *next; | |
288 | int ret; | |
289 | ||
290 | drm_gem_object_reference(&obj->base); | |
291 | list_for_each_entry_safe(vma, next, &obj->vma_list, vma_link) | |
292 | if (i915_vma_unbind(vma)) | |
293 | break; | |
294 | ||
295 | ret = i915_gem_object_put_pages(obj); | |
296 | drm_gem_object_unreference(&obj->base); | |
297 | ||
298 | return ret; | |
00731155 CW |
299 | } |
300 | ||
301 | int | |
302 | i915_gem_object_attach_phys(struct drm_i915_gem_object *obj, | |
303 | int align) | |
304 | { | |
305 | drm_dma_handle_t *phys; | |
6a2c4232 | 306 | int ret; |
00731155 CW |
307 | |
308 | if (obj->phys_handle) { | |
309 | if ((unsigned long)obj->phys_handle->vaddr & (align -1)) | |
310 | return -EBUSY; | |
311 | ||
312 | return 0; | |
313 | } | |
314 | ||
315 | if (obj->madv != I915_MADV_WILLNEED) | |
316 | return -EFAULT; | |
317 | ||
318 | if (obj->base.filp == NULL) | |
319 | return -EINVAL; | |
320 | ||
6a2c4232 CW |
321 | ret = drop_pages(obj); |
322 | if (ret) | |
323 | return ret; | |
324 | ||
00731155 CW |
325 | /* create a new object */ |
326 | phys = drm_pci_alloc(obj->base.dev, obj->base.size, align); | |
327 | if (!phys) | |
328 | return -ENOMEM; | |
329 | ||
00731155 | 330 | obj->phys_handle = phys; |
6a2c4232 CW |
331 | obj->ops = &i915_gem_phys_ops; |
332 | ||
333 | return i915_gem_object_get_pages(obj); | |
00731155 CW |
334 | } |
335 | ||
336 | static int | |
337 | i915_gem_phys_pwrite(struct drm_i915_gem_object *obj, | |
338 | struct drm_i915_gem_pwrite *args, | |
339 | struct drm_file *file_priv) | |
340 | { | |
341 | struct drm_device *dev = obj->base.dev; | |
342 | void *vaddr = obj->phys_handle->vaddr + args->offset; | |
343 | char __user *user_data = to_user_ptr(args->data_ptr); | |
063e4e6b | 344 | int ret = 0; |
6a2c4232 CW |
345 | |
346 | /* We manually control the domain here and pretend that it | |
347 | * remains coherent i.e. in the GTT domain, like shmem_pwrite. | |
348 | */ | |
349 | ret = i915_gem_object_wait_rendering(obj, false); | |
350 | if (ret) | |
351 | return ret; | |
00731155 | 352 | |
063e4e6b | 353 | intel_fb_obj_invalidate(obj, NULL, ORIGIN_CPU); |
00731155 CW |
354 | if (__copy_from_user_inatomic_nocache(vaddr, user_data, args->size)) { |
355 | unsigned long unwritten; | |
356 | ||
357 | /* The physical object once assigned is fixed for the lifetime | |
358 | * of the obj, so we can safely drop the lock and continue | |
359 | * to access vaddr. | |
360 | */ | |
361 | mutex_unlock(&dev->struct_mutex); | |
362 | unwritten = copy_from_user(vaddr, user_data, args->size); | |
363 | mutex_lock(&dev->struct_mutex); | |
063e4e6b PZ |
364 | if (unwritten) { |
365 | ret = -EFAULT; | |
366 | goto out; | |
367 | } | |
00731155 CW |
368 | } |
369 | ||
6a2c4232 | 370 | drm_clflush_virt_range(vaddr, args->size); |
00731155 | 371 | i915_gem_chipset_flush(dev); |
063e4e6b PZ |
372 | |
373 | out: | |
374 | intel_fb_obj_flush(obj, false); | |
375 | return ret; | |
00731155 CW |
376 | } |
377 | ||
42dcedd4 CW |
378 | void *i915_gem_object_alloc(struct drm_device *dev) |
379 | { | |
380 | struct drm_i915_private *dev_priv = dev->dev_private; | |
efab6d8d | 381 | return kmem_cache_zalloc(dev_priv->objects, GFP_KERNEL); |
42dcedd4 CW |
382 | } |
383 | ||
384 | void i915_gem_object_free(struct drm_i915_gem_object *obj) | |
385 | { | |
386 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; | |
efab6d8d | 387 | kmem_cache_free(dev_priv->objects, obj); |
42dcedd4 CW |
388 | } |
389 | ||
ff72145b DA |
390 | static int |
391 | i915_gem_create(struct drm_file *file, | |
392 | struct drm_device *dev, | |
393 | uint64_t size, | |
394 | uint32_t *handle_p) | |
673a394b | 395 | { |
05394f39 | 396 | struct drm_i915_gem_object *obj; |
a1a2d1d3 PP |
397 | int ret; |
398 | u32 handle; | |
673a394b | 399 | |
ff72145b | 400 | size = roundup(size, PAGE_SIZE); |
8ffc0246 CW |
401 | if (size == 0) |
402 | return -EINVAL; | |
673a394b EA |
403 | |
404 | /* Allocate the new object */ | |
ff72145b | 405 | obj = i915_gem_alloc_object(dev, size); |
673a394b EA |
406 | if (obj == NULL) |
407 | return -ENOMEM; | |
408 | ||
05394f39 | 409 | ret = drm_gem_handle_create(file, &obj->base, &handle); |
202f2fef | 410 | /* drop reference from allocate - handle holds it now */ |
d861e338 DV |
411 | drm_gem_object_unreference_unlocked(&obj->base); |
412 | if (ret) | |
413 | return ret; | |
202f2fef | 414 | |
ff72145b | 415 | *handle_p = handle; |
673a394b EA |
416 | return 0; |
417 | } | |
418 | ||
ff72145b DA |
419 | int |
420 | i915_gem_dumb_create(struct drm_file *file, | |
421 | struct drm_device *dev, | |
422 | struct drm_mode_create_dumb *args) | |
423 | { | |
424 | /* have to work out size/pitch and return them */ | |
de45eaf7 | 425 | args->pitch = ALIGN(args->width * DIV_ROUND_UP(args->bpp, 8), 64); |
ff72145b DA |
426 | args->size = args->pitch * args->height; |
427 | return i915_gem_create(file, dev, | |
da6b51d0 | 428 | args->size, &args->handle); |
ff72145b DA |
429 | } |
430 | ||
ff72145b DA |
431 | /** |
432 | * Creates a new mm object and returns a handle to it. | |
433 | */ | |
434 | int | |
435 | i915_gem_create_ioctl(struct drm_device *dev, void *data, | |
436 | struct drm_file *file) | |
437 | { | |
438 | struct drm_i915_gem_create *args = data; | |
63ed2cb2 | 439 | |
ff72145b | 440 | return i915_gem_create(file, dev, |
da6b51d0 | 441 | args->size, &args->handle); |
ff72145b DA |
442 | } |
443 | ||
8461d226 DV |
444 | static inline int |
445 | __copy_to_user_swizzled(char __user *cpu_vaddr, | |
446 | const char *gpu_vaddr, int gpu_offset, | |
447 | int length) | |
448 | { | |
449 | int ret, cpu_offset = 0; | |
450 | ||
451 | while (length > 0) { | |
452 | int cacheline_end = ALIGN(gpu_offset + 1, 64); | |
453 | int this_length = min(cacheline_end - gpu_offset, length); | |
454 | int swizzled_gpu_offset = gpu_offset ^ 64; | |
455 | ||
456 | ret = __copy_to_user(cpu_vaddr + cpu_offset, | |
457 | gpu_vaddr + swizzled_gpu_offset, | |
458 | this_length); | |
459 | if (ret) | |
460 | return ret + length; | |
461 | ||
462 | cpu_offset += this_length; | |
463 | gpu_offset += this_length; | |
464 | length -= this_length; | |
465 | } | |
466 | ||
467 | return 0; | |
468 | } | |
469 | ||
8c59967c | 470 | static inline int |
4f0c7cfb BW |
471 | __copy_from_user_swizzled(char *gpu_vaddr, int gpu_offset, |
472 | const char __user *cpu_vaddr, | |
8c59967c DV |
473 | int length) |
474 | { | |
475 | int ret, cpu_offset = 0; | |
476 | ||
477 | while (length > 0) { | |
478 | int cacheline_end = ALIGN(gpu_offset + 1, 64); | |
479 | int this_length = min(cacheline_end - gpu_offset, length); | |
480 | int swizzled_gpu_offset = gpu_offset ^ 64; | |
481 | ||
482 | ret = __copy_from_user(gpu_vaddr + swizzled_gpu_offset, | |
483 | cpu_vaddr + cpu_offset, | |
484 | this_length); | |
485 | if (ret) | |
486 | return ret + length; | |
487 | ||
488 | cpu_offset += this_length; | |
489 | gpu_offset += this_length; | |
490 | length -= this_length; | |
491 | } | |
492 | ||
493 | return 0; | |
494 | } | |
495 | ||
4c914c0c BV |
496 | /* |
497 | * Pins the specified object's pages and synchronizes the object with | |
498 | * GPU accesses. Sets needs_clflush to non-zero if the caller should | |
499 | * flush the object from the CPU cache. | |
500 | */ | |
501 | int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object *obj, | |
502 | int *needs_clflush) | |
503 | { | |
504 | int ret; | |
505 | ||
506 | *needs_clflush = 0; | |
507 | ||
508 | if (!obj->base.filp) | |
509 | return -EINVAL; | |
510 | ||
511 | if (!(obj->base.read_domains & I915_GEM_DOMAIN_CPU)) { | |
512 | /* If we're not in the cpu read domain, set ourself into the gtt | |
513 | * read domain and manually flush cachelines (if required). This | |
514 | * optimizes for the case when the gpu will dirty the data | |
515 | * anyway again before the next pread happens. */ | |
516 | *needs_clflush = !cpu_cache_is_coherent(obj->base.dev, | |
517 | obj->cache_level); | |
518 | ret = i915_gem_object_wait_rendering(obj, true); | |
519 | if (ret) | |
520 | return ret; | |
521 | } | |
522 | ||
523 | ret = i915_gem_object_get_pages(obj); | |
524 | if (ret) | |
525 | return ret; | |
526 | ||
527 | i915_gem_object_pin_pages(obj); | |
528 | ||
529 | return ret; | |
530 | } | |
531 | ||
d174bd64 DV |
532 | /* Per-page copy function for the shmem pread fastpath. |
533 | * Flushes invalid cachelines before reading the target if | |
534 | * needs_clflush is set. */ | |
eb01459f | 535 | static int |
d174bd64 DV |
536 | shmem_pread_fast(struct page *page, int shmem_page_offset, int page_length, |
537 | char __user *user_data, | |
538 | bool page_do_bit17_swizzling, bool needs_clflush) | |
539 | { | |
540 | char *vaddr; | |
541 | int ret; | |
542 | ||
e7e58eb5 | 543 | if (unlikely(page_do_bit17_swizzling)) |
d174bd64 DV |
544 | return -EINVAL; |
545 | ||
546 | vaddr = kmap_atomic(page); | |
547 | if (needs_clflush) | |
548 | drm_clflush_virt_range(vaddr + shmem_page_offset, | |
549 | page_length); | |
550 | ret = __copy_to_user_inatomic(user_data, | |
551 | vaddr + shmem_page_offset, | |
552 | page_length); | |
553 | kunmap_atomic(vaddr); | |
554 | ||
f60d7f0c | 555 | return ret ? -EFAULT : 0; |
d174bd64 DV |
556 | } |
557 | ||
23c18c71 DV |
558 | static void |
559 | shmem_clflush_swizzled_range(char *addr, unsigned long length, | |
560 | bool swizzled) | |
561 | { | |
e7e58eb5 | 562 | if (unlikely(swizzled)) { |
23c18c71 DV |
563 | unsigned long start = (unsigned long) addr; |
564 | unsigned long end = (unsigned long) addr + length; | |
565 | ||
566 | /* For swizzling simply ensure that we always flush both | |
567 | * channels. Lame, but simple and it works. Swizzled | |
568 | * pwrite/pread is far from a hotpath - current userspace | |
569 | * doesn't use it at all. */ | |
570 | start = round_down(start, 128); | |
571 | end = round_up(end, 128); | |
572 | ||
573 | drm_clflush_virt_range((void *)start, end - start); | |
574 | } else { | |
575 | drm_clflush_virt_range(addr, length); | |
576 | } | |
577 | ||
578 | } | |
579 | ||
d174bd64 DV |
580 | /* Only difference to the fast-path function is that this can handle bit17 |
581 | * and uses non-atomic copy and kmap functions. */ | |
582 | static int | |
583 | shmem_pread_slow(struct page *page, int shmem_page_offset, int page_length, | |
584 | char __user *user_data, | |
585 | bool page_do_bit17_swizzling, bool needs_clflush) | |
586 | { | |
587 | char *vaddr; | |
588 | int ret; | |
589 | ||
590 | vaddr = kmap(page); | |
591 | if (needs_clflush) | |
23c18c71 DV |
592 | shmem_clflush_swizzled_range(vaddr + shmem_page_offset, |
593 | page_length, | |
594 | page_do_bit17_swizzling); | |
d174bd64 DV |
595 | |
596 | if (page_do_bit17_swizzling) | |
597 | ret = __copy_to_user_swizzled(user_data, | |
598 | vaddr, shmem_page_offset, | |
599 | page_length); | |
600 | else | |
601 | ret = __copy_to_user(user_data, | |
602 | vaddr + shmem_page_offset, | |
603 | page_length); | |
604 | kunmap(page); | |
605 | ||
f60d7f0c | 606 | return ret ? - EFAULT : 0; |
d174bd64 DV |
607 | } |
608 | ||
eb01459f | 609 | static int |
dbf7bff0 DV |
610 | i915_gem_shmem_pread(struct drm_device *dev, |
611 | struct drm_i915_gem_object *obj, | |
612 | struct drm_i915_gem_pread *args, | |
613 | struct drm_file *file) | |
eb01459f | 614 | { |
8461d226 | 615 | char __user *user_data; |
eb01459f | 616 | ssize_t remain; |
8461d226 | 617 | loff_t offset; |
eb2c0c81 | 618 | int shmem_page_offset, page_length, ret = 0; |
8461d226 | 619 | int obj_do_bit17_swizzling, page_do_bit17_swizzling; |
96d79b52 | 620 | int prefaulted = 0; |
8489731c | 621 | int needs_clflush = 0; |
67d5a50c | 622 | struct sg_page_iter sg_iter; |
eb01459f | 623 | |
2bb4629a | 624 | user_data = to_user_ptr(args->data_ptr); |
eb01459f EA |
625 | remain = args->size; |
626 | ||
8461d226 | 627 | obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj); |
eb01459f | 628 | |
4c914c0c | 629 | ret = i915_gem_obj_prepare_shmem_read(obj, &needs_clflush); |
f60d7f0c CW |
630 | if (ret) |
631 | return ret; | |
632 | ||
8461d226 | 633 | offset = args->offset; |
eb01459f | 634 | |
67d5a50c ID |
635 | for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, |
636 | offset >> PAGE_SHIFT) { | |
2db76d7c | 637 | struct page *page = sg_page_iter_page(&sg_iter); |
9da3da66 CW |
638 | |
639 | if (remain <= 0) | |
640 | break; | |
641 | ||
eb01459f EA |
642 | /* Operation in this page |
643 | * | |
eb01459f | 644 | * shmem_page_offset = offset within page in shmem file |
eb01459f EA |
645 | * page_length = bytes to copy for this page |
646 | */ | |
c8cbbb8b | 647 | shmem_page_offset = offset_in_page(offset); |
eb01459f EA |
648 | page_length = remain; |
649 | if ((shmem_page_offset + page_length) > PAGE_SIZE) | |
650 | page_length = PAGE_SIZE - shmem_page_offset; | |
eb01459f | 651 | |
8461d226 DV |
652 | page_do_bit17_swizzling = obj_do_bit17_swizzling && |
653 | (page_to_phys(page) & (1 << 17)) != 0; | |
654 | ||
d174bd64 DV |
655 | ret = shmem_pread_fast(page, shmem_page_offset, page_length, |
656 | user_data, page_do_bit17_swizzling, | |
657 | needs_clflush); | |
658 | if (ret == 0) | |
659 | goto next_page; | |
dbf7bff0 | 660 | |
dbf7bff0 DV |
661 | mutex_unlock(&dev->struct_mutex); |
662 | ||
d330a953 | 663 | if (likely(!i915.prefault_disable) && !prefaulted) { |
f56f821f | 664 | ret = fault_in_multipages_writeable(user_data, remain); |
96d79b52 DV |
665 | /* Userspace is tricking us, but we've already clobbered |
666 | * its pages with the prefault and promised to write the | |
667 | * data up to the first fault. Hence ignore any errors | |
668 | * and just continue. */ | |
669 | (void)ret; | |
670 | prefaulted = 1; | |
671 | } | |
eb01459f | 672 | |
d174bd64 DV |
673 | ret = shmem_pread_slow(page, shmem_page_offset, page_length, |
674 | user_data, page_do_bit17_swizzling, | |
675 | needs_clflush); | |
eb01459f | 676 | |
dbf7bff0 | 677 | mutex_lock(&dev->struct_mutex); |
f60d7f0c | 678 | |
f60d7f0c | 679 | if (ret) |
8461d226 | 680 | goto out; |
8461d226 | 681 | |
17793c9a | 682 | next_page: |
eb01459f | 683 | remain -= page_length; |
8461d226 | 684 | user_data += page_length; |
eb01459f EA |
685 | offset += page_length; |
686 | } | |
687 | ||
4f27b75d | 688 | out: |
f60d7f0c CW |
689 | i915_gem_object_unpin_pages(obj); |
690 | ||
eb01459f EA |
691 | return ret; |
692 | } | |
693 | ||
673a394b EA |
694 | /** |
695 | * Reads data from the object referenced by handle. | |
696 | * | |
697 | * On error, the contents of *data are undefined. | |
698 | */ | |
699 | int | |
700 | i915_gem_pread_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 701 | struct drm_file *file) |
673a394b EA |
702 | { |
703 | struct drm_i915_gem_pread *args = data; | |
05394f39 | 704 | struct drm_i915_gem_object *obj; |
35b62a89 | 705 | int ret = 0; |
673a394b | 706 | |
51311d0a CW |
707 | if (args->size == 0) |
708 | return 0; | |
709 | ||
710 | if (!access_ok(VERIFY_WRITE, | |
2bb4629a | 711 | to_user_ptr(args->data_ptr), |
51311d0a CW |
712 | args->size)) |
713 | return -EFAULT; | |
714 | ||
4f27b75d | 715 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 716 | if (ret) |
4f27b75d | 717 | return ret; |
673a394b | 718 | |
05394f39 | 719 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 720 | if (&obj->base == NULL) { |
1d7cfea1 CW |
721 | ret = -ENOENT; |
722 | goto unlock; | |
4f27b75d | 723 | } |
673a394b | 724 | |
7dcd2499 | 725 | /* Bounds check source. */ |
05394f39 CW |
726 | if (args->offset > obj->base.size || |
727 | args->size > obj->base.size - args->offset) { | |
ce9d419d | 728 | ret = -EINVAL; |
35b62a89 | 729 | goto out; |
ce9d419d CW |
730 | } |
731 | ||
1286ff73 DV |
732 | /* prime objects have no backing filp to GEM pread/pwrite |
733 | * pages from. | |
734 | */ | |
735 | if (!obj->base.filp) { | |
736 | ret = -EINVAL; | |
737 | goto out; | |
738 | } | |
739 | ||
db53a302 CW |
740 | trace_i915_gem_object_pread(obj, args->offset, args->size); |
741 | ||
dbf7bff0 | 742 | ret = i915_gem_shmem_pread(dev, obj, args, file); |
673a394b | 743 | |
35b62a89 | 744 | out: |
05394f39 | 745 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 746 | unlock: |
4f27b75d | 747 | mutex_unlock(&dev->struct_mutex); |
eb01459f | 748 | return ret; |
673a394b EA |
749 | } |
750 | ||
0839ccb8 KP |
751 | /* This is the fast write path which cannot handle |
752 | * page faults in the source data | |
9b7530cc | 753 | */ |
0839ccb8 KP |
754 | |
755 | static inline int | |
756 | fast_user_write(struct io_mapping *mapping, | |
757 | loff_t page_base, int page_offset, | |
758 | char __user *user_data, | |
759 | int length) | |
9b7530cc | 760 | { |
4f0c7cfb BW |
761 | void __iomem *vaddr_atomic; |
762 | void *vaddr; | |
0839ccb8 | 763 | unsigned long unwritten; |
9b7530cc | 764 | |
3e4d3af5 | 765 | vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base); |
4f0c7cfb BW |
766 | /* We can use the cpu mem copy function because this is X86. */ |
767 | vaddr = (void __force*)vaddr_atomic + page_offset; | |
768 | unwritten = __copy_from_user_inatomic_nocache(vaddr, | |
0839ccb8 | 769 | user_data, length); |
3e4d3af5 | 770 | io_mapping_unmap_atomic(vaddr_atomic); |
fbd5a26d | 771 | return unwritten; |
0839ccb8 KP |
772 | } |
773 | ||
3de09aa3 EA |
774 | /** |
775 | * This is the fast pwrite path, where we copy the data directly from the | |
776 | * user into the GTT, uncached. | |
777 | */ | |
673a394b | 778 | static int |
05394f39 CW |
779 | i915_gem_gtt_pwrite_fast(struct drm_device *dev, |
780 | struct drm_i915_gem_object *obj, | |
3de09aa3 | 781 | struct drm_i915_gem_pwrite *args, |
05394f39 | 782 | struct drm_file *file) |
673a394b | 783 | { |
3e31c6c0 | 784 | struct drm_i915_private *dev_priv = dev->dev_private; |
673a394b | 785 | ssize_t remain; |
0839ccb8 | 786 | loff_t offset, page_base; |
673a394b | 787 | char __user *user_data; |
935aaa69 DV |
788 | int page_offset, page_length, ret; |
789 | ||
1ec9e26d | 790 | ret = i915_gem_obj_ggtt_pin(obj, 0, PIN_MAPPABLE | PIN_NONBLOCK); |
935aaa69 DV |
791 | if (ret) |
792 | goto out; | |
793 | ||
794 | ret = i915_gem_object_set_to_gtt_domain(obj, true); | |
795 | if (ret) | |
796 | goto out_unpin; | |
797 | ||
798 | ret = i915_gem_object_put_fence(obj); | |
799 | if (ret) | |
800 | goto out_unpin; | |
673a394b | 801 | |
2bb4629a | 802 | user_data = to_user_ptr(args->data_ptr); |
673a394b | 803 | remain = args->size; |
673a394b | 804 | |
f343c5f6 | 805 | offset = i915_gem_obj_ggtt_offset(obj) + args->offset; |
673a394b | 806 | |
063e4e6b PZ |
807 | intel_fb_obj_invalidate(obj, NULL, ORIGIN_GTT); |
808 | ||
673a394b EA |
809 | while (remain > 0) { |
810 | /* Operation in this page | |
811 | * | |
0839ccb8 KP |
812 | * page_base = page offset within aperture |
813 | * page_offset = offset within page | |
814 | * page_length = bytes to copy for this page | |
673a394b | 815 | */ |
c8cbbb8b CW |
816 | page_base = offset & PAGE_MASK; |
817 | page_offset = offset_in_page(offset); | |
0839ccb8 KP |
818 | page_length = remain; |
819 | if ((page_offset + remain) > PAGE_SIZE) | |
820 | page_length = PAGE_SIZE - page_offset; | |
821 | ||
0839ccb8 | 822 | /* If we get a fault while copying data, then (presumably) our |
3de09aa3 EA |
823 | * source page isn't available. Return the error and we'll |
824 | * retry in the slow path. | |
0839ccb8 | 825 | */ |
5d4545ae | 826 | if (fast_user_write(dev_priv->gtt.mappable, page_base, |
935aaa69 DV |
827 | page_offset, user_data, page_length)) { |
828 | ret = -EFAULT; | |
063e4e6b | 829 | goto out_flush; |
935aaa69 | 830 | } |
673a394b | 831 | |
0839ccb8 KP |
832 | remain -= page_length; |
833 | user_data += page_length; | |
834 | offset += page_length; | |
673a394b | 835 | } |
673a394b | 836 | |
063e4e6b PZ |
837 | out_flush: |
838 | intel_fb_obj_flush(obj, false); | |
935aaa69 | 839 | out_unpin: |
d7f46fc4 | 840 | i915_gem_object_ggtt_unpin(obj); |
935aaa69 | 841 | out: |
3de09aa3 | 842 | return ret; |
673a394b EA |
843 | } |
844 | ||
d174bd64 DV |
845 | /* Per-page copy function for the shmem pwrite fastpath. |
846 | * Flushes invalid cachelines before writing to the target if | |
847 | * needs_clflush_before is set and flushes out any written cachelines after | |
848 | * writing if needs_clflush is set. */ | |
3043c60c | 849 | static int |
d174bd64 DV |
850 | shmem_pwrite_fast(struct page *page, int shmem_page_offset, int page_length, |
851 | char __user *user_data, | |
852 | bool page_do_bit17_swizzling, | |
853 | bool needs_clflush_before, | |
854 | bool needs_clflush_after) | |
673a394b | 855 | { |
d174bd64 | 856 | char *vaddr; |
673a394b | 857 | int ret; |
3de09aa3 | 858 | |
e7e58eb5 | 859 | if (unlikely(page_do_bit17_swizzling)) |
d174bd64 | 860 | return -EINVAL; |
3de09aa3 | 861 | |
d174bd64 DV |
862 | vaddr = kmap_atomic(page); |
863 | if (needs_clflush_before) | |
864 | drm_clflush_virt_range(vaddr + shmem_page_offset, | |
865 | page_length); | |
c2831a94 CW |
866 | ret = __copy_from_user_inatomic(vaddr + shmem_page_offset, |
867 | user_data, page_length); | |
d174bd64 DV |
868 | if (needs_clflush_after) |
869 | drm_clflush_virt_range(vaddr + shmem_page_offset, | |
870 | page_length); | |
871 | kunmap_atomic(vaddr); | |
3de09aa3 | 872 | |
755d2218 | 873 | return ret ? -EFAULT : 0; |
3de09aa3 EA |
874 | } |
875 | ||
d174bd64 DV |
876 | /* Only difference to the fast-path function is that this can handle bit17 |
877 | * and uses non-atomic copy and kmap functions. */ | |
3043c60c | 878 | static int |
d174bd64 DV |
879 | shmem_pwrite_slow(struct page *page, int shmem_page_offset, int page_length, |
880 | char __user *user_data, | |
881 | bool page_do_bit17_swizzling, | |
882 | bool needs_clflush_before, | |
883 | bool needs_clflush_after) | |
673a394b | 884 | { |
d174bd64 DV |
885 | char *vaddr; |
886 | int ret; | |
e5281ccd | 887 | |
d174bd64 | 888 | vaddr = kmap(page); |
e7e58eb5 | 889 | if (unlikely(needs_clflush_before || page_do_bit17_swizzling)) |
23c18c71 DV |
890 | shmem_clflush_swizzled_range(vaddr + shmem_page_offset, |
891 | page_length, | |
892 | page_do_bit17_swizzling); | |
d174bd64 DV |
893 | if (page_do_bit17_swizzling) |
894 | ret = __copy_from_user_swizzled(vaddr, shmem_page_offset, | |
e5281ccd CW |
895 | user_data, |
896 | page_length); | |
d174bd64 DV |
897 | else |
898 | ret = __copy_from_user(vaddr + shmem_page_offset, | |
899 | user_data, | |
900 | page_length); | |
901 | if (needs_clflush_after) | |
23c18c71 DV |
902 | shmem_clflush_swizzled_range(vaddr + shmem_page_offset, |
903 | page_length, | |
904 | page_do_bit17_swizzling); | |
d174bd64 | 905 | kunmap(page); |
40123c1f | 906 | |
755d2218 | 907 | return ret ? -EFAULT : 0; |
40123c1f EA |
908 | } |
909 | ||
40123c1f | 910 | static int |
e244a443 DV |
911 | i915_gem_shmem_pwrite(struct drm_device *dev, |
912 | struct drm_i915_gem_object *obj, | |
913 | struct drm_i915_gem_pwrite *args, | |
914 | struct drm_file *file) | |
40123c1f | 915 | { |
40123c1f | 916 | ssize_t remain; |
8c59967c DV |
917 | loff_t offset; |
918 | char __user *user_data; | |
eb2c0c81 | 919 | int shmem_page_offset, page_length, ret = 0; |
8c59967c | 920 | int obj_do_bit17_swizzling, page_do_bit17_swizzling; |
e244a443 | 921 | int hit_slowpath = 0; |
58642885 DV |
922 | int needs_clflush_after = 0; |
923 | int needs_clflush_before = 0; | |
67d5a50c | 924 | struct sg_page_iter sg_iter; |
40123c1f | 925 | |
2bb4629a | 926 | user_data = to_user_ptr(args->data_ptr); |
40123c1f EA |
927 | remain = args->size; |
928 | ||
8c59967c | 929 | obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj); |
40123c1f | 930 | |
58642885 DV |
931 | if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) { |
932 | /* If we're not in the cpu write domain, set ourself into the gtt | |
933 | * write domain and manually flush cachelines (if required). This | |
934 | * optimizes for the case when the gpu will use the data | |
935 | * right away and we therefore have to clflush anyway. */ | |
2c22569b | 936 | needs_clflush_after = cpu_write_needs_clflush(obj); |
23f54483 BW |
937 | ret = i915_gem_object_wait_rendering(obj, false); |
938 | if (ret) | |
939 | return ret; | |
58642885 | 940 | } |
c76ce038 CW |
941 | /* Same trick applies to invalidate partially written cachelines read |
942 | * before writing. */ | |
943 | if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0) | |
944 | needs_clflush_before = | |
945 | !cpu_cache_is_coherent(dev, obj->cache_level); | |
58642885 | 946 | |
755d2218 CW |
947 | ret = i915_gem_object_get_pages(obj); |
948 | if (ret) | |
949 | return ret; | |
950 | ||
063e4e6b PZ |
951 | intel_fb_obj_invalidate(obj, NULL, ORIGIN_CPU); |
952 | ||
755d2218 CW |
953 | i915_gem_object_pin_pages(obj); |
954 | ||
673a394b | 955 | offset = args->offset; |
05394f39 | 956 | obj->dirty = 1; |
673a394b | 957 | |
67d5a50c ID |
958 | for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, |
959 | offset >> PAGE_SHIFT) { | |
2db76d7c | 960 | struct page *page = sg_page_iter_page(&sg_iter); |
58642885 | 961 | int partial_cacheline_write; |
e5281ccd | 962 | |
9da3da66 CW |
963 | if (remain <= 0) |
964 | break; | |
965 | ||
40123c1f EA |
966 | /* Operation in this page |
967 | * | |
40123c1f | 968 | * shmem_page_offset = offset within page in shmem file |
40123c1f EA |
969 | * page_length = bytes to copy for this page |
970 | */ | |
c8cbbb8b | 971 | shmem_page_offset = offset_in_page(offset); |
40123c1f EA |
972 | |
973 | page_length = remain; | |
974 | if ((shmem_page_offset + page_length) > PAGE_SIZE) | |
975 | page_length = PAGE_SIZE - shmem_page_offset; | |
40123c1f | 976 | |
58642885 DV |
977 | /* If we don't overwrite a cacheline completely we need to be |
978 | * careful to have up-to-date data by first clflushing. Don't | |
979 | * overcomplicate things and flush the entire patch. */ | |
980 | partial_cacheline_write = needs_clflush_before && | |
981 | ((shmem_page_offset | page_length) | |
982 | & (boot_cpu_data.x86_clflush_size - 1)); | |
983 | ||
8c59967c DV |
984 | page_do_bit17_swizzling = obj_do_bit17_swizzling && |
985 | (page_to_phys(page) & (1 << 17)) != 0; | |
986 | ||
d174bd64 DV |
987 | ret = shmem_pwrite_fast(page, shmem_page_offset, page_length, |
988 | user_data, page_do_bit17_swizzling, | |
989 | partial_cacheline_write, | |
990 | needs_clflush_after); | |
991 | if (ret == 0) | |
992 | goto next_page; | |
e244a443 DV |
993 | |
994 | hit_slowpath = 1; | |
e244a443 | 995 | mutex_unlock(&dev->struct_mutex); |
d174bd64 DV |
996 | ret = shmem_pwrite_slow(page, shmem_page_offset, page_length, |
997 | user_data, page_do_bit17_swizzling, | |
998 | partial_cacheline_write, | |
999 | needs_clflush_after); | |
40123c1f | 1000 | |
e244a443 | 1001 | mutex_lock(&dev->struct_mutex); |
755d2218 | 1002 | |
755d2218 | 1003 | if (ret) |
8c59967c | 1004 | goto out; |
8c59967c | 1005 | |
17793c9a | 1006 | next_page: |
40123c1f | 1007 | remain -= page_length; |
8c59967c | 1008 | user_data += page_length; |
40123c1f | 1009 | offset += page_length; |
673a394b EA |
1010 | } |
1011 | ||
fbd5a26d | 1012 | out: |
755d2218 CW |
1013 | i915_gem_object_unpin_pages(obj); |
1014 | ||
e244a443 | 1015 | if (hit_slowpath) { |
8dcf015e DV |
1016 | /* |
1017 | * Fixup: Flush cpu caches in case we didn't flush the dirty | |
1018 | * cachelines in-line while writing and the object moved | |
1019 | * out of the cpu write domain while we've dropped the lock. | |
1020 | */ | |
1021 | if (!needs_clflush_after && | |
1022 | obj->base.write_domain != I915_GEM_DOMAIN_CPU) { | |
000433b6 CW |
1023 | if (i915_gem_clflush_object(obj, obj->pin_display)) |
1024 | i915_gem_chipset_flush(dev); | |
e244a443 | 1025 | } |
8c59967c | 1026 | } |
673a394b | 1027 | |
58642885 | 1028 | if (needs_clflush_after) |
e76e9aeb | 1029 | i915_gem_chipset_flush(dev); |
58642885 | 1030 | |
063e4e6b | 1031 | intel_fb_obj_flush(obj, false); |
40123c1f | 1032 | return ret; |
673a394b EA |
1033 | } |
1034 | ||
1035 | /** | |
1036 | * Writes data to the object referenced by handle. | |
1037 | * | |
1038 | * On error, the contents of the buffer that were to be modified are undefined. | |
1039 | */ | |
1040 | int | |
1041 | i915_gem_pwrite_ioctl(struct drm_device *dev, void *data, | |
fbd5a26d | 1042 | struct drm_file *file) |
673a394b | 1043 | { |
5d77d9c5 | 1044 | struct drm_i915_private *dev_priv = dev->dev_private; |
673a394b | 1045 | struct drm_i915_gem_pwrite *args = data; |
05394f39 | 1046 | struct drm_i915_gem_object *obj; |
51311d0a CW |
1047 | int ret; |
1048 | ||
1049 | if (args->size == 0) | |
1050 | return 0; | |
1051 | ||
1052 | if (!access_ok(VERIFY_READ, | |
2bb4629a | 1053 | to_user_ptr(args->data_ptr), |
51311d0a CW |
1054 | args->size)) |
1055 | return -EFAULT; | |
1056 | ||
d330a953 | 1057 | if (likely(!i915.prefault_disable)) { |
0b74b508 XZ |
1058 | ret = fault_in_multipages_readable(to_user_ptr(args->data_ptr), |
1059 | args->size); | |
1060 | if (ret) | |
1061 | return -EFAULT; | |
1062 | } | |
673a394b | 1063 | |
5d77d9c5 ID |
1064 | intel_runtime_pm_get(dev_priv); |
1065 | ||
fbd5a26d | 1066 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 1067 | if (ret) |
5d77d9c5 | 1068 | goto put_rpm; |
1d7cfea1 | 1069 | |
05394f39 | 1070 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 1071 | if (&obj->base == NULL) { |
1d7cfea1 CW |
1072 | ret = -ENOENT; |
1073 | goto unlock; | |
fbd5a26d | 1074 | } |
673a394b | 1075 | |
7dcd2499 | 1076 | /* Bounds check destination. */ |
05394f39 CW |
1077 | if (args->offset > obj->base.size || |
1078 | args->size > obj->base.size - args->offset) { | |
ce9d419d | 1079 | ret = -EINVAL; |
35b62a89 | 1080 | goto out; |
ce9d419d CW |
1081 | } |
1082 | ||
1286ff73 DV |
1083 | /* prime objects have no backing filp to GEM pread/pwrite |
1084 | * pages from. | |
1085 | */ | |
1086 | if (!obj->base.filp) { | |
1087 | ret = -EINVAL; | |
1088 | goto out; | |
1089 | } | |
1090 | ||
db53a302 CW |
1091 | trace_i915_gem_object_pwrite(obj, args->offset, args->size); |
1092 | ||
935aaa69 | 1093 | ret = -EFAULT; |
673a394b EA |
1094 | /* We can only do the GTT pwrite on untiled buffers, as otherwise |
1095 | * it would end up going through the fenced access, and we'll get | |
1096 | * different detiling behavior between reading and writing. | |
1097 | * pread/pwrite currently are reading and writing from the CPU | |
1098 | * perspective, requiring manual detiling by the client. | |
1099 | */ | |
2c22569b CW |
1100 | if (obj->tiling_mode == I915_TILING_NONE && |
1101 | obj->base.write_domain != I915_GEM_DOMAIN_CPU && | |
1102 | cpu_write_needs_clflush(obj)) { | |
fbd5a26d | 1103 | ret = i915_gem_gtt_pwrite_fast(dev, obj, args, file); |
935aaa69 DV |
1104 | /* Note that the gtt paths might fail with non-page-backed user |
1105 | * pointers (e.g. gtt mappings when moving data between | |
1106 | * textures). Fallback to the shmem path in that case. */ | |
fbd5a26d | 1107 | } |
673a394b | 1108 | |
6a2c4232 CW |
1109 | if (ret == -EFAULT || ret == -ENOSPC) { |
1110 | if (obj->phys_handle) | |
1111 | ret = i915_gem_phys_pwrite(obj, args, file); | |
1112 | else | |
1113 | ret = i915_gem_shmem_pwrite(dev, obj, args, file); | |
1114 | } | |
5c0480f2 | 1115 | |
35b62a89 | 1116 | out: |
05394f39 | 1117 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 1118 | unlock: |
fbd5a26d | 1119 | mutex_unlock(&dev->struct_mutex); |
5d77d9c5 ID |
1120 | put_rpm: |
1121 | intel_runtime_pm_put(dev_priv); | |
1122 | ||
673a394b EA |
1123 | return ret; |
1124 | } | |
1125 | ||
b361237b | 1126 | int |
33196ded | 1127 | i915_gem_check_wedge(struct i915_gpu_error *error, |
b361237b CW |
1128 | bool interruptible) |
1129 | { | |
1f83fee0 | 1130 | if (i915_reset_in_progress(error)) { |
b361237b CW |
1131 | /* Non-interruptible callers can't handle -EAGAIN, hence return |
1132 | * -EIO unconditionally for these. */ | |
1133 | if (!interruptible) | |
1134 | return -EIO; | |
1135 | ||
1f83fee0 DV |
1136 | /* Recovery complete, but the reset failed ... */ |
1137 | if (i915_terminally_wedged(error)) | |
b361237b CW |
1138 | return -EIO; |
1139 | ||
6689c167 MA |
1140 | /* |
1141 | * Check if GPU Reset is in progress - we need intel_ring_begin | |
1142 | * to work properly to reinit the hw state while the gpu is | |
1143 | * still marked as reset-in-progress. Handle this with a flag. | |
1144 | */ | |
1145 | if (!error->reload_in_reset) | |
1146 | return -EAGAIN; | |
b361237b CW |
1147 | } |
1148 | ||
1149 | return 0; | |
1150 | } | |
1151 | ||
1152 | /* | |
b6660d59 | 1153 | * Compare arbitrary request against outstanding lazy request. Emit on match. |
b361237b | 1154 | */ |
84c33a64 | 1155 | int |
b6660d59 | 1156 | i915_gem_check_olr(struct drm_i915_gem_request *req) |
b361237b CW |
1157 | { |
1158 | int ret; | |
1159 | ||
b6660d59 | 1160 | WARN_ON(!mutex_is_locked(&req->ring->dev->struct_mutex)); |
b361237b CW |
1161 | |
1162 | ret = 0; | |
b6660d59 | 1163 | if (req == req->ring->outstanding_lazy_request) |
9400ae5c | 1164 | ret = i915_add_request(req->ring); |
b361237b CW |
1165 | |
1166 | return ret; | |
1167 | } | |
1168 | ||
094f9a54 CW |
1169 | static void fake_irq(unsigned long data) |
1170 | { | |
1171 | wake_up_process((struct task_struct *)data); | |
1172 | } | |
1173 | ||
1174 | static bool missed_irq(struct drm_i915_private *dev_priv, | |
a4872ba6 | 1175 | struct intel_engine_cs *ring) |
094f9a54 CW |
1176 | { |
1177 | return test_bit(ring->id, &dev_priv->gpu_error.missed_irq_rings); | |
1178 | } | |
1179 | ||
eed29a5b | 1180 | static int __i915_spin_request(struct drm_i915_gem_request *req) |
b29c19b6 | 1181 | { |
2def4ad9 CW |
1182 | unsigned long timeout; |
1183 | ||
eed29a5b | 1184 | if (i915_gem_request_get_ring(req)->irq_refcount) |
2def4ad9 CW |
1185 | return -EBUSY; |
1186 | ||
1187 | timeout = jiffies + 1; | |
1188 | while (!need_resched()) { | |
eed29a5b | 1189 | if (i915_gem_request_completed(req, true)) |
2def4ad9 CW |
1190 | return 0; |
1191 | ||
1192 | if (time_after_eq(jiffies, timeout)) | |
1193 | break; | |
b29c19b6 | 1194 | |
2def4ad9 CW |
1195 | cpu_relax_lowlatency(); |
1196 | } | |
eed29a5b | 1197 | if (i915_gem_request_completed(req, false)) |
2def4ad9 CW |
1198 | return 0; |
1199 | ||
1200 | return -EAGAIN; | |
b29c19b6 CW |
1201 | } |
1202 | ||
b361237b | 1203 | /** |
9c654818 JH |
1204 | * __i915_wait_request - wait until execution of request has finished |
1205 | * @req: duh! | |
1206 | * @reset_counter: reset sequence associated with the given request | |
b361237b CW |
1207 | * @interruptible: do an interruptible wait (normally yes) |
1208 | * @timeout: in - how long to wait (NULL forever); out - how much time remaining | |
1209 | * | |
f69061be DV |
1210 | * Note: It is of utmost importance that the passed in seqno and reset_counter |
1211 | * values have been read by the caller in an smp safe manner. Where read-side | |
1212 | * locks are involved, it is sufficient to read the reset_counter before | |
1213 | * unlocking the lock that protects the seqno. For lockless tricks, the | |
1214 | * reset_counter _must_ be read before, and an appropriate smp_rmb must be | |
1215 | * inserted. | |
1216 | * | |
9c654818 | 1217 | * Returns 0 if the request was found within the alloted time. Else returns the |
b361237b CW |
1218 | * errno with remaining time filled in timeout argument. |
1219 | */ | |
9c654818 | 1220 | int __i915_wait_request(struct drm_i915_gem_request *req, |
f69061be | 1221 | unsigned reset_counter, |
b29c19b6 | 1222 | bool interruptible, |
5ed0bdf2 | 1223 | s64 *timeout, |
2e1b8730 | 1224 | struct intel_rps_client *rps) |
b361237b | 1225 | { |
9c654818 | 1226 | struct intel_engine_cs *ring = i915_gem_request_get_ring(req); |
3d13ef2e | 1227 | struct drm_device *dev = ring->dev; |
3e31c6c0 | 1228 | struct drm_i915_private *dev_priv = dev->dev_private; |
168c3f21 MK |
1229 | const bool irq_test_in_progress = |
1230 | ACCESS_ONCE(dev_priv->gpu_error.test_irq_rings) & intel_ring_flag(ring); | |
094f9a54 | 1231 | DEFINE_WAIT(wait); |
47e9766d | 1232 | unsigned long timeout_expire; |
5ed0bdf2 | 1233 | s64 before, now; |
b361237b CW |
1234 | int ret; |
1235 | ||
9df7575f | 1236 | WARN(!intel_irqs_enabled(dev_priv), "IRQs disabled"); |
c67a470b | 1237 | |
b4716185 CW |
1238 | if (list_empty(&req->list)) |
1239 | return 0; | |
1240 | ||
1b5a433a | 1241 | if (i915_gem_request_completed(req, true)) |
b361237b CW |
1242 | return 0; |
1243 | ||
7bd0e226 DV |
1244 | timeout_expire = timeout ? |
1245 | jiffies + nsecs_to_jiffies_timeout((u64)*timeout) : 0; | |
b361237b | 1246 | |
2e1b8730 | 1247 | if (INTEL_INFO(dev_priv)->gen >= 6) |
e61b9958 | 1248 | gen6_rps_boost(dev_priv, rps, req->emitted_jiffies); |
b361237b | 1249 | |
094f9a54 | 1250 | /* Record current time in case interrupted by signal, or wedged */ |
74328ee5 | 1251 | trace_i915_gem_request_wait_begin(req); |
5ed0bdf2 | 1252 | before = ktime_get_raw_ns(); |
2def4ad9 CW |
1253 | |
1254 | /* Optimistic spin for the next jiffie before touching IRQs */ | |
1255 | ret = __i915_spin_request(req); | |
1256 | if (ret == 0) | |
1257 | goto out; | |
1258 | ||
1259 | if (!irq_test_in_progress && WARN_ON(!ring->irq_get(ring))) { | |
1260 | ret = -ENODEV; | |
1261 | goto out; | |
1262 | } | |
1263 | ||
094f9a54 CW |
1264 | for (;;) { |
1265 | struct timer_list timer; | |
b361237b | 1266 | |
094f9a54 CW |
1267 | prepare_to_wait(&ring->irq_queue, &wait, |
1268 | interruptible ? TASK_INTERRUPTIBLE : TASK_UNINTERRUPTIBLE); | |
b361237b | 1269 | |
f69061be DV |
1270 | /* We need to check whether any gpu reset happened in between |
1271 | * the caller grabbing the seqno and now ... */ | |
094f9a54 CW |
1272 | if (reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter)) { |
1273 | /* ... but upgrade the -EAGAIN to an -EIO if the gpu | |
1274 | * is truely gone. */ | |
1275 | ret = i915_gem_check_wedge(&dev_priv->gpu_error, interruptible); | |
1276 | if (ret == 0) | |
1277 | ret = -EAGAIN; | |
1278 | break; | |
1279 | } | |
f69061be | 1280 | |
1b5a433a | 1281 | if (i915_gem_request_completed(req, false)) { |
094f9a54 CW |
1282 | ret = 0; |
1283 | break; | |
1284 | } | |
b361237b | 1285 | |
094f9a54 CW |
1286 | if (interruptible && signal_pending(current)) { |
1287 | ret = -ERESTARTSYS; | |
1288 | break; | |
1289 | } | |
1290 | ||
47e9766d | 1291 | if (timeout && time_after_eq(jiffies, timeout_expire)) { |
094f9a54 CW |
1292 | ret = -ETIME; |
1293 | break; | |
1294 | } | |
1295 | ||
1296 | timer.function = NULL; | |
1297 | if (timeout || missed_irq(dev_priv, ring)) { | |
47e9766d MK |
1298 | unsigned long expire; |
1299 | ||
094f9a54 | 1300 | setup_timer_on_stack(&timer, fake_irq, (unsigned long)current); |
47e9766d | 1301 | expire = missed_irq(dev_priv, ring) ? jiffies + 1 : timeout_expire; |
094f9a54 CW |
1302 | mod_timer(&timer, expire); |
1303 | } | |
1304 | ||
5035c275 | 1305 | io_schedule(); |
094f9a54 | 1306 | |
094f9a54 CW |
1307 | if (timer.function) { |
1308 | del_singleshot_timer_sync(&timer); | |
1309 | destroy_timer_on_stack(&timer); | |
1310 | } | |
1311 | } | |
168c3f21 MK |
1312 | if (!irq_test_in_progress) |
1313 | ring->irq_put(ring); | |
094f9a54 CW |
1314 | |
1315 | finish_wait(&ring->irq_queue, &wait); | |
b361237b | 1316 | |
2def4ad9 CW |
1317 | out: |
1318 | now = ktime_get_raw_ns(); | |
1319 | trace_i915_gem_request_wait_end(req); | |
1320 | ||
b361237b | 1321 | if (timeout) { |
5ed0bdf2 TG |
1322 | s64 tres = *timeout - (now - before); |
1323 | ||
1324 | *timeout = tres < 0 ? 0 : tres; | |
9cca3068 DV |
1325 | |
1326 | /* | |
1327 | * Apparently ktime isn't accurate enough and occasionally has a | |
1328 | * bit of mismatch in the jiffies<->nsecs<->ktime loop. So patch | |
1329 | * things up to make the test happy. We allow up to 1 jiffy. | |
1330 | * | |
1331 | * This is a regrssion from the timespec->ktime conversion. | |
1332 | */ | |
1333 | if (ret == -ETIME && *timeout < jiffies_to_usecs(1)*1000) | |
1334 | *timeout = 0; | |
b361237b CW |
1335 | } |
1336 | ||
094f9a54 | 1337 | return ret; |
b361237b CW |
1338 | } |
1339 | ||
b4716185 CW |
1340 | static inline void |
1341 | i915_gem_request_remove_from_client(struct drm_i915_gem_request *request) | |
1342 | { | |
1343 | struct drm_i915_file_private *file_priv = request->file_priv; | |
1344 | ||
1345 | if (!file_priv) | |
1346 | return; | |
1347 | ||
1348 | spin_lock(&file_priv->mm.lock); | |
1349 | list_del(&request->client_list); | |
1350 | request->file_priv = NULL; | |
1351 | spin_unlock(&file_priv->mm.lock); | |
1352 | } | |
1353 | ||
1354 | static void i915_gem_request_retire(struct drm_i915_gem_request *request) | |
1355 | { | |
1356 | trace_i915_gem_request_retire(request); | |
1357 | ||
1358 | /* We know the GPU must have read the request to have | |
1359 | * sent us the seqno + interrupt, so use the position | |
1360 | * of tail of the request to update the last known position | |
1361 | * of the GPU head. | |
1362 | * | |
1363 | * Note this requires that we are always called in request | |
1364 | * completion order. | |
1365 | */ | |
1366 | request->ringbuf->last_retired_head = request->postfix; | |
1367 | ||
1368 | list_del_init(&request->list); | |
1369 | i915_gem_request_remove_from_client(request); | |
1370 | ||
1371 | put_pid(request->pid); | |
1372 | ||
1373 | i915_gem_request_unreference(request); | |
1374 | } | |
1375 | ||
1376 | static void | |
1377 | __i915_gem_request_retire__upto(struct drm_i915_gem_request *req) | |
1378 | { | |
1379 | struct intel_engine_cs *engine = req->ring; | |
1380 | struct drm_i915_gem_request *tmp; | |
1381 | ||
1382 | lockdep_assert_held(&engine->dev->struct_mutex); | |
1383 | ||
1384 | if (list_empty(&req->list)) | |
1385 | return; | |
1386 | ||
1387 | do { | |
1388 | tmp = list_first_entry(&engine->request_list, | |
1389 | typeof(*tmp), list); | |
1390 | ||
1391 | i915_gem_request_retire(tmp); | |
1392 | } while (tmp != req); | |
1393 | ||
1394 | WARN_ON(i915_verify_lists(engine->dev)); | |
1395 | } | |
1396 | ||
b361237b | 1397 | /** |
a4b3a571 | 1398 | * Waits for a request to be signaled, and cleans up the |
b361237b CW |
1399 | * request and object lists appropriately for that event. |
1400 | */ | |
1401 | int | |
a4b3a571 | 1402 | i915_wait_request(struct drm_i915_gem_request *req) |
b361237b | 1403 | { |
a4b3a571 DV |
1404 | struct drm_device *dev; |
1405 | struct drm_i915_private *dev_priv; | |
1406 | bool interruptible; | |
b361237b CW |
1407 | int ret; |
1408 | ||
a4b3a571 DV |
1409 | BUG_ON(req == NULL); |
1410 | ||
1411 | dev = req->ring->dev; | |
1412 | dev_priv = dev->dev_private; | |
1413 | interruptible = dev_priv->mm.interruptible; | |
1414 | ||
b361237b | 1415 | BUG_ON(!mutex_is_locked(&dev->struct_mutex)); |
b361237b | 1416 | |
33196ded | 1417 | ret = i915_gem_check_wedge(&dev_priv->gpu_error, interruptible); |
b361237b CW |
1418 | if (ret) |
1419 | return ret; | |
1420 | ||
a4b3a571 | 1421 | ret = i915_gem_check_olr(req); |
b361237b CW |
1422 | if (ret) |
1423 | return ret; | |
1424 | ||
b4716185 CW |
1425 | ret = __i915_wait_request(req, |
1426 | atomic_read(&dev_priv->gpu_error.reset_counter), | |
9c654818 | 1427 | interruptible, NULL, NULL); |
b4716185 CW |
1428 | if (ret) |
1429 | return ret; | |
d26e3af8 | 1430 | |
b4716185 | 1431 | __i915_gem_request_retire__upto(req); |
d26e3af8 CW |
1432 | return 0; |
1433 | } | |
1434 | ||
b361237b CW |
1435 | /** |
1436 | * Ensures that all rendering to the object has completed and the object is | |
1437 | * safe to unbind from the GTT or access from the CPU. | |
1438 | */ | |
2e2f351d | 1439 | int |
b361237b CW |
1440 | i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj, |
1441 | bool readonly) | |
1442 | { | |
b4716185 | 1443 | int ret, i; |
b361237b | 1444 | |
b4716185 | 1445 | if (!obj->active) |
b361237b CW |
1446 | return 0; |
1447 | ||
b4716185 CW |
1448 | if (readonly) { |
1449 | if (obj->last_write_req != NULL) { | |
1450 | ret = i915_wait_request(obj->last_write_req); | |
1451 | if (ret) | |
1452 | return ret; | |
b361237b | 1453 | |
b4716185 CW |
1454 | i = obj->last_write_req->ring->id; |
1455 | if (obj->last_read_req[i] == obj->last_write_req) | |
1456 | i915_gem_object_retire__read(obj, i); | |
1457 | else | |
1458 | i915_gem_object_retire__write(obj); | |
1459 | } | |
1460 | } else { | |
1461 | for (i = 0; i < I915_NUM_RINGS; i++) { | |
1462 | if (obj->last_read_req[i] == NULL) | |
1463 | continue; | |
1464 | ||
1465 | ret = i915_wait_request(obj->last_read_req[i]); | |
1466 | if (ret) | |
1467 | return ret; | |
1468 | ||
1469 | i915_gem_object_retire__read(obj, i); | |
1470 | } | |
1471 | RQ_BUG_ON(obj->active); | |
1472 | } | |
1473 | ||
1474 | return 0; | |
1475 | } | |
1476 | ||
1477 | static void | |
1478 | i915_gem_object_retire_request(struct drm_i915_gem_object *obj, | |
1479 | struct drm_i915_gem_request *req) | |
1480 | { | |
1481 | int ring = req->ring->id; | |
1482 | ||
1483 | if (obj->last_read_req[ring] == req) | |
1484 | i915_gem_object_retire__read(obj, ring); | |
1485 | else if (obj->last_write_req == req) | |
1486 | i915_gem_object_retire__write(obj); | |
1487 | ||
1488 | __i915_gem_request_retire__upto(req); | |
b361237b CW |
1489 | } |
1490 | ||
3236f57a CW |
1491 | /* A nonblocking variant of the above wait. This is a highly dangerous routine |
1492 | * as the object state may change during this call. | |
1493 | */ | |
1494 | static __must_check int | |
1495 | i915_gem_object_wait_rendering__nonblocking(struct drm_i915_gem_object *obj, | |
2e1b8730 | 1496 | struct intel_rps_client *rps, |
3236f57a CW |
1497 | bool readonly) |
1498 | { | |
1499 | struct drm_device *dev = obj->base.dev; | |
1500 | struct drm_i915_private *dev_priv = dev->dev_private; | |
b4716185 | 1501 | struct drm_i915_gem_request *requests[I915_NUM_RINGS]; |
f69061be | 1502 | unsigned reset_counter; |
b4716185 | 1503 | int ret, i, n = 0; |
3236f57a CW |
1504 | |
1505 | BUG_ON(!mutex_is_locked(&dev->struct_mutex)); | |
1506 | BUG_ON(!dev_priv->mm.interruptible); | |
1507 | ||
b4716185 | 1508 | if (!obj->active) |
3236f57a CW |
1509 | return 0; |
1510 | ||
33196ded | 1511 | ret = i915_gem_check_wedge(&dev_priv->gpu_error, true); |
3236f57a CW |
1512 | if (ret) |
1513 | return ret; | |
1514 | ||
f69061be | 1515 | reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter); |
b4716185 CW |
1516 | |
1517 | if (readonly) { | |
1518 | struct drm_i915_gem_request *req; | |
1519 | ||
1520 | req = obj->last_write_req; | |
1521 | if (req == NULL) | |
1522 | return 0; | |
1523 | ||
1524 | ret = i915_gem_check_olr(req); | |
1525 | if (ret) | |
1526 | goto err; | |
1527 | ||
1528 | requests[n++] = i915_gem_request_reference(req); | |
1529 | } else { | |
1530 | for (i = 0; i < I915_NUM_RINGS; i++) { | |
1531 | struct drm_i915_gem_request *req; | |
1532 | ||
1533 | req = obj->last_read_req[i]; | |
1534 | if (req == NULL) | |
1535 | continue; | |
1536 | ||
1537 | ret = i915_gem_check_olr(req); | |
1538 | if (ret) | |
1539 | goto err; | |
1540 | ||
1541 | requests[n++] = i915_gem_request_reference(req); | |
1542 | } | |
1543 | } | |
1544 | ||
3236f57a | 1545 | mutex_unlock(&dev->struct_mutex); |
b4716185 CW |
1546 | for (i = 0; ret == 0 && i < n; i++) |
1547 | ret = __i915_wait_request(requests[i], reset_counter, true, | |
2e1b8730 | 1548 | NULL, rps); |
3236f57a CW |
1549 | mutex_lock(&dev->struct_mutex); |
1550 | ||
b4716185 CW |
1551 | err: |
1552 | for (i = 0; i < n; i++) { | |
1553 | if (ret == 0) | |
1554 | i915_gem_object_retire_request(obj, requests[i]); | |
1555 | i915_gem_request_unreference(requests[i]); | |
1556 | } | |
1557 | ||
1558 | return ret; | |
3236f57a CW |
1559 | } |
1560 | ||
2e1b8730 CW |
1561 | static struct intel_rps_client *to_rps_client(struct drm_file *file) |
1562 | { | |
1563 | struct drm_i915_file_private *fpriv = file->driver_priv; | |
1564 | return &fpriv->rps; | |
1565 | } | |
1566 | ||
673a394b | 1567 | /** |
2ef7eeaa EA |
1568 | * Called when user space prepares to use an object with the CPU, either |
1569 | * through the mmap ioctl's mapping or a GTT mapping. | |
673a394b EA |
1570 | */ |
1571 | int | |
1572 | i915_gem_set_domain_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 1573 | struct drm_file *file) |
673a394b EA |
1574 | { |
1575 | struct drm_i915_gem_set_domain *args = data; | |
05394f39 | 1576 | struct drm_i915_gem_object *obj; |
2ef7eeaa EA |
1577 | uint32_t read_domains = args->read_domains; |
1578 | uint32_t write_domain = args->write_domain; | |
673a394b EA |
1579 | int ret; |
1580 | ||
2ef7eeaa | 1581 | /* Only handle setting domains to types used by the CPU. */ |
21d509e3 | 1582 | if (write_domain & I915_GEM_GPU_DOMAINS) |
2ef7eeaa EA |
1583 | return -EINVAL; |
1584 | ||
21d509e3 | 1585 | if (read_domains & I915_GEM_GPU_DOMAINS) |
2ef7eeaa EA |
1586 | return -EINVAL; |
1587 | ||
1588 | /* Having something in the write domain implies it's in the read | |
1589 | * domain, and only that read domain. Enforce that in the request. | |
1590 | */ | |
1591 | if (write_domain != 0 && read_domains != write_domain) | |
1592 | return -EINVAL; | |
1593 | ||
76c1dec1 | 1594 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 1595 | if (ret) |
76c1dec1 | 1596 | return ret; |
1d7cfea1 | 1597 | |
05394f39 | 1598 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 1599 | if (&obj->base == NULL) { |
1d7cfea1 CW |
1600 | ret = -ENOENT; |
1601 | goto unlock; | |
76c1dec1 | 1602 | } |
673a394b | 1603 | |
3236f57a CW |
1604 | /* Try to flush the object off the GPU without holding the lock. |
1605 | * We will repeat the flush holding the lock in the normal manner | |
1606 | * to catch cases where we are gazumped. | |
1607 | */ | |
6e4930f6 | 1608 | ret = i915_gem_object_wait_rendering__nonblocking(obj, |
2e1b8730 | 1609 | to_rps_client(file), |
6e4930f6 | 1610 | !write_domain); |
3236f57a CW |
1611 | if (ret) |
1612 | goto unref; | |
1613 | ||
43566ded | 1614 | if (read_domains & I915_GEM_DOMAIN_GTT) |
2ef7eeaa | 1615 | ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0); |
43566ded | 1616 | else |
e47c68e9 | 1617 | ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0); |
2ef7eeaa | 1618 | |
3236f57a | 1619 | unref: |
05394f39 | 1620 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 1621 | unlock: |
673a394b EA |
1622 | mutex_unlock(&dev->struct_mutex); |
1623 | return ret; | |
1624 | } | |
1625 | ||
1626 | /** | |
1627 | * Called when user space has done writes to this buffer | |
1628 | */ | |
1629 | int | |
1630 | i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 1631 | struct drm_file *file) |
673a394b EA |
1632 | { |
1633 | struct drm_i915_gem_sw_finish *args = data; | |
05394f39 | 1634 | struct drm_i915_gem_object *obj; |
673a394b EA |
1635 | int ret = 0; |
1636 | ||
76c1dec1 | 1637 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 1638 | if (ret) |
76c1dec1 | 1639 | return ret; |
1d7cfea1 | 1640 | |
05394f39 | 1641 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 1642 | if (&obj->base == NULL) { |
1d7cfea1 CW |
1643 | ret = -ENOENT; |
1644 | goto unlock; | |
673a394b EA |
1645 | } |
1646 | ||
673a394b | 1647 | /* Pinned buffers may be scanout, so flush the cache */ |
2c22569b | 1648 | if (obj->pin_display) |
e62b59e4 | 1649 | i915_gem_object_flush_cpu_write_domain(obj); |
e47c68e9 | 1650 | |
05394f39 | 1651 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 1652 | unlock: |
673a394b EA |
1653 | mutex_unlock(&dev->struct_mutex); |
1654 | return ret; | |
1655 | } | |
1656 | ||
1657 | /** | |
1658 | * Maps the contents of an object, returning the address it is mapped | |
1659 | * into. | |
1660 | * | |
1661 | * While the mapping holds a reference on the contents of the object, it doesn't | |
1662 | * imply a ref on the object itself. | |
34367381 DV |
1663 | * |
1664 | * IMPORTANT: | |
1665 | * | |
1666 | * DRM driver writers who look a this function as an example for how to do GEM | |
1667 | * mmap support, please don't implement mmap support like here. The modern way | |
1668 | * to implement DRM mmap support is with an mmap offset ioctl (like | |
1669 | * i915_gem_mmap_gtt) and then using the mmap syscall on the DRM fd directly. | |
1670 | * That way debug tooling like valgrind will understand what's going on, hiding | |
1671 | * the mmap call in a driver private ioctl will break that. The i915 driver only | |
1672 | * does cpu mmaps this way because we didn't know better. | |
673a394b EA |
1673 | */ |
1674 | int | |
1675 | i915_gem_mmap_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 1676 | struct drm_file *file) |
673a394b EA |
1677 | { |
1678 | struct drm_i915_gem_mmap *args = data; | |
1679 | struct drm_gem_object *obj; | |
673a394b EA |
1680 | unsigned long addr; |
1681 | ||
1816f923 AG |
1682 | if (args->flags & ~(I915_MMAP_WC)) |
1683 | return -EINVAL; | |
1684 | ||
1685 | if (args->flags & I915_MMAP_WC && !cpu_has_pat) | |
1686 | return -ENODEV; | |
1687 | ||
05394f39 | 1688 | obj = drm_gem_object_lookup(dev, file, args->handle); |
673a394b | 1689 | if (obj == NULL) |
bf79cb91 | 1690 | return -ENOENT; |
673a394b | 1691 | |
1286ff73 DV |
1692 | /* prime objects have no backing filp to GEM mmap |
1693 | * pages from. | |
1694 | */ | |
1695 | if (!obj->filp) { | |
1696 | drm_gem_object_unreference_unlocked(obj); | |
1697 | return -EINVAL; | |
1698 | } | |
1699 | ||
6be5ceb0 | 1700 | addr = vm_mmap(obj->filp, 0, args->size, |
673a394b EA |
1701 | PROT_READ | PROT_WRITE, MAP_SHARED, |
1702 | args->offset); | |
1816f923 AG |
1703 | if (args->flags & I915_MMAP_WC) { |
1704 | struct mm_struct *mm = current->mm; | |
1705 | struct vm_area_struct *vma; | |
1706 | ||
1707 | down_write(&mm->mmap_sem); | |
1708 | vma = find_vma(mm, addr); | |
1709 | if (vma) | |
1710 | vma->vm_page_prot = | |
1711 | pgprot_writecombine(vm_get_page_prot(vma->vm_flags)); | |
1712 | else | |
1713 | addr = -ENOMEM; | |
1714 | up_write(&mm->mmap_sem); | |
1715 | } | |
bc9025bd | 1716 | drm_gem_object_unreference_unlocked(obj); |
673a394b EA |
1717 | if (IS_ERR((void *)addr)) |
1718 | return addr; | |
1719 | ||
1720 | args->addr_ptr = (uint64_t) addr; | |
1721 | ||
1722 | return 0; | |
1723 | } | |
1724 | ||
de151cf6 JB |
1725 | /** |
1726 | * i915_gem_fault - fault a page into the GTT | |
1727 | * vma: VMA in question | |
1728 | * vmf: fault info | |
1729 | * | |
1730 | * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped | |
1731 | * from userspace. The fault handler takes care of binding the object to | |
1732 | * the GTT (if needed), allocating and programming a fence register (again, | |
1733 | * only if needed based on whether the old reg is still valid or the object | |
1734 | * is tiled) and inserting a new PTE into the faulting process. | |
1735 | * | |
1736 | * Note that the faulting process may involve evicting existing objects | |
1737 | * from the GTT and/or fence registers to make room. So performance may | |
1738 | * suffer if the GTT working set is large or there are few fence registers | |
1739 | * left. | |
1740 | */ | |
1741 | int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf) | |
1742 | { | |
05394f39 CW |
1743 | struct drm_i915_gem_object *obj = to_intel_bo(vma->vm_private_data); |
1744 | struct drm_device *dev = obj->base.dev; | |
3e31c6c0 | 1745 | struct drm_i915_private *dev_priv = dev->dev_private; |
c5ad54cf | 1746 | struct i915_ggtt_view view = i915_ggtt_view_normal; |
de151cf6 JB |
1747 | pgoff_t page_offset; |
1748 | unsigned long pfn; | |
1749 | int ret = 0; | |
0f973f27 | 1750 | bool write = !!(vmf->flags & FAULT_FLAG_WRITE); |
de151cf6 | 1751 | |
f65c9168 PZ |
1752 | intel_runtime_pm_get(dev_priv); |
1753 | ||
de151cf6 JB |
1754 | /* We don't use vmf->pgoff since that has the fake offset */ |
1755 | page_offset = ((unsigned long)vmf->virtual_address - vma->vm_start) >> | |
1756 | PAGE_SHIFT; | |
1757 | ||
d9bc7e9f CW |
1758 | ret = i915_mutex_lock_interruptible(dev); |
1759 | if (ret) | |
1760 | goto out; | |
a00b10c3 | 1761 | |
db53a302 CW |
1762 | trace_i915_gem_object_fault(obj, page_offset, true, write); |
1763 | ||
6e4930f6 CW |
1764 | /* Try to flush the object off the GPU first without holding the lock. |
1765 | * Upon reacquiring the lock, we will perform our sanity checks and then | |
1766 | * repeat the flush holding the lock in the normal manner to catch cases | |
1767 | * where we are gazumped. | |
1768 | */ | |
1769 | ret = i915_gem_object_wait_rendering__nonblocking(obj, NULL, !write); | |
1770 | if (ret) | |
1771 | goto unlock; | |
1772 | ||
eb119bd6 CW |
1773 | /* Access to snoopable pages through the GTT is incoherent. */ |
1774 | if (obj->cache_level != I915_CACHE_NONE && !HAS_LLC(dev)) { | |
ddeff6ee | 1775 | ret = -EFAULT; |
eb119bd6 CW |
1776 | goto unlock; |
1777 | } | |
1778 | ||
c5ad54cf | 1779 | /* Use a partial view if the object is bigger than the aperture. */ |
e7ded2d7 JL |
1780 | if (obj->base.size >= dev_priv->gtt.mappable_end && |
1781 | obj->tiling_mode == I915_TILING_NONE) { | |
c5ad54cf | 1782 | static const unsigned int chunk_size = 256; // 1 MiB |
e7ded2d7 | 1783 | |
c5ad54cf JL |
1784 | memset(&view, 0, sizeof(view)); |
1785 | view.type = I915_GGTT_VIEW_PARTIAL; | |
1786 | view.params.partial.offset = rounddown(page_offset, chunk_size); | |
1787 | view.params.partial.size = | |
1788 | min_t(unsigned int, | |
1789 | chunk_size, | |
1790 | (vma->vm_end - vma->vm_start)/PAGE_SIZE - | |
1791 | view.params.partial.offset); | |
1792 | } | |
1793 | ||
1794 | /* Now pin it into the GTT if needed */ | |
1795 | ret = i915_gem_object_ggtt_pin(obj, &view, 0, PIN_MAPPABLE); | |
c9839303 CW |
1796 | if (ret) |
1797 | goto unlock; | |
4a684a41 | 1798 | |
c9839303 CW |
1799 | ret = i915_gem_object_set_to_gtt_domain(obj, write); |
1800 | if (ret) | |
1801 | goto unpin; | |
74898d7e | 1802 | |
06d98131 | 1803 | ret = i915_gem_object_get_fence(obj); |
d9e86c0e | 1804 | if (ret) |
c9839303 | 1805 | goto unpin; |
7d1c4804 | 1806 | |
b90b91d8 | 1807 | /* Finally, remap it using the new GTT offset */ |
c5ad54cf JL |
1808 | pfn = dev_priv->gtt.mappable_base + |
1809 | i915_gem_obj_ggtt_offset_view(obj, &view); | |
f343c5f6 | 1810 | pfn >>= PAGE_SHIFT; |
de151cf6 | 1811 | |
c5ad54cf JL |
1812 | if (unlikely(view.type == I915_GGTT_VIEW_PARTIAL)) { |
1813 | /* Overriding existing pages in partial view does not cause | |
1814 | * us any trouble as TLBs are still valid because the fault | |
1815 | * is due to userspace losing part of the mapping or never | |
1816 | * having accessed it before (at this partials' range). | |
1817 | */ | |
1818 | unsigned long base = vma->vm_start + | |
1819 | (view.params.partial.offset << PAGE_SHIFT); | |
1820 | unsigned int i; | |
b90b91d8 | 1821 | |
c5ad54cf JL |
1822 | for (i = 0; i < view.params.partial.size; i++) { |
1823 | ret = vm_insert_pfn(vma, base + i * PAGE_SIZE, pfn + i); | |
b90b91d8 CW |
1824 | if (ret) |
1825 | break; | |
1826 | } | |
1827 | ||
1828 | obj->fault_mappable = true; | |
c5ad54cf JL |
1829 | } else { |
1830 | if (!obj->fault_mappable) { | |
1831 | unsigned long size = min_t(unsigned long, | |
1832 | vma->vm_end - vma->vm_start, | |
1833 | obj->base.size); | |
1834 | int i; | |
1835 | ||
1836 | for (i = 0; i < size >> PAGE_SHIFT; i++) { | |
1837 | ret = vm_insert_pfn(vma, | |
1838 | (unsigned long)vma->vm_start + i * PAGE_SIZE, | |
1839 | pfn + i); | |
1840 | if (ret) | |
1841 | break; | |
1842 | } | |
1843 | ||
1844 | obj->fault_mappable = true; | |
1845 | } else | |
1846 | ret = vm_insert_pfn(vma, | |
1847 | (unsigned long)vmf->virtual_address, | |
1848 | pfn + page_offset); | |
1849 | } | |
c9839303 | 1850 | unpin: |
c5ad54cf | 1851 | i915_gem_object_ggtt_unpin_view(obj, &view); |
c715089f | 1852 | unlock: |
de151cf6 | 1853 | mutex_unlock(&dev->struct_mutex); |
d9bc7e9f | 1854 | out: |
de151cf6 | 1855 | switch (ret) { |
d9bc7e9f | 1856 | case -EIO: |
2232f031 DV |
1857 | /* |
1858 | * We eat errors when the gpu is terminally wedged to avoid | |
1859 | * userspace unduly crashing (gl has no provisions for mmaps to | |
1860 | * fail). But any other -EIO isn't ours (e.g. swap in failure) | |
1861 | * and so needs to be reported. | |
1862 | */ | |
1863 | if (!i915_terminally_wedged(&dev_priv->gpu_error)) { | |
f65c9168 PZ |
1864 | ret = VM_FAULT_SIGBUS; |
1865 | break; | |
1866 | } | |
045e769a | 1867 | case -EAGAIN: |
571c608d DV |
1868 | /* |
1869 | * EAGAIN means the gpu is hung and we'll wait for the error | |
1870 | * handler to reset everything when re-faulting in | |
1871 | * i915_mutex_lock_interruptible. | |
d9bc7e9f | 1872 | */ |
c715089f CW |
1873 | case 0: |
1874 | case -ERESTARTSYS: | |
bed636ab | 1875 | case -EINTR: |
e79e0fe3 DR |
1876 | case -EBUSY: |
1877 | /* | |
1878 | * EBUSY is ok: this just means that another thread | |
1879 | * already did the job. | |
1880 | */ | |
f65c9168 PZ |
1881 | ret = VM_FAULT_NOPAGE; |
1882 | break; | |
de151cf6 | 1883 | case -ENOMEM: |
f65c9168 PZ |
1884 | ret = VM_FAULT_OOM; |
1885 | break; | |
a7c2e1aa | 1886 | case -ENOSPC: |
45d67817 | 1887 | case -EFAULT: |
f65c9168 PZ |
1888 | ret = VM_FAULT_SIGBUS; |
1889 | break; | |
de151cf6 | 1890 | default: |
a7c2e1aa | 1891 | WARN_ONCE(ret, "unhandled error in i915_gem_fault: %i\n", ret); |
f65c9168 PZ |
1892 | ret = VM_FAULT_SIGBUS; |
1893 | break; | |
de151cf6 | 1894 | } |
f65c9168 PZ |
1895 | |
1896 | intel_runtime_pm_put(dev_priv); | |
1897 | return ret; | |
de151cf6 JB |
1898 | } |
1899 | ||
901782b2 CW |
1900 | /** |
1901 | * i915_gem_release_mmap - remove physical page mappings | |
1902 | * @obj: obj in question | |
1903 | * | |
af901ca1 | 1904 | * Preserve the reservation of the mmapping with the DRM core code, but |
901782b2 CW |
1905 | * relinquish ownership of the pages back to the system. |
1906 | * | |
1907 | * It is vital that we remove the page mapping if we have mapped a tiled | |
1908 | * object through the GTT and then lose the fence register due to | |
1909 | * resource pressure. Similarly if the object has been moved out of the | |
1910 | * aperture, than pages mapped into userspace must be revoked. Removing the | |
1911 | * mapping will then trigger a page fault on the next user access, allowing | |
1912 | * fixup by i915_gem_fault(). | |
1913 | */ | |
d05ca301 | 1914 | void |
05394f39 | 1915 | i915_gem_release_mmap(struct drm_i915_gem_object *obj) |
901782b2 | 1916 | { |
6299f992 CW |
1917 | if (!obj->fault_mappable) |
1918 | return; | |
901782b2 | 1919 | |
6796cb16 DH |
1920 | drm_vma_node_unmap(&obj->base.vma_node, |
1921 | obj->base.dev->anon_inode->i_mapping); | |
6299f992 | 1922 | obj->fault_mappable = false; |
901782b2 CW |
1923 | } |
1924 | ||
eedd10f4 CW |
1925 | void |
1926 | i915_gem_release_all_mmaps(struct drm_i915_private *dev_priv) | |
1927 | { | |
1928 | struct drm_i915_gem_object *obj; | |
1929 | ||
1930 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) | |
1931 | i915_gem_release_mmap(obj); | |
1932 | } | |
1933 | ||
0fa87796 | 1934 | uint32_t |
e28f8711 | 1935 | i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode) |
92b88aeb | 1936 | { |
e28f8711 | 1937 | uint32_t gtt_size; |
92b88aeb CW |
1938 | |
1939 | if (INTEL_INFO(dev)->gen >= 4 || | |
e28f8711 CW |
1940 | tiling_mode == I915_TILING_NONE) |
1941 | return size; | |
92b88aeb CW |
1942 | |
1943 | /* Previous chips need a power-of-two fence region when tiling */ | |
1944 | if (INTEL_INFO(dev)->gen == 3) | |
e28f8711 | 1945 | gtt_size = 1024*1024; |
92b88aeb | 1946 | else |
e28f8711 | 1947 | gtt_size = 512*1024; |
92b88aeb | 1948 | |
e28f8711 CW |
1949 | while (gtt_size < size) |
1950 | gtt_size <<= 1; | |
92b88aeb | 1951 | |
e28f8711 | 1952 | return gtt_size; |
92b88aeb CW |
1953 | } |
1954 | ||
de151cf6 JB |
1955 | /** |
1956 | * i915_gem_get_gtt_alignment - return required GTT alignment for an object | |
1957 | * @obj: object to check | |
1958 | * | |
1959 | * Return the required GTT alignment for an object, taking into account | |
5e783301 | 1960 | * potential fence register mapping. |
de151cf6 | 1961 | */ |
d865110c ID |
1962 | uint32_t |
1963 | i915_gem_get_gtt_alignment(struct drm_device *dev, uint32_t size, | |
1964 | int tiling_mode, bool fenced) | |
de151cf6 | 1965 | { |
de151cf6 JB |
1966 | /* |
1967 | * Minimum alignment is 4k (GTT page size), but might be greater | |
1968 | * if a fence register is needed for the object. | |
1969 | */ | |
d865110c | 1970 | if (INTEL_INFO(dev)->gen >= 4 || (!fenced && IS_G33(dev)) || |
e28f8711 | 1971 | tiling_mode == I915_TILING_NONE) |
de151cf6 JB |
1972 | return 4096; |
1973 | ||
a00b10c3 CW |
1974 | /* |
1975 | * Previous chips need to be aligned to the size of the smallest | |
1976 | * fence register that can contain the object. | |
1977 | */ | |
e28f8711 | 1978 | return i915_gem_get_gtt_size(dev, size, tiling_mode); |
a00b10c3 CW |
1979 | } |
1980 | ||
d8cb5086 CW |
1981 | static int i915_gem_object_create_mmap_offset(struct drm_i915_gem_object *obj) |
1982 | { | |
1983 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; | |
1984 | int ret; | |
1985 | ||
0de23977 | 1986 | if (drm_vma_node_has_offset(&obj->base.vma_node)) |
d8cb5086 CW |
1987 | return 0; |
1988 | ||
da494d7c DV |
1989 | dev_priv->mm.shrinker_no_lock_stealing = true; |
1990 | ||
d8cb5086 CW |
1991 | ret = drm_gem_create_mmap_offset(&obj->base); |
1992 | if (ret != -ENOSPC) | |
da494d7c | 1993 | goto out; |
d8cb5086 CW |
1994 | |
1995 | /* Badly fragmented mmap space? The only way we can recover | |
1996 | * space is by destroying unwanted objects. We can't randomly release | |
1997 | * mmap_offsets as userspace expects them to be persistent for the | |
1998 | * lifetime of the objects. The closest we can is to release the | |
1999 | * offsets on purgeable objects by truncating it and marking it purged, | |
2000 | * which prevents userspace from ever using that object again. | |
2001 | */ | |
21ab4e74 CW |
2002 | i915_gem_shrink(dev_priv, |
2003 | obj->base.size >> PAGE_SHIFT, | |
2004 | I915_SHRINK_BOUND | | |
2005 | I915_SHRINK_UNBOUND | | |
2006 | I915_SHRINK_PURGEABLE); | |
d8cb5086 CW |
2007 | ret = drm_gem_create_mmap_offset(&obj->base); |
2008 | if (ret != -ENOSPC) | |
da494d7c | 2009 | goto out; |
d8cb5086 CW |
2010 | |
2011 | i915_gem_shrink_all(dev_priv); | |
da494d7c DV |
2012 | ret = drm_gem_create_mmap_offset(&obj->base); |
2013 | out: | |
2014 | dev_priv->mm.shrinker_no_lock_stealing = false; | |
2015 | ||
2016 | return ret; | |
d8cb5086 CW |
2017 | } |
2018 | ||
2019 | static void i915_gem_object_free_mmap_offset(struct drm_i915_gem_object *obj) | |
2020 | { | |
d8cb5086 CW |
2021 | drm_gem_free_mmap_offset(&obj->base); |
2022 | } | |
2023 | ||
da6b51d0 | 2024 | int |
ff72145b DA |
2025 | i915_gem_mmap_gtt(struct drm_file *file, |
2026 | struct drm_device *dev, | |
da6b51d0 | 2027 | uint32_t handle, |
ff72145b | 2028 | uint64_t *offset) |
de151cf6 | 2029 | { |
05394f39 | 2030 | struct drm_i915_gem_object *obj; |
de151cf6 JB |
2031 | int ret; |
2032 | ||
76c1dec1 | 2033 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 2034 | if (ret) |
76c1dec1 | 2035 | return ret; |
de151cf6 | 2036 | |
ff72145b | 2037 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle)); |
c8725226 | 2038 | if (&obj->base == NULL) { |
1d7cfea1 CW |
2039 | ret = -ENOENT; |
2040 | goto unlock; | |
2041 | } | |
de151cf6 | 2042 | |
05394f39 | 2043 | if (obj->madv != I915_MADV_WILLNEED) { |
bd9b6a4e | 2044 | DRM_DEBUG("Attempting to mmap a purgeable buffer\n"); |
8c99e57d | 2045 | ret = -EFAULT; |
1d7cfea1 | 2046 | goto out; |
ab18282d CW |
2047 | } |
2048 | ||
d8cb5086 CW |
2049 | ret = i915_gem_object_create_mmap_offset(obj); |
2050 | if (ret) | |
2051 | goto out; | |
de151cf6 | 2052 | |
0de23977 | 2053 | *offset = drm_vma_node_offset_addr(&obj->base.vma_node); |
de151cf6 | 2054 | |
1d7cfea1 | 2055 | out: |
05394f39 | 2056 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 2057 | unlock: |
de151cf6 | 2058 | mutex_unlock(&dev->struct_mutex); |
1d7cfea1 | 2059 | return ret; |
de151cf6 JB |
2060 | } |
2061 | ||
ff72145b DA |
2062 | /** |
2063 | * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing | |
2064 | * @dev: DRM device | |
2065 | * @data: GTT mapping ioctl data | |
2066 | * @file: GEM object info | |
2067 | * | |
2068 | * Simply returns the fake offset to userspace so it can mmap it. | |
2069 | * The mmap call will end up in drm_gem_mmap(), which will set things | |
2070 | * up so we can get faults in the handler above. | |
2071 | * | |
2072 | * The fault handler will take care of binding the object into the GTT | |
2073 | * (since it may have been evicted to make room for something), allocating | |
2074 | * a fence register, and mapping the appropriate aperture address into | |
2075 | * userspace. | |
2076 | */ | |
2077 | int | |
2078 | i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data, | |
2079 | struct drm_file *file) | |
2080 | { | |
2081 | struct drm_i915_gem_mmap_gtt *args = data; | |
2082 | ||
da6b51d0 | 2083 | return i915_gem_mmap_gtt(file, dev, args->handle, &args->offset); |
ff72145b DA |
2084 | } |
2085 | ||
225067ee DV |
2086 | /* Immediately discard the backing storage */ |
2087 | static void | |
2088 | i915_gem_object_truncate(struct drm_i915_gem_object *obj) | |
e5281ccd | 2089 | { |
4d6294bf | 2090 | i915_gem_object_free_mmap_offset(obj); |
1286ff73 | 2091 | |
4d6294bf CW |
2092 | if (obj->base.filp == NULL) |
2093 | return; | |
e5281ccd | 2094 | |
225067ee DV |
2095 | /* Our goal here is to return as much of the memory as |
2096 | * is possible back to the system as we are called from OOM. | |
2097 | * To do this we must instruct the shmfs to drop all of its | |
2098 | * backing pages, *now*. | |
2099 | */ | |
5537252b | 2100 | shmem_truncate_range(file_inode(obj->base.filp), 0, (loff_t)-1); |
225067ee DV |
2101 | obj->madv = __I915_MADV_PURGED; |
2102 | } | |
e5281ccd | 2103 | |
5537252b CW |
2104 | /* Try to discard unwanted pages */ |
2105 | static void | |
2106 | i915_gem_object_invalidate(struct drm_i915_gem_object *obj) | |
225067ee | 2107 | { |
5537252b CW |
2108 | struct address_space *mapping; |
2109 | ||
2110 | switch (obj->madv) { | |
2111 | case I915_MADV_DONTNEED: | |
2112 | i915_gem_object_truncate(obj); | |
2113 | case __I915_MADV_PURGED: | |
2114 | return; | |
2115 | } | |
2116 | ||
2117 | if (obj->base.filp == NULL) | |
2118 | return; | |
2119 | ||
2120 | mapping = file_inode(obj->base.filp)->i_mapping, | |
2121 | invalidate_mapping_pages(mapping, 0, (loff_t)-1); | |
e5281ccd CW |
2122 | } |
2123 | ||
5cdf5881 | 2124 | static void |
05394f39 | 2125 | i915_gem_object_put_pages_gtt(struct drm_i915_gem_object *obj) |
673a394b | 2126 | { |
90797e6d ID |
2127 | struct sg_page_iter sg_iter; |
2128 | int ret; | |
1286ff73 | 2129 | |
05394f39 | 2130 | BUG_ON(obj->madv == __I915_MADV_PURGED); |
673a394b | 2131 | |
6c085a72 CW |
2132 | ret = i915_gem_object_set_to_cpu_domain(obj, true); |
2133 | if (ret) { | |
2134 | /* In the event of a disaster, abandon all caches and | |
2135 | * hope for the best. | |
2136 | */ | |
2137 | WARN_ON(ret != -EIO); | |
2c22569b | 2138 | i915_gem_clflush_object(obj, true); |
6c085a72 CW |
2139 | obj->base.read_domains = obj->base.write_domain = I915_GEM_DOMAIN_CPU; |
2140 | } | |
2141 | ||
6dacfd2f | 2142 | if (i915_gem_object_needs_bit17_swizzle(obj)) |
280b713b EA |
2143 | i915_gem_object_save_bit_17_swizzle(obj); |
2144 | ||
05394f39 CW |
2145 | if (obj->madv == I915_MADV_DONTNEED) |
2146 | obj->dirty = 0; | |
3ef94daa | 2147 | |
90797e6d | 2148 | for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, 0) { |
2db76d7c | 2149 | struct page *page = sg_page_iter_page(&sg_iter); |
9da3da66 | 2150 | |
05394f39 | 2151 | if (obj->dirty) |
9da3da66 | 2152 | set_page_dirty(page); |
3ef94daa | 2153 | |
05394f39 | 2154 | if (obj->madv == I915_MADV_WILLNEED) |
9da3da66 | 2155 | mark_page_accessed(page); |
3ef94daa | 2156 | |
9da3da66 | 2157 | page_cache_release(page); |
3ef94daa | 2158 | } |
05394f39 | 2159 | obj->dirty = 0; |
673a394b | 2160 | |
9da3da66 CW |
2161 | sg_free_table(obj->pages); |
2162 | kfree(obj->pages); | |
37e680a1 | 2163 | } |
6c085a72 | 2164 | |
dd624afd | 2165 | int |
37e680a1 CW |
2166 | i915_gem_object_put_pages(struct drm_i915_gem_object *obj) |
2167 | { | |
2168 | const struct drm_i915_gem_object_ops *ops = obj->ops; | |
2169 | ||
2f745ad3 | 2170 | if (obj->pages == NULL) |
37e680a1 CW |
2171 | return 0; |
2172 | ||
a5570178 CW |
2173 | if (obj->pages_pin_count) |
2174 | return -EBUSY; | |
2175 | ||
9843877d | 2176 | BUG_ON(i915_gem_obj_bound_any(obj)); |
3e123027 | 2177 | |
a2165e31 CW |
2178 | /* ->put_pages might need to allocate memory for the bit17 swizzle |
2179 | * array, hence protect them from being reaped by removing them from gtt | |
2180 | * lists early. */ | |
35c20a60 | 2181 | list_del(&obj->global_list); |
a2165e31 | 2182 | |
37e680a1 | 2183 | ops->put_pages(obj); |
05394f39 | 2184 | obj->pages = NULL; |
37e680a1 | 2185 | |
5537252b | 2186 | i915_gem_object_invalidate(obj); |
6c085a72 CW |
2187 | |
2188 | return 0; | |
2189 | } | |
2190 | ||
37e680a1 | 2191 | static int |
6c085a72 | 2192 | i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj) |
e5281ccd | 2193 | { |
6c085a72 | 2194 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
e5281ccd CW |
2195 | int page_count, i; |
2196 | struct address_space *mapping; | |
9da3da66 CW |
2197 | struct sg_table *st; |
2198 | struct scatterlist *sg; | |
90797e6d | 2199 | struct sg_page_iter sg_iter; |
e5281ccd | 2200 | struct page *page; |
90797e6d | 2201 | unsigned long last_pfn = 0; /* suppress gcc warning */ |
6c085a72 | 2202 | gfp_t gfp; |
e5281ccd | 2203 | |
6c085a72 CW |
2204 | /* Assert that the object is not currently in any GPU domain. As it |
2205 | * wasn't in the GTT, there shouldn't be any way it could have been in | |
2206 | * a GPU cache | |
2207 | */ | |
2208 | BUG_ON(obj->base.read_domains & I915_GEM_GPU_DOMAINS); | |
2209 | BUG_ON(obj->base.write_domain & I915_GEM_GPU_DOMAINS); | |
2210 | ||
9da3da66 CW |
2211 | st = kmalloc(sizeof(*st), GFP_KERNEL); |
2212 | if (st == NULL) | |
2213 | return -ENOMEM; | |
2214 | ||
05394f39 | 2215 | page_count = obj->base.size / PAGE_SIZE; |
9da3da66 | 2216 | if (sg_alloc_table(st, page_count, GFP_KERNEL)) { |
9da3da66 | 2217 | kfree(st); |
e5281ccd | 2218 | return -ENOMEM; |
9da3da66 | 2219 | } |
e5281ccd | 2220 | |
9da3da66 CW |
2221 | /* Get the list of pages out of our struct file. They'll be pinned |
2222 | * at this point until we release them. | |
2223 | * | |
2224 | * Fail silently without starting the shrinker | |
2225 | */ | |
496ad9aa | 2226 | mapping = file_inode(obj->base.filp)->i_mapping; |
6c085a72 | 2227 | gfp = mapping_gfp_mask(mapping); |
caf49191 | 2228 | gfp |= __GFP_NORETRY | __GFP_NOWARN | __GFP_NO_KSWAPD; |
6c085a72 | 2229 | gfp &= ~(__GFP_IO | __GFP_WAIT); |
90797e6d ID |
2230 | sg = st->sgl; |
2231 | st->nents = 0; | |
2232 | for (i = 0; i < page_count; i++) { | |
6c085a72 CW |
2233 | page = shmem_read_mapping_page_gfp(mapping, i, gfp); |
2234 | if (IS_ERR(page)) { | |
21ab4e74 CW |
2235 | i915_gem_shrink(dev_priv, |
2236 | page_count, | |
2237 | I915_SHRINK_BOUND | | |
2238 | I915_SHRINK_UNBOUND | | |
2239 | I915_SHRINK_PURGEABLE); | |
6c085a72 CW |
2240 | page = shmem_read_mapping_page_gfp(mapping, i, gfp); |
2241 | } | |
2242 | if (IS_ERR(page)) { | |
2243 | /* We've tried hard to allocate the memory by reaping | |
2244 | * our own buffer, now let the real VM do its job and | |
2245 | * go down in flames if truly OOM. | |
2246 | */ | |
6c085a72 | 2247 | i915_gem_shrink_all(dev_priv); |
f461d1be | 2248 | page = shmem_read_mapping_page(mapping, i); |
6c085a72 CW |
2249 | if (IS_ERR(page)) |
2250 | goto err_pages; | |
6c085a72 | 2251 | } |
426729dc KRW |
2252 | #ifdef CONFIG_SWIOTLB |
2253 | if (swiotlb_nr_tbl()) { | |
2254 | st->nents++; | |
2255 | sg_set_page(sg, page, PAGE_SIZE, 0); | |
2256 | sg = sg_next(sg); | |
2257 | continue; | |
2258 | } | |
2259 | #endif | |
90797e6d ID |
2260 | if (!i || page_to_pfn(page) != last_pfn + 1) { |
2261 | if (i) | |
2262 | sg = sg_next(sg); | |
2263 | st->nents++; | |
2264 | sg_set_page(sg, page, PAGE_SIZE, 0); | |
2265 | } else { | |
2266 | sg->length += PAGE_SIZE; | |
2267 | } | |
2268 | last_pfn = page_to_pfn(page); | |
3bbbe706 DV |
2269 | |
2270 | /* Check that the i965g/gm workaround works. */ | |
2271 | WARN_ON((gfp & __GFP_DMA32) && (last_pfn >= 0x00100000UL)); | |
e5281ccd | 2272 | } |
426729dc KRW |
2273 | #ifdef CONFIG_SWIOTLB |
2274 | if (!swiotlb_nr_tbl()) | |
2275 | #endif | |
2276 | sg_mark_end(sg); | |
74ce6b6c CW |
2277 | obj->pages = st; |
2278 | ||
6dacfd2f | 2279 | if (i915_gem_object_needs_bit17_swizzle(obj)) |
e5281ccd CW |
2280 | i915_gem_object_do_bit_17_swizzle(obj); |
2281 | ||
656bfa3a DV |
2282 | if (obj->tiling_mode != I915_TILING_NONE && |
2283 | dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES) | |
2284 | i915_gem_object_pin_pages(obj); | |
2285 | ||
e5281ccd CW |
2286 | return 0; |
2287 | ||
2288 | err_pages: | |
90797e6d ID |
2289 | sg_mark_end(sg); |
2290 | for_each_sg_page(st->sgl, &sg_iter, st->nents, 0) | |
2db76d7c | 2291 | page_cache_release(sg_page_iter_page(&sg_iter)); |
9da3da66 CW |
2292 | sg_free_table(st); |
2293 | kfree(st); | |
0820baf3 CW |
2294 | |
2295 | /* shmemfs first checks if there is enough memory to allocate the page | |
2296 | * and reports ENOSPC should there be insufficient, along with the usual | |
2297 | * ENOMEM for a genuine allocation failure. | |
2298 | * | |
2299 | * We use ENOSPC in our driver to mean that we have run out of aperture | |
2300 | * space and so want to translate the error from shmemfs back to our | |
2301 | * usual understanding of ENOMEM. | |
2302 | */ | |
2303 | if (PTR_ERR(page) == -ENOSPC) | |
2304 | return -ENOMEM; | |
2305 | else | |
2306 | return PTR_ERR(page); | |
673a394b EA |
2307 | } |
2308 | ||
37e680a1 CW |
2309 | /* Ensure that the associated pages are gathered from the backing storage |
2310 | * and pinned into our object. i915_gem_object_get_pages() may be called | |
2311 | * multiple times before they are released by a single call to | |
2312 | * i915_gem_object_put_pages() - once the pages are no longer referenced | |
2313 | * either as a result of memory pressure (reaping pages under the shrinker) | |
2314 | * or as the object is itself released. | |
2315 | */ | |
2316 | int | |
2317 | i915_gem_object_get_pages(struct drm_i915_gem_object *obj) | |
2318 | { | |
2319 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; | |
2320 | const struct drm_i915_gem_object_ops *ops = obj->ops; | |
2321 | int ret; | |
2322 | ||
2f745ad3 | 2323 | if (obj->pages) |
37e680a1 CW |
2324 | return 0; |
2325 | ||
43e28f09 | 2326 | if (obj->madv != I915_MADV_WILLNEED) { |
bd9b6a4e | 2327 | DRM_DEBUG("Attempting to obtain a purgeable object\n"); |
8c99e57d | 2328 | return -EFAULT; |
43e28f09 CW |
2329 | } |
2330 | ||
a5570178 CW |
2331 | BUG_ON(obj->pages_pin_count); |
2332 | ||
37e680a1 CW |
2333 | ret = ops->get_pages(obj); |
2334 | if (ret) | |
2335 | return ret; | |
2336 | ||
35c20a60 | 2337 | list_add_tail(&obj->global_list, &dev_priv->mm.unbound_list); |
ee286370 CW |
2338 | |
2339 | obj->get_page.sg = obj->pages->sgl; | |
2340 | obj->get_page.last = 0; | |
2341 | ||
37e680a1 | 2342 | return 0; |
673a394b EA |
2343 | } |
2344 | ||
b4716185 CW |
2345 | void i915_vma_move_to_active(struct i915_vma *vma, |
2346 | struct intel_engine_cs *ring) | |
673a394b | 2347 | { |
b4716185 | 2348 | struct drm_i915_gem_object *obj = vma->obj; |
673a394b EA |
2349 | |
2350 | /* Add a reference if we're newly entering the active list. */ | |
b4716185 | 2351 | if (obj->active == 0) |
05394f39 | 2352 | drm_gem_object_reference(&obj->base); |
b4716185 | 2353 | obj->active |= intel_ring_flag(ring); |
e35a41de | 2354 | |
b4716185 CW |
2355 | list_move_tail(&obj->ring_list[ring->id], &ring->active_list); |
2356 | i915_gem_request_assign(&obj->last_read_req[ring->id], | |
2357 | intel_ring_get_request(ring)); | |
caea7476 | 2358 | |
b4716185 | 2359 | list_move_tail(&vma->mm_list, &vma->vm->active_list); |
caea7476 CW |
2360 | } |
2361 | ||
b4716185 CW |
2362 | static void |
2363 | i915_gem_object_retire__write(struct drm_i915_gem_object *obj) | |
e2d05a8b | 2364 | { |
b4716185 CW |
2365 | RQ_BUG_ON(obj->last_write_req == NULL); |
2366 | RQ_BUG_ON(!(obj->active & intel_ring_flag(obj->last_write_req->ring))); | |
2367 | ||
2368 | i915_gem_request_assign(&obj->last_write_req, NULL); | |
2369 | intel_fb_obj_flush(obj, true); | |
e2d05a8b BW |
2370 | } |
2371 | ||
caea7476 | 2372 | static void |
b4716185 | 2373 | i915_gem_object_retire__read(struct drm_i915_gem_object *obj, int ring) |
ce44b0ea | 2374 | { |
feb822cf | 2375 | struct i915_vma *vma; |
ce44b0ea | 2376 | |
b4716185 CW |
2377 | RQ_BUG_ON(obj->last_read_req[ring] == NULL); |
2378 | RQ_BUG_ON(!(obj->active & (1 << ring))); | |
2379 | ||
2380 | list_del_init(&obj->ring_list[ring]); | |
2381 | i915_gem_request_assign(&obj->last_read_req[ring], NULL); | |
2382 | ||
2383 | if (obj->last_write_req && obj->last_write_req->ring->id == ring) | |
2384 | i915_gem_object_retire__write(obj); | |
2385 | ||
2386 | obj->active &= ~(1 << ring); | |
2387 | if (obj->active) | |
2388 | return; | |
caea7476 | 2389 | |
fe14d5f4 TU |
2390 | list_for_each_entry(vma, &obj->vma_list, vma_link) { |
2391 | if (!list_empty(&vma->mm_list)) | |
2392 | list_move_tail(&vma->mm_list, &vma->vm->inactive_list); | |
feb822cf | 2393 | } |
caea7476 | 2394 | |
97b2a6a1 | 2395 | i915_gem_request_assign(&obj->last_fenced_req, NULL); |
caea7476 | 2396 | drm_gem_object_unreference(&obj->base); |
c8725f3d CW |
2397 | } |
2398 | ||
9d773091 | 2399 | static int |
fca26bb4 | 2400 | i915_gem_init_seqno(struct drm_device *dev, u32 seqno) |
53d227f2 | 2401 | { |
9d773091 | 2402 | struct drm_i915_private *dev_priv = dev->dev_private; |
a4872ba6 | 2403 | struct intel_engine_cs *ring; |
9d773091 | 2404 | int ret, i, j; |
53d227f2 | 2405 | |
107f27a5 | 2406 | /* Carefully retire all requests without writing to the rings */ |
9d773091 | 2407 | for_each_ring(ring, dev_priv, i) { |
107f27a5 CW |
2408 | ret = intel_ring_idle(ring); |
2409 | if (ret) | |
2410 | return ret; | |
9d773091 | 2411 | } |
9d773091 | 2412 | i915_gem_retire_requests(dev); |
107f27a5 CW |
2413 | |
2414 | /* Finally reset hw state */ | |
9d773091 | 2415 | for_each_ring(ring, dev_priv, i) { |
fca26bb4 | 2416 | intel_ring_init_seqno(ring, seqno); |
498d2ac1 | 2417 | |
ebc348b2 BW |
2418 | for (j = 0; j < ARRAY_SIZE(ring->semaphore.sync_seqno); j++) |
2419 | ring->semaphore.sync_seqno[j] = 0; | |
9d773091 | 2420 | } |
53d227f2 | 2421 | |
9d773091 | 2422 | return 0; |
53d227f2 DV |
2423 | } |
2424 | ||
fca26bb4 MK |
2425 | int i915_gem_set_seqno(struct drm_device *dev, u32 seqno) |
2426 | { | |
2427 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2428 | int ret; | |
2429 | ||
2430 | if (seqno == 0) | |
2431 | return -EINVAL; | |
2432 | ||
2433 | /* HWS page needs to be set less than what we | |
2434 | * will inject to ring | |
2435 | */ | |
2436 | ret = i915_gem_init_seqno(dev, seqno - 1); | |
2437 | if (ret) | |
2438 | return ret; | |
2439 | ||
2440 | /* Carefully set the last_seqno value so that wrap | |
2441 | * detection still works | |
2442 | */ | |
2443 | dev_priv->next_seqno = seqno; | |
2444 | dev_priv->last_seqno = seqno - 1; | |
2445 | if (dev_priv->last_seqno == 0) | |
2446 | dev_priv->last_seqno--; | |
2447 | ||
2448 | return 0; | |
2449 | } | |
2450 | ||
9d773091 CW |
2451 | int |
2452 | i915_gem_get_seqno(struct drm_device *dev, u32 *seqno) | |
53d227f2 | 2453 | { |
9d773091 CW |
2454 | struct drm_i915_private *dev_priv = dev->dev_private; |
2455 | ||
2456 | /* reserve 0 for non-seqno */ | |
2457 | if (dev_priv->next_seqno == 0) { | |
fca26bb4 | 2458 | int ret = i915_gem_init_seqno(dev, 0); |
9d773091 CW |
2459 | if (ret) |
2460 | return ret; | |
53d227f2 | 2461 | |
9d773091 CW |
2462 | dev_priv->next_seqno = 1; |
2463 | } | |
53d227f2 | 2464 | |
f72b3435 | 2465 | *seqno = dev_priv->last_seqno = dev_priv->next_seqno++; |
9d773091 | 2466 | return 0; |
53d227f2 DV |
2467 | } |
2468 | ||
a4872ba6 | 2469 | int __i915_add_request(struct intel_engine_cs *ring, |
0025c077 | 2470 | struct drm_file *file, |
9400ae5c | 2471 | struct drm_i915_gem_object *obj) |
673a394b | 2472 | { |
3e31c6c0 | 2473 | struct drm_i915_private *dev_priv = ring->dev->dev_private; |
acb868d3 | 2474 | struct drm_i915_gem_request *request; |
48e29f55 | 2475 | struct intel_ringbuffer *ringbuf; |
6d3d8274 | 2476 | u32 request_start; |
3cce469c CW |
2477 | int ret; |
2478 | ||
6259cead | 2479 | request = ring->outstanding_lazy_request; |
48e29f55 OM |
2480 | if (WARN_ON(request == NULL)) |
2481 | return -ENOMEM; | |
2482 | ||
2483 | if (i915.enable_execlists) { | |
21076372 | 2484 | ringbuf = request->ctx->engine[ring->id].ringbuf; |
48e29f55 OM |
2485 | } else |
2486 | ringbuf = ring->buffer; | |
2487 | ||
2488 | request_start = intel_ring_get_tail(ringbuf); | |
cc889e0f DV |
2489 | /* |
2490 | * Emit any outstanding flushes - execbuf can fail to emit the flush | |
2491 | * after having emitted the batchbuffer command. Hence we need to fix | |
2492 | * things up similar to emitting the lazy request. The difference here | |
2493 | * is that the flush _must_ happen before the next request, no matter | |
2494 | * what. | |
2495 | */ | |
48e29f55 | 2496 | if (i915.enable_execlists) { |
21076372 | 2497 | ret = logical_ring_flush_all_caches(ringbuf, request->ctx); |
48e29f55 OM |
2498 | if (ret) |
2499 | return ret; | |
2500 | } else { | |
2501 | ret = intel_ring_flush_all_caches(ring); | |
2502 | if (ret) | |
2503 | return ret; | |
2504 | } | |
cc889e0f | 2505 | |
a71d8d94 CW |
2506 | /* Record the position of the start of the request so that |
2507 | * should we detect the updated seqno part-way through the | |
2508 | * GPU processing the request, we never over-estimate the | |
2509 | * position of the head. | |
2510 | */ | |
6d3d8274 | 2511 | request->postfix = intel_ring_get_tail(ringbuf); |
a71d8d94 | 2512 | |
48e29f55 | 2513 | if (i915.enable_execlists) { |
72f95afa | 2514 | ret = ring->emit_request(ringbuf, request); |
48e29f55 OM |
2515 | if (ret) |
2516 | return ret; | |
2517 | } else { | |
2518 | ret = ring->add_request(ring); | |
2519 | if (ret) | |
2520 | return ret; | |
53292cdb MT |
2521 | |
2522 | request->tail = intel_ring_get_tail(ringbuf); | |
48e29f55 | 2523 | } |
673a394b | 2524 | |
7d736f4f | 2525 | request->head = request_start; |
7d736f4f MK |
2526 | |
2527 | /* Whilst this request exists, batch_obj will be on the | |
2528 | * active_list, and so will hold the active reference. Only when this | |
2529 | * request is retired will the the batch_obj be moved onto the | |
2530 | * inactive_list and lose its active reference. Hence we do not need | |
2531 | * to explicitly hold another reference here. | |
2532 | */ | |
9a7e0c2a | 2533 | request->batch_obj = obj; |
0e50e96b | 2534 | |
48e29f55 OM |
2535 | if (!i915.enable_execlists) { |
2536 | /* Hold a reference to the current context so that we can inspect | |
2537 | * it later in case a hangcheck error event fires. | |
2538 | */ | |
2539 | request->ctx = ring->last_context; | |
2540 | if (request->ctx) | |
2541 | i915_gem_context_reference(request->ctx); | |
2542 | } | |
0e50e96b | 2543 | |
673a394b | 2544 | request->emitted_jiffies = jiffies; |
852835f3 | 2545 | list_add_tail(&request->list, &ring->request_list); |
3bb73aba | 2546 | request->file_priv = NULL; |
852835f3 | 2547 | |
db53a302 CW |
2548 | if (file) { |
2549 | struct drm_i915_file_private *file_priv = file->driver_priv; | |
2550 | ||
1c25595f | 2551 | spin_lock(&file_priv->mm.lock); |
f787a5f5 | 2552 | request->file_priv = file_priv; |
b962442e | 2553 | list_add_tail(&request->client_list, |
f787a5f5 | 2554 | &file_priv->mm.request_list); |
1c25595f | 2555 | spin_unlock(&file_priv->mm.lock); |
071c92de MK |
2556 | |
2557 | request->pid = get_pid(task_pid(current)); | |
b962442e | 2558 | } |
673a394b | 2559 | |
74328ee5 | 2560 | trace_i915_gem_request_add(request); |
6259cead | 2561 | ring->outstanding_lazy_request = NULL; |
db53a302 | 2562 | |
87255483 | 2563 | i915_queue_hangcheck(ring->dev); |
10cd45b6 | 2564 | |
87255483 DV |
2565 | queue_delayed_work(dev_priv->wq, |
2566 | &dev_priv->mm.retire_work, | |
2567 | round_jiffies_up_relative(HZ)); | |
2568 | intel_mark_busy(dev_priv->dev); | |
cc889e0f | 2569 | |
3cce469c | 2570 | return 0; |
673a394b EA |
2571 | } |
2572 | ||
939fd762 | 2573 | static bool i915_context_is_banned(struct drm_i915_private *dev_priv, |
273497e5 | 2574 | const struct intel_context *ctx) |
be62acb4 | 2575 | { |
44e2c070 | 2576 | unsigned long elapsed; |
be62acb4 | 2577 | |
44e2c070 MK |
2578 | elapsed = get_seconds() - ctx->hang_stats.guilty_ts; |
2579 | ||
2580 | if (ctx->hang_stats.banned) | |
be62acb4 MK |
2581 | return true; |
2582 | ||
676fa572 CW |
2583 | if (ctx->hang_stats.ban_period_seconds && |
2584 | elapsed <= ctx->hang_stats.ban_period_seconds) { | |
ccc7bed0 | 2585 | if (!i915_gem_context_is_default(ctx)) { |
3fac8978 | 2586 | DRM_DEBUG("context hanging too fast, banning!\n"); |
ccc7bed0 | 2587 | return true; |
88b4aa87 MK |
2588 | } else if (i915_stop_ring_allow_ban(dev_priv)) { |
2589 | if (i915_stop_ring_allow_warn(dev_priv)) | |
2590 | DRM_ERROR("gpu hanging too fast, banning!\n"); | |
ccc7bed0 | 2591 | return true; |
3fac8978 | 2592 | } |
be62acb4 MK |
2593 | } |
2594 | ||
2595 | return false; | |
2596 | } | |
2597 | ||
939fd762 | 2598 | static void i915_set_reset_status(struct drm_i915_private *dev_priv, |
273497e5 | 2599 | struct intel_context *ctx, |
b6b0fac0 | 2600 | const bool guilty) |
aa60c664 | 2601 | { |
44e2c070 MK |
2602 | struct i915_ctx_hang_stats *hs; |
2603 | ||
2604 | if (WARN_ON(!ctx)) | |
2605 | return; | |
aa60c664 | 2606 | |
44e2c070 MK |
2607 | hs = &ctx->hang_stats; |
2608 | ||
2609 | if (guilty) { | |
939fd762 | 2610 | hs->banned = i915_context_is_banned(dev_priv, ctx); |
44e2c070 MK |
2611 | hs->batch_active++; |
2612 | hs->guilty_ts = get_seconds(); | |
2613 | } else { | |
2614 | hs->batch_pending++; | |
aa60c664 MK |
2615 | } |
2616 | } | |
2617 | ||
abfe262a JH |
2618 | void i915_gem_request_free(struct kref *req_ref) |
2619 | { | |
2620 | struct drm_i915_gem_request *req = container_of(req_ref, | |
2621 | typeof(*req), ref); | |
2622 | struct intel_context *ctx = req->ctx; | |
2623 | ||
0794aed3 TD |
2624 | if (ctx) { |
2625 | if (i915.enable_execlists) { | |
abfe262a | 2626 | struct intel_engine_cs *ring = req->ring; |
0e50e96b | 2627 | |
0794aed3 TD |
2628 | if (ctx != ring->default_context) |
2629 | intel_lr_context_unpin(ring, ctx); | |
2630 | } | |
abfe262a | 2631 | |
dcb4c12a OM |
2632 | i915_gem_context_unreference(ctx); |
2633 | } | |
abfe262a | 2634 | |
efab6d8d | 2635 | kmem_cache_free(req->i915->requests, req); |
0e50e96b MK |
2636 | } |
2637 | ||
6689cb2b JH |
2638 | int i915_gem_request_alloc(struct intel_engine_cs *ring, |
2639 | struct intel_context *ctx) | |
2640 | { | |
efab6d8d | 2641 | struct drm_i915_private *dev_priv = to_i915(ring->dev); |
eed29a5b | 2642 | struct drm_i915_gem_request *req; |
6689cb2b | 2643 | int ret; |
6689cb2b JH |
2644 | |
2645 | if (ring->outstanding_lazy_request) | |
2646 | return 0; | |
2647 | ||
eed29a5b DV |
2648 | req = kmem_cache_zalloc(dev_priv->requests, GFP_KERNEL); |
2649 | if (req == NULL) | |
6689cb2b JH |
2650 | return -ENOMEM; |
2651 | ||
eed29a5b DV |
2652 | kref_init(&req->ref); |
2653 | req->i915 = dev_priv; | |
efab6d8d | 2654 | |
eed29a5b | 2655 | ret = i915_gem_get_seqno(ring->dev, &req->seqno); |
9a0c1e27 CW |
2656 | if (ret) |
2657 | goto err; | |
6689cb2b | 2658 | |
eed29a5b | 2659 | req->ring = ring; |
6689cb2b JH |
2660 | |
2661 | if (i915.enable_execlists) | |
eed29a5b | 2662 | ret = intel_logical_ring_alloc_request_extras(req, ctx); |
6689cb2b | 2663 | else |
eed29a5b | 2664 | ret = intel_ring_alloc_request_extras(req); |
9a0c1e27 CW |
2665 | if (ret) |
2666 | goto err; | |
6689cb2b | 2667 | |
eed29a5b | 2668 | ring->outstanding_lazy_request = req; |
6689cb2b | 2669 | return 0; |
9a0c1e27 CW |
2670 | |
2671 | err: | |
2672 | kmem_cache_free(dev_priv->requests, req); | |
2673 | return ret; | |
0e50e96b MK |
2674 | } |
2675 | ||
8d9fc7fd | 2676 | struct drm_i915_gem_request * |
a4872ba6 | 2677 | i915_gem_find_active_request(struct intel_engine_cs *ring) |
9375e446 | 2678 | { |
4db080f9 CW |
2679 | struct drm_i915_gem_request *request; |
2680 | ||
2681 | list_for_each_entry(request, &ring->request_list, list) { | |
1b5a433a | 2682 | if (i915_gem_request_completed(request, false)) |
4db080f9 | 2683 | continue; |
aa60c664 | 2684 | |
b6b0fac0 | 2685 | return request; |
4db080f9 | 2686 | } |
b6b0fac0 MK |
2687 | |
2688 | return NULL; | |
2689 | } | |
2690 | ||
2691 | static void i915_gem_reset_ring_status(struct drm_i915_private *dev_priv, | |
a4872ba6 | 2692 | struct intel_engine_cs *ring) |
b6b0fac0 MK |
2693 | { |
2694 | struct drm_i915_gem_request *request; | |
2695 | bool ring_hung; | |
2696 | ||
8d9fc7fd | 2697 | request = i915_gem_find_active_request(ring); |
b6b0fac0 MK |
2698 | |
2699 | if (request == NULL) | |
2700 | return; | |
2701 | ||
2702 | ring_hung = ring->hangcheck.score >= HANGCHECK_SCORE_RING_HUNG; | |
2703 | ||
939fd762 | 2704 | i915_set_reset_status(dev_priv, request->ctx, ring_hung); |
b6b0fac0 MK |
2705 | |
2706 | list_for_each_entry_continue(request, &ring->request_list, list) | |
939fd762 | 2707 | i915_set_reset_status(dev_priv, request->ctx, false); |
4db080f9 | 2708 | } |
aa60c664 | 2709 | |
4db080f9 | 2710 | static void i915_gem_reset_ring_cleanup(struct drm_i915_private *dev_priv, |
a4872ba6 | 2711 | struct intel_engine_cs *ring) |
4db080f9 | 2712 | { |
dfaae392 | 2713 | while (!list_empty(&ring->active_list)) { |
05394f39 | 2714 | struct drm_i915_gem_object *obj; |
9375e446 | 2715 | |
05394f39 CW |
2716 | obj = list_first_entry(&ring->active_list, |
2717 | struct drm_i915_gem_object, | |
b4716185 | 2718 | ring_list[ring->id]); |
9375e446 | 2719 | |
b4716185 | 2720 | i915_gem_object_retire__read(obj, ring->id); |
673a394b | 2721 | } |
1d62beea | 2722 | |
dcb4c12a OM |
2723 | /* |
2724 | * Clear the execlists queue up before freeing the requests, as those | |
2725 | * are the ones that keep the context and ringbuffer backing objects | |
2726 | * pinned in place. | |
2727 | */ | |
2728 | while (!list_empty(&ring->execlist_queue)) { | |
6d3d8274 | 2729 | struct drm_i915_gem_request *submit_req; |
dcb4c12a OM |
2730 | |
2731 | submit_req = list_first_entry(&ring->execlist_queue, | |
6d3d8274 | 2732 | struct drm_i915_gem_request, |
dcb4c12a OM |
2733 | execlist_link); |
2734 | list_del(&submit_req->execlist_link); | |
1197b4f2 MK |
2735 | |
2736 | if (submit_req->ctx != ring->default_context) | |
2737 | intel_lr_context_unpin(ring, submit_req->ctx); | |
2738 | ||
b3a38998 | 2739 | i915_gem_request_unreference(submit_req); |
dcb4c12a OM |
2740 | } |
2741 | ||
1d62beea BW |
2742 | /* |
2743 | * We must free the requests after all the corresponding objects have | |
2744 | * been moved off active lists. Which is the same order as the normal | |
2745 | * retire_requests function does. This is important if object hold | |
2746 | * implicit references on things like e.g. ppgtt address spaces through | |
2747 | * the request. | |
2748 | */ | |
2749 | while (!list_empty(&ring->request_list)) { | |
2750 | struct drm_i915_gem_request *request; | |
2751 | ||
2752 | request = list_first_entry(&ring->request_list, | |
2753 | struct drm_i915_gem_request, | |
2754 | list); | |
2755 | ||
b4716185 | 2756 | i915_gem_request_retire(request); |
1d62beea | 2757 | } |
e3efda49 | 2758 | |
6259cead JH |
2759 | /* This may not have been flushed before the reset, so clean it now */ |
2760 | i915_gem_request_assign(&ring->outstanding_lazy_request, NULL); | |
673a394b EA |
2761 | } |
2762 | ||
19b2dbde | 2763 | void i915_gem_restore_fences(struct drm_device *dev) |
312817a3 CW |
2764 | { |
2765 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2766 | int i; | |
2767 | ||
4b9de737 | 2768 | for (i = 0; i < dev_priv->num_fence_regs; i++) { |
312817a3 | 2769 | struct drm_i915_fence_reg *reg = &dev_priv->fence_regs[i]; |
7d2cb39c | 2770 | |
94a335db DV |
2771 | /* |
2772 | * Commit delayed tiling changes if we have an object still | |
2773 | * attached to the fence, otherwise just clear the fence. | |
2774 | */ | |
2775 | if (reg->obj) { | |
2776 | i915_gem_object_update_fence(reg->obj, reg, | |
2777 | reg->obj->tiling_mode); | |
2778 | } else { | |
2779 | i915_gem_write_fence(dev, i, NULL); | |
2780 | } | |
312817a3 CW |
2781 | } |
2782 | } | |
2783 | ||
069efc1d | 2784 | void i915_gem_reset(struct drm_device *dev) |
673a394b | 2785 | { |
77f01230 | 2786 | struct drm_i915_private *dev_priv = dev->dev_private; |
a4872ba6 | 2787 | struct intel_engine_cs *ring; |
1ec14ad3 | 2788 | int i; |
673a394b | 2789 | |
4db080f9 CW |
2790 | /* |
2791 | * Before we free the objects from the requests, we need to inspect | |
2792 | * them for finding the guilty party. As the requests only borrow | |
2793 | * their reference to the objects, the inspection must be done first. | |
2794 | */ | |
2795 | for_each_ring(ring, dev_priv, i) | |
2796 | i915_gem_reset_ring_status(dev_priv, ring); | |
2797 | ||
b4519513 | 2798 | for_each_ring(ring, dev_priv, i) |
4db080f9 | 2799 | i915_gem_reset_ring_cleanup(dev_priv, ring); |
dfaae392 | 2800 | |
acce9ffa BW |
2801 | i915_gem_context_reset(dev); |
2802 | ||
19b2dbde | 2803 | i915_gem_restore_fences(dev); |
b4716185 CW |
2804 | |
2805 | WARN_ON(i915_verify_lists(dev)); | |
673a394b EA |
2806 | } |
2807 | ||
2808 | /** | |
2809 | * This function clears the request list as sequence numbers are passed. | |
2810 | */ | |
1cf0ba14 | 2811 | void |
a4872ba6 | 2812 | i915_gem_retire_requests_ring(struct intel_engine_cs *ring) |
673a394b | 2813 | { |
db53a302 | 2814 | WARN_ON(i915_verify_lists(ring->dev)); |
673a394b | 2815 | |
b4716185 CW |
2816 | if (list_empty(&ring->active_list)) |
2817 | return; | |
2818 | ||
832a3aad CW |
2819 | /* Retire requests first as we use it above for the early return. |
2820 | * If we retire requests last, we may use a later seqno and so clear | |
2821 | * the requests lists without clearing the active list, leading to | |
2822 | * confusion. | |
e9103038 | 2823 | */ |
852835f3 | 2824 | while (!list_empty(&ring->request_list)) { |
673a394b | 2825 | struct drm_i915_gem_request *request; |
673a394b | 2826 | |
852835f3 | 2827 | request = list_first_entry(&ring->request_list, |
673a394b EA |
2828 | struct drm_i915_gem_request, |
2829 | list); | |
673a394b | 2830 | |
1b5a433a | 2831 | if (!i915_gem_request_completed(request, true)) |
b84d5f0c CW |
2832 | break; |
2833 | ||
b4716185 | 2834 | i915_gem_request_retire(request); |
b84d5f0c | 2835 | } |
673a394b | 2836 | |
832a3aad CW |
2837 | /* Move any buffers on the active list that are no longer referenced |
2838 | * by the ringbuffer to the flushing/inactive lists as appropriate, | |
2839 | * before we free the context associated with the requests. | |
2840 | */ | |
2841 | while (!list_empty(&ring->active_list)) { | |
2842 | struct drm_i915_gem_object *obj; | |
2843 | ||
2844 | obj = list_first_entry(&ring->active_list, | |
2845 | struct drm_i915_gem_object, | |
b4716185 | 2846 | ring_list[ring->id]); |
832a3aad | 2847 | |
b4716185 | 2848 | if (!list_empty(&obj->last_read_req[ring->id]->list)) |
832a3aad CW |
2849 | break; |
2850 | ||
b4716185 | 2851 | i915_gem_object_retire__read(obj, ring->id); |
832a3aad CW |
2852 | } |
2853 | ||
581c26e8 JH |
2854 | if (unlikely(ring->trace_irq_req && |
2855 | i915_gem_request_completed(ring->trace_irq_req, true))) { | |
1ec14ad3 | 2856 | ring->irq_put(ring); |
581c26e8 | 2857 | i915_gem_request_assign(&ring->trace_irq_req, NULL); |
9d34e5db | 2858 | } |
23bc5982 | 2859 | |
db53a302 | 2860 | WARN_ON(i915_verify_lists(ring->dev)); |
673a394b EA |
2861 | } |
2862 | ||
b29c19b6 | 2863 | bool |
b09a1fec CW |
2864 | i915_gem_retire_requests(struct drm_device *dev) |
2865 | { | |
3e31c6c0 | 2866 | struct drm_i915_private *dev_priv = dev->dev_private; |
a4872ba6 | 2867 | struct intel_engine_cs *ring; |
b29c19b6 | 2868 | bool idle = true; |
1ec14ad3 | 2869 | int i; |
b09a1fec | 2870 | |
b29c19b6 | 2871 | for_each_ring(ring, dev_priv, i) { |
b4519513 | 2872 | i915_gem_retire_requests_ring(ring); |
b29c19b6 | 2873 | idle &= list_empty(&ring->request_list); |
c86ee3a9 TD |
2874 | if (i915.enable_execlists) { |
2875 | unsigned long flags; | |
2876 | ||
2877 | spin_lock_irqsave(&ring->execlist_lock, flags); | |
2878 | idle &= list_empty(&ring->execlist_queue); | |
2879 | spin_unlock_irqrestore(&ring->execlist_lock, flags); | |
2880 | ||
2881 | intel_execlists_retire_requests(ring); | |
2882 | } | |
b29c19b6 CW |
2883 | } |
2884 | ||
2885 | if (idle) | |
2886 | mod_delayed_work(dev_priv->wq, | |
2887 | &dev_priv->mm.idle_work, | |
2888 | msecs_to_jiffies(100)); | |
2889 | ||
2890 | return idle; | |
b09a1fec CW |
2891 | } |
2892 | ||
75ef9da2 | 2893 | static void |
673a394b EA |
2894 | i915_gem_retire_work_handler(struct work_struct *work) |
2895 | { | |
b29c19b6 CW |
2896 | struct drm_i915_private *dev_priv = |
2897 | container_of(work, typeof(*dev_priv), mm.retire_work.work); | |
2898 | struct drm_device *dev = dev_priv->dev; | |
0a58705b | 2899 | bool idle; |
673a394b | 2900 | |
891b48cf | 2901 | /* Come back later if the device is busy... */ |
b29c19b6 CW |
2902 | idle = false; |
2903 | if (mutex_trylock(&dev->struct_mutex)) { | |
2904 | idle = i915_gem_retire_requests(dev); | |
2905 | mutex_unlock(&dev->struct_mutex); | |
673a394b | 2906 | } |
b29c19b6 | 2907 | if (!idle) |
bcb45086 CW |
2908 | queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, |
2909 | round_jiffies_up_relative(HZ)); | |
b29c19b6 | 2910 | } |
0a58705b | 2911 | |
b29c19b6 CW |
2912 | static void |
2913 | i915_gem_idle_work_handler(struct work_struct *work) | |
2914 | { | |
2915 | struct drm_i915_private *dev_priv = | |
2916 | container_of(work, typeof(*dev_priv), mm.idle_work.work); | |
35c94185 | 2917 | struct drm_device *dev = dev_priv->dev; |
423795cb CW |
2918 | struct intel_engine_cs *ring; |
2919 | int i; | |
b29c19b6 | 2920 | |
423795cb CW |
2921 | for_each_ring(ring, dev_priv, i) |
2922 | if (!list_empty(&ring->request_list)) | |
2923 | return; | |
35c94185 CW |
2924 | |
2925 | intel_mark_idle(dev); | |
2926 | ||
2927 | if (mutex_trylock(&dev->struct_mutex)) { | |
2928 | struct intel_engine_cs *ring; | |
2929 | int i; | |
2930 | ||
2931 | for_each_ring(ring, dev_priv, i) | |
2932 | i915_gem_batch_pool_fini(&ring->batch_pool); | |
b29c19b6 | 2933 | |
35c94185 CW |
2934 | mutex_unlock(&dev->struct_mutex); |
2935 | } | |
673a394b EA |
2936 | } |
2937 | ||
30dfebf3 DV |
2938 | /** |
2939 | * Ensures that an object will eventually get non-busy by flushing any required | |
2940 | * write domains, emitting any outstanding lazy request and retiring and | |
2941 | * completed requests. | |
2942 | */ | |
2943 | static int | |
2944 | i915_gem_object_flush_active(struct drm_i915_gem_object *obj) | |
2945 | { | |
b4716185 CW |
2946 | int ret, i; |
2947 | ||
2948 | if (!obj->active) | |
2949 | return 0; | |
30dfebf3 | 2950 | |
b4716185 CW |
2951 | for (i = 0; i < I915_NUM_RINGS; i++) { |
2952 | struct drm_i915_gem_request *req; | |
41c52415 | 2953 | |
b4716185 CW |
2954 | req = obj->last_read_req[i]; |
2955 | if (req == NULL) | |
2956 | continue; | |
2957 | ||
2958 | if (list_empty(&req->list)) | |
2959 | goto retire; | |
2960 | ||
2961 | ret = i915_gem_check_olr(req); | |
30dfebf3 DV |
2962 | if (ret) |
2963 | return ret; | |
2964 | ||
b4716185 CW |
2965 | if (i915_gem_request_completed(req, true)) { |
2966 | __i915_gem_request_retire__upto(req); | |
2967 | retire: | |
2968 | i915_gem_object_retire__read(obj, i); | |
2969 | } | |
30dfebf3 DV |
2970 | } |
2971 | ||
2972 | return 0; | |
2973 | } | |
2974 | ||
23ba4fd0 BW |
2975 | /** |
2976 | * i915_gem_wait_ioctl - implements DRM_IOCTL_I915_GEM_WAIT | |
2977 | * @DRM_IOCTL_ARGS: standard ioctl arguments | |
2978 | * | |
2979 | * Returns 0 if successful, else an error is returned with the remaining time in | |
2980 | * the timeout parameter. | |
2981 | * -ETIME: object is still busy after timeout | |
2982 | * -ERESTARTSYS: signal interrupted the wait | |
2983 | * -ENONENT: object doesn't exist | |
2984 | * Also possible, but rare: | |
2985 | * -EAGAIN: GPU wedged | |
2986 | * -ENOMEM: damn | |
2987 | * -ENODEV: Internal IRQ fail | |
2988 | * -E?: The add request failed | |
2989 | * | |
2990 | * The wait ioctl with a timeout of 0 reimplements the busy ioctl. With any | |
2991 | * non-zero timeout parameter the wait ioctl will wait for the given number of | |
2992 | * nanoseconds on an object becoming unbusy. Since the wait itself does so | |
2993 | * without holding struct_mutex the object may become re-busied before this | |
2994 | * function completes. A similar but shorter * race condition exists in the busy | |
2995 | * ioctl | |
2996 | */ | |
2997 | int | |
2998 | i915_gem_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *file) | |
2999 | { | |
3e31c6c0 | 3000 | struct drm_i915_private *dev_priv = dev->dev_private; |
23ba4fd0 BW |
3001 | struct drm_i915_gem_wait *args = data; |
3002 | struct drm_i915_gem_object *obj; | |
b4716185 | 3003 | struct drm_i915_gem_request *req[I915_NUM_RINGS]; |
f69061be | 3004 | unsigned reset_counter; |
b4716185 CW |
3005 | int i, n = 0; |
3006 | int ret; | |
23ba4fd0 | 3007 | |
11b5d511 DV |
3008 | if (args->flags != 0) |
3009 | return -EINVAL; | |
3010 | ||
23ba4fd0 BW |
3011 | ret = i915_mutex_lock_interruptible(dev); |
3012 | if (ret) | |
3013 | return ret; | |
3014 | ||
3015 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->bo_handle)); | |
3016 | if (&obj->base == NULL) { | |
3017 | mutex_unlock(&dev->struct_mutex); | |
3018 | return -ENOENT; | |
3019 | } | |
3020 | ||
30dfebf3 DV |
3021 | /* Need to make sure the object gets inactive eventually. */ |
3022 | ret = i915_gem_object_flush_active(obj); | |
23ba4fd0 BW |
3023 | if (ret) |
3024 | goto out; | |
3025 | ||
b4716185 | 3026 | if (!obj->active) |
97b2a6a1 | 3027 | goto out; |
23ba4fd0 | 3028 | |
23ba4fd0 | 3029 | /* Do this after OLR check to make sure we make forward progress polling |
762e4583 | 3030 | * on this IOCTL with a timeout == 0 (like busy ioctl) |
23ba4fd0 | 3031 | */ |
762e4583 | 3032 | if (args->timeout_ns == 0) { |
23ba4fd0 BW |
3033 | ret = -ETIME; |
3034 | goto out; | |
3035 | } | |
3036 | ||
3037 | drm_gem_object_unreference(&obj->base); | |
f69061be | 3038 | reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter); |
b4716185 CW |
3039 | |
3040 | for (i = 0; i < I915_NUM_RINGS; i++) { | |
3041 | if (obj->last_read_req[i] == NULL) | |
3042 | continue; | |
3043 | ||
3044 | req[n++] = i915_gem_request_reference(obj->last_read_req[i]); | |
3045 | } | |
3046 | ||
23ba4fd0 BW |
3047 | mutex_unlock(&dev->struct_mutex); |
3048 | ||
b4716185 CW |
3049 | for (i = 0; i < n; i++) { |
3050 | if (ret == 0) | |
3051 | ret = __i915_wait_request(req[i], reset_counter, true, | |
3052 | args->timeout_ns > 0 ? &args->timeout_ns : NULL, | |
3053 | file->driver_priv); | |
3054 | i915_gem_request_unreference__unlocked(req[i]); | |
3055 | } | |
ff865885 | 3056 | return ret; |
23ba4fd0 BW |
3057 | |
3058 | out: | |
3059 | drm_gem_object_unreference(&obj->base); | |
3060 | mutex_unlock(&dev->struct_mutex); | |
3061 | return ret; | |
3062 | } | |
3063 | ||
b4716185 CW |
3064 | static int |
3065 | __i915_gem_object_sync(struct drm_i915_gem_object *obj, | |
3066 | struct intel_engine_cs *to, | |
3067 | struct drm_i915_gem_request *req) | |
3068 | { | |
3069 | struct intel_engine_cs *from; | |
3070 | int ret; | |
3071 | ||
3072 | from = i915_gem_request_get_ring(req); | |
3073 | if (to == from) | |
3074 | return 0; | |
3075 | ||
3076 | if (i915_gem_request_completed(req, true)) | |
3077 | return 0; | |
3078 | ||
3079 | ret = i915_gem_check_olr(req); | |
3080 | if (ret) | |
3081 | return ret; | |
3082 | ||
3083 | if (!i915_semaphore_is_enabled(obj->base.dev)) { | |
a6f766f3 | 3084 | struct drm_i915_private *i915 = to_i915(obj->base.dev); |
b4716185 | 3085 | ret = __i915_wait_request(req, |
a6f766f3 CW |
3086 | atomic_read(&i915->gpu_error.reset_counter), |
3087 | i915->mm.interruptible, | |
3088 | NULL, | |
3089 | &i915->rps.semaphores); | |
b4716185 CW |
3090 | if (ret) |
3091 | return ret; | |
3092 | ||
3093 | i915_gem_object_retire_request(obj, req); | |
3094 | } else { | |
3095 | int idx = intel_ring_sync_index(from, to); | |
3096 | u32 seqno = i915_gem_request_get_seqno(req); | |
3097 | ||
3098 | if (seqno <= from->semaphore.sync_seqno[idx]) | |
3099 | return 0; | |
3100 | ||
3101 | trace_i915_gem_ring_sync_to(from, to, req); | |
3102 | ret = to->semaphore.sync_to(to, from, seqno); | |
3103 | if (ret) | |
3104 | return ret; | |
3105 | ||
3106 | /* We use last_read_req because sync_to() | |
3107 | * might have just caused seqno wrap under | |
3108 | * the radar. | |
3109 | */ | |
3110 | from->semaphore.sync_seqno[idx] = | |
3111 | i915_gem_request_get_seqno(obj->last_read_req[from->id]); | |
3112 | } | |
3113 | ||
3114 | return 0; | |
3115 | } | |
3116 | ||
5816d648 BW |
3117 | /** |
3118 | * i915_gem_object_sync - sync an object to a ring. | |
3119 | * | |
3120 | * @obj: object which may be in use on another ring. | |
3121 | * @to: ring we wish to use the object on. May be NULL. | |
3122 | * | |
3123 | * This code is meant to abstract object synchronization with the GPU. | |
3124 | * Calling with NULL implies synchronizing the object with the CPU | |
b4716185 CW |
3125 | * rather than a particular GPU ring. Conceptually we serialise writes |
3126 | * between engines inside the GPU. We only allow on engine to write | |
3127 | * into a buffer at any time, but multiple readers. To ensure each has | |
3128 | * a coherent view of memory, we must: | |
3129 | * | |
3130 | * - If there is an outstanding write request to the object, the new | |
3131 | * request must wait for it to complete (either CPU or in hw, requests | |
3132 | * on the same ring will be naturally ordered). | |
3133 | * | |
3134 | * - If we are a write request (pending_write_domain is set), the new | |
3135 | * request must wait for outstanding read requests to complete. | |
5816d648 BW |
3136 | * |
3137 | * Returns 0 if successful, else propagates up the lower layer error. | |
3138 | */ | |
2911a35b BW |
3139 | int |
3140 | i915_gem_object_sync(struct drm_i915_gem_object *obj, | |
a4872ba6 | 3141 | struct intel_engine_cs *to) |
2911a35b | 3142 | { |
b4716185 CW |
3143 | const bool readonly = obj->base.pending_write_domain == 0; |
3144 | struct drm_i915_gem_request *req[I915_NUM_RINGS]; | |
3145 | int ret, i, n; | |
41c52415 | 3146 | |
b4716185 | 3147 | if (!obj->active) |
2911a35b BW |
3148 | return 0; |
3149 | ||
b4716185 CW |
3150 | if (to == NULL) |
3151 | return i915_gem_object_wait_rendering(obj, readonly); | |
2911a35b | 3152 | |
b4716185 CW |
3153 | n = 0; |
3154 | if (readonly) { | |
3155 | if (obj->last_write_req) | |
3156 | req[n++] = obj->last_write_req; | |
3157 | } else { | |
3158 | for (i = 0; i < I915_NUM_RINGS; i++) | |
3159 | if (obj->last_read_req[i]) | |
3160 | req[n++] = obj->last_read_req[i]; | |
3161 | } | |
3162 | for (i = 0; i < n; i++) { | |
3163 | ret = __i915_gem_object_sync(obj, to, req[i]); | |
3164 | if (ret) | |
3165 | return ret; | |
3166 | } | |
2911a35b | 3167 | |
b4716185 | 3168 | return 0; |
2911a35b BW |
3169 | } |
3170 | ||
b5ffc9bc CW |
3171 | static void i915_gem_object_finish_gtt(struct drm_i915_gem_object *obj) |
3172 | { | |
3173 | u32 old_write_domain, old_read_domains; | |
3174 | ||
b5ffc9bc CW |
3175 | /* Force a pagefault for domain tracking on next user access */ |
3176 | i915_gem_release_mmap(obj); | |
3177 | ||
b97c3d9c KP |
3178 | if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0) |
3179 | return; | |
3180 | ||
97c809fd CW |
3181 | /* Wait for any direct GTT access to complete */ |
3182 | mb(); | |
3183 | ||
b5ffc9bc CW |
3184 | old_read_domains = obj->base.read_domains; |
3185 | old_write_domain = obj->base.write_domain; | |
3186 | ||
3187 | obj->base.read_domains &= ~I915_GEM_DOMAIN_GTT; | |
3188 | obj->base.write_domain &= ~I915_GEM_DOMAIN_GTT; | |
3189 | ||
3190 | trace_i915_gem_object_change_domain(obj, | |
3191 | old_read_domains, | |
3192 | old_write_domain); | |
3193 | } | |
3194 | ||
07fe0b12 | 3195 | int i915_vma_unbind(struct i915_vma *vma) |
673a394b | 3196 | { |
07fe0b12 | 3197 | struct drm_i915_gem_object *obj = vma->obj; |
3e31c6c0 | 3198 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
43e28f09 | 3199 | int ret; |
673a394b | 3200 | |
07fe0b12 | 3201 | if (list_empty(&vma->vma_link)) |
673a394b EA |
3202 | return 0; |
3203 | ||
0ff501cb DV |
3204 | if (!drm_mm_node_allocated(&vma->node)) { |
3205 | i915_gem_vma_destroy(vma); | |
0ff501cb DV |
3206 | return 0; |
3207 | } | |
433544bd | 3208 | |
d7f46fc4 | 3209 | if (vma->pin_count) |
31d8d651 | 3210 | return -EBUSY; |
673a394b | 3211 | |
c4670ad0 CW |
3212 | BUG_ON(obj->pages == NULL); |
3213 | ||
2e2f351d | 3214 | ret = i915_gem_object_wait_rendering(obj, false); |
1488fc08 | 3215 | if (ret) |
a8198eea CW |
3216 | return ret; |
3217 | /* Continue on if we fail due to EIO, the GPU is hung so we | |
3218 | * should be safe and we need to cleanup or else we might | |
3219 | * cause memory corruption through use-after-free. | |
3220 | */ | |
3221 | ||
fe14d5f4 TU |
3222 | if (i915_is_ggtt(vma->vm) && |
3223 | vma->ggtt_view.type == I915_GGTT_VIEW_NORMAL) { | |
8b1bc9b4 | 3224 | i915_gem_object_finish_gtt(obj); |
5323fd04 | 3225 | |
8b1bc9b4 DV |
3226 | /* release the fence reg _after_ flushing */ |
3227 | ret = i915_gem_object_put_fence(obj); | |
3228 | if (ret) | |
3229 | return ret; | |
3230 | } | |
96b47b65 | 3231 | |
07fe0b12 | 3232 | trace_i915_vma_unbind(vma); |
db53a302 | 3233 | |
777dc5bb | 3234 | vma->vm->unbind_vma(vma); |
5e562f1d | 3235 | vma->bound = 0; |
6f65e29a | 3236 | |
64bf9303 | 3237 | list_del_init(&vma->mm_list); |
fe14d5f4 TU |
3238 | if (i915_is_ggtt(vma->vm)) { |
3239 | if (vma->ggtt_view.type == I915_GGTT_VIEW_NORMAL) { | |
3240 | obj->map_and_fenceable = false; | |
3241 | } else if (vma->ggtt_view.pages) { | |
3242 | sg_free_table(vma->ggtt_view.pages); | |
3243 | kfree(vma->ggtt_view.pages); | |
3244 | vma->ggtt_view.pages = NULL; | |
3245 | } | |
3246 | } | |
673a394b | 3247 | |
2f633156 BW |
3248 | drm_mm_remove_node(&vma->node); |
3249 | i915_gem_vma_destroy(vma); | |
3250 | ||
3251 | /* Since the unbound list is global, only move to that list if | |
b93dab6e | 3252 | * no more VMAs exist. */ |
9490edb5 AR |
3253 | if (list_empty(&obj->vma_list)) { |
3254 | i915_gem_gtt_finish_object(obj); | |
2f633156 | 3255 | list_move_tail(&obj->global_list, &dev_priv->mm.unbound_list); |
9490edb5 | 3256 | } |
673a394b | 3257 | |
70903c3b CW |
3258 | /* And finally now the object is completely decoupled from this vma, |
3259 | * we can drop its hold on the backing storage and allow it to be | |
3260 | * reaped by the shrinker. | |
3261 | */ | |
3262 | i915_gem_object_unpin_pages(obj); | |
3263 | ||
88241785 | 3264 | return 0; |
54cf91dc CW |
3265 | } |
3266 | ||
b2da9fe5 | 3267 | int i915_gpu_idle(struct drm_device *dev) |
4df2faf4 | 3268 | { |
3e31c6c0 | 3269 | struct drm_i915_private *dev_priv = dev->dev_private; |
a4872ba6 | 3270 | struct intel_engine_cs *ring; |
1ec14ad3 | 3271 | int ret, i; |
4df2faf4 | 3272 | |
4df2faf4 | 3273 | /* Flush everything onto the inactive list. */ |
b4519513 | 3274 | for_each_ring(ring, dev_priv, i) { |
ecdb5fd8 TD |
3275 | if (!i915.enable_execlists) { |
3276 | ret = i915_switch_context(ring, ring->default_context); | |
3277 | if (ret) | |
3278 | return ret; | |
3279 | } | |
b6c7488d | 3280 | |
3e960501 | 3281 | ret = intel_ring_idle(ring); |
1ec14ad3 CW |
3282 | if (ret) |
3283 | return ret; | |
3284 | } | |
4df2faf4 | 3285 | |
b4716185 | 3286 | WARN_ON(i915_verify_lists(dev)); |
8a1a49f9 | 3287 | return 0; |
4df2faf4 DV |
3288 | } |
3289 | ||
9ce079e4 CW |
3290 | static void i965_write_fence_reg(struct drm_device *dev, int reg, |
3291 | struct drm_i915_gem_object *obj) | |
de151cf6 | 3292 | { |
3e31c6c0 | 3293 | struct drm_i915_private *dev_priv = dev->dev_private; |
56c844e5 ID |
3294 | int fence_reg; |
3295 | int fence_pitch_shift; | |
de151cf6 | 3296 | |
56c844e5 ID |
3297 | if (INTEL_INFO(dev)->gen >= 6) { |
3298 | fence_reg = FENCE_REG_SANDYBRIDGE_0; | |
3299 | fence_pitch_shift = SANDYBRIDGE_FENCE_PITCH_SHIFT; | |
3300 | } else { | |
3301 | fence_reg = FENCE_REG_965_0; | |
3302 | fence_pitch_shift = I965_FENCE_PITCH_SHIFT; | |
3303 | } | |
3304 | ||
d18b9619 CW |
3305 | fence_reg += reg * 8; |
3306 | ||
3307 | /* To w/a incoherency with non-atomic 64-bit register updates, | |
3308 | * we split the 64-bit update into two 32-bit writes. In order | |
3309 | * for a partial fence not to be evaluated between writes, we | |
3310 | * precede the update with write to turn off the fence register, | |
3311 | * and only enable the fence as the last step. | |
3312 | * | |
3313 | * For extra levels of paranoia, we make sure each step lands | |
3314 | * before applying the next step. | |
3315 | */ | |
3316 | I915_WRITE(fence_reg, 0); | |
3317 | POSTING_READ(fence_reg); | |
3318 | ||
9ce079e4 | 3319 | if (obj) { |
f343c5f6 | 3320 | u32 size = i915_gem_obj_ggtt_size(obj); |
d18b9619 | 3321 | uint64_t val; |
de151cf6 | 3322 | |
af1a7301 BP |
3323 | /* Adjust fence size to match tiled area */ |
3324 | if (obj->tiling_mode != I915_TILING_NONE) { | |
3325 | uint32_t row_size = obj->stride * | |
3326 | (obj->tiling_mode == I915_TILING_Y ? 32 : 8); | |
3327 | size = (size / row_size) * row_size; | |
3328 | } | |
3329 | ||
f343c5f6 | 3330 | val = (uint64_t)((i915_gem_obj_ggtt_offset(obj) + size - 4096) & |
9ce079e4 | 3331 | 0xfffff000) << 32; |
f343c5f6 | 3332 | val |= i915_gem_obj_ggtt_offset(obj) & 0xfffff000; |
56c844e5 | 3333 | val |= (uint64_t)((obj->stride / 128) - 1) << fence_pitch_shift; |
9ce079e4 CW |
3334 | if (obj->tiling_mode == I915_TILING_Y) |
3335 | val |= 1 << I965_FENCE_TILING_Y_SHIFT; | |
3336 | val |= I965_FENCE_REG_VALID; | |
c6642782 | 3337 | |
d18b9619 CW |
3338 | I915_WRITE(fence_reg + 4, val >> 32); |
3339 | POSTING_READ(fence_reg + 4); | |
3340 | ||
3341 | I915_WRITE(fence_reg + 0, val); | |
3342 | POSTING_READ(fence_reg); | |
3343 | } else { | |
3344 | I915_WRITE(fence_reg + 4, 0); | |
3345 | POSTING_READ(fence_reg + 4); | |
3346 | } | |
de151cf6 JB |
3347 | } |
3348 | ||
9ce079e4 CW |
3349 | static void i915_write_fence_reg(struct drm_device *dev, int reg, |
3350 | struct drm_i915_gem_object *obj) | |
de151cf6 | 3351 | { |
3e31c6c0 | 3352 | struct drm_i915_private *dev_priv = dev->dev_private; |
9ce079e4 | 3353 | u32 val; |
de151cf6 | 3354 | |
9ce079e4 | 3355 | if (obj) { |
f343c5f6 | 3356 | u32 size = i915_gem_obj_ggtt_size(obj); |
9ce079e4 CW |
3357 | int pitch_val; |
3358 | int tile_width; | |
c6642782 | 3359 | |
f343c5f6 | 3360 | WARN((i915_gem_obj_ggtt_offset(obj) & ~I915_FENCE_START_MASK) || |
9ce079e4 | 3361 | (size & -size) != size || |
f343c5f6 BW |
3362 | (i915_gem_obj_ggtt_offset(obj) & (size - 1)), |
3363 | "object 0x%08lx [fenceable? %d] not 1M or pot-size (0x%08x) aligned\n", | |
3364 | i915_gem_obj_ggtt_offset(obj), obj->map_and_fenceable, size); | |
c6642782 | 3365 | |
9ce079e4 CW |
3366 | if (obj->tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev)) |
3367 | tile_width = 128; | |
3368 | else | |
3369 | tile_width = 512; | |
3370 | ||
3371 | /* Note: pitch better be a power of two tile widths */ | |
3372 | pitch_val = obj->stride / tile_width; | |
3373 | pitch_val = ffs(pitch_val) - 1; | |
3374 | ||
f343c5f6 | 3375 | val = i915_gem_obj_ggtt_offset(obj); |
9ce079e4 CW |
3376 | if (obj->tiling_mode == I915_TILING_Y) |
3377 | val |= 1 << I830_FENCE_TILING_Y_SHIFT; | |
3378 | val |= I915_FENCE_SIZE_BITS(size); | |
3379 | val |= pitch_val << I830_FENCE_PITCH_SHIFT; | |
3380 | val |= I830_FENCE_REG_VALID; | |
3381 | } else | |
3382 | val = 0; | |
3383 | ||
3384 | if (reg < 8) | |
3385 | reg = FENCE_REG_830_0 + reg * 4; | |
3386 | else | |
3387 | reg = FENCE_REG_945_8 + (reg - 8) * 4; | |
3388 | ||
3389 | I915_WRITE(reg, val); | |
3390 | POSTING_READ(reg); | |
de151cf6 JB |
3391 | } |
3392 | ||
9ce079e4 CW |
3393 | static void i830_write_fence_reg(struct drm_device *dev, int reg, |
3394 | struct drm_i915_gem_object *obj) | |
de151cf6 | 3395 | { |
3e31c6c0 | 3396 | struct drm_i915_private *dev_priv = dev->dev_private; |
de151cf6 | 3397 | uint32_t val; |
de151cf6 | 3398 | |
9ce079e4 | 3399 | if (obj) { |
f343c5f6 | 3400 | u32 size = i915_gem_obj_ggtt_size(obj); |
9ce079e4 | 3401 | uint32_t pitch_val; |
de151cf6 | 3402 | |
f343c5f6 | 3403 | WARN((i915_gem_obj_ggtt_offset(obj) & ~I830_FENCE_START_MASK) || |
9ce079e4 | 3404 | (size & -size) != size || |
f343c5f6 BW |
3405 | (i915_gem_obj_ggtt_offset(obj) & (size - 1)), |
3406 | "object 0x%08lx not 512K or pot-size 0x%08x aligned\n", | |
3407 | i915_gem_obj_ggtt_offset(obj), size); | |
e76a16de | 3408 | |
9ce079e4 CW |
3409 | pitch_val = obj->stride / 128; |
3410 | pitch_val = ffs(pitch_val) - 1; | |
de151cf6 | 3411 | |
f343c5f6 | 3412 | val = i915_gem_obj_ggtt_offset(obj); |
9ce079e4 CW |
3413 | if (obj->tiling_mode == I915_TILING_Y) |
3414 | val |= 1 << I830_FENCE_TILING_Y_SHIFT; | |
3415 | val |= I830_FENCE_SIZE_BITS(size); | |
3416 | val |= pitch_val << I830_FENCE_PITCH_SHIFT; | |
3417 | val |= I830_FENCE_REG_VALID; | |
3418 | } else | |
3419 | val = 0; | |
c6642782 | 3420 | |
9ce079e4 CW |
3421 | I915_WRITE(FENCE_REG_830_0 + reg * 4, val); |
3422 | POSTING_READ(FENCE_REG_830_0 + reg * 4); | |
3423 | } | |
3424 | ||
d0a57789 CW |
3425 | inline static bool i915_gem_object_needs_mb(struct drm_i915_gem_object *obj) |
3426 | { | |
3427 | return obj && obj->base.read_domains & I915_GEM_DOMAIN_GTT; | |
3428 | } | |
3429 | ||
9ce079e4 CW |
3430 | static void i915_gem_write_fence(struct drm_device *dev, int reg, |
3431 | struct drm_i915_gem_object *obj) | |
3432 | { | |
d0a57789 CW |
3433 | struct drm_i915_private *dev_priv = dev->dev_private; |
3434 | ||
3435 | /* Ensure that all CPU reads are completed before installing a fence | |
3436 | * and all writes before removing the fence. | |
3437 | */ | |
3438 | if (i915_gem_object_needs_mb(dev_priv->fence_regs[reg].obj)) | |
3439 | mb(); | |
3440 | ||
94a335db DV |
3441 | WARN(obj && (!obj->stride || !obj->tiling_mode), |
3442 | "bogus fence setup with stride: 0x%x, tiling mode: %i\n", | |
3443 | obj->stride, obj->tiling_mode); | |
3444 | ||
ce38ab05 RV |
3445 | if (IS_GEN2(dev)) |
3446 | i830_write_fence_reg(dev, reg, obj); | |
3447 | else if (IS_GEN3(dev)) | |
3448 | i915_write_fence_reg(dev, reg, obj); | |
3449 | else if (INTEL_INFO(dev)->gen >= 4) | |
3450 | i965_write_fence_reg(dev, reg, obj); | |
d0a57789 CW |
3451 | |
3452 | /* And similarly be paranoid that no direct access to this region | |
3453 | * is reordered to before the fence is installed. | |
3454 | */ | |
3455 | if (i915_gem_object_needs_mb(obj)) | |
3456 | mb(); | |
de151cf6 JB |
3457 | } |
3458 | ||
61050808 CW |
3459 | static inline int fence_number(struct drm_i915_private *dev_priv, |
3460 | struct drm_i915_fence_reg *fence) | |
3461 | { | |
3462 | return fence - dev_priv->fence_regs; | |
3463 | } | |
3464 | ||
3465 | static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj, | |
3466 | struct drm_i915_fence_reg *fence, | |
3467 | bool enable) | |
3468 | { | |
2dc8aae0 | 3469 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
46a0b638 CW |
3470 | int reg = fence_number(dev_priv, fence); |
3471 | ||
3472 | i915_gem_write_fence(obj->base.dev, reg, enable ? obj : NULL); | |
61050808 CW |
3473 | |
3474 | if (enable) { | |
46a0b638 | 3475 | obj->fence_reg = reg; |
61050808 CW |
3476 | fence->obj = obj; |
3477 | list_move_tail(&fence->lru_list, &dev_priv->mm.fence_list); | |
3478 | } else { | |
3479 | obj->fence_reg = I915_FENCE_REG_NONE; | |
3480 | fence->obj = NULL; | |
3481 | list_del_init(&fence->lru_list); | |
3482 | } | |
94a335db | 3483 | obj->fence_dirty = false; |
61050808 CW |
3484 | } |
3485 | ||
d9e86c0e | 3486 | static int |
d0a57789 | 3487 | i915_gem_object_wait_fence(struct drm_i915_gem_object *obj) |
d9e86c0e | 3488 | { |
97b2a6a1 | 3489 | if (obj->last_fenced_req) { |
a4b3a571 | 3490 | int ret = i915_wait_request(obj->last_fenced_req); |
18991845 CW |
3491 | if (ret) |
3492 | return ret; | |
d9e86c0e | 3493 | |
97b2a6a1 | 3494 | i915_gem_request_assign(&obj->last_fenced_req, NULL); |
d9e86c0e CW |
3495 | } |
3496 | ||
3497 | return 0; | |
3498 | } | |
3499 | ||
3500 | int | |
3501 | i915_gem_object_put_fence(struct drm_i915_gem_object *obj) | |
3502 | { | |
61050808 | 3503 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
f9c513e9 | 3504 | struct drm_i915_fence_reg *fence; |
d9e86c0e CW |
3505 | int ret; |
3506 | ||
d0a57789 | 3507 | ret = i915_gem_object_wait_fence(obj); |
d9e86c0e CW |
3508 | if (ret) |
3509 | return ret; | |
3510 | ||
61050808 CW |
3511 | if (obj->fence_reg == I915_FENCE_REG_NONE) |
3512 | return 0; | |
d9e86c0e | 3513 | |
f9c513e9 CW |
3514 | fence = &dev_priv->fence_regs[obj->fence_reg]; |
3515 | ||
aff10b30 DV |
3516 | if (WARN_ON(fence->pin_count)) |
3517 | return -EBUSY; | |
3518 | ||
61050808 | 3519 | i915_gem_object_fence_lost(obj); |
f9c513e9 | 3520 | i915_gem_object_update_fence(obj, fence, false); |
d9e86c0e CW |
3521 | |
3522 | return 0; | |
3523 | } | |
3524 | ||
3525 | static struct drm_i915_fence_reg * | |
a360bb1a | 3526 | i915_find_fence_reg(struct drm_device *dev) |
ae3db24a | 3527 | { |
ae3db24a | 3528 | struct drm_i915_private *dev_priv = dev->dev_private; |
8fe301ad | 3529 | struct drm_i915_fence_reg *reg, *avail; |
d9e86c0e | 3530 | int i; |
ae3db24a DV |
3531 | |
3532 | /* First try to find a free reg */ | |
d9e86c0e | 3533 | avail = NULL; |
ae3db24a DV |
3534 | for (i = dev_priv->fence_reg_start; i < dev_priv->num_fence_regs; i++) { |
3535 | reg = &dev_priv->fence_regs[i]; | |
3536 | if (!reg->obj) | |
d9e86c0e | 3537 | return reg; |
ae3db24a | 3538 | |
1690e1eb | 3539 | if (!reg->pin_count) |
d9e86c0e | 3540 | avail = reg; |
ae3db24a DV |
3541 | } |
3542 | ||
d9e86c0e | 3543 | if (avail == NULL) |
5dce5b93 | 3544 | goto deadlock; |
ae3db24a DV |
3545 | |
3546 | /* None available, try to steal one or wait for a user to finish */ | |
d9e86c0e | 3547 | list_for_each_entry(reg, &dev_priv->mm.fence_list, lru_list) { |
1690e1eb | 3548 | if (reg->pin_count) |
ae3db24a DV |
3549 | continue; |
3550 | ||
8fe301ad | 3551 | return reg; |
ae3db24a DV |
3552 | } |
3553 | ||
5dce5b93 CW |
3554 | deadlock: |
3555 | /* Wait for completion of pending flips which consume fences */ | |
3556 | if (intel_has_pending_fb_unpin(dev)) | |
3557 | return ERR_PTR(-EAGAIN); | |
3558 | ||
3559 | return ERR_PTR(-EDEADLK); | |
ae3db24a DV |
3560 | } |
3561 | ||
de151cf6 | 3562 | /** |
9a5a53b3 | 3563 | * i915_gem_object_get_fence - set up fencing for an object |
de151cf6 JB |
3564 | * @obj: object to map through a fence reg |
3565 | * | |
3566 | * When mapping objects through the GTT, userspace wants to be able to write | |
3567 | * to them without having to worry about swizzling if the object is tiled. | |
de151cf6 JB |
3568 | * This function walks the fence regs looking for a free one for @obj, |
3569 | * stealing one if it can't find any. | |
3570 | * | |
3571 | * It then sets up the reg based on the object's properties: address, pitch | |
3572 | * and tiling format. | |
9a5a53b3 CW |
3573 | * |
3574 | * For an untiled surface, this removes any existing fence. | |
de151cf6 | 3575 | */ |
8c4b8c3f | 3576 | int |
06d98131 | 3577 | i915_gem_object_get_fence(struct drm_i915_gem_object *obj) |
de151cf6 | 3578 | { |
05394f39 | 3579 | struct drm_device *dev = obj->base.dev; |
79e53945 | 3580 | struct drm_i915_private *dev_priv = dev->dev_private; |
14415745 | 3581 | bool enable = obj->tiling_mode != I915_TILING_NONE; |
d9e86c0e | 3582 | struct drm_i915_fence_reg *reg; |
ae3db24a | 3583 | int ret; |
de151cf6 | 3584 | |
14415745 CW |
3585 | /* Have we updated the tiling parameters upon the object and so |
3586 | * will need to serialise the write to the associated fence register? | |
3587 | */ | |
5d82e3e6 | 3588 | if (obj->fence_dirty) { |
d0a57789 | 3589 | ret = i915_gem_object_wait_fence(obj); |
14415745 CW |
3590 | if (ret) |
3591 | return ret; | |
3592 | } | |
9a5a53b3 | 3593 | |
d9e86c0e | 3594 | /* Just update our place in the LRU if our fence is getting reused. */ |
05394f39 CW |
3595 | if (obj->fence_reg != I915_FENCE_REG_NONE) { |
3596 | reg = &dev_priv->fence_regs[obj->fence_reg]; | |
5d82e3e6 | 3597 | if (!obj->fence_dirty) { |
14415745 CW |
3598 | list_move_tail(®->lru_list, |
3599 | &dev_priv->mm.fence_list); | |
3600 | return 0; | |
3601 | } | |
3602 | } else if (enable) { | |
e6a84468 CW |
3603 | if (WARN_ON(!obj->map_and_fenceable)) |
3604 | return -EINVAL; | |
3605 | ||
14415745 | 3606 | reg = i915_find_fence_reg(dev); |
5dce5b93 CW |
3607 | if (IS_ERR(reg)) |
3608 | return PTR_ERR(reg); | |
d9e86c0e | 3609 | |
14415745 CW |
3610 | if (reg->obj) { |
3611 | struct drm_i915_gem_object *old = reg->obj; | |
3612 | ||
d0a57789 | 3613 | ret = i915_gem_object_wait_fence(old); |
29c5a587 CW |
3614 | if (ret) |
3615 | return ret; | |
3616 | ||
14415745 | 3617 | i915_gem_object_fence_lost(old); |
29c5a587 | 3618 | } |
14415745 | 3619 | } else |
a09ba7fa | 3620 | return 0; |
a09ba7fa | 3621 | |
14415745 | 3622 | i915_gem_object_update_fence(obj, reg, enable); |
14415745 | 3623 | |
9ce079e4 | 3624 | return 0; |
de151cf6 JB |
3625 | } |
3626 | ||
4144f9b5 | 3627 | static bool i915_gem_valid_gtt_space(struct i915_vma *vma, |
42d6ab48 CW |
3628 | unsigned long cache_level) |
3629 | { | |
4144f9b5 | 3630 | struct drm_mm_node *gtt_space = &vma->node; |
42d6ab48 CW |
3631 | struct drm_mm_node *other; |
3632 | ||
4144f9b5 CW |
3633 | /* |
3634 | * On some machines we have to be careful when putting differing types | |
3635 | * of snoopable memory together to avoid the prefetcher crossing memory | |
3636 | * domains and dying. During vm initialisation, we decide whether or not | |
3637 | * these constraints apply and set the drm_mm.color_adjust | |
3638 | * appropriately. | |
42d6ab48 | 3639 | */ |
4144f9b5 | 3640 | if (vma->vm->mm.color_adjust == NULL) |
42d6ab48 CW |
3641 | return true; |
3642 | ||
c6cfb325 | 3643 | if (!drm_mm_node_allocated(gtt_space)) |
42d6ab48 CW |
3644 | return true; |
3645 | ||
3646 | if (list_empty(>t_space->node_list)) | |
3647 | return true; | |
3648 | ||
3649 | other = list_entry(gtt_space->node_list.prev, struct drm_mm_node, node_list); | |
3650 | if (other->allocated && !other->hole_follows && other->color != cache_level) | |
3651 | return false; | |
3652 | ||
3653 | other = list_entry(gtt_space->node_list.next, struct drm_mm_node, node_list); | |
3654 | if (other->allocated && !gtt_space->hole_follows && other->color != cache_level) | |
3655 | return false; | |
3656 | ||
3657 | return true; | |
3658 | } | |
3659 | ||
673a394b | 3660 | /** |
91e6711e JL |
3661 | * Finds free space in the GTT aperture and binds the object or a view of it |
3662 | * there. | |
673a394b | 3663 | */ |
262de145 | 3664 | static struct i915_vma * |
07fe0b12 BW |
3665 | i915_gem_object_bind_to_vm(struct drm_i915_gem_object *obj, |
3666 | struct i915_address_space *vm, | |
ec7adb6e | 3667 | const struct i915_ggtt_view *ggtt_view, |
07fe0b12 | 3668 | unsigned alignment, |
ec7adb6e | 3669 | uint64_t flags) |
673a394b | 3670 | { |
05394f39 | 3671 | struct drm_device *dev = obj->base.dev; |
3e31c6c0 | 3672 | struct drm_i915_private *dev_priv = dev->dev_private; |
5e783301 | 3673 | u32 size, fence_size, fence_alignment, unfenced_alignment; |
d23db88c CW |
3674 | unsigned long start = |
3675 | flags & PIN_OFFSET_BIAS ? flags & PIN_OFFSET_MASK : 0; | |
3676 | unsigned long end = | |
1ec9e26d | 3677 | flags & PIN_MAPPABLE ? dev_priv->gtt.mappable_end : vm->total; |
2f633156 | 3678 | struct i915_vma *vma; |
07f73f69 | 3679 | int ret; |
673a394b | 3680 | |
91e6711e JL |
3681 | if (i915_is_ggtt(vm)) { |
3682 | u32 view_size; | |
3683 | ||
3684 | if (WARN_ON(!ggtt_view)) | |
3685 | return ERR_PTR(-EINVAL); | |
ec7adb6e | 3686 | |
91e6711e JL |
3687 | view_size = i915_ggtt_view_size(obj, ggtt_view); |
3688 | ||
3689 | fence_size = i915_gem_get_gtt_size(dev, | |
3690 | view_size, | |
3691 | obj->tiling_mode); | |
3692 | fence_alignment = i915_gem_get_gtt_alignment(dev, | |
3693 | view_size, | |
3694 | obj->tiling_mode, | |
3695 | true); | |
3696 | unfenced_alignment = i915_gem_get_gtt_alignment(dev, | |
3697 | view_size, | |
3698 | obj->tiling_mode, | |
3699 | false); | |
3700 | size = flags & PIN_MAPPABLE ? fence_size : view_size; | |
3701 | } else { | |
3702 | fence_size = i915_gem_get_gtt_size(dev, | |
3703 | obj->base.size, | |
3704 | obj->tiling_mode); | |
3705 | fence_alignment = i915_gem_get_gtt_alignment(dev, | |
3706 | obj->base.size, | |
3707 | obj->tiling_mode, | |
3708 | true); | |
3709 | unfenced_alignment = | |
3710 | i915_gem_get_gtt_alignment(dev, | |
3711 | obj->base.size, | |
3712 | obj->tiling_mode, | |
3713 | false); | |
3714 | size = flags & PIN_MAPPABLE ? fence_size : obj->base.size; | |
3715 | } | |
a00b10c3 | 3716 | |
673a394b | 3717 | if (alignment == 0) |
1ec9e26d | 3718 | alignment = flags & PIN_MAPPABLE ? fence_alignment : |
5e783301 | 3719 | unfenced_alignment; |
1ec9e26d | 3720 | if (flags & PIN_MAPPABLE && alignment & (fence_alignment - 1)) { |
91e6711e JL |
3721 | DRM_DEBUG("Invalid object (view type=%u) alignment requested %u\n", |
3722 | ggtt_view ? ggtt_view->type : 0, | |
3723 | alignment); | |
262de145 | 3724 | return ERR_PTR(-EINVAL); |
673a394b EA |
3725 | } |
3726 | ||
91e6711e JL |
3727 | /* If binding the object/GGTT view requires more space than the entire |
3728 | * aperture has, reject it early before evicting everything in a vain | |
3729 | * attempt to find space. | |
654fc607 | 3730 | */ |
91e6711e JL |
3731 | if (size > end) { |
3732 | DRM_DEBUG("Attempting to bind an object (view type=%u) larger than the aperture: size=%u > %s aperture=%lu\n", | |
3733 | ggtt_view ? ggtt_view->type : 0, | |
3734 | size, | |
1ec9e26d | 3735 | flags & PIN_MAPPABLE ? "mappable" : "total", |
d23db88c | 3736 | end); |
262de145 | 3737 | return ERR_PTR(-E2BIG); |
654fc607 CW |
3738 | } |
3739 | ||
37e680a1 | 3740 | ret = i915_gem_object_get_pages(obj); |
6c085a72 | 3741 | if (ret) |
262de145 | 3742 | return ERR_PTR(ret); |
6c085a72 | 3743 | |
fbdda6fb CW |
3744 | i915_gem_object_pin_pages(obj); |
3745 | ||
ec7adb6e JL |
3746 | vma = ggtt_view ? i915_gem_obj_lookup_or_create_ggtt_vma(obj, ggtt_view) : |
3747 | i915_gem_obj_lookup_or_create_vma(obj, vm); | |
3748 | ||
262de145 | 3749 | if (IS_ERR(vma)) |
bc6bc15b | 3750 | goto err_unpin; |
2f633156 | 3751 | |
0a9ae0d7 | 3752 | search_free: |
07fe0b12 | 3753 | ret = drm_mm_insert_node_in_range_generic(&vm->mm, &vma->node, |
0a9ae0d7 | 3754 | size, alignment, |
d23db88c CW |
3755 | obj->cache_level, |
3756 | start, end, | |
62347f9e LK |
3757 | DRM_MM_SEARCH_DEFAULT, |
3758 | DRM_MM_CREATE_DEFAULT); | |
dc9dd7a2 | 3759 | if (ret) { |
f6cd1f15 | 3760 | ret = i915_gem_evict_something(dev, vm, size, alignment, |
d23db88c CW |
3761 | obj->cache_level, |
3762 | start, end, | |
3763 | flags); | |
dc9dd7a2 CW |
3764 | if (ret == 0) |
3765 | goto search_free; | |
9731129c | 3766 | |
bc6bc15b | 3767 | goto err_free_vma; |
673a394b | 3768 | } |
4144f9b5 | 3769 | if (WARN_ON(!i915_gem_valid_gtt_space(vma, obj->cache_level))) { |
2f633156 | 3770 | ret = -EINVAL; |
bc6bc15b | 3771 | goto err_remove_node; |
673a394b EA |
3772 | } |
3773 | ||
74163907 | 3774 | ret = i915_gem_gtt_prepare_object(obj); |
2f633156 | 3775 | if (ret) |
bc6bc15b | 3776 | goto err_remove_node; |
673a394b | 3777 | |
fe14d5f4 | 3778 | trace_i915_vma_bind(vma, flags); |
0875546c | 3779 | ret = i915_vma_bind(vma, obj->cache_level, flags); |
fe14d5f4 TU |
3780 | if (ret) |
3781 | goto err_finish_gtt; | |
3782 | ||
35c20a60 | 3783 | list_move_tail(&obj->global_list, &dev_priv->mm.bound_list); |
ca191b13 | 3784 | list_add_tail(&vma->mm_list, &vm->inactive_list); |
bf1a1092 | 3785 | |
262de145 | 3786 | return vma; |
2f633156 | 3787 | |
fe14d5f4 TU |
3788 | err_finish_gtt: |
3789 | i915_gem_gtt_finish_object(obj); | |
bc6bc15b | 3790 | err_remove_node: |
6286ef9b | 3791 | drm_mm_remove_node(&vma->node); |
bc6bc15b | 3792 | err_free_vma: |
2f633156 | 3793 | i915_gem_vma_destroy(vma); |
262de145 | 3794 | vma = ERR_PTR(ret); |
bc6bc15b | 3795 | err_unpin: |
2f633156 | 3796 | i915_gem_object_unpin_pages(obj); |
262de145 | 3797 | return vma; |
673a394b EA |
3798 | } |
3799 | ||
000433b6 | 3800 | bool |
2c22569b CW |
3801 | i915_gem_clflush_object(struct drm_i915_gem_object *obj, |
3802 | bool force) | |
673a394b | 3803 | { |
673a394b EA |
3804 | /* If we don't have a page list set up, then we're not pinned |
3805 | * to GPU, and we can ignore the cache flush because it'll happen | |
3806 | * again at bind time. | |
3807 | */ | |
05394f39 | 3808 | if (obj->pages == NULL) |
000433b6 | 3809 | return false; |
673a394b | 3810 | |
769ce464 ID |
3811 | /* |
3812 | * Stolen memory is always coherent with the GPU as it is explicitly | |
3813 | * marked as wc by the system, or the system is cache-coherent. | |
3814 | */ | |
6a2c4232 | 3815 | if (obj->stolen || obj->phys_handle) |
000433b6 | 3816 | return false; |
769ce464 | 3817 | |
9c23f7fc CW |
3818 | /* If the GPU is snooping the contents of the CPU cache, |
3819 | * we do not need to manually clear the CPU cache lines. However, | |
3820 | * the caches are only snooped when the render cache is | |
3821 | * flushed/invalidated. As we always have to emit invalidations | |
3822 | * and flushes when moving into and out of the RENDER domain, correct | |
3823 | * snooping behaviour occurs naturally as the result of our domain | |
3824 | * tracking. | |
3825 | */ | |
0f71979a CW |
3826 | if (!force && cpu_cache_is_coherent(obj->base.dev, obj->cache_level)) { |
3827 | obj->cache_dirty = true; | |
000433b6 | 3828 | return false; |
0f71979a | 3829 | } |
9c23f7fc | 3830 | |
1c5d22f7 | 3831 | trace_i915_gem_object_clflush(obj); |
9da3da66 | 3832 | drm_clflush_sg(obj->pages); |
0f71979a | 3833 | obj->cache_dirty = false; |
000433b6 CW |
3834 | |
3835 | return true; | |
e47c68e9 EA |
3836 | } |
3837 | ||
3838 | /** Flushes the GTT write domain for the object if it's dirty. */ | |
3839 | static void | |
05394f39 | 3840 | i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj) |
e47c68e9 | 3841 | { |
1c5d22f7 CW |
3842 | uint32_t old_write_domain; |
3843 | ||
05394f39 | 3844 | if (obj->base.write_domain != I915_GEM_DOMAIN_GTT) |
e47c68e9 EA |
3845 | return; |
3846 | ||
63256ec5 | 3847 | /* No actual flushing is required for the GTT write domain. Writes |
e47c68e9 EA |
3848 | * to it immediately go to main memory as far as we know, so there's |
3849 | * no chipset flush. It also doesn't land in render cache. | |
63256ec5 CW |
3850 | * |
3851 | * However, we do have to enforce the order so that all writes through | |
3852 | * the GTT land before any writes to the device, such as updates to | |
3853 | * the GATT itself. | |
e47c68e9 | 3854 | */ |
63256ec5 CW |
3855 | wmb(); |
3856 | ||
05394f39 CW |
3857 | old_write_domain = obj->base.write_domain; |
3858 | obj->base.write_domain = 0; | |
1c5d22f7 | 3859 | |
f99d7069 DV |
3860 | intel_fb_obj_flush(obj, false); |
3861 | ||
1c5d22f7 | 3862 | trace_i915_gem_object_change_domain(obj, |
05394f39 | 3863 | obj->base.read_domains, |
1c5d22f7 | 3864 | old_write_domain); |
e47c68e9 EA |
3865 | } |
3866 | ||
3867 | /** Flushes the CPU write domain for the object if it's dirty. */ | |
3868 | static void | |
e62b59e4 | 3869 | i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj) |
e47c68e9 | 3870 | { |
1c5d22f7 | 3871 | uint32_t old_write_domain; |
e47c68e9 | 3872 | |
05394f39 | 3873 | if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) |
e47c68e9 EA |
3874 | return; |
3875 | ||
e62b59e4 | 3876 | if (i915_gem_clflush_object(obj, obj->pin_display)) |
000433b6 CW |
3877 | i915_gem_chipset_flush(obj->base.dev); |
3878 | ||
05394f39 CW |
3879 | old_write_domain = obj->base.write_domain; |
3880 | obj->base.write_domain = 0; | |
1c5d22f7 | 3881 | |
f99d7069 DV |
3882 | intel_fb_obj_flush(obj, false); |
3883 | ||
1c5d22f7 | 3884 | trace_i915_gem_object_change_domain(obj, |
05394f39 | 3885 | obj->base.read_domains, |
1c5d22f7 | 3886 | old_write_domain); |
e47c68e9 EA |
3887 | } |
3888 | ||
2ef7eeaa EA |
3889 | /** |
3890 | * Moves a single object to the GTT read, and possibly write domain. | |
3891 | * | |
3892 | * This function returns when the move is complete, including waiting on | |
3893 | * flushes to occur. | |
3894 | */ | |
79e53945 | 3895 | int |
2021746e | 3896 | i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write) |
2ef7eeaa | 3897 | { |
1c5d22f7 | 3898 | uint32_t old_write_domain, old_read_domains; |
43566ded | 3899 | struct i915_vma *vma; |
e47c68e9 | 3900 | int ret; |
2ef7eeaa | 3901 | |
8d7e3de1 CW |
3902 | if (obj->base.write_domain == I915_GEM_DOMAIN_GTT) |
3903 | return 0; | |
3904 | ||
0201f1ec | 3905 | ret = i915_gem_object_wait_rendering(obj, !write); |
88241785 CW |
3906 | if (ret) |
3907 | return ret; | |
3908 | ||
43566ded CW |
3909 | /* Flush and acquire obj->pages so that we are coherent through |
3910 | * direct access in memory with previous cached writes through | |
3911 | * shmemfs and that our cache domain tracking remains valid. | |
3912 | * For example, if the obj->filp was moved to swap without us | |
3913 | * being notified and releasing the pages, we would mistakenly | |
3914 | * continue to assume that the obj remained out of the CPU cached | |
3915 | * domain. | |
3916 | */ | |
3917 | ret = i915_gem_object_get_pages(obj); | |
3918 | if (ret) | |
3919 | return ret; | |
3920 | ||
e62b59e4 | 3921 | i915_gem_object_flush_cpu_write_domain(obj); |
1c5d22f7 | 3922 | |
d0a57789 CW |
3923 | /* Serialise direct access to this object with the barriers for |
3924 | * coherent writes from the GPU, by effectively invalidating the | |
3925 | * GTT domain upon first access. | |
3926 | */ | |
3927 | if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0) | |
3928 | mb(); | |
3929 | ||
05394f39 CW |
3930 | old_write_domain = obj->base.write_domain; |
3931 | old_read_domains = obj->base.read_domains; | |
1c5d22f7 | 3932 | |
e47c68e9 EA |
3933 | /* It should now be out of any other write domains, and we can update |
3934 | * the domain values for our changes. | |
3935 | */ | |
05394f39 CW |
3936 | BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_GTT) != 0); |
3937 | obj->base.read_domains |= I915_GEM_DOMAIN_GTT; | |
e47c68e9 | 3938 | if (write) { |
05394f39 CW |
3939 | obj->base.read_domains = I915_GEM_DOMAIN_GTT; |
3940 | obj->base.write_domain = I915_GEM_DOMAIN_GTT; | |
3941 | obj->dirty = 1; | |
2ef7eeaa EA |
3942 | } |
3943 | ||
f99d7069 | 3944 | if (write) |
a4001f1b | 3945 | intel_fb_obj_invalidate(obj, NULL, ORIGIN_GTT); |
f99d7069 | 3946 | |
1c5d22f7 CW |
3947 | trace_i915_gem_object_change_domain(obj, |
3948 | old_read_domains, | |
3949 | old_write_domain); | |
3950 | ||
8325a09d | 3951 | /* And bump the LRU for this access */ |
43566ded CW |
3952 | vma = i915_gem_obj_to_ggtt(obj); |
3953 | if (vma && drm_mm_node_allocated(&vma->node) && !obj->active) | |
dc8cd1e7 | 3954 | list_move_tail(&vma->mm_list, |
43566ded | 3955 | &to_i915(obj->base.dev)->gtt.base.inactive_list); |
8325a09d | 3956 | |
e47c68e9 EA |
3957 | return 0; |
3958 | } | |
3959 | ||
e4ffd173 CW |
3960 | int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj, |
3961 | enum i915_cache_level cache_level) | |
3962 | { | |
7bddb01f | 3963 | struct drm_device *dev = obj->base.dev; |
df6f783a | 3964 | struct i915_vma *vma, *next; |
e4ffd173 CW |
3965 | int ret; |
3966 | ||
3967 | if (obj->cache_level == cache_level) | |
3968 | return 0; | |
3969 | ||
d7f46fc4 | 3970 | if (i915_gem_obj_is_pinned(obj)) { |
e4ffd173 CW |
3971 | DRM_DEBUG("can not change the cache level of pinned objects\n"); |
3972 | return -EBUSY; | |
3973 | } | |
3974 | ||
df6f783a | 3975 | list_for_each_entry_safe(vma, next, &obj->vma_list, vma_link) { |
4144f9b5 | 3976 | if (!i915_gem_valid_gtt_space(vma, cache_level)) { |
07fe0b12 | 3977 | ret = i915_vma_unbind(vma); |
3089c6f2 BW |
3978 | if (ret) |
3979 | return ret; | |
3089c6f2 | 3980 | } |
42d6ab48 CW |
3981 | } |
3982 | ||
3089c6f2 | 3983 | if (i915_gem_obj_bound_any(obj)) { |
2e2f351d | 3984 | ret = i915_gem_object_wait_rendering(obj, false); |
e4ffd173 CW |
3985 | if (ret) |
3986 | return ret; | |
3987 | ||
3988 | i915_gem_object_finish_gtt(obj); | |
3989 | ||
3990 | /* Before SandyBridge, you could not use tiling or fence | |
3991 | * registers with snooped memory, so relinquish any fences | |
3992 | * currently pointing to our region in the aperture. | |
3993 | */ | |
42d6ab48 | 3994 | if (INTEL_INFO(dev)->gen < 6) { |
e4ffd173 CW |
3995 | ret = i915_gem_object_put_fence(obj); |
3996 | if (ret) | |
3997 | return ret; | |
3998 | } | |
3999 | ||
6f65e29a | 4000 | list_for_each_entry(vma, &obj->vma_list, vma_link) |
fe14d5f4 TU |
4001 | if (drm_mm_node_allocated(&vma->node)) { |
4002 | ret = i915_vma_bind(vma, cache_level, | |
0875546c | 4003 | PIN_UPDATE); |
fe14d5f4 TU |
4004 | if (ret) |
4005 | return ret; | |
4006 | } | |
e4ffd173 CW |
4007 | } |
4008 | ||
2c22569b CW |
4009 | list_for_each_entry(vma, &obj->vma_list, vma_link) |
4010 | vma->node.color = cache_level; | |
4011 | obj->cache_level = cache_level; | |
4012 | ||
0f71979a CW |
4013 | if (obj->cache_dirty && |
4014 | obj->base.write_domain != I915_GEM_DOMAIN_CPU && | |
4015 | cpu_write_needs_clflush(obj)) { | |
4016 | if (i915_gem_clflush_object(obj, true)) | |
4017 | i915_gem_chipset_flush(obj->base.dev); | |
e4ffd173 CW |
4018 | } |
4019 | ||
e4ffd173 CW |
4020 | return 0; |
4021 | } | |
4022 | ||
199adf40 BW |
4023 | int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data, |
4024 | struct drm_file *file) | |
e6994aee | 4025 | { |
199adf40 | 4026 | struct drm_i915_gem_caching *args = data; |
e6994aee | 4027 | struct drm_i915_gem_object *obj; |
e6994aee CW |
4028 | |
4029 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); | |
432be69d CW |
4030 | if (&obj->base == NULL) |
4031 | return -ENOENT; | |
e6994aee | 4032 | |
651d794f CW |
4033 | switch (obj->cache_level) { |
4034 | case I915_CACHE_LLC: | |
4035 | case I915_CACHE_L3_LLC: | |
4036 | args->caching = I915_CACHING_CACHED; | |
4037 | break; | |
4038 | ||
4257d3ba CW |
4039 | case I915_CACHE_WT: |
4040 | args->caching = I915_CACHING_DISPLAY; | |
4041 | break; | |
4042 | ||
651d794f CW |
4043 | default: |
4044 | args->caching = I915_CACHING_NONE; | |
4045 | break; | |
4046 | } | |
e6994aee | 4047 | |
432be69d CW |
4048 | drm_gem_object_unreference_unlocked(&obj->base); |
4049 | return 0; | |
e6994aee CW |
4050 | } |
4051 | ||
199adf40 BW |
4052 | int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data, |
4053 | struct drm_file *file) | |
e6994aee | 4054 | { |
199adf40 | 4055 | struct drm_i915_gem_caching *args = data; |
e6994aee CW |
4056 | struct drm_i915_gem_object *obj; |
4057 | enum i915_cache_level level; | |
4058 | int ret; | |
4059 | ||
199adf40 BW |
4060 | switch (args->caching) { |
4061 | case I915_CACHING_NONE: | |
e6994aee CW |
4062 | level = I915_CACHE_NONE; |
4063 | break; | |
199adf40 | 4064 | case I915_CACHING_CACHED: |
e6994aee CW |
4065 | level = I915_CACHE_LLC; |
4066 | break; | |
4257d3ba CW |
4067 | case I915_CACHING_DISPLAY: |
4068 | level = HAS_WT(dev) ? I915_CACHE_WT : I915_CACHE_NONE; | |
4069 | break; | |
e6994aee CW |
4070 | default: |
4071 | return -EINVAL; | |
4072 | } | |
4073 | ||
3bc2913e BW |
4074 | ret = i915_mutex_lock_interruptible(dev); |
4075 | if (ret) | |
4076 | return ret; | |
4077 | ||
e6994aee CW |
4078 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
4079 | if (&obj->base == NULL) { | |
4080 | ret = -ENOENT; | |
4081 | goto unlock; | |
4082 | } | |
4083 | ||
4084 | ret = i915_gem_object_set_cache_level(obj, level); | |
4085 | ||
4086 | drm_gem_object_unreference(&obj->base); | |
4087 | unlock: | |
4088 | mutex_unlock(&dev->struct_mutex); | |
4089 | return ret; | |
4090 | } | |
4091 | ||
b9241ea3 | 4092 | /* |
2da3b9b9 CW |
4093 | * Prepare buffer for display plane (scanout, cursors, etc). |
4094 | * Can be called from an uninterruptible phase (modesetting) and allows | |
4095 | * any flushes to be pipelined (for pageflips). | |
b9241ea3 ZW |
4096 | */ |
4097 | int | |
2da3b9b9 CW |
4098 | i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj, |
4099 | u32 alignment, | |
e6617330 TU |
4100 | struct intel_engine_cs *pipelined, |
4101 | const struct i915_ggtt_view *view) | |
b9241ea3 | 4102 | { |
2da3b9b9 | 4103 | u32 old_read_domains, old_write_domain; |
b9241ea3 ZW |
4104 | int ret; |
4105 | ||
b4716185 CW |
4106 | ret = i915_gem_object_sync(obj, pipelined); |
4107 | if (ret) | |
4108 | return ret; | |
b9241ea3 | 4109 | |
cc98b413 CW |
4110 | /* Mark the pin_display early so that we account for the |
4111 | * display coherency whilst setting up the cache domains. | |
4112 | */ | |
8a0c39b1 | 4113 | obj->pin_display++; |
cc98b413 | 4114 | |
a7ef0640 EA |
4115 | /* The display engine is not coherent with the LLC cache on gen6. As |
4116 | * a result, we make sure that the pinning that is about to occur is | |
4117 | * done with uncached PTEs. This is lowest common denominator for all | |
4118 | * chipsets. | |
4119 | * | |
4120 | * However for gen6+, we could do better by using the GFDT bit instead | |
4121 | * of uncaching, which would allow us to flush all the LLC-cached data | |
4122 | * with that bit in the PTE to main memory with just one PIPE_CONTROL. | |
4123 | */ | |
651d794f CW |
4124 | ret = i915_gem_object_set_cache_level(obj, |
4125 | HAS_WT(obj->base.dev) ? I915_CACHE_WT : I915_CACHE_NONE); | |
a7ef0640 | 4126 | if (ret) |
cc98b413 | 4127 | goto err_unpin_display; |
a7ef0640 | 4128 | |
2da3b9b9 CW |
4129 | /* As the user may map the buffer once pinned in the display plane |
4130 | * (e.g. libkms for the bootup splash), we have to ensure that we | |
4131 | * always use map_and_fenceable for all scanout buffers. | |
4132 | */ | |
50470bb0 TU |
4133 | ret = i915_gem_object_ggtt_pin(obj, view, alignment, |
4134 | view->type == I915_GGTT_VIEW_NORMAL ? | |
4135 | PIN_MAPPABLE : 0); | |
2da3b9b9 | 4136 | if (ret) |
cc98b413 | 4137 | goto err_unpin_display; |
2da3b9b9 | 4138 | |
e62b59e4 | 4139 | i915_gem_object_flush_cpu_write_domain(obj); |
b118c1e3 | 4140 | |
2da3b9b9 | 4141 | old_write_domain = obj->base.write_domain; |
05394f39 | 4142 | old_read_domains = obj->base.read_domains; |
2da3b9b9 CW |
4143 | |
4144 | /* It should now be out of any other write domains, and we can update | |
4145 | * the domain values for our changes. | |
4146 | */ | |
e5f1d962 | 4147 | obj->base.write_domain = 0; |
05394f39 | 4148 | obj->base.read_domains |= I915_GEM_DOMAIN_GTT; |
b9241ea3 ZW |
4149 | |
4150 | trace_i915_gem_object_change_domain(obj, | |
4151 | old_read_domains, | |
2da3b9b9 | 4152 | old_write_domain); |
b9241ea3 ZW |
4153 | |
4154 | return 0; | |
cc98b413 CW |
4155 | |
4156 | err_unpin_display: | |
8a0c39b1 | 4157 | obj->pin_display--; |
cc98b413 CW |
4158 | return ret; |
4159 | } | |
4160 | ||
4161 | void | |
e6617330 TU |
4162 | i915_gem_object_unpin_from_display_plane(struct drm_i915_gem_object *obj, |
4163 | const struct i915_ggtt_view *view) | |
cc98b413 | 4164 | { |
8a0c39b1 TU |
4165 | if (WARN_ON(obj->pin_display == 0)) |
4166 | return; | |
4167 | ||
e6617330 TU |
4168 | i915_gem_object_ggtt_unpin_view(obj, view); |
4169 | ||
8a0c39b1 | 4170 | obj->pin_display--; |
b9241ea3 ZW |
4171 | } |
4172 | ||
e47c68e9 EA |
4173 | /** |
4174 | * Moves a single object to the CPU read, and possibly write domain. | |
4175 | * | |
4176 | * This function returns when the move is complete, including waiting on | |
4177 | * flushes to occur. | |
4178 | */ | |
dabdfe02 | 4179 | int |
919926ae | 4180 | i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write) |
e47c68e9 | 4181 | { |
1c5d22f7 | 4182 | uint32_t old_write_domain, old_read_domains; |
e47c68e9 EA |
4183 | int ret; |
4184 | ||
8d7e3de1 CW |
4185 | if (obj->base.write_domain == I915_GEM_DOMAIN_CPU) |
4186 | return 0; | |
4187 | ||
0201f1ec | 4188 | ret = i915_gem_object_wait_rendering(obj, !write); |
88241785 CW |
4189 | if (ret) |
4190 | return ret; | |
4191 | ||
e47c68e9 | 4192 | i915_gem_object_flush_gtt_write_domain(obj); |
2ef7eeaa | 4193 | |
05394f39 CW |
4194 | old_write_domain = obj->base.write_domain; |
4195 | old_read_domains = obj->base.read_domains; | |
1c5d22f7 | 4196 | |
e47c68e9 | 4197 | /* Flush the CPU cache if it's still invalid. */ |
05394f39 | 4198 | if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0) { |
2c22569b | 4199 | i915_gem_clflush_object(obj, false); |
2ef7eeaa | 4200 | |
05394f39 | 4201 | obj->base.read_domains |= I915_GEM_DOMAIN_CPU; |
2ef7eeaa EA |
4202 | } |
4203 | ||
4204 | /* It should now be out of any other write domains, and we can update | |
4205 | * the domain values for our changes. | |
4206 | */ | |
05394f39 | 4207 | BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_CPU) != 0); |
e47c68e9 EA |
4208 | |
4209 | /* If we're writing through the CPU, then the GPU read domains will | |
4210 | * need to be invalidated at next use. | |
4211 | */ | |
4212 | if (write) { | |
05394f39 CW |
4213 | obj->base.read_domains = I915_GEM_DOMAIN_CPU; |
4214 | obj->base.write_domain = I915_GEM_DOMAIN_CPU; | |
e47c68e9 | 4215 | } |
2ef7eeaa | 4216 | |
f99d7069 | 4217 | if (write) |
a4001f1b | 4218 | intel_fb_obj_invalidate(obj, NULL, ORIGIN_CPU); |
f99d7069 | 4219 | |
1c5d22f7 CW |
4220 | trace_i915_gem_object_change_domain(obj, |
4221 | old_read_domains, | |
4222 | old_write_domain); | |
4223 | ||
2ef7eeaa EA |
4224 | return 0; |
4225 | } | |
4226 | ||
673a394b EA |
4227 | /* Throttle our rendering by waiting until the ring has completed our requests |
4228 | * emitted over 20 msec ago. | |
4229 | * | |
b962442e EA |
4230 | * Note that if we were to use the current jiffies each time around the loop, |
4231 | * we wouldn't escape the function with any frames outstanding if the time to | |
4232 | * render a frame was over 20ms. | |
4233 | * | |
673a394b EA |
4234 | * This should get us reasonable parallelism between CPU and GPU but also |
4235 | * relatively low latency when blocking on a particular request to finish. | |
4236 | */ | |
40a5f0de | 4237 | static int |
f787a5f5 | 4238 | i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file) |
40a5f0de | 4239 | { |
f787a5f5 CW |
4240 | struct drm_i915_private *dev_priv = dev->dev_private; |
4241 | struct drm_i915_file_private *file_priv = file->driver_priv; | |
d0bc54f2 | 4242 | unsigned long recent_enough = jiffies - DRM_I915_THROTTLE_JIFFIES; |
54fb2411 | 4243 | struct drm_i915_gem_request *request, *target = NULL; |
f69061be | 4244 | unsigned reset_counter; |
f787a5f5 | 4245 | int ret; |
93533c29 | 4246 | |
308887aa DV |
4247 | ret = i915_gem_wait_for_error(&dev_priv->gpu_error); |
4248 | if (ret) | |
4249 | return ret; | |
4250 | ||
4251 | ret = i915_gem_check_wedge(&dev_priv->gpu_error, false); | |
4252 | if (ret) | |
4253 | return ret; | |
e110e8d6 | 4254 | |
1c25595f | 4255 | spin_lock(&file_priv->mm.lock); |
f787a5f5 | 4256 | list_for_each_entry(request, &file_priv->mm.request_list, client_list) { |
b962442e EA |
4257 | if (time_after_eq(request->emitted_jiffies, recent_enough)) |
4258 | break; | |
40a5f0de | 4259 | |
54fb2411 | 4260 | target = request; |
b962442e | 4261 | } |
f69061be | 4262 | reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter); |
ff865885 JH |
4263 | if (target) |
4264 | i915_gem_request_reference(target); | |
1c25595f | 4265 | spin_unlock(&file_priv->mm.lock); |
40a5f0de | 4266 | |
54fb2411 | 4267 | if (target == NULL) |
f787a5f5 | 4268 | return 0; |
2bc43b5c | 4269 | |
9c654818 | 4270 | ret = __i915_wait_request(target, reset_counter, true, NULL, NULL); |
f787a5f5 CW |
4271 | if (ret == 0) |
4272 | queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, 0); | |
40a5f0de | 4273 | |
41037f9f | 4274 | i915_gem_request_unreference__unlocked(target); |
ff865885 | 4275 | |
40a5f0de EA |
4276 | return ret; |
4277 | } | |
4278 | ||
d23db88c CW |
4279 | static bool |
4280 | i915_vma_misplaced(struct i915_vma *vma, uint32_t alignment, uint64_t flags) | |
4281 | { | |
4282 | struct drm_i915_gem_object *obj = vma->obj; | |
4283 | ||
4284 | if (alignment && | |
4285 | vma->node.start & (alignment - 1)) | |
4286 | return true; | |
4287 | ||
4288 | if (flags & PIN_MAPPABLE && !obj->map_and_fenceable) | |
4289 | return true; | |
4290 | ||
4291 | if (flags & PIN_OFFSET_BIAS && | |
4292 | vma->node.start < (flags & PIN_OFFSET_MASK)) | |
4293 | return true; | |
4294 | ||
4295 | return false; | |
4296 | } | |
4297 | ||
ec7adb6e JL |
4298 | static int |
4299 | i915_gem_object_do_pin(struct drm_i915_gem_object *obj, | |
4300 | struct i915_address_space *vm, | |
4301 | const struct i915_ggtt_view *ggtt_view, | |
4302 | uint32_t alignment, | |
4303 | uint64_t flags) | |
673a394b | 4304 | { |
6e7186af | 4305 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
07fe0b12 | 4306 | struct i915_vma *vma; |
ef79e17c | 4307 | unsigned bound; |
673a394b EA |
4308 | int ret; |
4309 | ||
6e7186af BW |
4310 | if (WARN_ON(vm == &dev_priv->mm.aliasing_ppgtt->base)) |
4311 | return -ENODEV; | |
4312 | ||
bf3d149b | 4313 | if (WARN_ON(flags & (PIN_GLOBAL | PIN_MAPPABLE) && !i915_is_ggtt(vm))) |
1ec9e26d | 4314 | return -EINVAL; |
07fe0b12 | 4315 | |
c826c449 CW |
4316 | if (WARN_ON((flags & (PIN_MAPPABLE | PIN_GLOBAL)) == PIN_MAPPABLE)) |
4317 | return -EINVAL; | |
4318 | ||
ec7adb6e JL |
4319 | if (WARN_ON(i915_is_ggtt(vm) != !!ggtt_view)) |
4320 | return -EINVAL; | |
4321 | ||
4322 | vma = ggtt_view ? i915_gem_obj_to_ggtt_view(obj, ggtt_view) : | |
4323 | i915_gem_obj_to_vma(obj, vm); | |
4324 | ||
4325 | if (IS_ERR(vma)) | |
4326 | return PTR_ERR(vma); | |
4327 | ||
07fe0b12 | 4328 | if (vma) { |
d7f46fc4 BW |
4329 | if (WARN_ON(vma->pin_count == DRM_I915_GEM_OBJECT_MAX_PIN_COUNT)) |
4330 | return -EBUSY; | |
4331 | ||
d23db88c | 4332 | if (i915_vma_misplaced(vma, alignment, flags)) { |
ec7adb6e | 4333 | unsigned long offset; |
9abc4648 | 4334 | offset = ggtt_view ? i915_gem_obj_ggtt_offset_view(obj, ggtt_view) : |
ec7adb6e | 4335 | i915_gem_obj_offset(obj, vm); |
d7f46fc4 | 4336 | WARN(vma->pin_count, |
ec7adb6e | 4337 | "bo is already pinned in %s with incorrect alignment:" |
f343c5f6 | 4338 | " offset=%lx, req.alignment=%x, req.map_and_fenceable=%d," |
75e9e915 | 4339 | " obj->map_and_fenceable=%d\n", |
ec7adb6e JL |
4340 | ggtt_view ? "ggtt" : "ppgtt", |
4341 | offset, | |
fe14d5f4 | 4342 | alignment, |
d23db88c | 4343 | !!(flags & PIN_MAPPABLE), |
05394f39 | 4344 | obj->map_and_fenceable); |
07fe0b12 | 4345 | ret = i915_vma_unbind(vma); |
ac0c6b5a CW |
4346 | if (ret) |
4347 | return ret; | |
8ea99c92 DV |
4348 | |
4349 | vma = NULL; | |
ac0c6b5a CW |
4350 | } |
4351 | } | |
4352 | ||
ef79e17c | 4353 | bound = vma ? vma->bound : 0; |
8ea99c92 | 4354 | if (vma == NULL || !drm_mm_node_allocated(&vma->node)) { |
ec7adb6e JL |
4355 | vma = i915_gem_object_bind_to_vm(obj, vm, ggtt_view, alignment, |
4356 | flags); | |
262de145 DV |
4357 | if (IS_ERR(vma)) |
4358 | return PTR_ERR(vma); | |
0875546c DV |
4359 | } else { |
4360 | ret = i915_vma_bind(vma, obj->cache_level, flags); | |
fe14d5f4 TU |
4361 | if (ret) |
4362 | return ret; | |
4363 | } | |
74898d7e | 4364 | |
91e6711e JL |
4365 | if (ggtt_view && ggtt_view->type == I915_GGTT_VIEW_NORMAL && |
4366 | (bound ^ vma->bound) & GLOBAL_BIND) { | |
ef79e17c CW |
4367 | bool mappable, fenceable; |
4368 | u32 fence_size, fence_alignment; | |
4369 | ||
4370 | fence_size = i915_gem_get_gtt_size(obj->base.dev, | |
4371 | obj->base.size, | |
4372 | obj->tiling_mode); | |
4373 | fence_alignment = i915_gem_get_gtt_alignment(obj->base.dev, | |
4374 | obj->base.size, | |
4375 | obj->tiling_mode, | |
4376 | true); | |
4377 | ||
4378 | fenceable = (vma->node.size == fence_size && | |
4379 | (vma->node.start & (fence_alignment - 1)) == 0); | |
4380 | ||
e8dec1dd | 4381 | mappable = (vma->node.start + fence_size <= |
ef79e17c CW |
4382 | dev_priv->gtt.mappable_end); |
4383 | ||
4384 | obj->map_and_fenceable = mappable && fenceable; | |
ef79e17c | 4385 | |
91e6711e JL |
4386 | WARN_ON(flags & PIN_MAPPABLE && !obj->map_and_fenceable); |
4387 | } | |
ef79e17c | 4388 | |
8ea99c92 | 4389 | vma->pin_count++; |
673a394b EA |
4390 | return 0; |
4391 | } | |
4392 | ||
ec7adb6e JL |
4393 | int |
4394 | i915_gem_object_pin(struct drm_i915_gem_object *obj, | |
4395 | struct i915_address_space *vm, | |
4396 | uint32_t alignment, | |
4397 | uint64_t flags) | |
4398 | { | |
4399 | return i915_gem_object_do_pin(obj, vm, | |
4400 | i915_is_ggtt(vm) ? &i915_ggtt_view_normal : NULL, | |
4401 | alignment, flags); | |
4402 | } | |
4403 | ||
4404 | int | |
4405 | i915_gem_object_ggtt_pin(struct drm_i915_gem_object *obj, | |
4406 | const struct i915_ggtt_view *view, | |
4407 | uint32_t alignment, | |
4408 | uint64_t flags) | |
4409 | { | |
4410 | if (WARN_ONCE(!view, "no view specified")) | |
4411 | return -EINVAL; | |
4412 | ||
4413 | return i915_gem_object_do_pin(obj, i915_obj_to_ggtt(obj), view, | |
6fafab76 | 4414 | alignment, flags | PIN_GLOBAL); |
ec7adb6e JL |
4415 | } |
4416 | ||
673a394b | 4417 | void |
e6617330 TU |
4418 | i915_gem_object_ggtt_unpin_view(struct drm_i915_gem_object *obj, |
4419 | const struct i915_ggtt_view *view) | |
673a394b | 4420 | { |
e6617330 | 4421 | struct i915_vma *vma = i915_gem_obj_to_ggtt_view(obj, view); |
673a394b | 4422 | |
d7f46fc4 | 4423 | BUG_ON(!vma); |
e6617330 | 4424 | WARN_ON(vma->pin_count == 0); |
9abc4648 | 4425 | WARN_ON(!i915_gem_obj_ggtt_bound_view(obj, view)); |
d7f46fc4 | 4426 | |
30154650 | 4427 | --vma->pin_count; |
673a394b EA |
4428 | } |
4429 | ||
d8ffa60b DV |
4430 | bool |
4431 | i915_gem_object_pin_fence(struct drm_i915_gem_object *obj) | |
4432 | { | |
4433 | if (obj->fence_reg != I915_FENCE_REG_NONE) { | |
4434 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; | |
4435 | struct i915_vma *ggtt_vma = i915_gem_obj_to_ggtt(obj); | |
4436 | ||
4437 | WARN_ON(!ggtt_vma || | |
4438 | dev_priv->fence_regs[obj->fence_reg].pin_count > | |
4439 | ggtt_vma->pin_count); | |
4440 | dev_priv->fence_regs[obj->fence_reg].pin_count++; | |
4441 | return true; | |
4442 | } else | |
4443 | return false; | |
4444 | } | |
4445 | ||
4446 | void | |
4447 | i915_gem_object_unpin_fence(struct drm_i915_gem_object *obj) | |
4448 | { | |
4449 | if (obj->fence_reg != I915_FENCE_REG_NONE) { | |
4450 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; | |
4451 | WARN_ON(dev_priv->fence_regs[obj->fence_reg].pin_count <= 0); | |
4452 | dev_priv->fence_regs[obj->fence_reg].pin_count--; | |
4453 | } | |
4454 | } | |
4455 | ||
673a394b EA |
4456 | int |
4457 | i915_gem_busy_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 4458 | struct drm_file *file) |
673a394b EA |
4459 | { |
4460 | struct drm_i915_gem_busy *args = data; | |
05394f39 | 4461 | struct drm_i915_gem_object *obj; |
30dbf0c0 CW |
4462 | int ret; |
4463 | ||
76c1dec1 | 4464 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 4465 | if (ret) |
76c1dec1 | 4466 | return ret; |
673a394b | 4467 | |
05394f39 | 4468 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 4469 | if (&obj->base == NULL) { |
1d7cfea1 CW |
4470 | ret = -ENOENT; |
4471 | goto unlock; | |
673a394b | 4472 | } |
d1b851fc | 4473 | |
0be555b6 CW |
4474 | /* Count all active objects as busy, even if they are currently not used |
4475 | * by the gpu. Users of this interface expect objects to eventually | |
4476 | * become non-busy without any further actions, therefore emit any | |
4477 | * necessary flushes here. | |
c4de0a5d | 4478 | */ |
30dfebf3 | 4479 | ret = i915_gem_object_flush_active(obj); |
b4716185 CW |
4480 | if (ret) |
4481 | goto unref; | |
0be555b6 | 4482 | |
b4716185 CW |
4483 | BUILD_BUG_ON(I915_NUM_RINGS > 16); |
4484 | args->busy = obj->active << 16; | |
4485 | if (obj->last_write_req) | |
4486 | args->busy |= obj->last_write_req->ring->id; | |
673a394b | 4487 | |
b4716185 | 4488 | unref: |
05394f39 | 4489 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 4490 | unlock: |
673a394b | 4491 | mutex_unlock(&dev->struct_mutex); |
1d7cfea1 | 4492 | return ret; |
673a394b EA |
4493 | } |
4494 | ||
4495 | int | |
4496 | i915_gem_throttle_ioctl(struct drm_device *dev, void *data, | |
4497 | struct drm_file *file_priv) | |
4498 | { | |
0206e353 | 4499 | return i915_gem_ring_throttle(dev, file_priv); |
673a394b EA |
4500 | } |
4501 | ||
3ef94daa CW |
4502 | int |
4503 | i915_gem_madvise_ioctl(struct drm_device *dev, void *data, | |
4504 | struct drm_file *file_priv) | |
4505 | { | |
656bfa3a | 4506 | struct drm_i915_private *dev_priv = dev->dev_private; |
3ef94daa | 4507 | struct drm_i915_gem_madvise *args = data; |
05394f39 | 4508 | struct drm_i915_gem_object *obj; |
76c1dec1 | 4509 | int ret; |
3ef94daa CW |
4510 | |
4511 | switch (args->madv) { | |
4512 | case I915_MADV_DONTNEED: | |
4513 | case I915_MADV_WILLNEED: | |
4514 | break; | |
4515 | default: | |
4516 | return -EINVAL; | |
4517 | } | |
4518 | ||
1d7cfea1 CW |
4519 | ret = i915_mutex_lock_interruptible(dev); |
4520 | if (ret) | |
4521 | return ret; | |
4522 | ||
05394f39 | 4523 | obj = to_intel_bo(drm_gem_object_lookup(dev, file_priv, args->handle)); |
c8725226 | 4524 | if (&obj->base == NULL) { |
1d7cfea1 CW |
4525 | ret = -ENOENT; |
4526 | goto unlock; | |
3ef94daa | 4527 | } |
3ef94daa | 4528 | |
d7f46fc4 | 4529 | if (i915_gem_obj_is_pinned(obj)) { |
1d7cfea1 CW |
4530 | ret = -EINVAL; |
4531 | goto out; | |
3ef94daa CW |
4532 | } |
4533 | ||
656bfa3a DV |
4534 | if (obj->pages && |
4535 | obj->tiling_mode != I915_TILING_NONE && | |
4536 | dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES) { | |
4537 | if (obj->madv == I915_MADV_WILLNEED) | |
4538 | i915_gem_object_unpin_pages(obj); | |
4539 | if (args->madv == I915_MADV_WILLNEED) | |
4540 | i915_gem_object_pin_pages(obj); | |
4541 | } | |
4542 | ||
05394f39 CW |
4543 | if (obj->madv != __I915_MADV_PURGED) |
4544 | obj->madv = args->madv; | |
3ef94daa | 4545 | |
6c085a72 | 4546 | /* if the object is no longer attached, discard its backing storage */ |
be6a0376 | 4547 | if (obj->madv == I915_MADV_DONTNEED && obj->pages == NULL) |
2d7ef395 CW |
4548 | i915_gem_object_truncate(obj); |
4549 | ||
05394f39 | 4550 | args->retained = obj->madv != __I915_MADV_PURGED; |
bb6baf76 | 4551 | |
1d7cfea1 | 4552 | out: |
05394f39 | 4553 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 4554 | unlock: |
3ef94daa | 4555 | mutex_unlock(&dev->struct_mutex); |
1d7cfea1 | 4556 | return ret; |
3ef94daa CW |
4557 | } |
4558 | ||
37e680a1 CW |
4559 | void i915_gem_object_init(struct drm_i915_gem_object *obj, |
4560 | const struct drm_i915_gem_object_ops *ops) | |
0327d6ba | 4561 | { |
b4716185 CW |
4562 | int i; |
4563 | ||
35c20a60 | 4564 | INIT_LIST_HEAD(&obj->global_list); |
b4716185 CW |
4565 | for (i = 0; i < I915_NUM_RINGS; i++) |
4566 | INIT_LIST_HEAD(&obj->ring_list[i]); | |
b25cb2f8 | 4567 | INIT_LIST_HEAD(&obj->obj_exec_link); |
2f633156 | 4568 | INIT_LIST_HEAD(&obj->vma_list); |
8d9d5744 | 4569 | INIT_LIST_HEAD(&obj->batch_pool_link); |
0327d6ba | 4570 | |
37e680a1 CW |
4571 | obj->ops = ops; |
4572 | ||
0327d6ba CW |
4573 | obj->fence_reg = I915_FENCE_REG_NONE; |
4574 | obj->madv = I915_MADV_WILLNEED; | |
0327d6ba CW |
4575 | |
4576 | i915_gem_info_add_obj(obj->base.dev->dev_private, obj->base.size); | |
4577 | } | |
4578 | ||
37e680a1 CW |
4579 | static const struct drm_i915_gem_object_ops i915_gem_object_ops = { |
4580 | .get_pages = i915_gem_object_get_pages_gtt, | |
4581 | .put_pages = i915_gem_object_put_pages_gtt, | |
4582 | }; | |
4583 | ||
05394f39 CW |
4584 | struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev, |
4585 | size_t size) | |
ac52bc56 | 4586 | { |
c397b908 | 4587 | struct drm_i915_gem_object *obj; |
5949eac4 | 4588 | struct address_space *mapping; |
1a240d4d | 4589 | gfp_t mask; |
ac52bc56 | 4590 | |
42dcedd4 | 4591 | obj = i915_gem_object_alloc(dev); |
c397b908 DV |
4592 | if (obj == NULL) |
4593 | return NULL; | |
673a394b | 4594 | |
c397b908 | 4595 | if (drm_gem_object_init(dev, &obj->base, size) != 0) { |
42dcedd4 | 4596 | i915_gem_object_free(obj); |
c397b908 DV |
4597 | return NULL; |
4598 | } | |
673a394b | 4599 | |
bed1ea95 CW |
4600 | mask = GFP_HIGHUSER | __GFP_RECLAIMABLE; |
4601 | if (IS_CRESTLINE(dev) || IS_BROADWATER(dev)) { | |
4602 | /* 965gm cannot relocate objects above 4GiB. */ | |
4603 | mask &= ~__GFP_HIGHMEM; | |
4604 | mask |= __GFP_DMA32; | |
4605 | } | |
4606 | ||
496ad9aa | 4607 | mapping = file_inode(obj->base.filp)->i_mapping; |
bed1ea95 | 4608 | mapping_set_gfp_mask(mapping, mask); |
5949eac4 | 4609 | |
37e680a1 | 4610 | i915_gem_object_init(obj, &i915_gem_object_ops); |
73aa808f | 4611 | |
c397b908 DV |
4612 | obj->base.write_domain = I915_GEM_DOMAIN_CPU; |
4613 | obj->base.read_domains = I915_GEM_DOMAIN_CPU; | |
673a394b | 4614 | |
3d29b842 ED |
4615 | if (HAS_LLC(dev)) { |
4616 | /* On some devices, we can have the GPU use the LLC (the CPU | |
a1871112 EA |
4617 | * cache) for about a 10% performance improvement |
4618 | * compared to uncached. Graphics requests other than | |
4619 | * display scanout are coherent with the CPU in | |
4620 | * accessing this cache. This means in this mode we | |
4621 | * don't need to clflush on the CPU side, and on the | |
4622 | * GPU side we only need to flush internal caches to | |
4623 | * get data visible to the CPU. | |
4624 | * | |
4625 | * However, we maintain the display planes as UC, and so | |
4626 | * need to rebind when first used as such. | |
4627 | */ | |
4628 | obj->cache_level = I915_CACHE_LLC; | |
4629 | } else | |
4630 | obj->cache_level = I915_CACHE_NONE; | |
4631 | ||
d861e338 DV |
4632 | trace_i915_gem_object_create(obj); |
4633 | ||
05394f39 | 4634 | return obj; |
c397b908 DV |
4635 | } |
4636 | ||
340fbd8c CW |
4637 | static bool discard_backing_storage(struct drm_i915_gem_object *obj) |
4638 | { | |
4639 | /* If we are the last user of the backing storage (be it shmemfs | |
4640 | * pages or stolen etc), we know that the pages are going to be | |
4641 | * immediately released. In this case, we can then skip copying | |
4642 | * back the contents from the GPU. | |
4643 | */ | |
4644 | ||
4645 | if (obj->madv != I915_MADV_WILLNEED) | |
4646 | return false; | |
4647 | ||
4648 | if (obj->base.filp == NULL) | |
4649 | return true; | |
4650 | ||
4651 | /* At first glance, this looks racy, but then again so would be | |
4652 | * userspace racing mmap against close. However, the first external | |
4653 | * reference to the filp can only be obtained through the | |
4654 | * i915_gem_mmap_ioctl() which safeguards us against the user | |
4655 | * acquiring such a reference whilst we are in the middle of | |
4656 | * freeing the object. | |
4657 | */ | |
4658 | return atomic_long_read(&obj->base.filp->f_count) == 1; | |
4659 | } | |
4660 | ||
1488fc08 | 4661 | void i915_gem_free_object(struct drm_gem_object *gem_obj) |
673a394b | 4662 | { |
1488fc08 | 4663 | struct drm_i915_gem_object *obj = to_intel_bo(gem_obj); |
05394f39 | 4664 | struct drm_device *dev = obj->base.dev; |
3e31c6c0 | 4665 | struct drm_i915_private *dev_priv = dev->dev_private; |
07fe0b12 | 4666 | struct i915_vma *vma, *next; |
673a394b | 4667 | |
f65c9168 PZ |
4668 | intel_runtime_pm_get(dev_priv); |
4669 | ||
26e12f89 CW |
4670 | trace_i915_gem_object_destroy(obj); |
4671 | ||
07fe0b12 | 4672 | list_for_each_entry_safe(vma, next, &obj->vma_list, vma_link) { |
d7f46fc4 BW |
4673 | int ret; |
4674 | ||
4675 | vma->pin_count = 0; | |
4676 | ret = i915_vma_unbind(vma); | |
07fe0b12 BW |
4677 | if (WARN_ON(ret == -ERESTARTSYS)) { |
4678 | bool was_interruptible; | |
1488fc08 | 4679 | |
07fe0b12 BW |
4680 | was_interruptible = dev_priv->mm.interruptible; |
4681 | dev_priv->mm.interruptible = false; | |
1488fc08 | 4682 | |
07fe0b12 | 4683 | WARN_ON(i915_vma_unbind(vma)); |
1488fc08 | 4684 | |
07fe0b12 BW |
4685 | dev_priv->mm.interruptible = was_interruptible; |
4686 | } | |
1488fc08 CW |
4687 | } |
4688 | ||
1d64ae71 BW |
4689 | /* Stolen objects don't hold a ref, but do hold pin count. Fix that up |
4690 | * before progressing. */ | |
4691 | if (obj->stolen) | |
4692 | i915_gem_object_unpin_pages(obj); | |
4693 | ||
a071fa00 DV |
4694 | WARN_ON(obj->frontbuffer_bits); |
4695 | ||
656bfa3a DV |
4696 | if (obj->pages && obj->madv == I915_MADV_WILLNEED && |
4697 | dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES && | |
4698 | obj->tiling_mode != I915_TILING_NONE) | |
4699 | i915_gem_object_unpin_pages(obj); | |
4700 | ||
401c29f6 BW |
4701 | if (WARN_ON(obj->pages_pin_count)) |
4702 | obj->pages_pin_count = 0; | |
340fbd8c | 4703 | if (discard_backing_storage(obj)) |
5537252b | 4704 | obj->madv = I915_MADV_DONTNEED; |
37e680a1 | 4705 | i915_gem_object_put_pages(obj); |
d8cb5086 | 4706 | i915_gem_object_free_mmap_offset(obj); |
de151cf6 | 4707 | |
9da3da66 CW |
4708 | BUG_ON(obj->pages); |
4709 | ||
2f745ad3 CW |
4710 | if (obj->base.import_attach) |
4711 | drm_prime_gem_destroy(&obj->base, NULL); | |
de151cf6 | 4712 | |
5cc9ed4b CW |
4713 | if (obj->ops->release) |
4714 | obj->ops->release(obj); | |
4715 | ||
05394f39 CW |
4716 | drm_gem_object_release(&obj->base); |
4717 | i915_gem_info_remove_obj(dev_priv, obj->base.size); | |
c397b908 | 4718 | |
05394f39 | 4719 | kfree(obj->bit_17); |
42dcedd4 | 4720 | i915_gem_object_free(obj); |
f65c9168 PZ |
4721 | |
4722 | intel_runtime_pm_put(dev_priv); | |
673a394b EA |
4723 | } |
4724 | ||
ec7adb6e JL |
4725 | struct i915_vma *i915_gem_obj_to_vma(struct drm_i915_gem_object *obj, |
4726 | struct i915_address_space *vm) | |
e656a6cb DV |
4727 | { |
4728 | struct i915_vma *vma; | |
ec7adb6e JL |
4729 | list_for_each_entry(vma, &obj->vma_list, vma_link) { |
4730 | if (i915_is_ggtt(vma->vm) && | |
4731 | vma->ggtt_view.type != I915_GGTT_VIEW_NORMAL) | |
4732 | continue; | |
4733 | if (vma->vm == vm) | |
e656a6cb | 4734 | return vma; |
ec7adb6e JL |
4735 | } |
4736 | return NULL; | |
4737 | } | |
4738 | ||
4739 | struct i915_vma *i915_gem_obj_to_ggtt_view(struct drm_i915_gem_object *obj, | |
4740 | const struct i915_ggtt_view *view) | |
4741 | { | |
4742 | struct i915_address_space *ggtt = i915_obj_to_ggtt(obj); | |
4743 | struct i915_vma *vma; | |
e656a6cb | 4744 | |
ec7adb6e JL |
4745 | if (WARN_ONCE(!view, "no view specified")) |
4746 | return ERR_PTR(-EINVAL); | |
4747 | ||
4748 | list_for_each_entry(vma, &obj->vma_list, vma_link) | |
9abc4648 JL |
4749 | if (vma->vm == ggtt && |
4750 | i915_ggtt_view_equal(&vma->ggtt_view, view)) | |
ec7adb6e | 4751 | return vma; |
e656a6cb DV |
4752 | return NULL; |
4753 | } | |
4754 | ||
2f633156 BW |
4755 | void i915_gem_vma_destroy(struct i915_vma *vma) |
4756 | { | |
b9d06dd9 | 4757 | struct i915_address_space *vm = NULL; |
2f633156 | 4758 | WARN_ON(vma->node.allocated); |
aaa05667 CW |
4759 | |
4760 | /* Keep the vma as a placeholder in the execbuffer reservation lists */ | |
4761 | if (!list_empty(&vma->exec_list)) | |
4762 | return; | |
4763 | ||
b9d06dd9 | 4764 | vm = vma->vm; |
b9d06dd9 | 4765 | |
841cd773 DV |
4766 | if (!i915_is_ggtt(vm)) |
4767 | i915_ppgtt_put(i915_vm_to_ppgtt(vm)); | |
b9d06dd9 | 4768 | |
8b9c2b94 | 4769 | list_del(&vma->vma_link); |
b93dab6e | 4770 | |
e20d2ab7 | 4771 | kmem_cache_free(to_i915(vma->obj->base.dev)->vmas, vma); |
2f633156 BW |
4772 | } |
4773 | ||
e3efda49 CW |
4774 | static void |
4775 | i915_gem_stop_ringbuffers(struct drm_device *dev) | |
4776 | { | |
4777 | struct drm_i915_private *dev_priv = dev->dev_private; | |
a4872ba6 | 4778 | struct intel_engine_cs *ring; |
e3efda49 CW |
4779 | int i; |
4780 | ||
4781 | for_each_ring(ring, dev_priv, i) | |
a83014d3 | 4782 | dev_priv->gt.stop_ring(ring); |
e3efda49 CW |
4783 | } |
4784 | ||
29105ccc | 4785 | int |
45c5f202 | 4786 | i915_gem_suspend(struct drm_device *dev) |
29105ccc | 4787 | { |
3e31c6c0 | 4788 | struct drm_i915_private *dev_priv = dev->dev_private; |
45c5f202 | 4789 | int ret = 0; |
28dfe52a | 4790 | |
45c5f202 | 4791 | mutex_lock(&dev->struct_mutex); |
b2da9fe5 | 4792 | ret = i915_gpu_idle(dev); |
f7403347 | 4793 | if (ret) |
45c5f202 | 4794 | goto err; |
f7403347 | 4795 | |
b2da9fe5 | 4796 | i915_gem_retire_requests(dev); |
673a394b | 4797 | |
e3efda49 | 4798 | i915_gem_stop_ringbuffers(dev); |
45c5f202 CW |
4799 | mutex_unlock(&dev->struct_mutex); |
4800 | ||
737b1506 | 4801 | cancel_delayed_work_sync(&dev_priv->gpu_error.hangcheck_work); |
29105ccc | 4802 | cancel_delayed_work_sync(&dev_priv->mm.retire_work); |
274fa1c1 | 4803 | flush_delayed_work(&dev_priv->mm.idle_work); |
29105ccc | 4804 | |
bdcf120b CW |
4805 | /* Assert that we sucessfully flushed all the work and |
4806 | * reset the GPU back to its idle, low power state. | |
4807 | */ | |
4808 | WARN_ON(dev_priv->mm.busy); | |
4809 | ||
673a394b | 4810 | return 0; |
45c5f202 CW |
4811 | |
4812 | err: | |
4813 | mutex_unlock(&dev->struct_mutex); | |
4814 | return ret; | |
673a394b EA |
4815 | } |
4816 | ||
a4872ba6 | 4817 | int i915_gem_l3_remap(struct intel_engine_cs *ring, int slice) |
b9524a1e | 4818 | { |
c3787e2e | 4819 | struct drm_device *dev = ring->dev; |
3e31c6c0 | 4820 | struct drm_i915_private *dev_priv = dev->dev_private; |
35a85ac6 BW |
4821 | u32 reg_base = GEN7_L3LOG_BASE + (slice * 0x200); |
4822 | u32 *remap_info = dev_priv->l3_parity.remap_info[slice]; | |
c3787e2e | 4823 | int i, ret; |
b9524a1e | 4824 | |
040d2baa | 4825 | if (!HAS_L3_DPF(dev) || !remap_info) |
c3787e2e | 4826 | return 0; |
b9524a1e | 4827 | |
c3787e2e BW |
4828 | ret = intel_ring_begin(ring, GEN7_L3LOG_SIZE / 4 * 3); |
4829 | if (ret) | |
4830 | return ret; | |
b9524a1e | 4831 | |
c3787e2e BW |
4832 | /* |
4833 | * Note: We do not worry about the concurrent register cacheline hang | |
4834 | * here because no other code should access these registers other than | |
4835 | * at initialization time. | |
4836 | */ | |
b9524a1e | 4837 | for (i = 0; i < GEN7_L3LOG_SIZE; i += 4) { |
c3787e2e BW |
4838 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); |
4839 | intel_ring_emit(ring, reg_base + i); | |
4840 | intel_ring_emit(ring, remap_info[i/4]); | |
b9524a1e BW |
4841 | } |
4842 | ||
c3787e2e | 4843 | intel_ring_advance(ring); |
b9524a1e | 4844 | |
c3787e2e | 4845 | return ret; |
b9524a1e BW |
4846 | } |
4847 | ||
f691e2f4 DV |
4848 | void i915_gem_init_swizzling(struct drm_device *dev) |
4849 | { | |
3e31c6c0 | 4850 | struct drm_i915_private *dev_priv = dev->dev_private; |
f691e2f4 | 4851 | |
11782b02 | 4852 | if (INTEL_INFO(dev)->gen < 5 || |
f691e2f4 DV |
4853 | dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_NONE) |
4854 | return; | |
4855 | ||
4856 | I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) | | |
4857 | DISP_TILE_SURFACE_SWIZZLING); | |
4858 | ||
11782b02 DV |
4859 | if (IS_GEN5(dev)) |
4860 | return; | |
4861 | ||
f691e2f4 DV |
4862 | I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_SWZCTL); |
4863 | if (IS_GEN6(dev)) | |
6b26c86d | 4864 | I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB)); |
8782e26c | 4865 | else if (IS_GEN7(dev)) |
6b26c86d | 4866 | I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB)); |
31a5336e BW |
4867 | else if (IS_GEN8(dev)) |
4868 | I915_WRITE(GAMTARBMODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_BDW)); | |
8782e26c BW |
4869 | else |
4870 | BUG(); | |
f691e2f4 | 4871 | } |
e21af88d | 4872 | |
67b1b571 CW |
4873 | static bool |
4874 | intel_enable_blt(struct drm_device *dev) | |
4875 | { | |
4876 | if (!HAS_BLT(dev)) | |
4877 | return false; | |
4878 | ||
4879 | /* The blitter was dysfunctional on early prototypes */ | |
4880 | if (IS_GEN6(dev) && dev->pdev->revision < 8) { | |
4881 | DRM_INFO("BLT not supported on this pre-production hardware;" | |
4882 | " graphics performance will be degraded.\n"); | |
4883 | return false; | |
4884 | } | |
4885 | ||
4886 | return true; | |
4887 | } | |
4888 | ||
81e7f200 VS |
4889 | static void init_unused_ring(struct drm_device *dev, u32 base) |
4890 | { | |
4891 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4892 | ||
4893 | I915_WRITE(RING_CTL(base), 0); | |
4894 | I915_WRITE(RING_HEAD(base), 0); | |
4895 | I915_WRITE(RING_TAIL(base), 0); | |
4896 | I915_WRITE(RING_START(base), 0); | |
4897 | } | |
4898 | ||
4899 | static void init_unused_rings(struct drm_device *dev) | |
4900 | { | |
4901 | if (IS_I830(dev)) { | |
4902 | init_unused_ring(dev, PRB1_BASE); | |
4903 | init_unused_ring(dev, SRB0_BASE); | |
4904 | init_unused_ring(dev, SRB1_BASE); | |
4905 | init_unused_ring(dev, SRB2_BASE); | |
4906 | init_unused_ring(dev, SRB3_BASE); | |
4907 | } else if (IS_GEN2(dev)) { | |
4908 | init_unused_ring(dev, SRB0_BASE); | |
4909 | init_unused_ring(dev, SRB1_BASE); | |
4910 | } else if (IS_GEN3(dev)) { | |
4911 | init_unused_ring(dev, PRB1_BASE); | |
4912 | init_unused_ring(dev, PRB2_BASE); | |
4913 | } | |
4914 | } | |
4915 | ||
a83014d3 | 4916 | int i915_gem_init_rings(struct drm_device *dev) |
8187a2b7 | 4917 | { |
4fc7c971 | 4918 | struct drm_i915_private *dev_priv = dev->dev_private; |
8187a2b7 | 4919 | int ret; |
68f95ba9 | 4920 | |
5c1143bb | 4921 | ret = intel_init_render_ring_buffer(dev); |
68f95ba9 | 4922 | if (ret) |
b6913e4b | 4923 | return ret; |
68f95ba9 CW |
4924 | |
4925 | if (HAS_BSD(dev)) { | |
5c1143bb | 4926 | ret = intel_init_bsd_ring_buffer(dev); |
68f95ba9 CW |
4927 | if (ret) |
4928 | goto cleanup_render_ring; | |
d1b851fc | 4929 | } |
68f95ba9 | 4930 | |
67b1b571 | 4931 | if (intel_enable_blt(dev)) { |
549f7365 CW |
4932 | ret = intel_init_blt_ring_buffer(dev); |
4933 | if (ret) | |
4934 | goto cleanup_bsd_ring; | |
4935 | } | |
4936 | ||
9a8a2213 BW |
4937 | if (HAS_VEBOX(dev)) { |
4938 | ret = intel_init_vebox_ring_buffer(dev); | |
4939 | if (ret) | |
4940 | goto cleanup_blt_ring; | |
4941 | } | |
4942 | ||
845f74a7 ZY |
4943 | if (HAS_BSD2(dev)) { |
4944 | ret = intel_init_bsd2_ring_buffer(dev); | |
4945 | if (ret) | |
4946 | goto cleanup_vebox_ring; | |
4947 | } | |
9a8a2213 | 4948 | |
99433931 | 4949 | ret = i915_gem_set_seqno(dev, ((u32)~0 - 0x1000)); |
4fc7c971 | 4950 | if (ret) |
845f74a7 | 4951 | goto cleanup_bsd2_ring; |
4fc7c971 BW |
4952 | |
4953 | return 0; | |
4954 | ||
845f74a7 ZY |
4955 | cleanup_bsd2_ring: |
4956 | intel_cleanup_ring_buffer(&dev_priv->ring[VCS2]); | |
9a8a2213 BW |
4957 | cleanup_vebox_ring: |
4958 | intel_cleanup_ring_buffer(&dev_priv->ring[VECS]); | |
4fc7c971 BW |
4959 | cleanup_blt_ring: |
4960 | intel_cleanup_ring_buffer(&dev_priv->ring[BCS]); | |
4961 | cleanup_bsd_ring: | |
4962 | intel_cleanup_ring_buffer(&dev_priv->ring[VCS]); | |
4963 | cleanup_render_ring: | |
4964 | intel_cleanup_ring_buffer(&dev_priv->ring[RCS]); | |
4965 | ||
4966 | return ret; | |
4967 | } | |
4968 | ||
4969 | int | |
4970 | i915_gem_init_hw(struct drm_device *dev) | |
4971 | { | |
3e31c6c0 | 4972 | struct drm_i915_private *dev_priv = dev->dev_private; |
35a57ffb | 4973 | struct intel_engine_cs *ring; |
35a85ac6 | 4974 | int ret, i; |
4fc7c971 BW |
4975 | |
4976 | if (INTEL_INFO(dev)->gen < 6 && !intel_enable_gtt()) | |
4977 | return -EIO; | |
4978 | ||
5e4f5189 CW |
4979 | /* Double layer security blanket, see i915_gem_init() */ |
4980 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); | |
4981 | ||
59124506 | 4982 | if (dev_priv->ellc_size) |
05e21cc4 | 4983 | I915_WRITE(HSW_IDICR, I915_READ(HSW_IDICR) | IDIHASHMSK(0xf)); |
4fc7c971 | 4984 | |
0bf21347 VS |
4985 | if (IS_HASWELL(dev)) |
4986 | I915_WRITE(MI_PREDICATE_RESULT_2, IS_HSW_GT3(dev) ? | |
4987 | LOWER_SLICE_ENABLED : LOWER_SLICE_DISABLED); | |
9435373e | 4988 | |
88a2b2a3 | 4989 | if (HAS_PCH_NOP(dev)) { |
6ba844b0 DV |
4990 | if (IS_IVYBRIDGE(dev)) { |
4991 | u32 temp = I915_READ(GEN7_MSG_CTL); | |
4992 | temp &= ~(WAIT_FOR_PCH_FLR_ACK | WAIT_FOR_PCH_RESET_ACK); | |
4993 | I915_WRITE(GEN7_MSG_CTL, temp); | |
4994 | } else if (INTEL_INFO(dev)->gen >= 7) { | |
4995 | u32 temp = I915_READ(HSW_NDE_RSTWRN_OPT); | |
4996 | temp &= ~RESET_PCH_HANDSHAKE_ENABLE; | |
4997 | I915_WRITE(HSW_NDE_RSTWRN_OPT, temp); | |
4998 | } | |
88a2b2a3 BW |
4999 | } |
5000 | ||
4fc7c971 BW |
5001 | i915_gem_init_swizzling(dev); |
5002 | ||
d5abdfda DV |
5003 | /* |
5004 | * At least 830 can leave some of the unused rings | |
5005 | * "active" (ie. head != tail) after resume which | |
5006 | * will prevent c3 entry. Makes sure all unused rings | |
5007 | * are totally idle. | |
5008 | */ | |
5009 | init_unused_rings(dev); | |
5010 | ||
35a57ffb DV |
5011 | for_each_ring(ring, dev_priv, i) { |
5012 | ret = ring->init_hw(ring); | |
5013 | if (ret) | |
5e4f5189 | 5014 | goto out; |
35a57ffb | 5015 | } |
99433931 | 5016 | |
c3787e2e BW |
5017 | for (i = 0; i < NUM_L3_SLICES(dev); i++) |
5018 | i915_gem_l3_remap(&dev_priv->ring[RCS], i); | |
5019 | ||
f48a0165 | 5020 | ret = i915_ppgtt_init_hw(dev); |
60990320 | 5021 | if (ret && ret != -EIO) { |
f48a0165 | 5022 | DRM_ERROR("PPGTT enable failed %d\n", ret); |
60990320 | 5023 | i915_gem_cleanup_ringbuffer(dev); |
82460d97 DV |
5024 | } |
5025 | ||
f48a0165 | 5026 | ret = i915_gem_context_enable(dev_priv); |
82460d97 | 5027 | if (ret && ret != -EIO) { |
f48a0165 | 5028 | DRM_ERROR("Context enable failed %d\n", ret); |
82460d97 | 5029 | i915_gem_cleanup_ringbuffer(dev); |
f48a0165 | 5030 | |
5e4f5189 | 5031 | goto out; |
b7c36d25 | 5032 | } |
e21af88d | 5033 | |
5e4f5189 CW |
5034 | out: |
5035 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); | |
2fa48d8d | 5036 | return ret; |
8187a2b7 ZN |
5037 | } |
5038 | ||
1070a42b CW |
5039 | int i915_gem_init(struct drm_device *dev) |
5040 | { | |
5041 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1070a42b CW |
5042 | int ret; |
5043 | ||
127f1003 OM |
5044 | i915.enable_execlists = intel_sanitize_enable_execlists(dev, |
5045 | i915.enable_execlists); | |
5046 | ||
1070a42b | 5047 | mutex_lock(&dev->struct_mutex); |
d62b4892 JB |
5048 | |
5049 | if (IS_VALLEYVIEW(dev)) { | |
5050 | /* VLVA0 (potential hack), BIOS isn't actually waking us */ | |
981a5aea ID |
5051 | I915_WRITE(VLV_GTLC_WAKE_CTRL, VLV_GTLC_ALLOWWAKEREQ); |
5052 | if (wait_for((I915_READ(VLV_GTLC_PW_STATUS) & | |
5053 | VLV_GTLC_ALLOWWAKEACK), 10)) | |
d62b4892 JB |
5054 | DRM_DEBUG_DRIVER("allow wake ack timed out\n"); |
5055 | } | |
5056 | ||
a83014d3 | 5057 | if (!i915.enable_execlists) { |
f3dc74c0 | 5058 | dev_priv->gt.execbuf_submit = i915_gem_ringbuffer_submission; |
a83014d3 OM |
5059 | dev_priv->gt.init_rings = i915_gem_init_rings; |
5060 | dev_priv->gt.cleanup_ring = intel_cleanup_ring_buffer; | |
5061 | dev_priv->gt.stop_ring = intel_stop_ring_buffer; | |
454afebd | 5062 | } else { |
f3dc74c0 | 5063 | dev_priv->gt.execbuf_submit = intel_execlists_submission; |
454afebd OM |
5064 | dev_priv->gt.init_rings = intel_logical_rings_init; |
5065 | dev_priv->gt.cleanup_ring = intel_logical_ring_cleanup; | |
5066 | dev_priv->gt.stop_ring = intel_logical_ring_stop; | |
a83014d3 OM |
5067 | } |
5068 | ||
5e4f5189 CW |
5069 | /* This is just a security blanket to placate dragons. |
5070 | * On some systems, we very sporadically observe that the first TLBs | |
5071 | * used by the CS may be stale, despite us poking the TLB reset. If | |
5072 | * we hold the forcewake during initialisation these problems | |
5073 | * just magically go away. | |
5074 | */ | |
5075 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); | |
5076 | ||
6c5566a8 | 5077 | ret = i915_gem_init_userptr(dev); |
7bcc3777 JN |
5078 | if (ret) |
5079 | goto out_unlock; | |
6c5566a8 | 5080 | |
d7e5008f | 5081 | i915_gem_init_global_gtt(dev); |
d62b4892 | 5082 | |
2fa48d8d | 5083 | ret = i915_gem_context_init(dev); |
7bcc3777 JN |
5084 | if (ret) |
5085 | goto out_unlock; | |
2fa48d8d | 5086 | |
35a57ffb DV |
5087 | ret = dev_priv->gt.init_rings(dev); |
5088 | if (ret) | |
7bcc3777 | 5089 | goto out_unlock; |
2fa48d8d | 5090 | |
1070a42b | 5091 | ret = i915_gem_init_hw(dev); |
60990320 CW |
5092 | if (ret == -EIO) { |
5093 | /* Allow ring initialisation to fail by marking the GPU as | |
5094 | * wedged. But we only want to do this where the GPU is angry, | |
5095 | * for all other failure, such as an allocation failure, bail. | |
5096 | */ | |
5097 | DRM_ERROR("Failed to initialize GPU, declaring it wedged\n"); | |
5098 | atomic_set_mask(I915_WEDGED, &dev_priv->gpu_error.reset_counter); | |
5099 | ret = 0; | |
1070a42b | 5100 | } |
7bcc3777 JN |
5101 | |
5102 | out_unlock: | |
5e4f5189 | 5103 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); |
60990320 | 5104 | mutex_unlock(&dev->struct_mutex); |
1070a42b | 5105 | |
60990320 | 5106 | return ret; |
1070a42b CW |
5107 | } |
5108 | ||
8187a2b7 ZN |
5109 | void |
5110 | i915_gem_cleanup_ringbuffer(struct drm_device *dev) | |
5111 | { | |
3e31c6c0 | 5112 | struct drm_i915_private *dev_priv = dev->dev_private; |
a4872ba6 | 5113 | struct intel_engine_cs *ring; |
1ec14ad3 | 5114 | int i; |
8187a2b7 | 5115 | |
b4519513 | 5116 | for_each_ring(ring, dev_priv, i) |
a83014d3 | 5117 | dev_priv->gt.cleanup_ring(ring); |
8187a2b7 ZN |
5118 | } |
5119 | ||
64193406 | 5120 | static void |
a4872ba6 | 5121 | init_ring_lists(struct intel_engine_cs *ring) |
64193406 CW |
5122 | { |
5123 | INIT_LIST_HEAD(&ring->active_list); | |
5124 | INIT_LIST_HEAD(&ring->request_list); | |
64193406 CW |
5125 | } |
5126 | ||
7e0d96bc BW |
5127 | void i915_init_vm(struct drm_i915_private *dev_priv, |
5128 | struct i915_address_space *vm) | |
fc8c067e | 5129 | { |
7e0d96bc BW |
5130 | if (!i915_is_ggtt(vm)) |
5131 | drm_mm_init(&vm->mm, vm->start, vm->total); | |
fc8c067e BW |
5132 | vm->dev = dev_priv->dev; |
5133 | INIT_LIST_HEAD(&vm->active_list); | |
5134 | INIT_LIST_HEAD(&vm->inactive_list); | |
5135 | INIT_LIST_HEAD(&vm->global_link); | |
f72d21ed | 5136 | list_add_tail(&vm->global_link, &dev_priv->vm_list); |
fc8c067e BW |
5137 | } |
5138 | ||
673a394b EA |
5139 | void |
5140 | i915_gem_load(struct drm_device *dev) | |
5141 | { | |
3e31c6c0 | 5142 | struct drm_i915_private *dev_priv = dev->dev_private; |
42dcedd4 CW |
5143 | int i; |
5144 | ||
efab6d8d | 5145 | dev_priv->objects = |
42dcedd4 CW |
5146 | kmem_cache_create("i915_gem_object", |
5147 | sizeof(struct drm_i915_gem_object), 0, | |
5148 | SLAB_HWCACHE_ALIGN, | |
5149 | NULL); | |
e20d2ab7 CW |
5150 | dev_priv->vmas = |
5151 | kmem_cache_create("i915_gem_vma", | |
5152 | sizeof(struct i915_vma), 0, | |
5153 | SLAB_HWCACHE_ALIGN, | |
5154 | NULL); | |
efab6d8d CW |
5155 | dev_priv->requests = |
5156 | kmem_cache_create("i915_gem_request", | |
5157 | sizeof(struct drm_i915_gem_request), 0, | |
5158 | SLAB_HWCACHE_ALIGN, | |
5159 | NULL); | |
673a394b | 5160 | |
fc8c067e BW |
5161 | INIT_LIST_HEAD(&dev_priv->vm_list); |
5162 | i915_init_vm(dev_priv, &dev_priv->gtt.base); | |
5163 | ||
a33afea5 | 5164 | INIT_LIST_HEAD(&dev_priv->context_list); |
6c085a72 CW |
5165 | INIT_LIST_HEAD(&dev_priv->mm.unbound_list); |
5166 | INIT_LIST_HEAD(&dev_priv->mm.bound_list); | |
a09ba7fa | 5167 | INIT_LIST_HEAD(&dev_priv->mm.fence_list); |
1ec14ad3 CW |
5168 | for (i = 0; i < I915_NUM_RINGS; i++) |
5169 | init_ring_lists(&dev_priv->ring[i]); | |
4b9de737 | 5170 | for (i = 0; i < I915_MAX_NUM_FENCES; i++) |
007cc8ac | 5171 | INIT_LIST_HEAD(&dev_priv->fence_regs[i].lru_list); |
673a394b EA |
5172 | INIT_DELAYED_WORK(&dev_priv->mm.retire_work, |
5173 | i915_gem_retire_work_handler); | |
b29c19b6 CW |
5174 | INIT_DELAYED_WORK(&dev_priv->mm.idle_work, |
5175 | i915_gem_idle_work_handler); | |
1f83fee0 | 5176 | init_waitqueue_head(&dev_priv->gpu_error.reset_queue); |
31169714 | 5177 | |
72bfa19c CW |
5178 | dev_priv->relative_constants_mode = I915_EXEC_CONSTANTS_REL_GENERAL; |
5179 | ||
42b5aeab VS |
5180 | if (INTEL_INFO(dev)->gen >= 7 && !IS_VALLEYVIEW(dev)) |
5181 | dev_priv->num_fence_regs = 32; | |
5182 | else if (INTEL_INFO(dev)->gen >= 4 || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) | |
de151cf6 JB |
5183 | dev_priv->num_fence_regs = 16; |
5184 | else | |
5185 | dev_priv->num_fence_regs = 8; | |
5186 | ||
eb82289a YZ |
5187 | if (intel_vgpu_active(dev)) |
5188 | dev_priv->num_fence_regs = | |
5189 | I915_READ(vgtif_reg(avail_rs.fence_num)); | |
5190 | ||
b5aa8a0f | 5191 | /* Initialize fence registers to zero */ |
19b2dbde CW |
5192 | INIT_LIST_HEAD(&dev_priv->mm.fence_list); |
5193 | i915_gem_restore_fences(dev); | |
10ed13e4 | 5194 | |
673a394b | 5195 | i915_gem_detect_bit_6_swizzle(dev); |
6b95a207 | 5196 | init_waitqueue_head(&dev_priv->pending_flip_queue); |
17250b71 | 5197 | |
ce453d81 CW |
5198 | dev_priv->mm.interruptible = true; |
5199 | ||
be6a0376 | 5200 | i915_gem_shrinker_init(dev_priv); |
f99d7069 DV |
5201 | |
5202 | mutex_init(&dev_priv->fb_tracking.lock); | |
673a394b | 5203 | } |
71acb5eb | 5204 | |
f787a5f5 | 5205 | void i915_gem_release(struct drm_device *dev, struct drm_file *file) |
b962442e | 5206 | { |
f787a5f5 | 5207 | struct drm_i915_file_private *file_priv = file->driver_priv; |
b962442e EA |
5208 | |
5209 | /* Clean up our request list when the client is going away, so that | |
5210 | * later retire_requests won't dereference our soon-to-be-gone | |
5211 | * file_priv. | |
5212 | */ | |
1c25595f | 5213 | spin_lock(&file_priv->mm.lock); |
f787a5f5 CW |
5214 | while (!list_empty(&file_priv->mm.request_list)) { |
5215 | struct drm_i915_gem_request *request; | |
5216 | ||
5217 | request = list_first_entry(&file_priv->mm.request_list, | |
5218 | struct drm_i915_gem_request, | |
5219 | client_list); | |
5220 | list_del(&request->client_list); | |
5221 | request->file_priv = NULL; | |
5222 | } | |
1c25595f | 5223 | spin_unlock(&file_priv->mm.lock); |
b29c19b6 | 5224 | |
2e1b8730 | 5225 | if (!list_empty(&file_priv->rps.link)) { |
8d3afd7d | 5226 | spin_lock(&to_i915(dev)->rps.client_lock); |
2e1b8730 | 5227 | list_del(&file_priv->rps.link); |
8d3afd7d | 5228 | spin_unlock(&to_i915(dev)->rps.client_lock); |
1854d5ca | 5229 | } |
b29c19b6 CW |
5230 | } |
5231 | ||
5232 | int i915_gem_open(struct drm_device *dev, struct drm_file *file) | |
5233 | { | |
5234 | struct drm_i915_file_private *file_priv; | |
e422b888 | 5235 | int ret; |
b29c19b6 CW |
5236 | |
5237 | DRM_DEBUG_DRIVER("\n"); | |
5238 | ||
5239 | file_priv = kzalloc(sizeof(*file_priv), GFP_KERNEL); | |
5240 | if (!file_priv) | |
5241 | return -ENOMEM; | |
5242 | ||
5243 | file->driver_priv = file_priv; | |
5244 | file_priv->dev_priv = dev->dev_private; | |
ab0e7ff9 | 5245 | file_priv->file = file; |
2e1b8730 | 5246 | INIT_LIST_HEAD(&file_priv->rps.link); |
b29c19b6 CW |
5247 | |
5248 | spin_lock_init(&file_priv->mm.lock); | |
5249 | INIT_LIST_HEAD(&file_priv->mm.request_list); | |
b29c19b6 | 5250 | |
e422b888 BW |
5251 | ret = i915_gem_context_open(dev, file); |
5252 | if (ret) | |
5253 | kfree(file_priv); | |
b29c19b6 | 5254 | |
e422b888 | 5255 | return ret; |
b29c19b6 CW |
5256 | } |
5257 | ||
b680c37a DV |
5258 | /** |
5259 | * i915_gem_track_fb - update frontbuffer tracking | |
5260 | * old: current GEM buffer for the frontbuffer slots | |
5261 | * new: new GEM buffer for the frontbuffer slots | |
5262 | * frontbuffer_bits: bitmask of frontbuffer slots | |
5263 | * | |
5264 | * This updates the frontbuffer tracking bits @frontbuffer_bits by clearing them | |
5265 | * from @old and setting them in @new. Both @old and @new can be NULL. | |
5266 | */ | |
a071fa00 DV |
5267 | void i915_gem_track_fb(struct drm_i915_gem_object *old, |
5268 | struct drm_i915_gem_object *new, | |
5269 | unsigned frontbuffer_bits) | |
5270 | { | |
5271 | if (old) { | |
5272 | WARN_ON(!mutex_is_locked(&old->base.dev->struct_mutex)); | |
5273 | WARN_ON(!(old->frontbuffer_bits & frontbuffer_bits)); | |
5274 | old->frontbuffer_bits &= ~frontbuffer_bits; | |
5275 | } | |
5276 | ||
5277 | if (new) { | |
5278 | WARN_ON(!mutex_is_locked(&new->base.dev->struct_mutex)); | |
5279 | WARN_ON(new->frontbuffer_bits & frontbuffer_bits); | |
5280 | new->frontbuffer_bits |= frontbuffer_bits; | |
5281 | } | |
5282 | } | |
5283 | ||
a70a3148 | 5284 | /* All the new VM stuff */ |
ec7adb6e JL |
5285 | unsigned long |
5286 | i915_gem_obj_offset(struct drm_i915_gem_object *o, | |
5287 | struct i915_address_space *vm) | |
a70a3148 BW |
5288 | { |
5289 | struct drm_i915_private *dev_priv = o->base.dev->dev_private; | |
5290 | struct i915_vma *vma; | |
5291 | ||
896ab1a5 | 5292 | WARN_ON(vm == &dev_priv->mm.aliasing_ppgtt->base); |
a70a3148 | 5293 | |
a70a3148 | 5294 | list_for_each_entry(vma, &o->vma_list, vma_link) { |
ec7adb6e JL |
5295 | if (i915_is_ggtt(vma->vm) && |
5296 | vma->ggtt_view.type != I915_GGTT_VIEW_NORMAL) | |
5297 | continue; | |
5298 | if (vma->vm == vm) | |
a70a3148 | 5299 | return vma->node.start; |
a70a3148 | 5300 | } |
ec7adb6e | 5301 | |
f25748ea DV |
5302 | WARN(1, "%s vma for this object not found.\n", |
5303 | i915_is_ggtt(vm) ? "global" : "ppgtt"); | |
a70a3148 BW |
5304 | return -1; |
5305 | } | |
5306 | ||
ec7adb6e JL |
5307 | unsigned long |
5308 | i915_gem_obj_ggtt_offset_view(struct drm_i915_gem_object *o, | |
9abc4648 | 5309 | const struct i915_ggtt_view *view) |
a70a3148 | 5310 | { |
ec7adb6e | 5311 | struct i915_address_space *ggtt = i915_obj_to_ggtt(o); |
a70a3148 BW |
5312 | struct i915_vma *vma; |
5313 | ||
5314 | list_for_each_entry(vma, &o->vma_list, vma_link) | |
9abc4648 JL |
5315 | if (vma->vm == ggtt && |
5316 | i915_ggtt_view_equal(&vma->ggtt_view, view)) | |
ec7adb6e JL |
5317 | return vma->node.start; |
5318 | ||
5678ad73 | 5319 | WARN(1, "global vma for this object not found. (view=%u)\n", view->type); |
ec7adb6e JL |
5320 | return -1; |
5321 | } | |
5322 | ||
5323 | bool i915_gem_obj_bound(struct drm_i915_gem_object *o, | |
5324 | struct i915_address_space *vm) | |
5325 | { | |
5326 | struct i915_vma *vma; | |
5327 | ||
5328 | list_for_each_entry(vma, &o->vma_list, vma_link) { | |
5329 | if (i915_is_ggtt(vma->vm) && | |
5330 | vma->ggtt_view.type != I915_GGTT_VIEW_NORMAL) | |
5331 | continue; | |
5332 | if (vma->vm == vm && drm_mm_node_allocated(&vma->node)) | |
5333 | return true; | |
5334 | } | |
5335 | ||
5336 | return false; | |
5337 | } | |
5338 | ||
5339 | bool i915_gem_obj_ggtt_bound_view(struct drm_i915_gem_object *o, | |
9abc4648 | 5340 | const struct i915_ggtt_view *view) |
ec7adb6e JL |
5341 | { |
5342 | struct i915_address_space *ggtt = i915_obj_to_ggtt(o); | |
5343 | struct i915_vma *vma; | |
5344 | ||
5345 | list_for_each_entry(vma, &o->vma_list, vma_link) | |
5346 | if (vma->vm == ggtt && | |
9abc4648 | 5347 | i915_ggtt_view_equal(&vma->ggtt_view, view) && |
fe14d5f4 | 5348 | drm_mm_node_allocated(&vma->node)) |
a70a3148 BW |
5349 | return true; |
5350 | ||
5351 | return false; | |
5352 | } | |
5353 | ||
5354 | bool i915_gem_obj_bound_any(struct drm_i915_gem_object *o) | |
5355 | { | |
5a1d5eb0 | 5356 | struct i915_vma *vma; |
a70a3148 | 5357 | |
5a1d5eb0 CW |
5358 | list_for_each_entry(vma, &o->vma_list, vma_link) |
5359 | if (drm_mm_node_allocated(&vma->node)) | |
a70a3148 BW |
5360 | return true; |
5361 | ||
5362 | return false; | |
5363 | } | |
5364 | ||
5365 | unsigned long i915_gem_obj_size(struct drm_i915_gem_object *o, | |
5366 | struct i915_address_space *vm) | |
5367 | { | |
5368 | struct drm_i915_private *dev_priv = o->base.dev->dev_private; | |
5369 | struct i915_vma *vma; | |
5370 | ||
896ab1a5 | 5371 | WARN_ON(vm == &dev_priv->mm.aliasing_ppgtt->base); |
a70a3148 BW |
5372 | |
5373 | BUG_ON(list_empty(&o->vma_list)); | |
5374 | ||
ec7adb6e JL |
5375 | list_for_each_entry(vma, &o->vma_list, vma_link) { |
5376 | if (i915_is_ggtt(vma->vm) && | |
5377 | vma->ggtt_view.type != I915_GGTT_VIEW_NORMAL) | |
5378 | continue; | |
a70a3148 BW |
5379 | if (vma->vm == vm) |
5380 | return vma->node.size; | |
ec7adb6e | 5381 | } |
a70a3148 BW |
5382 | return 0; |
5383 | } | |
5384 | ||
ec7adb6e | 5385 | bool i915_gem_obj_is_pinned(struct drm_i915_gem_object *obj) |
5c2abbea BW |
5386 | { |
5387 | struct i915_vma *vma; | |
a6631ae1 | 5388 | list_for_each_entry(vma, &obj->vma_list, vma_link) |
ec7adb6e JL |
5389 | if (vma->pin_count > 0) |
5390 | return true; | |
a6631ae1 | 5391 | |
ec7adb6e | 5392 | return false; |
5c2abbea | 5393 | } |
ec7adb6e | 5394 |