Commit | Line | Data |
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673a394b | 1 | /* |
be6a0376 | 2 | * Copyright © 2008-2015 Intel Corporation |
673a394b EA |
3 | * |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | * | |
26 | */ | |
27 | ||
760285e7 | 28 | #include <drm/drmP.h> |
0de23977 | 29 | #include <drm/drm_vma_manager.h> |
760285e7 | 30 | #include <drm/i915_drm.h> |
673a394b | 31 | #include "i915_drv.h" |
eb82289a | 32 | #include "i915_vgpu.h" |
1c5d22f7 | 33 | #include "i915_trace.h" |
652c393a | 34 | #include "intel_drv.h" |
5949eac4 | 35 | #include <linux/shmem_fs.h> |
5a0e3ad6 | 36 | #include <linux/slab.h> |
673a394b | 37 | #include <linux/swap.h> |
79e53945 | 38 | #include <linux/pci.h> |
1286ff73 | 39 | #include <linux/dma-buf.h> |
673a394b | 40 | |
b4716185 CW |
41 | #define RQ_BUG_ON(expr) |
42 | ||
05394f39 | 43 | static void i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj); |
e62b59e4 | 44 | static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj); |
c8725f3d | 45 | static void |
b4716185 CW |
46 | i915_gem_object_retire__write(struct drm_i915_gem_object *obj); |
47 | static void | |
48 | i915_gem_object_retire__read(struct drm_i915_gem_object *obj, int ring); | |
61050808 | 49 | |
c76ce038 CW |
50 | static bool cpu_cache_is_coherent(struct drm_device *dev, |
51 | enum i915_cache_level level) | |
52 | { | |
53 | return HAS_LLC(dev) || level != I915_CACHE_NONE; | |
54 | } | |
55 | ||
2c22569b CW |
56 | static bool cpu_write_needs_clflush(struct drm_i915_gem_object *obj) |
57 | { | |
58 | if (!cpu_cache_is_coherent(obj->base.dev, obj->cache_level)) | |
59 | return true; | |
60 | ||
61 | return obj->pin_display; | |
62 | } | |
63 | ||
73aa808f CW |
64 | /* some bookkeeping */ |
65 | static void i915_gem_info_add_obj(struct drm_i915_private *dev_priv, | |
66 | size_t size) | |
67 | { | |
c20e8355 | 68 | spin_lock(&dev_priv->mm.object_stat_lock); |
73aa808f CW |
69 | dev_priv->mm.object_count++; |
70 | dev_priv->mm.object_memory += size; | |
c20e8355 | 71 | spin_unlock(&dev_priv->mm.object_stat_lock); |
73aa808f CW |
72 | } |
73 | ||
74 | static void i915_gem_info_remove_obj(struct drm_i915_private *dev_priv, | |
75 | size_t size) | |
76 | { | |
c20e8355 | 77 | spin_lock(&dev_priv->mm.object_stat_lock); |
73aa808f CW |
78 | dev_priv->mm.object_count--; |
79 | dev_priv->mm.object_memory -= size; | |
c20e8355 | 80 | spin_unlock(&dev_priv->mm.object_stat_lock); |
73aa808f CW |
81 | } |
82 | ||
21dd3734 | 83 | static int |
33196ded | 84 | i915_gem_wait_for_error(struct i915_gpu_error *error) |
30dbf0c0 | 85 | { |
30dbf0c0 CW |
86 | int ret; |
87 | ||
7abb690a DV |
88 | #define EXIT_COND (!i915_reset_in_progress(error) || \ |
89 | i915_terminally_wedged(error)) | |
1f83fee0 | 90 | if (EXIT_COND) |
30dbf0c0 CW |
91 | return 0; |
92 | ||
0a6759c6 DV |
93 | /* |
94 | * Only wait 10 seconds for the gpu reset to complete to avoid hanging | |
95 | * userspace. If it takes that long something really bad is going on and | |
96 | * we should simply try to bail out and fail as gracefully as possible. | |
97 | */ | |
1f83fee0 DV |
98 | ret = wait_event_interruptible_timeout(error->reset_queue, |
99 | EXIT_COND, | |
100 | 10*HZ); | |
0a6759c6 DV |
101 | if (ret == 0) { |
102 | DRM_ERROR("Timed out waiting for the gpu reset to complete\n"); | |
103 | return -EIO; | |
104 | } else if (ret < 0) { | |
30dbf0c0 | 105 | return ret; |
0a6759c6 | 106 | } |
1f83fee0 | 107 | #undef EXIT_COND |
30dbf0c0 | 108 | |
21dd3734 | 109 | return 0; |
30dbf0c0 CW |
110 | } |
111 | ||
54cf91dc | 112 | int i915_mutex_lock_interruptible(struct drm_device *dev) |
76c1dec1 | 113 | { |
33196ded | 114 | struct drm_i915_private *dev_priv = dev->dev_private; |
76c1dec1 CW |
115 | int ret; |
116 | ||
33196ded | 117 | ret = i915_gem_wait_for_error(&dev_priv->gpu_error); |
76c1dec1 CW |
118 | if (ret) |
119 | return ret; | |
120 | ||
121 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
122 | if (ret) | |
123 | return ret; | |
124 | ||
23bc5982 | 125 | WARN_ON(i915_verify_lists(dev)); |
76c1dec1 CW |
126 | return 0; |
127 | } | |
30dbf0c0 | 128 | |
5a125c3c EA |
129 | int |
130 | i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 131 | struct drm_file *file) |
5a125c3c | 132 | { |
73aa808f | 133 | struct drm_i915_private *dev_priv = dev->dev_private; |
5a125c3c | 134 | struct drm_i915_gem_get_aperture *args = data; |
62106b4f | 135 | struct i915_ggtt *ggtt = &dev_priv->ggtt; |
ca1543be | 136 | struct i915_vma *vma; |
6299f992 | 137 | size_t pinned; |
5a125c3c | 138 | |
6299f992 | 139 | pinned = 0; |
73aa808f | 140 | mutex_lock(&dev->struct_mutex); |
1c7f4bca | 141 | list_for_each_entry(vma, &ggtt->base.active_list, vm_link) |
ca1543be TU |
142 | if (vma->pin_count) |
143 | pinned += vma->node.size; | |
1c7f4bca | 144 | list_for_each_entry(vma, &ggtt->base.inactive_list, vm_link) |
ca1543be TU |
145 | if (vma->pin_count) |
146 | pinned += vma->node.size; | |
73aa808f | 147 | mutex_unlock(&dev->struct_mutex); |
5a125c3c | 148 | |
62106b4f | 149 | args->aper_size = dev_priv->ggtt.base.total; |
0206e353 | 150 | args->aper_available_size = args->aper_size - pinned; |
6299f992 | 151 | |
5a125c3c EA |
152 | return 0; |
153 | } | |
154 | ||
6a2c4232 CW |
155 | static int |
156 | i915_gem_object_get_pages_phys(struct drm_i915_gem_object *obj) | |
00731155 | 157 | { |
6a2c4232 CW |
158 | struct address_space *mapping = file_inode(obj->base.filp)->i_mapping; |
159 | char *vaddr = obj->phys_handle->vaddr; | |
160 | struct sg_table *st; | |
161 | struct scatterlist *sg; | |
162 | int i; | |
00731155 | 163 | |
6a2c4232 CW |
164 | if (WARN_ON(i915_gem_object_needs_bit17_swizzle(obj))) |
165 | return -EINVAL; | |
166 | ||
167 | for (i = 0; i < obj->base.size / PAGE_SIZE; i++) { | |
168 | struct page *page; | |
169 | char *src; | |
170 | ||
171 | page = shmem_read_mapping_page(mapping, i); | |
172 | if (IS_ERR(page)) | |
173 | return PTR_ERR(page); | |
174 | ||
175 | src = kmap_atomic(page); | |
176 | memcpy(vaddr, src, PAGE_SIZE); | |
177 | drm_clflush_virt_range(vaddr, PAGE_SIZE); | |
178 | kunmap_atomic(src); | |
179 | ||
180 | page_cache_release(page); | |
181 | vaddr += PAGE_SIZE; | |
182 | } | |
183 | ||
184 | i915_gem_chipset_flush(obj->base.dev); | |
185 | ||
186 | st = kmalloc(sizeof(*st), GFP_KERNEL); | |
187 | if (st == NULL) | |
188 | return -ENOMEM; | |
189 | ||
190 | if (sg_alloc_table(st, 1, GFP_KERNEL)) { | |
191 | kfree(st); | |
192 | return -ENOMEM; | |
193 | } | |
194 | ||
195 | sg = st->sgl; | |
196 | sg->offset = 0; | |
197 | sg->length = obj->base.size; | |
00731155 | 198 | |
6a2c4232 CW |
199 | sg_dma_address(sg) = obj->phys_handle->busaddr; |
200 | sg_dma_len(sg) = obj->base.size; | |
201 | ||
202 | obj->pages = st; | |
6a2c4232 CW |
203 | return 0; |
204 | } | |
205 | ||
206 | static void | |
207 | i915_gem_object_put_pages_phys(struct drm_i915_gem_object *obj) | |
208 | { | |
209 | int ret; | |
210 | ||
211 | BUG_ON(obj->madv == __I915_MADV_PURGED); | |
00731155 | 212 | |
6a2c4232 CW |
213 | ret = i915_gem_object_set_to_cpu_domain(obj, true); |
214 | if (ret) { | |
215 | /* In the event of a disaster, abandon all caches and | |
216 | * hope for the best. | |
217 | */ | |
218 | WARN_ON(ret != -EIO); | |
219 | obj->base.read_domains = obj->base.write_domain = I915_GEM_DOMAIN_CPU; | |
220 | } | |
221 | ||
222 | if (obj->madv == I915_MADV_DONTNEED) | |
223 | obj->dirty = 0; | |
224 | ||
225 | if (obj->dirty) { | |
00731155 | 226 | struct address_space *mapping = file_inode(obj->base.filp)->i_mapping; |
6a2c4232 | 227 | char *vaddr = obj->phys_handle->vaddr; |
00731155 CW |
228 | int i; |
229 | ||
230 | for (i = 0; i < obj->base.size / PAGE_SIZE; i++) { | |
6a2c4232 CW |
231 | struct page *page; |
232 | char *dst; | |
233 | ||
234 | page = shmem_read_mapping_page(mapping, i); | |
235 | if (IS_ERR(page)) | |
236 | continue; | |
237 | ||
238 | dst = kmap_atomic(page); | |
239 | drm_clflush_virt_range(vaddr, PAGE_SIZE); | |
240 | memcpy(dst, vaddr, PAGE_SIZE); | |
241 | kunmap_atomic(dst); | |
242 | ||
243 | set_page_dirty(page); | |
244 | if (obj->madv == I915_MADV_WILLNEED) | |
00731155 | 245 | mark_page_accessed(page); |
6a2c4232 | 246 | page_cache_release(page); |
00731155 CW |
247 | vaddr += PAGE_SIZE; |
248 | } | |
6a2c4232 | 249 | obj->dirty = 0; |
00731155 CW |
250 | } |
251 | ||
6a2c4232 CW |
252 | sg_free_table(obj->pages); |
253 | kfree(obj->pages); | |
6a2c4232 CW |
254 | } |
255 | ||
256 | static void | |
257 | i915_gem_object_release_phys(struct drm_i915_gem_object *obj) | |
258 | { | |
259 | drm_pci_free(obj->base.dev, obj->phys_handle); | |
260 | } | |
261 | ||
262 | static const struct drm_i915_gem_object_ops i915_gem_phys_ops = { | |
263 | .get_pages = i915_gem_object_get_pages_phys, | |
264 | .put_pages = i915_gem_object_put_pages_phys, | |
265 | .release = i915_gem_object_release_phys, | |
266 | }; | |
267 | ||
268 | static int | |
269 | drop_pages(struct drm_i915_gem_object *obj) | |
270 | { | |
271 | struct i915_vma *vma, *next; | |
272 | int ret; | |
273 | ||
274 | drm_gem_object_reference(&obj->base); | |
1c7f4bca | 275 | list_for_each_entry_safe(vma, next, &obj->vma_list, obj_link) |
6a2c4232 CW |
276 | if (i915_vma_unbind(vma)) |
277 | break; | |
278 | ||
279 | ret = i915_gem_object_put_pages(obj); | |
280 | drm_gem_object_unreference(&obj->base); | |
281 | ||
282 | return ret; | |
00731155 CW |
283 | } |
284 | ||
285 | int | |
286 | i915_gem_object_attach_phys(struct drm_i915_gem_object *obj, | |
287 | int align) | |
288 | { | |
289 | drm_dma_handle_t *phys; | |
6a2c4232 | 290 | int ret; |
00731155 CW |
291 | |
292 | if (obj->phys_handle) { | |
293 | if ((unsigned long)obj->phys_handle->vaddr & (align -1)) | |
294 | return -EBUSY; | |
295 | ||
296 | return 0; | |
297 | } | |
298 | ||
299 | if (obj->madv != I915_MADV_WILLNEED) | |
300 | return -EFAULT; | |
301 | ||
302 | if (obj->base.filp == NULL) | |
303 | return -EINVAL; | |
304 | ||
6a2c4232 CW |
305 | ret = drop_pages(obj); |
306 | if (ret) | |
307 | return ret; | |
308 | ||
00731155 CW |
309 | /* create a new object */ |
310 | phys = drm_pci_alloc(obj->base.dev, obj->base.size, align); | |
311 | if (!phys) | |
312 | return -ENOMEM; | |
313 | ||
00731155 | 314 | obj->phys_handle = phys; |
6a2c4232 CW |
315 | obj->ops = &i915_gem_phys_ops; |
316 | ||
317 | return i915_gem_object_get_pages(obj); | |
00731155 CW |
318 | } |
319 | ||
320 | static int | |
321 | i915_gem_phys_pwrite(struct drm_i915_gem_object *obj, | |
322 | struct drm_i915_gem_pwrite *args, | |
323 | struct drm_file *file_priv) | |
324 | { | |
325 | struct drm_device *dev = obj->base.dev; | |
326 | void *vaddr = obj->phys_handle->vaddr + args->offset; | |
327 | char __user *user_data = to_user_ptr(args->data_ptr); | |
063e4e6b | 328 | int ret = 0; |
6a2c4232 CW |
329 | |
330 | /* We manually control the domain here and pretend that it | |
331 | * remains coherent i.e. in the GTT domain, like shmem_pwrite. | |
332 | */ | |
333 | ret = i915_gem_object_wait_rendering(obj, false); | |
334 | if (ret) | |
335 | return ret; | |
00731155 | 336 | |
77a0d1ca | 337 | intel_fb_obj_invalidate(obj, ORIGIN_CPU); |
00731155 CW |
338 | if (__copy_from_user_inatomic_nocache(vaddr, user_data, args->size)) { |
339 | unsigned long unwritten; | |
340 | ||
341 | /* The physical object once assigned is fixed for the lifetime | |
342 | * of the obj, so we can safely drop the lock and continue | |
343 | * to access vaddr. | |
344 | */ | |
345 | mutex_unlock(&dev->struct_mutex); | |
346 | unwritten = copy_from_user(vaddr, user_data, args->size); | |
347 | mutex_lock(&dev->struct_mutex); | |
063e4e6b PZ |
348 | if (unwritten) { |
349 | ret = -EFAULT; | |
350 | goto out; | |
351 | } | |
00731155 CW |
352 | } |
353 | ||
6a2c4232 | 354 | drm_clflush_virt_range(vaddr, args->size); |
00731155 | 355 | i915_gem_chipset_flush(dev); |
063e4e6b PZ |
356 | |
357 | out: | |
de152b62 | 358 | intel_fb_obj_flush(obj, false, ORIGIN_CPU); |
063e4e6b | 359 | return ret; |
00731155 CW |
360 | } |
361 | ||
42dcedd4 CW |
362 | void *i915_gem_object_alloc(struct drm_device *dev) |
363 | { | |
364 | struct drm_i915_private *dev_priv = dev->dev_private; | |
efab6d8d | 365 | return kmem_cache_zalloc(dev_priv->objects, GFP_KERNEL); |
42dcedd4 CW |
366 | } |
367 | ||
368 | void i915_gem_object_free(struct drm_i915_gem_object *obj) | |
369 | { | |
370 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; | |
efab6d8d | 371 | kmem_cache_free(dev_priv->objects, obj); |
42dcedd4 CW |
372 | } |
373 | ||
ff72145b DA |
374 | static int |
375 | i915_gem_create(struct drm_file *file, | |
376 | struct drm_device *dev, | |
377 | uint64_t size, | |
378 | uint32_t *handle_p) | |
673a394b | 379 | { |
05394f39 | 380 | struct drm_i915_gem_object *obj; |
a1a2d1d3 PP |
381 | int ret; |
382 | u32 handle; | |
673a394b | 383 | |
ff72145b | 384 | size = roundup(size, PAGE_SIZE); |
8ffc0246 CW |
385 | if (size == 0) |
386 | return -EINVAL; | |
673a394b EA |
387 | |
388 | /* Allocate the new object */ | |
ff72145b | 389 | obj = i915_gem_alloc_object(dev, size); |
673a394b EA |
390 | if (obj == NULL) |
391 | return -ENOMEM; | |
392 | ||
05394f39 | 393 | ret = drm_gem_handle_create(file, &obj->base, &handle); |
202f2fef | 394 | /* drop reference from allocate - handle holds it now */ |
d861e338 DV |
395 | drm_gem_object_unreference_unlocked(&obj->base); |
396 | if (ret) | |
397 | return ret; | |
202f2fef | 398 | |
ff72145b | 399 | *handle_p = handle; |
673a394b EA |
400 | return 0; |
401 | } | |
402 | ||
ff72145b DA |
403 | int |
404 | i915_gem_dumb_create(struct drm_file *file, | |
405 | struct drm_device *dev, | |
406 | struct drm_mode_create_dumb *args) | |
407 | { | |
408 | /* have to work out size/pitch and return them */ | |
de45eaf7 | 409 | args->pitch = ALIGN(args->width * DIV_ROUND_UP(args->bpp, 8), 64); |
ff72145b DA |
410 | args->size = args->pitch * args->height; |
411 | return i915_gem_create(file, dev, | |
da6b51d0 | 412 | args->size, &args->handle); |
ff72145b DA |
413 | } |
414 | ||
ff72145b DA |
415 | /** |
416 | * Creates a new mm object and returns a handle to it. | |
417 | */ | |
418 | int | |
419 | i915_gem_create_ioctl(struct drm_device *dev, void *data, | |
420 | struct drm_file *file) | |
421 | { | |
422 | struct drm_i915_gem_create *args = data; | |
63ed2cb2 | 423 | |
ff72145b | 424 | return i915_gem_create(file, dev, |
da6b51d0 | 425 | args->size, &args->handle); |
ff72145b DA |
426 | } |
427 | ||
8461d226 DV |
428 | static inline int |
429 | __copy_to_user_swizzled(char __user *cpu_vaddr, | |
430 | const char *gpu_vaddr, int gpu_offset, | |
431 | int length) | |
432 | { | |
433 | int ret, cpu_offset = 0; | |
434 | ||
435 | while (length > 0) { | |
436 | int cacheline_end = ALIGN(gpu_offset + 1, 64); | |
437 | int this_length = min(cacheline_end - gpu_offset, length); | |
438 | int swizzled_gpu_offset = gpu_offset ^ 64; | |
439 | ||
440 | ret = __copy_to_user(cpu_vaddr + cpu_offset, | |
441 | gpu_vaddr + swizzled_gpu_offset, | |
442 | this_length); | |
443 | if (ret) | |
444 | return ret + length; | |
445 | ||
446 | cpu_offset += this_length; | |
447 | gpu_offset += this_length; | |
448 | length -= this_length; | |
449 | } | |
450 | ||
451 | return 0; | |
452 | } | |
453 | ||
8c59967c | 454 | static inline int |
4f0c7cfb BW |
455 | __copy_from_user_swizzled(char *gpu_vaddr, int gpu_offset, |
456 | const char __user *cpu_vaddr, | |
8c59967c DV |
457 | int length) |
458 | { | |
459 | int ret, cpu_offset = 0; | |
460 | ||
461 | while (length > 0) { | |
462 | int cacheline_end = ALIGN(gpu_offset + 1, 64); | |
463 | int this_length = min(cacheline_end - gpu_offset, length); | |
464 | int swizzled_gpu_offset = gpu_offset ^ 64; | |
465 | ||
466 | ret = __copy_from_user(gpu_vaddr + swizzled_gpu_offset, | |
467 | cpu_vaddr + cpu_offset, | |
468 | this_length); | |
469 | if (ret) | |
470 | return ret + length; | |
471 | ||
472 | cpu_offset += this_length; | |
473 | gpu_offset += this_length; | |
474 | length -= this_length; | |
475 | } | |
476 | ||
477 | return 0; | |
478 | } | |
479 | ||
4c914c0c BV |
480 | /* |
481 | * Pins the specified object's pages and synchronizes the object with | |
482 | * GPU accesses. Sets needs_clflush to non-zero if the caller should | |
483 | * flush the object from the CPU cache. | |
484 | */ | |
485 | int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object *obj, | |
486 | int *needs_clflush) | |
487 | { | |
488 | int ret; | |
489 | ||
490 | *needs_clflush = 0; | |
491 | ||
1db6e2e7 | 492 | if (WARN_ON((obj->ops->flags & I915_GEM_OBJECT_HAS_STRUCT_PAGE) == 0)) |
4c914c0c BV |
493 | return -EINVAL; |
494 | ||
495 | if (!(obj->base.read_domains & I915_GEM_DOMAIN_CPU)) { | |
496 | /* If we're not in the cpu read domain, set ourself into the gtt | |
497 | * read domain and manually flush cachelines (if required). This | |
498 | * optimizes for the case when the gpu will dirty the data | |
499 | * anyway again before the next pread happens. */ | |
500 | *needs_clflush = !cpu_cache_is_coherent(obj->base.dev, | |
501 | obj->cache_level); | |
502 | ret = i915_gem_object_wait_rendering(obj, true); | |
503 | if (ret) | |
504 | return ret; | |
505 | } | |
506 | ||
507 | ret = i915_gem_object_get_pages(obj); | |
508 | if (ret) | |
509 | return ret; | |
510 | ||
511 | i915_gem_object_pin_pages(obj); | |
512 | ||
513 | return ret; | |
514 | } | |
515 | ||
d174bd64 DV |
516 | /* Per-page copy function for the shmem pread fastpath. |
517 | * Flushes invalid cachelines before reading the target if | |
518 | * needs_clflush is set. */ | |
eb01459f | 519 | static int |
d174bd64 DV |
520 | shmem_pread_fast(struct page *page, int shmem_page_offset, int page_length, |
521 | char __user *user_data, | |
522 | bool page_do_bit17_swizzling, bool needs_clflush) | |
523 | { | |
524 | char *vaddr; | |
525 | int ret; | |
526 | ||
e7e58eb5 | 527 | if (unlikely(page_do_bit17_swizzling)) |
d174bd64 DV |
528 | return -EINVAL; |
529 | ||
530 | vaddr = kmap_atomic(page); | |
531 | if (needs_clflush) | |
532 | drm_clflush_virt_range(vaddr + shmem_page_offset, | |
533 | page_length); | |
534 | ret = __copy_to_user_inatomic(user_data, | |
535 | vaddr + shmem_page_offset, | |
536 | page_length); | |
537 | kunmap_atomic(vaddr); | |
538 | ||
f60d7f0c | 539 | return ret ? -EFAULT : 0; |
d174bd64 DV |
540 | } |
541 | ||
23c18c71 DV |
542 | static void |
543 | shmem_clflush_swizzled_range(char *addr, unsigned long length, | |
544 | bool swizzled) | |
545 | { | |
e7e58eb5 | 546 | if (unlikely(swizzled)) { |
23c18c71 DV |
547 | unsigned long start = (unsigned long) addr; |
548 | unsigned long end = (unsigned long) addr + length; | |
549 | ||
550 | /* For swizzling simply ensure that we always flush both | |
551 | * channels. Lame, but simple and it works. Swizzled | |
552 | * pwrite/pread is far from a hotpath - current userspace | |
553 | * doesn't use it at all. */ | |
554 | start = round_down(start, 128); | |
555 | end = round_up(end, 128); | |
556 | ||
557 | drm_clflush_virt_range((void *)start, end - start); | |
558 | } else { | |
559 | drm_clflush_virt_range(addr, length); | |
560 | } | |
561 | ||
562 | } | |
563 | ||
d174bd64 DV |
564 | /* Only difference to the fast-path function is that this can handle bit17 |
565 | * and uses non-atomic copy and kmap functions. */ | |
566 | static int | |
567 | shmem_pread_slow(struct page *page, int shmem_page_offset, int page_length, | |
568 | char __user *user_data, | |
569 | bool page_do_bit17_swizzling, bool needs_clflush) | |
570 | { | |
571 | char *vaddr; | |
572 | int ret; | |
573 | ||
574 | vaddr = kmap(page); | |
575 | if (needs_clflush) | |
23c18c71 DV |
576 | shmem_clflush_swizzled_range(vaddr + shmem_page_offset, |
577 | page_length, | |
578 | page_do_bit17_swizzling); | |
d174bd64 DV |
579 | |
580 | if (page_do_bit17_swizzling) | |
581 | ret = __copy_to_user_swizzled(user_data, | |
582 | vaddr, shmem_page_offset, | |
583 | page_length); | |
584 | else | |
585 | ret = __copy_to_user(user_data, | |
586 | vaddr + shmem_page_offset, | |
587 | page_length); | |
588 | kunmap(page); | |
589 | ||
f60d7f0c | 590 | return ret ? - EFAULT : 0; |
d174bd64 DV |
591 | } |
592 | ||
eb01459f | 593 | static int |
dbf7bff0 DV |
594 | i915_gem_shmem_pread(struct drm_device *dev, |
595 | struct drm_i915_gem_object *obj, | |
596 | struct drm_i915_gem_pread *args, | |
597 | struct drm_file *file) | |
eb01459f | 598 | { |
8461d226 | 599 | char __user *user_data; |
eb01459f | 600 | ssize_t remain; |
8461d226 | 601 | loff_t offset; |
eb2c0c81 | 602 | int shmem_page_offset, page_length, ret = 0; |
8461d226 | 603 | int obj_do_bit17_swizzling, page_do_bit17_swizzling; |
96d79b52 | 604 | int prefaulted = 0; |
8489731c | 605 | int needs_clflush = 0; |
67d5a50c | 606 | struct sg_page_iter sg_iter; |
eb01459f | 607 | |
2bb4629a | 608 | user_data = to_user_ptr(args->data_ptr); |
eb01459f EA |
609 | remain = args->size; |
610 | ||
8461d226 | 611 | obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj); |
eb01459f | 612 | |
4c914c0c | 613 | ret = i915_gem_obj_prepare_shmem_read(obj, &needs_clflush); |
f60d7f0c CW |
614 | if (ret) |
615 | return ret; | |
616 | ||
8461d226 | 617 | offset = args->offset; |
eb01459f | 618 | |
67d5a50c ID |
619 | for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, |
620 | offset >> PAGE_SHIFT) { | |
2db76d7c | 621 | struct page *page = sg_page_iter_page(&sg_iter); |
9da3da66 CW |
622 | |
623 | if (remain <= 0) | |
624 | break; | |
625 | ||
eb01459f EA |
626 | /* Operation in this page |
627 | * | |
eb01459f | 628 | * shmem_page_offset = offset within page in shmem file |
eb01459f EA |
629 | * page_length = bytes to copy for this page |
630 | */ | |
c8cbbb8b | 631 | shmem_page_offset = offset_in_page(offset); |
eb01459f EA |
632 | page_length = remain; |
633 | if ((shmem_page_offset + page_length) > PAGE_SIZE) | |
634 | page_length = PAGE_SIZE - shmem_page_offset; | |
eb01459f | 635 | |
8461d226 DV |
636 | page_do_bit17_swizzling = obj_do_bit17_swizzling && |
637 | (page_to_phys(page) & (1 << 17)) != 0; | |
638 | ||
d174bd64 DV |
639 | ret = shmem_pread_fast(page, shmem_page_offset, page_length, |
640 | user_data, page_do_bit17_swizzling, | |
641 | needs_clflush); | |
642 | if (ret == 0) | |
643 | goto next_page; | |
dbf7bff0 | 644 | |
dbf7bff0 DV |
645 | mutex_unlock(&dev->struct_mutex); |
646 | ||
d330a953 | 647 | if (likely(!i915.prefault_disable) && !prefaulted) { |
f56f821f | 648 | ret = fault_in_multipages_writeable(user_data, remain); |
96d79b52 DV |
649 | /* Userspace is tricking us, but we've already clobbered |
650 | * its pages with the prefault and promised to write the | |
651 | * data up to the first fault. Hence ignore any errors | |
652 | * and just continue. */ | |
653 | (void)ret; | |
654 | prefaulted = 1; | |
655 | } | |
eb01459f | 656 | |
d174bd64 DV |
657 | ret = shmem_pread_slow(page, shmem_page_offset, page_length, |
658 | user_data, page_do_bit17_swizzling, | |
659 | needs_clflush); | |
eb01459f | 660 | |
dbf7bff0 | 661 | mutex_lock(&dev->struct_mutex); |
f60d7f0c | 662 | |
f60d7f0c | 663 | if (ret) |
8461d226 | 664 | goto out; |
8461d226 | 665 | |
17793c9a | 666 | next_page: |
eb01459f | 667 | remain -= page_length; |
8461d226 | 668 | user_data += page_length; |
eb01459f EA |
669 | offset += page_length; |
670 | } | |
671 | ||
4f27b75d | 672 | out: |
f60d7f0c CW |
673 | i915_gem_object_unpin_pages(obj); |
674 | ||
eb01459f EA |
675 | return ret; |
676 | } | |
677 | ||
673a394b EA |
678 | /** |
679 | * Reads data from the object referenced by handle. | |
680 | * | |
681 | * On error, the contents of *data are undefined. | |
682 | */ | |
683 | int | |
684 | i915_gem_pread_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 685 | struct drm_file *file) |
673a394b EA |
686 | { |
687 | struct drm_i915_gem_pread *args = data; | |
05394f39 | 688 | struct drm_i915_gem_object *obj; |
35b62a89 | 689 | int ret = 0; |
673a394b | 690 | |
51311d0a CW |
691 | if (args->size == 0) |
692 | return 0; | |
693 | ||
694 | if (!access_ok(VERIFY_WRITE, | |
2bb4629a | 695 | to_user_ptr(args->data_ptr), |
51311d0a CW |
696 | args->size)) |
697 | return -EFAULT; | |
698 | ||
4f27b75d | 699 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 700 | if (ret) |
4f27b75d | 701 | return ret; |
673a394b | 702 | |
05394f39 | 703 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 704 | if (&obj->base == NULL) { |
1d7cfea1 CW |
705 | ret = -ENOENT; |
706 | goto unlock; | |
4f27b75d | 707 | } |
673a394b | 708 | |
7dcd2499 | 709 | /* Bounds check source. */ |
05394f39 CW |
710 | if (args->offset > obj->base.size || |
711 | args->size > obj->base.size - args->offset) { | |
ce9d419d | 712 | ret = -EINVAL; |
35b62a89 | 713 | goto out; |
ce9d419d CW |
714 | } |
715 | ||
1286ff73 DV |
716 | /* prime objects have no backing filp to GEM pread/pwrite |
717 | * pages from. | |
718 | */ | |
719 | if (!obj->base.filp) { | |
720 | ret = -EINVAL; | |
721 | goto out; | |
722 | } | |
723 | ||
db53a302 CW |
724 | trace_i915_gem_object_pread(obj, args->offset, args->size); |
725 | ||
dbf7bff0 | 726 | ret = i915_gem_shmem_pread(dev, obj, args, file); |
673a394b | 727 | |
35b62a89 | 728 | out: |
05394f39 | 729 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 730 | unlock: |
4f27b75d | 731 | mutex_unlock(&dev->struct_mutex); |
eb01459f | 732 | return ret; |
673a394b EA |
733 | } |
734 | ||
0839ccb8 KP |
735 | /* This is the fast write path which cannot handle |
736 | * page faults in the source data | |
9b7530cc | 737 | */ |
0839ccb8 KP |
738 | |
739 | static inline int | |
740 | fast_user_write(struct io_mapping *mapping, | |
741 | loff_t page_base, int page_offset, | |
742 | char __user *user_data, | |
743 | int length) | |
9b7530cc | 744 | { |
4f0c7cfb BW |
745 | void __iomem *vaddr_atomic; |
746 | void *vaddr; | |
0839ccb8 | 747 | unsigned long unwritten; |
9b7530cc | 748 | |
3e4d3af5 | 749 | vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base); |
4f0c7cfb BW |
750 | /* We can use the cpu mem copy function because this is X86. */ |
751 | vaddr = (void __force*)vaddr_atomic + page_offset; | |
752 | unwritten = __copy_from_user_inatomic_nocache(vaddr, | |
0839ccb8 | 753 | user_data, length); |
3e4d3af5 | 754 | io_mapping_unmap_atomic(vaddr_atomic); |
fbd5a26d | 755 | return unwritten; |
0839ccb8 KP |
756 | } |
757 | ||
3de09aa3 EA |
758 | /** |
759 | * This is the fast pwrite path, where we copy the data directly from the | |
760 | * user into the GTT, uncached. | |
761 | */ | |
673a394b | 762 | static int |
05394f39 CW |
763 | i915_gem_gtt_pwrite_fast(struct drm_device *dev, |
764 | struct drm_i915_gem_object *obj, | |
3de09aa3 | 765 | struct drm_i915_gem_pwrite *args, |
05394f39 | 766 | struct drm_file *file) |
673a394b | 767 | { |
3e31c6c0 | 768 | struct drm_i915_private *dev_priv = dev->dev_private; |
673a394b | 769 | ssize_t remain; |
0839ccb8 | 770 | loff_t offset, page_base; |
673a394b | 771 | char __user *user_data; |
935aaa69 DV |
772 | int page_offset, page_length, ret; |
773 | ||
1ec9e26d | 774 | ret = i915_gem_obj_ggtt_pin(obj, 0, PIN_MAPPABLE | PIN_NONBLOCK); |
935aaa69 DV |
775 | if (ret) |
776 | goto out; | |
777 | ||
778 | ret = i915_gem_object_set_to_gtt_domain(obj, true); | |
779 | if (ret) | |
780 | goto out_unpin; | |
781 | ||
782 | ret = i915_gem_object_put_fence(obj); | |
783 | if (ret) | |
784 | goto out_unpin; | |
673a394b | 785 | |
2bb4629a | 786 | user_data = to_user_ptr(args->data_ptr); |
673a394b | 787 | remain = args->size; |
673a394b | 788 | |
f343c5f6 | 789 | offset = i915_gem_obj_ggtt_offset(obj) + args->offset; |
673a394b | 790 | |
77a0d1ca | 791 | intel_fb_obj_invalidate(obj, ORIGIN_GTT); |
063e4e6b | 792 | |
673a394b EA |
793 | while (remain > 0) { |
794 | /* Operation in this page | |
795 | * | |
0839ccb8 KP |
796 | * page_base = page offset within aperture |
797 | * page_offset = offset within page | |
798 | * page_length = bytes to copy for this page | |
673a394b | 799 | */ |
c8cbbb8b CW |
800 | page_base = offset & PAGE_MASK; |
801 | page_offset = offset_in_page(offset); | |
0839ccb8 KP |
802 | page_length = remain; |
803 | if ((page_offset + remain) > PAGE_SIZE) | |
804 | page_length = PAGE_SIZE - page_offset; | |
805 | ||
0839ccb8 | 806 | /* If we get a fault while copying data, then (presumably) our |
3de09aa3 EA |
807 | * source page isn't available. Return the error and we'll |
808 | * retry in the slow path. | |
0839ccb8 | 809 | */ |
62106b4f | 810 | if (fast_user_write(dev_priv->ggtt.mappable, page_base, |
935aaa69 DV |
811 | page_offset, user_data, page_length)) { |
812 | ret = -EFAULT; | |
063e4e6b | 813 | goto out_flush; |
935aaa69 | 814 | } |
673a394b | 815 | |
0839ccb8 KP |
816 | remain -= page_length; |
817 | user_data += page_length; | |
818 | offset += page_length; | |
673a394b | 819 | } |
673a394b | 820 | |
063e4e6b | 821 | out_flush: |
de152b62 | 822 | intel_fb_obj_flush(obj, false, ORIGIN_GTT); |
935aaa69 | 823 | out_unpin: |
d7f46fc4 | 824 | i915_gem_object_ggtt_unpin(obj); |
935aaa69 | 825 | out: |
3de09aa3 | 826 | return ret; |
673a394b EA |
827 | } |
828 | ||
d174bd64 DV |
829 | /* Per-page copy function for the shmem pwrite fastpath. |
830 | * Flushes invalid cachelines before writing to the target if | |
831 | * needs_clflush_before is set and flushes out any written cachelines after | |
832 | * writing if needs_clflush is set. */ | |
3043c60c | 833 | static int |
d174bd64 DV |
834 | shmem_pwrite_fast(struct page *page, int shmem_page_offset, int page_length, |
835 | char __user *user_data, | |
836 | bool page_do_bit17_swizzling, | |
837 | bool needs_clflush_before, | |
838 | bool needs_clflush_after) | |
673a394b | 839 | { |
d174bd64 | 840 | char *vaddr; |
673a394b | 841 | int ret; |
3de09aa3 | 842 | |
e7e58eb5 | 843 | if (unlikely(page_do_bit17_swizzling)) |
d174bd64 | 844 | return -EINVAL; |
3de09aa3 | 845 | |
d174bd64 DV |
846 | vaddr = kmap_atomic(page); |
847 | if (needs_clflush_before) | |
848 | drm_clflush_virt_range(vaddr + shmem_page_offset, | |
849 | page_length); | |
c2831a94 CW |
850 | ret = __copy_from_user_inatomic(vaddr + shmem_page_offset, |
851 | user_data, page_length); | |
d174bd64 DV |
852 | if (needs_clflush_after) |
853 | drm_clflush_virt_range(vaddr + shmem_page_offset, | |
854 | page_length); | |
855 | kunmap_atomic(vaddr); | |
3de09aa3 | 856 | |
755d2218 | 857 | return ret ? -EFAULT : 0; |
3de09aa3 EA |
858 | } |
859 | ||
d174bd64 DV |
860 | /* Only difference to the fast-path function is that this can handle bit17 |
861 | * and uses non-atomic copy and kmap functions. */ | |
3043c60c | 862 | static int |
d174bd64 DV |
863 | shmem_pwrite_slow(struct page *page, int shmem_page_offset, int page_length, |
864 | char __user *user_data, | |
865 | bool page_do_bit17_swizzling, | |
866 | bool needs_clflush_before, | |
867 | bool needs_clflush_after) | |
673a394b | 868 | { |
d174bd64 DV |
869 | char *vaddr; |
870 | int ret; | |
e5281ccd | 871 | |
d174bd64 | 872 | vaddr = kmap(page); |
e7e58eb5 | 873 | if (unlikely(needs_clflush_before || page_do_bit17_swizzling)) |
23c18c71 DV |
874 | shmem_clflush_swizzled_range(vaddr + shmem_page_offset, |
875 | page_length, | |
876 | page_do_bit17_swizzling); | |
d174bd64 DV |
877 | if (page_do_bit17_swizzling) |
878 | ret = __copy_from_user_swizzled(vaddr, shmem_page_offset, | |
e5281ccd CW |
879 | user_data, |
880 | page_length); | |
d174bd64 DV |
881 | else |
882 | ret = __copy_from_user(vaddr + shmem_page_offset, | |
883 | user_data, | |
884 | page_length); | |
885 | if (needs_clflush_after) | |
23c18c71 DV |
886 | shmem_clflush_swizzled_range(vaddr + shmem_page_offset, |
887 | page_length, | |
888 | page_do_bit17_swizzling); | |
d174bd64 | 889 | kunmap(page); |
40123c1f | 890 | |
755d2218 | 891 | return ret ? -EFAULT : 0; |
40123c1f EA |
892 | } |
893 | ||
40123c1f | 894 | static int |
e244a443 DV |
895 | i915_gem_shmem_pwrite(struct drm_device *dev, |
896 | struct drm_i915_gem_object *obj, | |
897 | struct drm_i915_gem_pwrite *args, | |
898 | struct drm_file *file) | |
40123c1f | 899 | { |
40123c1f | 900 | ssize_t remain; |
8c59967c DV |
901 | loff_t offset; |
902 | char __user *user_data; | |
eb2c0c81 | 903 | int shmem_page_offset, page_length, ret = 0; |
8c59967c | 904 | int obj_do_bit17_swizzling, page_do_bit17_swizzling; |
e244a443 | 905 | int hit_slowpath = 0; |
58642885 DV |
906 | int needs_clflush_after = 0; |
907 | int needs_clflush_before = 0; | |
67d5a50c | 908 | struct sg_page_iter sg_iter; |
40123c1f | 909 | |
2bb4629a | 910 | user_data = to_user_ptr(args->data_ptr); |
40123c1f EA |
911 | remain = args->size; |
912 | ||
8c59967c | 913 | obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj); |
40123c1f | 914 | |
58642885 DV |
915 | if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) { |
916 | /* If we're not in the cpu write domain, set ourself into the gtt | |
917 | * write domain and manually flush cachelines (if required). This | |
918 | * optimizes for the case when the gpu will use the data | |
919 | * right away and we therefore have to clflush anyway. */ | |
2c22569b | 920 | needs_clflush_after = cpu_write_needs_clflush(obj); |
23f54483 BW |
921 | ret = i915_gem_object_wait_rendering(obj, false); |
922 | if (ret) | |
923 | return ret; | |
58642885 | 924 | } |
c76ce038 CW |
925 | /* Same trick applies to invalidate partially written cachelines read |
926 | * before writing. */ | |
927 | if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0) | |
928 | needs_clflush_before = | |
929 | !cpu_cache_is_coherent(dev, obj->cache_level); | |
58642885 | 930 | |
755d2218 CW |
931 | ret = i915_gem_object_get_pages(obj); |
932 | if (ret) | |
933 | return ret; | |
934 | ||
77a0d1ca | 935 | intel_fb_obj_invalidate(obj, ORIGIN_CPU); |
063e4e6b | 936 | |
755d2218 CW |
937 | i915_gem_object_pin_pages(obj); |
938 | ||
673a394b | 939 | offset = args->offset; |
05394f39 | 940 | obj->dirty = 1; |
673a394b | 941 | |
67d5a50c ID |
942 | for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, |
943 | offset >> PAGE_SHIFT) { | |
2db76d7c | 944 | struct page *page = sg_page_iter_page(&sg_iter); |
58642885 | 945 | int partial_cacheline_write; |
e5281ccd | 946 | |
9da3da66 CW |
947 | if (remain <= 0) |
948 | break; | |
949 | ||
40123c1f EA |
950 | /* Operation in this page |
951 | * | |
40123c1f | 952 | * shmem_page_offset = offset within page in shmem file |
40123c1f EA |
953 | * page_length = bytes to copy for this page |
954 | */ | |
c8cbbb8b | 955 | shmem_page_offset = offset_in_page(offset); |
40123c1f EA |
956 | |
957 | page_length = remain; | |
958 | if ((shmem_page_offset + page_length) > PAGE_SIZE) | |
959 | page_length = PAGE_SIZE - shmem_page_offset; | |
40123c1f | 960 | |
58642885 DV |
961 | /* If we don't overwrite a cacheline completely we need to be |
962 | * careful to have up-to-date data by first clflushing. Don't | |
963 | * overcomplicate things and flush the entire patch. */ | |
964 | partial_cacheline_write = needs_clflush_before && | |
965 | ((shmem_page_offset | page_length) | |
966 | & (boot_cpu_data.x86_clflush_size - 1)); | |
967 | ||
8c59967c DV |
968 | page_do_bit17_swizzling = obj_do_bit17_swizzling && |
969 | (page_to_phys(page) & (1 << 17)) != 0; | |
970 | ||
d174bd64 DV |
971 | ret = shmem_pwrite_fast(page, shmem_page_offset, page_length, |
972 | user_data, page_do_bit17_swizzling, | |
973 | partial_cacheline_write, | |
974 | needs_clflush_after); | |
975 | if (ret == 0) | |
976 | goto next_page; | |
e244a443 DV |
977 | |
978 | hit_slowpath = 1; | |
e244a443 | 979 | mutex_unlock(&dev->struct_mutex); |
d174bd64 DV |
980 | ret = shmem_pwrite_slow(page, shmem_page_offset, page_length, |
981 | user_data, page_do_bit17_swizzling, | |
982 | partial_cacheline_write, | |
983 | needs_clflush_after); | |
40123c1f | 984 | |
e244a443 | 985 | mutex_lock(&dev->struct_mutex); |
755d2218 | 986 | |
755d2218 | 987 | if (ret) |
8c59967c | 988 | goto out; |
8c59967c | 989 | |
17793c9a | 990 | next_page: |
40123c1f | 991 | remain -= page_length; |
8c59967c | 992 | user_data += page_length; |
40123c1f | 993 | offset += page_length; |
673a394b EA |
994 | } |
995 | ||
fbd5a26d | 996 | out: |
755d2218 CW |
997 | i915_gem_object_unpin_pages(obj); |
998 | ||
e244a443 | 999 | if (hit_slowpath) { |
8dcf015e DV |
1000 | /* |
1001 | * Fixup: Flush cpu caches in case we didn't flush the dirty | |
1002 | * cachelines in-line while writing and the object moved | |
1003 | * out of the cpu write domain while we've dropped the lock. | |
1004 | */ | |
1005 | if (!needs_clflush_after && | |
1006 | obj->base.write_domain != I915_GEM_DOMAIN_CPU) { | |
000433b6 | 1007 | if (i915_gem_clflush_object(obj, obj->pin_display)) |
ed75a55b | 1008 | needs_clflush_after = true; |
e244a443 | 1009 | } |
8c59967c | 1010 | } |
673a394b | 1011 | |
58642885 | 1012 | if (needs_clflush_after) |
e76e9aeb | 1013 | i915_gem_chipset_flush(dev); |
ed75a55b VS |
1014 | else |
1015 | obj->cache_dirty = true; | |
58642885 | 1016 | |
de152b62 | 1017 | intel_fb_obj_flush(obj, false, ORIGIN_CPU); |
40123c1f | 1018 | return ret; |
673a394b EA |
1019 | } |
1020 | ||
1021 | /** | |
1022 | * Writes data to the object referenced by handle. | |
1023 | * | |
1024 | * On error, the contents of the buffer that were to be modified are undefined. | |
1025 | */ | |
1026 | int | |
1027 | i915_gem_pwrite_ioctl(struct drm_device *dev, void *data, | |
fbd5a26d | 1028 | struct drm_file *file) |
673a394b | 1029 | { |
5d77d9c5 | 1030 | struct drm_i915_private *dev_priv = dev->dev_private; |
673a394b | 1031 | struct drm_i915_gem_pwrite *args = data; |
05394f39 | 1032 | struct drm_i915_gem_object *obj; |
51311d0a CW |
1033 | int ret; |
1034 | ||
1035 | if (args->size == 0) | |
1036 | return 0; | |
1037 | ||
1038 | if (!access_ok(VERIFY_READ, | |
2bb4629a | 1039 | to_user_ptr(args->data_ptr), |
51311d0a CW |
1040 | args->size)) |
1041 | return -EFAULT; | |
1042 | ||
d330a953 | 1043 | if (likely(!i915.prefault_disable)) { |
0b74b508 XZ |
1044 | ret = fault_in_multipages_readable(to_user_ptr(args->data_ptr), |
1045 | args->size); | |
1046 | if (ret) | |
1047 | return -EFAULT; | |
1048 | } | |
673a394b | 1049 | |
5d77d9c5 ID |
1050 | intel_runtime_pm_get(dev_priv); |
1051 | ||
fbd5a26d | 1052 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 1053 | if (ret) |
5d77d9c5 | 1054 | goto put_rpm; |
1d7cfea1 | 1055 | |
05394f39 | 1056 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 1057 | if (&obj->base == NULL) { |
1d7cfea1 CW |
1058 | ret = -ENOENT; |
1059 | goto unlock; | |
fbd5a26d | 1060 | } |
673a394b | 1061 | |
7dcd2499 | 1062 | /* Bounds check destination. */ |
05394f39 CW |
1063 | if (args->offset > obj->base.size || |
1064 | args->size > obj->base.size - args->offset) { | |
ce9d419d | 1065 | ret = -EINVAL; |
35b62a89 | 1066 | goto out; |
ce9d419d CW |
1067 | } |
1068 | ||
1286ff73 DV |
1069 | /* prime objects have no backing filp to GEM pread/pwrite |
1070 | * pages from. | |
1071 | */ | |
1072 | if (!obj->base.filp) { | |
1073 | ret = -EINVAL; | |
1074 | goto out; | |
1075 | } | |
1076 | ||
db53a302 CW |
1077 | trace_i915_gem_object_pwrite(obj, args->offset, args->size); |
1078 | ||
935aaa69 | 1079 | ret = -EFAULT; |
673a394b EA |
1080 | /* We can only do the GTT pwrite on untiled buffers, as otherwise |
1081 | * it would end up going through the fenced access, and we'll get | |
1082 | * different detiling behavior between reading and writing. | |
1083 | * pread/pwrite currently are reading and writing from the CPU | |
1084 | * perspective, requiring manual detiling by the client. | |
1085 | */ | |
2c22569b CW |
1086 | if (obj->tiling_mode == I915_TILING_NONE && |
1087 | obj->base.write_domain != I915_GEM_DOMAIN_CPU && | |
1088 | cpu_write_needs_clflush(obj)) { | |
fbd5a26d | 1089 | ret = i915_gem_gtt_pwrite_fast(dev, obj, args, file); |
935aaa69 DV |
1090 | /* Note that the gtt paths might fail with non-page-backed user |
1091 | * pointers (e.g. gtt mappings when moving data between | |
1092 | * textures). Fallback to the shmem path in that case. */ | |
fbd5a26d | 1093 | } |
673a394b | 1094 | |
6a2c4232 CW |
1095 | if (ret == -EFAULT || ret == -ENOSPC) { |
1096 | if (obj->phys_handle) | |
1097 | ret = i915_gem_phys_pwrite(obj, args, file); | |
1098 | else | |
1099 | ret = i915_gem_shmem_pwrite(dev, obj, args, file); | |
1100 | } | |
5c0480f2 | 1101 | |
35b62a89 | 1102 | out: |
05394f39 | 1103 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 1104 | unlock: |
fbd5a26d | 1105 | mutex_unlock(&dev->struct_mutex); |
5d77d9c5 ID |
1106 | put_rpm: |
1107 | intel_runtime_pm_put(dev_priv); | |
1108 | ||
673a394b EA |
1109 | return ret; |
1110 | } | |
1111 | ||
b361237b | 1112 | int |
33196ded | 1113 | i915_gem_check_wedge(struct i915_gpu_error *error, |
b361237b CW |
1114 | bool interruptible) |
1115 | { | |
1f83fee0 | 1116 | if (i915_reset_in_progress(error)) { |
b361237b CW |
1117 | /* Non-interruptible callers can't handle -EAGAIN, hence return |
1118 | * -EIO unconditionally for these. */ | |
1119 | if (!interruptible) | |
1120 | return -EIO; | |
1121 | ||
1f83fee0 DV |
1122 | /* Recovery complete, but the reset failed ... */ |
1123 | if (i915_terminally_wedged(error)) | |
b361237b CW |
1124 | return -EIO; |
1125 | ||
6689c167 MA |
1126 | /* |
1127 | * Check if GPU Reset is in progress - we need intel_ring_begin | |
1128 | * to work properly to reinit the hw state while the gpu is | |
1129 | * still marked as reset-in-progress. Handle this with a flag. | |
1130 | */ | |
1131 | if (!error->reload_in_reset) | |
1132 | return -EAGAIN; | |
b361237b CW |
1133 | } |
1134 | ||
1135 | return 0; | |
1136 | } | |
1137 | ||
094f9a54 CW |
1138 | static void fake_irq(unsigned long data) |
1139 | { | |
1140 | wake_up_process((struct task_struct *)data); | |
1141 | } | |
1142 | ||
1143 | static bool missed_irq(struct drm_i915_private *dev_priv, | |
0bc40be8 | 1144 | struct intel_engine_cs *engine) |
094f9a54 | 1145 | { |
0bc40be8 | 1146 | return test_bit(engine->id, &dev_priv->gpu_error.missed_irq_rings); |
094f9a54 CW |
1147 | } |
1148 | ||
ca5b721e CW |
1149 | static unsigned long local_clock_us(unsigned *cpu) |
1150 | { | |
1151 | unsigned long t; | |
1152 | ||
1153 | /* Cheaply and approximately convert from nanoseconds to microseconds. | |
1154 | * The result and subsequent calculations are also defined in the same | |
1155 | * approximate microseconds units. The principal source of timing | |
1156 | * error here is from the simple truncation. | |
1157 | * | |
1158 | * Note that local_clock() is only defined wrt to the current CPU; | |
1159 | * the comparisons are no longer valid if we switch CPUs. Instead of | |
1160 | * blocking preemption for the entire busywait, we can detect the CPU | |
1161 | * switch and use that as indicator of system load and a reason to | |
1162 | * stop busywaiting, see busywait_stop(). | |
1163 | */ | |
1164 | *cpu = get_cpu(); | |
1165 | t = local_clock() >> 10; | |
1166 | put_cpu(); | |
1167 | ||
1168 | return t; | |
1169 | } | |
1170 | ||
1171 | static bool busywait_stop(unsigned long timeout, unsigned cpu) | |
1172 | { | |
1173 | unsigned this_cpu; | |
1174 | ||
1175 | if (time_after(local_clock_us(&this_cpu), timeout)) | |
1176 | return true; | |
1177 | ||
1178 | return this_cpu != cpu; | |
1179 | } | |
1180 | ||
91b0c352 | 1181 | static int __i915_spin_request(struct drm_i915_gem_request *req, int state) |
b29c19b6 | 1182 | { |
2def4ad9 | 1183 | unsigned long timeout; |
ca5b721e CW |
1184 | unsigned cpu; |
1185 | ||
1186 | /* When waiting for high frequency requests, e.g. during synchronous | |
1187 | * rendering split between the CPU and GPU, the finite amount of time | |
1188 | * required to set up the irq and wait upon it limits the response | |
1189 | * rate. By busywaiting on the request completion for a short while we | |
1190 | * can service the high frequency waits as quick as possible. However, | |
1191 | * if it is a slow request, we want to sleep as quickly as possible. | |
1192 | * The tradeoff between waiting and sleeping is roughly the time it | |
1193 | * takes to sleep on a request, on the order of a microsecond. | |
1194 | */ | |
2def4ad9 | 1195 | |
4a570db5 | 1196 | if (req->engine->irq_refcount) |
2def4ad9 CW |
1197 | return -EBUSY; |
1198 | ||
821485dc CW |
1199 | /* Only spin if we know the GPU is processing this request */ |
1200 | if (!i915_gem_request_started(req, true)) | |
1201 | return -EAGAIN; | |
1202 | ||
ca5b721e | 1203 | timeout = local_clock_us(&cpu) + 5; |
2def4ad9 | 1204 | while (!need_resched()) { |
eed29a5b | 1205 | if (i915_gem_request_completed(req, true)) |
2def4ad9 CW |
1206 | return 0; |
1207 | ||
91b0c352 CW |
1208 | if (signal_pending_state(state, current)) |
1209 | break; | |
1210 | ||
ca5b721e | 1211 | if (busywait_stop(timeout, cpu)) |
2def4ad9 | 1212 | break; |
b29c19b6 | 1213 | |
2def4ad9 CW |
1214 | cpu_relax_lowlatency(); |
1215 | } | |
821485dc | 1216 | |
eed29a5b | 1217 | if (i915_gem_request_completed(req, false)) |
2def4ad9 CW |
1218 | return 0; |
1219 | ||
1220 | return -EAGAIN; | |
b29c19b6 CW |
1221 | } |
1222 | ||
b361237b | 1223 | /** |
9c654818 JH |
1224 | * __i915_wait_request - wait until execution of request has finished |
1225 | * @req: duh! | |
1226 | * @reset_counter: reset sequence associated with the given request | |
b361237b CW |
1227 | * @interruptible: do an interruptible wait (normally yes) |
1228 | * @timeout: in - how long to wait (NULL forever); out - how much time remaining | |
1229 | * | |
f69061be DV |
1230 | * Note: It is of utmost importance that the passed in seqno and reset_counter |
1231 | * values have been read by the caller in an smp safe manner. Where read-side | |
1232 | * locks are involved, it is sufficient to read the reset_counter before | |
1233 | * unlocking the lock that protects the seqno. For lockless tricks, the | |
1234 | * reset_counter _must_ be read before, and an appropriate smp_rmb must be | |
1235 | * inserted. | |
1236 | * | |
9c654818 | 1237 | * Returns 0 if the request was found within the alloted time. Else returns the |
b361237b CW |
1238 | * errno with remaining time filled in timeout argument. |
1239 | */ | |
9c654818 | 1240 | int __i915_wait_request(struct drm_i915_gem_request *req, |
f69061be | 1241 | unsigned reset_counter, |
b29c19b6 | 1242 | bool interruptible, |
5ed0bdf2 | 1243 | s64 *timeout, |
2e1b8730 | 1244 | struct intel_rps_client *rps) |
b361237b | 1245 | { |
666796da | 1246 | struct intel_engine_cs *engine = i915_gem_request_get_engine(req); |
e2f80391 | 1247 | struct drm_device *dev = engine->dev; |
3e31c6c0 | 1248 | struct drm_i915_private *dev_priv = dev->dev_private; |
168c3f21 | 1249 | const bool irq_test_in_progress = |
666796da | 1250 | ACCESS_ONCE(dev_priv->gpu_error.test_irq_rings) & intel_engine_flag(engine); |
91b0c352 | 1251 | int state = interruptible ? TASK_INTERRUPTIBLE : TASK_UNINTERRUPTIBLE; |
094f9a54 | 1252 | DEFINE_WAIT(wait); |
47e9766d | 1253 | unsigned long timeout_expire; |
e0313db0 | 1254 | s64 before = 0; /* Only to silence a compiler warning. */ |
b361237b CW |
1255 | int ret; |
1256 | ||
9df7575f | 1257 | WARN(!intel_irqs_enabled(dev_priv), "IRQs disabled"); |
c67a470b | 1258 | |
b4716185 CW |
1259 | if (list_empty(&req->list)) |
1260 | return 0; | |
1261 | ||
1b5a433a | 1262 | if (i915_gem_request_completed(req, true)) |
b361237b CW |
1263 | return 0; |
1264 | ||
bb6d1984 CW |
1265 | timeout_expire = 0; |
1266 | if (timeout) { | |
1267 | if (WARN_ON(*timeout < 0)) | |
1268 | return -EINVAL; | |
1269 | ||
1270 | if (*timeout == 0) | |
1271 | return -ETIME; | |
1272 | ||
1273 | timeout_expire = jiffies + nsecs_to_jiffies_timeout(*timeout); | |
e0313db0 TU |
1274 | |
1275 | /* | |
1276 | * Record current time in case interrupted by signal, or wedged. | |
1277 | */ | |
1278 | before = ktime_get_raw_ns(); | |
bb6d1984 | 1279 | } |
b361237b | 1280 | |
2e1b8730 | 1281 | if (INTEL_INFO(dev_priv)->gen >= 6) |
e61b9958 | 1282 | gen6_rps_boost(dev_priv, rps, req->emitted_jiffies); |
b361237b | 1283 | |
74328ee5 | 1284 | trace_i915_gem_request_wait_begin(req); |
2def4ad9 CW |
1285 | |
1286 | /* Optimistic spin for the next jiffie before touching IRQs */ | |
91b0c352 | 1287 | ret = __i915_spin_request(req, state); |
2def4ad9 CW |
1288 | if (ret == 0) |
1289 | goto out; | |
1290 | ||
e2f80391 | 1291 | if (!irq_test_in_progress && WARN_ON(!engine->irq_get(engine))) { |
2def4ad9 CW |
1292 | ret = -ENODEV; |
1293 | goto out; | |
1294 | } | |
1295 | ||
094f9a54 CW |
1296 | for (;;) { |
1297 | struct timer_list timer; | |
b361237b | 1298 | |
e2f80391 | 1299 | prepare_to_wait(&engine->irq_queue, &wait, state); |
b361237b | 1300 | |
f69061be DV |
1301 | /* We need to check whether any gpu reset happened in between |
1302 | * the caller grabbing the seqno and now ... */ | |
094f9a54 CW |
1303 | if (reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter)) { |
1304 | /* ... but upgrade the -EAGAIN to an -EIO if the gpu | |
1305 | * is truely gone. */ | |
1306 | ret = i915_gem_check_wedge(&dev_priv->gpu_error, interruptible); | |
1307 | if (ret == 0) | |
1308 | ret = -EAGAIN; | |
1309 | break; | |
1310 | } | |
f69061be | 1311 | |
1b5a433a | 1312 | if (i915_gem_request_completed(req, false)) { |
094f9a54 CW |
1313 | ret = 0; |
1314 | break; | |
1315 | } | |
b361237b | 1316 | |
91b0c352 | 1317 | if (signal_pending_state(state, current)) { |
094f9a54 CW |
1318 | ret = -ERESTARTSYS; |
1319 | break; | |
1320 | } | |
1321 | ||
47e9766d | 1322 | if (timeout && time_after_eq(jiffies, timeout_expire)) { |
094f9a54 CW |
1323 | ret = -ETIME; |
1324 | break; | |
1325 | } | |
1326 | ||
1327 | timer.function = NULL; | |
e2f80391 | 1328 | if (timeout || missed_irq(dev_priv, engine)) { |
47e9766d MK |
1329 | unsigned long expire; |
1330 | ||
094f9a54 | 1331 | setup_timer_on_stack(&timer, fake_irq, (unsigned long)current); |
e2f80391 | 1332 | expire = missed_irq(dev_priv, engine) ? jiffies + 1 : timeout_expire; |
094f9a54 CW |
1333 | mod_timer(&timer, expire); |
1334 | } | |
1335 | ||
5035c275 | 1336 | io_schedule(); |
094f9a54 | 1337 | |
094f9a54 CW |
1338 | if (timer.function) { |
1339 | del_singleshot_timer_sync(&timer); | |
1340 | destroy_timer_on_stack(&timer); | |
1341 | } | |
1342 | } | |
168c3f21 | 1343 | if (!irq_test_in_progress) |
e2f80391 | 1344 | engine->irq_put(engine); |
094f9a54 | 1345 | |
e2f80391 | 1346 | finish_wait(&engine->irq_queue, &wait); |
b361237b | 1347 | |
2def4ad9 | 1348 | out: |
2def4ad9 CW |
1349 | trace_i915_gem_request_wait_end(req); |
1350 | ||
b361237b | 1351 | if (timeout) { |
e0313db0 | 1352 | s64 tres = *timeout - (ktime_get_raw_ns() - before); |
5ed0bdf2 TG |
1353 | |
1354 | *timeout = tres < 0 ? 0 : tres; | |
9cca3068 DV |
1355 | |
1356 | /* | |
1357 | * Apparently ktime isn't accurate enough and occasionally has a | |
1358 | * bit of mismatch in the jiffies<->nsecs<->ktime loop. So patch | |
1359 | * things up to make the test happy. We allow up to 1 jiffy. | |
1360 | * | |
1361 | * This is a regrssion from the timespec->ktime conversion. | |
1362 | */ | |
1363 | if (ret == -ETIME && *timeout < jiffies_to_usecs(1)*1000) | |
1364 | *timeout = 0; | |
b361237b CW |
1365 | } |
1366 | ||
094f9a54 | 1367 | return ret; |
b361237b CW |
1368 | } |
1369 | ||
fcfa423c JH |
1370 | int i915_gem_request_add_to_client(struct drm_i915_gem_request *req, |
1371 | struct drm_file *file) | |
1372 | { | |
fcfa423c JH |
1373 | struct drm_i915_file_private *file_priv; |
1374 | ||
1375 | WARN_ON(!req || !file || req->file_priv); | |
1376 | ||
1377 | if (!req || !file) | |
1378 | return -EINVAL; | |
1379 | ||
1380 | if (req->file_priv) | |
1381 | return -EINVAL; | |
1382 | ||
fcfa423c JH |
1383 | file_priv = file->driver_priv; |
1384 | ||
1385 | spin_lock(&file_priv->mm.lock); | |
1386 | req->file_priv = file_priv; | |
1387 | list_add_tail(&req->client_list, &file_priv->mm.request_list); | |
1388 | spin_unlock(&file_priv->mm.lock); | |
1389 | ||
1390 | req->pid = get_pid(task_pid(current)); | |
1391 | ||
1392 | return 0; | |
1393 | } | |
1394 | ||
b4716185 CW |
1395 | static inline void |
1396 | i915_gem_request_remove_from_client(struct drm_i915_gem_request *request) | |
1397 | { | |
1398 | struct drm_i915_file_private *file_priv = request->file_priv; | |
1399 | ||
1400 | if (!file_priv) | |
1401 | return; | |
1402 | ||
1403 | spin_lock(&file_priv->mm.lock); | |
1404 | list_del(&request->client_list); | |
1405 | request->file_priv = NULL; | |
1406 | spin_unlock(&file_priv->mm.lock); | |
fcfa423c JH |
1407 | |
1408 | put_pid(request->pid); | |
1409 | request->pid = NULL; | |
b4716185 CW |
1410 | } |
1411 | ||
1412 | static void i915_gem_request_retire(struct drm_i915_gem_request *request) | |
1413 | { | |
1414 | trace_i915_gem_request_retire(request); | |
1415 | ||
1416 | /* We know the GPU must have read the request to have | |
1417 | * sent us the seqno + interrupt, so use the position | |
1418 | * of tail of the request to update the last known position | |
1419 | * of the GPU head. | |
1420 | * | |
1421 | * Note this requires that we are always called in request | |
1422 | * completion order. | |
1423 | */ | |
1424 | request->ringbuf->last_retired_head = request->postfix; | |
1425 | ||
1426 | list_del_init(&request->list); | |
1427 | i915_gem_request_remove_from_client(request); | |
1428 | ||
b4716185 CW |
1429 | i915_gem_request_unreference(request); |
1430 | } | |
1431 | ||
1432 | static void | |
1433 | __i915_gem_request_retire__upto(struct drm_i915_gem_request *req) | |
1434 | { | |
4a570db5 | 1435 | struct intel_engine_cs *engine = req->engine; |
b4716185 CW |
1436 | struct drm_i915_gem_request *tmp; |
1437 | ||
1438 | lockdep_assert_held(&engine->dev->struct_mutex); | |
1439 | ||
1440 | if (list_empty(&req->list)) | |
1441 | return; | |
1442 | ||
1443 | do { | |
1444 | tmp = list_first_entry(&engine->request_list, | |
1445 | typeof(*tmp), list); | |
1446 | ||
1447 | i915_gem_request_retire(tmp); | |
1448 | } while (tmp != req); | |
1449 | ||
1450 | WARN_ON(i915_verify_lists(engine->dev)); | |
1451 | } | |
1452 | ||
b361237b | 1453 | /** |
a4b3a571 | 1454 | * Waits for a request to be signaled, and cleans up the |
b361237b CW |
1455 | * request and object lists appropriately for that event. |
1456 | */ | |
1457 | int | |
a4b3a571 | 1458 | i915_wait_request(struct drm_i915_gem_request *req) |
b361237b | 1459 | { |
a4b3a571 DV |
1460 | struct drm_device *dev; |
1461 | struct drm_i915_private *dev_priv; | |
1462 | bool interruptible; | |
b361237b CW |
1463 | int ret; |
1464 | ||
a4b3a571 DV |
1465 | BUG_ON(req == NULL); |
1466 | ||
4a570db5 | 1467 | dev = req->engine->dev; |
a4b3a571 DV |
1468 | dev_priv = dev->dev_private; |
1469 | interruptible = dev_priv->mm.interruptible; | |
1470 | ||
b361237b | 1471 | BUG_ON(!mutex_is_locked(&dev->struct_mutex)); |
b361237b | 1472 | |
33196ded | 1473 | ret = i915_gem_check_wedge(&dev_priv->gpu_error, interruptible); |
b361237b CW |
1474 | if (ret) |
1475 | return ret; | |
1476 | ||
b4716185 CW |
1477 | ret = __i915_wait_request(req, |
1478 | atomic_read(&dev_priv->gpu_error.reset_counter), | |
9c654818 | 1479 | interruptible, NULL, NULL); |
b4716185 CW |
1480 | if (ret) |
1481 | return ret; | |
d26e3af8 | 1482 | |
b4716185 | 1483 | __i915_gem_request_retire__upto(req); |
d26e3af8 CW |
1484 | return 0; |
1485 | } | |
1486 | ||
b361237b CW |
1487 | /** |
1488 | * Ensures that all rendering to the object has completed and the object is | |
1489 | * safe to unbind from the GTT or access from the CPU. | |
1490 | */ | |
2e2f351d | 1491 | int |
b361237b CW |
1492 | i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj, |
1493 | bool readonly) | |
1494 | { | |
b4716185 | 1495 | int ret, i; |
b361237b | 1496 | |
b4716185 | 1497 | if (!obj->active) |
b361237b CW |
1498 | return 0; |
1499 | ||
b4716185 CW |
1500 | if (readonly) { |
1501 | if (obj->last_write_req != NULL) { | |
1502 | ret = i915_wait_request(obj->last_write_req); | |
1503 | if (ret) | |
1504 | return ret; | |
b361237b | 1505 | |
4a570db5 | 1506 | i = obj->last_write_req->engine->id; |
b4716185 CW |
1507 | if (obj->last_read_req[i] == obj->last_write_req) |
1508 | i915_gem_object_retire__read(obj, i); | |
1509 | else | |
1510 | i915_gem_object_retire__write(obj); | |
1511 | } | |
1512 | } else { | |
666796da | 1513 | for (i = 0; i < I915_NUM_ENGINES; i++) { |
b4716185 CW |
1514 | if (obj->last_read_req[i] == NULL) |
1515 | continue; | |
1516 | ||
1517 | ret = i915_wait_request(obj->last_read_req[i]); | |
1518 | if (ret) | |
1519 | return ret; | |
1520 | ||
1521 | i915_gem_object_retire__read(obj, i); | |
1522 | } | |
1523 | RQ_BUG_ON(obj->active); | |
1524 | } | |
1525 | ||
1526 | return 0; | |
1527 | } | |
1528 | ||
1529 | static void | |
1530 | i915_gem_object_retire_request(struct drm_i915_gem_object *obj, | |
1531 | struct drm_i915_gem_request *req) | |
1532 | { | |
4a570db5 | 1533 | int ring = req->engine->id; |
b4716185 CW |
1534 | |
1535 | if (obj->last_read_req[ring] == req) | |
1536 | i915_gem_object_retire__read(obj, ring); | |
1537 | else if (obj->last_write_req == req) | |
1538 | i915_gem_object_retire__write(obj); | |
1539 | ||
1540 | __i915_gem_request_retire__upto(req); | |
b361237b CW |
1541 | } |
1542 | ||
3236f57a CW |
1543 | /* A nonblocking variant of the above wait. This is a highly dangerous routine |
1544 | * as the object state may change during this call. | |
1545 | */ | |
1546 | static __must_check int | |
1547 | i915_gem_object_wait_rendering__nonblocking(struct drm_i915_gem_object *obj, | |
2e1b8730 | 1548 | struct intel_rps_client *rps, |
3236f57a CW |
1549 | bool readonly) |
1550 | { | |
1551 | struct drm_device *dev = obj->base.dev; | |
1552 | struct drm_i915_private *dev_priv = dev->dev_private; | |
666796da | 1553 | struct drm_i915_gem_request *requests[I915_NUM_ENGINES]; |
f69061be | 1554 | unsigned reset_counter; |
b4716185 | 1555 | int ret, i, n = 0; |
3236f57a CW |
1556 | |
1557 | BUG_ON(!mutex_is_locked(&dev->struct_mutex)); | |
1558 | BUG_ON(!dev_priv->mm.interruptible); | |
1559 | ||
b4716185 | 1560 | if (!obj->active) |
3236f57a CW |
1561 | return 0; |
1562 | ||
33196ded | 1563 | ret = i915_gem_check_wedge(&dev_priv->gpu_error, true); |
3236f57a CW |
1564 | if (ret) |
1565 | return ret; | |
1566 | ||
f69061be | 1567 | reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter); |
b4716185 CW |
1568 | |
1569 | if (readonly) { | |
1570 | struct drm_i915_gem_request *req; | |
1571 | ||
1572 | req = obj->last_write_req; | |
1573 | if (req == NULL) | |
1574 | return 0; | |
1575 | ||
b4716185 CW |
1576 | requests[n++] = i915_gem_request_reference(req); |
1577 | } else { | |
666796da | 1578 | for (i = 0; i < I915_NUM_ENGINES; i++) { |
b4716185 CW |
1579 | struct drm_i915_gem_request *req; |
1580 | ||
1581 | req = obj->last_read_req[i]; | |
1582 | if (req == NULL) | |
1583 | continue; | |
1584 | ||
b4716185 CW |
1585 | requests[n++] = i915_gem_request_reference(req); |
1586 | } | |
1587 | } | |
1588 | ||
3236f57a | 1589 | mutex_unlock(&dev->struct_mutex); |
b4716185 CW |
1590 | for (i = 0; ret == 0 && i < n; i++) |
1591 | ret = __i915_wait_request(requests[i], reset_counter, true, | |
2e1b8730 | 1592 | NULL, rps); |
3236f57a CW |
1593 | mutex_lock(&dev->struct_mutex); |
1594 | ||
b4716185 CW |
1595 | for (i = 0; i < n; i++) { |
1596 | if (ret == 0) | |
1597 | i915_gem_object_retire_request(obj, requests[i]); | |
1598 | i915_gem_request_unreference(requests[i]); | |
1599 | } | |
1600 | ||
1601 | return ret; | |
3236f57a CW |
1602 | } |
1603 | ||
2e1b8730 CW |
1604 | static struct intel_rps_client *to_rps_client(struct drm_file *file) |
1605 | { | |
1606 | struct drm_i915_file_private *fpriv = file->driver_priv; | |
1607 | return &fpriv->rps; | |
1608 | } | |
1609 | ||
673a394b | 1610 | /** |
2ef7eeaa EA |
1611 | * Called when user space prepares to use an object with the CPU, either |
1612 | * through the mmap ioctl's mapping or a GTT mapping. | |
673a394b EA |
1613 | */ |
1614 | int | |
1615 | i915_gem_set_domain_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 1616 | struct drm_file *file) |
673a394b EA |
1617 | { |
1618 | struct drm_i915_gem_set_domain *args = data; | |
05394f39 | 1619 | struct drm_i915_gem_object *obj; |
2ef7eeaa EA |
1620 | uint32_t read_domains = args->read_domains; |
1621 | uint32_t write_domain = args->write_domain; | |
673a394b EA |
1622 | int ret; |
1623 | ||
2ef7eeaa | 1624 | /* Only handle setting domains to types used by the CPU. */ |
21d509e3 | 1625 | if (write_domain & I915_GEM_GPU_DOMAINS) |
2ef7eeaa EA |
1626 | return -EINVAL; |
1627 | ||
21d509e3 | 1628 | if (read_domains & I915_GEM_GPU_DOMAINS) |
2ef7eeaa EA |
1629 | return -EINVAL; |
1630 | ||
1631 | /* Having something in the write domain implies it's in the read | |
1632 | * domain, and only that read domain. Enforce that in the request. | |
1633 | */ | |
1634 | if (write_domain != 0 && read_domains != write_domain) | |
1635 | return -EINVAL; | |
1636 | ||
76c1dec1 | 1637 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 1638 | if (ret) |
76c1dec1 | 1639 | return ret; |
1d7cfea1 | 1640 | |
05394f39 | 1641 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 1642 | if (&obj->base == NULL) { |
1d7cfea1 CW |
1643 | ret = -ENOENT; |
1644 | goto unlock; | |
76c1dec1 | 1645 | } |
673a394b | 1646 | |
3236f57a CW |
1647 | /* Try to flush the object off the GPU without holding the lock. |
1648 | * We will repeat the flush holding the lock in the normal manner | |
1649 | * to catch cases where we are gazumped. | |
1650 | */ | |
6e4930f6 | 1651 | ret = i915_gem_object_wait_rendering__nonblocking(obj, |
2e1b8730 | 1652 | to_rps_client(file), |
6e4930f6 | 1653 | !write_domain); |
3236f57a CW |
1654 | if (ret) |
1655 | goto unref; | |
1656 | ||
43566ded | 1657 | if (read_domains & I915_GEM_DOMAIN_GTT) |
2ef7eeaa | 1658 | ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0); |
43566ded | 1659 | else |
e47c68e9 | 1660 | ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0); |
2ef7eeaa | 1661 | |
031b698a DV |
1662 | if (write_domain != 0) |
1663 | intel_fb_obj_invalidate(obj, | |
1664 | write_domain == I915_GEM_DOMAIN_GTT ? | |
1665 | ORIGIN_GTT : ORIGIN_CPU); | |
1666 | ||
3236f57a | 1667 | unref: |
05394f39 | 1668 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 1669 | unlock: |
673a394b EA |
1670 | mutex_unlock(&dev->struct_mutex); |
1671 | return ret; | |
1672 | } | |
1673 | ||
1674 | /** | |
1675 | * Called when user space has done writes to this buffer | |
1676 | */ | |
1677 | int | |
1678 | i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 1679 | struct drm_file *file) |
673a394b EA |
1680 | { |
1681 | struct drm_i915_gem_sw_finish *args = data; | |
05394f39 | 1682 | struct drm_i915_gem_object *obj; |
673a394b EA |
1683 | int ret = 0; |
1684 | ||
76c1dec1 | 1685 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 1686 | if (ret) |
76c1dec1 | 1687 | return ret; |
1d7cfea1 | 1688 | |
05394f39 | 1689 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 1690 | if (&obj->base == NULL) { |
1d7cfea1 CW |
1691 | ret = -ENOENT; |
1692 | goto unlock; | |
673a394b EA |
1693 | } |
1694 | ||
673a394b | 1695 | /* Pinned buffers may be scanout, so flush the cache */ |
2c22569b | 1696 | if (obj->pin_display) |
e62b59e4 | 1697 | i915_gem_object_flush_cpu_write_domain(obj); |
e47c68e9 | 1698 | |
05394f39 | 1699 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 1700 | unlock: |
673a394b EA |
1701 | mutex_unlock(&dev->struct_mutex); |
1702 | return ret; | |
1703 | } | |
1704 | ||
1705 | /** | |
1706 | * Maps the contents of an object, returning the address it is mapped | |
1707 | * into. | |
1708 | * | |
1709 | * While the mapping holds a reference on the contents of the object, it doesn't | |
1710 | * imply a ref on the object itself. | |
34367381 DV |
1711 | * |
1712 | * IMPORTANT: | |
1713 | * | |
1714 | * DRM driver writers who look a this function as an example for how to do GEM | |
1715 | * mmap support, please don't implement mmap support like here. The modern way | |
1716 | * to implement DRM mmap support is with an mmap offset ioctl (like | |
1717 | * i915_gem_mmap_gtt) and then using the mmap syscall on the DRM fd directly. | |
1718 | * That way debug tooling like valgrind will understand what's going on, hiding | |
1719 | * the mmap call in a driver private ioctl will break that. The i915 driver only | |
1720 | * does cpu mmaps this way because we didn't know better. | |
673a394b EA |
1721 | */ |
1722 | int | |
1723 | i915_gem_mmap_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 1724 | struct drm_file *file) |
673a394b EA |
1725 | { |
1726 | struct drm_i915_gem_mmap *args = data; | |
1727 | struct drm_gem_object *obj; | |
673a394b EA |
1728 | unsigned long addr; |
1729 | ||
1816f923 AG |
1730 | if (args->flags & ~(I915_MMAP_WC)) |
1731 | return -EINVAL; | |
1732 | ||
1733 | if (args->flags & I915_MMAP_WC && !cpu_has_pat) | |
1734 | return -ENODEV; | |
1735 | ||
05394f39 | 1736 | obj = drm_gem_object_lookup(dev, file, args->handle); |
673a394b | 1737 | if (obj == NULL) |
bf79cb91 | 1738 | return -ENOENT; |
673a394b | 1739 | |
1286ff73 DV |
1740 | /* prime objects have no backing filp to GEM mmap |
1741 | * pages from. | |
1742 | */ | |
1743 | if (!obj->filp) { | |
1744 | drm_gem_object_unreference_unlocked(obj); | |
1745 | return -EINVAL; | |
1746 | } | |
1747 | ||
6be5ceb0 | 1748 | addr = vm_mmap(obj->filp, 0, args->size, |
673a394b EA |
1749 | PROT_READ | PROT_WRITE, MAP_SHARED, |
1750 | args->offset); | |
1816f923 AG |
1751 | if (args->flags & I915_MMAP_WC) { |
1752 | struct mm_struct *mm = current->mm; | |
1753 | struct vm_area_struct *vma; | |
1754 | ||
1755 | down_write(&mm->mmap_sem); | |
1756 | vma = find_vma(mm, addr); | |
1757 | if (vma) | |
1758 | vma->vm_page_prot = | |
1759 | pgprot_writecombine(vm_get_page_prot(vma->vm_flags)); | |
1760 | else | |
1761 | addr = -ENOMEM; | |
1762 | up_write(&mm->mmap_sem); | |
1763 | } | |
bc9025bd | 1764 | drm_gem_object_unreference_unlocked(obj); |
673a394b EA |
1765 | if (IS_ERR((void *)addr)) |
1766 | return addr; | |
1767 | ||
1768 | args->addr_ptr = (uint64_t) addr; | |
1769 | ||
1770 | return 0; | |
1771 | } | |
1772 | ||
de151cf6 JB |
1773 | /** |
1774 | * i915_gem_fault - fault a page into the GTT | |
d9072a3e GT |
1775 | * @vma: VMA in question |
1776 | * @vmf: fault info | |
de151cf6 JB |
1777 | * |
1778 | * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped | |
1779 | * from userspace. The fault handler takes care of binding the object to | |
1780 | * the GTT (if needed), allocating and programming a fence register (again, | |
1781 | * only if needed based on whether the old reg is still valid or the object | |
1782 | * is tiled) and inserting a new PTE into the faulting process. | |
1783 | * | |
1784 | * Note that the faulting process may involve evicting existing objects | |
1785 | * from the GTT and/or fence registers to make room. So performance may | |
1786 | * suffer if the GTT working set is large or there are few fence registers | |
1787 | * left. | |
1788 | */ | |
1789 | int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf) | |
1790 | { | |
05394f39 CW |
1791 | struct drm_i915_gem_object *obj = to_intel_bo(vma->vm_private_data); |
1792 | struct drm_device *dev = obj->base.dev; | |
3e31c6c0 | 1793 | struct drm_i915_private *dev_priv = dev->dev_private; |
c5ad54cf | 1794 | struct i915_ggtt_view view = i915_ggtt_view_normal; |
de151cf6 JB |
1795 | pgoff_t page_offset; |
1796 | unsigned long pfn; | |
1797 | int ret = 0; | |
0f973f27 | 1798 | bool write = !!(vmf->flags & FAULT_FLAG_WRITE); |
de151cf6 | 1799 | |
f65c9168 PZ |
1800 | intel_runtime_pm_get(dev_priv); |
1801 | ||
de151cf6 JB |
1802 | /* We don't use vmf->pgoff since that has the fake offset */ |
1803 | page_offset = ((unsigned long)vmf->virtual_address - vma->vm_start) >> | |
1804 | PAGE_SHIFT; | |
1805 | ||
d9bc7e9f CW |
1806 | ret = i915_mutex_lock_interruptible(dev); |
1807 | if (ret) | |
1808 | goto out; | |
a00b10c3 | 1809 | |
db53a302 CW |
1810 | trace_i915_gem_object_fault(obj, page_offset, true, write); |
1811 | ||
6e4930f6 CW |
1812 | /* Try to flush the object off the GPU first without holding the lock. |
1813 | * Upon reacquiring the lock, we will perform our sanity checks and then | |
1814 | * repeat the flush holding the lock in the normal manner to catch cases | |
1815 | * where we are gazumped. | |
1816 | */ | |
1817 | ret = i915_gem_object_wait_rendering__nonblocking(obj, NULL, !write); | |
1818 | if (ret) | |
1819 | goto unlock; | |
1820 | ||
eb119bd6 CW |
1821 | /* Access to snoopable pages through the GTT is incoherent. */ |
1822 | if (obj->cache_level != I915_CACHE_NONE && !HAS_LLC(dev)) { | |
ddeff6ee | 1823 | ret = -EFAULT; |
eb119bd6 CW |
1824 | goto unlock; |
1825 | } | |
1826 | ||
c5ad54cf | 1827 | /* Use a partial view if the object is bigger than the aperture. */ |
62106b4f | 1828 | if (obj->base.size >= dev_priv->ggtt.mappable_end && |
e7ded2d7 | 1829 | obj->tiling_mode == I915_TILING_NONE) { |
c5ad54cf | 1830 | static const unsigned int chunk_size = 256; // 1 MiB |
e7ded2d7 | 1831 | |
c5ad54cf JL |
1832 | memset(&view, 0, sizeof(view)); |
1833 | view.type = I915_GGTT_VIEW_PARTIAL; | |
1834 | view.params.partial.offset = rounddown(page_offset, chunk_size); | |
1835 | view.params.partial.size = | |
1836 | min_t(unsigned int, | |
1837 | chunk_size, | |
1838 | (vma->vm_end - vma->vm_start)/PAGE_SIZE - | |
1839 | view.params.partial.offset); | |
1840 | } | |
1841 | ||
1842 | /* Now pin it into the GTT if needed */ | |
1843 | ret = i915_gem_object_ggtt_pin(obj, &view, 0, PIN_MAPPABLE); | |
c9839303 CW |
1844 | if (ret) |
1845 | goto unlock; | |
4a684a41 | 1846 | |
c9839303 CW |
1847 | ret = i915_gem_object_set_to_gtt_domain(obj, write); |
1848 | if (ret) | |
1849 | goto unpin; | |
74898d7e | 1850 | |
06d98131 | 1851 | ret = i915_gem_object_get_fence(obj); |
d9e86c0e | 1852 | if (ret) |
c9839303 | 1853 | goto unpin; |
7d1c4804 | 1854 | |
b90b91d8 | 1855 | /* Finally, remap it using the new GTT offset */ |
62106b4f | 1856 | pfn = dev_priv->ggtt.mappable_base + |
c5ad54cf | 1857 | i915_gem_obj_ggtt_offset_view(obj, &view); |
f343c5f6 | 1858 | pfn >>= PAGE_SHIFT; |
de151cf6 | 1859 | |
c5ad54cf JL |
1860 | if (unlikely(view.type == I915_GGTT_VIEW_PARTIAL)) { |
1861 | /* Overriding existing pages in partial view does not cause | |
1862 | * us any trouble as TLBs are still valid because the fault | |
1863 | * is due to userspace losing part of the mapping or never | |
1864 | * having accessed it before (at this partials' range). | |
1865 | */ | |
1866 | unsigned long base = vma->vm_start + | |
1867 | (view.params.partial.offset << PAGE_SHIFT); | |
1868 | unsigned int i; | |
b90b91d8 | 1869 | |
c5ad54cf JL |
1870 | for (i = 0; i < view.params.partial.size; i++) { |
1871 | ret = vm_insert_pfn(vma, base + i * PAGE_SIZE, pfn + i); | |
b90b91d8 CW |
1872 | if (ret) |
1873 | break; | |
1874 | } | |
1875 | ||
1876 | obj->fault_mappable = true; | |
c5ad54cf JL |
1877 | } else { |
1878 | if (!obj->fault_mappable) { | |
1879 | unsigned long size = min_t(unsigned long, | |
1880 | vma->vm_end - vma->vm_start, | |
1881 | obj->base.size); | |
1882 | int i; | |
1883 | ||
1884 | for (i = 0; i < size >> PAGE_SHIFT; i++) { | |
1885 | ret = vm_insert_pfn(vma, | |
1886 | (unsigned long)vma->vm_start + i * PAGE_SIZE, | |
1887 | pfn + i); | |
1888 | if (ret) | |
1889 | break; | |
1890 | } | |
1891 | ||
1892 | obj->fault_mappable = true; | |
1893 | } else | |
1894 | ret = vm_insert_pfn(vma, | |
1895 | (unsigned long)vmf->virtual_address, | |
1896 | pfn + page_offset); | |
1897 | } | |
c9839303 | 1898 | unpin: |
c5ad54cf | 1899 | i915_gem_object_ggtt_unpin_view(obj, &view); |
c715089f | 1900 | unlock: |
de151cf6 | 1901 | mutex_unlock(&dev->struct_mutex); |
d9bc7e9f | 1902 | out: |
de151cf6 | 1903 | switch (ret) { |
d9bc7e9f | 1904 | case -EIO: |
2232f031 DV |
1905 | /* |
1906 | * We eat errors when the gpu is terminally wedged to avoid | |
1907 | * userspace unduly crashing (gl has no provisions for mmaps to | |
1908 | * fail). But any other -EIO isn't ours (e.g. swap in failure) | |
1909 | * and so needs to be reported. | |
1910 | */ | |
1911 | if (!i915_terminally_wedged(&dev_priv->gpu_error)) { | |
f65c9168 PZ |
1912 | ret = VM_FAULT_SIGBUS; |
1913 | break; | |
1914 | } | |
045e769a | 1915 | case -EAGAIN: |
571c608d DV |
1916 | /* |
1917 | * EAGAIN means the gpu is hung and we'll wait for the error | |
1918 | * handler to reset everything when re-faulting in | |
1919 | * i915_mutex_lock_interruptible. | |
d9bc7e9f | 1920 | */ |
c715089f CW |
1921 | case 0: |
1922 | case -ERESTARTSYS: | |
bed636ab | 1923 | case -EINTR: |
e79e0fe3 DR |
1924 | case -EBUSY: |
1925 | /* | |
1926 | * EBUSY is ok: this just means that another thread | |
1927 | * already did the job. | |
1928 | */ | |
f65c9168 PZ |
1929 | ret = VM_FAULT_NOPAGE; |
1930 | break; | |
de151cf6 | 1931 | case -ENOMEM: |
f65c9168 PZ |
1932 | ret = VM_FAULT_OOM; |
1933 | break; | |
a7c2e1aa | 1934 | case -ENOSPC: |
45d67817 | 1935 | case -EFAULT: |
f65c9168 PZ |
1936 | ret = VM_FAULT_SIGBUS; |
1937 | break; | |
de151cf6 | 1938 | default: |
a7c2e1aa | 1939 | WARN_ONCE(ret, "unhandled error in i915_gem_fault: %i\n", ret); |
f65c9168 PZ |
1940 | ret = VM_FAULT_SIGBUS; |
1941 | break; | |
de151cf6 | 1942 | } |
f65c9168 PZ |
1943 | |
1944 | intel_runtime_pm_put(dev_priv); | |
1945 | return ret; | |
de151cf6 JB |
1946 | } |
1947 | ||
901782b2 CW |
1948 | /** |
1949 | * i915_gem_release_mmap - remove physical page mappings | |
1950 | * @obj: obj in question | |
1951 | * | |
af901ca1 | 1952 | * Preserve the reservation of the mmapping with the DRM core code, but |
901782b2 CW |
1953 | * relinquish ownership of the pages back to the system. |
1954 | * | |
1955 | * It is vital that we remove the page mapping if we have mapped a tiled | |
1956 | * object through the GTT and then lose the fence register due to | |
1957 | * resource pressure. Similarly if the object has been moved out of the | |
1958 | * aperture, than pages mapped into userspace must be revoked. Removing the | |
1959 | * mapping will then trigger a page fault on the next user access, allowing | |
1960 | * fixup by i915_gem_fault(). | |
1961 | */ | |
d05ca301 | 1962 | void |
05394f39 | 1963 | i915_gem_release_mmap(struct drm_i915_gem_object *obj) |
901782b2 | 1964 | { |
6299f992 CW |
1965 | if (!obj->fault_mappable) |
1966 | return; | |
901782b2 | 1967 | |
6796cb16 DH |
1968 | drm_vma_node_unmap(&obj->base.vma_node, |
1969 | obj->base.dev->anon_inode->i_mapping); | |
6299f992 | 1970 | obj->fault_mappable = false; |
901782b2 CW |
1971 | } |
1972 | ||
eedd10f4 CW |
1973 | void |
1974 | i915_gem_release_all_mmaps(struct drm_i915_private *dev_priv) | |
1975 | { | |
1976 | struct drm_i915_gem_object *obj; | |
1977 | ||
1978 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) | |
1979 | i915_gem_release_mmap(obj); | |
1980 | } | |
1981 | ||
0fa87796 | 1982 | uint32_t |
e28f8711 | 1983 | i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode) |
92b88aeb | 1984 | { |
e28f8711 | 1985 | uint32_t gtt_size; |
92b88aeb CW |
1986 | |
1987 | if (INTEL_INFO(dev)->gen >= 4 || | |
e28f8711 CW |
1988 | tiling_mode == I915_TILING_NONE) |
1989 | return size; | |
92b88aeb CW |
1990 | |
1991 | /* Previous chips need a power-of-two fence region when tiling */ | |
1992 | if (INTEL_INFO(dev)->gen == 3) | |
e28f8711 | 1993 | gtt_size = 1024*1024; |
92b88aeb | 1994 | else |
e28f8711 | 1995 | gtt_size = 512*1024; |
92b88aeb | 1996 | |
e28f8711 CW |
1997 | while (gtt_size < size) |
1998 | gtt_size <<= 1; | |
92b88aeb | 1999 | |
e28f8711 | 2000 | return gtt_size; |
92b88aeb CW |
2001 | } |
2002 | ||
de151cf6 JB |
2003 | /** |
2004 | * i915_gem_get_gtt_alignment - return required GTT alignment for an object | |
2005 | * @obj: object to check | |
2006 | * | |
2007 | * Return the required GTT alignment for an object, taking into account | |
5e783301 | 2008 | * potential fence register mapping. |
de151cf6 | 2009 | */ |
d865110c ID |
2010 | uint32_t |
2011 | i915_gem_get_gtt_alignment(struct drm_device *dev, uint32_t size, | |
2012 | int tiling_mode, bool fenced) | |
de151cf6 | 2013 | { |
de151cf6 JB |
2014 | /* |
2015 | * Minimum alignment is 4k (GTT page size), but might be greater | |
2016 | * if a fence register is needed for the object. | |
2017 | */ | |
d865110c | 2018 | if (INTEL_INFO(dev)->gen >= 4 || (!fenced && IS_G33(dev)) || |
e28f8711 | 2019 | tiling_mode == I915_TILING_NONE) |
de151cf6 JB |
2020 | return 4096; |
2021 | ||
a00b10c3 CW |
2022 | /* |
2023 | * Previous chips need to be aligned to the size of the smallest | |
2024 | * fence register that can contain the object. | |
2025 | */ | |
e28f8711 | 2026 | return i915_gem_get_gtt_size(dev, size, tiling_mode); |
a00b10c3 CW |
2027 | } |
2028 | ||
d8cb5086 CW |
2029 | static int i915_gem_object_create_mmap_offset(struct drm_i915_gem_object *obj) |
2030 | { | |
2031 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; | |
2032 | int ret; | |
2033 | ||
0de23977 | 2034 | if (drm_vma_node_has_offset(&obj->base.vma_node)) |
d8cb5086 CW |
2035 | return 0; |
2036 | ||
da494d7c DV |
2037 | dev_priv->mm.shrinker_no_lock_stealing = true; |
2038 | ||
d8cb5086 CW |
2039 | ret = drm_gem_create_mmap_offset(&obj->base); |
2040 | if (ret != -ENOSPC) | |
da494d7c | 2041 | goto out; |
d8cb5086 CW |
2042 | |
2043 | /* Badly fragmented mmap space? The only way we can recover | |
2044 | * space is by destroying unwanted objects. We can't randomly release | |
2045 | * mmap_offsets as userspace expects them to be persistent for the | |
2046 | * lifetime of the objects. The closest we can is to release the | |
2047 | * offsets on purgeable objects by truncating it and marking it purged, | |
2048 | * which prevents userspace from ever using that object again. | |
2049 | */ | |
21ab4e74 CW |
2050 | i915_gem_shrink(dev_priv, |
2051 | obj->base.size >> PAGE_SHIFT, | |
2052 | I915_SHRINK_BOUND | | |
2053 | I915_SHRINK_UNBOUND | | |
2054 | I915_SHRINK_PURGEABLE); | |
d8cb5086 CW |
2055 | ret = drm_gem_create_mmap_offset(&obj->base); |
2056 | if (ret != -ENOSPC) | |
da494d7c | 2057 | goto out; |
d8cb5086 CW |
2058 | |
2059 | i915_gem_shrink_all(dev_priv); | |
da494d7c DV |
2060 | ret = drm_gem_create_mmap_offset(&obj->base); |
2061 | out: | |
2062 | dev_priv->mm.shrinker_no_lock_stealing = false; | |
2063 | ||
2064 | return ret; | |
d8cb5086 CW |
2065 | } |
2066 | ||
2067 | static void i915_gem_object_free_mmap_offset(struct drm_i915_gem_object *obj) | |
2068 | { | |
d8cb5086 CW |
2069 | drm_gem_free_mmap_offset(&obj->base); |
2070 | } | |
2071 | ||
da6b51d0 | 2072 | int |
ff72145b DA |
2073 | i915_gem_mmap_gtt(struct drm_file *file, |
2074 | struct drm_device *dev, | |
da6b51d0 | 2075 | uint32_t handle, |
ff72145b | 2076 | uint64_t *offset) |
de151cf6 | 2077 | { |
05394f39 | 2078 | struct drm_i915_gem_object *obj; |
de151cf6 JB |
2079 | int ret; |
2080 | ||
76c1dec1 | 2081 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 2082 | if (ret) |
76c1dec1 | 2083 | return ret; |
de151cf6 | 2084 | |
ff72145b | 2085 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle)); |
c8725226 | 2086 | if (&obj->base == NULL) { |
1d7cfea1 CW |
2087 | ret = -ENOENT; |
2088 | goto unlock; | |
2089 | } | |
de151cf6 | 2090 | |
05394f39 | 2091 | if (obj->madv != I915_MADV_WILLNEED) { |
bd9b6a4e | 2092 | DRM_DEBUG("Attempting to mmap a purgeable buffer\n"); |
8c99e57d | 2093 | ret = -EFAULT; |
1d7cfea1 | 2094 | goto out; |
ab18282d CW |
2095 | } |
2096 | ||
d8cb5086 CW |
2097 | ret = i915_gem_object_create_mmap_offset(obj); |
2098 | if (ret) | |
2099 | goto out; | |
de151cf6 | 2100 | |
0de23977 | 2101 | *offset = drm_vma_node_offset_addr(&obj->base.vma_node); |
de151cf6 | 2102 | |
1d7cfea1 | 2103 | out: |
05394f39 | 2104 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 2105 | unlock: |
de151cf6 | 2106 | mutex_unlock(&dev->struct_mutex); |
1d7cfea1 | 2107 | return ret; |
de151cf6 JB |
2108 | } |
2109 | ||
ff72145b DA |
2110 | /** |
2111 | * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing | |
2112 | * @dev: DRM device | |
2113 | * @data: GTT mapping ioctl data | |
2114 | * @file: GEM object info | |
2115 | * | |
2116 | * Simply returns the fake offset to userspace so it can mmap it. | |
2117 | * The mmap call will end up in drm_gem_mmap(), which will set things | |
2118 | * up so we can get faults in the handler above. | |
2119 | * | |
2120 | * The fault handler will take care of binding the object into the GTT | |
2121 | * (since it may have been evicted to make room for something), allocating | |
2122 | * a fence register, and mapping the appropriate aperture address into | |
2123 | * userspace. | |
2124 | */ | |
2125 | int | |
2126 | i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data, | |
2127 | struct drm_file *file) | |
2128 | { | |
2129 | struct drm_i915_gem_mmap_gtt *args = data; | |
2130 | ||
da6b51d0 | 2131 | return i915_gem_mmap_gtt(file, dev, args->handle, &args->offset); |
ff72145b DA |
2132 | } |
2133 | ||
225067ee DV |
2134 | /* Immediately discard the backing storage */ |
2135 | static void | |
2136 | i915_gem_object_truncate(struct drm_i915_gem_object *obj) | |
e5281ccd | 2137 | { |
4d6294bf | 2138 | i915_gem_object_free_mmap_offset(obj); |
1286ff73 | 2139 | |
4d6294bf CW |
2140 | if (obj->base.filp == NULL) |
2141 | return; | |
e5281ccd | 2142 | |
225067ee DV |
2143 | /* Our goal here is to return as much of the memory as |
2144 | * is possible back to the system as we are called from OOM. | |
2145 | * To do this we must instruct the shmfs to drop all of its | |
2146 | * backing pages, *now*. | |
2147 | */ | |
5537252b | 2148 | shmem_truncate_range(file_inode(obj->base.filp), 0, (loff_t)-1); |
225067ee DV |
2149 | obj->madv = __I915_MADV_PURGED; |
2150 | } | |
e5281ccd | 2151 | |
5537252b CW |
2152 | /* Try to discard unwanted pages */ |
2153 | static void | |
2154 | i915_gem_object_invalidate(struct drm_i915_gem_object *obj) | |
225067ee | 2155 | { |
5537252b CW |
2156 | struct address_space *mapping; |
2157 | ||
2158 | switch (obj->madv) { | |
2159 | case I915_MADV_DONTNEED: | |
2160 | i915_gem_object_truncate(obj); | |
2161 | case __I915_MADV_PURGED: | |
2162 | return; | |
2163 | } | |
2164 | ||
2165 | if (obj->base.filp == NULL) | |
2166 | return; | |
2167 | ||
2168 | mapping = file_inode(obj->base.filp)->i_mapping, | |
2169 | invalidate_mapping_pages(mapping, 0, (loff_t)-1); | |
e5281ccd CW |
2170 | } |
2171 | ||
5cdf5881 | 2172 | static void |
05394f39 | 2173 | i915_gem_object_put_pages_gtt(struct drm_i915_gem_object *obj) |
673a394b | 2174 | { |
90797e6d ID |
2175 | struct sg_page_iter sg_iter; |
2176 | int ret; | |
1286ff73 | 2177 | |
05394f39 | 2178 | BUG_ON(obj->madv == __I915_MADV_PURGED); |
673a394b | 2179 | |
6c085a72 CW |
2180 | ret = i915_gem_object_set_to_cpu_domain(obj, true); |
2181 | if (ret) { | |
2182 | /* In the event of a disaster, abandon all caches and | |
2183 | * hope for the best. | |
2184 | */ | |
2185 | WARN_ON(ret != -EIO); | |
2c22569b | 2186 | i915_gem_clflush_object(obj, true); |
6c085a72 CW |
2187 | obj->base.read_domains = obj->base.write_domain = I915_GEM_DOMAIN_CPU; |
2188 | } | |
2189 | ||
e2273302 ID |
2190 | i915_gem_gtt_finish_object(obj); |
2191 | ||
6dacfd2f | 2192 | if (i915_gem_object_needs_bit17_swizzle(obj)) |
280b713b EA |
2193 | i915_gem_object_save_bit_17_swizzle(obj); |
2194 | ||
05394f39 CW |
2195 | if (obj->madv == I915_MADV_DONTNEED) |
2196 | obj->dirty = 0; | |
3ef94daa | 2197 | |
90797e6d | 2198 | for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, 0) { |
2db76d7c | 2199 | struct page *page = sg_page_iter_page(&sg_iter); |
9da3da66 | 2200 | |
05394f39 | 2201 | if (obj->dirty) |
9da3da66 | 2202 | set_page_dirty(page); |
3ef94daa | 2203 | |
05394f39 | 2204 | if (obj->madv == I915_MADV_WILLNEED) |
9da3da66 | 2205 | mark_page_accessed(page); |
3ef94daa | 2206 | |
9da3da66 | 2207 | page_cache_release(page); |
3ef94daa | 2208 | } |
05394f39 | 2209 | obj->dirty = 0; |
673a394b | 2210 | |
9da3da66 CW |
2211 | sg_free_table(obj->pages); |
2212 | kfree(obj->pages); | |
37e680a1 | 2213 | } |
6c085a72 | 2214 | |
dd624afd | 2215 | int |
37e680a1 CW |
2216 | i915_gem_object_put_pages(struct drm_i915_gem_object *obj) |
2217 | { | |
2218 | const struct drm_i915_gem_object_ops *ops = obj->ops; | |
2219 | ||
2f745ad3 | 2220 | if (obj->pages == NULL) |
37e680a1 CW |
2221 | return 0; |
2222 | ||
a5570178 CW |
2223 | if (obj->pages_pin_count) |
2224 | return -EBUSY; | |
2225 | ||
9843877d | 2226 | BUG_ON(i915_gem_obj_bound_any(obj)); |
3e123027 | 2227 | |
a2165e31 CW |
2228 | /* ->put_pages might need to allocate memory for the bit17 swizzle |
2229 | * array, hence protect them from being reaped by removing them from gtt | |
2230 | * lists early. */ | |
35c20a60 | 2231 | list_del(&obj->global_list); |
a2165e31 | 2232 | |
37e680a1 | 2233 | ops->put_pages(obj); |
05394f39 | 2234 | obj->pages = NULL; |
37e680a1 | 2235 | |
5537252b | 2236 | i915_gem_object_invalidate(obj); |
6c085a72 CW |
2237 | |
2238 | return 0; | |
2239 | } | |
2240 | ||
37e680a1 | 2241 | static int |
6c085a72 | 2242 | i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj) |
e5281ccd | 2243 | { |
6c085a72 | 2244 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
e5281ccd CW |
2245 | int page_count, i; |
2246 | struct address_space *mapping; | |
9da3da66 CW |
2247 | struct sg_table *st; |
2248 | struct scatterlist *sg; | |
90797e6d | 2249 | struct sg_page_iter sg_iter; |
e5281ccd | 2250 | struct page *page; |
90797e6d | 2251 | unsigned long last_pfn = 0; /* suppress gcc warning */ |
e2273302 | 2252 | int ret; |
6c085a72 | 2253 | gfp_t gfp; |
e5281ccd | 2254 | |
6c085a72 CW |
2255 | /* Assert that the object is not currently in any GPU domain. As it |
2256 | * wasn't in the GTT, there shouldn't be any way it could have been in | |
2257 | * a GPU cache | |
2258 | */ | |
2259 | BUG_ON(obj->base.read_domains & I915_GEM_GPU_DOMAINS); | |
2260 | BUG_ON(obj->base.write_domain & I915_GEM_GPU_DOMAINS); | |
2261 | ||
9da3da66 CW |
2262 | st = kmalloc(sizeof(*st), GFP_KERNEL); |
2263 | if (st == NULL) | |
2264 | return -ENOMEM; | |
2265 | ||
05394f39 | 2266 | page_count = obj->base.size / PAGE_SIZE; |
9da3da66 | 2267 | if (sg_alloc_table(st, page_count, GFP_KERNEL)) { |
9da3da66 | 2268 | kfree(st); |
e5281ccd | 2269 | return -ENOMEM; |
9da3da66 | 2270 | } |
e5281ccd | 2271 | |
9da3da66 CW |
2272 | /* Get the list of pages out of our struct file. They'll be pinned |
2273 | * at this point until we release them. | |
2274 | * | |
2275 | * Fail silently without starting the shrinker | |
2276 | */ | |
496ad9aa | 2277 | mapping = file_inode(obj->base.filp)->i_mapping; |
c62d2555 | 2278 | gfp = mapping_gfp_constraint(mapping, ~(__GFP_IO | __GFP_RECLAIM)); |
d0164adc | 2279 | gfp |= __GFP_NORETRY | __GFP_NOWARN; |
90797e6d ID |
2280 | sg = st->sgl; |
2281 | st->nents = 0; | |
2282 | for (i = 0; i < page_count; i++) { | |
6c085a72 CW |
2283 | page = shmem_read_mapping_page_gfp(mapping, i, gfp); |
2284 | if (IS_ERR(page)) { | |
21ab4e74 CW |
2285 | i915_gem_shrink(dev_priv, |
2286 | page_count, | |
2287 | I915_SHRINK_BOUND | | |
2288 | I915_SHRINK_UNBOUND | | |
2289 | I915_SHRINK_PURGEABLE); | |
6c085a72 CW |
2290 | page = shmem_read_mapping_page_gfp(mapping, i, gfp); |
2291 | } | |
2292 | if (IS_ERR(page)) { | |
2293 | /* We've tried hard to allocate the memory by reaping | |
2294 | * our own buffer, now let the real VM do its job and | |
2295 | * go down in flames if truly OOM. | |
2296 | */ | |
6c085a72 | 2297 | i915_gem_shrink_all(dev_priv); |
f461d1be | 2298 | page = shmem_read_mapping_page(mapping, i); |
e2273302 ID |
2299 | if (IS_ERR(page)) { |
2300 | ret = PTR_ERR(page); | |
6c085a72 | 2301 | goto err_pages; |
e2273302 | 2302 | } |
6c085a72 | 2303 | } |
426729dc KRW |
2304 | #ifdef CONFIG_SWIOTLB |
2305 | if (swiotlb_nr_tbl()) { | |
2306 | st->nents++; | |
2307 | sg_set_page(sg, page, PAGE_SIZE, 0); | |
2308 | sg = sg_next(sg); | |
2309 | continue; | |
2310 | } | |
2311 | #endif | |
90797e6d ID |
2312 | if (!i || page_to_pfn(page) != last_pfn + 1) { |
2313 | if (i) | |
2314 | sg = sg_next(sg); | |
2315 | st->nents++; | |
2316 | sg_set_page(sg, page, PAGE_SIZE, 0); | |
2317 | } else { | |
2318 | sg->length += PAGE_SIZE; | |
2319 | } | |
2320 | last_pfn = page_to_pfn(page); | |
3bbbe706 DV |
2321 | |
2322 | /* Check that the i965g/gm workaround works. */ | |
2323 | WARN_ON((gfp & __GFP_DMA32) && (last_pfn >= 0x00100000UL)); | |
e5281ccd | 2324 | } |
426729dc KRW |
2325 | #ifdef CONFIG_SWIOTLB |
2326 | if (!swiotlb_nr_tbl()) | |
2327 | #endif | |
2328 | sg_mark_end(sg); | |
74ce6b6c CW |
2329 | obj->pages = st; |
2330 | ||
e2273302 ID |
2331 | ret = i915_gem_gtt_prepare_object(obj); |
2332 | if (ret) | |
2333 | goto err_pages; | |
2334 | ||
6dacfd2f | 2335 | if (i915_gem_object_needs_bit17_swizzle(obj)) |
e5281ccd CW |
2336 | i915_gem_object_do_bit_17_swizzle(obj); |
2337 | ||
656bfa3a DV |
2338 | if (obj->tiling_mode != I915_TILING_NONE && |
2339 | dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES) | |
2340 | i915_gem_object_pin_pages(obj); | |
2341 | ||
e5281ccd CW |
2342 | return 0; |
2343 | ||
2344 | err_pages: | |
90797e6d ID |
2345 | sg_mark_end(sg); |
2346 | for_each_sg_page(st->sgl, &sg_iter, st->nents, 0) | |
2db76d7c | 2347 | page_cache_release(sg_page_iter_page(&sg_iter)); |
9da3da66 CW |
2348 | sg_free_table(st); |
2349 | kfree(st); | |
0820baf3 CW |
2350 | |
2351 | /* shmemfs first checks if there is enough memory to allocate the page | |
2352 | * and reports ENOSPC should there be insufficient, along with the usual | |
2353 | * ENOMEM for a genuine allocation failure. | |
2354 | * | |
2355 | * We use ENOSPC in our driver to mean that we have run out of aperture | |
2356 | * space and so want to translate the error from shmemfs back to our | |
2357 | * usual understanding of ENOMEM. | |
2358 | */ | |
e2273302 ID |
2359 | if (ret == -ENOSPC) |
2360 | ret = -ENOMEM; | |
2361 | ||
2362 | return ret; | |
673a394b EA |
2363 | } |
2364 | ||
37e680a1 CW |
2365 | /* Ensure that the associated pages are gathered from the backing storage |
2366 | * and pinned into our object. i915_gem_object_get_pages() may be called | |
2367 | * multiple times before they are released by a single call to | |
2368 | * i915_gem_object_put_pages() - once the pages are no longer referenced | |
2369 | * either as a result of memory pressure (reaping pages under the shrinker) | |
2370 | * or as the object is itself released. | |
2371 | */ | |
2372 | int | |
2373 | i915_gem_object_get_pages(struct drm_i915_gem_object *obj) | |
2374 | { | |
2375 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; | |
2376 | const struct drm_i915_gem_object_ops *ops = obj->ops; | |
2377 | int ret; | |
2378 | ||
2f745ad3 | 2379 | if (obj->pages) |
37e680a1 CW |
2380 | return 0; |
2381 | ||
43e28f09 | 2382 | if (obj->madv != I915_MADV_WILLNEED) { |
bd9b6a4e | 2383 | DRM_DEBUG("Attempting to obtain a purgeable object\n"); |
8c99e57d | 2384 | return -EFAULT; |
43e28f09 CW |
2385 | } |
2386 | ||
a5570178 CW |
2387 | BUG_ON(obj->pages_pin_count); |
2388 | ||
37e680a1 CW |
2389 | ret = ops->get_pages(obj); |
2390 | if (ret) | |
2391 | return ret; | |
2392 | ||
35c20a60 | 2393 | list_add_tail(&obj->global_list, &dev_priv->mm.unbound_list); |
ee286370 CW |
2394 | |
2395 | obj->get_page.sg = obj->pages->sgl; | |
2396 | obj->get_page.last = 0; | |
2397 | ||
37e680a1 | 2398 | return 0; |
673a394b EA |
2399 | } |
2400 | ||
b4716185 | 2401 | void i915_vma_move_to_active(struct i915_vma *vma, |
b2af0376 | 2402 | struct drm_i915_gem_request *req) |
673a394b | 2403 | { |
b4716185 | 2404 | struct drm_i915_gem_object *obj = vma->obj; |
e2f80391 | 2405 | struct intel_engine_cs *engine; |
b2af0376 | 2406 | |
666796da | 2407 | engine = i915_gem_request_get_engine(req); |
673a394b EA |
2408 | |
2409 | /* Add a reference if we're newly entering the active list. */ | |
b4716185 | 2410 | if (obj->active == 0) |
05394f39 | 2411 | drm_gem_object_reference(&obj->base); |
666796da | 2412 | obj->active |= intel_engine_flag(engine); |
e35a41de | 2413 | |
117897f4 | 2414 | list_move_tail(&obj->engine_list[engine->id], &engine->active_list); |
e2f80391 | 2415 | i915_gem_request_assign(&obj->last_read_req[engine->id], req); |
caea7476 | 2416 | |
1c7f4bca | 2417 | list_move_tail(&vma->vm_link, &vma->vm->active_list); |
caea7476 CW |
2418 | } |
2419 | ||
b4716185 CW |
2420 | static void |
2421 | i915_gem_object_retire__write(struct drm_i915_gem_object *obj) | |
e2d05a8b | 2422 | { |
b4716185 | 2423 | RQ_BUG_ON(obj->last_write_req == NULL); |
666796da | 2424 | RQ_BUG_ON(!(obj->active & intel_engine_flag(obj->last_write_req->engine))); |
b4716185 CW |
2425 | |
2426 | i915_gem_request_assign(&obj->last_write_req, NULL); | |
de152b62 | 2427 | intel_fb_obj_flush(obj, true, ORIGIN_CS); |
e2d05a8b BW |
2428 | } |
2429 | ||
caea7476 | 2430 | static void |
b4716185 | 2431 | i915_gem_object_retire__read(struct drm_i915_gem_object *obj, int ring) |
ce44b0ea | 2432 | { |
feb822cf | 2433 | struct i915_vma *vma; |
ce44b0ea | 2434 | |
b4716185 CW |
2435 | RQ_BUG_ON(obj->last_read_req[ring] == NULL); |
2436 | RQ_BUG_ON(!(obj->active & (1 << ring))); | |
2437 | ||
117897f4 | 2438 | list_del_init(&obj->engine_list[ring]); |
b4716185 CW |
2439 | i915_gem_request_assign(&obj->last_read_req[ring], NULL); |
2440 | ||
4a570db5 | 2441 | if (obj->last_write_req && obj->last_write_req->engine->id == ring) |
b4716185 CW |
2442 | i915_gem_object_retire__write(obj); |
2443 | ||
2444 | obj->active &= ~(1 << ring); | |
2445 | if (obj->active) | |
2446 | return; | |
caea7476 | 2447 | |
6c246959 CW |
2448 | /* Bump our place on the bound list to keep it roughly in LRU order |
2449 | * so that we don't steal from recently used but inactive objects | |
2450 | * (unless we are forced to ofc!) | |
2451 | */ | |
2452 | list_move_tail(&obj->global_list, | |
2453 | &to_i915(obj->base.dev)->mm.bound_list); | |
2454 | ||
1c7f4bca CW |
2455 | list_for_each_entry(vma, &obj->vma_list, obj_link) { |
2456 | if (!list_empty(&vma->vm_link)) | |
2457 | list_move_tail(&vma->vm_link, &vma->vm->inactive_list); | |
feb822cf | 2458 | } |
caea7476 | 2459 | |
97b2a6a1 | 2460 | i915_gem_request_assign(&obj->last_fenced_req, NULL); |
caea7476 | 2461 | drm_gem_object_unreference(&obj->base); |
c8725f3d CW |
2462 | } |
2463 | ||
9d773091 | 2464 | static int |
fca26bb4 | 2465 | i915_gem_init_seqno(struct drm_device *dev, u32 seqno) |
53d227f2 | 2466 | { |
9d773091 | 2467 | struct drm_i915_private *dev_priv = dev->dev_private; |
e2f80391 | 2468 | struct intel_engine_cs *engine; |
b4ac5afc | 2469 | int ret, j; |
53d227f2 | 2470 | |
107f27a5 | 2471 | /* Carefully retire all requests without writing to the rings */ |
b4ac5afc | 2472 | for_each_engine(engine, dev_priv) { |
666796da | 2473 | ret = intel_engine_idle(engine); |
107f27a5 CW |
2474 | if (ret) |
2475 | return ret; | |
9d773091 | 2476 | } |
9d773091 | 2477 | i915_gem_retire_requests(dev); |
107f27a5 CW |
2478 | |
2479 | /* Finally reset hw state */ | |
b4ac5afc | 2480 | for_each_engine(engine, dev_priv) { |
e2f80391 | 2481 | intel_ring_init_seqno(engine, seqno); |
498d2ac1 | 2482 | |
e2f80391 TU |
2483 | for (j = 0; j < ARRAY_SIZE(engine->semaphore.sync_seqno); j++) |
2484 | engine->semaphore.sync_seqno[j] = 0; | |
9d773091 | 2485 | } |
53d227f2 | 2486 | |
9d773091 | 2487 | return 0; |
53d227f2 DV |
2488 | } |
2489 | ||
fca26bb4 MK |
2490 | int i915_gem_set_seqno(struct drm_device *dev, u32 seqno) |
2491 | { | |
2492 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2493 | int ret; | |
2494 | ||
2495 | if (seqno == 0) | |
2496 | return -EINVAL; | |
2497 | ||
2498 | /* HWS page needs to be set less than what we | |
2499 | * will inject to ring | |
2500 | */ | |
2501 | ret = i915_gem_init_seqno(dev, seqno - 1); | |
2502 | if (ret) | |
2503 | return ret; | |
2504 | ||
2505 | /* Carefully set the last_seqno value so that wrap | |
2506 | * detection still works | |
2507 | */ | |
2508 | dev_priv->next_seqno = seqno; | |
2509 | dev_priv->last_seqno = seqno - 1; | |
2510 | if (dev_priv->last_seqno == 0) | |
2511 | dev_priv->last_seqno--; | |
2512 | ||
2513 | return 0; | |
2514 | } | |
2515 | ||
9d773091 CW |
2516 | int |
2517 | i915_gem_get_seqno(struct drm_device *dev, u32 *seqno) | |
53d227f2 | 2518 | { |
9d773091 CW |
2519 | struct drm_i915_private *dev_priv = dev->dev_private; |
2520 | ||
2521 | /* reserve 0 for non-seqno */ | |
2522 | if (dev_priv->next_seqno == 0) { | |
fca26bb4 | 2523 | int ret = i915_gem_init_seqno(dev, 0); |
9d773091 CW |
2524 | if (ret) |
2525 | return ret; | |
53d227f2 | 2526 | |
9d773091 CW |
2527 | dev_priv->next_seqno = 1; |
2528 | } | |
53d227f2 | 2529 | |
f72b3435 | 2530 | *seqno = dev_priv->last_seqno = dev_priv->next_seqno++; |
9d773091 | 2531 | return 0; |
53d227f2 DV |
2532 | } |
2533 | ||
bf7dc5b7 JH |
2534 | /* |
2535 | * NB: This function is not allowed to fail. Doing so would mean the the | |
2536 | * request is not being tracked for completion but the work itself is | |
2537 | * going to happen on the hardware. This would be a Bad Thing(tm). | |
2538 | */ | |
75289874 | 2539 | void __i915_add_request(struct drm_i915_gem_request *request, |
5b4a60c2 JH |
2540 | struct drm_i915_gem_object *obj, |
2541 | bool flush_caches) | |
673a394b | 2542 | { |
e2f80391 | 2543 | struct intel_engine_cs *engine; |
75289874 | 2544 | struct drm_i915_private *dev_priv; |
48e29f55 | 2545 | struct intel_ringbuffer *ringbuf; |
6d3d8274 | 2546 | u32 request_start; |
3cce469c CW |
2547 | int ret; |
2548 | ||
48e29f55 | 2549 | if (WARN_ON(request == NULL)) |
bf7dc5b7 | 2550 | return; |
48e29f55 | 2551 | |
4a570db5 | 2552 | engine = request->engine; |
39dabecd | 2553 | dev_priv = request->i915; |
75289874 JH |
2554 | ringbuf = request->ringbuf; |
2555 | ||
29b1b415 JH |
2556 | /* |
2557 | * To ensure that this call will not fail, space for its emissions | |
2558 | * should already have been reserved in the ring buffer. Let the ring | |
2559 | * know that it is time to use that space up. | |
2560 | */ | |
2561 | intel_ring_reserved_space_use(ringbuf); | |
2562 | ||
48e29f55 | 2563 | request_start = intel_ring_get_tail(ringbuf); |
cc889e0f DV |
2564 | /* |
2565 | * Emit any outstanding flushes - execbuf can fail to emit the flush | |
2566 | * after having emitted the batchbuffer command. Hence we need to fix | |
2567 | * things up similar to emitting the lazy request. The difference here | |
2568 | * is that the flush _must_ happen before the next request, no matter | |
2569 | * what. | |
2570 | */ | |
5b4a60c2 JH |
2571 | if (flush_caches) { |
2572 | if (i915.enable_execlists) | |
4866d729 | 2573 | ret = logical_ring_flush_all_caches(request); |
5b4a60c2 | 2574 | else |
4866d729 | 2575 | ret = intel_ring_flush_all_caches(request); |
5b4a60c2 JH |
2576 | /* Not allowed to fail! */ |
2577 | WARN(ret, "*_ring_flush_all_caches failed: %d!\n", ret); | |
2578 | } | |
cc889e0f | 2579 | |
a71d8d94 CW |
2580 | /* Record the position of the start of the request so that |
2581 | * should we detect the updated seqno part-way through the | |
2582 | * GPU processing the request, we never over-estimate the | |
2583 | * position of the head. | |
2584 | */ | |
6d3d8274 | 2585 | request->postfix = intel_ring_get_tail(ringbuf); |
a71d8d94 | 2586 | |
bf7dc5b7 | 2587 | if (i915.enable_execlists) |
e2f80391 | 2588 | ret = engine->emit_request(request); |
bf7dc5b7 | 2589 | else { |
e2f80391 | 2590 | ret = engine->add_request(request); |
53292cdb MT |
2591 | |
2592 | request->tail = intel_ring_get_tail(ringbuf); | |
48e29f55 | 2593 | } |
bf7dc5b7 JH |
2594 | /* Not allowed to fail! */ |
2595 | WARN(ret, "emit|add_request failed: %d!\n", ret); | |
673a394b | 2596 | |
7d736f4f | 2597 | request->head = request_start; |
7d736f4f MK |
2598 | |
2599 | /* Whilst this request exists, batch_obj will be on the | |
2600 | * active_list, and so will hold the active reference. Only when this | |
2601 | * request is retired will the the batch_obj be moved onto the | |
2602 | * inactive_list and lose its active reference. Hence we do not need | |
2603 | * to explicitly hold another reference here. | |
2604 | */ | |
9a7e0c2a | 2605 | request->batch_obj = obj; |
0e50e96b | 2606 | |
673a394b | 2607 | request->emitted_jiffies = jiffies; |
e2f80391 TU |
2608 | request->previous_seqno = engine->last_submitted_seqno; |
2609 | engine->last_submitted_seqno = request->seqno; | |
2610 | list_add_tail(&request->list, &engine->request_list); | |
673a394b | 2611 | |
74328ee5 | 2612 | trace_i915_gem_request_add(request); |
db53a302 | 2613 | |
e2f80391 | 2614 | i915_queue_hangcheck(engine->dev); |
10cd45b6 | 2615 | |
87255483 DV |
2616 | queue_delayed_work(dev_priv->wq, |
2617 | &dev_priv->mm.retire_work, | |
2618 | round_jiffies_up_relative(HZ)); | |
2619 | intel_mark_busy(dev_priv->dev); | |
cc889e0f | 2620 | |
29b1b415 JH |
2621 | /* Sanity check that the reserved size was large enough. */ |
2622 | intel_ring_reserved_space_end(ringbuf); | |
673a394b EA |
2623 | } |
2624 | ||
939fd762 | 2625 | static bool i915_context_is_banned(struct drm_i915_private *dev_priv, |
273497e5 | 2626 | const struct intel_context *ctx) |
be62acb4 | 2627 | { |
44e2c070 | 2628 | unsigned long elapsed; |
be62acb4 | 2629 | |
44e2c070 MK |
2630 | elapsed = get_seconds() - ctx->hang_stats.guilty_ts; |
2631 | ||
2632 | if (ctx->hang_stats.banned) | |
be62acb4 MK |
2633 | return true; |
2634 | ||
676fa572 CW |
2635 | if (ctx->hang_stats.ban_period_seconds && |
2636 | elapsed <= ctx->hang_stats.ban_period_seconds) { | |
ccc7bed0 | 2637 | if (!i915_gem_context_is_default(ctx)) { |
3fac8978 | 2638 | DRM_DEBUG("context hanging too fast, banning!\n"); |
ccc7bed0 | 2639 | return true; |
88b4aa87 MK |
2640 | } else if (i915_stop_ring_allow_ban(dev_priv)) { |
2641 | if (i915_stop_ring_allow_warn(dev_priv)) | |
2642 | DRM_ERROR("gpu hanging too fast, banning!\n"); | |
ccc7bed0 | 2643 | return true; |
3fac8978 | 2644 | } |
be62acb4 MK |
2645 | } |
2646 | ||
2647 | return false; | |
2648 | } | |
2649 | ||
939fd762 | 2650 | static void i915_set_reset_status(struct drm_i915_private *dev_priv, |
273497e5 | 2651 | struct intel_context *ctx, |
b6b0fac0 | 2652 | const bool guilty) |
aa60c664 | 2653 | { |
44e2c070 MK |
2654 | struct i915_ctx_hang_stats *hs; |
2655 | ||
2656 | if (WARN_ON(!ctx)) | |
2657 | return; | |
aa60c664 | 2658 | |
44e2c070 MK |
2659 | hs = &ctx->hang_stats; |
2660 | ||
2661 | if (guilty) { | |
939fd762 | 2662 | hs->banned = i915_context_is_banned(dev_priv, ctx); |
44e2c070 MK |
2663 | hs->batch_active++; |
2664 | hs->guilty_ts = get_seconds(); | |
2665 | } else { | |
2666 | hs->batch_pending++; | |
aa60c664 MK |
2667 | } |
2668 | } | |
2669 | ||
abfe262a JH |
2670 | void i915_gem_request_free(struct kref *req_ref) |
2671 | { | |
2672 | struct drm_i915_gem_request *req = container_of(req_ref, | |
2673 | typeof(*req), ref); | |
2674 | struct intel_context *ctx = req->ctx; | |
2675 | ||
fcfa423c JH |
2676 | if (req->file_priv) |
2677 | i915_gem_request_remove_from_client(req); | |
2678 | ||
0794aed3 | 2679 | if (ctx) { |
e28e404c | 2680 | if (i915.enable_execlists && ctx != req->i915->kernel_context) |
4a570db5 | 2681 | intel_lr_context_unpin(ctx, req->engine); |
abfe262a | 2682 | |
dcb4c12a OM |
2683 | i915_gem_context_unreference(ctx); |
2684 | } | |
abfe262a | 2685 | |
efab6d8d | 2686 | kmem_cache_free(req->i915->requests, req); |
0e50e96b MK |
2687 | } |
2688 | ||
26827088 | 2689 | static inline int |
0bc40be8 | 2690 | __i915_gem_request_alloc(struct intel_engine_cs *engine, |
26827088 DG |
2691 | struct intel_context *ctx, |
2692 | struct drm_i915_gem_request **req_out) | |
6689cb2b | 2693 | { |
0bc40be8 | 2694 | struct drm_i915_private *dev_priv = to_i915(engine->dev); |
eed29a5b | 2695 | struct drm_i915_gem_request *req; |
6689cb2b | 2696 | int ret; |
6689cb2b | 2697 | |
217e46b5 JH |
2698 | if (!req_out) |
2699 | return -EINVAL; | |
2700 | ||
bccca494 | 2701 | *req_out = NULL; |
6689cb2b | 2702 | |
eed29a5b DV |
2703 | req = kmem_cache_zalloc(dev_priv->requests, GFP_KERNEL); |
2704 | if (req == NULL) | |
6689cb2b JH |
2705 | return -ENOMEM; |
2706 | ||
0bc40be8 | 2707 | ret = i915_gem_get_seqno(engine->dev, &req->seqno); |
9a0c1e27 CW |
2708 | if (ret) |
2709 | goto err; | |
6689cb2b | 2710 | |
40e895ce JH |
2711 | kref_init(&req->ref); |
2712 | req->i915 = dev_priv; | |
4a570db5 | 2713 | req->engine = engine; |
40e895ce JH |
2714 | req->ctx = ctx; |
2715 | i915_gem_context_reference(req->ctx); | |
6689cb2b JH |
2716 | |
2717 | if (i915.enable_execlists) | |
40e895ce | 2718 | ret = intel_logical_ring_alloc_request_extras(req); |
6689cb2b | 2719 | else |
eed29a5b | 2720 | ret = intel_ring_alloc_request_extras(req); |
40e895ce JH |
2721 | if (ret) { |
2722 | i915_gem_context_unreference(req->ctx); | |
9a0c1e27 | 2723 | goto err; |
40e895ce | 2724 | } |
6689cb2b | 2725 | |
29b1b415 JH |
2726 | /* |
2727 | * Reserve space in the ring buffer for all the commands required to | |
2728 | * eventually emit this request. This is to guarantee that the | |
2729 | * i915_add_request() call can't fail. Note that the reserve may need | |
2730 | * to be redone if the request is not actually submitted straight | |
2731 | * away, e.g. because a GPU scheduler has deferred it. | |
29b1b415 | 2732 | */ |
ccd98fe4 JH |
2733 | if (i915.enable_execlists) |
2734 | ret = intel_logical_ring_reserve_space(req); | |
2735 | else | |
2736 | ret = intel_ring_reserve_space(req); | |
2737 | if (ret) { | |
2738 | /* | |
2739 | * At this point, the request is fully allocated even if not | |
2740 | * fully prepared. Thus it can be cleaned up using the proper | |
2741 | * free code. | |
2742 | */ | |
2743 | i915_gem_request_cancel(req); | |
2744 | return ret; | |
2745 | } | |
29b1b415 | 2746 | |
bccca494 | 2747 | *req_out = req; |
6689cb2b | 2748 | return 0; |
9a0c1e27 CW |
2749 | |
2750 | err: | |
2751 | kmem_cache_free(dev_priv->requests, req); | |
2752 | return ret; | |
0e50e96b MK |
2753 | } |
2754 | ||
26827088 DG |
2755 | /** |
2756 | * i915_gem_request_alloc - allocate a request structure | |
2757 | * | |
2758 | * @engine: engine that we wish to issue the request on. | |
2759 | * @ctx: context that the request will be associated with. | |
2760 | * This can be NULL if the request is not directly related to | |
2761 | * any specific user context, in which case this function will | |
2762 | * choose an appropriate context to use. | |
2763 | * | |
2764 | * Returns a pointer to the allocated request if successful, | |
2765 | * or an error code if not. | |
2766 | */ | |
2767 | struct drm_i915_gem_request * | |
2768 | i915_gem_request_alloc(struct intel_engine_cs *engine, | |
2769 | struct intel_context *ctx) | |
2770 | { | |
2771 | struct drm_i915_gem_request *req; | |
2772 | int err; | |
2773 | ||
2774 | if (ctx == NULL) | |
ed54c1a1 | 2775 | ctx = to_i915(engine->dev)->kernel_context; |
26827088 DG |
2776 | err = __i915_gem_request_alloc(engine, ctx, &req); |
2777 | return err ? ERR_PTR(err) : req; | |
2778 | } | |
2779 | ||
29b1b415 JH |
2780 | void i915_gem_request_cancel(struct drm_i915_gem_request *req) |
2781 | { | |
2782 | intel_ring_reserved_space_cancel(req->ringbuf); | |
2783 | ||
2784 | i915_gem_request_unreference(req); | |
2785 | } | |
2786 | ||
8d9fc7fd | 2787 | struct drm_i915_gem_request * |
0bc40be8 | 2788 | i915_gem_find_active_request(struct intel_engine_cs *engine) |
9375e446 | 2789 | { |
4db080f9 CW |
2790 | struct drm_i915_gem_request *request; |
2791 | ||
0bc40be8 | 2792 | list_for_each_entry(request, &engine->request_list, list) { |
1b5a433a | 2793 | if (i915_gem_request_completed(request, false)) |
4db080f9 | 2794 | continue; |
aa60c664 | 2795 | |
b6b0fac0 | 2796 | return request; |
4db080f9 | 2797 | } |
b6b0fac0 MK |
2798 | |
2799 | return NULL; | |
2800 | } | |
2801 | ||
666796da | 2802 | static void i915_gem_reset_engine_status(struct drm_i915_private *dev_priv, |
0bc40be8 | 2803 | struct intel_engine_cs *engine) |
b6b0fac0 MK |
2804 | { |
2805 | struct drm_i915_gem_request *request; | |
2806 | bool ring_hung; | |
2807 | ||
0bc40be8 | 2808 | request = i915_gem_find_active_request(engine); |
b6b0fac0 MK |
2809 | |
2810 | if (request == NULL) | |
2811 | return; | |
2812 | ||
0bc40be8 | 2813 | ring_hung = engine->hangcheck.score >= HANGCHECK_SCORE_RING_HUNG; |
b6b0fac0 | 2814 | |
939fd762 | 2815 | i915_set_reset_status(dev_priv, request->ctx, ring_hung); |
b6b0fac0 | 2816 | |
0bc40be8 | 2817 | list_for_each_entry_continue(request, &engine->request_list, list) |
939fd762 | 2818 | i915_set_reset_status(dev_priv, request->ctx, false); |
4db080f9 | 2819 | } |
aa60c664 | 2820 | |
666796da | 2821 | static void i915_gem_reset_engine_cleanup(struct drm_i915_private *dev_priv, |
0bc40be8 | 2822 | struct intel_engine_cs *engine) |
4db080f9 | 2823 | { |
608c1a52 CW |
2824 | struct intel_ringbuffer *buffer; |
2825 | ||
0bc40be8 | 2826 | while (!list_empty(&engine->active_list)) { |
05394f39 | 2827 | struct drm_i915_gem_object *obj; |
9375e446 | 2828 | |
0bc40be8 | 2829 | obj = list_first_entry(&engine->active_list, |
05394f39 | 2830 | struct drm_i915_gem_object, |
117897f4 | 2831 | engine_list[engine->id]); |
9375e446 | 2832 | |
0bc40be8 | 2833 | i915_gem_object_retire__read(obj, engine->id); |
673a394b | 2834 | } |
1d62beea | 2835 | |
dcb4c12a OM |
2836 | /* |
2837 | * Clear the execlists queue up before freeing the requests, as those | |
2838 | * are the ones that keep the context and ringbuffer backing objects | |
2839 | * pinned in place. | |
2840 | */ | |
dcb4c12a | 2841 | |
7de1691a | 2842 | if (i915.enable_execlists) { |
0bc40be8 | 2843 | spin_lock_irq(&engine->execlist_lock); |
1197b4f2 | 2844 | |
c5baa566 | 2845 | /* list_splice_tail_init checks for empty lists */ |
0bc40be8 TU |
2846 | list_splice_tail_init(&engine->execlist_queue, |
2847 | &engine->execlist_retired_req_list); | |
1197b4f2 | 2848 | |
0bc40be8 TU |
2849 | spin_unlock_irq(&engine->execlist_lock); |
2850 | intel_execlists_retire_requests(engine); | |
dcb4c12a OM |
2851 | } |
2852 | ||
1d62beea BW |
2853 | /* |
2854 | * We must free the requests after all the corresponding objects have | |
2855 | * been moved off active lists. Which is the same order as the normal | |
2856 | * retire_requests function does. This is important if object hold | |
2857 | * implicit references on things like e.g. ppgtt address spaces through | |
2858 | * the request. | |
2859 | */ | |
0bc40be8 | 2860 | while (!list_empty(&engine->request_list)) { |
1d62beea BW |
2861 | struct drm_i915_gem_request *request; |
2862 | ||
0bc40be8 | 2863 | request = list_first_entry(&engine->request_list, |
1d62beea BW |
2864 | struct drm_i915_gem_request, |
2865 | list); | |
2866 | ||
b4716185 | 2867 | i915_gem_request_retire(request); |
1d62beea | 2868 | } |
608c1a52 CW |
2869 | |
2870 | /* Having flushed all requests from all queues, we know that all | |
2871 | * ringbuffers must now be empty. However, since we do not reclaim | |
2872 | * all space when retiring the request (to prevent HEADs colliding | |
2873 | * with rapid ringbuffer wraparound) the amount of available space | |
2874 | * upon reset is less than when we start. Do one more pass over | |
2875 | * all the ringbuffers to reset last_retired_head. | |
2876 | */ | |
0bc40be8 | 2877 | list_for_each_entry(buffer, &engine->buffers, link) { |
608c1a52 CW |
2878 | buffer->last_retired_head = buffer->tail; |
2879 | intel_ring_update_space(buffer); | |
2880 | } | |
673a394b EA |
2881 | } |
2882 | ||
069efc1d | 2883 | void i915_gem_reset(struct drm_device *dev) |
673a394b | 2884 | { |
77f01230 | 2885 | struct drm_i915_private *dev_priv = dev->dev_private; |
e2f80391 | 2886 | struct intel_engine_cs *engine; |
673a394b | 2887 | |
4db080f9 CW |
2888 | /* |
2889 | * Before we free the objects from the requests, we need to inspect | |
2890 | * them for finding the guilty party. As the requests only borrow | |
2891 | * their reference to the objects, the inspection must be done first. | |
2892 | */ | |
b4ac5afc | 2893 | for_each_engine(engine, dev_priv) |
666796da | 2894 | i915_gem_reset_engine_status(dev_priv, engine); |
4db080f9 | 2895 | |
b4ac5afc | 2896 | for_each_engine(engine, dev_priv) |
666796da | 2897 | i915_gem_reset_engine_cleanup(dev_priv, engine); |
dfaae392 | 2898 | |
acce9ffa BW |
2899 | i915_gem_context_reset(dev); |
2900 | ||
19b2dbde | 2901 | i915_gem_restore_fences(dev); |
b4716185 CW |
2902 | |
2903 | WARN_ON(i915_verify_lists(dev)); | |
673a394b EA |
2904 | } |
2905 | ||
2906 | /** | |
2907 | * This function clears the request list as sequence numbers are passed. | |
2908 | */ | |
1cf0ba14 | 2909 | void |
0bc40be8 | 2910 | i915_gem_retire_requests_ring(struct intel_engine_cs *engine) |
673a394b | 2911 | { |
0bc40be8 | 2912 | WARN_ON(i915_verify_lists(engine->dev)); |
673a394b | 2913 | |
832a3aad CW |
2914 | /* Retire requests first as we use it above for the early return. |
2915 | * If we retire requests last, we may use a later seqno and so clear | |
2916 | * the requests lists without clearing the active list, leading to | |
2917 | * confusion. | |
e9103038 | 2918 | */ |
0bc40be8 | 2919 | while (!list_empty(&engine->request_list)) { |
673a394b | 2920 | struct drm_i915_gem_request *request; |
673a394b | 2921 | |
0bc40be8 | 2922 | request = list_first_entry(&engine->request_list, |
673a394b EA |
2923 | struct drm_i915_gem_request, |
2924 | list); | |
673a394b | 2925 | |
1b5a433a | 2926 | if (!i915_gem_request_completed(request, true)) |
b84d5f0c CW |
2927 | break; |
2928 | ||
b4716185 | 2929 | i915_gem_request_retire(request); |
b84d5f0c | 2930 | } |
673a394b | 2931 | |
832a3aad CW |
2932 | /* Move any buffers on the active list that are no longer referenced |
2933 | * by the ringbuffer to the flushing/inactive lists as appropriate, | |
2934 | * before we free the context associated with the requests. | |
2935 | */ | |
0bc40be8 | 2936 | while (!list_empty(&engine->active_list)) { |
832a3aad CW |
2937 | struct drm_i915_gem_object *obj; |
2938 | ||
0bc40be8 TU |
2939 | obj = list_first_entry(&engine->active_list, |
2940 | struct drm_i915_gem_object, | |
117897f4 | 2941 | engine_list[engine->id]); |
832a3aad | 2942 | |
0bc40be8 | 2943 | if (!list_empty(&obj->last_read_req[engine->id]->list)) |
832a3aad CW |
2944 | break; |
2945 | ||
0bc40be8 | 2946 | i915_gem_object_retire__read(obj, engine->id); |
832a3aad CW |
2947 | } |
2948 | ||
0bc40be8 TU |
2949 | if (unlikely(engine->trace_irq_req && |
2950 | i915_gem_request_completed(engine->trace_irq_req, true))) { | |
2951 | engine->irq_put(engine); | |
2952 | i915_gem_request_assign(&engine->trace_irq_req, NULL); | |
9d34e5db | 2953 | } |
23bc5982 | 2954 | |
0bc40be8 | 2955 | WARN_ON(i915_verify_lists(engine->dev)); |
673a394b EA |
2956 | } |
2957 | ||
b29c19b6 | 2958 | bool |
b09a1fec CW |
2959 | i915_gem_retire_requests(struct drm_device *dev) |
2960 | { | |
3e31c6c0 | 2961 | struct drm_i915_private *dev_priv = dev->dev_private; |
e2f80391 | 2962 | struct intel_engine_cs *engine; |
b29c19b6 | 2963 | bool idle = true; |
b09a1fec | 2964 | |
b4ac5afc | 2965 | for_each_engine(engine, dev_priv) { |
e2f80391 TU |
2966 | i915_gem_retire_requests_ring(engine); |
2967 | idle &= list_empty(&engine->request_list); | |
c86ee3a9 | 2968 | if (i915.enable_execlists) { |
e2f80391 TU |
2969 | spin_lock_irq(&engine->execlist_lock); |
2970 | idle &= list_empty(&engine->execlist_queue); | |
2971 | spin_unlock_irq(&engine->execlist_lock); | |
c86ee3a9 | 2972 | |
e2f80391 | 2973 | intel_execlists_retire_requests(engine); |
c86ee3a9 | 2974 | } |
b29c19b6 CW |
2975 | } |
2976 | ||
2977 | if (idle) | |
2978 | mod_delayed_work(dev_priv->wq, | |
2979 | &dev_priv->mm.idle_work, | |
2980 | msecs_to_jiffies(100)); | |
2981 | ||
2982 | return idle; | |
b09a1fec CW |
2983 | } |
2984 | ||
75ef9da2 | 2985 | static void |
673a394b EA |
2986 | i915_gem_retire_work_handler(struct work_struct *work) |
2987 | { | |
b29c19b6 CW |
2988 | struct drm_i915_private *dev_priv = |
2989 | container_of(work, typeof(*dev_priv), mm.retire_work.work); | |
2990 | struct drm_device *dev = dev_priv->dev; | |
0a58705b | 2991 | bool idle; |
673a394b | 2992 | |
891b48cf | 2993 | /* Come back later if the device is busy... */ |
b29c19b6 CW |
2994 | idle = false; |
2995 | if (mutex_trylock(&dev->struct_mutex)) { | |
2996 | idle = i915_gem_retire_requests(dev); | |
2997 | mutex_unlock(&dev->struct_mutex); | |
673a394b | 2998 | } |
b29c19b6 | 2999 | if (!idle) |
bcb45086 CW |
3000 | queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, |
3001 | round_jiffies_up_relative(HZ)); | |
b29c19b6 | 3002 | } |
0a58705b | 3003 | |
b29c19b6 CW |
3004 | static void |
3005 | i915_gem_idle_work_handler(struct work_struct *work) | |
3006 | { | |
3007 | struct drm_i915_private *dev_priv = | |
3008 | container_of(work, typeof(*dev_priv), mm.idle_work.work); | |
35c94185 | 3009 | struct drm_device *dev = dev_priv->dev; |
b4ac5afc | 3010 | struct intel_engine_cs *engine; |
b29c19b6 | 3011 | |
b4ac5afc DG |
3012 | for_each_engine(engine, dev_priv) |
3013 | if (!list_empty(&engine->request_list)) | |
423795cb | 3014 | return; |
35c94185 | 3015 | |
30ecad77 | 3016 | /* we probably should sync with hangcheck here, using cancel_work_sync. |
b4ac5afc | 3017 | * Also locking seems to be fubar here, engine->request_list is protected |
30ecad77 DV |
3018 | * by dev->struct_mutex. */ |
3019 | ||
35c94185 CW |
3020 | intel_mark_idle(dev); |
3021 | ||
3022 | if (mutex_trylock(&dev->struct_mutex)) { | |
b4ac5afc | 3023 | for_each_engine(engine, dev_priv) |
e2f80391 | 3024 | i915_gem_batch_pool_fini(&engine->batch_pool); |
b29c19b6 | 3025 | |
35c94185 CW |
3026 | mutex_unlock(&dev->struct_mutex); |
3027 | } | |
673a394b EA |
3028 | } |
3029 | ||
30dfebf3 DV |
3030 | /** |
3031 | * Ensures that an object will eventually get non-busy by flushing any required | |
3032 | * write domains, emitting any outstanding lazy request and retiring and | |
3033 | * completed requests. | |
3034 | */ | |
3035 | static int | |
3036 | i915_gem_object_flush_active(struct drm_i915_gem_object *obj) | |
3037 | { | |
a5ac0f90 | 3038 | int i; |
b4716185 CW |
3039 | |
3040 | if (!obj->active) | |
3041 | return 0; | |
30dfebf3 | 3042 | |
666796da | 3043 | for (i = 0; i < I915_NUM_ENGINES; i++) { |
b4716185 | 3044 | struct drm_i915_gem_request *req; |
41c52415 | 3045 | |
b4716185 CW |
3046 | req = obj->last_read_req[i]; |
3047 | if (req == NULL) | |
3048 | continue; | |
3049 | ||
3050 | if (list_empty(&req->list)) | |
3051 | goto retire; | |
3052 | ||
b4716185 CW |
3053 | if (i915_gem_request_completed(req, true)) { |
3054 | __i915_gem_request_retire__upto(req); | |
3055 | retire: | |
3056 | i915_gem_object_retire__read(obj, i); | |
3057 | } | |
30dfebf3 DV |
3058 | } |
3059 | ||
3060 | return 0; | |
3061 | } | |
3062 | ||
23ba4fd0 BW |
3063 | /** |
3064 | * i915_gem_wait_ioctl - implements DRM_IOCTL_I915_GEM_WAIT | |
3065 | * @DRM_IOCTL_ARGS: standard ioctl arguments | |
3066 | * | |
3067 | * Returns 0 if successful, else an error is returned with the remaining time in | |
3068 | * the timeout parameter. | |
3069 | * -ETIME: object is still busy after timeout | |
3070 | * -ERESTARTSYS: signal interrupted the wait | |
3071 | * -ENONENT: object doesn't exist | |
3072 | * Also possible, but rare: | |
3073 | * -EAGAIN: GPU wedged | |
3074 | * -ENOMEM: damn | |
3075 | * -ENODEV: Internal IRQ fail | |
3076 | * -E?: The add request failed | |
3077 | * | |
3078 | * The wait ioctl with a timeout of 0 reimplements the busy ioctl. With any | |
3079 | * non-zero timeout parameter the wait ioctl will wait for the given number of | |
3080 | * nanoseconds on an object becoming unbusy. Since the wait itself does so | |
3081 | * without holding struct_mutex the object may become re-busied before this | |
3082 | * function completes. A similar but shorter * race condition exists in the busy | |
3083 | * ioctl | |
3084 | */ | |
3085 | int | |
3086 | i915_gem_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *file) | |
3087 | { | |
3e31c6c0 | 3088 | struct drm_i915_private *dev_priv = dev->dev_private; |
23ba4fd0 BW |
3089 | struct drm_i915_gem_wait *args = data; |
3090 | struct drm_i915_gem_object *obj; | |
666796da | 3091 | struct drm_i915_gem_request *req[I915_NUM_ENGINES]; |
f69061be | 3092 | unsigned reset_counter; |
b4716185 CW |
3093 | int i, n = 0; |
3094 | int ret; | |
23ba4fd0 | 3095 | |
11b5d511 DV |
3096 | if (args->flags != 0) |
3097 | return -EINVAL; | |
3098 | ||
23ba4fd0 BW |
3099 | ret = i915_mutex_lock_interruptible(dev); |
3100 | if (ret) | |
3101 | return ret; | |
3102 | ||
3103 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->bo_handle)); | |
3104 | if (&obj->base == NULL) { | |
3105 | mutex_unlock(&dev->struct_mutex); | |
3106 | return -ENOENT; | |
3107 | } | |
3108 | ||
30dfebf3 DV |
3109 | /* Need to make sure the object gets inactive eventually. */ |
3110 | ret = i915_gem_object_flush_active(obj); | |
23ba4fd0 BW |
3111 | if (ret) |
3112 | goto out; | |
3113 | ||
b4716185 | 3114 | if (!obj->active) |
97b2a6a1 | 3115 | goto out; |
23ba4fd0 | 3116 | |
23ba4fd0 | 3117 | /* Do this after OLR check to make sure we make forward progress polling |
762e4583 | 3118 | * on this IOCTL with a timeout == 0 (like busy ioctl) |
23ba4fd0 | 3119 | */ |
762e4583 | 3120 | if (args->timeout_ns == 0) { |
23ba4fd0 BW |
3121 | ret = -ETIME; |
3122 | goto out; | |
3123 | } | |
3124 | ||
3125 | drm_gem_object_unreference(&obj->base); | |
f69061be | 3126 | reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter); |
b4716185 | 3127 | |
666796da | 3128 | for (i = 0; i < I915_NUM_ENGINES; i++) { |
b4716185 CW |
3129 | if (obj->last_read_req[i] == NULL) |
3130 | continue; | |
3131 | ||
3132 | req[n++] = i915_gem_request_reference(obj->last_read_req[i]); | |
3133 | } | |
3134 | ||
23ba4fd0 BW |
3135 | mutex_unlock(&dev->struct_mutex); |
3136 | ||
b4716185 CW |
3137 | for (i = 0; i < n; i++) { |
3138 | if (ret == 0) | |
3139 | ret = __i915_wait_request(req[i], reset_counter, true, | |
3140 | args->timeout_ns > 0 ? &args->timeout_ns : NULL, | |
b6aa0873 | 3141 | to_rps_client(file)); |
b4716185 CW |
3142 | i915_gem_request_unreference__unlocked(req[i]); |
3143 | } | |
ff865885 | 3144 | return ret; |
23ba4fd0 BW |
3145 | |
3146 | out: | |
3147 | drm_gem_object_unreference(&obj->base); | |
3148 | mutex_unlock(&dev->struct_mutex); | |
3149 | return ret; | |
3150 | } | |
3151 | ||
b4716185 CW |
3152 | static int |
3153 | __i915_gem_object_sync(struct drm_i915_gem_object *obj, | |
3154 | struct intel_engine_cs *to, | |
91af127f JH |
3155 | struct drm_i915_gem_request *from_req, |
3156 | struct drm_i915_gem_request **to_req) | |
b4716185 CW |
3157 | { |
3158 | struct intel_engine_cs *from; | |
3159 | int ret; | |
3160 | ||
666796da | 3161 | from = i915_gem_request_get_engine(from_req); |
b4716185 CW |
3162 | if (to == from) |
3163 | return 0; | |
3164 | ||
91af127f | 3165 | if (i915_gem_request_completed(from_req, true)) |
b4716185 CW |
3166 | return 0; |
3167 | ||
b4716185 | 3168 | if (!i915_semaphore_is_enabled(obj->base.dev)) { |
a6f766f3 | 3169 | struct drm_i915_private *i915 = to_i915(obj->base.dev); |
91af127f | 3170 | ret = __i915_wait_request(from_req, |
a6f766f3 CW |
3171 | atomic_read(&i915->gpu_error.reset_counter), |
3172 | i915->mm.interruptible, | |
3173 | NULL, | |
3174 | &i915->rps.semaphores); | |
b4716185 CW |
3175 | if (ret) |
3176 | return ret; | |
3177 | ||
91af127f | 3178 | i915_gem_object_retire_request(obj, from_req); |
b4716185 CW |
3179 | } else { |
3180 | int idx = intel_ring_sync_index(from, to); | |
91af127f JH |
3181 | u32 seqno = i915_gem_request_get_seqno(from_req); |
3182 | ||
3183 | WARN_ON(!to_req); | |
b4716185 CW |
3184 | |
3185 | if (seqno <= from->semaphore.sync_seqno[idx]) | |
3186 | return 0; | |
3187 | ||
91af127f | 3188 | if (*to_req == NULL) { |
26827088 DG |
3189 | struct drm_i915_gem_request *req; |
3190 | ||
3191 | req = i915_gem_request_alloc(to, NULL); | |
3192 | if (IS_ERR(req)) | |
3193 | return PTR_ERR(req); | |
3194 | ||
3195 | *to_req = req; | |
91af127f JH |
3196 | } |
3197 | ||
599d924c JH |
3198 | trace_i915_gem_ring_sync_to(*to_req, from, from_req); |
3199 | ret = to->semaphore.sync_to(*to_req, from, seqno); | |
b4716185 CW |
3200 | if (ret) |
3201 | return ret; | |
3202 | ||
3203 | /* We use last_read_req because sync_to() | |
3204 | * might have just caused seqno wrap under | |
3205 | * the radar. | |
3206 | */ | |
3207 | from->semaphore.sync_seqno[idx] = | |
3208 | i915_gem_request_get_seqno(obj->last_read_req[from->id]); | |
3209 | } | |
3210 | ||
3211 | return 0; | |
3212 | } | |
3213 | ||
5816d648 BW |
3214 | /** |
3215 | * i915_gem_object_sync - sync an object to a ring. | |
3216 | * | |
3217 | * @obj: object which may be in use on another ring. | |
3218 | * @to: ring we wish to use the object on. May be NULL. | |
91af127f JH |
3219 | * @to_req: request we wish to use the object for. See below. |
3220 | * This will be allocated and returned if a request is | |
3221 | * required but not passed in. | |
5816d648 BW |
3222 | * |
3223 | * This code is meant to abstract object synchronization with the GPU. | |
3224 | * Calling with NULL implies synchronizing the object with the CPU | |
b4716185 | 3225 | * rather than a particular GPU ring. Conceptually we serialise writes |
91af127f | 3226 | * between engines inside the GPU. We only allow one engine to write |
b4716185 CW |
3227 | * into a buffer at any time, but multiple readers. To ensure each has |
3228 | * a coherent view of memory, we must: | |
3229 | * | |
3230 | * - If there is an outstanding write request to the object, the new | |
3231 | * request must wait for it to complete (either CPU or in hw, requests | |
3232 | * on the same ring will be naturally ordered). | |
3233 | * | |
3234 | * - If we are a write request (pending_write_domain is set), the new | |
3235 | * request must wait for outstanding read requests to complete. | |
5816d648 | 3236 | * |
91af127f JH |
3237 | * For CPU synchronisation (NULL to) no request is required. For syncing with |
3238 | * rings to_req must be non-NULL. However, a request does not have to be | |
3239 | * pre-allocated. If *to_req is NULL and sync commands will be emitted then a | |
3240 | * request will be allocated automatically and returned through *to_req. Note | |
3241 | * that it is not guaranteed that commands will be emitted (because the system | |
3242 | * might already be idle). Hence there is no need to create a request that | |
3243 | * might never have any work submitted. Note further that if a request is | |
3244 | * returned in *to_req, it is the responsibility of the caller to submit | |
3245 | * that request (after potentially adding more work to it). | |
3246 | * | |
5816d648 BW |
3247 | * Returns 0 if successful, else propagates up the lower layer error. |
3248 | */ | |
2911a35b BW |
3249 | int |
3250 | i915_gem_object_sync(struct drm_i915_gem_object *obj, | |
91af127f JH |
3251 | struct intel_engine_cs *to, |
3252 | struct drm_i915_gem_request **to_req) | |
2911a35b | 3253 | { |
b4716185 | 3254 | const bool readonly = obj->base.pending_write_domain == 0; |
666796da | 3255 | struct drm_i915_gem_request *req[I915_NUM_ENGINES]; |
b4716185 | 3256 | int ret, i, n; |
41c52415 | 3257 | |
b4716185 | 3258 | if (!obj->active) |
2911a35b BW |
3259 | return 0; |
3260 | ||
b4716185 CW |
3261 | if (to == NULL) |
3262 | return i915_gem_object_wait_rendering(obj, readonly); | |
2911a35b | 3263 | |
b4716185 CW |
3264 | n = 0; |
3265 | if (readonly) { | |
3266 | if (obj->last_write_req) | |
3267 | req[n++] = obj->last_write_req; | |
3268 | } else { | |
666796da | 3269 | for (i = 0; i < I915_NUM_ENGINES; i++) |
b4716185 CW |
3270 | if (obj->last_read_req[i]) |
3271 | req[n++] = obj->last_read_req[i]; | |
3272 | } | |
3273 | for (i = 0; i < n; i++) { | |
91af127f | 3274 | ret = __i915_gem_object_sync(obj, to, req[i], to_req); |
b4716185 CW |
3275 | if (ret) |
3276 | return ret; | |
3277 | } | |
2911a35b | 3278 | |
b4716185 | 3279 | return 0; |
2911a35b BW |
3280 | } |
3281 | ||
b5ffc9bc CW |
3282 | static void i915_gem_object_finish_gtt(struct drm_i915_gem_object *obj) |
3283 | { | |
3284 | u32 old_write_domain, old_read_domains; | |
3285 | ||
b5ffc9bc CW |
3286 | /* Force a pagefault for domain tracking on next user access */ |
3287 | i915_gem_release_mmap(obj); | |
3288 | ||
b97c3d9c KP |
3289 | if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0) |
3290 | return; | |
3291 | ||
97c809fd CW |
3292 | /* Wait for any direct GTT access to complete */ |
3293 | mb(); | |
3294 | ||
b5ffc9bc CW |
3295 | old_read_domains = obj->base.read_domains; |
3296 | old_write_domain = obj->base.write_domain; | |
3297 | ||
3298 | obj->base.read_domains &= ~I915_GEM_DOMAIN_GTT; | |
3299 | obj->base.write_domain &= ~I915_GEM_DOMAIN_GTT; | |
3300 | ||
3301 | trace_i915_gem_object_change_domain(obj, | |
3302 | old_read_domains, | |
3303 | old_write_domain); | |
3304 | } | |
3305 | ||
e9f24d5f | 3306 | static int __i915_vma_unbind(struct i915_vma *vma, bool wait) |
673a394b | 3307 | { |
07fe0b12 | 3308 | struct drm_i915_gem_object *obj = vma->obj; |
3e31c6c0 | 3309 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
43e28f09 | 3310 | int ret; |
673a394b | 3311 | |
1c7f4bca | 3312 | if (list_empty(&vma->obj_link)) |
673a394b EA |
3313 | return 0; |
3314 | ||
0ff501cb DV |
3315 | if (!drm_mm_node_allocated(&vma->node)) { |
3316 | i915_gem_vma_destroy(vma); | |
0ff501cb DV |
3317 | return 0; |
3318 | } | |
433544bd | 3319 | |
d7f46fc4 | 3320 | if (vma->pin_count) |
31d8d651 | 3321 | return -EBUSY; |
673a394b | 3322 | |
c4670ad0 CW |
3323 | BUG_ON(obj->pages == NULL); |
3324 | ||
e9f24d5f TU |
3325 | if (wait) { |
3326 | ret = i915_gem_object_wait_rendering(obj, false); | |
3327 | if (ret) | |
3328 | return ret; | |
3329 | } | |
a8198eea | 3330 | |
596c5923 | 3331 | if (vma->is_ggtt && vma->ggtt_view.type == I915_GGTT_VIEW_NORMAL) { |
8b1bc9b4 | 3332 | i915_gem_object_finish_gtt(obj); |
5323fd04 | 3333 | |
8b1bc9b4 DV |
3334 | /* release the fence reg _after_ flushing */ |
3335 | ret = i915_gem_object_put_fence(obj); | |
3336 | if (ret) | |
3337 | return ret; | |
3338 | } | |
96b47b65 | 3339 | |
07fe0b12 | 3340 | trace_i915_vma_unbind(vma); |
db53a302 | 3341 | |
777dc5bb | 3342 | vma->vm->unbind_vma(vma); |
5e562f1d | 3343 | vma->bound = 0; |
6f65e29a | 3344 | |
1c7f4bca | 3345 | list_del_init(&vma->vm_link); |
596c5923 | 3346 | if (vma->is_ggtt) { |
fe14d5f4 TU |
3347 | if (vma->ggtt_view.type == I915_GGTT_VIEW_NORMAL) { |
3348 | obj->map_and_fenceable = false; | |
3349 | } else if (vma->ggtt_view.pages) { | |
3350 | sg_free_table(vma->ggtt_view.pages); | |
3351 | kfree(vma->ggtt_view.pages); | |
fe14d5f4 | 3352 | } |
016a65a3 | 3353 | vma->ggtt_view.pages = NULL; |
fe14d5f4 | 3354 | } |
673a394b | 3355 | |
2f633156 BW |
3356 | drm_mm_remove_node(&vma->node); |
3357 | i915_gem_vma_destroy(vma); | |
3358 | ||
3359 | /* Since the unbound list is global, only move to that list if | |
b93dab6e | 3360 | * no more VMAs exist. */ |
e2273302 | 3361 | if (list_empty(&obj->vma_list)) |
2f633156 | 3362 | list_move_tail(&obj->global_list, &dev_priv->mm.unbound_list); |
673a394b | 3363 | |
70903c3b CW |
3364 | /* And finally now the object is completely decoupled from this vma, |
3365 | * we can drop its hold on the backing storage and allow it to be | |
3366 | * reaped by the shrinker. | |
3367 | */ | |
3368 | i915_gem_object_unpin_pages(obj); | |
3369 | ||
88241785 | 3370 | return 0; |
54cf91dc CW |
3371 | } |
3372 | ||
e9f24d5f TU |
3373 | int i915_vma_unbind(struct i915_vma *vma) |
3374 | { | |
3375 | return __i915_vma_unbind(vma, true); | |
3376 | } | |
3377 | ||
3378 | int __i915_vma_unbind_no_wait(struct i915_vma *vma) | |
3379 | { | |
3380 | return __i915_vma_unbind(vma, false); | |
3381 | } | |
3382 | ||
b2da9fe5 | 3383 | int i915_gpu_idle(struct drm_device *dev) |
4df2faf4 | 3384 | { |
3e31c6c0 | 3385 | struct drm_i915_private *dev_priv = dev->dev_private; |
e2f80391 | 3386 | struct intel_engine_cs *engine; |
b4ac5afc | 3387 | int ret; |
4df2faf4 | 3388 | |
4df2faf4 | 3389 | /* Flush everything onto the inactive list. */ |
b4ac5afc | 3390 | for_each_engine(engine, dev_priv) { |
ecdb5fd8 | 3391 | if (!i915.enable_execlists) { |
73cfa865 JH |
3392 | struct drm_i915_gem_request *req; |
3393 | ||
e2f80391 | 3394 | req = i915_gem_request_alloc(engine, NULL); |
26827088 DG |
3395 | if (IS_ERR(req)) |
3396 | return PTR_ERR(req); | |
73cfa865 | 3397 | |
ba01cc93 | 3398 | ret = i915_switch_context(req); |
73cfa865 JH |
3399 | if (ret) { |
3400 | i915_gem_request_cancel(req); | |
3401 | return ret; | |
3402 | } | |
3403 | ||
75289874 | 3404 | i915_add_request_no_flush(req); |
ecdb5fd8 | 3405 | } |
b6c7488d | 3406 | |
666796da | 3407 | ret = intel_engine_idle(engine); |
1ec14ad3 CW |
3408 | if (ret) |
3409 | return ret; | |
3410 | } | |
4df2faf4 | 3411 | |
b4716185 | 3412 | WARN_ON(i915_verify_lists(dev)); |
8a1a49f9 | 3413 | return 0; |
4df2faf4 DV |
3414 | } |
3415 | ||
4144f9b5 | 3416 | static bool i915_gem_valid_gtt_space(struct i915_vma *vma, |
42d6ab48 CW |
3417 | unsigned long cache_level) |
3418 | { | |
4144f9b5 | 3419 | struct drm_mm_node *gtt_space = &vma->node; |
42d6ab48 CW |
3420 | struct drm_mm_node *other; |
3421 | ||
4144f9b5 CW |
3422 | /* |
3423 | * On some machines we have to be careful when putting differing types | |
3424 | * of snoopable memory together to avoid the prefetcher crossing memory | |
3425 | * domains and dying. During vm initialisation, we decide whether or not | |
3426 | * these constraints apply and set the drm_mm.color_adjust | |
3427 | * appropriately. | |
42d6ab48 | 3428 | */ |
4144f9b5 | 3429 | if (vma->vm->mm.color_adjust == NULL) |
42d6ab48 CW |
3430 | return true; |
3431 | ||
c6cfb325 | 3432 | if (!drm_mm_node_allocated(gtt_space)) |
42d6ab48 CW |
3433 | return true; |
3434 | ||
3435 | if (list_empty(>t_space->node_list)) | |
3436 | return true; | |
3437 | ||
3438 | other = list_entry(gtt_space->node_list.prev, struct drm_mm_node, node_list); | |
3439 | if (other->allocated && !other->hole_follows && other->color != cache_level) | |
3440 | return false; | |
3441 | ||
3442 | other = list_entry(gtt_space->node_list.next, struct drm_mm_node, node_list); | |
3443 | if (other->allocated && !gtt_space->hole_follows && other->color != cache_level) | |
3444 | return false; | |
3445 | ||
3446 | return true; | |
3447 | } | |
3448 | ||
673a394b | 3449 | /** |
91e6711e JL |
3450 | * Finds free space in the GTT aperture and binds the object or a view of it |
3451 | * there. | |
673a394b | 3452 | */ |
262de145 | 3453 | static struct i915_vma * |
07fe0b12 BW |
3454 | i915_gem_object_bind_to_vm(struct drm_i915_gem_object *obj, |
3455 | struct i915_address_space *vm, | |
ec7adb6e | 3456 | const struct i915_ggtt_view *ggtt_view, |
07fe0b12 | 3457 | unsigned alignment, |
ec7adb6e | 3458 | uint64_t flags) |
673a394b | 3459 | { |
05394f39 | 3460 | struct drm_device *dev = obj->base.dev; |
3e31c6c0 | 3461 | struct drm_i915_private *dev_priv = dev->dev_private; |
65bd342f | 3462 | u32 fence_alignment, unfenced_alignment; |
101b506a MT |
3463 | u32 search_flag, alloc_flag; |
3464 | u64 start, end; | |
65bd342f | 3465 | u64 size, fence_size; |
2f633156 | 3466 | struct i915_vma *vma; |
07f73f69 | 3467 | int ret; |
673a394b | 3468 | |
91e6711e JL |
3469 | if (i915_is_ggtt(vm)) { |
3470 | u32 view_size; | |
3471 | ||
3472 | if (WARN_ON(!ggtt_view)) | |
3473 | return ERR_PTR(-EINVAL); | |
ec7adb6e | 3474 | |
91e6711e JL |
3475 | view_size = i915_ggtt_view_size(obj, ggtt_view); |
3476 | ||
3477 | fence_size = i915_gem_get_gtt_size(dev, | |
3478 | view_size, | |
3479 | obj->tiling_mode); | |
3480 | fence_alignment = i915_gem_get_gtt_alignment(dev, | |
3481 | view_size, | |
3482 | obj->tiling_mode, | |
3483 | true); | |
3484 | unfenced_alignment = i915_gem_get_gtt_alignment(dev, | |
3485 | view_size, | |
3486 | obj->tiling_mode, | |
3487 | false); | |
3488 | size = flags & PIN_MAPPABLE ? fence_size : view_size; | |
3489 | } else { | |
3490 | fence_size = i915_gem_get_gtt_size(dev, | |
3491 | obj->base.size, | |
3492 | obj->tiling_mode); | |
3493 | fence_alignment = i915_gem_get_gtt_alignment(dev, | |
3494 | obj->base.size, | |
3495 | obj->tiling_mode, | |
3496 | true); | |
3497 | unfenced_alignment = | |
3498 | i915_gem_get_gtt_alignment(dev, | |
3499 | obj->base.size, | |
3500 | obj->tiling_mode, | |
3501 | false); | |
3502 | size = flags & PIN_MAPPABLE ? fence_size : obj->base.size; | |
3503 | } | |
a00b10c3 | 3504 | |
101b506a MT |
3505 | start = flags & PIN_OFFSET_BIAS ? flags & PIN_OFFSET_MASK : 0; |
3506 | end = vm->total; | |
3507 | if (flags & PIN_MAPPABLE) | |
62106b4f | 3508 | end = min_t(u64, end, dev_priv->ggtt.mappable_end); |
101b506a | 3509 | if (flags & PIN_ZONE_4G) |
48ea1e32 | 3510 | end = min_t(u64, end, (1ULL << 32) - PAGE_SIZE); |
101b506a | 3511 | |
673a394b | 3512 | if (alignment == 0) |
1ec9e26d | 3513 | alignment = flags & PIN_MAPPABLE ? fence_alignment : |
5e783301 | 3514 | unfenced_alignment; |
1ec9e26d | 3515 | if (flags & PIN_MAPPABLE && alignment & (fence_alignment - 1)) { |
91e6711e JL |
3516 | DRM_DEBUG("Invalid object (view type=%u) alignment requested %u\n", |
3517 | ggtt_view ? ggtt_view->type : 0, | |
3518 | alignment); | |
262de145 | 3519 | return ERR_PTR(-EINVAL); |
673a394b EA |
3520 | } |
3521 | ||
91e6711e JL |
3522 | /* If binding the object/GGTT view requires more space than the entire |
3523 | * aperture has, reject it early before evicting everything in a vain | |
3524 | * attempt to find space. | |
654fc607 | 3525 | */ |
91e6711e | 3526 | if (size > end) { |
65bd342f | 3527 | DRM_DEBUG("Attempting to bind an object (view type=%u) larger than the aperture: size=%llu > %s aperture=%llu\n", |
91e6711e JL |
3528 | ggtt_view ? ggtt_view->type : 0, |
3529 | size, | |
1ec9e26d | 3530 | flags & PIN_MAPPABLE ? "mappable" : "total", |
d23db88c | 3531 | end); |
262de145 | 3532 | return ERR_PTR(-E2BIG); |
654fc607 CW |
3533 | } |
3534 | ||
37e680a1 | 3535 | ret = i915_gem_object_get_pages(obj); |
6c085a72 | 3536 | if (ret) |
262de145 | 3537 | return ERR_PTR(ret); |
6c085a72 | 3538 | |
fbdda6fb CW |
3539 | i915_gem_object_pin_pages(obj); |
3540 | ||
ec7adb6e JL |
3541 | vma = ggtt_view ? i915_gem_obj_lookup_or_create_ggtt_vma(obj, ggtt_view) : |
3542 | i915_gem_obj_lookup_or_create_vma(obj, vm); | |
3543 | ||
262de145 | 3544 | if (IS_ERR(vma)) |
bc6bc15b | 3545 | goto err_unpin; |
2f633156 | 3546 | |
506a8e87 CW |
3547 | if (flags & PIN_OFFSET_FIXED) { |
3548 | uint64_t offset = flags & PIN_OFFSET_MASK; | |
3549 | ||
3550 | if (offset & (alignment - 1) || offset + size > end) { | |
3551 | ret = -EINVAL; | |
3552 | goto err_free_vma; | |
3553 | } | |
3554 | vma->node.start = offset; | |
3555 | vma->node.size = size; | |
3556 | vma->node.color = obj->cache_level; | |
3557 | ret = drm_mm_reserve_node(&vm->mm, &vma->node); | |
3558 | if (ret) { | |
3559 | ret = i915_gem_evict_for_vma(vma); | |
3560 | if (ret == 0) | |
3561 | ret = drm_mm_reserve_node(&vm->mm, &vma->node); | |
3562 | } | |
3563 | if (ret) | |
3564 | goto err_free_vma; | |
101b506a | 3565 | } else { |
506a8e87 CW |
3566 | if (flags & PIN_HIGH) { |
3567 | search_flag = DRM_MM_SEARCH_BELOW; | |
3568 | alloc_flag = DRM_MM_CREATE_TOP; | |
3569 | } else { | |
3570 | search_flag = DRM_MM_SEARCH_DEFAULT; | |
3571 | alloc_flag = DRM_MM_CREATE_DEFAULT; | |
3572 | } | |
101b506a | 3573 | |
0a9ae0d7 | 3574 | search_free: |
506a8e87 CW |
3575 | ret = drm_mm_insert_node_in_range_generic(&vm->mm, &vma->node, |
3576 | size, alignment, | |
3577 | obj->cache_level, | |
3578 | start, end, | |
3579 | search_flag, | |
3580 | alloc_flag); | |
3581 | if (ret) { | |
3582 | ret = i915_gem_evict_something(dev, vm, size, alignment, | |
3583 | obj->cache_level, | |
3584 | start, end, | |
3585 | flags); | |
3586 | if (ret == 0) | |
3587 | goto search_free; | |
9731129c | 3588 | |
506a8e87 CW |
3589 | goto err_free_vma; |
3590 | } | |
673a394b | 3591 | } |
4144f9b5 | 3592 | if (WARN_ON(!i915_gem_valid_gtt_space(vma, obj->cache_level))) { |
2f633156 | 3593 | ret = -EINVAL; |
bc6bc15b | 3594 | goto err_remove_node; |
673a394b EA |
3595 | } |
3596 | ||
fe14d5f4 | 3597 | trace_i915_vma_bind(vma, flags); |
0875546c | 3598 | ret = i915_vma_bind(vma, obj->cache_level, flags); |
fe14d5f4 | 3599 | if (ret) |
e2273302 | 3600 | goto err_remove_node; |
fe14d5f4 | 3601 | |
35c20a60 | 3602 | list_move_tail(&obj->global_list, &dev_priv->mm.bound_list); |
1c7f4bca | 3603 | list_add_tail(&vma->vm_link, &vm->inactive_list); |
bf1a1092 | 3604 | |
262de145 | 3605 | return vma; |
2f633156 | 3606 | |
bc6bc15b | 3607 | err_remove_node: |
6286ef9b | 3608 | drm_mm_remove_node(&vma->node); |
bc6bc15b | 3609 | err_free_vma: |
2f633156 | 3610 | i915_gem_vma_destroy(vma); |
262de145 | 3611 | vma = ERR_PTR(ret); |
bc6bc15b | 3612 | err_unpin: |
2f633156 | 3613 | i915_gem_object_unpin_pages(obj); |
262de145 | 3614 | return vma; |
673a394b EA |
3615 | } |
3616 | ||
000433b6 | 3617 | bool |
2c22569b CW |
3618 | i915_gem_clflush_object(struct drm_i915_gem_object *obj, |
3619 | bool force) | |
673a394b | 3620 | { |
673a394b EA |
3621 | /* If we don't have a page list set up, then we're not pinned |
3622 | * to GPU, and we can ignore the cache flush because it'll happen | |
3623 | * again at bind time. | |
3624 | */ | |
05394f39 | 3625 | if (obj->pages == NULL) |
000433b6 | 3626 | return false; |
673a394b | 3627 | |
769ce464 ID |
3628 | /* |
3629 | * Stolen memory is always coherent with the GPU as it is explicitly | |
3630 | * marked as wc by the system, or the system is cache-coherent. | |
3631 | */ | |
6a2c4232 | 3632 | if (obj->stolen || obj->phys_handle) |
000433b6 | 3633 | return false; |
769ce464 | 3634 | |
9c23f7fc CW |
3635 | /* If the GPU is snooping the contents of the CPU cache, |
3636 | * we do not need to manually clear the CPU cache lines. However, | |
3637 | * the caches are only snooped when the render cache is | |
3638 | * flushed/invalidated. As we always have to emit invalidations | |
3639 | * and flushes when moving into and out of the RENDER domain, correct | |
3640 | * snooping behaviour occurs naturally as the result of our domain | |
3641 | * tracking. | |
3642 | */ | |
0f71979a CW |
3643 | if (!force && cpu_cache_is_coherent(obj->base.dev, obj->cache_level)) { |
3644 | obj->cache_dirty = true; | |
000433b6 | 3645 | return false; |
0f71979a | 3646 | } |
9c23f7fc | 3647 | |
1c5d22f7 | 3648 | trace_i915_gem_object_clflush(obj); |
9da3da66 | 3649 | drm_clflush_sg(obj->pages); |
0f71979a | 3650 | obj->cache_dirty = false; |
000433b6 CW |
3651 | |
3652 | return true; | |
e47c68e9 EA |
3653 | } |
3654 | ||
3655 | /** Flushes the GTT write domain for the object if it's dirty. */ | |
3656 | static void | |
05394f39 | 3657 | i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj) |
e47c68e9 | 3658 | { |
1c5d22f7 CW |
3659 | uint32_t old_write_domain; |
3660 | ||
05394f39 | 3661 | if (obj->base.write_domain != I915_GEM_DOMAIN_GTT) |
e47c68e9 EA |
3662 | return; |
3663 | ||
63256ec5 | 3664 | /* No actual flushing is required for the GTT write domain. Writes |
e47c68e9 EA |
3665 | * to it immediately go to main memory as far as we know, so there's |
3666 | * no chipset flush. It also doesn't land in render cache. | |
63256ec5 CW |
3667 | * |
3668 | * However, we do have to enforce the order so that all writes through | |
3669 | * the GTT land before any writes to the device, such as updates to | |
3670 | * the GATT itself. | |
e47c68e9 | 3671 | */ |
63256ec5 CW |
3672 | wmb(); |
3673 | ||
05394f39 CW |
3674 | old_write_domain = obj->base.write_domain; |
3675 | obj->base.write_domain = 0; | |
1c5d22f7 | 3676 | |
de152b62 | 3677 | intel_fb_obj_flush(obj, false, ORIGIN_GTT); |
f99d7069 | 3678 | |
1c5d22f7 | 3679 | trace_i915_gem_object_change_domain(obj, |
05394f39 | 3680 | obj->base.read_domains, |
1c5d22f7 | 3681 | old_write_domain); |
e47c68e9 EA |
3682 | } |
3683 | ||
3684 | /** Flushes the CPU write domain for the object if it's dirty. */ | |
3685 | static void | |
e62b59e4 | 3686 | i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj) |
e47c68e9 | 3687 | { |
1c5d22f7 | 3688 | uint32_t old_write_domain; |
e47c68e9 | 3689 | |
05394f39 | 3690 | if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) |
e47c68e9 EA |
3691 | return; |
3692 | ||
e62b59e4 | 3693 | if (i915_gem_clflush_object(obj, obj->pin_display)) |
000433b6 CW |
3694 | i915_gem_chipset_flush(obj->base.dev); |
3695 | ||
05394f39 CW |
3696 | old_write_domain = obj->base.write_domain; |
3697 | obj->base.write_domain = 0; | |
1c5d22f7 | 3698 | |
de152b62 | 3699 | intel_fb_obj_flush(obj, false, ORIGIN_CPU); |
f99d7069 | 3700 | |
1c5d22f7 | 3701 | trace_i915_gem_object_change_domain(obj, |
05394f39 | 3702 | obj->base.read_domains, |
1c5d22f7 | 3703 | old_write_domain); |
e47c68e9 EA |
3704 | } |
3705 | ||
2ef7eeaa EA |
3706 | /** |
3707 | * Moves a single object to the GTT read, and possibly write domain. | |
3708 | * | |
3709 | * This function returns when the move is complete, including waiting on | |
3710 | * flushes to occur. | |
3711 | */ | |
79e53945 | 3712 | int |
2021746e | 3713 | i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write) |
2ef7eeaa | 3714 | { |
1c5d22f7 | 3715 | uint32_t old_write_domain, old_read_domains; |
43566ded | 3716 | struct i915_vma *vma; |
e47c68e9 | 3717 | int ret; |
2ef7eeaa | 3718 | |
8d7e3de1 CW |
3719 | if (obj->base.write_domain == I915_GEM_DOMAIN_GTT) |
3720 | return 0; | |
3721 | ||
0201f1ec | 3722 | ret = i915_gem_object_wait_rendering(obj, !write); |
88241785 CW |
3723 | if (ret) |
3724 | return ret; | |
3725 | ||
43566ded CW |
3726 | /* Flush and acquire obj->pages so that we are coherent through |
3727 | * direct access in memory with previous cached writes through | |
3728 | * shmemfs and that our cache domain tracking remains valid. | |
3729 | * For example, if the obj->filp was moved to swap without us | |
3730 | * being notified and releasing the pages, we would mistakenly | |
3731 | * continue to assume that the obj remained out of the CPU cached | |
3732 | * domain. | |
3733 | */ | |
3734 | ret = i915_gem_object_get_pages(obj); | |
3735 | if (ret) | |
3736 | return ret; | |
3737 | ||
e62b59e4 | 3738 | i915_gem_object_flush_cpu_write_domain(obj); |
1c5d22f7 | 3739 | |
d0a57789 CW |
3740 | /* Serialise direct access to this object with the barriers for |
3741 | * coherent writes from the GPU, by effectively invalidating the | |
3742 | * GTT domain upon first access. | |
3743 | */ | |
3744 | if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0) | |
3745 | mb(); | |
3746 | ||
05394f39 CW |
3747 | old_write_domain = obj->base.write_domain; |
3748 | old_read_domains = obj->base.read_domains; | |
1c5d22f7 | 3749 | |
e47c68e9 EA |
3750 | /* It should now be out of any other write domains, and we can update |
3751 | * the domain values for our changes. | |
3752 | */ | |
05394f39 CW |
3753 | BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_GTT) != 0); |
3754 | obj->base.read_domains |= I915_GEM_DOMAIN_GTT; | |
e47c68e9 | 3755 | if (write) { |
05394f39 CW |
3756 | obj->base.read_domains = I915_GEM_DOMAIN_GTT; |
3757 | obj->base.write_domain = I915_GEM_DOMAIN_GTT; | |
3758 | obj->dirty = 1; | |
2ef7eeaa EA |
3759 | } |
3760 | ||
1c5d22f7 CW |
3761 | trace_i915_gem_object_change_domain(obj, |
3762 | old_read_domains, | |
3763 | old_write_domain); | |
3764 | ||
8325a09d | 3765 | /* And bump the LRU for this access */ |
43566ded CW |
3766 | vma = i915_gem_obj_to_ggtt(obj); |
3767 | if (vma && drm_mm_node_allocated(&vma->node) && !obj->active) | |
1c7f4bca | 3768 | list_move_tail(&vma->vm_link, |
62106b4f | 3769 | &to_i915(obj->base.dev)->ggtt.base.inactive_list); |
8325a09d | 3770 | |
e47c68e9 EA |
3771 | return 0; |
3772 | } | |
3773 | ||
ef55f92a CW |
3774 | /** |
3775 | * Changes the cache-level of an object across all VMA. | |
3776 | * | |
3777 | * After this function returns, the object will be in the new cache-level | |
3778 | * across all GTT and the contents of the backing storage will be coherent, | |
3779 | * with respect to the new cache-level. In order to keep the backing storage | |
3780 | * coherent for all users, we only allow a single cache level to be set | |
3781 | * globally on the object and prevent it from being changed whilst the | |
3782 | * hardware is reading from the object. That is if the object is currently | |
3783 | * on the scanout it will be set to uncached (or equivalent display | |
3784 | * cache coherency) and all non-MOCS GPU access will also be uncached so | |
3785 | * that all direct access to the scanout remains coherent. | |
3786 | */ | |
e4ffd173 CW |
3787 | int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj, |
3788 | enum i915_cache_level cache_level) | |
3789 | { | |
7bddb01f | 3790 | struct drm_device *dev = obj->base.dev; |
df6f783a | 3791 | struct i915_vma *vma, *next; |
ef55f92a | 3792 | bool bound = false; |
ed75a55b | 3793 | int ret = 0; |
e4ffd173 CW |
3794 | |
3795 | if (obj->cache_level == cache_level) | |
ed75a55b | 3796 | goto out; |
e4ffd173 | 3797 | |
ef55f92a CW |
3798 | /* Inspect the list of currently bound VMA and unbind any that would |
3799 | * be invalid given the new cache-level. This is principally to | |
3800 | * catch the issue of the CS prefetch crossing page boundaries and | |
3801 | * reading an invalid PTE on older architectures. | |
3802 | */ | |
1c7f4bca | 3803 | list_for_each_entry_safe(vma, next, &obj->vma_list, obj_link) { |
ef55f92a CW |
3804 | if (!drm_mm_node_allocated(&vma->node)) |
3805 | continue; | |
3806 | ||
3807 | if (vma->pin_count) { | |
3808 | DRM_DEBUG("can not change the cache level of pinned objects\n"); | |
3809 | return -EBUSY; | |
3810 | } | |
3811 | ||
4144f9b5 | 3812 | if (!i915_gem_valid_gtt_space(vma, cache_level)) { |
07fe0b12 | 3813 | ret = i915_vma_unbind(vma); |
3089c6f2 BW |
3814 | if (ret) |
3815 | return ret; | |
ef55f92a CW |
3816 | } else |
3817 | bound = true; | |
42d6ab48 CW |
3818 | } |
3819 | ||
ef55f92a CW |
3820 | /* We can reuse the existing drm_mm nodes but need to change the |
3821 | * cache-level on the PTE. We could simply unbind them all and | |
3822 | * rebind with the correct cache-level on next use. However since | |
3823 | * we already have a valid slot, dma mapping, pages etc, we may as | |
3824 | * rewrite the PTE in the belief that doing so tramples upon less | |
3825 | * state and so involves less work. | |
3826 | */ | |
3827 | if (bound) { | |
3828 | /* Before we change the PTE, the GPU must not be accessing it. | |
3829 | * If we wait upon the object, we know that all the bound | |
3830 | * VMA are no longer active. | |
3831 | */ | |
2e2f351d | 3832 | ret = i915_gem_object_wait_rendering(obj, false); |
e4ffd173 CW |
3833 | if (ret) |
3834 | return ret; | |
3835 | ||
ef55f92a CW |
3836 | if (!HAS_LLC(dev) && cache_level != I915_CACHE_NONE) { |
3837 | /* Access to snoopable pages through the GTT is | |
3838 | * incoherent and on some machines causes a hard | |
3839 | * lockup. Relinquish the CPU mmaping to force | |
3840 | * userspace to refault in the pages and we can | |
3841 | * then double check if the GTT mapping is still | |
3842 | * valid for that pointer access. | |
3843 | */ | |
3844 | i915_gem_release_mmap(obj); | |
3845 | ||
3846 | /* As we no longer need a fence for GTT access, | |
3847 | * we can relinquish it now (and so prevent having | |
3848 | * to steal a fence from someone else on the next | |
3849 | * fence request). Note GPU activity would have | |
3850 | * dropped the fence as all snoopable access is | |
3851 | * supposed to be linear. | |
3852 | */ | |
e4ffd173 CW |
3853 | ret = i915_gem_object_put_fence(obj); |
3854 | if (ret) | |
3855 | return ret; | |
ef55f92a CW |
3856 | } else { |
3857 | /* We either have incoherent backing store and | |
3858 | * so no GTT access or the architecture is fully | |
3859 | * coherent. In such cases, existing GTT mmaps | |
3860 | * ignore the cache bit in the PTE and we can | |
3861 | * rewrite it without confusing the GPU or having | |
3862 | * to force userspace to fault back in its mmaps. | |
3863 | */ | |
e4ffd173 CW |
3864 | } |
3865 | ||
1c7f4bca | 3866 | list_for_each_entry(vma, &obj->vma_list, obj_link) { |
ef55f92a CW |
3867 | if (!drm_mm_node_allocated(&vma->node)) |
3868 | continue; | |
3869 | ||
3870 | ret = i915_vma_bind(vma, cache_level, PIN_UPDATE); | |
3871 | if (ret) | |
3872 | return ret; | |
3873 | } | |
e4ffd173 CW |
3874 | } |
3875 | ||
1c7f4bca | 3876 | list_for_each_entry(vma, &obj->vma_list, obj_link) |
2c22569b CW |
3877 | vma->node.color = cache_level; |
3878 | obj->cache_level = cache_level; | |
3879 | ||
ed75a55b | 3880 | out: |
ef55f92a CW |
3881 | /* Flush the dirty CPU caches to the backing storage so that the |
3882 | * object is now coherent at its new cache level (with respect | |
3883 | * to the access domain). | |
3884 | */ | |
0f71979a CW |
3885 | if (obj->cache_dirty && |
3886 | obj->base.write_domain != I915_GEM_DOMAIN_CPU && | |
3887 | cpu_write_needs_clflush(obj)) { | |
3888 | if (i915_gem_clflush_object(obj, true)) | |
3889 | i915_gem_chipset_flush(obj->base.dev); | |
e4ffd173 CW |
3890 | } |
3891 | ||
e4ffd173 CW |
3892 | return 0; |
3893 | } | |
3894 | ||
199adf40 BW |
3895 | int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data, |
3896 | struct drm_file *file) | |
e6994aee | 3897 | { |
199adf40 | 3898 | struct drm_i915_gem_caching *args = data; |
e6994aee | 3899 | struct drm_i915_gem_object *obj; |
e6994aee CW |
3900 | |
3901 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); | |
432be69d CW |
3902 | if (&obj->base == NULL) |
3903 | return -ENOENT; | |
e6994aee | 3904 | |
651d794f CW |
3905 | switch (obj->cache_level) { |
3906 | case I915_CACHE_LLC: | |
3907 | case I915_CACHE_L3_LLC: | |
3908 | args->caching = I915_CACHING_CACHED; | |
3909 | break; | |
3910 | ||
4257d3ba CW |
3911 | case I915_CACHE_WT: |
3912 | args->caching = I915_CACHING_DISPLAY; | |
3913 | break; | |
3914 | ||
651d794f CW |
3915 | default: |
3916 | args->caching = I915_CACHING_NONE; | |
3917 | break; | |
3918 | } | |
e6994aee | 3919 | |
432be69d CW |
3920 | drm_gem_object_unreference_unlocked(&obj->base); |
3921 | return 0; | |
e6994aee CW |
3922 | } |
3923 | ||
199adf40 BW |
3924 | int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data, |
3925 | struct drm_file *file) | |
e6994aee | 3926 | { |
fd0fe6ac | 3927 | struct drm_i915_private *dev_priv = dev->dev_private; |
199adf40 | 3928 | struct drm_i915_gem_caching *args = data; |
e6994aee CW |
3929 | struct drm_i915_gem_object *obj; |
3930 | enum i915_cache_level level; | |
3931 | int ret; | |
3932 | ||
199adf40 BW |
3933 | switch (args->caching) { |
3934 | case I915_CACHING_NONE: | |
e6994aee CW |
3935 | level = I915_CACHE_NONE; |
3936 | break; | |
199adf40 | 3937 | case I915_CACHING_CACHED: |
e5756c10 ID |
3938 | /* |
3939 | * Due to a HW issue on BXT A stepping, GPU stores via a | |
3940 | * snooped mapping may leave stale data in a corresponding CPU | |
3941 | * cacheline, whereas normally such cachelines would get | |
3942 | * invalidated. | |
3943 | */ | |
ca377809 | 3944 | if (!HAS_LLC(dev) && !HAS_SNOOP(dev)) |
e5756c10 ID |
3945 | return -ENODEV; |
3946 | ||
e6994aee CW |
3947 | level = I915_CACHE_LLC; |
3948 | break; | |
4257d3ba CW |
3949 | case I915_CACHING_DISPLAY: |
3950 | level = HAS_WT(dev) ? I915_CACHE_WT : I915_CACHE_NONE; | |
3951 | break; | |
e6994aee CW |
3952 | default: |
3953 | return -EINVAL; | |
3954 | } | |
3955 | ||
fd0fe6ac ID |
3956 | intel_runtime_pm_get(dev_priv); |
3957 | ||
3bc2913e BW |
3958 | ret = i915_mutex_lock_interruptible(dev); |
3959 | if (ret) | |
fd0fe6ac | 3960 | goto rpm_put; |
3bc2913e | 3961 | |
e6994aee CW |
3962 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
3963 | if (&obj->base == NULL) { | |
3964 | ret = -ENOENT; | |
3965 | goto unlock; | |
3966 | } | |
3967 | ||
3968 | ret = i915_gem_object_set_cache_level(obj, level); | |
3969 | ||
3970 | drm_gem_object_unreference(&obj->base); | |
3971 | unlock: | |
3972 | mutex_unlock(&dev->struct_mutex); | |
fd0fe6ac ID |
3973 | rpm_put: |
3974 | intel_runtime_pm_put(dev_priv); | |
3975 | ||
e6994aee CW |
3976 | return ret; |
3977 | } | |
3978 | ||
b9241ea3 | 3979 | /* |
2da3b9b9 CW |
3980 | * Prepare buffer for display plane (scanout, cursors, etc). |
3981 | * Can be called from an uninterruptible phase (modesetting) and allows | |
3982 | * any flushes to be pipelined (for pageflips). | |
b9241ea3 ZW |
3983 | */ |
3984 | int | |
2da3b9b9 CW |
3985 | i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj, |
3986 | u32 alignment, | |
e6617330 | 3987 | const struct i915_ggtt_view *view) |
b9241ea3 | 3988 | { |
2da3b9b9 | 3989 | u32 old_read_domains, old_write_domain; |
b9241ea3 ZW |
3990 | int ret; |
3991 | ||
cc98b413 CW |
3992 | /* Mark the pin_display early so that we account for the |
3993 | * display coherency whilst setting up the cache domains. | |
3994 | */ | |
8a0c39b1 | 3995 | obj->pin_display++; |
cc98b413 | 3996 | |
a7ef0640 EA |
3997 | /* The display engine is not coherent with the LLC cache on gen6. As |
3998 | * a result, we make sure that the pinning that is about to occur is | |
3999 | * done with uncached PTEs. This is lowest common denominator for all | |
4000 | * chipsets. | |
4001 | * | |
4002 | * However for gen6+, we could do better by using the GFDT bit instead | |
4003 | * of uncaching, which would allow us to flush all the LLC-cached data | |
4004 | * with that bit in the PTE to main memory with just one PIPE_CONTROL. | |
4005 | */ | |
651d794f CW |
4006 | ret = i915_gem_object_set_cache_level(obj, |
4007 | HAS_WT(obj->base.dev) ? I915_CACHE_WT : I915_CACHE_NONE); | |
a7ef0640 | 4008 | if (ret) |
cc98b413 | 4009 | goto err_unpin_display; |
a7ef0640 | 4010 | |
2da3b9b9 CW |
4011 | /* As the user may map the buffer once pinned in the display plane |
4012 | * (e.g. libkms for the bootup splash), we have to ensure that we | |
4013 | * always use map_and_fenceable for all scanout buffers. | |
4014 | */ | |
50470bb0 TU |
4015 | ret = i915_gem_object_ggtt_pin(obj, view, alignment, |
4016 | view->type == I915_GGTT_VIEW_NORMAL ? | |
4017 | PIN_MAPPABLE : 0); | |
2da3b9b9 | 4018 | if (ret) |
cc98b413 | 4019 | goto err_unpin_display; |
2da3b9b9 | 4020 | |
e62b59e4 | 4021 | i915_gem_object_flush_cpu_write_domain(obj); |
b118c1e3 | 4022 | |
2da3b9b9 | 4023 | old_write_domain = obj->base.write_domain; |
05394f39 | 4024 | old_read_domains = obj->base.read_domains; |
2da3b9b9 CW |
4025 | |
4026 | /* It should now be out of any other write domains, and we can update | |
4027 | * the domain values for our changes. | |
4028 | */ | |
e5f1d962 | 4029 | obj->base.write_domain = 0; |
05394f39 | 4030 | obj->base.read_domains |= I915_GEM_DOMAIN_GTT; |
b9241ea3 ZW |
4031 | |
4032 | trace_i915_gem_object_change_domain(obj, | |
4033 | old_read_domains, | |
2da3b9b9 | 4034 | old_write_domain); |
b9241ea3 ZW |
4035 | |
4036 | return 0; | |
cc98b413 CW |
4037 | |
4038 | err_unpin_display: | |
8a0c39b1 | 4039 | obj->pin_display--; |
cc98b413 CW |
4040 | return ret; |
4041 | } | |
4042 | ||
4043 | void | |
e6617330 TU |
4044 | i915_gem_object_unpin_from_display_plane(struct drm_i915_gem_object *obj, |
4045 | const struct i915_ggtt_view *view) | |
cc98b413 | 4046 | { |
8a0c39b1 TU |
4047 | if (WARN_ON(obj->pin_display == 0)) |
4048 | return; | |
4049 | ||
e6617330 TU |
4050 | i915_gem_object_ggtt_unpin_view(obj, view); |
4051 | ||
8a0c39b1 | 4052 | obj->pin_display--; |
b9241ea3 ZW |
4053 | } |
4054 | ||
e47c68e9 EA |
4055 | /** |
4056 | * Moves a single object to the CPU read, and possibly write domain. | |
4057 | * | |
4058 | * This function returns when the move is complete, including waiting on | |
4059 | * flushes to occur. | |
4060 | */ | |
dabdfe02 | 4061 | int |
919926ae | 4062 | i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write) |
e47c68e9 | 4063 | { |
1c5d22f7 | 4064 | uint32_t old_write_domain, old_read_domains; |
e47c68e9 EA |
4065 | int ret; |
4066 | ||
8d7e3de1 CW |
4067 | if (obj->base.write_domain == I915_GEM_DOMAIN_CPU) |
4068 | return 0; | |
4069 | ||
0201f1ec | 4070 | ret = i915_gem_object_wait_rendering(obj, !write); |
88241785 CW |
4071 | if (ret) |
4072 | return ret; | |
4073 | ||
e47c68e9 | 4074 | i915_gem_object_flush_gtt_write_domain(obj); |
2ef7eeaa | 4075 | |
05394f39 CW |
4076 | old_write_domain = obj->base.write_domain; |
4077 | old_read_domains = obj->base.read_domains; | |
1c5d22f7 | 4078 | |
e47c68e9 | 4079 | /* Flush the CPU cache if it's still invalid. */ |
05394f39 | 4080 | if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0) { |
2c22569b | 4081 | i915_gem_clflush_object(obj, false); |
2ef7eeaa | 4082 | |
05394f39 | 4083 | obj->base.read_domains |= I915_GEM_DOMAIN_CPU; |
2ef7eeaa EA |
4084 | } |
4085 | ||
4086 | /* It should now be out of any other write domains, and we can update | |
4087 | * the domain values for our changes. | |
4088 | */ | |
05394f39 | 4089 | BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_CPU) != 0); |
e47c68e9 EA |
4090 | |
4091 | /* If we're writing through the CPU, then the GPU read domains will | |
4092 | * need to be invalidated at next use. | |
4093 | */ | |
4094 | if (write) { | |
05394f39 CW |
4095 | obj->base.read_domains = I915_GEM_DOMAIN_CPU; |
4096 | obj->base.write_domain = I915_GEM_DOMAIN_CPU; | |
e47c68e9 | 4097 | } |
2ef7eeaa | 4098 | |
1c5d22f7 CW |
4099 | trace_i915_gem_object_change_domain(obj, |
4100 | old_read_domains, | |
4101 | old_write_domain); | |
4102 | ||
2ef7eeaa EA |
4103 | return 0; |
4104 | } | |
4105 | ||
673a394b EA |
4106 | /* Throttle our rendering by waiting until the ring has completed our requests |
4107 | * emitted over 20 msec ago. | |
4108 | * | |
b962442e EA |
4109 | * Note that if we were to use the current jiffies each time around the loop, |
4110 | * we wouldn't escape the function with any frames outstanding if the time to | |
4111 | * render a frame was over 20ms. | |
4112 | * | |
673a394b EA |
4113 | * This should get us reasonable parallelism between CPU and GPU but also |
4114 | * relatively low latency when blocking on a particular request to finish. | |
4115 | */ | |
40a5f0de | 4116 | static int |
f787a5f5 | 4117 | i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file) |
40a5f0de | 4118 | { |
f787a5f5 CW |
4119 | struct drm_i915_private *dev_priv = dev->dev_private; |
4120 | struct drm_i915_file_private *file_priv = file->driver_priv; | |
d0bc54f2 | 4121 | unsigned long recent_enough = jiffies - DRM_I915_THROTTLE_JIFFIES; |
54fb2411 | 4122 | struct drm_i915_gem_request *request, *target = NULL; |
f69061be | 4123 | unsigned reset_counter; |
f787a5f5 | 4124 | int ret; |
93533c29 | 4125 | |
308887aa DV |
4126 | ret = i915_gem_wait_for_error(&dev_priv->gpu_error); |
4127 | if (ret) | |
4128 | return ret; | |
4129 | ||
4130 | ret = i915_gem_check_wedge(&dev_priv->gpu_error, false); | |
4131 | if (ret) | |
4132 | return ret; | |
e110e8d6 | 4133 | |
1c25595f | 4134 | spin_lock(&file_priv->mm.lock); |
f787a5f5 | 4135 | list_for_each_entry(request, &file_priv->mm.request_list, client_list) { |
b962442e EA |
4136 | if (time_after_eq(request->emitted_jiffies, recent_enough)) |
4137 | break; | |
40a5f0de | 4138 | |
fcfa423c JH |
4139 | /* |
4140 | * Note that the request might not have been submitted yet. | |
4141 | * In which case emitted_jiffies will be zero. | |
4142 | */ | |
4143 | if (!request->emitted_jiffies) | |
4144 | continue; | |
4145 | ||
54fb2411 | 4146 | target = request; |
b962442e | 4147 | } |
f69061be | 4148 | reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter); |
ff865885 JH |
4149 | if (target) |
4150 | i915_gem_request_reference(target); | |
1c25595f | 4151 | spin_unlock(&file_priv->mm.lock); |
40a5f0de | 4152 | |
54fb2411 | 4153 | if (target == NULL) |
f787a5f5 | 4154 | return 0; |
2bc43b5c | 4155 | |
9c654818 | 4156 | ret = __i915_wait_request(target, reset_counter, true, NULL, NULL); |
f787a5f5 CW |
4157 | if (ret == 0) |
4158 | queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, 0); | |
40a5f0de | 4159 | |
41037f9f | 4160 | i915_gem_request_unreference__unlocked(target); |
ff865885 | 4161 | |
40a5f0de EA |
4162 | return ret; |
4163 | } | |
4164 | ||
d23db88c CW |
4165 | static bool |
4166 | i915_vma_misplaced(struct i915_vma *vma, uint32_t alignment, uint64_t flags) | |
4167 | { | |
4168 | struct drm_i915_gem_object *obj = vma->obj; | |
4169 | ||
4170 | if (alignment && | |
4171 | vma->node.start & (alignment - 1)) | |
4172 | return true; | |
4173 | ||
4174 | if (flags & PIN_MAPPABLE && !obj->map_and_fenceable) | |
4175 | return true; | |
4176 | ||
4177 | if (flags & PIN_OFFSET_BIAS && | |
4178 | vma->node.start < (flags & PIN_OFFSET_MASK)) | |
4179 | return true; | |
4180 | ||
506a8e87 CW |
4181 | if (flags & PIN_OFFSET_FIXED && |
4182 | vma->node.start != (flags & PIN_OFFSET_MASK)) | |
4183 | return true; | |
4184 | ||
d23db88c CW |
4185 | return false; |
4186 | } | |
4187 | ||
d0710abb CW |
4188 | void __i915_vma_set_map_and_fenceable(struct i915_vma *vma) |
4189 | { | |
4190 | struct drm_i915_gem_object *obj = vma->obj; | |
4191 | bool mappable, fenceable; | |
4192 | u32 fence_size, fence_alignment; | |
4193 | ||
4194 | fence_size = i915_gem_get_gtt_size(obj->base.dev, | |
4195 | obj->base.size, | |
4196 | obj->tiling_mode); | |
4197 | fence_alignment = i915_gem_get_gtt_alignment(obj->base.dev, | |
4198 | obj->base.size, | |
4199 | obj->tiling_mode, | |
4200 | true); | |
4201 | ||
4202 | fenceable = (vma->node.size == fence_size && | |
4203 | (vma->node.start & (fence_alignment - 1)) == 0); | |
4204 | ||
4205 | mappable = (vma->node.start + fence_size <= | |
62106b4f | 4206 | to_i915(obj->base.dev)->ggtt.mappable_end); |
d0710abb CW |
4207 | |
4208 | obj->map_and_fenceable = mappable && fenceable; | |
4209 | } | |
4210 | ||
ec7adb6e JL |
4211 | static int |
4212 | i915_gem_object_do_pin(struct drm_i915_gem_object *obj, | |
4213 | struct i915_address_space *vm, | |
4214 | const struct i915_ggtt_view *ggtt_view, | |
4215 | uint32_t alignment, | |
4216 | uint64_t flags) | |
673a394b | 4217 | { |
6e7186af | 4218 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
07fe0b12 | 4219 | struct i915_vma *vma; |
ef79e17c | 4220 | unsigned bound; |
673a394b EA |
4221 | int ret; |
4222 | ||
6e7186af BW |
4223 | if (WARN_ON(vm == &dev_priv->mm.aliasing_ppgtt->base)) |
4224 | return -ENODEV; | |
4225 | ||
bf3d149b | 4226 | if (WARN_ON(flags & (PIN_GLOBAL | PIN_MAPPABLE) && !i915_is_ggtt(vm))) |
1ec9e26d | 4227 | return -EINVAL; |
07fe0b12 | 4228 | |
c826c449 CW |
4229 | if (WARN_ON((flags & (PIN_MAPPABLE | PIN_GLOBAL)) == PIN_MAPPABLE)) |
4230 | return -EINVAL; | |
4231 | ||
ec7adb6e JL |
4232 | if (WARN_ON(i915_is_ggtt(vm) != !!ggtt_view)) |
4233 | return -EINVAL; | |
4234 | ||
4235 | vma = ggtt_view ? i915_gem_obj_to_ggtt_view(obj, ggtt_view) : | |
4236 | i915_gem_obj_to_vma(obj, vm); | |
4237 | ||
07fe0b12 | 4238 | if (vma) { |
d7f46fc4 BW |
4239 | if (WARN_ON(vma->pin_count == DRM_I915_GEM_OBJECT_MAX_PIN_COUNT)) |
4240 | return -EBUSY; | |
4241 | ||
d23db88c | 4242 | if (i915_vma_misplaced(vma, alignment, flags)) { |
d7f46fc4 | 4243 | WARN(vma->pin_count, |
ec7adb6e | 4244 | "bo is already pinned in %s with incorrect alignment:" |
088e0df4 | 4245 | " offset=%08x %08x, req.alignment=%x, req.map_and_fenceable=%d," |
75e9e915 | 4246 | " obj->map_and_fenceable=%d\n", |
ec7adb6e | 4247 | ggtt_view ? "ggtt" : "ppgtt", |
088e0df4 MT |
4248 | upper_32_bits(vma->node.start), |
4249 | lower_32_bits(vma->node.start), | |
fe14d5f4 | 4250 | alignment, |
d23db88c | 4251 | !!(flags & PIN_MAPPABLE), |
05394f39 | 4252 | obj->map_and_fenceable); |
07fe0b12 | 4253 | ret = i915_vma_unbind(vma); |
ac0c6b5a CW |
4254 | if (ret) |
4255 | return ret; | |
8ea99c92 DV |
4256 | |
4257 | vma = NULL; | |
ac0c6b5a CW |
4258 | } |
4259 | } | |
4260 | ||
ef79e17c | 4261 | bound = vma ? vma->bound : 0; |
8ea99c92 | 4262 | if (vma == NULL || !drm_mm_node_allocated(&vma->node)) { |
ec7adb6e JL |
4263 | vma = i915_gem_object_bind_to_vm(obj, vm, ggtt_view, alignment, |
4264 | flags); | |
262de145 DV |
4265 | if (IS_ERR(vma)) |
4266 | return PTR_ERR(vma); | |
0875546c DV |
4267 | } else { |
4268 | ret = i915_vma_bind(vma, obj->cache_level, flags); | |
fe14d5f4 TU |
4269 | if (ret) |
4270 | return ret; | |
4271 | } | |
74898d7e | 4272 | |
91e6711e JL |
4273 | if (ggtt_view && ggtt_view->type == I915_GGTT_VIEW_NORMAL && |
4274 | (bound ^ vma->bound) & GLOBAL_BIND) { | |
d0710abb | 4275 | __i915_vma_set_map_and_fenceable(vma); |
91e6711e JL |
4276 | WARN_ON(flags & PIN_MAPPABLE && !obj->map_and_fenceable); |
4277 | } | |
ef79e17c | 4278 | |
8ea99c92 | 4279 | vma->pin_count++; |
673a394b EA |
4280 | return 0; |
4281 | } | |
4282 | ||
ec7adb6e JL |
4283 | int |
4284 | i915_gem_object_pin(struct drm_i915_gem_object *obj, | |
4285 | struct i915_address_space *vm, | |
4286 | uint32_t alignment, | |
4287 | uint64_t flags) | |
4288 | { | |
4289 | return i915_gem_object_do_pin(obj, vm, | |
4290 | i915_is_ggtt(vm) ? &i915_ggtt_view_normal : NULL, | |
4291 | alignment, flags); | |
4292 | } | |
4293 | ||
4294 | int | |
4295 | i915_gem_object_ggtt_pin(struct drm_i915_gem_object *obj, | |
4296 | const struct i915_ggtt_view *view, | |
4297 | uint32_t alignment, | |
4298 | uint64_t flags) | |
4299 | { | |
ade7daa1 | 4300 | BUG_ON(!view); |
ec7adb6e JL |
4301 | |
4302 | return i915_gem_object_do_pin(obj, i915_obj_to_ggtt(obj), view, | |
6fafab76 | 4303 | alignment, flags | PIN_GLOBAL); |
ec7adb6e JL |
4304 | } |
4305 | ||
673a394b | 4306 | void |
e6617330 TU |
4307 | i915_gem_object_ggtt_unpin_view(struct drm_i915_gem_object *obj, |
4308 | const struct i915_ggtt_view *view) | |
673a394b | 4309 | { |
e6617330 | 4310 | struct i915_vma *vma = i915_gem_obj_to_ggtt_view(obj, view); |
673a394b | 4311 | |
d7f46fc4 | 4312 | BUG_ON(!vma); |
e6617330 | 4313 | WARN_ON(vma->pin_count == 0); |
9abc4648 | 4314 | WARN_ON(!i915_gem_obj_ggtt_bound_view(obj, view)); |
d7f46fc4 | 4315 | |
30154650 | 4316 | --vma->pin_count; |
673a394b EA |
4317 | } |
4318 | ||
673a394b EA |
4319 | int |
4320 | i915_gem_busy_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 4321 | struct drm_file *file) |
673a394b EA |
4322 | { |
4323 | struct drm_i915_gem_busy *args = data; | |
05394f39 | 4324 | struct drm_i915_gem_object *obj; |
30dbf0c0 CW |
4325 | int ret; |
4326 | ||
76c1dec1 | 4327 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 4328 | if (ret) |
76c1dec1 | 4329 | return ret; |
673a394b | 4330 | |
05394f39 | 4331 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 4332 | if (&obj->base == NULL) { |
1d7cfea1 CW |
4333 | ret = -ENOENT; |
4334 | goto unlock; | |
673a394b | 4335 | } |
d1b851fc | 4336 | |
0be555b6 CW |
4337 | /* Count all active objects as busy, even if they are currently not used |
4338 | * by the gpu. Users of this interface expect objects to eventually | |
4339 | * become non-busy without any further actions, therefore emit any | |
4340 | * necessary flushes here. | |
c4de0a5d | 4341 | */ |
30dfebf3 | 4342 | ret = i915_gem_object_flush_active(obj); |
b4716185 CW |
4343 | if (ret) |
4344 | goto unref; | |
0be555b6 | 4345 | |
426960be CW |
4346 | args->busy = 0; |
4347 | if (obj->active) { | |
4348 | int i; | |
4349 | ||
666796da | 4350 | for (i = 0; i < I915_NUM_ENGINES; i++) { |
426960be CW |
4351 | struct drm_i915_gem_request *req; |
4352 | ||
4353 | req = obj->last_read_req[i]; | |
4354 | if (req) | |
4a570db5 | 4355 | args->busy |= 1 << (16 + req->engine->exec_id); |
426960be CW |
4356 | } |
4357 | if (obj->last_write_req) | |
4a570db5 | 4358 | args->busy |= obj->last_write_req->engine->exec_id; |
426960be | 4359 | } |
673a394b | 4360 | |
b4716185 | 4361 | unref: |
05394f39 | 4362 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 4363 | unlock: |
673a394b | 4364 | mutex_unlock(&dev->struct_mutex); |
1d7cfea1 | 4365 | return ret; |
673a394b EA |
4366 | } |
4367 | ||
4368 | int | |
4369 | i915_gem_throttle_ioctl(struct drm_device *dev, void *data, | |
4370 | struct drm_file *file_priv) | |
4371 | { | |
0206e353 | 4372 | return i915_gem_ring_throttle(dev, file_priv); |
673a394b EA |
4373 | } |
4374 | ||
3ef94daa CW |
4375 | int |
4376 | i915_gem_madvise_ioctl(struct drm_device *dev, void *data, | |
4377 | struct drm_file *file_priv) | |
4378 | { | |
656bfa3a | 4379 | struct drm_i915_private *dev_priv = dev->dev_private; |
3ef94daa | 4380 | struct drm_i915_gem_madvise *args = data; |
05394f39 | 4381 | struct drm_i915_gem_object *obj; |
76c1dec1 | 4382 | int ret; |
3ef94daa CW |
4383 | |
4384 | switch (args->madv) { | |
4385 | case I915_MADV_DONTNEED: | |
4386 | case I915_MADV_WILLNEED: | |
4387 | break; | |
4388 | default: | |
4389 | return -EINVAL; | |
4390 | } | |
4391 | ||
1d7cfea1 CW |
4392 | ret = i915_mutex_lock_interruptible(dev); |
4393 | if (ret) | |
4394 | return ret; | |
4395 | ||
05394f39 | 4396 | obj = to_intel_bo(drm_gem_object_lookup(dev, file_priv, args->handle)); |
c8725226 | 4397 | if (&obj->base == NULL) { |
1d7cfea1 CW |
4398 | ret = -ENOENT; |
4399 | goto unlock; | |
3ef94daa | 4400 | } |
3ef94daa | 4401 | |
d7f46fc4 | 4402 | if (i915_gem_obj_is_pinned(obj)) { |
1d7cfea1 CW |
4403 | ret = -EINVAL; |
4404 | goto out; | |
3ef94daa CW |
4405 | } |
4406 | ||
656bfa3a DV |
4407 | if (obj->pages && |
4408 | obj->tiling_mode != I915_TILING_NONE && | |
4409 | dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES) { | |
4410 | if (obj->madv == I915_MADV_WILLNEED) | |
4411 | i915_gem_object_unpin_pages(obj); | |
4412 | if (args->madv == I915_MADV_WILLNEED) | |
4413 | i915_gem_object_pin_pages(obj); | |
4414 | } | |
4415 | ||
05394f39 CW |
4416 | if (obj->madv != __I915_MADV_PURGED) |
4417 | obj->madv = args->madv; | |
3ef94daa | 4418 | |
6c085a72 | 4419 | /* if the object is no longer attached, discard its backing storage */ |
be6a0376 | 4420 | if (obj->madv == I915_MADV_DONTNEED && obj->pages == NULL) |
2d7ef395 CW |
4421 | i915_gem_object_truncate(obj); |
4422 | ||
05394f39 | 4423 | args->retained = obj->madv != __I915_MADV_PURGED; |
bb6baf76 | 4424 | |
1d7cfea1 | 4425 | out: |
05394f39 | 4426 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 4427 | unlock: |
3ef94daa | 4428 | mutex_unlock(&dev->struct_mutex); |
1d7cfea1 | 4429 | return ret; |
3ef94daa CW |
4430 | } |
4431 | ||
37e680a1 CW |
4432 | void i915_gem_object_init(struct drm_i915_gem_object *obj, |
4433 | const struct drm_i915_gem_object_ops *ops) | |
0327d6ba | 4434 | { |
b4716185 CW |
4435 | int i; |
4436 | ||
35c20a60 | 4437 | INIT_LIST_HEAD(&obj->global_list); |
666796da | 4438 | for (i = 0; i < I915_NUM_ENGINES; i++) |
117897f4 | 4439 | INIT_LIST_HEAD(&obj->engine_list[i]); |
b25cb2f8 | 4440 | INIT_LIST_HEAD(&obj->obj_exec_link); |
2f633156 | 4441 | INIT_LIST_HEAD(&obj->vma_list); |
8d9d5744 | 4442 | INIT_LIST_HEAD(&obj->batch_pool_link); |
0327d6ba | 4443 | |
37e680a1 CW |
4444 | obj->ops = ops; |
4445 | ||
0327d6ba CW |
4446 | obj->fence_reg = I915_FENCE_REG_NONE; |
4447 | obj->madv = I915_MADV_WILLNEED; | |
0327d6ba CW |
4448 | |
4449 | i915_gem_info_add_obj(obj->base.dev->dev_private, obj->base.size); | |
4450 | } | |
4451 | ||
37e680a1 | 4452 | static const struct drm_i915_gem_object_ops i915_gem_object_ops = { |
de472664 | 4453 | .flags = I915_GEM_OBJECT_HAS_STRUCT_PAGE, |
37e680a1 CW |
4454 | .get_pages = i915_gem_object_get_pages_gtt, |
4455 | .put_pages = i915_gem_object_put_pages_gtt, | |
4456 | }; | |
4457 | ||
05394f39 CW |
4458 | struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev, |
4459 | size_t size) | |
ac52bc56 | 4460 | { |
c397b908 | 4461 | struct drm_i915_gem_object *obj; |
5949eac4 | 4462 | struct address_space *mapping; |
1a240d4d | 4463 | gfp_t mask; |
ac52bc56 | 4464 | |
42dcedd4 | 4465 | obj = i915_gem_object_alloc(dev); |
c397b908 DV |
4466 | if (obj == NULL) |
4467 | return NULL; | |
673a394b | 4468 | |
c397b908 | 4469 | if (drm_gem_object_init(dev, &obj->base, size) != 0) { |
42dcedd4 | 4470 | i915_gem_object_free(obj); |
c397b908 DV |
4471 | return NULL; |
4472 | } | |
673a394b | 4473 | |
bed1ea95 CW |
4474 | mask = GFP_HIGHUSER | __GFP_RECLAIMABLE; |
4475 | if (IS_CRESTLINE(dev) || IS_BROADWATER(dev)) { | |
4476 | /* 965gm cannot relocate objects above 4GiB. */ | |
4477 | mask &= ~__GFP_HIGHMEM; | |
4478 | mask |= __GFP_DMA32; | |
4479 | } | |
4480 | ||
496ad9aa | 4481 | mapping = file_inode(obj->base.filp)->i_mapping; |
bed1ea95 | 4482 | mapping_set_gfp_mask(mapping, mask); |
5949eac4 | 4483 | |
37e680a1 | 4484 | i915_gem_object_init(obj, &i915_gem_object_ops); |
73aa808f | 4485 | |
c397b908 DV |
4486 | obj->base.write_domain = I915_GEM_DOMAIN_CPU; |
4487 | obj->base.read_domains = I915_GEM_DOMAIN_CPU; | |
673a394b | 4488 | |
3d29b842 ED |
4489 | if (HAS_LLC(dev)) { |
4490 | /* On some devices, we can have the GPU use the LLC (the CPU | |
a1871112 EA |
4491 | * cache) for about a 10% performance improvement |
4492 | * compared to uncached. Graphics requests other than | |
4493 | * display scanout are coherent with the CPU in | |
4494 | * accessing this cache. This means in this mode we | |
4495 | * don't need to clflush on the CPU side, and on the | |
4496 | * GPU side we only need to flush internal caches to | |
4497 | * get data visible to the CPU. | |
4498 | * | |
4499 | * However, we maintain the display planes as UC, and so | |
4500 | * need to rebind when first used as such. | |
4501 | */ | |
4502 | obj->cache_level = I915_CACHE_LLC; | |
4503 | } else | |
4504 | obj->cache_level = I915_CACHE_NONE; | |
4505 | ||
d861e338 DV |
4506 | trace_i915_gem_object_create(obj); |
4507 | ||
05394f39 | 4508 | return obj; |
c397b908 DV |
4509 | } |
4510 | ||
340fbd8c CW |
4511 | static bool discard_backing_storage(struct drm_i915_gem_object *obj) |
4512 | { | |
4513 | /* If we are the last user of the backing storage (be it shmemfs | |
4514 | * pages or stolen etc), we know that the pages are going to be | |
4515 | * immediately released. In this case, we can then skip copying | |
4516 | * back the contents from the GPU. | |
4517 | */ | |
4518 | ||
4519 | if (obj->madv != I915_MADV_WILLNEED) | |
4520 | return false; | |
4521 | ||
4522 | if (obj->base.filp == NULL) | |
4523 | return true; | |
4524 | ||
4525 | /* At first glance, this looks racy, but then again so would be | |
4526 | * userspace racing mmap against close. However, the first external | |
4527 | * reference to the filp can only be obtained through the | |
4528 | * i915_gem_mmap_ioctl() which safeguards us against the user | |
4529 | * acquiring such a reference whilst we are in the middle of | |
4530 | * freeing the object. | |
4531 | */ | |
4532 | return atomic_long_read(&obj->base.filp->f_count) == 1; | |
4533 | } | |
4534 | ||
1488fc08 | 4535 | void i915_gem_free_object(struct drm_gem_object *gem_obj) |
673a394b | 4536 | { |
1488fc08 | 4537 | struct drm_i915_gem_object *obj = to_intel_bo(gem_obj); |
05394f39 | 4538 | struct drm_device *dev = obj->base.dev; |
3e31c6c0 | 4539 | struct drm_i915_private *dev_priv = dev->dev_private; |
07fe0b12 | 4540 | struct i915_vma *vma, *next; |
673a394b | 4541 | |
f65c9168 PZ |
4542 | intel_runtime_pm_get(dev_priv); |
4543 | ||
26e12f89 CW |
4544 | trace_i915_gem_object_destroy(obj); |
4545 | ||
1c7f4bca | 4546 | list_for_each_entry_safe(vma, next, &obj->vma_list, obj_link) { |
d7f46fc4 BW |
4547 | int ret; |
4548 | ||
4549 | vma->pin_count = 0; | |
4550 | ret = i915_vma_unbind(vma); | |
07fe0b12 BW |
4551 | if (WARN_ON(ret == -ERESTARTSYS)) { |
4552 | bool was_interruptible; | |
1488fc08 | 4553 | |
07fe0b12 BW |
4554 | was_interruptible = dev_priv->mm.interruptible; |
4555 | dev_priv->mm.interruptible = false; | |
1488fc08 | 4556 | |
07fe0b12 | 4557 | WARN_ON(i915_vma_unbind(vma)); |
1488fc08 | 4558 | |
07fe0b12 BW |
4559 | dev_priv->mm.interruptible = was_interruptible; |
4560 | } | |
1488fc08 CW |
4561 | } |
4562 | ||
1d64ae71 BW |
4563 | /* Stolen objects don't hold a ref, but do hold pin count. Fix that up |
4564 | * before progressing. */ | |
4565 | if (obj->stolen) | |
4566 | i915_gem_object_unpin_pages(obj); | |
4567 | ||
a071fa00 DV |
4568 | WARN_ON(obj->frontbuffer_bits); |
4569 | ||
656bfa3a DV |
4570 | if (obj->pages && obj->madv == I915_MADV_WILLNEED && |
4571 | dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES && | |
4572 | obj->tiling_mode != I915_TILING_NONE) | |
4573 | i915_gem_object_unpin_pages(obj); | |
4574 | ||
401c29f6 BW |
4575 | if (WARN_ON(obj->pages_pin_count)) |
4576 | obj->pages_pin_count = 0; | |
340fbd8c | 4577 | if (discard_backing_storage(obj)) |
5537252b | 4578 | obj->madv = I915_MADV_DONTNEED; |
37e680a1 | 4579 | i915_gem_object_put_pages(obj); |
d8cb5086 | 4580 | i915_gem_object_free_mmap_offset(obj); |
de151cf6 | 4581 | |
9da3da66 CW |
4582 | BUG_ON(obj->pages); |
4583 | ||
2f745ad3 CW |
4584 | if (obj->base.import_attach) |
4585 | drm_prime_gem_destroy(&obj->base, NULL); | |
de151cf6 | 4586 | |
5cc9ed4b CW |
4587 | if (obj->ops->release) |
4588 | obj->ops->release(obj); | |
4589 | ||
05394f39 CW |
4590 | drm_gem_object_release(&obj->base); |
4591 | i915_gem_info_remove_obj(dev_priv, obj->base.size); | |
c397b908 | 4592 | |
05394f39 | 4593 | kfree(obj->bit_17); |
42dcedd4 | 4594 | i915_gem_object_free(obj); |
f65c9168 PZ |
4595 | |
4596 | intel_runtime_pm_put(dev_priv); | |
673a394b EA |
4597 | } |
4598 | ||
ec7adb6e JL |
4599 | struct i915_vma *i915_gem_obj_to_vma(struct drm_i915_gem_object *obj, |
4600 | struct i915_address_space *vm) | |
e656a6cb DV |
4601 | { |
4602 | struct i915_vma *vma; | |
1c7f4bca | 4603 | list_for_each_entry(vma, &obj->vma_list, obj_link) { |
1b683729 TU |
4604 | if (vma->ggtt_view.type == I915_GGTT_VIEW_NORMAL && |
4605 | vma->vm == vm) | |
e656a6cb | 4606 | return vma; |
ec7adb6e JL |
4607 | } |
4608 | return NULL; | |
4609 | } | |
4610 | ||
4611 | struct i915_vma *i915_gem_obj_to_ggtt_view(struct drm_i915_gem_object *obj, | |
4612 | const struct i915_ggtt_view *view) | |
4613 | { | |
4614 | struct i915_address_space *ggtt = i915_obj_to_ggtt(obj); | |
4615 | struct i915_vma *vma; | |
e656a6cb | 4616 | |
ade7daa1 | 4617 | BUG_ON(!view); |
ec7adb6e | 4618 | |
1c7f4bca | 4619 | list_for_each_entry(vma, &obj->vma_list, obj_link) |
9abc4648 JL |
4620 | if (vma->vm == ggtt && |
4621 | i915_ggtt_view_equal(&vma->ggtt_view, view)) | |
ec7adb6e | 4622 | return vma; |
e656a6cb DV |
4623 | return NULL; |
4624 | } | |
4625 | ||
2f633156 BW |
4626 | void i915_gem_vma_destroy(struct i915_vma *vma) |
4627 | { | |
4628 | WARN_ON(vma->node.allocated); | |
aaa05667 CW |
4629 | |
4630 | /* Keep the vma as a placeholder in the execbuffer reservation lists */ | |
4631 | if (!list_empty(&vma->exec_list)) | |
4632 | return; | |
4633 | ||
596c5923 CW |
4634 | if (!vma->is_ggtt) |
4635 | i915_ppgtt_put(i915_vm_to_ppgtt(vma->vm)); | |
b9d06dd9 | 4636 | |
1c7f4bca | 4637 | list_del(&vma->obj_link); |
b93dab6e | 4638 | |
e20d2ab7 | 4639 | kmem_cache_free(to_i915(vma->obj->base.dev)->vmas, vma); |
2f633156 BW |
4640 | } |
4641 | ||
e3efda49 | 4642 | static void |
117897f4 | 4643 | i915_gem_stop_engines(struct drm_device *dev) |
e3efda49 CW |
4644 | { |
4645 | struct drm_i915_private *dev_priv = dev->dev_private; | |
e2f80391 | 4646 | struct intel_engine_cs *engine; |
e3efda49 | 4647 | |
b4ac5afc | 4648 | for_each_engine(engine, dev_priv) |
117897f4 | 4649 | dev_priv->gt.stop_engine(engine); |
e3efda49 CW |
4650 | } |
4651 | ||
29105ccc | 4652 | int |
45c5f202 | 4653 | i915_gem_suspend(struct drm_device *dev) |
29105ccc | 4654 | { |
3e31c6c0 | 4655 | struct drm_i915_private *dev_priv = dev->dev_private; |
45c5f202 | 4656 | int ret = 0; |
28dfe52a | 4657 | |
45c5f202 | 4658 | mutex_lock(&dev->struct_mutex); |
b2da9fe5 | 4659 | ret = i915_gpu_idle(dev); |
f7403347 | 4660 | if (ret) |
45c5f202 | 4661 | goto err; |
f7403347 | 4662 | |
b2da9fe5 | 4663 | i915_gem_retire_requests(dev); |
673a394b | 4664 | |
117897f4 | 4665 | i915_gem_stop_engines(dev); |
45c5f202 CW |
4666 | mutex_unlock(&dev->struct_mutex); |
4667 | ||
737b1506 | 4668 | cancel_delayed_work_sync(&dev_priv->gpu_error.hangcheck_work); |
29105ccc | 4669 | cancel_delayed_work_sync(&dev_priv->mm.retire_work); |
274fa1c1 | 4670 | flush_delayed_work(&dev_priv->mm.idle_work); |
29105ccc | 4671 | |
bdcf120b CW |
4672 | /* Assert that we sucessfully flushed all the work and |
4673 | * reset the GPU back to its idle, low power state. | |
4674 | */ | |
4675 | WARN_ON(dev_priv->mm.busy); | |
4676 | ||
673a394b | 4677 | return 0; |
45c5f202 CW |
4678 | |
4679 | err: | |
4680 | mutex_unlock(&dev->struct_mutex); | |
4681 | return ret; | |
673a394b EA |
4682 | } |
4683 | ||
6909a666 | 4684 | int i915_gem_l3_remap(struct drm_i915_gem_request *req, int slice) |
b9524a1e | 4685 | { |
4a570db5 | 4686 | struct intel_engine_cs *engine = req->engine; |
e2f80391 | 4687 | struct drm_device *dev = engine->dev; |
3e31c6c0 | 4688 | struct drm_i915_private *dev_priv = dev->dev_private; |
35a85ac6 | 4689 | u32 *remap_info = dev_priv->l3_parity.remap_info[slice]; |
c3787e2e | 4690 | int i, ret; |
b9524a1e | 4691 | |
040d2baa | 4692 | if (!HAS_L3_DPF(dev) || !remap_info) |
c3787e2e | 4693 | return 0; |
b9524a1e | 4694 | |
5fb9de1a | 4695 | ret = intel_ring_begin(req, GEN7_L3LOG_SIZE / 4 * 3); |
c3787e2e BW |
4696 | if (ret) |
4697 | return ret; | |
b9524a1e | 4698 | |
c3787e2e BW |
4699 | /* |
4700 | * Note: We do not worry about the concurrent register cacheline hang | |
4701 | * here because no other code should access these registers other than | |
4702 | * at initialization time. | |
4703 | */ | |
6fa1c5f1 | 4704 | for (i = 0; i < GEN7_L3LOG_SIZE / 4; i++) { |
e2f80391 TU |
4705 | intel_ring_emit(engine, MI_LOAD_REGISTER_IMM(1)); |
4706 | intel_ring_emit_reg(engine, GEN7_L3LOG(slice, i)); | |
4707 | intel_ring_emit(engine, remap_info[i]); | |
b9524a1e BW |
4708 | } |
4709 | ||
e2f80391 | 4710 | intel_ring_advance(engine); |
b9524a1e | 4711 | |
c3787e2e | 4712 | return ret; |
b9524a1e BW |
4713 | } |
4714 | ||
f691e2f4 DV |
4715 | void i915_gem_init_swizzling(struct drm_device *dev) |
4716 | { | |
3e31c6c0 | 4717 | struct drm_i915_private *dev_priv = dev->dev_private; |
f691e2f4 | 4718 | |
11782b02 | 4719 | if (INTEL_INFO(dev)->gen < 5 || |
f691e2f4 DV |
4720 | dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_NONE) |
4721 | return; | |
4722 | ||
4723 | I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) | | |
4724 | DISP_TILE_SURFACE_SWIZZLING); | |
4725 | ||
11782b02 DV |
4726 | if (IS_GEN5(dev)) |
4727 | return; | |
4728 | ||
f691e2f4 DV |
4729 | I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_SWZCTL); |
4730 | if (IS_GEN6(dev)) | |
6b26c86d | 4731 | I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB)); |
8782e26c | 4732 | else if (IS_GEN7(dev)) |
6b26c86d | 4733 | I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB)); |
31a5336e BW |
4734 | else if (IS_GEN8(dev)) |
4735 | I915_WRITE(GAMTARBMODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_BDW)); | |
8782e26c BW |
4736 | else |
4737 | BUG(); | |
f691e2f4 | 4738 | } |
e21af88d | 4739 | |
81e7f200 VS |
4740 | static void init_unused_ring(struct drm_device *dev, u32 base) |
4741 | { | |
4742 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4743 | ||
4744 | I915_WRITE(RING_CTL(base), 0); | |
4745 | I915_WRITE(RING_HEAD(base), 0); | |
4746 | I915_WRITE(RING_TAIL(base), 0); | |
4747 | I915_WRITE(RING_START(base), 0); | |
4748 | } | |
4749 | ||
4750 | static void init_unused_rings(struct drm_device *dev) | |
4751 | { | |
4752 | if (IS_I830(dev)) { | |
4753 | init_unused_ring(dev, PRB1_BASE); | |
4754 | init_unused_ring(dev, SRB0_BASE); | |
4755 | init_unused_ring(dev, SRB1_BASE); | |
4756 | init_unused_ring(dev, SRB2_BASE); | |
4757 | init_unused_ring(dev, SRB3_BASE); | |
4758 | } else if (IS_GEN2(dev)) { | |
4759 | init_unused_ring(dev, SRB0_BASE); | |
4760 | init_unused_ring(dev, SRB1_BASE); | |
4761 | } else if (IS_GEN3(dev)) { | |
4762 | init_unused_ring(dev, PRB1_BASE); | |
4763 | init_unused_ring(dev, PRB2_BASE); | |
4764 | } | |
4765 | } | |
4766 | ||
117897f4 | 4767 | int i915_gem_init_engines(struct drm_device *dev) |
8187a2b7 | 4768 | { |
4fc7c971 | 4769 | struct drm_i915_private *dev_priv = dev->dev_private; |
8187a2b7 | 4770 | int ret; |
68f95ba9 | 4771 | |
5c1143bb | 4772 | ret = intel_init_render_ring_buffer(dev); |
68f95ba9 | 4773 | if (ret) |
b6913e4b | 4774 | return ret; |
68f95ba9 CW |
4775 | |
4776 | if (HAS_BSD(dev)) { | |
5c1143bb | 4777 | ret = intel_init_bsd_ring_buffer(dev); |
68f95ba9 CW |
4778 | if (ret) |
4779 | goto cleanup_render_ring; | |
d1b851fc | 4780 | } |
68f95ba9 | 4781 | |
d39398f5 | 4782 | if (HAS_BLT(dev)) { |
549f7365 CW |
4783 | ret = intel_init_blt_ring_buffer(dev); |
4784 | if (ret) | |
4785 | goto cleanup_bsd_ring; | |
4786 | } | |
4787 | ||
9a8a2213 BW |
4788 | if (HAS_VEBOX(dev)) { |
4789 | ret = intel_init_vebox_ring_buffer(dev); | |
4790 | if (ret) | |
4791 | goto cleanup_blt_ring; | |
4792 | } | |
4793 | ||
845f74a7 ZY |
4794 | if (HAS_BSD2(dev)) { |
4795 | ret = intel_init_bsd2_ring_buffer(dev); | |
4796 | if (ret) | |
4797 | goto cleanup_vebox_ring; | |
4798 | } | |
9a8a2213 | 4799 | |
4fc7c971 BW |
4800 | return 0; |
4801 | ||
9a8a2213 | 4802 | cleanup_vebox_ring: |
117897f4 | 4803 | intel_cleanup_engine(&dev_priv->engine[VECS]); |
4fc7c971 | 4804 | cleanup_blt_ring: |
117897f4 | 4805 | intel_cleanup_engine(&dev_priv->engine[BCS]); |
4fc7c971 | 4806 | cleanup_bsd_ring: |
117897f4 | 4807 | intel_cleanup_engine(&dev_priv->engine[VCS]); |
4fc7c971 | 4808 | cleanup_render_ring: |
117897f4 | 4809 | intel_cleanup_engine(&dev_priv->engine[RCS]); |
4fc7c971 BW |
4810 | |
4811 | return ret; | |
4812 | } | |
4813 | ||
4814 | int | |
4815 | i915_gem_init_hw(struct drm_device *dev) | |
4816 | { | |
3e31c6c0 | 4817 | struct drm_i915_private *dev_priv = dev->dev_private; |
e2f80391 | 4818 | struct intel_engine_cs *engine; |
b4ac5afc | 4819 | int ret, j; |
4fc7c971 BW |
4820 | |
4821 | if (INTEL_INFO(dev)->gen < 6 && !intel_enable_gtt()) | |
4822 | return -EIO; | |
4823 | ||
5e4f5189 CW |
4824 | /* Double layer security blanket, see i915_gem_init() */ |
4825 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); | |
4826 | ||
59124506 | 4827 | if (dev_priv->ellc_size) |
05e21cc4 | 4828 | I915_WRITE(HSW_IDICR, I915_READ(HSW_IDICR) | IDIHASHMSK(0xf)); |
4fc7c971 | 4829 | |
0bf21347 VS |
4830 | if (IS_HASWELL(dev)) |
4831 | I915_WRITE(MI_PREDICATE_RESULT_2, IS_HSW_GT3(dev) ? | |
4832 | LOWER_SLICE_ENABLED : LOWER_SLICE_DISABLED); | |
9435373e | 4833 | |
88a2b2a3 | 4834 | if (HAS_PCH_NOP(dev)) { |
6ba844b0 DV |
4835 | if (IS_IVYBRIDGE(dev)) { |
4836 | u32 temp = I915_READ(GEN7_MSG_CTL); | |
4837 | temp &= ~(WAIT_FOR_PCH_FLR_ACK | WAIT_FOR_PCH_RESET_ACK); | |
4838 | I915_WRITE(GEN7_MSG_CTL, temp); | |
4839 | } else if (INTEL_INFO(dev)->gen >= 7) { | |
4840 | u32 temp = I915_READ(HSW_NDE_RSTWRN_OPT); | |
4841 | temp &= ~RESET_PCH_HANDSHAKE_ENABLE; | |
4842 | I915_WRITE(HSW_NDE_RSTWRN_OPT, temp); | |
4843 | } | |
88a2b2a3 BW |
4844 | } |
4845 | ||
4fc7c971 BW |
4846 | i915_gem_init_swizzling(dev); |
4847 | ||
d5abdfda DV |
4848 | /* |
4849 | * At least 830 can leave some of the unused rings | |
4850 | * "active" (ie. head != tail) after resume which | |
4851 | * will prevent c3 entry. Makes sure all unused rings | |
4852 | * are totally idle. | |
4853 | */ | |
4854 | init_unused_rings(dev); | |
4855 | ||
ed54c1a1 | 4856 | BUG_ON(!dev_priv->kernel_context); |
90638cc1 | 4857 | |
4ad2fd88 JH |
4858 | ret = i915_ppgtt_init_hw(dev); |
4859 | if (ret) { | |
4860 | DRM_ERROR("PPGTT enable HW failed %d\n", ret); | |
4861 | goto out; | |
4862 | } | |
4863 | ||
4864 | /* Need to do basic initialisation of all rings first: */ | |
b4ac5afc | 4865 | for_each_engine(engine, dev_priv) { |
e2f80391 | 4866 | ret = engine->init_hw(engine); |
35a57ffb | 4867 | if (ret) |
5e4f5189 | 4868 | goto out; |
35a57ffb | 4869 | } |
99433931 | 4870 | |
33a732f4 | 4871 | /* We can't enable contexts until all firmware is loaded */ |
87bcdd2e JB |
4872 | if (HAS_GUC_UCODE(dev)) { |
4873 | ret = intel_guc_ucode_load(dev); | |
4874 | if (ret) { | |
9f9e539f DV |
4875 | DRM_ERROR("Failed to initialize GuC, error %d\n", ret); |
4876 | ret = -EIO; | |
4877 | goto out; | |
87bcdd2e | 4878 | } |
33a732f4 AD |
4879 | } |
4880 | ||
e84fe803 NH |
4881 | /* |
4882 | * Increment the next seqno by 0x100 so we have a visible break | |
4883 | * on re-initialisation | |
4884 | */ | |
4885 | ret = i915_gem_set_seqno(dev, dev_priv->next_seqno+0x100); | |
4886 | if (ret) | |
4887 | goto out; | |
4888 | ||
4ad2fd88 | 4889 | /* Now it is safe to go back round and do everything else: */ |
b4ac5afc | 4890 | for_each_engine(engine, dev_priv) { |
dc4be607 JH |
4891 | struct drm_i915_gem_request *req; |
4892 | ||
e2f80391 | 4893 | req = i915_gem_request_alloc(engine, NULL); |
26827088 DG |
4894 | if (IS_ERR(req)) { |
4895 | ret = PTR_ERR(req); | |
117897f4 | 4896 | i915_gem_cleanup_engines(dev); |
dc4be607 JH |
4897 | goto out; |
4898 | } | |
4899 | ||
e2f80391 | 4900 | if (engine->id == RCS) { |
4ad2fd88 | 4901 | for (j = 0; j < NUM_L3_SLICES(dev); j++) |
6909a666 | 4902 | i915_gem_l3_remap(req, j); |
4ad2fd88 | 4903 | } |
c3787e2e | 4904 | |
b3dd6b96 | 4905 | ret = i915_ppgtt_init_ring(req); |
4ad2fd88 | 4906 | if (ret && ret != -EIO) { |
b4ac5afc DG |
4907 | DRM_ERROR("PPGTT enable %s failed %d\n", |
4908 | engine->name, ret); | |
dc4be607 | 4909 | i915_gem_request_cancel(req); |
117897f4 | 4910 | i915_gem_cleanup_engines(dev); |
4ad2fd88 JH |
4911 | goto out; |
4912 | } | |
82460d97 | 4913 | |
b3dd6b96 | 4914 | ret = i915_gem_context_enable(req); |
90638cc1 | 4915 | if (ret && ret != -EIO) { |
b4ac5afc DG |
4916 | DRM_ERROR("Context enable %s failed %d\n", |
4917 | engine->name, ret); | |
dc4be607 | 4918 | i915_gem_request_cancel(req); |
117897f4 | 4919 | i915_gem_cleanup_engines(dev); |
90638cc1 JH |
4920 | goto out; |
4921 | } | |
dc4be607 | 4922 | |
75289874 | 4923 | i915_add_request_no_flush(req); |
b7c36d25 | 4924 | } |
e21af88d | 4925 | |
5e4f5189 CW |
4926 | out: |
4927 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); | |
2fa48d8d | 4928 | return ret; |
8187a2b7 ZN |
4929 | } |
4930 | ||
1070a42b CW |
4931 | int i915_gem_init(struct drm_device *dev) |
4932 | { | |
4933 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1070a42b CW |
4934 | int ret; |
4935 | ||
127f1003 OM |
4936 | i915.enable_execlists = intel_sanitize_enable_execlists(dev, |
4937 | i915.enable_execlists); | |
4938 | ||
1070a42b | 4939 | mutex_lock(&dev->struct_mutex); |
d62b4892 | 4940 | |
a83014d3 | 4941 | if (!i915.enable_execlists) { |
f3dc74c0 | 4942 | dev_priv->gt.execbuf_submit = i915_gem_ringbuffer_submission; |
117897f4 TU |
4943 | dev_priv->gt.init_engines = i915_gem_init_engines; |
4944 | dev_priv->gt.cleanup_engine = intel_cleanup_engine; | |
4945 | dev_priv->gt.stop_engine = intel_stop_engine; | |
454afebd | 4946 | } else { |
f3dc74c0 | 4947 | dev_priv->gt.execbuf_submit = intel_execlists_submission; |
117897f4 TU |
4948 | dev_priv->gt.init_engines = intel_logical_rings_init; |
4949 | dev_priv->gt.cleanup_engine = intel_logical_ring_cleanup; | |
4950 | dev_priv->gt.stop_engine = intel_logical_ring_stop; | |
a83014d3 OM |
4951 | } |
4952 | ||
5e4f5189 CW |
4953 | /* This is just a security blanket to placate dragons. |
4954 | * On some systems, we very sporadically observe that the first TLBs | |
4955 | * used by the CS may be stale, despite us poking the TLB reset. If | |
4956 | * we hold the forcewake during initialisation these problems | |
4957 | * just magically go away. | |
4958 | */ | |
4959 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); | |
4960 | ||
6c5566a8 | 4961 | ret = i915_gem_init_userptr(dev); |
7bcc3777 JN |
4962 | if (ret) |
4963 | goto out_unlock; | |
6c5566a8 | 4964 | |
d85489d3 | 4965 | i915_gem_init_ggtt(dev); |
d62b4892 | 4966 | |
2fa48d8d | 4967 | ret = i915_gem_context_init(dev); |
7bcc3777 JN |
4968 | if (ret) |
4969 | goto out_unlock; | |
2fa48d8d | 4970 | |
117897f4 | 4971 | ret = dev_priv->gt.init_engines(dev); |
35a57ffb | 4972 | if (ret) |
7bcc3777 | 4973 | goto out_unlock; |
2fa48d8d | 4974 | |
1070a42b | 4975 | ret = i915_gem_init_hw(dev); |
60990320 CW |
4976 | if (ret == -EIO) { |
4977 | /* Allow ring initialisation to fail by marking the GPU as | |
4978 | * wedged. But we only want to do this where the GPU is angry, | |
4979 | * for all other failure, such as an allocation failure, bail. | |
4980 | */ | |
4981 | DRM_ERROR("Failed to initialize GPU, declaring it wedged\n"); | |
805de8f4 | 4982 | atomic_or(I915_WEDGED, &dev_priv->gpu_error.reset_counter); |
60990320 | 4983 | ret = 0; |
1070a42b | 4984 | } |
7bcc3777 JN |
4985 | |
4986 | out_unlock: | |
5e4f5189 | 4987 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); |
60990320 | 4988 | mutex_unlock(&dev->struct_mutex); |
1070a42b | 4989 | |
60990320 | 4990 | return ret; |
1070a42b CW |
4991 | } |
4992 | ||
8187a2b7 | 4993 | void |
117897f4 | 4994 | i915_gem_cleanup_engines(struct drm_device *dev) |
8187a2b7 | 4995 | { |
3e31c6c0 | 4996 | struct drm_i915_private *dev_priv = dev->dev_private; |
e2f80391 | 4997 | struct intel_engine_cs *engine; |
8187a2b7 | 4998 | |
b4ac5afc | 4999 | for_each_engine(engine, dev_priv) |
117897f4 | 5000 | dev_priv->gt.cleanup_engine(engine); |
a647828a | 5001 | |
ee4b6faf MK |
5002 | if (i915.enable_execlists) |
5003 | /* | |
5004 | * Neither the BIOS, ourselves or any other kernel | |
5005 | * expects the system to be in execlists mode on startup, | |
5006 | * so we need to reset the GPU back to legacy mode. | |
5007 | */ | |
5008 | intel_gpu_reset(dev, ALL_ENGINES); | |
8187a2b7 ZN |
5009 | } |
5010 | ||
64193406 | 5011 | static void |
666796da | 5012 | init_engine_lists(struct intel_engine_cs *engine) |
64193406 | 5013 | { |
0bc40be8 TU |
5014 | INIT_LIST_HEAD(&engine->active_list); |
5015 | INIT_LIST_HEAD(&engine->request_list); | |
64193406 CW |
5016 | } |
5017 | ||
40ae4e16 ID |
5018 | void |
5019 | i915_gem_load_init_fences(struct drm_i915_private *dev_priv) | |
5020 | { | |
5021 | struct drm_device *dev = dev_priv->dev; | |
5022 | ||
5023 | if (INTEL_INFO(dev_priv)->gen >= 7 && !IS_VALLEYVIEW(dev_priv) && | |
5024 | !IS_CHERRYVIEW(dev_priv)) | |
5025 | dev_priv->num_fence_regs = 32; | |
5026 | else if (INTEL_INFO(dev_priv)->gen >= 4 || IS_I945G(dev_priv) || | |
5027 | IS_I945GM(dev_priv) || IS_G33(dev_priv)) | |
5028 | dev_priv->num_fence_regs = 16; | |
5029 | else | |
5030 | dev_priv->num_fence_regs = 8; | |
5031 | ||
5032 | if (intel_vgpu_active(dev)) | |
5033 | dev_priv->num_fence_regs = | |
5034 | I915_READ(vgtif_reg(avail_rs.fence_num)); | |
5035 | ||
5036 | /* Initialize fence registers to zero */ | |
5037 | i915_gem_restore_fences(dev); | |
5038 | ||
5039 | i915_gem_detect_bit_6_swizzle(dev); | |
5040 | } | |
5041 | ||
673a394b | 5042 | void |
d64aa096 | 5043 | i915_gem_load_init(struct drm_device *dev) |
673a394b | 5044 | { |
3e31c6c0 | 5045 | struct drm_i915_private *dev_priv = dev->dev_private; |
42dcedd4 CW |
5046 | int i; |
5047 | ||
efab6d8d | 5048 | dev_priv->objects = |
42dcedd4 CW |
5049 | kmem_cache_create("i915_gem_object", |
5050 | sizeof(struct drm_i915_gem_object), 0, | |
5051 | SLAB_HWCACHE_ALIGN, | |
5052 | NULL); | |
e20d2ab7 CW |
5053 | dev_priv->vmas = |
5054 | kmem_cache_create("i915_gem_vma", | |
5055 | sizeof(struct i915_vma), 0, | |
5056 | SLAB_HWCACHE_ALIGN, | |
5057 | NULL); | |
efab6d8d CW |
5058 | dev_priv->requests = |
5059 | kmem_cache_create("i915_gem_request", | |
5060 | sizeof(struct drm_i915_gem_request), 0, | |
5061 | SLAB_HWCACHE_ALIGN, | |
5062 | NULL); | |
673a394b | 5063 | |
fc8c067e | 5064 | INIT_LIST_HEAD(&dev_priv->vm_list); |
a33afea5 | 5065 | INIT_LIST_HEAD(&dev_priv->context_list); |
6c085a72 CW |
5066 | INIT_LIST_HEAD(&dev_priv->mm.unbound_list); |
5067 | INIT_LIST_HEAD(&dev_priv->mm.bound_list); | |
a09ba7fa | 5068 | INIT_LIST_HEAD(&dev_priv->mm.fence_list); |
666796da TU |
5069 | for (i = 0; i < I915_NUM_ENGINES; i++) |
5070 | init_engine_lists(&dev_priv->engine[i]); | |
4b9de737 | 5071 | for (i = 0; i < I915_MAX_NUM_FENCES; i++) |
007cc8ac | 5072 | INIT_LIST_HEAD(&dev_priv->fence_regs[i].lru_list); |
673a394b EA |
5073 | INIT_DELAYED_WORK(&dev_priv->mm.retire_work, |
5074 | i915_gem_retire_work_handler); | |
b29c19b6 CW |
5075 | INIT_DELAYED_WORK(&dev_priv->mm.idle_work, |
5076 | i915_gem_idle_work_handler); | |
1f83fee0 | 5077 | init_waitqueue_head(&dev_priv->gpu_error.reset_queue); |
31169714 | 5078 | |
72bfa19c CW |
5079 | dev_priv->relative_constants_mode = I915_EXEC_CONSTANTS_REL_GENERAL; |
5080 | ||
e84fe803 NH |
5081 | /* |
5082 | * Set initial sequence number for requests. | |
5083 | * Using this number allows the wraparound to happen early, | |
5084 | * catching any obvious problems. | |
5085 | */ | |
5086 | dev_priv->next_seqno = ((u32)~0 - 0x1100); | |
5087 | dev_priv->last_seqno = ((u32)~0 - 0x1101); | |
5088 | ||
19b2dbde | 5089 | INIT_LIST_HEAD(&dev_priv->mm.fence_list); |
10ed13e4 | 5090 | |
6b95a207 | 5091 | init_waitqueue_head(&dev_priv->pending_flip_queue); |
17250b71 | 5092 | |
ce453d81 CW |
5093 | dev_priv->mm.interruptible = true; |
5094 | ||
f99d7069 | 5095 | mutex_init(&dev_priv->fb_tracking.lock); |
673a394b | 5096 | } |
71acb5eb | 5097 | |
d64aa096 ID |
5098 | void i915_gem_load_cleanup(struct drm_device *dev) |
5099 | { | |
5100 | struct drm_i915_private *dev_priv = to_i915(dev); | |
5101 | ||
5102 | kmem_cache_destroy(dev_priv->requests); | |
5103 | kmem_cache_destroy(dev_priv->vmas); | |
5104 | kmem_cache_destroy(dev_priv->objects); | |
5105 | } | |
5106 | ||
f787a5f5 | 5107 | void i915_gem_release(struct drm_device *dev, struct drm_file *file) |
b962442e | 5108 | { |
f787a5f5 | 5109 | struct drm_i915_file_private *file_priv = file->driver_priv; |
b962442e EA |
5110 | |
5111 | /* Clean up our request list when the client is going away, so that | |
5112 | * later retire_requests won't dereference our soon-to-be-gone | |
5113 | * file_priv. | |
5114 | */ | |
1c25595f | 5115 | spin_lock(&file_priv->mm.lock); |
f787a5f5 CW |
5116 | while (!list_empty(&file_priv->mm.request_list)) { |
5117 | struct drm_i915_gem_request *request; | |
5118 | ||
5119 | request = list_first_entry(&file_priv->mm.request_list, | |
5120 | struct drm_i915_gem_request, | |
5121 | client_list); | |
5122 | list_del(&request->client_list); | |
5123 | request->file_priv = NULL; | |
5124 | } | |
1c25595f | 5125 | spin_unlock(&file_priv->mm.lock); |
b29c19b6 | 5126 | |
2e1b8730 | 5127 | if (!list_empty(&file_priv->rps.link)) { |
8d3afd7d | 5128 | spin_lock(&to_i915(dev)->rps.client_lock); |
2e1b8730 | 5129 | list_del(&file_priv->rps.link); |
8d3afd7d | 5130 | spin_unlock(&to_i915(dev)->rps.client_lock); |
1854d5ca | 5131 | } |
b29c19b6 CW |
5132 | } |
5133 | ||
5134 | int i915_gem_open(struct drm_device *dev, struct drm_file *file) | |
5135 | { | |
5136 | struct drm_i915_file_private *file_priv; | |
e422b888 | 5137 | int ret; |
b29c19b6 CW |
5138 | |
5139 | DRM_DEBUG_DRIVER("\n"); | |
5140 | ||
5141 | file_priv = kzalloc(sizeof(*file_priv), GFP_KERNEL); | |
5142 | if (!file_priv) | |
5143 | return -ENOMEM; | |
5144 | ||
5145 | file->driver_priv = file_priv; | |
5146 | file_priv->dev_priv = dev->dev_private; | |
ab0e7ff9 | 5147 | file_priv->file = file; |
2e1b8730 | 5148 | INIT_LIST_HEAD(&file_priv->rps.link); |
b29c19b6 CW |
5149 | |
5150 | spin_lock_init(&file_priv->mm.lock); | |
5151 | INIT_LIST_HEAD(&file_priv->mm.request_list); | |
b29c19b6 | 5152 | |
de1add36 TU |
5153 | file_priv->bsd_ring = -1; |
5154 | ||
e422b888 BW |
5155 | ret = i915_gem_context_open(dev, file); |
5156 | if (ret) | |
5157 | kfree(file_priv); | |
b29c19b6 | 5158 | |
e422b888 | 5159 | return ret; |
b29c19b6 CW |
5160 | } |
5161 | ||
b680c37a DV |
5162 | /** |
5163 | * i915_gem_track_fb - update frontbuffer tracking | |
d9072a3e GT |
5164 | * @old: current GEM buffer for the frontbuffer slots |
5165 | * @new: new GEM buffer for the frontbuffer slots | |
5166 | * @frontbuffer_bits: bitmask of frontbuffer slots | |
b680c37a DV |
5167 | * |
5168 | * This updates the frontbuffer tracking bits @frontbuffer_bits by clearing them | |
5169 | * from @old and setting them in @new. Both @old and @new can be NULL. | |
5170 | */ | |
a071fa00 DV |
5171 | void i915_gem_track_fb(struct drm_i915_gem_object *old, |
5172 | struct drm_i915_gem_object *new, | |
5173 | unsigned frontbuffer_bits) | |
5174 | { | |
5175 | if (old) { | |
5176 | WARN_ON(!mutex_is_locked(&old->base.dev->struct_mutex)); | |
5177 | WARN_ON(!(old->frontbuffer_bits & frontbuffer_bits)); | |
5178 | old->frontbuffer_bits &= ~frontbuffer_bits; | |
5179 | } | |
5180 | ||
5181 | if (new) { | |
5182 | WARN_ON(!mutex_is_locked(&new->base.dev->struct_mutex)); | |
5183 | WARN_ON(new->frontbuffer_bits & frontbuffer_bits); | |
5184 | new->frontbuffer_bits |= frontbuffer_bits; | |
5185 | } | |
5186 | } | |
5187 | ||
a70a3148 | 5188 | /* All the new VM stuff */ |
088e0df4 MT |
5189 | u64 i915_gem_obj_offset(struct drm_i915_gem_object *o, |
5190 | struct i915_address_space *vm) | |
a70a3148 BW |
5191 | { |
5192 | struct drm_i915_private *dev_priv = o->base.dev->dev_private; | |
5193 | struct i915_vma *vma; | |
5194 | ||
896ab1a5 | 5195 | WARN_ON(vm == &dev_priv->mm.aliasing_ppgtt->base); |
a70a3148 | 5196 | |
1c7f4bca | 5197 | list_for_each_entry(vma, &o->vma_list, obj_link) { |
596c5923 | 5198 | if (vma->is_ggtt && |
ec7adb6e JL |
5199 | vma->ggtt_view.type != I915_GGTT_VIEW_NORMAL) |
5200 | continue; | |
5201 | if (vma->vm == vm) | |
a70a3148 | 5202 | return vma->node.start; |
a70a3148 | 5203 | } |
ec7adb6e | 5204 | |
f25748ea DV |
5205 | WARN(1, "%s vma for this object not found.\n", |
5206 | i915_is_ggtt(vm) ? "global" : "ppgtt"); | |
a70a3148 BW |
5207 | return -1; |
5208 | } | |
5209 | ||
088e0df4 MT |
5210 | u64 i915_gem_obj_ggtt_offset_view(struct drm_i915_gem_object *o, |
5211 | const struct i915_ggtt_view *view) | |
a70a3148 | 5212 | { |
ec7adb6e | 5213 | struct i915_address_space *ggtt = i915_obj_to_ggtt(o); |
a70a3148 BW |
5214 | struct i915_vma *vma; |
5215 | ||
1c7f4bca | 5216 | list_for_each_entry(vma, &o->vma_list, obj_link) |
9abc4648 JL |
5217 | if (vma->vm == ggtt && |
5218 | i915_ggtt_view_equal(&vma->ggtt_view, view)) | |
ec7adb6e JL |
5219 | return vma->node.start; |
5220 | ||
5678ad73 | 5221 | WARN(1, "global vma for this object not found. (view=%u)\n", view->type); |
ec7adb6e JL |
5222 | return -1; |
5223 | } | |
5224 | ||
5225 | bool i915_gem_obj_bound(struct drm_i915_gem_object *o, | |
5226 | struct i915_address_space *vm) | |
5227 | { | |
5228 | struct i915_vma *vma; | |
5229 | ||
1c7f4bca | 5230 | list_for_each_entry(vma, &o->vma_list, obj_link) { |
596c5923 | 5231 | if (vma->is_ggtt && |
ec7adb6e JL |
5232 | vma->ggtt_view.type != I915_GGTT_VIEW_NORMAL) |
5233 | continue; | |
5234 | if (vma->vm == vm && drm_mm_node_allocated(&vma->node)) | |
5235 | return true; | |
5236 | } | |
5237 | ||
5238 | return false; | |
5239 | } | |
5240 | ||
5241 | bool i915_gem_obj_ggtt_bound_view(struct drm_i915_gem_object *o, | |
9abc4648 | 5242 | const struct i915_ggtt_view *view) |
ec7adb6e JL |
5243 | { |
5244 | struct i915_address_space *ggtt = i915_obj_to_ggtt(o); | |
5245 | struct i915_vma *vma; | |
5246 | ||
1c7f4bca | 5247 | list_for_each_entry(vma, &o->vma_list, obj_link) |
ec7adb6e | 5248 | if (vma->vm == ggtt && |
9abc4648 | 5249 | i915_ggtt_view_equal(&vma->ggtt_view, view) && |
fe14d5f4 | 5250 | drm_mm_node_allocated(&vma->node)) |
a70a3148 BW |
5251 | return true; |
5252 | ||
5253 | return false; | |
5254 | } | |
5255 | ||
5256 | bool i915_gem_obj_bound_any(struct drm_i915_gem_object *o) | |
5257 | { | |
5a1d5eb0 | 5258 | struct i915_vma *vma; |
a70a3148 | 5259 | |
1c7f4bca | 5260 | list_for_each_entry(vma, &o->vma_list, obj_link) |
5a1d5eb0 | 5261 | if (drm_mm_node_allocated(&vma->node)) |
a70a3148 BW |
5262 | return true; |
5263 | ||
5264 | return false; | |
5265 | } | |
5266 | ||
5267 | unsigned long i915_gem_obj_size(struct drm_i915_gem_object *o, | |
5268 | struct i915_address_space *vm) | |
5269 | { | |
5270 | struct drm_i915_private *dev_priv = o->base.dev->dev_private; | |
5271 | struct i915_vma *vma; | |
5272 | ||
896ab1a5 | 5273 | WARN_ON(vm == &dev_priv->mm.aliasing_ppgtt->base); |
a70a3148 BW |
5274 | |
5275 | BUG_ON(list_empty(&o->vma_list)); | |
5276 | ||
1c7f4bca | 5277 | list_for_each_entry(vma, &o->vma_list, obj_link) { |
596c5923 | 5278 | if (vma->is_ggtt && |
ec7adb6e JL |
5279 | vma->ggtt_view.type != I915_GGTT_VIEW_NORMAL) |
5280 | continue; | |
a70a3148 BW |
5281 | if (vma->vm == vm) |
5282 | return vma->node.size; | |
ec7adb6e | 5283 | } |
a70a3148 BW |
5284 | return 0; |
5285 | } | |
5286 | ||
ec7adb6e | 5287 | bool i915_gem_obj_is_pinned(struct drm_i915_gem_object *obj) |
5c2abbea BW |
5288 | { |
5289 | struct i915_vma *vma; | |
1c7f4bca | 5290 | list_for_each_entry(vma, &obj->vma_list, obj_link) |
ec7adb6e JL |
5291 | if (vma->pin_count > 0) |
5292 | return true; | |
a6631ae1 | 5293 | |
ec7adb6e | 5294 | return false; |
5c2abbea | 5295 | } |
ea70299d | 5296 | |
033908ae DG |
5297 | /* Like i915_gem_object_get_page(), but mark the returned page dirty */ |
5298 | struct page * | |
5299 | i915_gem_object_get_dirty_page(struct drm_i915_gem_object *obj, int n) | |
5300 | { | |
5301 | struct page *page; | |
5302 | ||
5303 | /* Only default objects have per-page dirty tracking */ | |
de472664 | 5304 | if (WARN_ON((obj->ops->flags & I915_GEM_OBJECT_HAS_STRUCT_PAGE) == 0)) |
033908ae DG |
5305 | return NULL; |
5306 | ||
5307 | page = i915_gem_object_get_page(obj, n); | |
5308 | set_page_dirty(page); | |
5309 | return page; | |
5310 | } | |
5311 | ||
ea70299d DG |
5312 | /* Allocate a new GEM object and fill it with the supplied data */ |
5313 | struct drm_i915_gem_object * | |
5314 | i915_gem_object_create_from_data(struct drm_device *dev, | |
5315 | const void *data, size_t size) | |
5316 | { | |
5317 | struct drm_i915_gem_object *obj; | |
5318 | struct sg_table *sg; | |
5319 | size_t bytes; | |
5320 | int ret; | |
5321 | ||
5322 | obj = i915_gem_alloc_object(dev, round_up(size, PAGE_SIZE)); | |
5323 | if (IS_ERR_OR_NULL(obj)) | |
5324 | return obj; | |
5325 | ||
5326 | ret = i915_gem_object_set_to_cpu_domain(obj, true); | |
5327 | if (ret) | |
5328 | goto fail; | |
5329 | ||
5330 | ret = i915_gem_object_get_pages(obj); | |
5331 | if (ret) | |
5332 | goto fail; | |
5333 | ||
5334 | i915_gem_object_pin_pages(obj); | |
5335 | sg = obj->pages; | |
5336 | bytes = sg_copy_from_buffer(sg->sgl, sg->nents, (void *)data, size); | |
9e7d18c0 | 5337 | obj->dirty = 1; /* Backing store is now out of date */ |
ea70299d DG |
5338 | i915_gem_object_unpin_pages(obj); |
5339 | ||
5340 | if (WARN_ON(bytes != size)) { | |
5341 | DRM_ERROR("Incomplete copy, wrote %zu of %zu", bytes, size); | |
5342 | ret = -EFAULT; | |
5343 | goto fail; | |
5344 | } | |
5345 | ||
5346 | return obj; | |
5347 | ||
5348 | fail: | |
5349 | drm_gem_object_unreference(&obj->base); | |
5350 | return ERR_PTR(ret); | |
5351 | } |