Commit | Line | Data |
---|---|---|
673a394b EA |
1 | /* |
2 | * Copyright © 2008 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | * | |
26 | */ | |
27 | ||
760285e7 | 28 | #include <drm/drmP.h> |
0de23977 | 29 | #include <drm/drm_vma_manager.h> |
760285e7 | 30 | #include <drm/i915_drm.h> |
673a394b | 31 | #include "i915_drv.h" |
1c5d22f7 | 32 | #include "i915_trace.h" |
652c393a | 33 | #include "intel_drv.h" |
5949eac4 | 34 | #include <linux/shmem_fs.h> |
5a0e3ad6 | 35 | #include <linux/slab.h> |
673a394b | 36 | #include <linux/swap.h> |
79e53945 | 37 | #include <linux/pci.h> |
1286ff73 | 38 | #include <linux/dma-buf.h> |
673a394b | 39 | |
05394f39 | 40 | static void i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj); |
2c22569b CW |
41 | static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj, |
42 | bool force); | |
07fe0b12 | 43 | static __must_check int |
23f54483 BW |
44 | i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj, |
45 | bool readonly); | |
05394f39 CW |
46 | static int i915_gem_phys_pwrite(struct drm_device *dev, |
47 | struct drm_i915_gem_object *obj, | |
71acb5eb | 48 | struct drm_i915_gem_pwrite *args, |
05394f39 | 49 | struct drm_file *file); |
673a394b | 50 | |
61050808 CW |
51 | static void i915_gem_write_fence(struct drm_device *dev, int reg, |
52 | struct drm_i915_gem_object *obj); | |
53 | static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj, | |
54 | struct drm_i915_fence_reg *fence, | |
55 | bool enable); | |
56 | ||
7dc19d5a DC |
57 | static unsigned long i915_gem_inactive_count(struct shrinker *shrinker, |
58 | struct shrink_control *sc); | |
59 | static unsigned long i915_gem_inactive_scan(struct shrinker *shrinker, | |
60 | struct shrink_control *sc); | |
d9973b43 CW |
61 | static unsigned long i915_gem_purge(struct drm_i915_private *dev_priv, long target); |
62 | static unsigned long i915_gem_shrink_all(struct drm_i915_private *dev_priv); | |
8c59967c | 63 | static void i915_gem_object_truncate(struct drm_i915_gem_object *obj); |
cb216aa8 | 64 | static void i915_gem_retire_requests_ring(struct intel_ring_buffer *ring); |
31169714 | 65 | |
c76ce038 CW |
66 | static bool cpu_cache_is_coherent(struct drm_device *dev, |
67 | enum i915_cache_level level) | |
68 | { | |
69 | return HAS_LLC(dev) || level != I915_CACHE_NONE; | |
70 | } | |
71 | ||
2c22569b CW |
72 | static bool cpu_write_needs_clflush(struct drm_i915_gem_object *obj) |
73 | { | |
74 | if (!cpu_cache_is_coherent(obj->base.dev, obj->cache_level)) | |
75 | return true; | |
76 | ||
77 | return obj->pin_display; | |
78 | } | |
79 | ||
61050808 CW |
80 | static inline void i915_gem_object_fence_lost(struct drm_i915_gem_object *obj) |
81 | { | |
82 | if (obj->tiling_mode) | |
83 | i915_gem_release_mmap(obj); | |
84 | ||
85 | /* As we do not have an associated fence register, we will force | |
86 | * a tiling change if we ever need to acquire one. | |
87 | */ | |
5d82e3e6 | 88 | obj->fence_dirty = false; |
61050808 CW |
89 | obj->fence_reg = I915_FENCE_REG_NONE; |
90 | } | |
91 | ||
73aa808f CW |
92 | /* some bookkeeping */ |
93 | static void i915_gem_info_add_obj(struct drm_i915_private *dev_priv, | |
94 | size_t size) | |
95 | { | |
c20e8355 | 96 | spin_lock(&dev_priv->mm.object_stat_lock); |
73aa808f CW |
97 | dev_priv->mm.object_count++; |
98 | dev_priv->mm.object_memory += size; | |
c20e8355 | 99 | spin_unlock(&dev_priv->mm.object_stat_lock); |
73aa808f CW |
100 | } |
101 | ||
102 | static void i915_gem_info_remove_obj(struct drm_i915_private *dev_priv, | |
103 | size_t size) | |
104 | { | |
c20e8355 | 105 | spin_lock(&dev_priv->mm.object_stat_lock); |
73aa808f CW |
106 | dev_priv->mm.object_count--; |
107 | dev_priv->mm.object_memory -= size; | |
c20e8355 | 108 | spin_unlock(&dev_priv->mm.object_stat_lock); |
73aa808f CW |
109 | } |
110 | ||
21dd3734 | 111 | static int |
33196ded | 112 | i915_gem_wait_for_error(struct i915_gpu_error *error) |
30dbf0c0 | 113 | { |
30dbf0c0 CW |
114 | int ret; |
115 | ||
7abb690a DV |
116 | #define EXIT_COND (!i915_reset_in_progress(error) || \ |
117 | i915_terminally_wedged(error)) | |
1f83fee0 | 118 | if (EXIT_COND) |
30dbf0c0 CW |
119 | return 0; |
120 | ||
0a6759c6 DV |
121 | /* |
122 | * Only wait 10 seconds for the gpu reset to complete to avoid hanging | |
123 | * userspace. If it takes that long something really bad is going on and | |
124 | * we should simply try to bail out and fail as gracefully as possible. | |
125 | */ | |
1f83fee0 DV |
126 | ret = wait_event_interruptible_timeout(error->reset_queue, |
127 | EXIT_COND, | |
128 | 10*HZ); | |
0a6759c6 DV |
129 | if (ret == 0) { |
130 | DRM_ERROR("Timed out waiting for the gpu reset to complete\n"); | |
131 | return -EIO; | |
132 | } else if (ret < 0) { | |
30dbf0c0 | 133 | return ret; |
0a6759c6 | 134 | } |
1f83fee0 | 135 | #undef EXIT_COND |
30dbf0c0 | 136 | |
21dd3734 | 137 | return 0; |
30dbf0c0 CW |
138 | } |
139 | ||
54cf91dc | 140 | int i915_mutex_lock_interruptible(struct drm_device *dev) |
76c1dec1 | 141 | { |
33196ded | 142 | struct drm_i915_private *dev_priv = dev->dev_private; |
76c1dec1 CW |
143 | int ret; |
144 | ||
33196ded | 145 | ret = i915_gem_wait_for_error(&dev_priv->gpu_error); |
76c1dec1 CW |
146 | if (ret) |
147 | return ret; | |
148 | ||
149 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
150 | if (ret) | |
151 | return ret; | |
152 | ||
23bc5982 | 153 | WARN_ON(i915_verify_lists(dev)); |
76c1dec1 CW |
154 | return 0; |
155 | } | |
30dbf0c0 | 156 | |
7d1c4804 | 157 | static inline bool |
05394f39 | 158 | i915_gem_object_is_inactive(struct drm_i915_gem_object *obj) |
7d1c4804 | 159 | { |
9843877d | 160 | return i915_gem_obj_bound_any(obj) && !obj->active; |
7d1c4804 CW |
161 | } |
162 | ||
79e53945 JB |
163 | int |
164 | i915_gem_init_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 165 | struct drm_file *file) |
79e53945 | 166 | { |
93d18799 | 167 | struct drm_i915_private *dev_priv = dev->dev_private; |
79e53945 | 168 | struct drm_i915_gem_init *args = data; |
2021746e | 169 | |
7bb6fb8d DV |
170 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
171 | return -ENODEV; | |
172 | ||
2021746e CW |
173 | if (args->gtt_start >= args->gtt_end || |
174 | (args->gtt_end | args->gtt_start) & (PAGE_SIZE - 1)) | |
175 | return -EINVAL; | |
79e53945 | 176 | |
f534bc0b DV |
177 | /* GEM with user mode setting was never supported on ilk and later. */ |
178 | if (INTEL_INFO(dev)->gen >= 5) | |
179 | return -ENODEV; | |
180 | ||
79e53945 | 181 | mutex_lock(&dev->struct_mutex); |
d7e5008f BW |
182 | i915_gem_setup_global_gtt(dev, args->gtt_start, args->gtt_end, |
183 | args->gtt_end); | |
93d18799 | 184 | dev_priv->gtt.mappable_end = args->gtt_end; |
673a394b EA |
185 | mutex_unlock(&dev->struct_mutex); |
186 | ||
2021746e | 187 | return 0; |
673a394b EA |
188 | } |
189 | ||
5a125c3c EA |
190 | int |
191 | i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 192 | struct drm_file *file) |
5a125c3c | 193 | { |
73aa808f | 194 | struct drm_i915_private *dev_priv = dev->dev_private; |
5a125c3c | 195 | struct drm_i915_gem_get_aperture *args = data; |
6299f992 CW |
196 | struct drm_i915_gem_object *obj; |
197 | size_t pinned; | |
5a125c3c | 198 | |
6299f992 | 199 | pinned = 0; |
73aa808f | 200 | mutex_lock(&dev->struct_mutex); |
35c20a60 | 201 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) |
d7f46fc4 | 202 | if (i915_gem_obj_is_pinned(obj)) |
f343c5f6 | 203 | pinned += i915_gem_obj_ggtt_size(obj); |
73aa808f | 204 | mutex_unlock(&dev->struct_mutex); |
5a125c3c | 205 | |
853ba5d2 | 206 | args->aper_size = dev_priv->gtt.base.total; |
0206e353 | 207 | args->aper_available_size = args->aper_size - pinned; |
6299f992 | 208 | |
5a125c3c EA |
209 | return 0; |
210 | } | |
211 | ||
42dcedd4 CW |
212 | void *i915_gem_object_alloc(struct drm_device *dev) |
213 | { | |
214 | struct drm_i915_private *dev_priv = dev->dev_private; | |
fac15c10 | 215 | return kmem_cache_zalloc(dev_priv->slab, GFP_KERNEL); |
42dcedd4 CW |
216 | } |
217 | ||
218 | void i915_gem_object_free(struct drm_i915_gem_object *obj) | |
219 | { | |
220 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; | |
221 | kmem_cache_free(dev_priv->slab, obj); | |
222 | } | |
223 | ||
ff72145b DA |
224 | static int |
225 | i915_gem_create(struct drm_file *file, | |
226 | struct drm_device *dev, | |
227 | uint64_t size, | |
228 | uint32_t *handle_p) | |
673a394b | 229 | { |
05394f39 | 230 | struct drm_i915_gem_object *obj; |
a1a2d1d3 PP |
231 | int ret; |
232 | u32 handle; | |
673a394b | 233 | |
ff72145b | 234 | size = roundup(size, PAGE_SIZE); |
8ffc0246 CW |
235 | if (size == 0) |
236 | return -EINVAL; | |
673a394b EA |
237 | |
238 | /* Allocate the new object */ | |
ff72145b | 239 | obj = i915_gem_alloc_object(dev, size); |
673a394b EA |
240 | if (obj == NULL) |
241 | return -ENOMEM; | |
242 | ||
05394f39 | 243 | ret = drm_gem_handle_create(file, &obj->base, &handle); |
202f2fef | 244 | /* drop reference from allocate - handle holds it now */ |
d861e338 DV |
245 | drm_gem_object_unreference_unlocked(&obj->base); |
246 | if (ret) | |
247 | return ret; | |
202f2fef | 248 | |
ff72145b | 249 | *handle_p = handle; |
673a394b EA |
250 | return 0; |
251 | } | |
252 | ||
ff72145b DA |
253 | int |
254 | i915_gem_dumb_create(struct drm_file *file, | |
255 | struct drm_device *dev, | |
256 | struct drm_mode_create_dumb *args) | |
257 | { | |
258 | /* have to work out size/pitch and return them */ | |
de45eaf7 | 259 | args->pitch = ALIGN(args->width * DIV_ROUND_UP(args->bpp, 8), 64); |
ff72145b DA |
260 | args->size = args->pitch * args->height; |
261 | return i915_gem_create(file, dev, | |
262 | args->size, &args->handle); | |
263 | } | |
264 | ||
ff72145b DA |
265 | /** |
266 | * Creates a new mm object and returns a handle to it. | |
267 | */ | |
268 | int | |
269 | i915_gem_create_ioctl(struct drm_device *dev, void *data, | |
270 | struct drm_file *file) | |
271 | { | |
272 | struct drm_i915_gem_create *args = data; | |
63ed2cb2 | 273 | |
ff72145b DA |
274 | return i915_gem_create(file, dev, |
275 | args->size, &args->handle); | |
276 | } | |
277 | ||
8461d226 DV |
278 | static inline int |
279 | __copy_to_user_swizzled(char __user *cpu_vaddr, | |
280 | const char *gpu_vaddr, int gpu_offset, | |
281 | int length) | |
282 | { | |
283 | int ret, cpu_offset = 0; | |
284 | ||
285 | while (length > 0) { | |
286 | int cacheline_end = ALIGN(gpu_offset + 1, 64); | |
287 | int this_length = min(cacheline_end - gpu_offset, length); | |
288 | int swizzled_gpu_offset = gpu_offset ^ 64; | |
289 | ||
290 | ret = __copy_to_user(cpu_vaddr + cpu_offset, | |
291 | gpu_vaddr + swizzled_gpu_offset, | |
292 | this_length); | |
293 | if (ret) | |
294 | return ret + length; | |
295 | ||
296 | cpu_offset += this_length; | |
297 | gpu_offset += this_length; | |
298 | length -= this_length; | |
299 | } | |
300 | ||
301 | return 0; | |
302 | } | |
303 | ||
8c59967c | 304 | static inline int |
4f0c7cfb BW |
305 | __copy_from_user_swizzled(char *gpu_vaddr, int gpu_offset, |
306 | const char __user *cpu_vaddr, | |
8c59967c DV |
307 | int length) |
308 | { | |
309 | int ret, cpu_offset = 0; | |
310 | ||
311 | while (length > 0) { | |
312 | int cacheline_end = ALIGN(gpu_offset + 1, 64); | |
313 | int this_length = min(cacheline_end - gpu_offset, length); | |
314 | int swizzled_gpu_offset = gpu_offset ^ 64; | |
315 | ||
316 | ret = __copy_from_user(gpu_vaddr + swizzled_gpu_offset, | |
317 | cpu_vaddr + cpu_offset, | |
318 | this_length); | |
319 | if (ret) | |
320 | return ret + length; | |
321 | ||
322 | cpu_offset += this_length; | |
323 | gpu_offset += this_length; | |
324 | length -= this_length; | |
325 | } | |
326 | ||
327 | return 0; | |
328 | } | |
329 | ||
4c914c0c BV |
330 | /* |
331 | * Pins the specified object's pages and synchronizes the object with | |
332 | * GPU accesses. Sets needs_clflush to non-zero if the caller should | |
333 | * flush the object from the CPU cache. | |
334 | */ | |
335 | int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object *obj, | |
336 | int *needs_clflush) | |
337 | { | |
338 | int ret; | |
339 | ||
340 | *needs_clflush = 0; | |
341 | ||
342 | if (!obj->base.filp) | |
343 | return -EINVAL; | |
344 | ||
345 | if (!(obj->base.read_domains & I915_GEM_DOMAIN_CPU)) { | |
346 | /* If we're not in the cpu read domain, set ourself into the gtt | |
347 | * read domain and manually flush cachelines (if required). This | |
348 | * optimizes for the case when the gpu will dirty the data | |
349 | * anyway again before the next pread happens. */ | |
350 | *needs_clflush = !cpu_cache_is_coherent(obj->base.dev, | |
351 | obj->cache_level); | |
352 | ret = i915_gem_object_wait_rendering(obj, true); | |
353 | if (ret) | |
354 | return ret; | |
355 | } | |
356 | ||
357 | ret = i915_gem_object_get_pages(obj); | |
358 | if (ret) | |
359 | return ret; | |
360 | ||
361 | i915_gem_object_pin_pages(obj); | |
362 | ||
363 | return ret; | |
364 | } | |
365 | ||
d174bd64 DV |
366 | /* Per-page copy function for the shmem pread fastpath. |
367 | * Flushes invalid cachelines before reading the target if | |
368 | * needs_clflush is set. */ | |
eb01459f | 369 | static int |
d174bd64 DV |
370 | shmem_pread_fast(struct page *page, int shmem_page_offset, int page_length, |
371 | char __user *user_data, | |
372 | bool page_do_bit17_swizzling, bool needs_clflush) | |
373 | { | |
374 | char *vaddr; | |
375 | int ret; | |
376 | ||
e7e58eb5 | 377 | if (unlikely(page_do_bit17_swizzling)) |
d174bd64 DV |
378 | return -EINVAL; |
379 | ||
380 | vaddr = kmap_atomic(page); | |
381 | if (needs_clflush) | |
382 | drm_clflush_virt_range(vaddr + shmem_page_offset, | |
383 | page_length); | |
384 | ret = __copy_to_user_inatomic(user_data, | |
385 | vaddr + shmem_page_offset, | |
386 | page_length); | |
387 | kunmap_atomic(vaddr); | |
388 | ||
f60d7f0c | 389 | return ret ? -EFAULT : 0; |
d174bd64 DV |
390 | } |
391 | ||
23c18c71 DV |
392 | static void |
393 | shmem_clflush_swizzled_range(char *addr, unsigned long length, | |
394 | bool swizzled) | |
395 | { | |
e7e58eb5 | 396 | if (unlikely(swizzled)) { |
23c18c71 DV |
397 | unsigned long start = (unsigned long) addr; |
398 | unsigned long end = (unsigned long) addr + length; | |
399 | ||
400 | /* For swizzling simply ensure that we always flush both | |
401 | * channels. Lame, but simple and it works. Swizzled | |
402 | * pwrite/pread is far from a hotpath - current userspace | |
403 | * doesn't use it at all. */ | |
404 | start = round_down(start, 128); | |
405 | end = round_up(end, 128); | |
406 | ||
407 | drm_clflush_virt_range((void *)start, end - start); | |
408 | } else { | |
409 | drm_clflush_virt_range(addr, length); | |
410 | } | |
411 | ||
412 | } | |
413 | ||
d174bd64 DV |
414 | /* Only difference to the fast-path function is that this can handle bit17 |
415 | * and uses non-atomic copy and kmap functions. */ | |
416 | static int | |
417 | shmem_pread_slow(struct page *page, int shmem_page_offset, int page_length, | |
418 | char __user *user_data, | |
419 | bool page_do_bit17_swizzling, bool needs_clflush) | |
420 | { | |
421 | char *vaddr; | |
422 | int ret; | |
423 | ||
424 | vaddr = kmap(page); | |
425 | if (needs_clflush) | |
23c18c71 DV |
426 | shmem_clflush_swizzled_range(vaddr + shmem_page_offset, |
427 | page_length, | |
428 | page_do_bit17_swizzling); | |
d174bd64 DV |
429 | |
430 | if (page_do_bit17_swizzling) | |
431 | ret = __copy_to_user_swizzled(user_data, | |
432 | vaddr, shmem_page_offset, | |
433 | page_length); | |
434 | else | |
435 | ret = __copy_to_user(user_data, | |
436 | vaddr + shmem_page_offset, | |
437 | page_length); | |
438 | kunmap(page); | |
439 | ||
f60d7f0c | 440 | return ret ? - EFAULT : 0; |
d174bd64 DV |
441 | } |
442 | ||
eb01459f | 443 | static int |
dbf7bff0 DV |
444 | i915_gem_shmem_pread(struct drm_device *dev, |
445 | struct drm_i915_gem_object *obj, | |
446 | struct drm_i915_gem_pread *args, | |
447 | struct drm_file *file) | |
eb01459f | 448 | { |
8461d226 | 449 | char __user *user_data; |
eb01459f | 450 | ssize_t remain; |
8461d226 | 451 | loff_t offset; |
eb2c0c81 | 452 | int shmem_page_offset, page_length, ret = 0; |
8461d226 | 453 | int obj_do_bit17_swizzling, page_do_bit17_swizzling; |
96d79b52 | 454 | int prefaulted = 0; |
8489731c | 455 | int needs_clflush = 0; |
67d5a50c | 456 | struct sg_page_iter sg_iter; |
eb01459f | 457 | |
2bb4629a | 458 | user_data = to_user_ptr(args->data_ptr); |
eb01459f EA |
459 | remain = args->size; |
460 | ||
8461d226 | 461 | obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj); |
eb01459f | 462 | |
4c914c0c | 463 | ret = i915_gem_obj_prepare_shmem_read(obj, &needs_clflush); |
f60d7f0c CW |
464 | if (ret) |
465 | return ret; | |
466 | ||
8461d226 | 467 | offset = args->offset; |
eb01459f | 468 | |
67d5a50c ID |
469 | for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, |
470 | offset >> PAGE_SHIFT) { | |
2db76d7c | 471 | struct page *page = sg_page_iter_page(&sg_iter); |
9da3da66 CW |
472 | |
473 | if (remain <= 0) | |
474 | break; | |
475 | ||
eb01459f EA |
476 | /* Operation in this page |
477 | * | |
eb01459f | 478 | * shmem_page_offset = offset within page in shmem file |
eb01459f EA |
479 | * page_length = bytes to copy for this page |
480 | */ | |
c8cbbb8b | 481 | shmem_page_offset = offset_in_page(offset); |
eb01459f EA |
482 | page_length = remain; |
483 | if ((shmem_page_offset + page_length) > PAGE_SIZE) | |
484 | page_length = PAGE_SIZE - shmem_page_offset; | |
eb01459f | 485 | |
8461d226 DV |
486 | page_do_bit17_swizzling = obj_do_bit17_swizzling && |
487 | (page_to_phys(page) & (1 << 17)) != 0; | |
488 | ||
d174bd64 DV |
489 | ret = shmem_pread_fast(page, shmem_page_offset, page_length, |
490 | user_data, page_do_bit17_swizzling, | |
491 | needs_clflush); | |
492 | if (ret == 0) | |
493 | goto next_page; | |
dbf7bff0 | 494 | |
dbf7bff0 DV |
495 | mutex_unlock(&dev->struct_mutex); |
496 | ||
d330a953 | 497 | if (likely(!i915.prefault_disable) && !prefaulted) { |
f56f821f | 498 | ret = fault_in_multipages_writeable(user_data, remain); |
96d79b52 DV |
499 | /* Userspace is tricking us, but we've already clobbered |
500 | * its pages with the prefault and promised to write the | |
501 | * data up to the first fault. Hence ignore any errors | |
502 | * and just continue. */ | |
503 | (void)ret; | |
504 | prefaulted = 1; | |
505 | } | |
eb01459f | 506 | |
d174bd64 DV |
507 | ret = shmem_pread_slow(page, shmem_page_offset, page_length, |
508 | user_data, page_do_bit17_swizzling, | |
509 | needs_clflush); | |
eb01459f | 510 | |
dbf7bff0 | 511 | mutex_lock(&dev->struct_mutex); |
f60d7f0c | 512 | |
dbf7bff0 | 513 | next_page: |
e5281ccd | 514 | mark_page_accessed(page); |
e5281ccd | 515 | |
f60d7f0c | 516 | if (ret) |
8461d226 | 517 | goto out; |
8461d226 | 518 | |
eb01459f | 519 | remain -= page_length; |
8461d226 | 520 | user_data += page_length; |
eb01459f EA |
521 | offset += page_length; |
522 | } | |
523 | ||
4f27b75d | 524 | out: |
f60d7f0c CW |
525 | i915_gem_object_unpin_pages(obj); |
526 | ||
eb01459f EA |
527 | return ret; |
528 | } | |
529 | ||
673a394b EA |
530 | /** |
531 | * Reads data from the object referenced by handle. | |
532 | * | |
533 | * On error, the contents of *data are undefined. | |
534 | */ | |
535 | int | |
536 | i915_gem_pread_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 537 | struct drm_file *file) |
673a394b EA |
538 | { |
539 | struct drm_i915_gem_pread *args = data; | |
05394f39 | 540 | struct drm_i915_gem_object *obj; |
35b62a89 | 541 | int ret = 0; |
673a394b | 542 | |
51311d0a CW |
543 | if (args->size == 0) |
544 | return 0; | |
545 | ||
546 | if (!access_ok(VERIFY_WRITE, | |
2bb4629a | 547 | to_user_ptr(args->data_ptr), |
51311d0a CW |
548 | args->size)) |
549 | return -EFAULT; | |
550 | ||
4f27b75d | 551 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 552 | if (ret) |
4f27b75d | 553 | return ret; |
673a394b | 554 | |
05394f39 | 555 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 556 | if (&obj->base == NULL) { |
1d7cfea1 CW |
557 | ret = -ENOENT; |
558 | goto unlock; | |
4f27b75d | 559 | } |
673a394b | 560 | |
7dcd2499 | 561 | /* Bounds check source. */ |
05394f39 CW |
562 | if (args->offset > obj->base.size || |
563 | args->size > obj->base.size - args->offset) { | |
ce9d419d | 564 | ret = -EINVAL; |
35b62a89 | 565 | goto out; |
ce9d419d CW |
566 | } |
567 | ||
1286ff73 DV |
568 | /* prime objects have no backing filp to GEM pread/pwrite |
569 | * pages from. | |
570 | */ | |
571 | if (!obj->base.filp) { | |
572 | ret = -EINVAL; | |
573 | goto out; | |
574 | } | |
575 | ||
db53a302 CW |
576 | trace_i915_gem_object_pread(obj, args->offset, args->size); |
577 | ||
dbf7bff0 | 578 | ret = i915_gem_shmem_pread(dev, obj, args, file); |
673a394b | 579 | |
35b62a89 | 580 | out: |
05394f39 | 581 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 582 | unlock: |
4f27b75d | 583 | mutex_unlock(&dev->struct_mutex); |
eb01459f | 584 | return ret; |
673a394b EA |
585 | } |
586 | ||
0839ccb8 KP |
587 | /* This is the fast write path which cannot handle |
588 | * page faults in the source data | |
9b7530cc | 589 | */ |
0839ccb8 KP |
590 | |
591 | static inline int | |
592 | fast_user_write(struct io_mapping *mapping, | |
593 | loff_t page_base, int page_offset, | |
594 | char __user *user_data, | |
595 | int length) | |
9b7530cc | 596 | { |
4f0c7cfb BW |
597 | void __iomem *vaddr_atomic; |
598 | void *vaddr; | |
0839ccb8 | 599 | unsigned long unwritten; |
9b7530cc | 600 | |
3e4d3af5 | 601 | vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base); |
4f0c7cfb BW |
602 | /* We can use the cpu mem copy function because this is X86. */ |
603 | vaddr = (void __force*)vaddr_atomic + page_offset; | |
604 | unwritten = __copy_from_user_inatomic_nocache(vaddr, | |
0839ccb8 | 605 | user_data, length); |
3e4d3af5 | 606 | io_mapping_unmap_atomic(vaddr_atomic); |
fbd5a26d | 607 | return unwritten; |
0839ccb8 KP |
608 | } |
609 | ||
3de09aa3 EA |
610 | /** |
611 | * This is the fast pwrite path, where we copy the data directly from the | |
612 | * user into the GTT, uncached. | |
613 | */ | |
673a394b | 614 | static int |
05394f39 CW |
615 | i915_gem_gtt_pwrite_fast(struct drm_device *dev, |
616 | struct drm_i915_gem_object *obj, | |
3de09aa3 | 617 | struct drm_i915_gem_pwrite *args, |
05394f39 | 618 | struct drm_file *file) |
673a394b | 619 | { |
0839ccb8 | 620 | drm_i915_private_t *dev_priv = dev->dev_private; |
673a394b | 621 | ssize_t remain; |
0839ccb8 | 622 | loff_t offset, page_base; |
673a394b | 623 | char __user *user_data; |
935aaa69 DV |
624 | int page_offset, page_length, ret; |
625 | ||
1ec9e26d | 626 | ret = i915_gem_obj_ggtt_pin(obj, 0, PIN_MAPPABLE | PIN_NONBLOCK); |
935aaa69 DV |
627 | if (ret) |
628 | goto out; | |
629 | ||
630 | ret = i915_gem_object_set_to_gtt_domain(obj, true); | |
631 | if (ret) | |
632 | goto out_unpin; | |
633 | ||
634 | ret = i915_gem_object_put_fence(obj); | |
635 | if (ret) | |
636 | goto out_unpin; | |
673a394b | 637 | |
2bb4629a | 638 | user_data = to_user_ptr(args->data_ptr); |
673a394b | 639 | remain = args->size; |
673a394b | 640 | |
f343c5f6 | 641 | offset = i915_gem_obj_ggtt_offset(obj) + args->offset; |
673a394b EA |
642 | |
643 | while (remain > 0) { | |
644 | /* Operation in this page | |
645 | * | |
0839ccb8 KP |
646 | * page_base = page offset within aperture |
647 | * page_offset = offset within page | |
648 | * page_length = bytes to copy for this page | |
673a394b | 649 | */ |
c8cbbb8b CW |
650 | page_base = offset & PAGE_MASK; |
651 | page_offset = offset_in_page(offset); | |
0839ccb8 KP |
652 | page_length = remain; |
653 | if ((page_offset + remain) > PAGE_SIZE) | |
654 | page_length = PAGE_SIZE - page_offset; | |
655 | ||
0839ccb8 | 656 | /* If we get a fault while copying data, then (presumably) our |
3de09aa3 EA |
657 | * source page isn't available. Return the error and we'll |
658 | * retry in the slow path. | |
0839ccb8 | 659 | */ |
5d4545ae | 660 | if (fast_user_write(dev_priv->gtt.mappable, page_base, |
935aaa69 DV |
661 | page_offset, user_data, page_length)) { |
662 | ret = -EFAULT; | |
663 | goto out_unpin; | |
664 | } | |
673a394b | 665 | |
0839ccb8 KP |
666 | remain -= page_length; |
667 | user_data += page_length; | |
668 | offset += page_length; | |
673a394b | 669 | } |
673a394b | 670 | |
935aaa69 | 671 | out_unpin: |
d7f46fc4 | 672 | i915_gem_object_ggtt_unpin(obj); |
935aaa69 | 673 | out: |
3de09aa3 | 674 | return ret; |
673a394b EA |
675 | } |
676 | ||
d174bd64 DV |
677 | /* Per-page copy function for the shmem pwrite fastpath. |
678 | * Flushes invalid cachelines before writing to the target if | |
679 | * needs_clflush_before is set and flushes out any written cachelines after | |
680 | * writing if needs_clflush is set. */ | |
3043c60c | 681 | static int |
d174bd64 DV |
682 | shmem_pwrite_fast(struct page *page, int shmem_page_offset, int page_length, |
683 | char __user *user_data, | |
684 | bool page_do_bit17_swizzling, | |
685 | bool needs_clflush_before, | |
686 | bool needs_clflush_after) | |
673a394b | 687 | { |
d174bd64 | 688 | char *vaddr; |
673a394b | 689 | int ret; |
3de09aa3 | 690 | |
e7e58eb5 | 691 | if (unlikely(page_do_bit17_swizzling)) |
d174bd64 | 692 | return -EINVAL; |
3de09aa3 | 693 | |
d174bd64 DV |
694 | vaddr = kmap_atomic(page); |
695 | if (needs_clflush_before) | |
696 | drm_clflush_virt_range(vaddr + shmem_page_offset, | |
697 | page_length); | |
698 | ret = __copy_from_user_inatomic_nocache(vaddr + shmem_page_offset, | |
699 | user_data, | |
700 | page_length); | |
701 | if (needs_clflush_after) | |
702 | drm_clflush_virt_range(vaddr + shmem_page_offset, | |
703 | page_length); | |
704 | kunmap_atomic(vaddr); | |
3de09aa3 | 705 | |
755d2218 | 706 | return ret ? -EFAULT : 0; |
3de09aa3 EA |
707 | } |
708 | ||
d174bd64 DV |
709 | /* Only difference to the fast-path function is that this can handle bit17 |
710 | * and uses non-atomic copy and kmap functions. */ | |
3043c60c | 711 | static int |
d174bd64 DV |
712 | shmem_pwrite_slow(struct page *page, int shmem_page_offset, int page_length, |
713 | char __user *user_data, | |
714 | bool page_do_bit17_swizzling, | |
715 | bool needs_clflush_before, | |
716 | bool needs_clflush_after) | |
673a394b | 717 | { |
d174bd64 DV |
718 | char *vaddr; |
719 | int ret; | |
e5281ccd | 720 | |
d174bd64 | 721 | vaddr = kmap(page); |
e7e58eb5 | 722 | if (unlikely(needs_clflush_before || page_do_bit17_swizzling)) |
23c18c71 DV |
723 | shmem_clflush_swizzled_range(vaddr + shmem_page_offset, |
724 | page_length, | |
725 | page_do_bit17_swizzling); | |
d174bd64 DV |
726 | if (page_do_bit17_swizzling) |
727 | ret = __copy_from_user_swizzled(vaddr, shmem_page_offset, | |
e5281ccd CW |
728 | user_data, |
729 | page_length); | |
d174bd64 DV |
730 | else |
731 | ret = __copy_from_user(vaddr + shmem_page_offset, | |
732 | user_data, | |
733 | page_length); | |
734 | if (needs_clflush_after) | |
23c18c71 DV |
735 | shmem_clflush_swizzled_range(vaddr + shmem_page_offset, |
736 | page_length, | |
737 | page_do_bit17_swizzling); | |
d174bd64 | 738 | kunmap(page); |
40123c1f | 739 | |
755d2218 | 740 | return ret ? -EFAULT : 0; |
40123c1f EA |
741 | } |
742 | ||
40123c1f | 743 | static int |
e244a443 DV |
744 | i915_gem_shmem_pwrite(struct drm_device *dev, |
745 | struct drm_i915_gem_object *obj, | |
746 | struct drm_i915_gem_pwrite *args, | |
747 | struct drm_file *file) | |
40123c1f | 748 | { |
40123c1f | 749 | ssize_t remain; |
8c59967c DV |
750 | loff_t offset; |
751 | char __user *user_data; | |
eb2c0c81 | 752 | int shmem_page_offset, page_length, ret = 0; |
8c59967c | 753 | int obj_do_bit17_swizzling, page_do_bit17_swizzling; |
e244a443 | 754 | int hit_slowpath = 0; |
58642885 DV |
755 | int needs_clflush_after = 0; |
756 | int needs_clflush_before = 0; | |
67d5a50c | 757 | struct sg_page_iter sg_iter; |
40123c1f | 758 | |
2bb4629a | 759 | user_data = to_user_ptr(args->data_ptr); |
40123c1f EA |
760 | remain = args->size; |
761 | ||
8c59967c | 762 | obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj); |
40123c1f | 763 | |
58642885 DV |
764 | if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) { |
765 | /* If we're not in the cpu write domain, set ourself into the gtt | |
766 | * write domain and manually flush cachelines (if required). This | |
767 | * optimizes for the case when the gpu will use the data | |
768 | * right away and we therefore have to clflush anyway. */ | |
2c22569b | 769 | needs_clflush_after = cpu_write_needs_clflush(obj); |
23f54483 BW |
770 | ret = i915_gem_object_wait_rendering(obj, false); |
771 | if (ret) | |
772 | return ret; | |
58642885 | 773 | } |
c76ce038 CW |
774 | /* Same trick applies to invalidate partially written cachelines read |
775 | * before writing. */ | |
776 | if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0) | |
777 | needs_clflush_before = | |
778 | !cpu_cache_is_coherent(dev, obj->cache_level); | |
58642885 | 779 | |
755d2218 CW |
780 | ret = i915_gem_object_get_pages(obj); |
781 | if (ret) | |
782 | return ret; | |
783 | ||
784 | i915_gem_object_pin_pages(obj); | |
785 | ||
673a394b | 786 | offset = args->offset; |
05394f39 | 787 | obj->dirty = 1; |
673a394b | 788 | |
67d5a50c ID |
789 | for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, |
790 | offset >> PAGE_SHIFT) { | |
2db76d7c | 791 | struct page *page = sg_page_iter_page(&sg_iter); |
58642885 | 792 | int partial_cacheline_write; |
e5281ccd | 793 | |
9da3da66 CW |
794 | if (remain <= 0) |
795 | break; | |
796 | ||
40123c1f EA |
797 | /* Operation in this page |
798 | * | |
40123c1f | 799 | * shmem_page_offset = offset within page in shmem file |
40123c1f EA |
800 | * page_length = bytes to copy for this page |
801 | */ | |
c8cbbb8b | 802 | shmem_page_offset = offset_in_page(offset); |
40123c1f EA |
803 | |
804 | page_length = remain; | |
805 | if ((shmem_page_offset + page_length) > PAGE_SIZE) | |
806 | page_length = PAGE_SIZE - shmem_page_offset; | |
40123c1f | 807 | |
58642885 DV |
808 | /* If we don't overwrite a cacheline completely we need to be |
809 | * careful to have up-to-date data by first clflushing. Don't | |
810 | * overcomplicate things and flush the entire patch. */ | |
811 | partial_cacheline_write = needs_clflush_before && | |
812 | ((shmem_page_offset | page_length) | |
813 | & (boot_cpu_data.x86_clflush_size - 1)); | |
814 | ||
8c59967c DV |
815 | page_do_bit17_swizzling = obj_do_bit17_swizzling && |
816 | (page_to_phys(page) & (1 << 17)) != 0; | |
817 | ||
d174bd64 DV |
818 | ret = shmem_pwrite_fast(page, shmem_page_offset, page_length, |
819 | user_data, page_do_bit17_swizzling, | |
820 | partial_cacheline_write, | |
821 | needs_clflush_after); | |
822 | if (ret == 0) | |
823 | goto next_page; | |
e244a443 DV |
824 | |
825 | hit_slowpath = 1; | |
e244a443 | 826 | mutex_unlock(&dev->struct_mutex); |
d174bd64 DV |
827 | ret = shmem_pwrite_slow(page, shmem_page_offset, page_length, |
828 | user_data, page_do_bit17_swizzling, | |
829 | partial_cacheline_write, | |
830 | needs_clflush_after); | |
40123c1f | 831 | |
e244a443 | 832 | mutex_lock(&dev->struct_mutex); |
755d2218 | 833 | |
e244a443 | 834 | next_page: |
e5281ccd CW |
835 | set_page_dirty(page); |
836 | mark_page_accessed(page); | |
e5281ccd | 837 | |
755d2218 | 838 | if (ret) |
8c59967c | 839 | goto out; |
8c59967c | 840 | |
40123c1f | 841 | remain -= page_length; |
8c59967c | 842 | user_data += page_length; |
40123c1f | 843 | offset += page_length; |
673a394b EA |
844 | } |
845 | ||
fbd5a26d | 846 | out: |
755d2218 CW |
847 | i915_gem_object_unpin_pages(obj); |
848 | ||
e244a443 | 849 | if (hit_slowpath) { |
8dcf015e DV |
850 | /* |
851 | * Fixup: Flush cpu caches in case we didn't flush the dirty | |
852 | * cachelines in-line while writing and the object moved | |
853 | * out of the cpu write domain while we've dropped the lock. | |
854 | */ | |
855 | if (!needs_clflush_after && | |
856 | obj->base.write_domain != I915_GEM_DOMAIN_CPU) { | |
000433b6 CW |
857 | if (i915_gem_clflush_object(obj, obj->pin_display)) |
858 | i915_gem_chipset_flush(dev); | |
e244a443 | 859 | } |
8c59967c | 860 | } |
673a394b | 861 | |
58642885 | 862 | if (needs_clflush_after) |
e76e9aeb | 863 | i915_gem_chipset_flush(dev); |
58642885 | 864 | |
40123c1f | 865 | return ret; |
673a394b EA |
866 | } |
867 | ||
868 | /** | |
869 | * Writes data to the object referenced by handle. | |
870 | * | |
871 | * On error, the contents of the buffer that were to be modified are undefined. | |
872 | */ | |
873 | int | |
874 | i915_gem_pwrite_ioctl(struct drm_device *dev, void *data, | |
fbd5a26d | 875 | struct drm_file *file) |
673a394b EA |
876 | { |
877 | struct drm_i915_gem_pwrite *args = data; | |
05394f39 | 878 | struct drm_i915_gem_object *obj; |
51311d0a CW |
879 | int ret; |
880 | ||
881 | if (args->size == 0) | |
882 | return 0; | |
883 | ||
884 | if (!access_ok(VERIFY_READ, | |
2bb4629a | 885 | to_user_ptr(args->data_ptr), |
51311d0a CW |
886 | args->size)) |
887 | return -EFAULT; | |
888 | ||
d330a953 | 889 | if (likely(!i915.prefault_disable)) { |
0b74b508 XZ |
890 | ret = fault_in_multipages_readable(to_user_ptr(args->data_ptr), |
891 | args->size); | |
892 | if (ret) | |
893 | return -EFAULT; | |
894 | } | |
673a394b | 895 | |
fbd5a26d | 896 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 897 | if (ret) |
fbd5a26d | 898 | return ret; |
1d7cfea1 | 899 | |
05394f39 | 900 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 901 | if (&obj->base == NULL) { |
1d7cfea1 CW |
902 | ret = -ENOENT; |
903 | goto unlock; | |
fbd5a26d | 904 | } |
673a394b | 905 | |
7dcd2499 | 906 | /* Bounds check destination. */ |
05394f39 CW |
907 | if (args->offset > obj->base.size || |
908 | args->size > obj->base.size - args->offset) { | |
ce9d419d | 909 | ret = -EINVAL; |
35b62a89 | 910 | goto out; |
ce9d419d CW |
911 | } |
912 | ||
1286ff73 DV |
913 | /* prime objects have no backing filp to GEM pread/pwrite |
914 | * pages from. | |
915 | */ | |
916 | if (!obj->base.filp) { | |
917 | ret = -EINVAL; | |
918 | goto out; | |
919 | } | |
920 | ||
db53a302 CW |
921 | trace_i915_gem_object_pwrite(obj, args->offset, args->size); |
922 | ||
935aaa69 | 923 | ret = -EFAULT; |
673a394b EA |
924 | /* We can only do the GTT pwrite on untiled buffers, as otherwise |
925 | * it would end up going through the fenced access, and we'll get | |
926 | * different detiling behavior between reading and writing. | |
927 | * pread/pwrite currently are reading and writing from the CPU | |
928 | * perspective, requiring manual detiling by the client. | |
929 | */ | |
5c0480f2 | 930 | if (obj->phys_obj) { |
fbd5a26d | 931 | ret = i915_gem_phys_pwrite(dev, obj, args, file); |
5c0480f2 DV |
932 | goto out; |
933 | } | |
934 | ||
2c22569b CW |
935 | if (obj->tiling_mode == I915_TILING_NONE && |
936 | obj->base.write_domain != I915_GEM_DOMAIN_CPU && | |
937 | cpu_write_needs_clflush(obj)) { | |
fbd5a26d | 938 | ret = i915_gem_gtt_pwrite_fast(dev, obj, args, file); |
935aaa69 DV |
939 | /* Note that the gtt paths might fail with non-page-backed user |
940 | * pointers (e.g. gtt mappings when moving data between | |
941 | * textures). Fallback to the shmem path in that case. */ | |
fbd5a26d | 942 | } |
673a394b | 943 | |
86a1ee26 | 944 | if (ret == -EFAULT || ret == -ENOSPC) |
935aaa69 | 945 | ret = i915_gem_shmem_pwrite(dev, obj, args, file); |
5c0480f2 | 946 | |
35b62a89 | 947 | out: |
05394f39 | 948 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 949 | unlock: |
fbd5a26d | 950 | mutex_unlock(&dev->struct_mutex); |
673a394b EA |
951 | return ret; |
952 | } | |
953 | ||
b361237b | 954 | int |
33196ded | 955 | i915_gem_check_wedge(struct i915_gpu_error *error, |
b361237b CW |
956 | bool interruptible) |
957 | { | |
1f83fee0 | 958 | if (i915_reset_in_progress(error)) { |
b361237b CW |
959 | /* Non-interruptible callers can't handle -EAGAIN, hence return |
960 | * -EIO unconditionally for these. */ | |
961 | if (!interruptible) | |
962 | return -EIO; | |
963 | ||
1f83fee0 DV |
964 | /* Recovery complete, but the reset failed ... */ |
965 | if (i915_terminally_wedged(error)) | |
b361237b CW |
966 | return -EIO; |
967 | ||
968 | return -EAGAIN; | |
969 | } | |
970 | ||
971 | return 0; | |
972 | } | |
973 | ||
974 | /* | |
975 | * Compare seqno against outstanding lazy request. Emit a request if they are | |
976 | * equal. | |
977 | */ | |
978 | static int | |
979 | i915_gem_check_olr(struct intel_ring_buffer *ring, u32 seqno) | |
980 | { | |
981 | int ret; | |
982 | ||
983 | BUG_ON(!mutex_is_locked(&ring->dev->struct_mutex)); | |
984 | ||
985 | ret = 0; | |
1823521d | 986 | if (seqno == ring->outstanding_lazy_seqno) |
0025c077 | 987 | ret = i915_add_request(ring, NULL); |
b361237b CW |
988 | |
989 | return ret; | |
990 | } | |
991 | ||
094f9a54 CW |
992 | static void fake_irq(unsigned long data) |
993 | { | |
994 | wake_up_process((struct task_struct *)data); | |
995 | } | |
996 | ||
997 | static bool missed_irq(struct drm_i915_private *dev_priv, | |
998 | struct intel_ring_buffer *ring) | |
999 | { | |
1000 | return test_bit(ring->id, &dev_priv->gpu_error.missed_irq_rings); | |
1001 | } | |
1002 | ||
b29c19b6 CW |
1003 | static bool can_wait_boost(struct drm_i915_file_private *file_priv) |
1004 | { | |
1005 | if (file_priv == NULL) | |
1006 | return true; | |
1007 | ||
1008 | return !atomic_xchg(&file_priv->rps_wait_boost, true); | |
1009 | } | |
1010 | ||
b361237b CW |
1011 | /** |
1012 | * __wait_seqno - wait until execution of seqno has finished | |
1013 | * @ring: the ring expected to report seqno | |
1014 | * @seqno: duh! | |
f69061be | 1015 | * @reset_counter: reset sequence associated with the given seqno |
b361237b CW |
1016 | * @interruptible: do an interruptible wait (normally yes) |
1017 | * @timeout: in - how long to wait (NULL forever); out - how much time remaining | |
1018 | * | |
f69061be DV |
1019 | * Note: It is of utmost importance that the passed in seqno and reset_counter |
1020 | * values have been read by the caller in an smp safe manner. Where read-side | |
1021 | * locks are involved, it is sufficient to read the reset_counter before | |
1022 | * unlocking the lock that protects the seqno. For lockless tricks, the | |
1023 | * reset_counter _must_ be read before, and an appropriate smp_rmb must be | |
1024 | * inserted. | |
1025 | * | |
b361237b CW |
1026 | * Returns 0 if the seqno was found within the alloted time. Else returns the |
1027 | * errno with remaining time filled in timeout argument. | |
1028 | */ | |
1029 | static int __wait_seqno(struct intel_ring_buffer *ring, u32 seqno, | |
f69061be | 1030 | unsigned reset_counter, |
b29c19b6 CW |
1031 | bool interruptible, |
1032 | struct timespec *timeout, | |
1033 | struct drm_i915_file_private *file_priv) | |
b361237b | 1034 | { |
3d13ef2e DL |
1035 | struct drm_device *dev = ring->dev; |
1036 | drm_i915_private_t *dev_priv = dev->dev_private; | |
168c3f21 MK |
1037 | const bool irq_test_in_progress = |
1038 | ACCESS_ONCE(dev_priv->gpu_error.test_irq_rings) & intel_ring_flag(ring); | |
094f9a54 CW |
1039 | struct timespec before, now; |
1040 | DEFINE_WAIT(wait); | |
47e9766d | 1041 | unsigned long timeout_expire; |
b361237b CW |
1042 | int ret; |
1043 | ||
c67a470b PZ |
1044 | WARN(dev_priv->pc8.irqs_disabled, "IRQs disabled\n"); |
1045 | ||
b361237b CW |
1046 | if (i915_seqno_passed(ring->get_seqno(ring, true), seqno)) |
1047 | return 0; | |
1048 | ||
47e9766d | 1049 | timeout_expire = timeout ? jiffies + timespec_to_jiffies_timeout(timeout) : 0; |
b361237b | 1050 | |
3d13ef2e | 1051 | if (INTEL_INFO(dev)->gen >= 6 && can_wait_boost(file_priv)) { |
b29c19b6 CW |
1052 | gen6_rps_boost(dev_priv); |
1053 | if (file_priv) | |
1054 | mod_delayed_work(dev_priv->wq, | |
1055 | &file_priv->mm.idle_work, | |
1056 | msecs_to_jiffies(100)); | |
1057 | } | |
1058 | ||
168c3f21 | 1059 | if (!irq_test_in_progress && WARN_ON(!ring->irq_get(ring))) |
b361237b CW |
1060 | return -ENODEV; |
1061 | ||
094f9a54 CW |
1062 | /* Record current time in case interrupted by signal, or wedged */ |
1063 | trace_i915_gem_request_wait_begin(ring, seqno); | |
b361237b | 1064 | getrawmonotonic(&before); |
094f9a54 CW |
1065 | for (;;) { |
1066 | struct timer_list timer; | |
b361237b | 1067 | |
094f9a54 CW |
1068 | prepare_to_wait(&ring->irq_queue, &wait, |
1069 | interruptible ? TASK_INTERRUPTIBLE : TASK_UNINTERRUPTIBLE); | |
b361237b | 1070 | |
f69061be DV |
1071 | /* We need to check whether any gpu reset happened in between |
1072 | * the caller grabbing the seqno and now ... */ | |
094f9a54 CW |
1073 | if (reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter)) { |
1074 | /* ... but upgrade the -EAGAIN to an -EIO if the gpu | |
1075 | * is truely gone. */ | |
1076 | ret = i915_gem_check_wedge(&dev_priv->gpu_error, interruptible); | |
1077 | if (ret == 0) | |
1078 | ret = -EAGAIN; | |
1079 | break; | |
1080 | } | |
f69061be | 1081 | |
094f9a54 CW |
1082 | if (i915_seqno_passed(ring->get_seqno(ring, false), seqno)) { |
1083 | ret = 0; | |
1084 | break; | |
1085 | } | |
b361237b | 1086 | |
094f9a54 CW |
1087 | if (interruptible && signal_pending(current)) { |
1088 | ret = -ERESTARTSYS; | |
1089 | break; | |
1090 | } | |
1091 | ||
47e9766d | 1092 | if (timeout && time_after_eq(jiffies, timeout_expire)) { |
094f9a54 CW |
1093 | ret = -ETIME; |
1094 | break; | |
1095 | } | |
1096 | ||
1097 | timer.function = NULL; | |
1098 | if (timeout || missed_irq(dev_priv, ring)) { | |
47e9766d MK |
1099 | unsigned long expire; |
1100 | ||
094f9a54 | 1101 | setup_timer_on_stack(&timer, fake_irq, (unsigned long)current); |
47e9766d | 1102 | expire = missed_irq(dev_priv, ring) ? jiffies + 1 : timeout_expire; |
094f9a54 CW |
1103 | mod_timer(&timer, expire); |
1104 | } | |
1105 | ||
5035c275 | 1106 | io_schedule(); |
094f9a54 | 1107 | |
094f9a54 CW |
1108 | if (timer.function) { |
1109 | del_singleshot_timer_sync(&timer); | |
1110 | destroy_timer_on_stack(&timer); | |
1111 | } | |
1112 | } | |
b361237b | 1113 | getrawmonotonic(&now); |
094f9a54 | 1114 | trace_i915_gem_request_wait_end(ring, seqno); |
b361237b | 1115 | |
168c3f21 MK |
1116 | if (!irq_test_in_progress) |
1117 | ring->irq_put(ring); | |
094f9a54 CW |
1118 | |
1119 | finish_wait(&ring->irq_queue, &wait); | |
b361237b CW |
1120 | |
1121 | if (timeout) { | |
1122 | struct timespec sleep_time = timespec_sub(now, before); | |
1123 | *timeout = timespec_sub(*timeout, sleep_time); | |
4f42f4ef CW |
1124 | if (!timespec_valid(timeout)) /* i.e. negative time remains */ |
1125 | set_normalized_timespec(timeout, 0, 0); | |
b361237b CW |
1126 | } |
1127 | ||
094f9a54 | 1128 | return ret; |
b361237b CW |
1129 | } |
1130 | ||
1131 | /** | |
1132 | * Waits for a sequence number to be signaled, and cleans up the | |
1133 | * request and object lists appropriately for that event. | |
1134 | */ | |
1135 | int | |
1136 | i915_wait_seqno(struct intel_ring_buffer *ring, uint32_t seqno) | |
1137 | { | |
1138 | struct drm_device *dev = ring->dev; | |
1139 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1140 | bool interruptible = dev_priv->mm.interruptible; | |
1141 | int ret; | |
1142 | ||
1143 | BUG_ON(!mutex_is_locked(&dev->struct_mutex)); | |
1144 | BUG_ON(seqno == 0); | |
1145 | ||
33196ded | 1146 | ret = i915_gem_check_wedge(&dev_priv->gpu_error, interruptible); |
b361237b CW |
1147 | if (ret) |
1148 | return ret; | |
1149 | ||
1150 | ret = i915_gem_check_olr(ring, seqno); | |
1151 | if (ret) | |
1152 | return ret; | |
1153 | ||
f69061be DV |
1154 | return __wait_seqno(ring, seqno, |
1155 | atomic_read(&dev_priv->gpu_error.reset_counter), | |
b29c19b6 | 1156 | interruptible, NULL, NULL); |
b361237b CW |
1157 | } |
1158 | ||
d26e3af8 CW |
1159 | static int |
1160 | i915_gem_object_wait_rendering__tail(struct drm_i915_gem_object *obj, | |
1161 | struct intel_ring_buffer *ring) | |
1162 | { | |
1163 | i915_gem_retire_requests_ring(ring); | |
1164 | ||
1165 | /* Manually manage the write flush as we may have not yet | |
1166 | * retired the buffer. | |
1167 | * | |
1168 | * Note that the last_write_seqno is always the earlier of | |
1169 | * the two (read/write) seqno, so if we haved successfully waited, | |
1170 | * we know we have passed the last write. | |
1171 | */ | |
1172 | obj->last_write_seqno = 0; | |
1173 | obj->base.write_domain &= ~I915_GEM_GPU_DOMAINS; | |
1174 | ||
1175 | return 0; | |
1176 | } | |
1177 | ||
b361237b CW |
1178 | /** |
1179 | * Ensures that all rendering to the object has completed and the object is | |
1180 | * safe to unbind from the GTT or access from the CPU. | |
1181 | */ | |
1182 | static __must_check int | |
1183 | i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj, | |
1184 | bool readonly) | |
1185 | { | |
1186 | struct intel_ring_buffer *ring = obj->ring; | |
1187 | u32 seqno; | |
1188 | int ret; | |
1189 | ||
1190 | seqno = readonly ? obj->last_write_seqno : obj->last_read_seqno; | |
1191 | if (seqno == 0) | |
1192 | return 0; | |
1193 | ||
1194 | ret = i915_wait_seqno(ring, seqno); | |
1195 | if (ret) | |
1196 | return ret; | |
1197 | ||
d26e3af8 | 1198 | return i915_gem_object_wait_rendering__tail(obj, ring); |
b361237b CW |
1199 | } |
1200 | ||
3236f57a CW |
1201 | /* A nonblocking variant of the above wait. This is a highly dangerous routine |
1202 | * as the object state may change during this call. | |
1203 | */ | |
1204 | static __must_check int | |
1205 | i915_gem_object_wait_rendering__nonblocking(struct drm_i915_gem_object *obj, | |
6e4930f6 | 1206 | struct drm_i915_file_private *file_priv, |
3236f57a CW |
1207 | bool readonly) |
1208 | { | |
1209 | struct drm_device *dev = obj->base.dev; | |
1210 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1211 | struct intel_ring_buffer *ring = obj->ring; | |
f69061be | 1212 | unsigned reset_counter; |
3236f57a CW |
1213 | u32 seqno; |
1214 | int ret; | |
1215 | ||
1216 | BUG_ON(!mutex_is_locked(&dev->struct_mutex)); | |
1217 | BUG_ON(!dev_priv->mm.interruptible); | |
1218 | ||
1219 | seqno = readonly ? obj->last_write_seqno : obj->last_read_seqno; | |
1220 | if (seqno == 0) | |
1221 | return 0; | |
1222 | ||
33196ded | 1223 | ret = i915_gem_check_wedge(&dev_priv->gpu_error, true); |
3236f57a CW |
1224 | if (ret) |
1225 | return ret; | |
1226 | ||
1227 | ret = i915_gem_check_olr(ring, seqno); | |
1228 | if (ret) | |
1229 | return ret; | |
1230 | ||
f69061be | 1231 | reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter); |
3236f57a | 1232 | mutex_unlock(&dev->struct_mutex); |
6e4930f6 | 1233 | ret = __wait_seqno(ring, seqno, reset_counter, true, NULL, file_priv); |
3236f57a | 1234 | mutex_lock(&dev->struct_mutex); |
d26e3af8 CW |
1235 | if (ret) |
1236 | return ret; | |
3236f57a | 1237 | |
d26e3af8 | 1238 | return i915_gem_object_wait_rendering__tail(obj, ring); |
3236f57a CW |
1239 | } |
1240 | ||
673a394b | 1241 | /** |
2ef7eeaa EA |
1242 | * Called when user space prepares to use an object with the CPU, either |
1243 | * through the mmap ioctl's mapping or a GTT mapping. | |
673a394b EA |
1244 | */ |
1245 | int | |
1246 | i915_gem_set_domain_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 1247 | struct drm_file *file) |
673a394b EA |
1248 | { |
1249 | struct drm_i915_gem_set_domain *args = data; | |
05394f39 | 1250 | struct drm_i915_gem_object *obj; |
2ef7eeaa EA |
1251 | uint32_t read_domains = args->read_domains; |
1252 | uint32_t write_domain = args->write_domain; | |
673a394b EA |
1253 | int ret; |
1254 | ||
2ef7eeaa | 1255 | /* Only handle setting domains to types used by the CPU. */ |
21d509e3 | 1256 | if (write_domain & I915_GEM_GPU_DOMAINS) |
2ef7eeaa EA |
1257 | return -EINVAL; |
1258 | ||
21d509e3 | 1259 | if (read_domains & I915_GEM_GPU_DOMAINS) |
2ef7eeaa EA |
1260 | return -EINVAL; |
1261 | ||
1262 | /* Having something in the write domain implies it's in the read | |
1263 | * domain, and only that read domain. Enforce that in the request. | |
1264 | */ | |
1265 | if (write_domain != 0 && read_domains != write_domain) | |
1266 | return -EINVAL; | |
1267 | ||
76c1dec1 | 1268 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 1269 | if (ret) |
76c1dec1 | 1270 | return ret; |
1d7cfea1 | 1271 | |
05394f39 | 1272 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 1273 | if (&obj->base == NULL) { |
1d7cfea1 CW |
1274 | ret = -ENOENT; |
1275 | goto unlock; | |
76c1dec1 | 1276 | } |
673a394b | 1277 | |
3236f57a CW |
1278 | /* Try to flush the object off the GPU without holding the lock. |
1279 | * We will repeat the flush holding the lock in the normal manner | |
1280 | * to catch cases where we are gazumped. | |
1281 | */ | |
6e4930f6 CW |
1282 | ret = i915_gem_object_wait_rendering__nonblocking(obj, |
1283 | file->driver_priv, | |
1284 | !write_domain); | |
3236f57a CW |
1285 | if (ret) |
1286 | goto unref; | |
1287 | ||
2ef7eeaa EA |
1288 | if (read_domains & I915_GEM_DOMAIN_GTT) { |
1289 | ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0); | |
02354392 EA |
1290 | |
1291 | /* Silently promote "you're not bound, there was nothing to do" | |
1292 | * to success, since the client was just asking us to | |
1293 | * make sure everything was done. | |
1294 | */ | |
1295 | if (ret == -EINVAL) | |
1296 | ret = 0; | |
2ef7eeaa | 1297 | } else { |
e47c68e9 | 1298 | ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0); |
2ef7eeaa EA |
1299 | } |
1300 | ||
3236f57a | 1301 | unref: |
05394f39 | 1302 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 1303 | unlock: |
673a394b EA |
1304 | mutex_unlock(&dev->struct_mutex); |
1305 | return ret; | |
1306 | } | |
1307 | ||
1308 | /** | |
1309 | * Called when user space has done writes to this buffer | |
1310 | */ | |
1311 | int | |
1312 | i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 1313 | struct drm_file *file) |
673a394b EA |
1314 | { |
1315 | struct drm_i915_gem_sw_finish *args = data; | |
05394f39 | 1316 | struct drm_i915_gem_object *obj; |
673a394b EA |
1317 | int ret = 0; |
1318 | ||
76c1dec1 | 1319 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 1320 | if (ret) |
76c1dec1 | 1321 | return ret; |
1d7cfea1 | 1322 | |
05394f39 | 1323 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 1324 | if (&obj->base == NULL) { |
1d7cfea1 CW |
1325 | ret = -ENOENT; |
1326 | goto unlock; | |
673a394b EA |
1327 | } |
1328 | ||
673a394b | 1329 | /* Pinned buffers may be scanout, so flush the cache */ |
2c22569b CW |
1330 | if (obj->pin_display) |
1331 | i915_gem_object_flush_cpu_write_domain(obj, true); | |
e47c68e9 | 1332 | |
05394f39 | 1333 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 1334 | unlock: |
673a394b EA |
1335 | mutex_unlock(&dev->struct_mutex); |
1336 | return ret; | |
1337 | } | |
1338 | ||
1339 | /** | |
1340 | * Maps the contents of an object, returning the address it is mapped | |
1341 | * into. | |
1342 | * | |
1343 | * While the mapping holds a reference on the contents of the object, it doesn't | |
1344 | * imply a ref on the object itself. | |
1345 | */ | |
1346 | int | |
1347 | i915_gem_mmap_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 1348 | struct drm_file *file) |
673a394b EA |
1349 | { |
1350 | struct drm_i915_gem_mmap *args = data; | |
1351 | struct drm_gem_object *obj; | |
673a394b EA |
1352 | unsigned long addr; |
1353 | ||
05394f39 | 1354 | obj = drm_gem_object_lookup(dev, file, args->handle); |
673a394b | 1355 | if (obj == NULL) |
bf79cb91 | 1356 | return -ENOENT; |
673a394b | 1357 | |
1286ff73 DV |
1358 | /* prime objects have no backing filp to GEM mmap |
1359 | * pages from. | |
1360 | */ | |
1361 | if (!obj->filp) { | |
1362 | drm_gem_object_unreference_unlocked(obj); | |
1363 | return -EINVAL; | |
1364 | } | |
1365 | ||
6be5ceb0 | 1366 | addr = vm_mmap(obj->filp, 0, args->size, |
673a394b EA |
1367 | PROT_READ | PROT_WRITE, MAP_SHARED, |
1368 | args->offset); | |
bc9025bd | 1369 | drm_gem_object_unreference_unlocked(obj); |
673a394b EA |
1370 | if (IS_ERR((void *)addr)) |
1371 | return addr; | |
1372 | ||
1373 | args->addr_ptr = (uint64_t) addr; | |
1374 | ||
1375 | return 0; | |
1376 | } | |
1377 | ||
de151cf6 JB |
1378 | /** |
1379 | * i915_gem_fault - fault a page into the GTT | |
1380 | * vma: VMA in question | |
1381 | * vmf: fault info | |
1382 | * | |
1383 | * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped | |
1384 | * from userspace. The fault handler takes care of binding the object to | |
1385 | * the GTT (if needed), allocating and programming a fence register (again, | |
1386 | * only if needed based on whether the old reg is still valid or the object | |
1387 | * is tiled) and inserting a new PTE into the faulting process. | |
1388 | * | |
1389 | * Note that the faulting process may involve evicting existing objects | |
1390 | * from the GTT and/or fence registers to make room. So performance may | |
1391 | * suffer if the GTT working set is large or there are few fence registers | |
1392 | * left. | |
1393 | */ | |
1394 | int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf) | |
1395 | { | |
05394f39 CW |
1396 | struct drm_i915_gem_object *obj = to_intel_bo(vma->vm_private_data); |
1397 | struct drm_device *dev = obj->base.dev; | |
7d1c4804 | 1398 | drm_i915_private_t *dev_priv = dev->dev_private; |
de151cf6 JB |
1399 | pgoff_t page_offset; |
1400 | unsigned long pfn; | |
1401 | int ret = 0; | |
0f973f27 | 1402 | bool write = !!(vmf->flags & FAULT_FLAG_WRITE); |
de151cf6 | 1403 | |
f65c9168 PZ |
1404 | intel_runtime_pm_get(dev_priv); |
1405 | ||
de151cf6 JB |
1406 | /* We don't use vmf->pgoff since that has the fake offset */ |
1407 | page_offset = ((unsigned long)vmf->virtual_address - vma->vm_start) >> | |
1408 | PAGE_SHIFT; | |
1409 | ||
d9bc7e9f CW |
1410 | ret = i915_mutex_lock_interruptible(dev); |
1411 | if (ret) | |
1412 | goto out; | |
a00b10c3 | 1413 | |
db53a302 CW |
1414 | trace_i915_gem_object_fault(obj, page_offset, true, write); |
1415 | ||
6e4930f6 CW |
1416 | /* Try to flush the object off the GPU first without holding the lock. |
1417 | * Upon reacquiring the lock, we will perform our sanity checks and then | |
1418 | * repeat the flush holding the lock in the normal manner to catch cases | |
1419 | * where we are gazumped. | |
1420 | */ | |
1421 | ret = i915_gem_object_wait_rendering__nonblocking(obj, NULL, !write); | |
1422 | if (ret) | |
1423 | goto unlock; | |
1424 | ||
eb119bd6 CW |
1425 | /* Access to snoopable pages through the GTT is incoherent. */ |
1426 | if (obj->cache_level != I915_CACHE_NONE && !HAS_LLC(dev)) { | |
1427 | ret = -EINVAL; | |
1428 | goto unlock; | |
1429 | } | |
1430 | ||
d9bc7e9f | 1431 | /* Now bind it into the GTT if needed */ |
1ec9e26d | 1432 | ret = i915_gem_obj_ggtt_pin(obj, 0, PIN_MAPPABLE); |
c9839303 CW |
1433 | if (ret) |
1434 | goto unlock; | |
4a684a41 | 1435 | |
c9839303 CW |
1436 | ret = i915_gem_object_set_to_gtt_domain(obj, write); |
1437 | if (ret) | |
1438 | goto unpin; | |
74898d7e | 1439 | |
06d98131 | 1440 | ret = i915_gem_object_get_fence(obj); |
d9e86c0e | 1441 | if (ret) |
c9839303 | 1442 | goto unpin; |
7d1c4804 | 1443 | |
6299f992 CW |
1444 | obj->fault_mappable = true; |
1445 | ||
f343c5f6 BW |
1446 | pfn = dev_priv->gtt.mappable_base + i915_gem_obj_ggtt_offset(obj); |
1447 | pfn >>= PAGE_SHIFT; | |
1448 | pfn += page_offset; | |
de151cf6 JB |
1449 | |
1450 | /* Finally, remap it using the new GTT offset */ | |
1451 | ret = vm_insert_pfn(vma, (unsigned long)vmf->virtual_address, pfn); | |
c9839303 | 1452 | unpin: |
d7f46fc4 | 1453 | i915_gem_object_ggtt_unpin(obj); |
c715089f | 1454 | unlock: |
de151cf6 | 1455 | mutex_unlock(&dev->struct_mutex); |
d9bc7e9f | 1456 | out: |
de151cf6 | 1457 | switch (ret) { |
d9bc7e9f | 1458 | case -EIO: |
a9340cca DV |
1459 | /* If this -EIO is due to a gpu hang, give the reset code a |
1460 | * chance to clean up the mess. Otherwise return the proper | |
1461 | * SIGBUS. */ | |
f65c9168 PZ |
1462 | if (i915_terminally_wedged(&dev_priv->gpu_error)) { |
1463 | ret = VM_FAULT_SIGBUS; | |
1464 | break; | |
1465 | } | |
045e769a | 1466 | case -EAGAIN: |
571c608d DV |
1467 | /* |
1468 | * EAGAIN means the gpu is hung and we'll wait for the error | |
1469 | * handler to reset everything when re-faulting in | |
1470 | * i915_mutex_lock_interruptible. | |
d9bc7e9f | 1471 | */ |
c715089f CW |
1472 | case 0: |
1473 | case -ERESTARTSYS: | |
bed636ab | 1474 | case -EINTR: |
e79e0fe3 DR |
1475 | case -EBUSY: |
1476 | /* | |
1477 | * EBUSY is ok: this just means that another thread | |
1478 | * already did the job. | |
1479 | */ | |
f65c9168 PZ |
1480 | ret = VM_FAULT_NOPAGE; |
1481 | break; | |
de151cf6 | 1482 | case -ENOMEM: |
f65c9168 PZ |
1483 | ret = VM_FAULT_OOM; |
1484 | break; | |
a7c2e1aa | 1485 | case -ENOSPC: |
45d67817 | 1486 | case -EFAULT: |
f65c9168 PZ |
1487 | ret = VM_FAULT_SIGBUS; |
1488 | break; | |
de151cf6 | 1489 | default: |
a7c2e1aa | 1490 | WARN_ONCE(ret, "unhandled error in i915_gem_fault: %i\n", ret); |
f65c9168 PZ |
1491 | ret = VM_FAULT_SIGBUS; |
1492 | break; | |
de151cf6 | 1493 | } |
f65c9168 PZ |
1494 | |
1495 | intel_runtime_pm_put(dev_priv); | |
1496 | return ret; | |
de151cf6 JB |
1497 | } |
1498 | ||
48018a57 PZ |
1499 | void i915_gem_release_all_mmaps(struct drm_i915_private *dev_priv) |
1500 | { | |
1501 | struct i915_vma *vma; | |
1502 | ||
1503 | /* | |
1504 | * Only the global gtt is relevant for gtt memory mappings, so restrict | |
1505 | * list traversal to objects bound into the global address space. Note | |
1506 | * that the active list should be empty, but better safe than sorry. | |
1507 | */ | |
1508 | WARN_ON(!list_empty(&dev_priv->gtt.base.active_list)); | |
1509 | list_for_each_entry(vma, &dev_priv->gtt.base.active_list, mm_list) | |
1510 | i915_gem_release_mmap(vma->obj); | |
1511 | list_for_each_entry(vma, &dev_priv->gtt.base.inactive_list, mm_list) | |
1512 | i915_gem_release_mmap(vma->obj); | |
1513 | } | |
1514 | ||
901782b2 CW |
1515 | /** |
1516 | * i915_gem_release_mmap - remove physical page mappings | |
1517 | * @obj: obj in question | |
1518 | * | |
af901ca1 | 1519 | * Preserve the reservation of the mmapping with the DRM core code, but |
901782b2 CW |
1520 | * relinquish ownership of the pages back to the system. |
1521 | * | |
1522 | * It is vital that we remove the page mapping if we have mapped a tiled | |
1523 | * object through the GTT and then lose the fence register due to | |
1524 | * resource pressure. Similarly if the object has been moved out of the | |
1525 | * aperture, than pages mapped into userspace must be revoked. Removing the | |
1526 | * mapping will then trigger a page fault on the next user access, allowing | |
1527 | * fixup by i915_gem_fault(). | |
1528 | */ | |
d05ca301 | 1529 | void |
05394f39 | 1530 | i915_gem_release_mmap(struct drm_i915_gem_object *obj) |
901782b2 | 1531 | { |
6299f992 CW |
1532 | if (!obj->fault_mappable) |
1533 | return; | |
901782b2 | 1534 | |
51335df9 | 1535 | drm_vma_node_unmap(&obj->base.vma_node, obj->base.dev->dev_mapping); |
6299f992 | 1536 | obj->fault_mappable = false; |
901782b2 CW |
1537 | } |
1538 | ||
0fa87796 | 1539 | uint32_t |
e28f8711 | 1540 | i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode) |
92b88aeb | 1541 | { |
e28f8711 | 1542 | uint32_t gtt_size; |
92b88aeb CW |
1543 | |
1544 | if (INTEL_INFO(dev)->gen >= 4 || | |
e28f8711 CW |
1545 | tiling_mode == I915_TILING_NONE) |
1546 | return size; | |
92b88aeb CW |
1547 | |
1548 | /* Previous chips need a power-of-two fence region when tiling */ | |
1549 | if (INTEL_INFO(dev)->gen == 3) | |
e28f8711 | 1550 | gtt_size = 1024*1024; |
92b88aeb | 1551 | else |
e28f8711 | 1552 | gtt_size = 512*1024; |
92b88aeb | 1553 | |
e28f8711 CW |
1554 | while (gtt_size < size) |
1555 | gtt_size <<= 1; | |
92b88aeb | 1556 | |
e28f8711 | 1557 | return gtt_size; |
92b88aeb CW |
1558 | } |
1559 | ||
de151cf6 JB |
1560 | /** |
1561 | * i915_gem_get_gtt_alignment - return required GTT alignment for an object | |
1562 | * @obj: object to check | |
1563 | * | |
1564 | * Return the required GTT alignment for an object, taking into account | |
5e783301 | 1565 | * potential fence register mapping. |
de151cf6 | 1566 | */ |
d865110c ID |
1567 | uint32_t |
1568 | i915_gem_get_gtt_alignment(struct drm_device *dev, uint32_t size, | |
1569 | int tiling_mode, bool fenced) | |
de151cf6 | 1570 | { |
de151cf6 JB |
1571 | /* |
1572 | * Minimum alignment is 4k (GTT page size), but might be greater | |
1573 | * if a fence register is needed for the object. | |
1574 | */ | |
d865110c | 1575 | if (INTEL_INFO(dev)->gen >= 4 || (!fenced && IS_G33(dev)) || |
e28f8711 | 1576 | tiling_mode == I915_TILING_NONE) |
de151cf6 JB |
1577 | return 4096; |
1578 | ||
a00b10c3 CW |
1579 | /* |
1580 | * Previous chips need to be aligned to the size of the smallest | |
1581 | * fence register that can contain the object. | |
1582 | */ | |
e28f8711 | 1583 | return i915_gem_get_gtt_size(dev, size, tiling_mode); |
a00b10c3 CW |
1584 | } |
1585 | ||
d8cb5086 CW |
1586 | static int i915_gem_object_create_mmap_offset(struct drm_i915_gem_object *obj) |
1587 | { | |
1588 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; | |
1589 | int ret; | |
1590 | ||
0de23977 | 1591 | if (drm_vma_node_has_offset(&obj->base.vma_node)) |
d8cb5086 CW |
1592 | return 0; |
1593 | ||
da494d7c DV |
1594 | dev_priv->mm.shrinker_no_lock_stealing = true; |
1595 | ||
d8cb5086 CW |
1596 | ret = drm_gem_create_mmap_offset(&obj->base); |
1597 | if (ret != -ENOSPC) | |
da494d7c | 1598 | goto out; |
d8cb5086 CW |
1599 | |
1600 | /* Badly fragmented mmap space? The only way we can recover | |
1601 | * space is by destroying unwanted objects. We can't randomly release | |
1602 | * mmap_offsets as userspace expects them to be persistent for the | |
1603 | * lifetime of the objects. The closest we can is to release the | |
1604 | * offsets on purgeable objects by truncating it and marking it purged, | |
1605 | * which prevents userspace from ever using that object again. | |
1606 | */ | |
1607 | i915_gem_purge(dev_priv, obj->base.size >> PAGE_SHIFT); | |
1608 | ret = drm_gem_create_mmap_offset(&obj->base); | |
1609 | if (ret != -ENOSPC) | |
da494d7c | 1610 | goto out; |
d8cb5086 CW |
1611 | |
1612 | i915_gem_shrink_all(dev_priv); | |
da494d7c DV |
1613 | ret = drm_gem_create_mmap_offset(&obj->base); |
1614 | out: | |
1615 | dev_priv->mm.shrinker_no_lock_stealing = false; | |
1616 | ||
1617 | return ret; | |
d8cb5086 CW |
1618 | } |
1619 | ||
1620 | static void i915_gem_object_free_mmap_offset(struct drm_i915_gem_object *obj) | |
1621 | { | |
d8cb5086 CW |
1622 | drm_gem_free_mmap_offset(&obj->base); |
1623 | } | |
1624 | ||
de151cf6 | 1625 | int |
ff72145b DA |
1626 | i915_gem_mmap_gtt(struct drm_file *file, |
1627 | struct drm_device *dev, | |
1628 | uint32_t handle, | |
1629 | uint64_t *offset) | |
de151cf6 | 1630 | { |
da761a6e | 1631 | struct drm_i915_private *dev_priv = dev->dev_private; |
05394f39 | 1632 | struct drm_i915_gem_object *obj; |
de151cf6 JB |
1633 | int ret; |
1634 | ||
76c1dec1 | 1635 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 1636 | if (ret) |
76c1dec1 | 1637 | return ret; |
de151cf6 | 1638 | |
ff72145b | 1639 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle)); |
c8725226 | 1640 | if (&obj->base == NULL) { |
1d7cfea1 CW |
1641 | ret = -ENOENT; |
1642 | goto unlock; | |
1643 | } | |
de151cf6 | 1644 | |
5d4545ae | 1645 | if (obj->base.size > dev_priv->gtt.mappable_end) { |
da761a6e | 1646 | ret = -E2BIG; |
ff56b0bc | 1647 | goto out; |
da761a6e CW |
1648 | } |
1649 | ||
05394f39 | 1650 | if (obj->madv != I915_MADV_WILLNEED) { |
bd9b6a4e | 1651 | DRM_DEBUG("Attempting to mmap a purgeable buffer\n"); |
8c99e57d | 1652 | ret = -EFAULT; |
1d7cfea1 | 1653 | goto out; |
ab18282d CW |
1654 | } |
1655 | ||
d8cb5086 CW |
1656 | ret = i915_gem_object_create_mmap_offset(obj); |
1657 | if (ret) | |
1658 | goto out; | |
de151cf6 | 1659 | |
0de23977 | 1660 | *offset = drm_vma_node_offset_addr(&obj->base.vma_node); |
de151cf6 | 1661 | |
1d7cfea1 | 1662 | out: |
05394f39 | 1663 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 1664 | unlock: |
de151cf6 | 1665 | mutex_unlock(&dev->struct_mutex); |
1d7cfea1 | 1666 | return ret; |
de151cf6 JB |
1667 | } |
1668 | ||
ff72145b DA |
1669 | /** |
1670 | * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing | |
1671 | * @dev: DRM device | |
1672 | * @data: GTT mapping ioctl data | |
1673 | * @file: GEM object info | |
1674 | * | |
1675 | * Simply returns the fake offset to userspace so it can mmap it. | |
1676 | * The mmap call will end up in drm_gem_mmap(), which will set things | |
1677 | * up so we can get faults in the handler above. | |
1678 | * | |
1679 | * The fault handler will take care of binding the object into the GTT | |
1680 | * (since it may have been evicted to make room for something), allocating | |
1681 | * a fence register, and mapping the appropriate aperture address into | |
1682 | * userspace. | |
1683 | */ | |
1684 | int | |
1685 | i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data, | |
1686 | struct drm_file *file) | |
1687 | { | |
1688 | struct drm_i915_gem_mmap_gtt *args = data; | |
1689 | ||
ff72145b DA |
1690 | return i915_gem_mmap_gtt(file, dev, args->handle, &args->offset); |
1691 | } | |
1692 | ||
225067ee DV |
1693 | /* Immediately discard the backing storage */ |
1694 | static void | |
1695 | i915_gem_object_truncate(struct drm_i915_gem_object *obj) | |
e5281ccd | 1696 | { |
e5281ccd | 1697 | struct inode *inode; |
e5281ccd | 1698 | |
4d6294bf | 1699 | i915_gem_object_free_mmap_offset(obj); |
1286ff73 | 1700 | |
4d6294bf CW |
1701 | if (obj->base.filp == NULL) |
1702 | return; | |
e5281ccd | 1703 | |
225067ee DV |
1704 | /* Our goal here is to return as much of the memory as |
1705 | * is possible back to the system as we are called from OOM. | |
1706 | * To do this we must instruct the shmfs to drop all of its | |
1707 | * backing pages, *now*. | |
1708 | */ | |
496ad9aa | 1709 | inode = file_inode(obj->base.filp); |
225067ee | 1710 | shmem_truncate_range(inode, 0, (loff_t)-1); |
e5281ccd | 1711 | |
225067ee DV |
1712 | obj->madv = __I915_MADV_PURGED; |
1713 | } | |
e5281ccd | 1714 | |
225067ee DV |
1715 | static inline int |
1716 | i915_gem_object_is_purgeable(struct drm_i915_gem_object *obj) | |
1717 | { | |
1718 | return obj->madv == I915_MADV_DONTNEED; | |
e5281ccd CW |
1719 | } |
1720 | ||
5cdf5881 | 1721 | static void |
05394f39 | 1722 | i915_gem_object_put_pages_gtt(struct drm_i915_gem_object *obj) |
673a394b | 1723 | { |
90797e6d ID |
1724 | struct sg_page_iter sg_iter; |
1725 | int ret; | |
1286ff73 | 1726 | |
05394f39 | 1727 | BUG_ON(obj->madv == __I915_MADV_PURGED); |
673a394b | 1728 | |
6c085a72 CW |
1729 | ret = i915_gem_object_set_to_cpu_domain(obj, true); |
1730 | if (ret) { | |
1731 | /* In the event of a disaster, abandon all caches and | |
1732 | * hope for the best. | |
1733 | */ | |
1734 | WARN_ON(ret != -EIO); | |
2c22569b | 1735 | i915_gem_clflush_object(obj, true); |
6c085a72 CW |
1736 | obj->base.read_domains = obj->base.write_domain = I915_GEM_DOMAIN_CPU; |
1737 | } | |
1738 | ||
6dacfd2f | 1739 | if (i915_gem_object_needs_bit17_swizzle(obj)) |
280b713b EA |
1740 | i915_gem_object_save_bit_17_swizzle(obj); |
1741 | ||
05394f39 CW |
1742 | if (obj->madv == I915_MADV_DONTNEED) |
1743 | obj->dirty = 0; | |
3ef94daa | 1744 | |
90797e6d | 1745 | for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, 0) { |
2db76d7c | 1746 | struct page *page = sg_page_iter_page(&sg_iter); |
9da3da66 | 1747 | |
05394f39 | 1748 | if (obj->dirty) |
9da3da66 | 1749 | set_page_dirty(page); |
3ef94daa | 1750 | |
05394f39 | 1751 | if (obj->madv == I915_MADV_WILLNEED) |
9da3da66 | 1752 | mark_page_accessed(page); |
3ef94daa | 1753 | |
9da3da66 | 1754 | page_cache_release(page); |
3ef94daa | 1755 | } |
05394f39 | 1756 | obj->dirty = 0; |
673a394b | 1757 | |
9da3da66 CW |
1758 | sg_free_table(obj->pages); |
1759 | kfree(obj->pages); | |
37e680a1 | 1760 | } |
6c085a72 | 1761 | |
dd624afd | 1762 | int |
37e680a1 CW |
1763 | i915_gem_object_put_pages(struct drm_i915_gem_object *obj) |
1764 | { | |
1765 | const struct drm_i915_gem_object_ops *ops = obj->ops; | |
1766 | ||
2f745ad3 | 1767 | if (obj->pages == NULL) |
37e680a1 CW |
1768 | return 0; |
1769 | ||
a5570178 CW |
1770 | if (obj->pages_pin_count) |
1771 | return -EBUSY; | |
1772 | ||
9843877d | 1773 | BUG_ON(i915_gem_obj_bound_any(obj)); |
3e123027 | 1774 | |
a2165e31 CW |
1775 | /* ->put_pages might need to allocate memory for the bit17 swizzle |
1776 | * array, hence protect them from being reaped by removing them from gtt | |
1777 | * lists early. */ | |
35c20a60 | 1778 | list_del(&obj->global_list); |
a2165e31 | 1779 | |
37e680a1 | 1780 | ops->put_pages(obj); |
05394f39 | 1781 | obj->pages = NULL; |
37e680a1 | 1782 | |
6c085a72 CW |
1783 | if (i915_gem_object_is_purgeable(obj)) |
1784 | i915_gem_object_truncate(obj); | |
1785 | ||
1786 | return 0; | |
1787 | } | |
1788 | ||
d9973b43 | 1789 | static unsigned long |
93927ca5 DV |
1790 | __i915_gem_shrink(struct drm_i915_private *dev_priv, long target, |
1791 | bool purgeable_only) | |
6c085a72 | 1792 | { |
57094f82 | 1793 | struct list_head still_bound_list; |
6c085a72 | 1794 | struct drm_i915_gem_object *obj, *next; |
d9973b43 | 1795 | unsigned long count = 0; |
6c085a72 CW |
1796 | |
1797 | list_for_each_entry_safe(obj, next, | |
1798 | &dev_priv->mm.unbound_list, | |
35c20a60 | 1799 | global_list) { |
93927ca5 | 1800 | if ((i915_gem_object_is_purgeable(obj) || !purgeable_only) && |
37e680a1 | 1801 | i915_gem_object_put_pages(obj) == 0) { |
6c085a72 CW |
1802 | count += obj->base.size >> PAGE_SHIFT; |
1803 | if (count >= target) | |
1804 | return count; | |
1805 | } | |
1806 | } | |
1807 | ||
57094f82 CW |
1808 | /* |
1809 | * As we may completely rewrite the bound list whilst unbinding | |
1810 | * (due to retiring requests) we have to strictly process only | |
1811 | * one element of the list at the time, and recheck the list | |
1812 | * on every iteration. | |
1813 | */ | |
1814 | INIT_LIST_HEAD(&still_bound_list); | |
1815 | while (count < target && !list_empty(&dev_priv->mm.bound_list)) { | |
07fe0b12 | 1816 | struct i915_vma *vma, *v; |
80dcfdbd | 1817 | |
57094f82 CW |
1818 | obj = list_first_entry(&dev_priv->mm.bound_list, |
1819 | typeof(*obj), global_list); | |
1820 | list_move_tail(&obj->global_list, &still_bound_list); | |
1821 | ||
80dcfdbd BW |
1822 | if (!i915_gem_object_is_purgeable(obj) && purgeable_only) |
1823 | continue; | |
1824 | ||
57094f82 CW |
1825 | /* |
1826 | * Hold a reference whilst we unbind this object, as we may | |
1827 | * end up waiting for and retiring requests. This might | |
1828 | * release the final reference (held by the active list) | |
1829 | * and result in the object being freed from under us. | |
1830 | * in this object being freed. | |
1831 | * | |
1832 | * Note 1: Shrinking the bound list is special since only active | |
1833 | * (and hence bound objects) can contain such limbo objects, so | |
1834 | * we don't need special tricks for shrinking the unbound list. | |
1835 | * The only other place where we have to be careful with active | |
1836 | * objects suddenly disappearing due to retiring requests is the | |
1837 | * eviction code. | |
1838 | * | |
1839 | * Note 2: Even though the bound list doesn't hold a reference | |
1840 | * to the object we can safely grab one here: The final object | |
1841 | * unreferencing and the bound_list are both protected by the | |
1842 | * dev->struct_mutex and so we won't ever be able to observe an | |
1843 | * object on the bound_list with a reference count equals 0. | |
1844 | */ | |
1845 | drm_gem_object_reference(&obj->base); | |
1846 | ||
07fe0b12 BW |
1847 | list_for_each_entry_safe(vma, v, &obj->vma_list, vma_link) |
1848 | if (i915_vma_unbind(vma)) | |
1849 | break; | |
80dcfdbd | 1850 | |
57094f82 | 1851 | if (i915_gem_object_put_pages(obj) == 0) |
6c085a72 | 1852 | count += obj->base.size >> PAGE_SHIFT; |
57094f82 CW |
1853 | |
1854 | drm_gem_object_unreference(&obj->base); | |
6c085a72 | 1855 | } |
57094f82 | 1856 | list_splice(&still_bound_list, &dev_priv->mm.bound_list); |
6c085a72 CW |
1857 | |
1858 | return count; | |
1859 | } | |
1860 | ||
d9973b43 | 1861 | static unsigned long |
93927ca5 DV |
1862 | i915_gem_purge(struct drm_i915_private *dev_priv, long target) |
1863 | { | |
1864 | return __i915_gem_shrink(dev_priv, target, true); | |
1865 | } | |
1866 | ||
d9973b43 | 1867 | static unsigned long |
6c085a72 CW |
1868 | i915_gem_shrink_all(struct drm_i915_private *dev_priv) |
1869 | { | |
1870 | struct drm_i915_gem_object *obj, *next; | |
7dc19d5a | 1871 | long freed = 0; |
6c085a72 CW |
1872 | |
1873 | i915_gem_evict_everything(dev_priv->dev); | |
1874 | ||
35c20a60 | 1875 | list_for_each_entry_safe(obj, next, &dev_priv->mm.unbound_list, |
7dc19d5a | 1876 | global_list) { |
d9973b43 | 1877 | if (i915_gem_object_put_pages(obj) == 0) |
7dc19d5a | 1878 | freed += obj->base.size >> PAGE_SHIFT; |
7dc19d5a DC |
1879 | } |
1880 | return freed; | |
225067ee DV |
1881 | } |
1882 | ||
37e680a1 | 1883 | static int |
6c085a72 | 1884 | i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj) |
e5281ccd | 1885 | { |
6c085a72 | 1886 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
e5281ccd CW |
1887 | int page_count, i; |
1888 | struct address_space *mapping; | |
9da3da66 CW |
1889 | struct sg_table *st; |
1890 | struct scatterlist *sg; | |
90797e6d | 1891 | struct sg_page_iter sg_iter; |
e5281ccd | 1892 | struct page *page; |
90797e6d | 1893 | unsigned long last_pfn = 0; /* suppress gcc warning */ |
6c085a72 | 1894 | gfp_t gfp; |
e5281ccd | 1895 | |
6c085a72 CW |
1896 | /* Assert that the object is not currently in any GPU domain. As it |
1897 | * wasn't in the GTT, there shouldn't be any way it could have been in | |
1898 | * a GPU cache | |
1899 | */ | |
1900 | BUG_ON(obj->base.read_domains & I915_GEM_GPU_DOMAINS); | |
1901 | BUG_ON(obj->base.write_domain & I915_GEM_GPU_DOMAINS); | |
1902 | ||
9da3da66 CW |
1903 | st = kmalloc(sizeof(*st), GFP_KERNEL); |
1904 | if (st == NULL) | |
1905 | return -ENOMEM; | |
1906 | ||
05394f39 | 1907 | page_count = obj->base.size / PAGE_SIZE; |
9da3da66 | 1908 | if (sg_alloc_table(st, page_count, GFP_KERNEL)) { |
9da3da66 | 1909 | kfree(st); |
e5281ccd | 1910 | return -ENOMEM; |
9da3da66 | 1911 | } |
e5281ccd | 1912 | |
9da3da66 CW |
1913 | /* Get the list of pages out of our struct file. They'll be pinned |
1914 | * at this point until we release them. | |
1915 | * | |
1916 | * Fail silently without starting the shrinker | |
1917 | */ | |
496ad9aa | 1918 | mapping = file_inode(obj->base.filp)->i_mapping; |
6c085a72 | 1919 | gfp = mapping_gfp_mask(mapping); |
caf49191 | 1920 | gfp |= __GFP_NORETRY | __GFP_NOWARN | __GFP_NO_KSWAPD; |
6c085a72 | 1921 | gfp &= ~(__GFP_IO | __GFP_WAIT); |
90797e6d ID |
1922 | sg = st->sgl; |
1923 | st->nents = 0; | |
1924 | for (i = 0; i < page_count; i++) { | |
6c085a72 CW |
1925 | page = shmem_read_mapping_page_gfp(mapping, i, gfp); |
1926 | if (IS_ERR(page)) { | |
1927 | i915_gem_purge(dev_priv, page_count); | |
1928 | page = shmem_read_mapping_page_gfp(mapping, i, gfp); | |
1929 | } | |
1930 | if (IS_ERR(page)) { | |
1931 | /* We've tried hard to allocate the memory by reaping | |
1932 | * our own buffer, now let the real VM do its job and | |
1933 | * go down in flames if truly OOM. | |
1934 | */ | |
caf49191 | 1935 | gfp &= ~(__GFP_NORETRY | __GFP_NOWARN | __GFP_NO_KSWAPD); |
6c085a72 CW |
1936 | gfp |= __GFP_IO | __GFP_WAIT; |
1937 | ||
1938 | i915_gem_shrink_all(dev_priv); | |
1939 | page = shmem_read_mapping_page_gfp(mapping, i, gfp); | |
1940 | if (IS_ERR(page)) | |
1941 | goto err_pages; | |
1942 | ||
caf49191 | 1943 | gfp |= __GFP_NORETRY | __GFP_NOWARN | __GFP_NO_KSWAPD; |
6c085a72 CW |
1944 | gfp &= ~(__GFP_IO | __GFP_WAIT); |
1945 | } | |
426729dc KRW |
1946 | #ifdef CONFIG_SWIOTLB |
1947 | if (swiotlb_nr_tbl()) { | |
1948 | st->nents++; | |
1949 | sg_set_page(sg, page, PAGE_SIZE, 0); | |
1950 | sg = sg_next(sg); | |
1951 | continue; | |
1952 | } | |
1953 | #endif | |
90797e6d ID |
1954 | if (!i || page_to_pfn(page) != last_pfn + 1) { |
1955 | if (i) | |
1956 | sg = sg_next(sg); | |
1957 | st->nents++; | |
1958 | sg_set_page(sg, page, PAGE_SIZE, 0); | |
1959 | } else { | |
1960 | sg->length += PAGE_SIZE; | |
1961 | } | |
1962 | last_pfn = page_to_pfn(page); | |
3bbbe706 DV |
1963 | |
1964 | /* Check that the i965g/gm workaround works. */ | |
1965 | WARN_ON((gfp & __GFP_DMA32) && (last_pfn >= 0x00100000UL)); | |
e5281ccd | 1966 | } |
426729dc KRW |
1967 | #ifdef CONFIG_SWIOTLB |
1968 | if (!swiotlb_nr_tbl()) | |
1969 | #endif | |
1970 | sg_mark_end(sg); | |
74ce6b6c CW |
1971 | obj->pages = st; |
1972 | ||
6dacfd2f | 1973 | if (i915_gem_object_needs_bit17_swizzle(obj)) |
e5281ccd CW |
1974 | i915_gem_object_do_bit_17_swizzle(obj); |
1975 | ||
1976 | return 0; | |
1977 | ||
1978 | err_pages: | |
90797e6d ID |
1979 | sg_mark_end(sg); |
1980 | for_each_sg_page(st->sgl, &sg_iter, st->nents, 0) | |
2db76d7c | 1981 | page_cache_release(sg_page_iter_page(&sg_iter)); |
9da3da66 CW |
1982 | sg_free_table(st); |
1983 | kfree(st); | |
e5281ccd | 1984 | return PTR_ERR(page); |
673a394b EA |
1985 | } |
1986 | ||
37e680a1 CW |
1987 | /* Ensure that the associated pages are gathered from the backing storage |
1988 | * and pinned into our object. i915_gem_object_get_pages() may be called | |
1989 | * multiple times before they are released by a single call to | |
1990 | * i915_gem_object_put_pages() - once the pages are no longer referenced | |
1991 | * either as a result of memory pressure (reaping pages under the shrinker) | |
1992 | * or as the object is itself released. | |
1993 | */ | |
1994 | int | |
1995 | i915_gem_object_get_pages(struct drm_i915_gem_object *obj) | |
1996 | { | |
1997 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; | |
1998 | const struct drm_i915_gem_object_ops *ops = obj->ops; | |
1999 | int ret; | |
2000 | ||
2f745ad3 | 2001 | if (obj->pages) |
37e680a1 CW |
2002 | return 0; |
2003 | ||
43e28f09 | 2004 | if (obj->madv != I915_MADV_WILLNEED) { |
bd9b6a4e | 2005 | DRM_DEBUG("Attempting to obtain a purgeable object\n"); |
8c99e57d | 2006 | return -EFAULT; |
43e28f09 CW |
2007 | } |
2008 | ||
a5570178 CW |
2009 | BUG_ON(obj->pages_pin_count); |
2010 | ||
37e680a1 CW |
2011 | ret = ops->get_pages(obj); |
2012 | if (ret) | |
2013 | return ret; | |
2014 | ||
35c20a60 | 2015 | list_add_tail(&obj->global_list, &dev_priv->mm.unbound_list); |
37e680a1 | 2016 | return 0; |
673a394b EA |
2017 | } |
2018 | ||
e2d05a8b | 2019 | static void |
05394f39 | 2020 | i915_gem_object_move_to_active(struct drm_i915_gem_object *obj, |
9d773091 | 2021 | struct intel_ring_buffer *ring) |
673a394b | 2022 | { |
05394f39 | 2023 | struct drm_device *dev = obj->base.dev; |
69dc4987 | 2024 | struct drm_i915_private *dev_priv = dev->dev_private; |
9d773091 | 2025 | u32 seqno = intel_ring_get_seqno(ring); |
617dbe27 | 2026 | |
852835f3 | 2027 | BUG_ON(ring == NULL); |
02978ff5 CW |
2028 | if (obj->ring != ring && obj->last_write_seqno) { |
2029 | /* Keep the seqno relative to the current ring */ | |
2030 | obj->last_write_seqno = seqno; | |
2031 | } | |
05394f39 | 2032 | obj->ring = ring; |
673a394b EA |
2033 | |
2034 | /* Add a reference if we're newly entering the active list. */ | |
05394f39 CW |
2035 | if (!obj->active) { |
2036 | drm_gem_object_reference(&obj->base); | |
2037 | obj->active = 1; | |
673a394b | 2038 | } |
e35a41de | 2039 | |
05394f39 | 2040 | list_move_tail(&obj->ring_list, &ring->active_list); |
caea7476 | 2041 | |
0201f1ec | 2042 | obj->last_read_seqno = seqno; |
caea7476 | 2043 | |
7dd49065 | 2044 | if (obj->fenced_gpu_access) { |
caea7476 | 2045 | obj->last_fenced_seqno = seqno; |
caea7476 | 2046 | |
7dd49065 CW |
2047 | /* Bump MRU to take account of the delayed flush */ |
2048 | if (obj->fence_reg != I915_FENCE_REG_NONE) { | |
2049 | struct drm_i915_fence_reg *reg; | |
2050 | ||
2051 | reg = &dev_priv->fence_regs[obj->fence_reg]; | |
2052 | list_move_tail(®->lru_list, | |
2053 | &dev_priv->mm.fence_list); | |
2054 | } | |
caea7476 CW |
2055 | } |
2056 | } | |
2057 | ||
e2d05a8b BW |
2058 | void i915_vma_move_to_active(struct i915_vma *vma, |
2059 | struct intel_ring_buffer *ring) | |
2060 | { | |
2061 | list_move_tail(&vma->mm_list, &vma->vm->active_list); | |
2062 | return i915_gem_object_move_to_active(vma->obj, ring); | |
2063 | } | |
2064 | ||
caea7476 | 2065 | static void |
caea7476 | 2066 | i915_gem_object_move_to_inactive(struct drm_i915_gem_object *obj) |
ce44b0ea | 2067 | { |
ca191b13 | 2068 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
feb822cf BW |
2069 | struct i915_address_space *vm; |
2070 | struct i915_vma *vma; | |
ce44b0ea | 2071 | |
65ce3027 | 2072 | BUG_ON(obj->base.write_domain & ~I915_GEM_GPU_DOMAINS); |
05394f39 | 2073 | BUG_ON(!obj->active); |
caea7476 | 2074 | |
feb822cf BW |
2075 | list_for_each_entry(vm, &dev_priv->vm_list, global_link) { |
2076 | vma = i915_gem_obj_to_vma(obj, vm); | |
2077 | if (vma && !list_empty(&vma->mm_list)) | |
2078 | list_move_tail(&vma->mm_list, &vm->inactive_list); | |
2079 | } | |
caea7476 | 2080 | |
65ce3027 | 2081 | list_del_init(&obj->ring_list); |
caea7476 CW |
2082 | obj->ring = NULL; |
2083 | ||
65ce3027 CW |
2084 | obj->last_read_seqno = 0; |
2085 | obj->last_write_seqno = 0; | |
2086 | obj->base.write_domain = 0; | |
2087 | ||
2088 | obj->last_fenced_seqno = 0; | |
caea7476 | 2089 | obj->fenced_gpu_access = false; |
caea7476 CW |
2090 | |
2091 | obj->active = 0; | |
2092 | drm_gem_object_unreference(&obj->base); | |
2093 | ||
2094 | WARN_ON(i915_verify_lists(dev)); | |
ce44b0ea | 2095 | } |
673a394b | 2096 | |
9d773091 | 2097 | static int |
fca26bb4 | 2098 | i915_gem_init_seqno(struct drm_device *dev, u32 seqno) |
53d227f2 | 2099 | { |
9d773091 CW |
2100 | struct drm_i915_private *dev_priv = dev->dev_private; |
2101 | struct intel_ring_buffer *ring; | |
2102 | int ret, i, j; | |
53d227f2 | 2103 | |
107f27a5 | 2104 | /* Carefully retire all requests without writing to the rings */ |
9d773091 | 2105 | for_each_ring(ring, dev_priv, i) { |
107f27a5 CW |
2106 | ret = intel_ring_idle(ring); |
2107 | if (ret) | |
2108 | return ret; | |
9d773091 | 2109 | } |
9d773091 | 2110 | i915_gem_retire_requests(dev); |
107f27a5 CW |
2111 | |
2112 | /* Finally reset hw state */ | |
9d773091 | 2113 | for_each_ring(ring, dev_priv, i) { |
fca26bb4 | 2114 | intel_ring_init_seqno(ring, seqno); |
498d2ac1 | 2115 | |
9d773091 CW |
2116 | for (j = 0; j < ARRAY_SIZE(ring->sync_seqno); j++) |
2117 | ring->sync_seqno[j] = 0; | |
2118 | } | |
53d227f2 | 2119 | |
9d773091 | 2120 | return 0; |
53d227f2 DV |
2121 | } |
2122 | ||
fca26bb4 MK |
2123 | int i915_gem_set_seqno(struct drm_device *dev, u32 seqno) |
2124 | { | |
2125 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2126 | int ret; | |
2127 | ||
2128 | if (seqno == 0) | |
2129 | return -EINVAL; | |
2130 | ||
2131 | /* HWS page needs to be set less than what we | |
2132 | * will inject to ring | |
2133 | */ | |
2134 | ret = i915_gem_init_seqno(dev, seqno - 1); | |
2135 | if (ret) | |
2136 | return ret; | |
2137 | ||
2138 | /* Carefully set the last_seqno value so that wrap | |
2139 | * detection still works | |
2140 | */ | |
2141 | dev_priv->next_seqno = seqno; | |
2142 | dev_priv->last_seqno = seqno - 1; | |
2143 | if (dev_priv->last_seqno == 0) | |
2144 | dev_priv->last_seqno--; | |
2145 | ||
2146 | return 0; | |
2147 | } | |
2148 | ||
9d773091 CW |
2149 | int |
2150 | i915_gem_get_seqno(struct drm_device *dev, u32 *seqno) | |
53d227f2 | 2151 | { |
9d773091 CW |
2152 | struct drm_i915_private *dev_priv = dev->dev_private; |
2153 | ||
2154 | /* reserve 0 for non-seqno */ | |
2155 | if (dev_priv->next_seqno == 0) { | |
fca26bb4 | 2156 | int ret = i915_gem_init_seqno(dev, 0); |
9d773091 CW |
2157 | if (ret) |
2158 | return ret; | |
53d227f2 | 2159 | |
9d773091 CW |
2160 | dev_priv->next_seqno = 1; |
2161 | } | |
53d227f2 | 2162 | |
f72b3435 | 2163 | *seqno = dev_priv->last_seqno = dev_priv->next_seqno++; |
9d773091 | 2164 | return 0; |
53d227f2 DV |
2165 | } |
2166 | ||
0025c077 MK |
2167 | int __i915_add_request(struct intel_ring_buffer *ring, |
2168 | struct drm_file *file, | |
7d736f4f | 2169 | struct drm_i915_gem_object *obj, |
0025c077 | 2170 | u32 *out_seqno) |
673a394b | 2171 | { |
db53a302 | 2172 | drm_i915_private_t *dev_priv = ring->dev->dev_private; |
acb868d3 | 2173 | struct drm_i915_gem_request *request; |
7d736f4f | 2174 | u32 request_ring_position, request_start; |
3cce469c CW |
2175 | int ret; |
2176 | ||
7d736f4f | 2177 | request_start = intel_ring_get_tail(ring); |
cc889e0f DV |
2178 | /* |
2179 | * Emit any outstanding flushes - execbuf can fail to emit the flush | |
2180 | * after having emitted the batchbuffer command. Hence we need to fix | |
2181 | * things up similar to emitting the lazy request. The difference here | |
2182 | * is that the flush _must_ happen before the next request, no matter | |
2183 | * what. | |
2184 | */ | |
a7b9761d CW |
2185 | ret = intel_ring_flush_all_caches(ring); |
2186 | if (ret) | |
2187 | return ret; | |
cc889e0f | 2188 | |
3c0e234c CW |
2189 | request = ring->preallocated_lazy_request; |
2190 | if (WARN_ON(request == NULL)) | |
acb868d3 | 2191 | return -ENOMEM; |
cc889e0f | 2192 | |
a71d8d94 CW |
2193 | /* Record the position of the start of the request so that |
2194 | * should we detect the updated seqno part-way through the | |
2195 | * GPU processing the request, we never over-estimate the | |
2196 | * position of the head. | |
2197 | */ | |
2198 | request_ring_position = intel_ring_get_tail(ring); | |
2199 | ||
9d773091 | 2200 | ret = ring->add_request(ring); |
3c0e234c | 2201 | if (ret) |
3bb73aba | 2202 | return ret; |
673a394b | 2203 | |
9d773091 | 2204 | request->seqno = intel_ring_get_seqno(ring); |
852835f3 | 2205 | request->ring = ring; |
7d736f4f | 2206 | request->head = request_start; |
a71d8d94 | 2207 | request->tail = request_ring_position; |
7d736f4f MK |
2208 | |
2209 | /* Whilst this request exists, batch_obj will be on the | |
2210 | * active_list, and so will hold the active reference. Only when this | |
2211 | * request is retired will the the batch_obj be moved onto the | |
2212 | * inactive_list and lose its active reference. Hence we do not need | |
2213 | * to explicitly hold another reference here. | |
2214 | */ | |
9a7e0c2a | 2215 | request->batch_obj = obj; |
0e50e96b | 2216 | |
9a7e0c2a CW |
2217 | /* Hold a reference to the current context so that we can inspect |
2218 | * it later in case a hangcheck error event fires. | |
2219 | */ | |
2220 | request->ctx = ring->last_context; | |
0e50e96b MK |
2221 | if (request->ctx) |
2222 | i915_gem_context_reference(request->ctx); | |
2223 | ||
673a394b | 2224 | request->emitted_jiffies = jiffies; |
852835f3 | 2225 | list_add_tail(&request->list, &ring->request_list); |
3bb73aba | 2226 | request->file_priv = NULL; |
852835f3 | 2227 | |
db53a302 CW |
2228 | if (file) { |
2229 | struct drm_i915_file_private *file_priv = file->driver_priv; | |
2230 | ||
1c25595f | 2231 | spin_lock(&file_priv->mm.lock); |
f787a5f5 | 2232 | request->file_priv = file_priv; |
b962442e | 2233 | list_add_tail(&request->client_list, |
f787a5f5 | 2234 | &file_priv->mm.request_list); |
1c25595f | 2235 | spin_unlock(&file_priv->mm.lock); |
b962442e | 2236 | } |
673a394b | 2237 | |
9d773091 | 2238 | trace_i915_gem_request_add(ring, request->seqno); |
1823521d | 2239 | ring->outstanding_lazy_seqno = 0; |
3c0e234c | 2240 | ring->preallocated_lazy_request = NULL; |
db53a302 | 2241 | |
db1b76ca | 2242 | if (!dev_priv->ums.mm_suspended) { |
10cd45b6 MK |
2243 | i915_queue_hangcheck(ring->dev); |
2244 | ||
f62a0076 CW |
2245 | cancel_delayed_work_sync(&dev_priv->mm.idle_work); |
2246 | queue_delayed_work(dev_priv->wq, | |
2247 | &dev_priv->mm.retire_work, | |
2248 | round_jiffies_up_relative(HZ)); | |
2249 | intel_mark_busy(dev_priv->dev); | |
f65d9421 | 2250 | } |
cc889e0f | 2251 | |
acb868d3 | 2252 | if (out_seqno) |
9d773091 | 2253 | *out_seqno = request->seqno; |
3cce469c | 2254 | return 0; |
673a394b EA |
2255 | } |
2256 | ||
f787a5f5 CW |
2257 | static inline void |
2258 | i915_gem_request_remove_from_client(struct drm_i915_gem_request *request) | |
673a394b | 2259 | { |
1c25595f | 2260 | struct drm_i915_file_private *file_priv = request->file_priv; |
673a394b | 2261 | |
1c25595f CW |
2262 | if (!file_priv) |
2263 | return; | |
1c5d22f7 | 2264 | |
1c25595f | 2265 | spin_lock(&file_priv->mm.lock); |
b29c19b6 CW |
2266 | list_del(&request->client_list); |
2267 | request->file_priv = NULL; | |
1c25595f | 2268 | spin_unlock(&file_priv->mm.lock); |
673a394b | 2269 | } |
673a394b | 2270 | |
939fd762 | 2271 | static bool i915_context_is_banned(struct drm_i915_private *dev_priv, |
44e2c070 | 2272 | const struct i915_hw_context *ctx) |
be62acb4 | 2273 | { |
44e2c070 | 2274 | unsigned long elapsed; |
be62acb4 | 2275 | |
44e2c070 MK |
2276 | elapsed = get_seconds() - ctx->hang_stats.guilty_ts; |
2277 | ||
2278 | if (ctx->hang_stats.banned) | |
be62acb4 MK |
2279 | return true; |
2280 | ||
2281 | if (elapsed <= DRM_I915_CTX_BAN_PERIOD) { | |
ccc7bed0 | 2282 | if (!i915_gem_context_is_default(ctx)) { |
3fac8978 | 2283 | DRM_DEBUG("context hanging too fast, banning!\n"); |
ccc7bed0 VS |
2284 | return true; |
2285 | } else if (dev_priv->gpu_error.stop_rings == 0) { | |
2286 | DRM_ERROR("gpu hanging too fast, banning!\n"); | |
2287 | return true; | |
3fac8978 | 2288 | } |
be62acb4 MK |
2289 | } |
2290 | ||
2291 | return false; | |
2292 | } | |
2293 | ||
939fd762 MK |
2294 | static void i915_set_reset_status(struct drm_i915_private *dev_priv, |
2295 | struct i915_hw_context *ctx, | |
b6b0fac0 | 2296 | const bool guilty) |
aa60c664 | 2297 | { |
44e2c070 MK |
2298 | struct i915_ctx_hang_stats *hs; |
2299 | ||
2300 | if (WARN_ON(!ctx)) | |
2301 | return; | |
aa60c664 | 2302 | |
44e2c070 MK |
2303 | hs = &ctx->hang_stats; |
2304 | ||
2305 | if (guilty) { | |
939fd762 | 2306 | hs->banned = i915_context_is_banned(dev_priv, ctx); |
44e2c070 MK |
2307 | hs->batch_active++; |
2308 | hs->guilty_ts = get_seconds(); | |
2309 | } else { | |
2310 | hs->batch_pending++; | |
aa60c664 MK |
2311 | } |
2312 | } | |
2313 | ||
0e50e96b MK |
2314 | static void i915_gem_free_request(struct drm_i915_gem_request *request) |
2315 | { | |
2316 | list_del(&request->list); | |
2317 | i915_gem_request_remove_from_client(request); | |
2318 | ||
2319 | if (request->ctx) | |
2320 | i915_gem_context_unreference(request->ctx); | |
2321 | ||
2322 | kfree(request); | |
2323 | } | |
2324 | ||
8d9fc7fd CW |
2325 | struct drm_i915_gem_request * |
2326 | i915_gem_find_active_request(struct intel_ring_buffer *ring) | |
9375e446 | 2327 | { |
4db080f9 | 2328 | struct drm_i915_gem_request *request; |
8d9fc7fd CW |
2329 | u32 completed_seqno; |
2330 | ||
2331 | completed_seqno = ring->get_seqno(ring, false); | |
4db080f9 CW |
2332 | |
2333 | list_for_each_entry(request, &ring->request_list, list) { | |
2334 | if (i915_seqno_passed(completed_seqno, request->seqno)) | |
2335 | continue; | |
aa60c664 | 2336 | |
b6b0fac0 | 2337 | return request; |
4db080f9 | 2338 | } |
b6b0fac0 MK |
2339 | |
2340 | return NULL; | |
2341 | } | |
2342 | ||
2343 | static void i915_gem_reset_ring_status(struct drm_i915_private *dev_priv, | |
2344 | struct intel_ring_buffer *ring) | |
2345 | { | |
2346 | struct drm_i915_gem_request *request; | |
2347 | bool ring_hung; | |
2348 | ||
8d9fc7fd | 2349 | request = i915_gem_find_active_request(ring); |
b6b0fac0 MK |
2350 | |
2351 | if (request == NULL) | |
2352 | return; | |
2353 | ||
2354 | ring_hung = ring->hangcheck.score >= HANGCHECK_SCORE_RING_HUNG; | |
2355 | ||
939fd762 | 2356 | i915_set_reset_status(dev_priv, request->ctx, ring_hung); |
b6b0fac0 MK |
2357 | |
2358 | list_for_each_entry_continue(request, &ring->request_list, list) | |
939fd762 | 2359 | i915_set_reset_status(dev_priv, request->ctx, false); |
4db080f9 | 2360 | } |
aa60c664 | 2361 | |
4db080f9 CW |
2362 | static void i915_gem_reset_ring_cleanup(struct drm_i915_private *dev_priv, |
2363 | struct intel_ring_buffer *ring) | |
2364 | { | |
dfaae392 | 2365 | while (!list_empty(&ring->active_list)) { |
05394f39 | 2366 | struct drm_i915_gem_object *obj; |
9375e446 | 2367 | |
05394f39 CW |
2368 | obj = list_first_entry(&ring->active_list, |
2369 | struct drm_i915_gem_object, | |
2370 | ring_list); | |
9375e446 | 2371 | |
05394f39 | 2372 | i915_gem_object_move_to_inactive(obj); |
673a394b | 2373 | } |
1d62beea BW |
2374 | |
2375 | /* | |
2376 | * We must free the requests after all the corresponding objects have | |
2377 | * been moved off active lists. Which is the same order as the normal | |
2378 | * retire_requests function does. This is important if object hold | |
2379 | * implicit references on things like e.g. ppgtt address spaces through | |
2380 | * the request. | |
2381 | */ | |
2382 | while (!list_empty(&ring->request_list)) { | |
2383 | struct drm_i915_gem_request *request; | |
2384 | ||
2385 | request = list_first_entry(&ring->request_list, | |
2386 | struct drm_i915_gem_request, | |
2387 | list); | |
2388 | ||
2389 | i915_gem_free_request(request); | |
2390 | } | |
673a394b EA |
2391 | } |
2392 | ||
19b2dbde | 2393 | void i915_gem_restore_fences(struct drm_device *dev) |
312817a3 CW |
2394 | { |
2395 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2396 | int i; | |
2397 | ||
4b9de737 | 2398 | for (i = 0; i < dev_priv->num_fence_regs; i++) { |
312817a3 | 2399 | struct drm_i915_fence_reg *reg = &dev_priv->fence_regs[i]; |
7d2cb39c | 2400 | |
94a335db DV |
2401 | /* |
2402 | * Commit delayed tiling changes if we have an object still | |
2403 | * attached to the fence, otherwise just clear the fence. | |
2404 | */ | |
2405 | if (reg->obj) { | |
2406 | i915_gem_object_update_fence(reg->obj, reg, | |
2407 | reg->obj->tiling_mode); | |
2408 | } else { | |
2409 | i915_gem_write_fence(dev, i, NULL); | |
2410 | } | |
312817a3 CW |
2411 | } |
2412 | } | |
2413 | ||
069efc1d | 2414 | void i915_gem_reset(struct drm_device *dev) |
673a394b | 2415 | { |
77f01230 | 2416 | struct drm_i915_private *dev_priv = dev->dev_private; |
b4519513 | 2417 | struct intel_ring_buffer *ring; |
1ec14ad3 | 2418 | int i; |
673a394b | 2419 | |
4db080f9 CW |
2420 | /* |
2421 | * Before we free the objects from the requests, we need to inspect | |
2422 | * them for finding the guilty party. As the requests only borrow | |
2423 | * their reference to the objects, the inspection must be done first. | |
2424 | */ | |
2425 | for_each_ring(ring, dev_priv, i) | |
2426 | i915_gem_reset_ring_status(dev_priv, ring); | |
2427 | ||
b4519513 | 2428 | for_each_ring(ring, dev_priv, i) |
4db080f9 | 2429 | i915_gem_reset_ring_cleanup(dev_priv, ring); |
dfaae392 | 2430 | |
3d57e5bd BW |
2431 | i915_gem_cleanup_ringbuffer(dev); |
2432 | ||
acce9ffa BW |
2433 | i915_gem_context_reset(dev); |
2434 | ||
19b2dbde | 2435 | i915_gem_restore_fences(dev); |
673a394b EA |
2436 | } |
2437 | ||
2438 | /** | |
2439 | * This function clears the request list as sequence numbers are passed. | |
2440 | */ | |
cb216aa8 | 2441 | static void |
db53a302 | 2442 | i915_gem_retire_requests_ring(struct intel_ring_buffer *ring) |
673a394b | 2443 | { |
673a394b EA |
2444 | uint32_t seqno; |
2445 | ||
db53a302 | 2446 | if (list_empty(&ring->request_list)) |
6c0594a3 KW |
2447 | return; |
2448 | ||
db53a302 | 2449 | WARN_ON(i915_verify_lists(ring->dev)); |
673a394b | 2450 | |
b2eadbc8 | 2451 | seqno = ring->get_seqno(ring, true); |
1ec14ad3 | 2452 | |
e9103038 CW |
2453 | /* Move any buffers on the active list that are no longer referenced |
2454 | * by the ringbuffer to the flushing/inactive lists as appropriate, | |
2455 | * before we free the context associated with the requests. | |
2456 | */ | |
2457 | while (!list_empty(&ring->active_list)) { | |
2458 | struct drm_i915_gem_object *obj; | |
2459 | ||
2460 | obj = list_first_entry(&ring->active_list, | |
2461 | struct drm_i915_gem_object, | |
2462 | ring_list); | |
2463 | ||
2464 | if (!i915_seqno_passed(seqno, obj->last_read_seqno)) | |
2465 | break; | |
2466 | ||
2467 | i915_gem_object_move_to_inactive(obj); | |
2468 | } | |
2469 | ||
2470 | ||
852835f3 | 2471 | while (!list_empty(&ring->request_list)) { |
673a394b | 2472 | struct drm_i915_gem_request *request; |
673a394b | 2473 | |
852835f3 | 2474 | request = list_first_entry(&ring->request_list, |
673a394b EA |
2475 | struct drm_i915_gem_request, |
2476 | list); | |
673a394b | 2477 | |
dfaae392 | 2478 | if (!i915_seqno_passed(seqno, request->seqno)) |
b84d5f0c CW |
2479 | break; |
2480 | ||
db53a302 | 2481 | trace_i915_gem_request_retire(ring, request->seqno); |
a71d8d94 CW |
2482 | /* We know the GPU must have read the request to have |
2483 | * sent us the seqno + interrupt, so use the position | |
2484 | * of tail of the request to update the last known position | |
2485 | * of the GPU head. | |
2486 | */ | |
2487 | ring->last_retired_head = request->tail; | |
b84d5f0c | 2488 | |
0e50e96b | 2489 | i915_gem_free_request(request); |
b84d5f0c | 2490 | } |
673a394b | 2491 | |
db53a302 CW |
2492 | if (unlikely(ring->trace_irq_seqno && |
2493 | i915_seqno_passed(seqno, ring->trace_irq_seqno))) { | |
1ec14ad3 | 2494 | ring->irq_put(ring); |
db53a302 | 2495 | ring->trace_irq_seqno = 0; |
9d34e5db | 2496 | } |
23bc5982 | 2497 | |
db53a302 | 2498 | WARN_ON(i915_verify_lists(ring->dev)); |
673a394b EA |
2499 | } |
2500 | ||
b29c19b6 | 2501 | bool |
b09a1fec CW |
2502 | i915_gem_retire_requests(struct drm_device *dev) |
2503 | { | |
2504 | drm_i915_private_t *dev_priv = dev->dev_private; | |
b4519513 | 2505 | struct intel_ring_buffer *ring; |
b29c19b6 | 2506 | bool idle = true; |
1ec14ad3 | 2507 | int i; |
b09a1fec | 2508 | |
b29c19b6 | 2509 | for_each_ring(ring, dev_priv, i) { |
b4519513 | 2510 | i915_gem_retire_requests_ring(ring); |
b29c19b6 CW |
2511 | idle &= list_empty(&ring->request_list); |
2512 | } | |
2513 | ||
2514 | if (idle) | |
2515 | mod_delayed_work(dev_priv->wq, | |
2516 | &dev_priv->mm.idle_work, | |
2517 | msecs_to_jiffies(100)); | |
2518 | ||
2519 | return idle; | |
b09a1fec CW |
2520 | } |
2521 | ||
75ef9da2 | 2522 | static void |
673a394b EA |
2523 | i915_gem_retire_work_handler(struct work_struct *work) |
2524 | { | |
b29c19b6 CW |
2525 | struct drm_i915_private *dev_priv = |
2526 | container_of(work, typeof(*dev_priv), mm.retire_work.work); | |
2527 | struct drm_device *dev = dev_priv->dev; | |
0a58705b | 2528 | bool idle; |
673a394b | 2529 | |
891b48cf | 2530 | /* Come back later if the device is busy... */ |
b29c19b6 CW |
2531 | idle = false; |
2532 | if (mutex_trylock(&dev->struct_mutex)) { | |
2533 | idle = i915_gem_retire_requests(dev); | |
2534 | mutex_unlock(&dev->struct_mutex); | |
673a394b | 2535 | } |
b29c19b6 | 2536 | if (!idle) |
bcb45086 CW |
2537 | queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, |
2538 | round_jiffies_up_relative(HZ)); | |
b29c19b6 | 2539 | } |
0a58705b | 2540 | |
b29c19b6 CW |
2541 | static void |
2542 | i915_gem_idle_work_handler(struct work_struct *work) | |
2543 | { | |
2544 | struct drm_i915_private *dev_priv = | |
2545 | container_of(work, typeof(*dev_priv), mm.idle_work.work); | |
2546 | ||
2547 | intel_mark_idle(dev_priv->dev); | |
673a394b EA |
2548 | } |
2549 | ||
30dfebf3 DV |
2550 | /** |
2551 | * Ensures that an object will eventually get non-busy by flushing any required | |
2552 | * write domains, emitting any outstanding lazy request and retiring and | |
2553 | * completed requests. | |
2554 | */ | |
2555 | static int | |
2556 | i915_gem_object_flush_active(struct drm_i915_gem_object *obj) | |
2557 | { | |
2558 | int ret; | |
2559 | ||
2560 | if (obj->active) { | |
0201f1ec | 2561 | ret = i915_gem_check_olr(obj->ring, obj->last_read_seqno); |
30dfebf3 DV |
2562 | if (ret) |
2563 | return ret; | |
2564 | ||
30dfebf3 DV |
2565 | i915_gem_retire_requests_ring(obj->ring); |
2566 | } | |
2567 | ||
2568 | return 0; | |
2569 | } | |
2570 | ||
23ba4fd0 BW |
2571 | /** |
2572 | * i915_gem_wait_ioctl - implements DRM_IOCTL_I915_GEM_WAIT | |
2573 | * @DRM_IOCTL_ARGS: standard ioctl arguments | |
2574 | * | |
2575 | * Returns 0 if successful, else an error is returned with the remaining time in | |
2576 | * the timeout parameter. | |
2577 | * -ETIME: object is still busy after timeout | |
2578 | * -ERESTARTSYS: signal interrupted the wait | |
2579 | * -ENONENT: object doesn't exist | |
2580 | * Also possible, but rare: | |
2581 | * -EAGAIN: GPU wedged | |
2582 | * -ENOMEM: damn | |
2583 | * -ENODEV: Internal IRQ fail | |
2584 | * -E?: The add request failed | |
2585 | * | |
2586 | * The wait ioctl with a timeout of 0 reimplements the busy ioctl. With any | |
2587 | * non-zero timeout parameter the wait ioctl will wait for the given number of | |
2588 | * nanoseconds on an object becoming unbusy. Since the wait itself does so | |
2589 | * without holding struct_mutex the object may become re-busied before this | |
2590 | * function completes. A similar but shorter * race condition exists in the busy | |
2591 | * ioctl | |
2592 | */ | |
2593 | int | |
2594 | i915_gem_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *file) | |
2595 | { | |
f69061be | 2596 | drm_i915_private_t *dev_priv = dev->dev_private; |
23ba4fd0 BW |
2597 | struct drm_i915_gem_wait *args = data; |
2598 | struct drm_i915_gem_object *obj; | |
2599 | struct intel_ring_buffer *ring = NULL; | |
eac1f14f | 2600 | struct timespec timeout_stack, *timeout = NULL; |
f69061be | 2601 | unsigned reset_counter; |
23ba4fd0 BW |
2602 | u32 seqno = 0; |
2603 | int ret = 0; | |
2604 | ||
eac1f14f BW |
2605 | if (args->timeout_ns >= 0) { |
2606 | timeout_stack = ns_to_timespec(args->timeout_ns); | |
2607 | timeout = &timeout_stack; | |
2608 | } | |
23ba4fd0 BW |
2609 | |
2610 | ret = i915_mutex_lock_interruptible(dev); | |
2611 | if (ret) | |
2612 | return ret; | |
2613 | ||
2614 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->bo_handle)); | |
2615 | if (&obj->base == NULL) { | |
2616 | mutex_unlock(&dev->struct_mutex); | |
2617 | return -ENOENT; | |
2618 | } | |
2619 | ||
30dfebf3 DV |
2620 | /* Need to make sure the object gets inactive eventually. */ |
2621 | ret = i915_gem_object_flush_active(obj); | |
23ba4fd0 BW |
2622 | if (ret) |
2623 | goto out; | |
2624 | ||
2625 | if (obj->active) { | |
0201f1ec | 2626 | seqno = obj->last_read_seqno; |
23ba4fd0 BW |
2627 | ring = obj->ring; |
2628 | } | |
2629 | ||
2630 | if (seqno == 0) | |
2631 | goto out; | |
2632 | ||
23ba4fd0 BW |
2633 | /* Do this after OLR check to make sure we make forward progress polling |
2634 | * on this IOCTL with a 0 timeout (like busy ioctl) | |
2635 | */ | |
2636 | if (!args->timeout_ns) { | |
2637 | ret = -ETIME; | |
2638 | goto out; | |
2639 | } | |
2640 | ||
2641 | drm_gem_object_unreference(&obj->base); | |
f69061be | 2642 | reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter); |
23ba4fd0 BW |
2643 | mutex_unlock(&dev->struct_mutex); |
2644 | ||
b29c19b6 | 2645 | ret = __wait_seqno(ring, seqno, reset_counter, true, timeout, file->driver_priv); |
4f42f4ef | 2646 | if (timeout) |
eac1f14f | 2647 | args->timeout_ns = timespec_to_ns(timeout); |
23ba4fd0 BW |
2648 | return ret; |
2649 | ||
2650 | out: | |
2651 | drm_gem_object_unreference(&obj->base); | |
2652 | mutex_unlock(&dev->struct_mutex); | |
2653 | return ret; | |
2654 | } | |
2655 | ||
5816d648 BW |
2656 | /** |
2657 | * i915_gem_object_sync - sync an object to a ring. | |
2658 | * | |
2659 | * @obj: object which may be in use on another ring. | |
2660 | * @to: ring we wish to use the object on. May be NULL. | |
2661 | * | |
2662 | * This code is meant to abstract object synchronization with the GPU. | |
2663 | * Calling with NULL implies synchronizing the object with the CPU | |
2664 | * rather than a particular GPU ring. | |
2665 | * | |
2666 | * Returns 0 if successful, else propagates up the lower layer error. | |
2667 | */ | |
2911a35b BW |
2668 | int |
2669 | i915_gem_object_sync(struct drm_i915_gem_object *obj, | |
2670 | struct intel_ring_buffer *to) | |
2671 | { | |
2672 | struct intel_ring_buffer *from = obj->ring; | |
2673 | u32 seqno; | |
2674 | int ret, idx; | |
2675 | ||
2676 | if (from == NULL || to == from) | |
2677 | return 0; | |
2678 | ||
5816d648 | 2679 | if (to == NULL || !i915_semaphore_is_enabled(obj->base.dev)) |
0201f1ec | 2680 | return i915_gem_object_wait_rendering(obj, false); |
2911a35b BW |
2681 | |
2682 | idx = intel_ring_sync_index(from, to); | |
2683 | ||
0201f1ec | 2684 | seqno = obj->last_read_seqno; |
2911a35b BW |
2685 | if (seqno <= from->sync_seqno[idx]) |
2686 | return 0; | |
2687 | ||
b4aca010 BW |
2688 | ret = i915_gem_check_olr(obj->ring, seqno); |
2689 | if (ret) | |
2690 | return ret; | |
2911a35b | 2691 | |
b52b89da | 2692 | trace_i915_gem_ring_sync_to(from, to, seqno); |
1500f7ea | 2693 | ret = to->sync_to(to, from, seqno); |
e3a5a225 | 2694 | if (!ret) |
7b01e260 MK |
2695 | /* We use last_read_seqno because sync_to() |
2696 | * might have just caused seqno wrap under | |
2697 | * the radar. | |
2698 | */ | |
2699 | from->sync_seqno[idx] = obj->last_read_seqno; | |
2911a35b | 2700 | |
e3a5a225 | 2701 | return ret; |
2911a35b BW |
2702 | } |
2703 | ||
b5ffc9bc CW |
2704 | static void i915_gem_object_finish_gtt(struct drm_i915_gem_object *obj) |
2705 | { | |
2706 | u32 old_write_domain, old_read_domains; | |
2707 | ||
b5ffc9bc CW |
2708 | /* Force a pagefault for domain tracking on next user access */ |
2709 | i915_gem_release_mmap(obj); | |
2710 | ||
b97c3d9c KP |
2711 | if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0) |
2712 | return; | |
2713 | ||
97c809fd CW |
2714 | /* Wait for any direct GTT access to complete */ |
2715 | mb(); | |
2716 | ||
b5ffc9bc CW |
2717 | old_read_domains = obj->base.read_domains; |
2718 | old_write_domain = obj->base.write_domain; | |
2719 | ||
2720 | obj->base.read_domains &= ~I915_GEM_DOMAIN_GTT; | |
2721 | obj->base.write_domain &= ~I915_GEM_DOMAIN_GTT; | |
2722 | ||
2723 | trace_i915_gem_object_change_domain(obj, | |
2724 | old_read_domains, | |
2725 | old_write_domain); | |
2726 | } | |
2727 | ||
07fe0b12 | 2728 | int i915_vma_unbind(struct i915_vma *vma) |
673a394b | 2729 | { |
07fe0b12 | 2730 | struct drm_i915_gem_object *obj = vma->obj; |
7bddb01f | 2731 | drm_i915_private_t *dev_priv = obj->base.dev->dev_private; |
43e28f09 | 2732 | int ret; |
673a394b | 2733 | |
07fe0b12 | 2734 | if (list_empty(&vma->vma_link)) |
673a394b EA |
2735 | return 0; |
2736 | ||
0ff501cb DV |
2737 | if (!drm_mm_node_allocated(&vma->node)) { |
2738 | i915_gem_vma_destroy(vma); | |
0ff501cb DV |
2739 | return 0; |
2740 | } | |
433544bd | 2741 | |
d7f46fc4 | 2742 | if (vma->pin_count) |
31d8d651 | 2743 | return -EBUSY; |
673a394b | 2744 | |
c4670ad0 CW |
2745 | BUG_ON(obj->pages == NULL); |
2746 | ||
a8198eea | 2747 | ret = i915_gem_object_finish_gpu(obj); |
1488fc08 | 2748 | if (ret) |
a8198eea CW |
2749 | return ret; |
2750 | /* Continue on if we fail due to EIO, the GPU is hung so we | |
2751 | * should be safe and we need to cleanup or else we might | |
2752 | * cause memory corruption through use-after-free. | |
2753 | */ | |
2754 | ||
b5ffc9bc | 2755 | i915_gem_object_finish_gtt(obj); |
5323fd04 | 2756 | |
96b47b65 | 2757 | /* release the fence reg _after_ flushing */ |
d9e86c0e | 2758 | ret = i915_gem_object_put_fence(obj); |
1488fc08 | 2759 | if (ret) |
d9e86c0e | 2760 | return ret; |
96b47b65 | 2761 | |
07fe0b12 | 2762 | trace_i915_vma_unbind(vma); |
db53a302 | 2763 | |
6f65e29a BW |
2764 | vma->unbind_vma(vma); |
2765 | ||
74163907 | 2766 | i915_gem_gtt_finish_object(obj); |
7bddb01f | 2767 | |
64bf9303 | 2768 | list_del_init(&vma->mm_list); |
75e9e915 | 2769 | /* Avoid an unnecessary call to unbind on rebind. */ |
5cacaac7 BW |
2770 | if (i915_is_ggtt(vma->vm)) |
2771 | obj->map_and_fenceable = true; | |
673a394b | 2772 | |
2f633156 BW |
2773 | drm_mm_remove_node(&vma->node); |
2774 | i915_gem_vma_destroy(vma); | |
2775 | ||
2776 | /* Since the unbound list is global, only move to that list if | |
b93dab6e | 2777 | * no more VMAs exist. */ |
2f633156 BW |
2778 | if (list_empty(&obj->vma_list)) |
2779 | list_move_tail(&obj->global_list, &dev_priv->mm.unbound_list); | |
673a394b | 2780 | |
70903c3b CW |
2781 | /* And finally now the object is completely decoupled from this vma, |
2782 | * we can drop its hold on the backing storage and allow it to be | |
2783 | * reaped by the shrinker. | |
2784 | */ | |
2785 | i915_gem_object_unpin_pages(obj); | |
2786 | ||
88241785 | 2787 | return 0; |
54cf91dc CW |
2788 | } |
2789 | ||
b2da9fe5 | 2790 | int i915_gpu_idle(struct drm_device *dev) |
4df2faf4 DV |
2791 | { |
2792 | drm_i915_private_t *dev_priv = dev->dev_private; | |
b4519513 | 2793 | struct intel_ring_buffer *ring; |
1ec14ad3 | 2794 | int ret, i; |
4df2faf4 | 2795 | |
4df2faf4 | 2796 | /* Flush everything onto the inactive list. */ |
b4519513 | 2797 | for_each_ring(ring, dev_priv, i) { |
41bde553 | 2798 | ret = i915_switch_context(ring, NULL, ring->default_context); |
b6c7488d BW |
2799 | if (ret) |
2800 | return ret; | |
2801 | ||
3e960501 | 2802 | ret = intel_ring_idle(ring); |
1ec14ad3 CW |
2803 | if (ret) |
2804 | return ret; | |
2805 | } | |
4df2faf4 | 2806 | |
8a1a49f9 | 2807 | return 0; |
4df2faf4 DV |
2808 | } |
2809 | ||
9ce079e4 CW |
2810 | static void i965_write_fence_reg(struct drm_device *dev, int reg, |
2811 | struct drm_i915_gem_object *obj) | |
de151cf6 | 2812 | { |
de151cf6 | 2813 | drm_i915_private_t *dev_priv = dev->dev_private; |
56c844e5 ID |
2814 | int fence_reg; |
2815 | int fence_pitch_shift; | |
de151cf6 | 2816 | |
56c844e5 ID |
2817 | if (INTEL_INFO(dev)->gen >= 6) { |
2818 | fence_reg = FENCE_REG_SANDYBRIDGE_0; | |
2819 | fence_pitch_shift = SANDYBRIDGE_FENCE_PITCH_SHIFT; | |
2820 | } else { | |
2821 | fence_reg = FENCE_REG_965_0; | |
2822 | fence_pitch_shift = I965_FENCE_PITCH_SHIFT; | |
2823 | } | |
2824 | ||
d18b9619 CW |
2825 | fence_reg += reg * 8; |
2826 | ||
2827 | /* To w/a incoherency with non-atomic 64-bit register updates, | |
2828 | * we split the 64-bit update into two 32-bit writes. In order | |
2829 | * for a partial fence not to be evaluated between writes, we | |
2830 | * precede the update with write to turn off the fence register, | |
2831 | * and only enable the fence as the last step. | |
2832 | * | |
2833 | * For extra levels of paranoia, we make sure each step lands | |
2834 | * before applying the next step. | |
2835 | */ | |
2836 | I915_WRITE(fence_reg, 0); | |
2837 | POSTING_READ(fence_reg); | |
2838 | ||
9ce079e4 | 2839 | if (obj) { |
f343c5f6 | 2840 | u32 size = i915_gem_obj_ggtt_size(obj); |
d18b9619 | 2841 | uint64_t val; |
de151cf6 | 2842 | |
f343c5f6 | 2843 | val = (uint64_t)((i915_gem_obj_ggtt_offset(obj) + size - 4096) & |
9ce079e4 | 2844 | 0xfffff000) << 32; |
f343c5f6 | 2845 | val |= i915_gem_obj_ggtt_offset(obj) & 0xfffff000; |
56c844e5 | 2846 | val |= (uint64_t)((obj->stride / 128) - 1) << fence_pitch_shift; |
9ce079e4 CW |
2847 | if (obj->tiling_mode == I915_TILING_Y) |
2848 | val |= 1 << I965_FENCE_TILING_Y_SHIFT; | |
2849 | val |= I965_FENCE_REG_VALID; | |
c6642782 | 2850 | |
d18b9619 CW |
2851 | I915_WRITE(fence_reg + 4, val >> 32); |
2852 | POSTING_READ(fence_reg + 4); | |
2853 | ||
2854 | I915_WRITE(fence_reg + 0, val); | |
2855 | POSTING_READ(fence_reg); | |
2856 | } else { | |
2857 | I915_WRITE(fence_reg + 4, 0); | |
2858 | POSTING_READ(fence_reg + 4); | |
2859 | } | |
de151cf6 JB |
2860 | } |
2861 | ||
9ce079e4 CW |
2862 | static void i915_write_fence_reg(struct drm_device *dev, int reg, |
2863 | struct drm_i915_gem_object *obj) | |
de151cf6 | 2864 | { |
de151cf6 | 2865 | drm_i915_private_t *dev_priv = dev->dev_private; |
9ce079e4 | 2866 | u32 val; |
de151cf6 | 2867 | |
9ce079e4 | 2868 | if (obj) { |
f343c5f6 | 2869 | u32 size = i915_gem_obj_ggtt_size(obj); |
9ce079e4 CW |
2870 | int pitch_val; |
2871 | int tile_width; | |
c6642782 | 2872 | |
f343c5f6 | 2873 | WARN((i915_gem_obj_ggtt_offset(obj) & ~I915_FENCE_START_MASK) || |
9ce079e4 | 2874 | (size & -size) != size || |
f343c5f6 BW |
2875 | (i915_gem_obj_ggtt_offset(obj) & (size - 1)), |
2876 | "object 0x%08lx [fenceable? %d] not 1M or pot-size (0x%08x) aligned\n", | |
2877 | i915_gem_obj_ggtt_offset(obj), obj->map_and_fenceable, size); | |
c6642782 | 2878 | |
9ce079e4 CW |
2879 | if (obj->tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev)) |
2880 | tile_width = 128; | |
2881 | else | |
2882 | tile_width = 512; | |
2883 | ||
2884 | /* Note: pitch better be a power of two tile widths */ | |
2885 | pitch_val = obj->stride / tile_width; | |
2886 | pitch_val = ffs(pitch_val) - 1; | |
2887 | ||
f343c5f6 | 2888 | val = i915_gem_obj_ggtt_offset(obj); |
9ce079e4 CW |
2889 | if (obj->tiling_mode == I915_TILING_Y) |
2890 | val |= 1 << I830_FENCE_TILING_Y_SHIFT; | |
2891 | val |= I915_FENCE_SIZE_BITS(size); | |
2892 | val |= pitch_val << I830_FENCE_PITCH_SHIFT; | |
2893 | val |= I830_FENCE_REG_VALID; | |
2894 | } else | |
2895 | val = 0; | |
2896 | ||
2897 | if (reg < 8) | |
2898 | reg = FENCE_REG_830_0 + reg * 4; | |
2899 | else | |
2900 | reg = FENCE_REG_945_8 + (reg - 8) * 4; | |
2901 | ||
2902 | I915_WRITE(reg, val); | |
2903 | POSTING_READ(reg); | |
de151cf6 JB |
2904 | } |
2905 | ||
9ce079e4 CW |
2906 | static void i830_write_fence_reg(struct drm_device *dev, int reg, |
2907 | struct drm_i915_gem_object *obj) | |
de151cf6 | 2908 | { |
de151cf6 | 2909 | drm_i915_private_t *dev_priv = dev->dev_private; |
de151cf6 | 2910 | uint32_t val; |
de151cf6 | 2911 | |
9ce079e4 | 2912 | if (obj) { |
f343c5f6 | 2913 | u32 size = i915_gem_obj_ggtt_size(obj); |
9ce079e4 | 2914 | uint32_t pitch_val; |
de151cf6 | 2915 | |
f343c5f6 | 2916 | WARN((i915_gem_obj_ggtt_offset(obj) & ~I830_FENCE_START_MASK) || |
9ce079e4 | 2917 | (size & -size) != size || |
f343c5f6 BW |
2918 | (i915_gem_obj_ggtt_offset(obj) & (size - 1)), |
2919 | "object 0x%08lx not 512K or pot-size 0x%08x aligned\n", | |
2920 | i915_gem_obj_ggtt_offset(obj), size); | |
e76a16de | 2921 | |
9ce079e4 CW |
2922 | pitch_val = obj->stride / 128; |
2923 | pitch_val = ffs(pitch_val) - 1; | |
de151cf6 | 2924 | |
f343c5f6 | 2925 | val = i915_gem_obj_ggtt_offset(obj); |
9ce079e4 CW |
2926 | if (obj->tiling_mode == I915_TILING_Y) |
2927 | val |= 1 << I830_FENCE_TILING_Y_SHIFT; | |
2928 | val |= I830_FENCE_SIZE_BITS(size); | |
2929 | val |= pitch_val << I830_FENCE_PITCH_SHIFT; | |
2930 | val |= I830_FENCE_REG_VALID; | |
2931 | } else | |
2932 | val = 0; | |
c6642782 | 2933 | |
9ce079e4 CW |
2934 | I915_WRITE(FENCE_REG_830_0 + reg * 4, val); |
2935 | POSTING_READ(FENCE_REG_830_0 + reg * 4); | |
2936 | } | |
2937 | ||
d0a57789 CW |
2938 | inline static bool i915_gem_object_needs_mb(struct drm_i915_gem_object *obj) |
2939 | { | |
2940 | return obj && obj->base.read_domains & I915_GEM_DOMAIN_GTT; | |
2941 | } | |
2942 | ||
9ce079e4 CW |
2943 | static void i915_gem_write_fence(struct drm_device *dev, int reg, |
2944 | struct drm_i915_gem_object *obj) | |
2945 | { | |
d0a57789 CW |
2946 | struct drm_i915_private *dev_priv = dev->dev_private; |
2947 | ||
2948 | /* Ensure that all CPU reads are completed before installing a fence | |
2949 | * and all writes before removing the fence. | |
2950 | */ | |
2951 | if (i915_gem_object_needs_mb(dev_priv->fence_regs[reg].obj)) | |
2952 | mb(); | |
2953 | ||
94a335db DV |
2954 | WARN(obj && (!obj->stride || !obj->tiling_mode), |
2955 | "bogus fence setup with stride: 0x%x, tiling mode: %i\n", | |
2956 | obj->stride, obj->tiling_mode); | |
2957 | ||
9ce079e4 | 2958 | switch (INTEL_INFO(dev)->gen) { |
5ab31333 | 2959 | case 8: |
9ce079e4 | 2960 | case 7: |
56c844e5 | 2961 | case 6: |
9ce079e4 CW |
2962 | case 5: |
2963 | case 4: i965_write_fence_reg(dev, reg, obj); break; | |
2964 | case 3: i915_write_fence_reg(dev, reg, obj); break; | |
2965 | case 2: i830_write_fence_reg(dev, reg, obj); break; | |
7dbf9d6e | 2966 | default: BUG(); |
9ce079e4 | 2967 | } |
d0a57789 CW |
2968 | |
2969 | /* And similarly be paranoid that no direct access to this region | |
2970 | * is reordered to before the fence is installed. | |
2971 | */ | |
2972 | if (i915_gem_object_needs_mb(obj)) | |
2973 | mb(); | |
de151cf6 JB |
2974 | } |
2975 | ||
61050808 CW |
2976 | static inline int fence_number(struct drm_i915_private *dev_priv, |
2977 | struct drm_i915_fence_reg *fence) | |
2978 | { | |
2979 | return fence - dev_priv->fence_regs; | |
2980 | } | |
2981 | ||
2982 | static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj, | |
2983 | struct drm_i915_fence_reg *fence, | |
2984 | bool enable) | |
2985 | { | |
2dc8aae0 | 2986 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
46a0b638 CW |
2987 | int reg = fence_number(dev_priv, fence); |
2988 | ||
2989 | i915_gem_write_fence(obj->base.dev, reg, enable ? obj : NULL); | |
61050808 CW |
2990 | |
2991 | if (enable) { | |
46a0b638 | 2992 | obj->fence_reg = reg; |
61050808 CW |
2993 | fence->obj = obj; |
2994 | list_move_tail(&fence->lru_list, &dev_priv->mm.fence_list); | |
2995 | } else { | |
2996 | obj->fence_reg = I915_FENCE_REG_NONE; | |
2997 | fence->obj = NULL; | |
2998 | list_del_init(&fence->lru_list); | |
2999 | } | |
94a335db | 3000 | obj->fence_dirty = false; |
61050808 CW |
3001 | } |
3002 | ||
d9e86c0e | 3003 | static int |
d0a57789 | 3004 | i915_gem_object_wait_fence(struct drm_i915_gem_object *obj) |
d9e86c0e | 3005 | { |
1c293ea3 | 3006 | if (obj->last_fenced_seqno) { |
86d5bc37 | 3007 | int ret = i915_wait_seqno(obj->ring, obj->last_fenced_seqno); |
18991845 CW |
3008 | if (ret) |
3009 | return ret; | |
d9e86c0e CW |
3010 | |
3011 | obj->last_fenced_seqno = 0; | |
d9e86c0e CW |
3012 | } |
3013 | ||
86d5bc37 | 3014 | obj->fenced_gpu_access = false; |
d9e86c0e CW |
3015 | return 0; |
3016 | } | |
3017 | ||
3018 | int | |
3019 | i915_gem_object_put_fence(struct drm_i915_gem_object *obj) | |
3020 | { | |
61050808 | 3021 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
f9c513e9 | 3022 | struct drm_i915_fence_reg *fence; |
d9e86c0e CW |
3023 | int ret; |
3024 | ||
d0a57789 | 3025 | ret = i915_gem_object_wait_fence(obj); |
d9e86c0e CW |
3026 | if (ret) |
3027 | return ret; | |
3028 | ||
61050808 CW |
3029 | if (obj->fence_reg == I915_FENCE_REG_NONE) |
3030 | return 0; | |
d9e86c0e | 3031 | |
f9c513e9 CW |
3032 | fence = &dev_priv->fence_regs[obj->fence_reg]; |
3033 | ||
61050808 | 3034 | i915_gem_object_fence_lost(obj); |
f9c513e9 | 3035 | i915_gem_object_update_fence(obj, fence, false); |
d9e86c0e CW |
3036 | |
3037 | return 0; | |
3038 | } | |
3039 | ||
3040 | static struct drm_i915_fence_reg * | |
a360bb1a | 3041 | i915_find_fence_reg(struct drm_device *dev) |
ae3db24a | 3042 | { |
ae3db24a | 3043 | struct drm_i915_private *dev_priv = dev->dev_private; |
8fe301ad | 3044 | struct drm_i915_fence_reg *reg, *avail; |
d9e86c0e | 3045 | int i; |
ae3db24a DV |
3046 | |
3047 | /* First try to find a free reg */ | |
d9e86c0e | 3048 | avail = NULL; |
ae3db24a DV |
3049 | for (i = dev_priv->fence_reg_start; i < dev_priv->num_fence_regs; i++) { |
3050 | reg = &dev_priv->fence_regs[i]; | |
3051 | if (!reg->obj) | |
d9e86c0e | 3052 | return reg; |
ae3db24a | 3053 | |
1690e1eb | 3054 | if (!reg->pin_count) |
d9e86c0e | 3055 | avail = reg; |
ae3db24a DV |
3056 | } |
3057 | ||
d9e86c0e | 3058 | if (avail == NULL) |
5dce5b93 | 3059 | goto deadlock; |
ae3db24a DV |
3060 | |
3061 | /* None available, try to steal one or wait for a user to finish */ | |
d9e86c0e | 3062 | list_for_each_entry(reg, &dev_priv->mm.fence_list, lru_list) { |
1690e1eb | 3063 | if (reg->pin_count) |
ae3db24a DV |
3064 | continue; |
3065 | ||
8fe301ad | 3066 | return reg; |
ae3db24a DV |
3067 | } |
3068 | ||
5dce5b93 CW |
3069 | deadlock: |
3070 | /* Wait for completion of pending flips which consume fences */ | |
3071 | if (intel_has_pending_fb_unpin(dev)) | |
3072 | return ERR_PTR(-EAGAIN); | |
3073 | ||
3074 | return ERR_PTR(-EDEADLK); | |
ae3db24a DV |
3075 | } |
3076 | ||
de151cf6 | 3077 | /** |
9a5a53b3 | 3078 | * i915_gem_object_get_fence - set up fencing for an object |
de151cf6 JB |
3079 | * @obj: object to map through a fence reg |
3080 | * | |
3081 | * When mapping objects through the GTT, userspace wants to be able to write | |
3082 | * to them without having to worry about swizzling if the object is tiled. | |
de151cf6 JB |
3083 | * This function walks the fence regs looking for a free one for @obj, |
3084 | * stealing one if it can't find any. | |
3085 | * | |
3086 | * It then sets up the reg based on the object's properties: address, pitch | |
3087 | * and tiling format. | |
9a5a53b3 CW |
3088 | * |
3089 | * For an untiled surface, this removes any existing fence. | |
de151cf6 | 3090 | */ |
8c4b8c3f | 3091 | int |
06d98131 | 3092 | i915_gem_object_get_fence(struct drm_i915_gem_object *obj) |
de151cf6 | 3093 | { |
05394f39 | 3094 | struct drm_device *dev = obj->base.dev; |
79e53945 | 3095 | struct drm_i915_private *dev_priv = dev->dev_private; |
14415745 | 3096 | bool enable = obj->tiling_mode != I915_TILING_NONE; |
d9e86c0e | 3097 | struct drm_i915_fence_reg *reg; |
ae3db24a | 3098 | int ret; |
de151cf6 | 3099 | |
14415745 CW |
3100 | /* Have we updated the tiling parameters upon the object and so |
3101 | * will need to serialise the write to the associated fence register? | |
3102 | */ | |
5d82e3e6 | 3103 | if (obj->fence_dirty) { |
d0a57789 | 3104 | ret = i915_gem_object_wait_fence(obj); |
14415745 CW |
3105 | if (ret) |
3106 | return ret; | |
3107 | } | |
9a5a53b3 | 3108 | |
d9e86c0e | 3109 | /* Just update our place in the LRU if our fence is getting reused. */ |
05394f39 CW |
3110 | if (obj->fence_reg != I915_FENCE_REG_NONE) { |
3111 | reg = &dev_priv->fence_regs[obj->fence_reg]; | |
5d82e3e6 | 3112 | if (!obj->fence_dirty) { |
14415745 CW |
3113 | list_move_tail(®->lru_list, |
3114 | &dev_priv->mm.fence_list); | |
3115 | return 0; | |
3116 | } | |
3117 | } else if (enable) { | |
3118 | reg = i915_find_fence_reg(dev); | |
5dce5b93 CW |
3119 | if (IS_ERR(reg)) |
3120 | return PTR_ERR(reg); | |
d9e86c0e | 3121 | |
14415745 CW |
3122 | if (reg->obj) { |
3123 | struct drm_i915_gem_object *old = reg->obj; | |
3124 | ||
d0a57789 | 3125 | ret = i915_gem_object_wait_fence(old); |
29c5a587 CW |
3126 | if (ret) |
3127 | return ret; | |
3128 | ||
14415745 | 3129 | i915_gem_object_fence_lost(old); |
29c5a587 | 3130 | } |
14415745 | 3131 | } else |
a09ba7fa | 3132 | return 0; |
a09ba7fa | 3133 | |
14415745 | 3134 | i915_gem_object_update_fence(obj, reg, enable); |
14415745 | 3135 | |
9ce079e4 | 3136 | return 0; |
de151cf6 JB |
3137 | } |
3138 | ||
42d6ab48 CW |
3139 | static bool i915_gem_valid_gtt_space(struct drm_device *dev, |
3140 | struct drm_mm_node *gtt_space, | |
3141 | unsigned long cache_level) | |
3142 | { | |
3143 | struct drm_mm_node *other; | |
3144 | ||
3145 | /* On non-LLC machines we have to be careful when putting differing | |
3146 | * types of snoopable memory together to avoid the prefetcher | |
4239ca77 | 3147 | * crossing memory domains and dying. |
42d6ab48 CW |
3148 | */ |
3149 | if (HAS_LLC(dev)) | |
3150 | return true; | |
3151 | ||
c6cfb325 | 3152 | if (!drm_mm_node_allocated(gtt_space)) |
42d6ab48 CW |
3153 | return true; |
3154 | ||
3155 | if (list_empty(>t_space->node_list)) | |
3156 | return true; | |
3157 | ||
3158 | other = list_entry(gtt_space->node_list.prev, struct drm_mm_node, node_list); | |
3159 | if (other->allocated && !other->hole_follows && other->color != cache_level) | |
3160 | return false; | |
3161 | ||
3162 | other = list_entry(gtt_space->node_list.next, struct drm_mm_node, node_list); | |
3163 | if (other->allocated && !gtt_space->hole_follows && other->color != cache_level) | |
3164 | return false; | |
3165 | ||
3166 | return true; | |
3167 | } | |
3168 | ||
3169 | static void i915_gem_verify_gtt(struct drm_device *dev) | |
3170 | { | |
3171 | #if WATCH_GTT | |
3172 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3173 | struct drm_i915_gem_object *obj; | |
3174 | int err = 0; | |
3175 | ||
35c20a60 | 3176 | list_for_each_entry(obj, &dev_priv->mm.gtt_list, global_list) { |
42d6ab48 CW |
3177 | if (obj->gtt_space == NULL) { |
3178 | printk(KERN_ERR "object found on GTT list with no space reserved\n"); | |
3179 | err++; | |
3180 | continue; | |
3181 | } | |
3182 | ||
3183 | if (obj->cache_level != obj->gtt_space->color) { | |
3184 | printk(KERN_ERR "object reserved space [%08lx, %08lx] with wrong color, cache_level=%x, color=%lx\n", | |
f343c5f6 BW |
3185 | i915_gem_obj_ggtt_offset(obj), |
3186 | i915_gem_obj_ggtt_offset(obj) + i915_gem_obj_ggtt_size(obj), | |
42d6ab48 CW |
3187 | obj->cache_level, |
3188 | obj->gtt_space->color); | |
3189 | err++; | |
3190 | continue; | |
3191 | } | |
3192 | ||
3193 | if (!i915_gem_valid_gtt_space(dev, | |
3194 | obj->gtt_space, | |
3195 | obj->cache_level)) { | |
3196 | printk(KERN_ERR "invalid GTT space found at [%08lx, %08lx] - color=%x\n", | |
f343c5f6 BW |
3197 | i915_gem_obj_ggtt_offset(obj), |
3198 | i915_gem_obj_ggtt_offset(obj) + i915_gem_obj_ggtt_size(obj), | |
42d6ab48 CW |
3199 | obj->cache_level); |
3200 | err++; | |
3201 | continue; | |
3202 | } | |
3203 | } | |
3204 | ||
3205 | WARN_ON(err); | |
3206 | #endif | |
3207 | } | |
3208 | ||
673a394b EA |
3209 | /** |
3210 | * Finds free space in the GTT aperture and binds the object there. | |
3211 | */ | |
262de145 | 3212 | static struct i915_vma * |
07fe0b12 BW |
3213 | i915_gem_object_bind_to_vm(struct drm_i915_gem_object *obj, |
3214 | struct i915_address_space *vm, | |
3215 | unsigned alignment, | |
1ec9e26d | 3216 | unsigned flags) |
673a394b | 3217 | { |
05394f39 | 3218 | struct drm_device *dev = obj->base.dev; |
673a394b | 3219 | drm_i915_private_t *dev_priv = dev->dev_private; |
5e783301 | 3220 | u32 size, fence_size, fence_alignment, unfenced_alignment; |
07fe0b12 | 3221 | size_t gtt_max = |
1ec9e26d | 3222 | flags & PIN_MAPPABLE ? dev_priv->gtt.mappable_end : vm->total; |
2f633156 | 3223 | struct i915_vma *vma; |
07f73f69 | 3224 | int ret; |
673a394b | 3225 | |
e28f8711 CW |
3226 | fence_size = i915_gem_get_gtt_size(dev, |
3227 | obj->base.size, | |
3228 | obj->tiling_mode); | |
3229 | fence_alignment = i915_gem_get_gtt_alignment(dev, | |
3230 | obj->base.size, | |
d865110c | 3231 | obj->tiling_mode, true); |
e28f8711 | 3232 | unfenced_alignment = |
d865110c | 3233 | i915_gem_get_gtt_alignment(dev, |
1ec9e26d DV |
3234 | obj->base.size, |
3235 | obj->tiling_mode, false); | |
a00b10c3 | 3236 | |
673a394b | 3237 | if (alignment == 0) |
1ec9e26d | 3238 | alignment = flags & PIN_MAPPABLE ? fence_alignment : |
5e783301 | 3239 | unfenced_alignment; |
1ec9e26d | 3240 | if (flags & PIN_MAPPABLE && alignment & (fence_alignment - 1)) { |
bd9b6a4e | 3241 | DRM_DEBUG("Invalid object alignment requested %u\n", alignment); |
262de145 | 3242 | return ERR_PTR(-EINVAL); |
673a394b EA |
3243 | } |
3244 | ||
1ec9e26d | 3245 | size = flags & PIN_MAPPABLE ? fence_size : obj->base.size; |
a00b10c3 | 3246 | |
654fc607 CW |
3247 | /* If the object is bigger than the entire aperture, reject it early |
3248 | * before evicting everything in a vain attempt to find space. | |
3249 | */ | |
0a9ae0d7 | 3250 | if (obj->base.size > gtt_max) { |
bd9b6a4e | 3251 | DRM_DEBUG("Attempting to bind an object larger than the aperture: object=%zd > %s aperture=%zu\n", |
a36689cb | 3252 | obj->base.size, |
1ec9e26d | 3253 | flags & PIN_MAPPABLE ? "mappable" : "total", |
0a9ae0d7 | 3254 | gtt_max); |
262de145 | 3255 | return ERR_PTR(-E2BIG); |
654fc607 CW |
3256 | } |
3257 | ||
37e680a1 | 3258 | ret = i915_gem_object_get_pages(obj); |
6c085a72 | 3259 | if (ret) |
262de145 | 3260 | return ERR_PTR(ret); |
6c085a72 | 3261 | |
fbdda6fb CW |
3262 | i915_gem_object_pin_pages(obj); |
3263 | ||
accfef2e | 3264 | vma = i915_gem_obj_lookup_or_create_vma(obj, vm); |
262de145 | 3265 | if (IS_ERR(vma)) |
bc6bc15b | 3266 | goto err_unpin; |
2f633156 | 3267 | |
0a9ae0d7 | 3268 | search_free: |
07fe0b12 | 3269 | ret = drm_mm_insert_node_in_range_generic(&vm->mm, &vma->node, |
0a9ae0d7 | 3270 | size, alignment, |
31e5d7c6 DH |
3271 | obj->cache_level, 0, gtt_max, |
3272 | DRM_MM_SEARCH_DEFAULT); | |
dc9dd7a2 | 3273 | if (ret) { |
f6cd1f15 | 3274 | ret = i915_gem_evict_something(dev, vm, size, alignment, |
1ec9e26d | 3275 | obj->cache_level, flags); |
dc9dd7a2 CW |
3276 | if (ret == 0) |
3277 | goto search_free; | |
9731129c | 3278 | |
bc6bc15b | 3279 | goto err_free_vma; |
673a394b | 3280 | } |
2f633156 | 3281 | if (WARN_ON(!i915_gem_valid_gtt_space(dev, &vma->node, |
c6cfb325 | 3282 | obj->cache_level))) { |
2f633156 | 3283 | ret = -EINVAL; |
bc6bc15b | 3284 | goto err_remove_node; |
673a394b EA |
3285 | } |
3286 | ||
74163907 | 3287 | ret = i915_gem_gtt_prepare_object(obj); |
2f633156 | 3288 | if (ret) |
bc6bc15b | 3289 | goto err_remove_node; |
673a394b | 3290 | |
35c20a60 | 3291 | list_move_tail(&obj->global_list, &dev_priv->mm.bound_list); |
ca191b13 | 3292 | list_add_tail(&vma->mm_list, &vm->inactive_list); |
bf1a1092 | 3293 | |
4bd561b3 BW |
3294 | if (i915_is_ggtt(vm)) { |
3295 | bool mappable, fenceable; | |
a00b10c3 | 3296 | |
49987099 DV |
3297 | fenceable = (vma->node.size == fence_size && |
3298 | (vma->node.start & (fence_alignment - 1)) == 0); | |
4bd561b3 | 3299 | |
49987099 DV |
3300 | mappable = (vma->node.start + obj->base.size <= |
3301 | dev_priv->gtt.mappable_end); | |
a00b10c3 | 3302 | |
5cacaac7 | 3303 | obj->map_and_fenceable = mappable && fenceable; |
4bd561b3 | 3304 | } |
75e9e915 | 3305 | |
1ec9e26d | 3306 | WARN_ON(flags & PIN_MAPPABLE && !obj->map_and_fenceable); |
75e9e915 | 3307 | |
1ec9e26d | 3308 | trace_i915_vma_bind(vma, flags); |
8ea99c92 DV |
3309 | vma->bind_vma(vma, obj->cache_level, |
3310 | flags & (PIN_MAPPABLE | PIN_GLOBAL) ? GLOBAL_BIND : 0); | |
3311 | ||
42d6ab48 | 3312 | i915_gem_verify_gtt(dev); |
262de145 | 3313 | return vma; |
2f633156 | 3314 | |
bc6bc15b | 3315 | err_remove_node: |
6286ef9b | 3316 | drm_mm_remove_node(&vma->node); |
bc6bc15b | 3317 | err_free_vma: |
2f633156 | 3318 | i915_gem_vma_destroy(vma); |
262de145 | 3319 | vma = ERR_PTR(ret); |
bc6bc15b | 3320 | err_unpin: |
2f633156 | 3321 | i915_gem_object_unpin_pages(obj); |
262de145 | 3322 | return vma; |
673a394b EA |
3323 | } |
3324 | ||
000433b6 | 3325 | bool |
2c22569b CW |
3326 | i915_gem_clflush_object(struct drm_i915_gem_object *obj, |
3327 | bool force) | |
673a394b | 3328 | { |
673a394b EA |
3329 | /* If we don't have a page list set up, then we're not pinned |
3330 | * to GPU, and we can ignore the cache flush because it'll happen | |
3331 | * again at bind time. | |
3332 | */ | |
05394f39 | 3333 | if (obj->pages == NULL) |
000433b6 | 3334 | return false; |
673a394b | 3335 | |
769ce464 ID |
3336 | /* |
3337 | * Stolen memory is always coherent with the GPU as it is explicitly | |
3338 | * marked as wc by the system, or the system is cache-coherent. | |
3339 | */ | |
3340 | if (obj->stolen) | |
000433b6 | 3341 | return false; |
769ce464 | 3342 | |
9c23f7fc CW |
3343 | /* If the GPU is snooping the contents of the CPU cache, |
3344 | * we do not need to manually clear the CPU cache lines. However, | |
3345 | * the caches are only snooped when the render cache is | |
3346 | * flushed/invalidated. As we always have to emit invalidations | |
3347 | * and flushes when moving into and out of the RENDER domain, correct | |
3348 | * snooping behaviour occurs naturally as the result of our domain | |
3349 | * tracking. | |
3350 | */ | |
2c22569b | 3351 | if (!force && cpu_cache_is_coherent(obj->base.dev, obj->cache_level)) |
000433b6 | 3352 | return false; |
9c23f7fc | 3353 | |
1c5d22f7 | 3354 | trace_i915_gem_object_clflush(obj); |
9da3da66 | 3355 | drm_clflush_sg(obj->pages); |
000433b6 CW |
3356 | |
3357 | return true; | |
e47c68e9 EA |
3358 | } |
3359 | ||
3360 | /** Flushes the GTT write domain for the object if it's dirty. */ | |
3361 | static void | |
05394f39 | 3362 | i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj) |
e47c68e9 | 3363 | { |
1c5d22f7 CW |
3364 | uint32_t old_write_domain; |
3365 | ||
05394f39 | 3366 | if (obj->base.write_domain != I915_GEM_DOMAIN_GTT) |
e47c68e9 EA |
3367 | return; |
3368 | ||
63256ec5 | 3369 | /* No actual flushing is required for the GTT write domain. Writes |
e47c68e9 EA |
3370 | * to it immediately go to main memory as far as we know, so there's |
3371 | * no chipset flush. It also doesn't land in render cache. | |
63256ec5 CW |
3372 | * |
3373 | * However, we do have to enforce the order so that all writes through | |
3374 | * the GTT land before any writes to the device, such as updates to | |
3375 | * the GATT itself. | |
e47c68e9 | 3376 | */ |
63256ec5 CW |
3377 | wmb(); |
3378 | ||
05394f39 CW |
3379 | old_write_domain = obj->base.write_domain; |
3380 | obj->base.write_domain = 0; | |
1c5d22f7 CW |
3381 | |
3382 | trace_i915_gem_object_change_domain(obj, | |
05394f39 | 3383 | obj->base.read_domains, |
1c5d22f7 | 3384 | old_write_domain); |
e47c68e9 EA |
3385 | } |
3386 | ||
3387 | /** Flushes the CPU write domain for the object if it's dirty. */ | |
3388 | static void | |
2c22569b CW |
3389 | i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj, |
3390 | bool force) | |
e47c68e9 | 3391 | { |
1c5d22f7 | 3392 | uint32_t old_write_domain; |
e47c68e9 | 3393 | |
05394f39 | 3394 | if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) |
e47c68e9 EA |
3395 | return; |
3396 | ||
000433b6 CW |
3397 | if (i915_gem_clflush_object(obj, force)) |
3398 | i915_gem_chipset_flush(obj->base.dev); | |
3399 | ||
05394f39 CW |
3400 | old_write_domain = obj->base.write_domain; |
3401 | obj->base.write_domain = 0; | |
1c5d22f7 CW |
3402 | |
3403 | trace_i915_gem_object_change_domain(obj, | |
05394f39 | 3404 | obj->base.read_domains, |
1c5d22f7 | 3405 | old_write_domain); |
e47c68e9 EA |
3406 | } |
3407 | ||
2ef7eeaa EA |
3408 | /** |
3409 | * Moves a single object to the GTT read, and possibly write domain. | |
3410 | * | |
3411 | * This function returns when the move is complete, including waiting on | |
3412 | * flushes to occur. | |
3413 | */ | |
79e53945 | 3414 | int |
2021746e | 3415 | i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write) |
2ef7eeaa | 3416 | { |
8325a09d | 3417 | drm_i915_private_t *dev_priv = obj->base.dev->dev_private; |
1c5d22f7 | 3418 | uint32_t old_write_domain, old_read_domains; |
e47c68e9 | 3419 | int ret; |
2ef7eeaa | 3420 | |
02354392 | 3421 | /* Not valid to be called on unbound objects. */ |
9843877d | 3422 | if (!i915_gem_obj_bound_any(obj)) |
02354392 EA |
3423 | return -EINVAL; |
3424 | ||
8d7e3de1 CW |
3425 | if (obj->base.write_domain == I915_GEM_DOMAIN_GTT) |
3426 | return 0; | |
3427 | ||
0201f1ec | 3428 | ret = i915_gem_object_wait_rendering(obj, !write); |
88241785 CW |
3429 | if (ret) |
3430 | return ret; | |
3431 | ||
2c22569b | 3432 | i915_gem_object_flush_cpu_write_domain(obj, false); |
1c5d22f7 | 3433 | |
d0a57789 CW |
3434 | /* Serialise direct access to this object with the barriers for |
3435 | * coherent writes from the GPU, by effectively invalidating the | |
3436 | * GTT domain upon first access. | |
3437 | */ | |
3438 | if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0) | |
3439 | mb(); | |
3440 | ||
05394f39 CW |
3441 | old_write_domain = obj->base.write_domain; |
3442 | old_read_domains = obj->base.read_domains; | |
1c5d22f7 | 3443 | |
e47c68e9 EA |
3444 | /* It should now be out of any other write domains, and we can update |
3445 | * the domain values for our changes. | |
3446 | */ | |
05394f39 CW |
3447 | BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_GTT) != 0); |
3448 | obj->base.read_domains |= I915_GEM_DOMAIN_GTT; | |
e47c68e9 | 3449 | if (write) { |
05394f39 CW |
3450 | obj->base.read_domains = I915_GEM_DOMAIN_GTT; |
3451 | obj->base.write_domain = I915_GEM_DOMAIN_GTT; | |
3452 | obj->dirty = 1; | |
2ef7eeaa EA |
3453 | } |
3454 | ||
1c5d22f7 CW |
3455 | trace_i915_gem_object_change_domain(obj, |
3456 | old_read_domains, | |
3457 | old_write_domain); | |
3458 | ||
8325a09d | 3459 | /* And bump the LRU for this access */ |
ca191b13 | 3460 | if (i915_gem_object_is_inactive(obj)) { |
5c2abbea | 3461 | struct i915_vma *vma = i915_gem_obj_to_ggtt(obj); |
ca191b13 BW |
3462 | if (vma) |
3463 | list_move_tail(&vma->mm_list, | |
3464 | &dev_priv->gtt.base.inactive_list); | |
3465 | ||
3466 | } | |
8325a09d | 3467 | |
e47c68e9 EA |
3468 | return 0; |
3469 | } | |
3470 | ||
e4ffd173 CW |
3471 | int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj, |
3472 | enum i915_cache_level cache_level) | |
3473 | { | |
7bddb01f | 3474 | struct drm_device *dev = obj->base.dev; |
3089c6f2 | 3475 | struct i915_vma *vma; |
e4ffd173 CW |
3476 | int ret; |
3477 | ||
3478 | if (obj->cache_level == cache_level) | |
3479 | return 0; | |
3480 | ||
d7f46fc4 | 3481 | if (i915_gem_obj_is_pinned(obj)) { |
e4ffd173 CW |
3482 | DRM_DEBUG("can not change the cache level of pinned objects\n"); |
3483 | return -EBUSY; | |
3484 | } | |
3485 | ||
3089c6f2 BW |
3486 | list_for_each_entry(vma, &obj->vma_list, vma_link) { |
3487 | if (!i915_gem_valid_gtt_space(dev, &vma->node, cache_level)) { | |
07fe0b12 | 3488 | ret = i915_vma_unbind(vma); |
3089c6f2 BW |
3489 | if (ret) |
3490 | return ret; | |
3491 | ||
3492 | break; | |
3493 | } | |
42d6ab48 CW |
3494 | } |
3495 | ||
3089c6f2 | 3496 | if (i915_gem_obj_bound_any(obj)) { |
e4ffd173 CW |
3497 | ret = i915_gem_object_finish_gpu(obj); |
3498 | if (ret) | |
3499 | return ret; | |
3500 | ||
3501 | i915_gem_object_finish_gtt(obj); | |
3502 | ||
3503 | /* Before SandyBridge, you could not use tiling or fence | |
3504 | * registers with snooped memory, so relinquish any fences | |
3505 | * currently pointing to our region in the aperture. | |
3506 | */ | |
42d6ab48 | 3507 | if (INTEL_INFO(dev)->gen < 6) { |
e4ffd173 CW |
3508 | ret = i915_gem_object_put_fence(obj); |
3509 | if (ret) | |
3510 | return ret; | |
3511 | } | |
3512 | ||
6f65e29a | 3513 | list_for_each_entry(vma, &obj->vma_list, vma_link) |
8ea99c92 DV |
3514 | if (drm_mm_node_allocated(&vma->node)) |
3515 | vma->bind_vma(vma, cache_level, | |
3516 | obj->has_global_gtt_mapping ? GLOBAL_BIND : 0); | |
e4ffd173 CW |
3517 | } |
3518 | ||
2c22569b CW |
3519 | list_for_each_entry(vma, &obj->vma_list, vma_link) |
3520 | vma->node.color = cache_level; | |
3521 | obj->cache_level = cache_level; | |
3522 | ||
3523 | if (cpu_write_needs_clflush(obj)) { | |
e4ffd173 CW |
3524 | u32 old_read_domains, old_write_domain; |
3525 | ||
3526 | /* If we're coming from LLC cached, then we haven't | |
3527 | * actually been tracking whether the data is in the | |
3528 | * CPU cache or not, since we only allow one bit set | |
3529 | * in obj->write_domain and have been skipping the clflushes. | |
3530 | * Just set it to the CPU cache for now. | |
3531 | */ | |
3532 | WARN_ON(obj->base.write_domain & ~I915_GEM_DOMAIN_CPU); | |
e4ffd173 CW |
3533 | |
3534 | old_read_domains = obj->base.read_domains; | |
3535 | old_write_domain = obj->base.write_domain; | |
3536 | ||
3537 | obj->base.read_domains = I915_GEM_DOMAIN_CPU; | |
3538 | obj->base.write_domain = I915_GEM_DOMAIN_CPU; | |
3539 | ||
3540 | trace_i915_gem_object_change_domain(obj, | |
3541 | old_read_domains, | |
3542 | old_write_domain); | |
3543 | } | |
3544 | ||
42d6ab48 | 3545 | i915_gem_verify_gtt(dev); |
e4ffd173 CW |
3546 | return 0; |
3547 | } | |
3548 | ||
199adf40 BW |
3549 | int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data, |
3550 | struct drm_file *file) | |
e6994aee | 3551 | { |
199adf40 | 3552 | struct drm_i915_gem_caching *args = data; |
e6994aee CW |
3553 | struct drm_i915_gem_object *obj; |
3554 | int ret; | |
3555 | ||
3556 | ret = i915_mutex_lock_interruptible(dev); | |
3557 | if (ret) | |
3558 | return ret; | |
3559 | ||
3560 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); | |
3561 | if (&obj->base == NULL) { | |
3562 | ret = -ENOENT; | |
3563 | goto unlock; | |
3564 | } | |
3565 | ||
651d794f CW |
3566 | switch (obj->cache_level) { |
3567 | case I915_CACHE_LLC: | |
3568 | case I915_CACHE_L3_LLC: | |
3569 | args->caching = I915_CACHING_CACHED; | |
3570 | break; | |
3571 | ||
4257d3ba CW |
3572 | case I915_CACHE_WT: |
3573 | args->caching = I915_CACHING_DISPLAY; | |
3574 | break; | |
3575 | ||
651d794f CW |
3576 | default: |
3577 | args->caching = I915_CACHING_NONE; | |
3578 | break; | |
3579 | } | |
e6994aee CW |
3580 | |
3581 | drm_gem_object_unreference(&obj->base); | |
3582 | unlock: | |
3583 | mutex_unlock(&dev->struct_mutex); | |
3584 | return ret; | |
3585 | } | |
3586 | ||
199adf40 BW |
3587 | int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data, |
3588 | struct drm_file *file) | |
e6994aee | 3589 | { |
199adf40 | 3590 | struct drm_i915_gem_caching *args = data; |
e6994aee CW |
3591 | struct drm_i915_gem_object *obj; |
3592 | enum i915_cache_level level; | |
3593 | int ret; | |
3594 | ||
199adf40 BW |
3595 | switch (args->caching) { |
3596 | case I915_CACHING_NONE: | |
e6994aee CW |
3597 | level = I915_CACHE_NONE; |
3598 | break; | |
199adf40 | 3599 | case I915_CACHING_CACHED: |
e6994aee CW |
3600 | level = I915_CACHE_LLC; |
3601 | break; | |
4257d3ba CW |
3602 | case I915_CACHING_DISPLAY: |
3603 | level = HAS_WT(dev) ? I915_CACHE_WT : I915_CACHE_NONE; | |
3604 | break; | |
e6994aee CW |
3605 | default: |
3606 | return -EINVAL; | |
3607 | } | |
3608 | ||
3bc2913e BW |
3609 | ret = i915_mutex_lock_interruptible(dev); |
3610 | if (ret) | |
3611 | return ret; | |
3612 | ||
e6994aee CW |
3613 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
3614 | if (&obj->base == NULL) { | |
3615 | ret = -ENOENT; | |
3616 | goto unlock; | |
3617 | } | |
3618 | ||
3619 | ret = i915_gem_object_set_cache_level(obj, level); | |
3620 | ||
3621 | drm_gem_object_unreference(&obj->base); | |
3622 | unlock: | |
3623 | mutex_unlock(&dev->struct_mutex); | |
3624 | return ret; | |
3625 | } | |
3626 | ||
cc98b413 CW |
3627 | static bool is_pin_display(struct drm_i915_gem_object *obj) |
3628 | { | |
3629 | /* There are 3 sources that pin objects: | |
3630 | * 1. The display engine (scanouts, sprites, cursors); | |
3631 | * 2. Reservations for execbuffer; | |
3632 | * 3. The user. | |
3633 | * | |
3634 | * We can ignore reservations as we hold the struct_mutex and | |
3635 | * are only called outside of the reservation path. The user | |
3636 | * can only increment pin_count once, and so if after | |
3637 | * subtracting the potential reference by the user, any pin_count | |
3638 | * remains, it must be due to another use by the display engine. | |
3639 | */ | |
d7f46fc4 | 3640 | return i915_gem_obj_to_ggtt(obj)->pin_count - !!obj->user_pin_count; |
cc98b413 CW |
3641 | } |
3642 | ||
b9241ea3 | 3643 | /* |
2da3b9b9 CW |
3644 | * Prepare buffer for display plane (scanout, cursors, etc). |
3645 | * Can be called from an uninterruptible phase (modesetting) and allows | |
3646 | * any flushes to be pipelined (for pageflips). | |
b9241ea3 ZW |
3647 | */ |
3648 | int | |
2da3b9b9 CW |
3649 | i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj, |
3650 | u32 alignment, | |
919926ae | 3651 | struct intel_ring_buffer *pipelined) |
b9241ea3 | 3652 | { |
2da3b9b9 | 3653 | u32 old_read_domains, old_write_domain; |
b9241ea3 ZW |
3654 | int ret; |
3655 | ||
0be73284 | 3656 | if (pipelined != obj->ring) { |
2911a35b BW |
3657 | ret = i915_gem_object_sync(obj, pipelined); |
3658 | if (ret) | |
b9241ea3 ZW |
3659 | return ret; |
3660 | } | |
3661 | ||
cc98b413 CW |
3662 | /* Mark the pin_display early so that we account for the |
3663 | * display coherency whilst setting up the cache domains. | |
3664 | */ | |
3665 | obj->pin_display = true; | |
3666 | ||
a7ef0640 EA |
3667 | /* The display engine is not coherent with the LLC cache on gen6. As |
3668 | * a result, we make sure that the pinning that is about to occur is | |
3669 | * done with uncached PTEs. This is lowest common denominator for all | |
3670 | * chipsets. | |
3671 | * | |
3672 | * However for gen6+, we could do better by using the GFDT bit instead | |
3673 | * of uncaching, which would allow us to flush all the LLC-cached data | |
3674 | * with that bit in the PTE to main memory with just one PIPE_CONTROL. | |
3675 | */ | |
651d794f CW |
3676 | ret = i915_gem_object_set_cache_level(obj, |
3677 | HAS_WT(obj->base.dev) ? I915_CACHE_WT : I915_CACHE_NONE); | |
a7ef0640 | 3678 | if (ret) |
cc98b413 | 3679 | goto err_unpin_display; |
a7ef0640 | 3680 | |
2da3b9b9 CW |
3681 | /* As the user may map the buffer once pinned in the display plane |
3682 | * (e.g. libkms for the bootup splash), we have to ensure that we | |
3683 | * always use map_and_fenceable for all scanout buffers. | |
3684 | */ | |
1ec9e26d | 3685 | ret = i915_gem_obj_ggtt_pin(obj, alignment, PIN_MAPPABLE); |
2da3b9b9 | 3686 | if (ret) |
cc98b413 | 3687 | goto err_unpin_display; |
2da3b9b9 | 3688 | |
2c22569b | 3689 | i915_gem_object_flush_cpu_write_domain(obj, true); |
b118c1e3 | 3690 | |
2da3b9b9 | 3691 | old_write_domain = obj->base.write_domain; |
05394f39 | 3692 | old_read_domains = obj->base.read_domains; |
2da3b9b9 CW |
3693 | |
3694 | /* It should now be out of any other write domains, and we can update | |
3695 | * the domain values for our changes. | |
3696 | */ | |
e5f1d962 | 3697 | obj->base.write_domain = 0; |
05394f39 | 3698 | obj->base.read_domains |= I915_GEM_DOMAIN_GTT; |
b9241ea3 ZW |
3699 | |
3700 | trace_i915_gem_object_change_domain(obj, | |
3701 | old_read_domains, | |
2da3b9b9 | 3702 | old_write_domain); |
b9241ea3 ZW |
3703 | |
3704 | return 0; | |
cc98b413 CW |
3705 | |
3706 | err_unpin_display: | |
3707 | obj->pin_display = is_pin_display(obj); | |
3708 | return ret; | |
3709 | } | |
3710 | ||
3711 | void | |
3712 | i915_gem_object_unpin_from_display_plane(struct drm_i915_gem_object *obj) | |
3713 | { | |
d7f46fc4 | 3714 | i915_gem_object_ggtt_unpin(obj); |
cc98b413 | 3715 | obj->pin_display = is_pin_display(obj); |
b9241ea3 ZW |
3716 | } |
3717 | ||
85345517 | 3718 | int |
a8198eea | 3719 | i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj) |
85345517 | 3720 | { |
88241785 CW |
3721 | int ret; |
3722 | ||
a8198eea | 3723 | if ((obj->base.read_domains & I915_GEM_GPU_DOMAINS) == 0) |
85345517 CW |
3724 | return 0; |
3725 | ||
0201f1ec | 3726 | ret = i915_gem_object_wait_rendering(obj, false); |
c501ae7f CW |
3727 | if (ret) |
3728 | return ret; | |
3729 | ||
a8198eea CW |
3730 | /* Ensure that we invalidate the GPU's caches and TLBs. */ |
3731 | obj->base.read_domains &= ~I915_GEM_GPU_DOMAINS; | |
c501ae7f | 3732 | return 0; |
85345517 CW |
3733 | } |
3734 | ||
e47c68e9 EA |
3735 | /** |
3736 | * Moves a single object to the CPU read, and possibly write domain. | |
3737 | * | |
3738 | * This function returns when the move is complete, including waiting on | |
3739 | * flushes to occur. | |
3740 | */ | |
dabdfe02 | 3741 | int |
919926ae | 3742 | i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write) |
e47c68e9 | 3743 | { |
1c5d22f7 | 3744 | uint32_t old_write_domain, old_read_domains; |
e47c68e9 EA |
3745 | int ret; |
3746 | ||
8d7e3de1 CW |
3747 | if (obj->base.write_domain == I915_GEM_DOMAIN_CPU) |
3748 | return 0; | |
3749 | ||
0201f1ec | 3750 | ret = i915_gem_object_wait_rendering(obj, !write); |
88241785 CW |
3751 | if (ret) |
3752 | return ret; | |
3753 | ||
e47c68e9 | 3754 | i915_gem_object_flush_gtt_write_domain(obj); |
2ef7eeaa | 3755 | |
05394f39 CW |
3756 | old_write_domain = obj->base.write_domain; |
3757 | old_read_domains = obj->base.read_domains; | |
1c5d22f7 | 3758 | |
e47c68e9 | 3759 | /* Flush the CPU cache if it's still invalid. */ |
05394f39 | 3760 | if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0) { |
2c22569b | 3761 | i915_gem_clflush_object(obj, false); |
2ef7eeaa | 3762 | |
05394f39 | 3763 | obj->base.read_domains |= I915_GEM_DOMAIN_CPU; |
2ef7eeaa EA |
3764 | } |
3765 | ||
3766 | /* It should now be out of any other write domains, and we can update | |
3767 | * the domain values for our changes. | |
3768 | */ | |
05394f39 | 3769 | BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_CPU) != 0); |
e47c68e9 EA |
3770 | |
3771 | /* If we're writing through the CPU, then the GPU read domains will | |
3772 | * need to be invalidated at next use. | |
3773 | */ | |
3774 | if (write) { | |
05394f39 CW |
3775 | obj->base.read_domains = I915_GEM_DOMAIN_CPU; |
3776 | obj->base.write_domain = I915_GEM_DOMAIN_CPU; | |
e47c68e9 | 3777 | } |
2ef7eeaa | 3778 | |
1c5d22f7 CW |
3779 | trace_i915_gem_object_change_domain(obj, |
3780 | old_read_domains, | |
3781 | old_write_domain); | |
3782 | ||
2ef7eeaa EA |
3783 | return 0; |
3784 | } | |
3785 | ||
673a394b EA |
3786 | /* Throttle our rendering by waiting until the ring has completed our requests |
3787 | * emitted over 20 msec ago. | |
3788 | * | |
b962442e EA |
3789 | * Note that if we were to use the current jiffies each time around the loop, |
3790 | * we wouldn't escape the function with any frames outstanding if the time to | |
3791 | * render a frame was over 20ms. | |
3792 | * | |
673a394b EA |
3793 | * This should get us reasonable parallelism between CPU and GPU but also |
3794 | * relatively low latency when blocking on a particular request to finish. | |
3795 | */ | |
40a5f0de | 3796 | static int |
f787a5f5 | 3797 | i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file) |
40a5f0de | 3798 | { |
f787a5f5 CW |
3799 | struct drm_i915_private *dev_priv = dev->dev_private; |
3800 | struct drm_i915_file_private *file_priv = file->driver_priv; | |
b962442e | 3801 | unsigned long recent_enough = jiffies - msecs_to_jiffies(20); |
f787a5f5 CW |
3802 | struct drm_i915_gem_request *request; |
3803 | struct intel_ring_buffer *ring = NULL; | |
f69061be | 3804 | unsigned reset_counter; |
f787a5f5 CW |
3805 | u32 seqno = 0; |
3806 | int ret; | |
93533c29 | 3807 | |
308887aa DV |
3808 | ret = i915_gem_wait_for_error(&dev_priv->gpu_error); |
3809 | if (ret) | |
3810 | return ret; | |
3811 | ||
3812 | ret = i915_gem_check_wedge(&dev_priv->gpu_error, false); | |
3813 | if (ret) | |
3814 | return ret; | |
e110e8d6 | 3815 | |
1c25595f | 3816 | spin_lock(&file_priv->mm.lock); |
f787a5f5 | 3817 | list_for_each_entry(request, &file_priv->mm.request_list, client_list) { |
b962442e EA |
3818 | if (time_after_eq(request->emitted_jiffies, recent_enough)) |
3819 | break; | |
40a5f0de | 3820 | |
f787a5f5 CW |
3821 | ring = request->ring; |
3822 | seqno = request->seqno; | |
b962442e | 3823 | } |
f69061be | 3824 | reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter); |
1c25595f | 3825 | spin_unlock(&file_priv->mm.lock); |
40a5f0de | 3826 | |
f787a5f5 CW |
3827 | if (seqno == 0) |
3828 | return 0; | |
2bc43b5c | 3829 | |
b29c19b6 | 3830 | ret = __wait_seqno(ring, seqno, reset_counter, true, NULL, NULL); |
f787a5f5 CW |
3831 | if (ret == 0) |
3832 | queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, 0); | |
40a5f0de EA |
3833 | |
3834 | return ret; | |
3835 | } | |
3836 | ||
673a394b | 3837 | int |
05394f39 | 3838 | i915_gem_object_pin(struct drm_i915_gem_object *obj, |
c37e2204 | 3839 | struct i915_address_space *vm, |
05394f39 | 3840 | uint32_t alignment, |
1ec9e26d | 3841 | unsigned flags) |
673a394b | 3842 | { |
07fe0b12 | 3843 | struct i915_vma *vma; |
673a394b EA |
3844 | int ret; |
3845 | ||
bf3d149b | 3846 | if (WARN_ON(flags & (PIN_GLOBAL | PIN_MAPPABLE) && !i915_is_ggtt(vm))) |
1ec9e26d | 3847 | return -EINVAL; |
07fe0b12 BW |
3848 | |
3849 | vma = i915_gem_obj_to_vma(obj, vm); | |
07fe0b12 | 3850 | if (vma) { |
d7f46fc4 BW |
3851 | if (WARN_ON(vma->pin_count == DRM_I915_GEM_OBJECT_MAX_PIN_COUNT)) |
3852 | return -EBUSY; | |
3853 | ||
07fe0b12 BW |
3854 | if ((alignment && |
3855 | vma->node.start & (alignment - 1)) || | |
1ec9e26d | 3856 | (flags & PIN_MAPPABLE && !obj->map_and_fenceable)) { |
d7f46fc4 | 3857 | WARN(vma->pin_count, |
ae7d49d8 | 3858 | "bo is already pinned with incorrect alignment:" |
f343c5f6 | 3859 | " offset=%lx, req.alignment=%x, req.map_and_fenceable=%d," |
75e9e915 | 3860 | " obj->map_and_fenceable=%d\n", |
07fe0b12 | 3861 | i915_gem_obj_offset(obj, vm), alignment, |
1ec9e26d | 3862 | flags & PIN_MAPPABLE, |
05394f39 | 3863 | obj->map_and_fenceable); |
07fe0b12 | 3864 | ret = i915_vma_unbind(vma); |
ac0c6b5a CW |
3865 | if (ret) |
3866 | return ret; | |
8ea99c92 DV |
3867 | |
3868 | vma = NULL; | |
ac0c6b5a CW |
3869 | } |
3870 | } | |
3871 | ||
8ea99c92 | 3872 | if (vma == NULL || !drm_mm_node_allocated(&vma->node)) { |
262de145 DV |
3873 | vma = i915_gem_object_bind_to_vm(obj, vm, alignment, flags); |
3874 | if (IS_ERR(vma)) | |
3875 | return PTR_ERR(vma); | |
22c344e9 | 3876 | } |
76446cac | 3877 | |
8ea99c92 DV |
3878 | if (flags & PIN_GLOBAL && !obj->has_global_gtt_mapping) |
3879 | vma->bind_vma(vma, obj->cache_level, GLOBAL_BIND); | |
74898d7e | 3880 | |
8ea99c92 | 3881 | vma->pin_count++; |
1ec9e26d DV |
3882 | if (flags & PIN_MAPPABLE) |
3883 | obj->pin_mappable |= true; | |
673a394b EA |
3884 | |
3885 | return 0; | |
3886 | } | |
3887 | ||
3888 | void | |
d7f46fc4 | 3889 | i915_gem_object_ggtt_unpin(struct drm_i915_gem_object *obj) |
673a394b | 3890 | { |
d7f46fc4 | 3891 | struct i915_vma *vma = i915_gem_obj_to_ggtt(obj); |
673a394b | 3892 | |
d7f46fc4 BW |
3893 | BUG_ON(!vma); |
3894 | BUG_ON(vma->pin_count == 0); | |
3895 | BUG_ON(!i915_gem_obj_ggtt_bound(obj)); | |
3896 | ||
3897 | if (--vma->pin_count == 0) | |
6299f992 | 3898 | obj->pin_mappable = false; |
673a394b EA |
3899 | } |
3900 | ||
3901 | int | |
3902 | i915_gem_pin_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 3903 | struct drm_file *file) |
673a394b EA |
3904 | { |
3905 | struct drm_i915_gem_pin *args = data; | |
05394f39 | 3906 | struct drm_i915_gem_object *obj; |
673a394b EA |
3907 | int ret; |
3908 | ||
02f6bccc DV |
3909 | if (INTEL_INFO(dev)->gen >= 6) |
3910 | return -ENODEV; | |
3911 | ||
1d7cfea1 CW |
3912 | ret = i915_mutex_lock_interruptible(dev); |
3913 | if (ret) | |
3914 | return ret; | |
673a394b | 3915 | |
05394f39 | 3916 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 3917 | if (&obj->base == NULL) { |
1d7cfea1 CW |
3918 | ret = -ENOENT; |
3919 | goto unlock; | |
673a394b | 3920 | } |
673a394b | 3921 | |
05394f39 | 3922 | if (obj->madv != I915_MADV_WILLNEED) { |
bd9b6a4e | 3923 | DRM_DEBUG("Attempting to pin a purgeable buffer\n"); |
8c99e57d | 3924 | ret = -EFAULT; |
1d7cfea1 | 3925 | goto out; |
3ef94daa CW |
3926 | } |
3927 | ||
05394f39 | 3928 | if (obj->pin_filp != NULL && obj->pin_filp != file) { |
bd9b6a4e | 3929 | DRM_DEBUG("Already pinned in i915_gem_pin_ioctl(): %d\n", |
79e53945 | 3930 | args->handle); |
1d7cfea1 CW |
3931 | ret = -EINVAL; |
3932 | goto out; | |
79e53945 JB |
3933 | } |
3934 | ||
aa5f8021 DV |
3935 | if (obj->user_pin_count == ULONG_MAX) { |
3936 | ret = -EBUSY; | |
3937 | goto out; | |
3938 | } | |
3939 | ||
93be8788 | 3940 | if (obj->user_pin_count == 0) { |
1ec9e26d | 3941 | ret = i915_gem_obj_ggtt_pin(obj, args->alignment, PIN_MAPPABLE); |
1d7cfea1 CW |
3942 | if (ret) |
3943 | goto out; | |
673a394b EA |
3944 | } |
3945 | ||
93be8788 CW |
3946 | obj->user_pin_count++; |
3947 | obj->pin_filp = file; | |
3948 | ||
f343c5f6 | 3949 | args->offset = i915_gem_obj_ggtt_offset(obj); |
1d7cfea1 | 3950 | out: |
05394f39 | 3951 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 3952 | unlock: |
673a394b | 3953 | mutex_unlock(&dev->struct_mutex); |
1d7cfea1 | 3954 | return ret; |
673a394b EA |
3955 | } |
3956 | ||
3957 | int | |
3958 | i915_gem_unpin_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 3959 | struct drm_file *file) |
673a394b EA |
3960 | { |
3961 | struct drm_i915_gem_pin *args = data; | |
05394f39 | 3962 | struct drm_i915_gem_object *obj; |
76c1dec1 | 3963 | int ret; |
673a394b | 3964 | |
1d7cfea1 CW |
3965 | ret = i915_mutex_lock_interruptible(dev); |
3966 | if (ret) | |
3967 | return ret; | |
673a394b | 3968 | |
05394f39 | 3969 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 3970 | if (&obj->base == NULL) { |
1d7cfea1 CW |
3971 | ret = -ENOENT; |
3972 | goto unlock; | |
673a394b | 3973 | } |
76c1dec1 | 3974 | |
05394f39 | 3975 | if (obj->pin_filp != file) { |
bd9b6a4e | 3976 | DRM_DEBUG("Not pinned by caller in i915_gem_pin_ioctl(): %d\n", |
79e53945 | 3977 | args->handle); |
1d7cfea1 CW |
3978 | ret = -EINVAL; |
3979 | goto out; | |
79e53945 | 3980 | } |
05394f39 CW |
3981 | obj->user_pin_count--; |
3982 | if (obj->user_pin_count == 0) { | |
3983 | obj->pin_filp = NULL; | |
d7f46fc4 | 3984 | i915_gem_object_ggtt_unpin(obj); |
79e53945 | 3985 | } |
673a394b | 3986 | |
1d7cfea1 | 3987 | out: |
05394f39 | 3988 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 3989 | unlock: |
673a394b | 3990 | mutex_unlock(&dev->struct_mutex); |
1d7cfea1 | 3991 | return ret; |
673a394b EA |
3992 | } |
3993 | ||
3994 | int | |
3995 | i915_gem_busy_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 3996 | struct drm_file *file) |
673a394b EA |
3997 | { |
3998 | struct drm_i915_gem_busy *args = data; | |
05394f39 | 3999 | struct drm_i915_gem_object *obj; |
30dbf0c0 CW |
4000 | int ret; |
4001 | ||
76c1dec1 | 4002 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 4003 | if (ret) |
76c1dec1 | 4004 | return ret; |
673a394b | 4005 | |
05394f39 | 4006 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 4007 | if (&obj->base == NULL) { |
1d7cfea1 CW |
4008 | ret = -ENOENT; |
4009 | goto unlock; | |
673a394b | 4010 | } |
d1b851fc | 4011 | |
0be555b6 CW |
4012 | /* Count all active objects as busy, even if they are currently not used |
4013 | * by the gpu. Users of this interface expect objects to eventually | |
4014 | * become non-busy without any further actions, therefore emit any | |
4015 | * necessary flushes here. | |
c4de0a5d | 4016 | */ |
30dfebf3 | 4017 | ret = i915_gem_object_flush_active(obj); |
0be555b6 | 4018 | |
30dfebf3 | 4019 | args->busy = obj->active; |
e9808edd CW |
4020 | if (obj->ring) { |
4021 | BUILD_BUG_ON(I915_NUM_RINGS > 16); | |
4022 | args->busy |= intel_ring_flag(obj->ring) << 16; | |
4023 | } | |
673a394b | 4024 | |
05394f39 | 4025 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 4026 | unlock: |
673a394b | 4027 | mutex_unlock(&dev->struct_mutex); |
1d7cfea1 | 4028 | return ret; |
673a394b EA |
4029 | } |
4030 | ||
4031 | int | |
4032 | i915_gem_throttle_ioctl(struct drm_device *dev, void *data, | |
4033 | struct drm_file *file_priv) | |
4034 | { | |
0206e353 | 4035 | return i915_gem_ring_throttle(dev, file_priv); |
673a394b EA |
4036 | } |
4037 | ||
3ef94daa CW |
4038 | int |
4039 | i915_gem_madvise_ioctl(struct drm_device *dev, void *data, | |
4040 | struct drm_file *file_priv) | |
4041 | { | |
4042 | struct drm_i915_gem_madvise *args = data; | |
05394f39 | 4043 | struct drm_i915_gem_object *obj; |
76c1dec1 | 4044 | int ret; |
3ef94daa CW |
4045 | |
4046 | switch (args->madv) { | |
4047 | case I915_MADV_DONTNEED: | |
4048 | case I915_MADV_WILLNEED: | |
4049 | break; | |
4050 | default: | |
4051 | return -EINVAL; | |
4052 | } | |
4053 | ||
1d7cfea1 CW |
4054 | ret = i915_mutex_lock_interruptible(dev); |
4055 | if (ret) | |
4056 | return ret; | |
4057 | ||
05394f39 | 4058 | obj = to_intel_bo(drm_gem_object_lookup(dev, file_priv, args->handle)); |
c8725226 | 4059 | if (&obj->base == NULL) { |
1d7cfea1 CW |
4060 | ret = -ENOENT; |
4061 | goto unlock; | |
3ef94daa | 4062 | } |
3ef94daa | 4063 | |
d7f46fc4 | 4064 | if (i915_gem_obj_is_pinned(obj)) { |
1d7cfea1 CW |
4065 | ret = -EINVAL; |
4066 | goto out; | |
3ef94daa CW |
4067 | } |
4068 | ||
05394f39 CW |
4069 | if (obj->madv != __I915_MADV_PURGED) |
4070 | obj->madv = args->madv; | |
3ef94daa | 4071 | |
6c085a72 CW |
4072 | /* if the object is no longer attached, discard its backing storage */ |
4073 | if (i915_gem_object_is_purgeable(obj) && obj->pages == NULL) | |
2d7ef395 CW |
4074 | i915_gem_object_truncate(obj); |
4075 | ||
05394f39 | 4076 | args->retained = obj->madv != __I915_MADV_PURGED; |
bb6baf76 | 4077 | |
1d7cfea1 | 4078 | out: |
05394f39 | 4079 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 4080 | unlock: |
3ef94daa | 4081 | mutex_unlock(&dev->struct_mutex); |
1d7cfea1 | 4082 | return ret; |
3ef94daa CW |
4083 | } |
4084 | ||
37e680a1 CW |
4085 | void i915_gem_object_init(struct drm_i915_gem_object *obj, |
4086 | const struct drm_i915_gem_object_ops *ops) | |
0327d6ba | 4087 | { |
35c20a60 | 4088 | INIT_LIST_HEAD(&obj->global_list); |
0327d6ba | 4089 | INIT_LIST_HEAD(&obj->ring_list); |
b25cb2f8 | 4090 | INIT_LIST_HEAD(&obj->obj_exec_link); |
2f633156 | 4091 | INIT_LIST_HEAD(&obj->vma_list); |
0327d6ba | 4092 | |
37e680a1 CW |
4093 | obj->ops = ops; |
4094 | ||
0327d6ba CW |
4095 | obj->fence_reg = I915_FENCE_REG_NONE; |
4096 | obj->madv = I915_MADV_WILLNEED; | |
4097 | /* Avoid an unnecessary call to unbind on the first bind. */ | |
4098 | obj->map_and_fenceable = true; | |
4099 | ||
4100 | i915_gem_info_add_obj(obj->base.dev->dev_private, obj->base.size); | |
4101 | } | |
4102 | ||
37e680a1 CW |
4103 | static const struct drm_i915_gem_object_ops i915_gem_object_ops = { |
4104 | .get_pages = i915_gem_object_get_pages_gtt, | |
4105 | .put_pages = i915_gem_object_put_pages_gtt, | |
4106 | }; | |
4107 | ||
05394f39 CW |
4108 | struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev, |
4109 | size_t size) | |
ac52bc56 | 4110 | { |
c397b908 | 4111 | struct drm_i915_gem_object *obj; |
5949eac4 | 4112 | struct address_space *mapping; |
1a240d4d | 4113 | gfp_t mask; |
ac52bc56 | 4114 | |
42dcedd4 | 4115 | obj = i915_gem_object_alloc(dev); |
c397b908 DV |
4116 | if (obj == NULL) |
4117 | return NULL; | |
673a394b | 4118 | |
c397b908 | 4119 | if (drm_gem_object_init(dev, &obj->base, size) != 0) { |
42dcedd4 | 4120 | i915_gem_object_free(obj); |
c397b908 DV |
4121 | return NULL; |
4122 | } | |
673a394b | 4123 | |
bed1ea95 CW |
4124 | mask = GFP_HIGHUSER | __GFP_RECLAIMABLE; |
4125 | if (IS_CRESTLINE(dev) || IS_BROADWATER(dev)) { | |
4126 | /* 965gm cannot relocate objects above 4GiB. */ | |
4127 | mask &= ~__GFP_HIGHMEM; | |
4128 | mask |= __GFP_DMA32; | |
4129 | } | |
4130 | ||
496ad9aa | 4131 | mapping = file_inode(obj->base.filp)->i_mapping; |
bed1ea95 | 4132 | mapping_set_gfp_mask(mapping, mask); |
5949eac4 | 4133 | |
37e680a1 | 4134 | i915_gem_object_init(obj, &i915_gem_object_ops); |
73aa808f | 4135 | |
c397b908 DV |
4136 | obj->base.write_domain = I915_GEM_DOMAIN_CPU; |
4137 | obj->base.read_domains = I915_GEM_DOMAIN_CPU; | |
673a394b | 4138 | |
3d29b842 ED |
4139 | if (HAS_LLC(dev)) { |
4140 | /* On some devices, we can have the GPU use the LLC (the CPU | |
a1871112 EA |
4141 | * cache) for about a 10% performance improvement |
4142 | * compared to uncached. Graphics requests other than | |
4143 | * display scanout are coherent with the CPU in | |
4144 | * accessing this cache. This means in this mode we | |
4145 | * don't need to clflush on the CPU side, and on the | |
4146 | * GPU side we only need to flush internal caches to | |
4147 | * get data visible to the CPU. | |
4148 | * | |
4149 | * However, we maintain the display planes as UC, and so | |
4150 | * need to rebind when first used as such. | |
4151 | */ | |
4152 | obj->cache_level = I915_CACHE_LLC; | |
4153 | } else | |
4154 | obj->cache_level = I915_CACHE_NONE; | |
4155 | ||
d861e338 DV |
4156 | trace_i915_gem_object_create(obj); |
4157 | ||
05394f39 | 4158 | return obj; |
c397b908 DV |
4159 | } |
4160 | ||
1488fc08 | 4161 | void i915_gem_free_object(struct drm_gem_object *gem_obj) |
673a394b | 4162 | { |
1488fc08 | 4163 | struct drm_i915_gem_object *obj = to_intel_bo(gem_obj); |
05394f39 | 4164 | struct drm_device *dev = obj->base.dev; |
be72615b | 4165 | drm_i915_private_t *dev_priv = dev->dev_private; |
07fe0b12 | 4166 | struct i915_vma *vma, *next; |
673a394b | 4167 | |
f65c9168 PZ |
4168 | intel_runtime_pm_get(dev_priv); |
4169 | ||
26e12f89 CW |
4170 | trace_i915_gem_object_destroy(obj); |
4171 | ||
1488fc08 CW |
4172 | if (obj->phys_obj) |
4173 | i915_gem_detach_phys_object(dev, obj); | |
4174 | ||
07fe0b12 | 4175 | list_for_each_entry_safe(vma, next, &obj->vma_list, vma_link) { |
d7f46fc4 BW |
4176 | int ret; |
4177 | ||
4178 | vma->pin_count = 0; | |
4179 | ret = i915_vma_unbind(vma); | |
07fe0b12 BW |
4180 | if (WARN_ON(ret == -ERESTARTSYS)) { |
4181 | bool was_interruptible; | |
1488fc08 | 4182 | |
07fe0b12 BW |
4183 | was_interruptible = dev_priv->mm.interruptible; |
4184 | dev_priv->mm.interruptible = false; | |
1488fc08 | 4185 | |
07fe0b12 | 4186 | WARN_ON(i915_vma_unbind(vma)); |
1488fc08 | 4187 | |
07fe0b12 BW |
4188 | dev_priv->mm.interruptible = was_interruptible; |
4189 | } | |
1488fc08 CW |
4190 | } |
4191 | ||
1d64ae71 BW |
4192 | /* Stolen objects don't hold a ref, but do hold pin count. Fix that up |
4193 | * before progressing. */ | |
4194 | if (obj->stolen) | |
4195 | i915_gem_object_unpin_pages(obj); | |
4196 | ||
401c29f6 BW |
4197 | if (WARN_ON(obj->pages_pin_count)) |
4198 | obj->pages_pin_count = 0; | |
37e680a1 | 4199 | i915_gem_object_put_pages(obj); |
d8cb5086 | 4200 | i915_gem_object_free_mmap_offset(obj); |
0104fdbb | 4201 | i915_gem_object_release_stolen(obj); |
de151cf6 | 4202 | |
9da3da66 CW |
4203 | BUG_ON(obj->pages); |
4204 | ||
2f745ad3 CW |
4205 | if (obj->base.import_attach) |
4206 | drm_prime_gem_destroy(&obj->base, NULL); | |
de151cf6 | 4207 | |
05394f39 CW |
4208 | drm_gem_object_release(&obj->base); |
4209 | i915_gem_info_remove_obj(dev_priv, obj->base.size); | |
c397b908 | 4210 | |
05394f39 | 4211 | kfree(obj->bit_17); |
42dcedd4 | 4212 | i915_gem_object_free(obj); |
f65c9168 PZ |
4213 | |
4214 | intel_runtime_pm_put(dev_priv); | |
673a394b EA |
4215 | } |
4216 | ||
e656a6cb | 4217 | struct i915_vma *i915_gem_obj_to_vma(struct drm_i915_gem_object *obj, |
2f633156 | 4218 | struct i915_address_space *vm) |
e656a6cb DV |
4219 | { |
4220 | struct i915_vma *vma; | |
4221 | list_for_each_entry(vma, &obj->vma_list, vma_link) | |
4222 | if (vma->vm == vm) | |
4223 | return vma; | |
4224 | ||
4225 | return NULL; | |
4226 | } | |
4227 | ||
2f633156 BW |
4228 | void i915_gem_vma_destroy(struct i915_vma *vma) |
4229 | { | |
4230 | WARN_ON(vma->node.allocated); | |
aaa05667 CW |
4231 | |
4232 | /* Keep the vma as a placeholder in the execbuffer reservation lists */ | |
4233 | if (!list_empty(&vma->exec_list)) | |
4234 | return; | |
4235 | ||
8b9c2b94 | 4236 | list_del(&vma->vma_link); |
b93dab6e | 4237 | |
2f633156 BW |
4238 | kfree(vma); |
4239 | } | |
4240 | ||
29105ccc | 4241 | int |
45c5f202 | 4242 | i915_gem_suspend(struct drm_device *dev) |
29105ccc CW |
4243 | { |
4244 | drm_i915_private_t *dev_priv = dev->dev_private; | |
45c5f202 | 4245 | int ret = 0; |
28dfe52a | 4246 | |
45c5f202 | 4247 | mutex_lock(&dev->struct_mutex); |
f7403347 | 4248 | if (dev_priv->ums.mm_suspended) |
45c5f202 | 4249 | goto err; |
28dfe52a | 4250 | |
b2da9fe5 | 4251 | ret = i915_gpu_idle(dev); |
f7403347 | 4252 | if (ret) |
45c5f202 | 4253 | goto err; |
f7403347 | 4254 | |
b2da9fe5 | 4255 | i915_gem_retire_requests(dev); |
673a394b | 4256 | |
29105ccc | 4257 | /* Under UMS, be paranoid and evict. */ |
a39d7efc | 4258 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) |
6c085a72 | 4259 | i915_gem_evict_everything(dev); |
29105ccc | 4260 | |
29105ccc | 4261 | i915_kernel_lost_context(dev); |
6dbe2772 | 4262 | i915_gem_cleanup_ringbuffer(dev); |
29105ccc | 4263 | |
45c5f202 CW |
4264 | /* Hack! Don't let anybody do execbuf while we don't control the chip. |
4265 | * We need to replace this with a semaphore, or something. | |
4266 | * And not confound ums.mm_suspended! | |
4267 | */ | |
4268 | dev_priv->ums.mm_suspended = !drm_core_check_feature(dev, | |
4269 | DRIVER_MODESET); | |
4270 | mutex_unlock(&dev->struct_mutex); | |
4271 | ||
4272 | del_timer_sync(&dev_priv->gpu_error.hangcheck_timer); | |
29105ccc | 4273 | cancel_delayed_work_sync(&dev_priv->mm.retire_work); |
b29c19b6 | 4274 | cancel_delayed_work_sync(&dev_priv->mm.idle_work); |
29105ccc | 4275 | |
673a394b | 4276 | return 0; |
45c5f202 CW |
4277 | |
4278 | err: | |
4279 | mutex_unlock(&dev->struct_mutex); | |
4280 | return ret; | |
673a394b EA |
4281 | } |
4282 | ||
c3787e2e | 4283 | int i915_gem_l3_remap(struct intel_ring_buffer *ring, int slice) |
b9524a1e | 4284 | { |
c3787e2e | 4285 | struct drm_device *dev = ring->dev; |
b9524a1e | 4286 | drm_i915_private_t *dev_priv = dev->dev_private; |
35a85ac6 BW |
4287 | u32 reg_base = GEN7_L3LOG_BASE + (slice * 0x200); |
4288 | u32 *remap_info = dev_priv->l3_parity.remap_info[slice]; | |
c3787e2e | 4289 | int i, ret; |
b9524a1e | 4290 | |
040d2baa | 4291 | if (!HAS_L3_DPF(dev) || !remap_info) |
c3787e2e | 4292 | return 0; |
b9524a1e | 4293 | |
c3787e2e BW |
4294 | ret = intel_ring_begin(ring, GEN7_L3LOG_SIZE / 4 * 3); |
4295 | if (ret) | |
4296 | return ret; | |
b9524a1e | 4297 | |
c3787e2e BW |
4298 | /* |
4299 | * Note: We do not worry about the concurrent register cacheline hang | |
4300 | * here because no other code should access these registers other than | |
4301 | * at initialization time. | |
4302 | */ | |
b9524a1e | 4303 | for (i = 0; i < GEN7_L3LOG_SIZE; i += 4) { |
c3787e2e BW |
4304 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); |
4305 | intel_ring_emit(ring, reg_base + i); | |
4306 | intel_ring_emit(ring, remap_info[i/4]); | |
b9524a1e BW |
4307 | } |
4308 | ||
c3787e2e | 4309 | intel_ring_advance(ring); |
b9524a1e | 4310 | |
c3787e2e | 4311 | return ret; |
b9524a1e BW |
4312 | } |
4313 | ||
f691e2f4 DV |
4314 | void i915_gem_init_swizzling(struct drm_device *dev) |
4315 | { | |
4316 | drm_i915_private_t *dev_priv = dev->dev_private; | |
4317 | ||
11782b02 | 4318 | if (INTEL_INFO(dev)->gen < 5 || |
f691e2f4 DV |
4319 | dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_NONE) |
4320 | return; | |
4321 | ||
4322 | I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) | | |
4323 | DISP_TILE_SURFACE_SWIZZLING); | |
4324 | ||
11782b02 DV |
4325 | if (IS_GEN5(dev)) |
4326 | return; | |
4327 | ||
f691e2f4 DV |
4328 | I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_SWZCTL); |
4329 | if (IS_GEN6(dev)) | |
6b26c86d | 4330 | I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB)); |
8782e26c | 4331 | else if (IS_GEN7(dev)) |
6b26c86d | 4332 | I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB)); |
31a5336e BW |
4333 | else if (IS_GEN8(dev)) |
4334 | I915_WRITE(GAMTARBMODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_BDW)); | |
8782e26c BW |
4335 | else |
4336 | BUG(); | |
f691e2f4 | 4337 | } |
e21af88d | 4338 | |
67b1b571 CW |
4339 | static bool |
4340 | intel_enable_blt(struct drm_device *dev) | |
4341 | { | |
4342 | if (!HAS_BLT(dev)) | |
4343 | return false; | |
4344 | ||
4345 | /* The blitter was dysfunctional on early prototypes */ | |
4346 | if (IS_GEN6(dev) && dev->pdev->revision < 8) { | |
4347 | DRM_INFO("BLT not supported on this pre-production hardware;" | |
4348 | " graphics performance will be degraded.\n"); | |
4349 | return false; | |
4350 | } | |
4351 | ||
4352 | return true; | |
4353 | } | |
4354 | ||
4fc7c971 | 4355 | static int i915_gem_init_rings(struct drm_device *dev) |
8187a2b7 | 4356 | { |
4fc7c971 | 4357 | struct drm_i915_private *dev_priv = dev->dev_private; |
8187a2b7 | 4358 | int ret; |
68f95ba9 | 4359 | |
5c1143bb | 4360 | ret = intel_init_render_ring_buffer(dev); |
68f95ba9 | 4361 | if (ret) |
b6913e4b | 4362 | return ret; |
68f95ba9 CW |
4363 | |
4364 | if (HAS_BSD(dev)) { | |
5c1143bb | 4365 | ret = intel_init_bsd_ring_buffer(dev); |
68f95ba9 CW |
4366 | if (ret) |
4367 | goto cleanup_render_ring; | |
d1b851fc | 4368 | } |
68f95ba9 | 4369 | |
67b1b571 | 4370 | if (intel_enable_blt(dev)) { |
549f7365 CW |
4371 | ret = intel_init_blt_ring_buffer(dev); |
4372 | if (ret) | |
4373 | goto cleanup_bsd_ring; | |
4374 | } | |
4375 | ||
9a8a2213 BW |
4376 | if (HAS_VEBOX(dev)) { |
4377 | ret = intel_init_vebox_ring_buffer(dev); | |
4378 | if (ret) | |
4379 | goto cleanup_blt_ring; | |
4380 | } | |
4381 | ||
4382 | ||
99433931 | 4383 | ret = i915_gem_set_seqno(dev, ((u32)~0 - 0x1000)); |
4fc7c971 | 4384 | if (ret) |
9a8a2213 | 4385 | goto cleanup_vebox_ring; |
4fc7c971 BW |
4386 | |
4387 | return 0; | |
4388 | ||
9a8a2213 BW |
4389 | cleanup_vebox_ring: |
4390 | intel_cleanup_ring_buffer(&dev_priv->ring[VECS]); | |
4fc7c971 BW |
4391 | cleanup_blt_ring: |
4392 | intel_cleanup_ring_buffer(&dev_priv->ring[BCS]); | |
4393 | cleanup_bsd_ring: | |
4394 | intel_cleanup_ring_buffer(&dev_priv->ring[VCS]); | |
4395 | cleanup_render_ring: | |
4396 | intel_cleanup_ring_buffer(&dev_priv->ring[RCS]); | |
4397 | ||
4398 | return ret; | |
4399 | } | |
4400 | ||
4401 | int | |
4402 | i915_gem_init_hw(struct drm_device *dev) | |
4403 | { | |
4404 | drm_i915_private_t *dev_priv = dev->dev_private; | |
35a85ac6 | 4405 | int ret, i; |
4fc7c971 BW |
4406 | |
4407 | if (INTEL_INFO(dev)->gen < 6 && !intel_enable_gtt()) | |
4408 | return -EIO; | |
4409 | ||
59124506 | 4410 | if (dev_priv->ellc_size) |
05e21cc4 | 4411 | I915_WRITE(HSW_IDICR, I915_READ(HSW_IDICR) | IDIHASHMSK(0xf)); |
4fc7c971 | 4412 | |
0bf21347 VS |
4413 | if (IS_HASWELL(dev)) |
4414 | I915_WRITE(MI_PREDICATE_RESULT_2, IS_HSW_GT3(dev) ? | |
4415 | LOWER_SLICE_ENABLED : LOWER_SLICE_DISABLED); | |
9435373e | 4416 | |
88a2b2a3 | 4417 | if (HAS_PCH_NOP(dev)) { |
6ba844b0 DV |
4418 | if (IS_IVYBRIDGE(dev)) { |
4419 | u32 temp = I915_READ(GEN7_MSG_CTL); | |
4420 | temp &= ~(WAIT_FOR_PCH_FLR_ACK | WAIT_FOR_PCH_RESET_ACK); | |
4421 | I915_WRITE(GEN7_MSG_CTL, temp); | |
4422 | } else if (INTEL_INFO(dev)->gen >= 7) { | |
4423 | u32 temp = I915_READ(HSW_NDE_RSTWRN_OPT); | |
4424 | temp &= ~RESET_PCH_HANDSHAKE_ENABLE; | |
4425 | I915_WRITE(HSW_NDE_RSTWRN_OPT, temp); | |
4426 | } | |
88a2b2a3 BW |
4427 | } |
4428 | ||
4fc7c971 BW |
4429 | i915_gem_init_swizzling(dev); |
4430 | ||
4431 | ret = i915_gem_init_rings(dev); | |
99433931 MK |
4432 | if (ret) |
4433 | return ret; | |
4434 | ||
c3787e2e BW |
4435 | for (i = 0; i < NUM_L3_SLICES(dev); i++) |
4436 | i915_gem_l3_remap(&dev_priv->ring[RCS], i); | |
4437 | ||
254f965c | 4438 | /* |
2fa48d8d BW |
4439 | * XXX: Contexts should only be initialized once. Doing a switch to the |
4440 | * default context switch however is something we'd like to do after | |
4441 | * reset or thaw (the latter may not actually be necessary for HW, but | |
4442 | * goes with our code better). Context switching requires rings (for | |
4443 | * the do_switch), but before enabling PPGTT. So don't move this. | |
254f965c | 4444 | */ |
2fa48d8d | 4445 | ret = i915_gem_context_enable(dev_priv); |
8245be31 | 4446 | if (ret) { |
2fa48d8d BW |
4447 | DRM_ERROR("Context enable failed %d\n", ret); |
4448 | goto err_out; | |
b7c36d25 | 4449 | } |
e21af88d | 4450 | |
68f95ba9 | 4451 | return 0; |
2fa48d8d BW |
4452 | |
4453 | err_out: | |
4454 | i915_gem_cleanup_ringbuffer(dev); | |
4455 | return ret; | |
8187a2b7 ZN |
4456 | } |
4457 | ||
1070a42b CW |
4458 | int i915_gem_init(struct drm_device *dev) |
4459 | { | |
4460 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1070a42b CW |
4461 | int ret; |
4462 | ||
1070a42b | 4463 | mutex_lock(&dev->struct_mutex); |
d62b4892 JB |
4464 | |
4465 | if (IS_VALLEYVIEW(dev)) { | |
4466 | /* VLVA0 (potential hack), BIOS isn't actually waking us */ | |
4467 | I915_WRITE(VLV_GTLC_WAKE_CTRL, 1); | |
4468 | if (wait_for((I915_READ(VLV_GTLC_PW_STATUS) & 1) == 1, 10)) | |
4469 | DRM_DEBUG_DRIVER("allow wake ack timed out\n"); | |
4470 | } | |
4471 | ||
d7e5008f | 4472 | i915_gem_init_global_gtt(dev); |
d62b4892 | 4473 | |
2fa48d8d | 4474 | ret = i915_gem_context_init(dev); |
e3848694 MK |
4475 | if (ret) { |
4476 | mutex_unlock(&dev->struct_mutex); | |
2fa48d8d | 4477 | return ret; |
e3848694 | 4478 | } |
2fa48d8d | 4479 | |
1070a42b CW |
4480 | ret = i915_gem_init_hw(dev); |
4481 | mutex_unlock(&dev->struct_mutex); | |
4482 | if (ret) { | |
bdf4fd7e | 4483 | WARN_ON(dev_priv->mm.aliasing_ppgtt); |
2fa48d8d | 4484 | i915_gem_context_fini(dev); |
c39538a8 | 4485 | drm_mm_takedown(&dev_priv->gtt.base.mm); |
1070a42b CW |
4486 | return ret; |
4487 | } | |
4488 | ||
53ca26ca DV |
4489 | /* Allow hardware batchbuffers unless told otherwise, but not for KMS. */ |
4490 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) | |
4491 | dev_priv->dri1.allow_batchbuffer = 1; | |
1070a42b CW |
4492 | return 0; |
4493 | } | |
4494 | ||
8187a2b7 ZN |
4495 | void |
4496 | i915_gem_cleanup_ringbuffer(struct drm_device *dev) | |
4497 | { | |
4498 | drm_i915_private_t *dev_priv = dev->dev_private; | |
b4519513 | 4499 | struct intel_ring_buffer *ring; |
1ec14ad3 | 4500 | int i; |
8187a2b7 | 4501 | |
b4519513 CW |
4502 | for_each_ring(ring, dev_priv, i) |
4503 | intel_cleanup_ring_buffer(ring); | |
8187a2b7 ZN |
4504 | } |
4505 | ||
673a394b EA |
4506 | int |
4507 | i915_gem_entervt_ioctl(struct drm_device *dev, void *data, | |
4508 | struct drm_file *file_priv) | |
4509 | { | |
db1b76ca | 4510 | struct drm_i915_private *dev_priv = dev->dev_private; |
b4519513 | 4511 | int ret; |
673a394b | 4512 | |
79e53945 JB |
4513 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
4514 | return 0; | |
4515 | ||
1f83fee0 | 4516 | if (i915_reset_in_progress(&dev_priv->gpu_error)) { |
673a394b | 4517 | DRM_ERROR("Reenabling wedged hardware, good luck\n"); |
1f83fee0 | 4518 | atomic_set(&dev_priv->gpu_error.reset_counter, 0); |
673a394b EA |
4519 | } |
4520 | ||
673a394b | 4521 | mutex_lock(&dev->struct_mutex); |
db1b76ca | 4522 | dev_priv->ums.mm_suspended = 0; |
9bb2d6f9 | 4523 | |
f691e2f4 | 4524 | ret = i915_gem_init_hw(dev); |
d816f6ac WF |
4525 | if (ret != 0) { |
4526 | mutex_unlock(&dev->struct_mutex); | |
9bb2d6f9 | 4527 | return ret; |
d816f6ac | 4528 | } |
9bb2d6f9 | 4529 | |
5cef07e1 | 4530 | BUG_ON(!list_empty(&dev_priv->gtt.base.active_list)); |
673a394b | 4531 | mutex_unlock(&dev->struct_mutex); |
dbb19d30 | 4532 | |
5f35308b CW |
4533 | ret = drm_irq_install(dev); |
4534 | if (ret) | |
4535 | goto cleanup_ringbuffer; | |
dbb19d30 | 4536 | |
673a394b | 4537 | return 0; |
5f35308b CW |
4538 | |
4539 | cleanup_ringbuffer: | |
4540 | mutex_lock(&dev->struct_mutex); | |
4541 | i915_gem_cleanup_ringbuffer(dev); | |
db1b76ca | 4542 | dev_priv->ums.mm_suspended = 1; |
5f35308b CW |
4543 | mutex_unlock(&dev->struct_mutex); |
4544 | ||
4545 | return ret; | |
673a394b EA |
4546 | } |
4547 | ||
4548 | int | |
4549 | i915_gem_leavevt_ioctl(struct drm_device *dev, void *data, | |
4550 | struct drm_file *file_priv) | |
4551 | { | |
79e53945 JB |
4552 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
4553 | return 0; | |
4554 | ||
dbb19d30 | 4555 | drm_irq_uninstall(dev); |
db1b76ca | 4556 | |
45c5f202 | 4557 | return i915_gem_suspend(dev); |
673a394b EA |
4558 | } |
4559 | ||
4560 | void | |
4561 | i915_gem_lastclose(struct drm_device *dev) | |
4562 | { | |
4563 | int ret; | |
673a394b | 4564 | |
e806b495 EA |
4565 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
4566 | return; | |
4567 | ||
45c5f202 | 4568 | ret = i915_gem_suspend(dev); |
6dbe2772 KP |
4569 | if (ret) |
4570 | DRM_ERROR("failed to idle hardware: %d\n", ret); | |
673a394b EA |
4571 | } |
4572 | ||
64193406 CW |
4573 | static void |
4574 | init_ring_lists(struct intel_ring_buffer *ring) | |
4575 | { | |
4576 | INIT_LIST_HEAD(&ring->active_list); | |
4577 | INIT_LIST_HEAD(&ring->request_list); | |
64193406 CW |
4578 | } |
4579 | ||
7e0d96bc BW |
4580 | void i915_init_vm(struct drm_i915_private *dev_priv, |
4581 | struct i915_address_space *vm) | |
fc8c067e | 4582 | { |
7e0d96bc BW |
4583 | if (!i915_is_ggtt(vm)) |
4584 | drm_mm_init(&vm->mm, vm->start, vm->total); | |
fc8c067e BW |
4585 | vm->dev = dev_priv->dev; |
4586 | INIT_LIST_HEAD(&vm->active_list); | |
4587 | INIT_LIST_HEAD(&vm->inactive_list); | |
4588 | INIT_LIST_HEAD(&vm->global_link); | |
f72d21ed | 4589 | list_add_tail(&vm->global_link, &dev_priv->vm_list); |
fc8c067e BW |
4590 | } |
4591 | ||
673a394b EA |
4592 | void |
4593 | i915_gem_load(struct drm_device *dev) | |
4594 | { | |
4595 | drm_i915_private_t *dev_priv = dev->dev_private; | |
42dcedd4 CW |
4596 | int i; |
4597 | ||
4598 | dev_priv->slab = | |
4599 | kmem_cache_create("i915_gem_object", | |
4600 | sizeof(struct drm_i915_gem_object), 0, | |
4601 | SLAB_HWCACHE_ALIGN, | |
4602 | NULL); | |
673a394b | 4603 | |
fc8c067e BW |
4604 | INIT_LIST_HEAD(&dev_priv->vm_list); |
4605 | i915_init_vm(dev_priv, &dev_priv->gtt.base); | |
4606 | ||
a33afea5 | 4607 | INIT_LIST_HEAD(&dev_priv->context_list); |
6c085a72 CW |
4608 | INIT_LIST_HEAD(&dev_priv->mm.unbound_list); |
4609 | INIT_LIST_HEAD(&dev_priv->mm.bound_list); | |
a09ba7fa | 4610 | INIT_LIST_HEAD(&dev_priv->mm.fence_list); |
1ec14ad3 CW |
4611 | for (i = 0; i < I915_NUM_RINGS; i++) |
4612 | init_ring_lists(&dev_priv->ring[i]); | |
4b9de737 | 4613 | for (i = 0; i < I915_MAX_NUM_FENCES; i++) |
007cc8ac | 4614 | INIT_LIST_HEAD(&dev_priv->fence_regs[i].lru_list); |
673a394b EA |
4615 | INIT_DELAYED_WORK(&dev_priv->mm.retire_work, |
4616 | i915_gem_retire_work_handler); | |
b29c19b6 CW |
4617 | INIT_DELAYED_WORK(&dev_priv->mm.idle_work, |
4618 | i915_gem_idle_work_handler); | |
1f83fee0 | 4619 | init_waitqueue_head(&dev_priv->gpu_error.reset_queue); |
31169714 | 4620 | |
94400120 DA |
4621 | /* On GEN3 we really need to make sure the ARB C3 LP bit is set */ |
4622 | if (IS_GEN3(dev)) { | |
50743298 DV |
4623 | I915_WRITE(MI_ARB_STATE, |
4624 | _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE)); | |
94400120 DA |
4625 | } |
4626 | ||
72bfa19c CW |
4627 | dev_priv->relative_constants_mode = I915_EXEC_CONSTANTS_REL_GENERAL; |
4628 | ||
de151cf6 | 4629 | /* Old X drivers will take 0-2 for front, back, depth buffers */ |
b397c836 EA |
4630 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) |
4631 | dev_priv->fence_reg_start = 3; | |
de151cf6 | 4632 | |
42b5aeab VS |
4633 | if (INTEL_INFO(dev)->gen >= 7 && !IS_VALLEYVIEW(dev)) |
4634 | dev_priv->num_fence_regs = 32; | |
4635 | else if (INTEL_INFO(dev)->gen >= 4 || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) | |
de151cf6 JB |
4636 | dev_priv->num_fence_regs = 16; |
4637 | else | |
4638 | dev_priv->num_fence_regs = 8; | |
4639 | ||
b5aa8a0f | 4640 | /* Initialize fence registers to zero */ |
19b2dbde CW |
4641 | INIT_LIST_HEAD(&dev_priv->mm.fence_list); |
4642 | i915_gem_restore_fences(dev); | |
10ed13e4 | 4643 | |
673a394b | 4644 | i915_gem_detect_bit_6_swizzle(dev); |
6b95a207 | 4645 | init_waitqueue_head(&dev_priv->pending_flip_queue); |
17250b71 | 4646 | |
ce453d81 CW |
4647 | dev_priv->mm.interruptible = true; |
4648 | ||
7dc19d5a DC |
4649 | dev_priv->mm.inactive_shrinker.scan_objects = i915_gem_inactive_scan; |
4650 | dev_priv->mm.inactive_shrinker.count_objects = i915_gem_inactive_count; | |
17250b71 CW |
4651 | dev_priv->mm.inactive_shrinker.seeks = DEFAULT_SEEKS; |
4652 | register_shrinker(&dev_priv->mm.inactive_shrinker); | |
673a394b | 4653 | } |
71acb5eb DA |
4654 | |
4655 | /* | |
4656 | * Create a physically contiguous memory object for this object | |
4657 | * e.g. for cursor + overlay regs | |
4658 | */ | |
995b6762 CW |
4659 | static int i915_gem_init_phys_object(struct drm_device *dev, |
4660 | int id, int size, int align) | |
71acb5eb DA |
4661 | { |
4662 | drm_i915_private_t *dev_priv = dev->dev_private; | |
4663 | struct drm_i915_gem_phys_object *phys_obj; | |
4664 | int ret; | |
4665 | ||
4666 | if (dev_priv->mm.phys_objs[id - 1] || !size) | |
4667 | return 0; | |
4668 | ||
b14c5679 | 4669 | phys_obj = kzalloc(sizeof(*phys_obj), GFP_KERNEL); |
71acb5eb DA |
4670 | if (!phys_obj) |
4671 | return -ENOMEM; | |
4672 | ||
4673 | phys_obj->id = id; | |
4674 | ||
6eeefaf3 | 4675 | phys_obj->handle = drm_pci_alloc(dev, size, align); |
71acb5eb DA |
4676 | if (!phys_obj->handle) { |
4677 | ret = -ENOMEM; | |
4678 | goto kfree_obj; | |
4679 | } | |
4680 | #ifdef CONFIG_X86 | |
4681 | set_memory_wc((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE); | |
4682 | #endif | |
4683 | ||
4684 | dev_priv->mm.phys_objs[id - 1] = phys_obj; | |
4685 | ||
4686 | return 0; | |
4687 | kfree_obj: | |
9a298b2a | 4688 | kfree(phys_obj); |
71acb5eb DA |
4689 | return ret; |
4690 | } | |
4691 | ||
995b6762 | 4692 | static void i915_gem_free_phys_object(struct drm_device *dev, int id) |
71acb5eb DA |
4693 | { |
4694 | drm_i915_private_t *dev_priv = dev->dev_private; | |
4695 | struct drm_i915_gem_phys_object *phys_obj; | |
4696 | ||
4697 | if (!dev_priv->mm.phys_objs[id - 1]) | |
4698 | return; | |
4699 | ||
4700 | phys_obj = dev_priv->mm.phys_objs[id - 1]; | |
4701 | if (phys_obj->cur_obj) { | |
4702 | i915_gem_detach_phys_object(dev, phys_obj->cur_obj); | |
4703 | } | |
4704 | ||
4705 | #ifdef CONFIG_X86 | |
4706 | set_memory_wb((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE); | |
4707 | #endif | |
4708 | drm_pci_free(dev, phys_obj->handle); | |
4709 | kfree(phys_obj); | |
4710 | dev_priv->mm.phys_objs[id - 1] = NULL; | |
4711 | } | |
4712 | ||
4713 | void i915_gem_free_all_phys_object(struct drm_device *dev) | |
4714 | { | |
4715 | int i; | |
4716 | ||
260883c8 | 4717 | for (i = I915_GEM_PHYS_CURSOR_0; i <= I915_MAX_PHYS_OBJECT; i++) |
71acb5eb DA |
4718 | i915_gem_free_phys_object(dev, i); |
4719 | } | |
4720 | ||
4721 | void i915_gem_detach_phys_object(struct drm_device *dev, | |
05394f39 | 4722 | struct drm_i915_gem_object *obj) |
71acb5eb | 4723 | { |
496ad9aa | 4724 | struct address_space *mapping = file_inode(obj->base.filp)->i_mapping; |
e5281ccd | 4725 | char *vaddr; |
71acb5eb | 4726 | int i; |
71acb5eb DA |
4727 | int page_count; |
4728 | ||
05394f39 | 4729 | if (!obj->phys_obj) |
71acb5eb | 4730 | return; |
05394f39 | 4731 | vaddr = obj->phys_obj->handle->vaddr; |
71acb5eb | 4732 | |
05394f39 | 4733 | page_count = obj->base.size / PAGE_SIZE; |
71acb5eb | 4734 | for (i = 0; i < page_count; i++) { |
5949eac4 | 4735 | struct page *page = shmem_read_mapping_page(mapping, i); |
e5281ccd CW |
4736 | if (!IS_ERR(page)) { |
4737 | char *dst = kmap_atomic(page); | |
4738 | memcpy(dst, vaddr + i*PAGE_SIZE, PAGE_SIZE); | |
4739 | kunmap_atomic(dst); | |
4740 | ||
4741 | drm_clflush_pages(&page, 1); | |
4742 | ||
4743 | set_page_dirty(page); | |
4744 | mark_page_accessed(page); | |
4745 | page_cache_release(page); | |
4746 | } | |
71acb5eb | 4747 | } |
e76e9aeb | 4748 | i915_gem_chipset_flush(dev); |
d78b47b9 | 4749 | |
05394f39 CW |
4750 | obj->phys_obj->cur_obj = NULL; |
4751 | obj->phys_obj = NULL; | |
71acb5eb DA |
4752 | } |
4753 | ||
4754 | int | |
4755 | i915_gem_attach_phys_object(struct drm_device *dev, | |
05394f39 | 4756 | struct drm_i915_gem_object *obj, |
6eeefaf3 CW |
4757 | int id, |
4758 | int align) | |
71acb5eb | 4759 | { |
496ad9aa | 4760 | struct address_space *mapping = file_inode(obj->base.filp)->i_mapping; |
71acb5eb | 4761 | drm_i915_private_t *dev_priv = dev->dev_private; |
71acb5eb DA |
4762 | int ret = 0; |
4763 | int page_count; | |
4764 | int i; | |
4765 | ||
4766 | if (id > I915_MAX_PHYS_OBJECT) | |
4767 | return -EINVAL; | |
4768 | ||
05394f39 CW |
4769 | if (obj->phys_obj) { |
4770 | if (obj->phys_obj->id == id) | |
71acb5eb DA |
4771 | return 0; |
4772 | i915_gem_detach_phys_object(dev, obj); | |
4773 | } | |
4774 | ||
71acb5eb DA |
4775 | /* create a new object */ |
4776 | if (!dev_priv->mm.phys_objs[id - 1]) { | |
4777 | ret = i915_gem_init_phys_object(dev, id, | |
05394f39 | 4778 | obj->base.size, align); |
71acb5eb | 4779 | if (ret) { |
05394f39 CW |
4780 | DRM_ERROR("failed to init phys object %d size: %zu\n", |
4781 | id, obj->base.size); | |
e5281ccd | 4782 | return ret; |
71acb5eb DA |
4783 | } |
4784 | } | |
4785 | ||
4786 | /* bind to the object */ | |
05394f39 CW |
4787 | obj->phys_obj = dev_priv->mm.phys_objs[id - 1]; |
4788 | obj->phys_obj->cur_obj = obj; | |
71acb5eb | 4789 | |
05394f39 | 4790 | page_count = obj->base.size / PAGE_SIZE; |
71acb5eb DA |
4791 | |
4792 | for (i = 0; i < page_count; i++) { | |
e5281ccd CW |
4793 | struct page *page; |
4794 | char *dst, *src; | |
4795 | ||
5949eac4 | 4796 | page = shmem_read_mapping_page(mapping, i); |
e5281ccd CW |
4797 | if (IS_ERR(page)) |
4798 | return PTR_ERR(page); | |
71acb5eb | 4799 | |
ff75b9bc | 4800 | src = kmap_atomic(page); |
05394f39 | 4801 | dst = obj->phys_obj->handle->vaddr + (i * PAGE_SIZE); |
71acb5eb | 4802 | memcpy(dst, src, PAGE_SIZE); |
3e4d3af5 | 4803 | kunmap_atomic(src); |
71acb5eb | 4804 | |
e5281ccd CW |
4805 | mark_page_accessed(page); |
4806 | page_cache_release(page); | |
4807 | } | |
d78b47b9 | 4808 | |
71acb5eb | 4809 | return 0; |
71acb5eb DA |
4810 | } |
4811 | ||
4812 | static int | |
05394f39 CW |
4813 | i915_gem_phys_pwrite(struct drm_device *dev, |
4814 | struct drm_i915_gem_object *obj, | |
71acb5eb DA |
4815 | struct drm_i915_gem_pwrite *args, |
4816 | struct drm_file *file_priv) | |
4817 | { | |
05394f39 | 4818 | void *vaddr = obj->phys_obj->handle->vaddr + args->offset; |
2bb4629a | 4819 | char __user *user_data = to_user_ptr(args->data_ptr); |
71acb5eb | 4820 | |
b47b30cc CW |
4821 | if (__copy_from_user_inatomic_nocache(vaddr, user_data, args->size)) { |
4822 | unsigned long unwritten; | |
4823 | ||
4824 | /* The physical object once assigned is fixed for the lifetime | |
4825 | * of the obj, so we can safely drop the lock and continue | |
4826 | * to access vaddr. | |
4827 | */ | |
4828 | mutex_unlock(&dev->struct_mutex); | |
4829 | unwritten = copy_from_user(vaddr, user_data, args->size); | |
4830 | mutex_lock(&dev->struct_mutex); | |
4831 | if (unwritten) | |
4832 | return -EFAULT; | |
4833 | } | |
71acb5eb | 4834 | |
e76e9aeb | 4835 | i915_gem_chipset_flush(dev); |
71acb5eb DA |
4836 | return 0; |
4837 | } | |
b962442e | 4838 | |
f787a5f5 | 4839 | void i915_gem_release(struct drm_device *dev, struct drm_file *file) |
b962442e | 4840 | { |
f787a5f5 | 4841 | struct drm_i915_file_private *file_priv = file->driver_priv; |
b962442e | 4842 | |
b29c19b6 CW |
4843 | cancel_delayed_work_sync(&file_priv->mm.idle_work); |
4844 | ||
b962442e EA |
4845 | /* Clean up our request list when the client is going away, so that |
4846 | * later retire_requests won't dereference our soon-to-be-gone | |
4847 | * file_priv. | |
4848 | */ | |
1c25595f | 4849 | spin_lock(&file_priv->mm.lock); |
f787a5f5 CW |
4850 | while (!list_empty(&file_priv->mm.request_list)) { |
4851 | struct drm_i915_gem_request *request; | |
4852 | ||
4853 | request = list_first_entry(&file_priv->mm.request_list, | |
4854 | struct drm_i915_gem_request, | |
4855 | client_list); | |
4856 | list_del(&request->client_list); | |
4857 | request->file_priv = NULL; | |
4858 | } | |
1c25595f | 4859 | spin_unlock(&file_priv->mm.lock); |
b962442e | 4860 | } |
31169714 | 4861 | |
b29c19b6 CW |
4862 | static void |
4863 | i915_gem_file_idle_work_handler(struct work_struct *work) | |
4864 | { | |
4865 | struct drm_i915_file_private *file_priv = | |
4866 | container_of(work, typeof(*file_priv), mm.idle_work.work); | |
4867 | ||
4868 | atomic_set(&file_priv->rps_wait_boost, false); | |
4869 | } | |
4870 | ||
4871 | int i915_gem_open(struct drm_device *dev, struct drm_file *file) | |
4872 | { | |
4873 | struct drm_i915_file_private *file_priv; | |
e422b888 | 4874 | int ret; |
b29c19b6 CW |
4875 | |
4876 | DRM_DEBUG_DRIVER("\n"); | |
4877 | ||
4878 | file_priv = kzalloc(sizeof(*file_priv), GFP_KERNEL); | |
4879 | if (!file_priv) | |
4880 | return -ENOMEM; | |
4881 | ||
4882 | file->driver_priv = file_priv; | |
4883 | file_priv->dev_priv = dev->dev_private; | |
ab0e7ff9 | 4884 | file_priv->file = file; |
b29c19b6 CW |
4885 | |
4886 | spin_lock_init(&file_priv->mm.lock); | |
4887 | INIT_LIST_HEAD(&file_priv->mm.request_list); | |
4888 | INIT_DELAYED_WORK(&file_priv->mm.idle_work, | |
4889 | i915_gem_file_idle_work_handler); | |
4890 | ||
e422b888 BW |
4891 | ret = i915_gem_context_open(dev, file); |
4892 | if (ret) | |
4893 | kfree(file_priv); | |
b29c19b6 | 4894 | |
e422b888 | 4895 | return ret; |
b29c19b6 CW |
4896 | } |
4897 | ||
5774506f CW |
4898 | static bool mutex_is_locked_by(struct mutex *mutex, struct task_struct *task) |
4899 | { | |
4900 | if (!mutex_is_locked(mutex)) | |
4901 | return false; | |
4902 | ||
4903 | #if defined(CONFIG_SMP) || defined(CONFIG_DEBUG_MUTEXES) | |
4904 | return mutex->owner == task; | |
4905 | #else | |
4906 | /* Since UP may be pre-empted, we cannot assume that we own the lock */ | |
4907 | return false; | |
4908 | #endif | |
4909 | } | |
4910 | ||
7dc19d5a DC |
4911 | static unsigned long |
4912 | i915_gem_inactive_count(struct shrinker *shrinker, struct shrink_control *sc) | |
31169714 | 4913 | { |
17250b71 CW |
4914 | struct drm_i915_private *dev_priv = |
4915 | container_of(shrinker, | |
4916 | struct drm_i915_private, | |
4917 | mm.inactive_shrinker); | |
4918 | struct drm_device *dev = dev_priv->dev; | |
6c085a72 | 4919 | struct drm_i915_gem_object *obj; |
5774506f | 4920 | bool unlock = true; |
7dc19d5a | 4921 | unsigned long count; |
17250b71 | 4922 | |
5774506f CW |
4923 | if (!mutex_trylock(&dev->struct_mutex)) { |
4924 | if (!mutex_is_locked_by(&dev->struct_mutex, current)) | |
d3227046 | 4925 | return 0; |
5774506f | 4926 | |
677feac2 | 4927 | if (dev_priv->mm.shrinker_no_lock_stealing) |
d3227046 | 4928 | return 0; |
677feac2 | 4929 | |
5774506f CW |
4930 | unlock = false; |
4931 | } | |
31169714 | 4932 | |
7dc19d5a | 4933 | count = 0; |
35c20a60 | 4934 | list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) |
a5570178 | 4935 | if (obj->pages_pin_count == 0) |
7dc19d5a | 4936 | count += obj->base.size >> PAGE_SHIFT; |
fcb4a578 BW |
4937 | |
4938 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) { | |
4939 | if (obj->active) | |
4940 | continue; | |
4941 | ||
d7f46fc4 | 4942 | if (!i915_gem_obj_is_pinned(obj) && obj->pages_pin_count == 0) |
7dc19d5a | 4943 | count += obj->base.size >> PAGE_SHIFT; |
fcb4a578 | 4944 | } |
17250b71 | 4945 | |
5774506f CW |
4946 | if (unlock) |
4947 | mutex_unlock(&dev->struct_mutex); | |
d9973b43 | 4948 | |
7dc19d5a | 4949 | return count; |
31169714 | 4950 | } |
a70a3148 BW |
4951 | |
4952 | /* All the new VM stuff */ | |
4953 | unsigned long i915_gem_obj_offset(struct drm_i915_gem_object *o, | |
4954 | struct i915_address_space *vm) | |
4955 | { | |
4956 | struct drm_i915_private *dev_priv = o->base.dev->dev_private; | |
4957 | struct i915_vma *vma; | |
4958 | ||
6f425321 BW |
4959 | if (!dev_priv->mm.aliasing_ppgtt || |
4960 | vm == &dev_priv->mm.aliasing_ppgtt->base) | |
a70a3148 BW |
4961 | vm = &dev_priv->gtt.base; |
4962 | ||
4963 | BUG_ON(list_empty(&o->vma_list)); | |
4964 | list_for_each_entry(vma, &o->vma_list, vma_link) { | |
4965 | if (vma->vm == vm) | |
4966 | return vma->node.start; | |
4967 | ||
4968 | } | |
4969 | return -1; | |
4970 | } | |
4971 | ||
4972 | bool i915_gem_obj_bound(struct drm_i915_gem_object *o, | |
4973 | struct i915_address_space *vm) | |
4974 | { | |
4975 | struct i915_vma *vma; | |
4976 | ||
4977 | list_for_each_entry(vma, &o->vma_list, vma_link) | |
8b9c2b94 | 4978 | if (vma->vm == vm && drm_mm_node_allocated(&vma->node)) |
a70a3148 BW |
4979 | return true; |
4980 | ||
4981 | return false; | |
4982 | } | |
4983 | ||
4984 | bool i915_gem_obj_bound_any(struct drm_i915_gem_object *o) | |
4985 | { | |
5a1d5eb0 | 4986 | struct i915_vma *vma; |
a70a3148 | 4987 | |
5a1d5eb0 CW |
4988 | list_for_each_entry(vma, &o->vma_list, vma_link) |
4989 | if (drm_mm_node_allocated(&vma->node)) | |
a70a3148 BW |
4990 | return true; |
4991 | ||
4992 | return false; | |
4993 | } | |
4994 | ||
4995 | unsigned long i915_gem_obj_size(struct drm_i915_gem_object *o, | |
4996 | struct i915_address_space *vm) | |
4997 | { | |
4998 | struct drm_i915_private *dev_priv = o->base.dev->dev_private; | |
4999 | struct i915_vma *vma; | |
5000 | ||
6f425321 BW |
5001 | if (!dev_priv->mm.aliasing_ppgtt || |
5002 | vm == &dev_priv->mm.aliasing_ppgtt->base) | |
a70a3148 BW |
5003 | vm = &dev_priv->gtt.base; |
5004 | ||
5005 | BUG_ON(list_empty(&o->vma_list)); | |
5006 | ||
5007 | list_for_each_entry(vma, &o->vma_list, vma_link) | |
5008 | if (vma->vm == vm) | |
5009 | return vma->node.size; | |
5010 | ||
5011 | return 0; | |
5012 | } | |
5013 | ||
7dc19d5a DC |
5014 | static unsigned long |
5015 | i915_gem_inactive_scan(struct shrinker *shrinker, struct shrink_control *sc) | |
5016 | { | |
5017 | struct drm_i915_private *dev_priv = | |
5018 | container_of(shrinker, | |
5019 | struct drm_i915_private, | |
5020 | mm.inactive_shrinker); | |
5021 | struct drm_device *dev = dev_priv->dev; | |
7dc19d5a DC |
5022 | unsigned long freed; |
5023 | bool unlock = true; | |
5024 | ||
5025 | if (!mutex_trylock(&dev->struct_mutex)) { | |
5026 | if (!mutex_is_locked_by(&dev->struct_mutex, current)) | |
d3227046 | 5027 | return SHRINK_STOP; |
7dc19d5a DC |
5028 | |
5029 | if (dev_priv->mm.shrinker_no_lock_stealing) | |
d3227046 | 5030 | return SHRINK_STOP; |
7dc19d5a DC |
5031 | |
5032 | unlock = false; | |
5033 | } | |
5034 | ||
d9973b43 CW |
5035 | freed = i915_gem_purge(dev_priv, sc->nr_to_scan); |
5036 | if (freed < sc->nr_to_scan) | |
5037 | freed += __i915_gem_shrink(dev_priv, | |
5038 | sc->nr_to_scan - freed, | |
5039 | false); | |
5040 | if (freed < sc->nr_to_scan) | |
7dc19d5a DC |
5041 | freed += i915_gem_shrink_all(dev_priv); |
5042 | ||
5043 | if (unlock) | |
5044 | mutex_unlock(&dev->struct_mutex); | |
d9973b43 | 5045 | |
7dc19d5a DC |
5046 | return freed; |
5047 | } | |
5c2abbea BW |
5048 | |
5049 | struct i915_vma *i915_gem_obj_to_ggtt(struct drm_i915_gem_object *obj) | |
5050 | { | |
5051 | struct i915_vma *vma; | |
5052 | ||
5053 | if (WARN_ON(list_empty(&obj->vma_list))) | |
5054 | return NULL; | |
5055 | ||
5056 | vma = list_first_entry(&obj->vma_list, typeof(*vma), vma_link); | |
6e164c33 | 5057 | if (vma->vm != obj_to_ggtt(obj)) |
5c2abbea BW |
5058 | return NULL; |
5059 | ||
5060 | return vma; | |
5061 | } |