Commit | Line | Data |
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673a394b EA |
1 | /* |
2 | * Copyright © 2008 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | * | |
26 | */ | |
27 | ||
28 | #include "drmP.h" | |
29 | #include "drm.h" | |
30 | #include "i915_drm.h" | |
31 | #include "i915_drv.h" | |
32 | #include <linux/swap.h> | |
79e53945 | 33 | #include <linux/pci.h> |
673a394b | 34 | |
28dfe52a EA |
35 | #define I915_GEM_GPU_DOMAINS (~(I915_GEM_DOMAIN_CPU | I915_GEM_DOMAIN_GTT)) |
36 | ||
c0d90829 KP |
37 | static void |
38 | i915_gem_object_set_to_gpu_domain(struct drm_gem_object *obj, | |
39 | uint32_t read_domains, | |
40 | uint32_t write_domain); | |
e47c68e9 EA |
41 | static void i915_gem_object_flush_gpu_write_domain(struct drm_gem_object *obj); |
42 | static void i915_gem_object_flush_gtt_write_domain(struct drm_gem_object *obj); | |
43 | static void i915_gem_object_flush_cpu_write_domain(struct drm_gem_object *obj); | |
e47c68e9 EA |
44 | static int i915_gem_object_set_to_cpu_domain(struct drm_gem_object *obj, |
45 | int write); | |
46 | static int i915_gem_object_set_cpu_read_domain_range(struct drm_gem_object *obj, | |
47 | uint64_t offset, | |
48 | uint64_t size); | |
49 | static void i915_gem_object_set_to_full_cpu_read_domain(struct drm_gem_object *obj); | |
673a394b EA |
50 | static int i915_gem_object_get_page_list(struct drm_gem_object *obj); |
51 | static void i915_gem_object_free_page_list(struct drm_gem_object *obj); | |
52 | static int i915_gem_object_wait_rendering(struct drm_gem_object *obj); | |
de151cf6 JB |
53 | static int i915_gem_object_bind_to_gtt(struct drm_gem_object *obj, |
54 | unsigned alignment); | |
55 | static void i915_gem_object_get_fence_reg(struct drm_gem_object *obj); | |
56 | static void i915_gem_clear_fence_reg(struct drm_gem_object *obj); | |
57 | static int i915_gem_evict_something(struct drm_device *dev); | |
673a394b | 58 | |
79e53945 JB |
59 | int i915_gem_do_init(struct drm_device *dev, unsigned long start, |
60 | unsigned long end) | |
673a394b EA |
61 | { |
62 | drm_i915_private_t *dev_priv = dev->dev_private; | |
673a394b | 63 | |
79e53945 JB |
64 | if (start >= end || |
65 | (start & (PAGE_SIZE - 1)) != 0 || | |
66 | (end & (PAGE_SIZE - 1)) != 0) { | |
673a394b EA |
67 | return -EINVAL; |
68 | } | |
69 | ||
79e53945 JB |
70 | drm_mm_init(&dev_priv->mm.gtt_space, start, |
71 | end - start); | |
673a394b | 72 | |
79e53945 JB |
73 | dev->gtt_total = (uint32_t) (end - start); |
74 | ||
75 | return 0; | |
76 | } | |
673a394b | 77 | |
79e53945 JB |
78 | int |
79 | i915_gem_init_ioctl(struct drm_device *dev, void *data, | |
80 | struct drm_file *file_priv) | |
81 | { | |
82 | struct drm_i915_gem_init *args = data; | |
83 | int ret; | |
84 | ||
85 | mutex_lock(&dev->struct_mutex); | |
86 | ret = i915_gem_do_init(dev, args->gtt_start, args->gtt_end); | |
673a394b EA |
87 | mutex_unlock(&dev->struct_mutex); |
88 | ||
79e53945 | 89 | return ret; |
673a394b EA |
90 | } |
91 | ||
5a125c3c EA |
92 | int |
93 | i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data, | |
94 | struct drm_file *file_priv) | |
95 | { | |
5a125c3c | 96 | struct drm_i915_gem_get_aperture *args = data; |
5a125c3c EA |
97 | |
98 | if (!(dev->driver->driver_features & DRIVER_GEM)) | |
99 | return -ENODEV; | |
100 | ||
101 | args->aper_size = dev->gtt_total; | |
2678d9d6 KP |
102 | args->aper_available_size = (args->aper_size - |
103 | atomic_read(&dev->pin_memory)); | |
5a125c3c EA |
104 | |
105 | return 0; | |
106 | } | |
107 | ||
673a394b EA |
108 | |
109 | /** | |
110 | * Creates a new mm object and returns a handle to it. | |
111 | */ | |
112 | int | |
113 | i915_gem_create_ioctl(struct drm_device *dev, void *data, | |
114 | struct drm_file *file_priv) | |
115 | { | |
116 | struct drm_i915_gem_create *args = data; | |
117 | struct drm_gem_object *obj; | |
118 | int handle, ret; | |
119 | ||
120 | args->size = roundup(args->size, PAGE_SIZE); | |
121 | ||
122 | /* Allocate the new object */ | |
123 | obj = drm_gem_object_alloc(dev, args->size); | |
124 | if (obj == NULL) | |
125 | return -ENOMEM; | |
126 | ||
127 | ret = drm_gem_handle_create(file_priv, obj, &handle); | |
128 | mutex_lock(&dev->struct_mutex); | |
129 | drm_gem_object_handle_unreference(obj); | |
130 | mutex_unlock(&dev->struct_mutex); | |
131 | ||
132 | if (ret) | |
133 | return ret; | |
134 | ||
135 | args->handle = handle; | |
136 | ||
137 | return 0; | |
138 | } | |
139 | ||
140 | /** | |
141 | * Reads data from the object referenced by handle. | |
142 | * | |
143 | * On error, the contents of *data are undefined. | |
144 | */ | |
145 | int | |
146 | i915_gem_pread_ioctl(struct drm_device *dev, void *data, | |
147 | struct drm_file *file_priv) | |
148 | { | |
149 | struct drm_i915_gem_pread *args = data; | |
150 | struct drm_gem_object *obj; | |
151 | struct drm_i915_gem_object *obj_priv; | |
152 | ssize_t read; | |
153 | loff_t offset; | |
154 | int ret; | |
155 | ||
156 | obj = drm_gem_object_lookup(dev, file_priv, args->handle); | |
157 | if (obj == NULL) | |
158 | return -EBADF; | |
159 | obj_priv = obj->driver_private; | |
160 | ||
161 | /* Bounds check source. | |
162 | * | |
163 | * XXX: This could use review for overflow issues... | |
164 | */ | |
165 | if (args->offset > obj->size || args->size > obj->size || | |
166 | args->offset + args->size > obj->size) { | |
167 | drm_gem_object_unreference(obj); | |
168 | return -EINVAL; | |
169 | } | |
170 | ||
171 | mutex_lock(&dev->struct_mutex); | |
172 | ||
e47c68e9 EA |
173 | ret = i915_gem_object_set_cpu_read_domain_range(obj, args->offset, |
174 | args->size); | |
673a394b EA |
175 | if (ret != 0) { |
176 | drm_gem_object_unreference(obj); | |
177 | mutex_unlock(&dev->struct_mutex); | |
e7d22bc3 | 178 | return ret; |
673a394b EA |
179 | } |
180 | ||
181 | offset = args->offset; | |
182 | ||
183 | read = vfs_read(obj->filp, (char __user *)(uintptr_t)args->data_ptr, | |
184 | args->size, &offset); | |
185 | if (read != args->size) { | |
186 | drm_gem_object_unreference(obj); | |
187 | mutex_unlock(&dev->struct_mutex); | |
188 | if (read < 0) | |
189 | return read; | |
190 | else | |
191 | return -EINVAL; | |
192 | } | |
193 | ||
194 | drm_gem_object_unreference(obj); | |
195 | mutex_unlock(&dev->struct_mutex); | |
196 | ||
197 | return 0; | |
198 | } | |
199 | ||
0839ccb8 KP |
200 | /* This is the fast write path which cannot handle |
201 | * page faults in the source data | |
9b7530cc | 202 | */ |
0839ccb8 KP |
203 | |
204 | static inline int | |
205 | fast_user_write(struct io_mapping *mapping, | |
206 | loff_t page_base, int page_offset, | |
207 | char __user *user_data, | |
208 | int length) | |
9b7530cc | 209 | { |
9b7530cc | 210 | char *vaddr_atomic; |
0839ccb8 | 211 | unsigned long unwritten; |
9b7530cc | 212 | |
0839ccb8 KP |
213 | vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base); |
214 | unwritten = __copy_from_user_inatomic_nocache(vaddr_atomic + page_offset, | |
215 | user_data, length); | |
216 | io_mapping_unmap_atomic(vaddr_atomic); | |
217 | if (unwritten) | |
218 | return -EFAULT; | |
219 | return 0; | |
220 | } | |
221 | ||
222 | /* Here's the write path which can sleep for | |
223 | * page faults | |
224 | */ | |
225 | ||
226 | static inline int | |
227 | slow_user_write(struct io_mapping *mapping, | |
228 | loff_t page_base, int page_offset, | |
229 | char __user *user_data, | |
230 | int length) | |
231 | { | |
232 | char __iomem *vaddr; | |
233 | unsigned long unwritten; | |
234 | ||
235 | vaddr = io_mapping_map_wc(mapping, page_base); | |
236 | if (vaddr == NULL) | |
237 | return -EFAULT; | |
238 | unwritten = __copy_from_user(vaddr + page_offset, | |
239 | user_data, length); | |
240 | io_mapping_unmap(vaddr); | |
241 | if (unwritten) | |
242 | return -EFAULT; | |
9b7530cc | 243 | return 0; |
9b7530cc LT |
244 | } |
245 | ||
673a394b EA |
246 | static int |
247 | i915_gem_gtt_pwrite(struct drm_device *dev, struct drm_gem_object *obj, | |
248 | struct drm_i915_gem_pwrite *args, | |
249 | struct drm_file *file_priv) | |
250 | { | |
251 | struct drm_i915_gem_object *obj_priv = obj->driver_private; | |
0839ccb8 | 252 | drm_i915_private_t *dev_priv = dev->dev_private; |
673a394b | 253 | ssize_t remain; |
0839ccb8 | 254 | loff_t offset, page_base; |
673a394b | 255 | char __user *user_data; |
0839ccb8 KP |
256 | int page_offset, page_length; |
257 | int ret; | |
673a394b EA |
258 | |
259 | user_data = (char __user *) (uintptr_t) args->data_ptr; | |
260 | remain = args->size; | |
261 | if (!access_ok(VERIFY_READ, user_data, remain)) | |
262 | return -EFAULT; | |
263 | ||
264 | ||
265 | mutex_lock(&dev->struct_mutex); | |
266 | ret = i915_gem_object_pin(obj, 0); | |
267 | if (ret) { | |
268 | mutex_unlock(&dev->struct_mutex); | |
269 | return ret; | |
270 | } | |
2ef7eeaa | 271 | ret = i915_gem_object_set_to_gtt_domain(obj, 1); |
673a394b EA |
272 | if (ret) |
273 | goto fail; | |
274 | ||
275 | obj_priv = obj->driver_private; | |
276 | offset = obj_priv->gtt_offset + args->offset; | |
277 | obj_priv->dirty = 1; | |
278 | ||
279 | while (remain > 0) { | |
280 | /* Operation in this page | |
281 | * | |
0839ccb8 KP |
282 | * page_base = page offset within aperture |
283 | * page_offset = offset within page | |
284 | * page_length = bytes to copy for this page | |
673a394b | 285 | */ |
0839ccb8 KP |
286 | page_base = (offset & ~(PAGE_SIZE-1)); |
287 | page_offset = offset & (PAGE_SIZE-1); | |
288 | page_length = remain; | |
289 | if ((page_offset + remain) > PAGE_SIZE) | |
290 | page_length = PAGE_SIZE - page_offset; | |
291 | ||
292 | ret = fast_user_write (dev_priv->mm.gtt_mapping, page_base, | |
293 | page_offset, user_data, page_length); | |
294 | ||
295 | /* If we get a fault while copying data, then (presumably) our | |
296 | * source page isn't available. In this case, use the | |
297 | * non-atomic function | |
298 | */ | |
299 | if (ret) { | |
300 | ret = slow_user_write (dev_priv->mm.gtt_mapping, | |
301 | page_base, page_offset, | |
302 | user_data, page_length); | |
303 | if (ret) | |
673a394b | 304 | goto fail; |
673a394b EA |
305 | } |
306 | ||
0839ccb8 KP |
307 | remain -= page_length; |
308 | user_data += page_length; | |
309 | offset += page_length; | |
673a394b | 310 | } |
673a394b EA |
311 | |
312 | fail: | |
313 | i915_gem_object_unpin(obj); | |
314 | mutex_unlock(&dev->struct_mutex); | |
315 | ||
316 | return ret; | |
317 | } | |
318 | ||
3043c60c | 319 | static int |
673a394b EA |
320 | i915_gem_shmem_pwrite(struct drm_device *dev, struct drm_gem_object *obj, |
321 | struct drm_i915_gem_pwrite *args, | |
322 | struct drm_file *file_priv) | |
323 | { | |
324 | int ret; | |
325 | loff_t offset; | |
326 | ssize_t written; | |
327 | ||
328 | mutex_lock(&dev->struct_mutex); | |
329 | ||
e47c68e9 | 330 | ret = i915_gem_object_set_to_cpu_domain(obj, 1); |
673a394b EA |
331 | if (ret) { |
332 | mutex_unlock(&dev->struct_mutex); | |
333 | return ret; | |
334 | } | |
335 | ||
336 | offset = args->offset; | |
337 | ||
338 | written = vfs_write(obj->filp, | |
339 | (char __user *)(uintptr_t) args->data_ptr, | |
340 | args->size, &offset); | |
341 | if (written != args->size) { | |
342 | mutex_unlock(&dev->struct_mutex); | |
343 | if (written < 0) | |
344 | return written; | |
345 | else | |
346 | return -EINVAL; | |
347 | } | |
348 | ||
349 | mutex_unlock(&dev->struct_mutex); | |
350 | ||
351 | return 0; | |
352 | } | |
353 | ||
354 | /** | |
355 | * Writes data to the object referenced by handle. | |
356 | * | |
357 | * On error, the contents of the buffer that were to be modified are undefined. | |
358 | */ | |
359 | int | |
360 | i915_gem_pwrite_ioctl(struct drm_device *dev, void *data, | |
361 | struct drm_file *file_priv) | |
362 | { | |
363 | struct drm_i915_gem_pwrite *args = data; | |
364 | struct drm_gem_object *obj; | |
365 | struct drm_i915_gem_object *obj_priv; | |
366 | int ret = 0; | |
367 | ||
368 | obj = drm_gem_object_lookup(dev, file_priv, args->handle); | |
369 | if (obj == NULL) | |
370 | return -EBADF; | |
371 | obj_priv = obj->driver_private; | |
372 | ||
373 | /* Bounds check destination. | |
374 | * | |
375 | * XXX: This could use review for overflow issues... | |
376 | */ | |
377 | if (args->offset > obj->size || args->size > obj->size || | |
378 | args->offset + args->size > obj->size) { | |
379 | drm_gem_object_unreference(obj); | |
380 | return -EINVAL; | |
381 | } | |
382 | ||
383 | /* We can only do the GTT pwrite on untiled buffers, as otherwise | |
384 | * it would end up going through the fenced access, and we'll get | |
385 | * different detiling behavior between reading and writing. | |
386 | * pread/pwrite currently are reading and writing from the CPU | |
387 | * perspective, requiring manual detiling by the client. | |
388 | */ | |
389 | if (obj_priv->tiling_mode == I915_TILING_NONE && | |
390 | dev->gtt_total != 0) | |
391 | ret = i915_gem_gtt_pwrite(dev, obj, args, file_priv); | |
392 | else | |
393 | ret = i915_gem_shmem_pwrite(dev, obj, args, file_priv); | |
394 | ||
395 | #if WATCH_PWRITE | |
396 | if (ret) | |
397 | DRM_INFO("pwrite failed %d\n", ret); | |
398 | #endif | |
399 | ||
400 | drm_gem_object_unreference(obj); | |
401 | ||
402 | return ret; | |
403 | } | |
404 | ||
405 | /** | |
2ef7eeaa EA |
406 | * Called when user space prepares to use an object with the CPU, either |
407 | * through the mmap ioctl's mapping or a GTT mapping. | |
673a394b EA |
408 | */ |
409 | int | |
410 | i915_gem_set_domain_ioctl(struct drm_device *dev, void *data, | |
411 | struct drm_file *file_priv) | |
412 | { | |
413 | struct drm_i915_gem_set_domain *args = data; | |
414 | struct drm_gem_object *obj; | |
2ef7eeaa EA |
415 | uint32_t read_domains = args->read_domains; |
416 | uint32_t write_domain = args->write_domain; | |
673a394b EA |
417 | int ret; |
418 | ||
419 | if (!(dev->driver->driver_features & DRIVER_GEM)) | |
420 | return -ENODEV; | |
421 | ||
2ef7eeaa EA |
422 | /* Only handle setting domains to types used by the CPU. */ |
423 | if (write_domain & ~(I915_GEM_DOMAIN_CPU | I915_GEM_DOMAIN_GTT)) | |
424 | return -EINVAL; | |
425 | ||
426 | if (read_domains & ~(I915_GEM_DOMAIN_CPU | I915_GEM_DOMAIN_GTT)) | |
427 | return -EINVAL; | |
428 | ||
429 | /* Having something in the write domain implies it's in the read | |
430 | * domain, and only that read domain. Enforce that in the request. | |
431 | */ | |
432 | if (write_domain != 0 && read_domains != write_domain) | |
433 | return -EINVAL; | |
434 | ||
673a394b EA |
435 | obj = drm_gem_object_lookup(dev, file_priv, args->handle); |
436 | if (obj == NULL) | |
437 | return -EBADF; | |
438 | ||
439 | mutex_lock(&dev->struct_mutex); | |
440 | #if WATCH_BUF | |
441 | DRM_INFO("set_domain_ioctl %p(%d), %08x %08x\n", | |
2ef7eeaa | 442 | obj, obj->size, read_domains, write_domain); |
673a394b | 443 | #endif |
2ef7eeaa EA |
444 | if (read_domains & I915_GEM_DOMAIN_GTT) { |
445 | ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0); | |
02354392 EA |
446 | |
447 | /* Silently promote "you're not bound, there was nothing to do" | |
448 | * to success, since the client was just asking us to | |
449 | * make sure everything was done. | |
450 | */ | |
451 | if (ret == -EINVAL) | |
452 | ret = 0; | |
2ef7eeaa | 453 | } else { |
e47c68e9 | 454 | ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0); |
2ef7eeaa EA |
455 | } |
456 | ||
673a394b EA |
457 | drm_gem_object_unreference(obj); |
458 | mutex_unlock(&dev->struct_mutex); | |
459 | return ret; | |
460 | } | |
461 | ||
462 | /** | |
463 | * Called when user space has done writes to this buffer | |
464 | */ | |
465 | int | |
466 | i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data, | |
467 | struct drm_file *file_priv) | |
468 | { | |
469 | struct drm_i915_gem_sw_finish *args = data; | |
470 | struct drm_gem_object *obj; | |
471 | struct drm_i915_gem_object *obj_priv; | |
472 | int ret = 0; | |
473 | ||
474 | if (!(dev->driver->driver_features & DRIVER_GEM)) | |
475 | return -ENODEV; | |
476 | ||
477 | mutex_lock(&dev->struct_mutex); | |
478 | obj = drm_gem_object_lookup(dev, file_priv, args->handle); | |
479 | if (obj == NULL) { | |
480 | mutex_unlock(&dev->struct_mutex); | |
481 | return -EBADF; | |
482 | } | |
483 | ||
484 | #if WATCH_BUF | |
485 | DRM_INFO("%s: sw_finish %d (%p %d)\n", | |
486 | __func__, args->handle, obj, obj->size); | |
487 | #endif | |
488 | obj_priv = obj->driver_private; | |
489 | ||
490 | /* Pinned buffers may be scanout, so flush the cache */ | |
e47c68e9 EA |
491 | if (obj_priv->pin_count) |
492 | i915_gem_object_flush_cpu_write_domain(obj); | |
493 | ||
673a394b EA |
494 | drm_gem_object_unreference(obj); |
495 | mutex_unlock(&dev->struct_mutex); | |
496 | return ret; | |
497 | } | |
498 | ||
499 | /** | |
500 | * Maps the contents of an object, returning the address it is mapped | |
501 | * into. | |
502 | * | |
503 | * While the mapping holds a reference on the contents of the object, it doesn't | |
504 | * imply a ref on the object itself. | |
505 | */ | |
506 | int | |
507 | i915_gem_mmap_ioctl(struct drm_device *dev, void *data, | |
508 | struct drm_file *file_priv) | |
509 | { | |
510 | struct drm_i915_gem_mmap *args = data; | |
511 | struct drm_gem_object *obj; | |
512 | loff_t offset; | |
513 | unsigned long addr; | |
514 | ||
515 | if (!(dev->driver->driver_features & DRIVER_GEM)) | |
516 | return -ENODEV; | |
517 | ||
518 | obj = drm_gem_object_lookup(dev, file_priv, args->handle); | |
519 | if (obj == NULL) | |
520 | return -EBADF; | |
521 | ||
522 | offset = args->offset; | |
523 | ||
524 | down_write(¤t->mm->mmap_sem); | |
525 | addr = do_mmap(obj->filp, 0, args->size, | |
526 | PROT_READ | PROT_WRITE, MAP_SHARED, | |
527 | args->offset); | |
528 | up_write(¤t->mm->mmap_sem); | |
529 | mutex_lock(&dev->struct_mutex); | |
530 | drm_gem_object_unreference(obj); | |
531 | mutex_unlock(&dev->struct_mutex); | |
532 | if (IS_ERR((void *)addr)) | |
533 | return addr; | |
534 | ||
535 | args->addr_ptr = (uint64_t) addr; | |
536 | ||
537 | return 0; | |
538 | } | |
539 | ||
de151cf6 JB |
540 | /** |
541 | * i915_gem_fault - fault a page into the GTT | |
542 | * vma: VMA in question | |
543 | * vmf: fault info | |
544 | * | |
545 | * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped | |
546 | * from userspace. The fault handler takes care of binding the object to | |
547 | * the GTT (if needed), allocating and programming a fence register (again, | |
548 | * only if needed based on whether the old reg is still valid or the object | |
549 | * is tiled) and inserting a new PTE into the faulting process. | |
550 | * | |
551 | * Note that the faulting process may involve evicting existing objects | |
552 | * from the GTT and/or fence registers to make room. So performance may | |
553 | * suffer if the GTT working set is large or there are few fence registers | |
554 | * left. | |
555 | */ | |
556 | int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf) | |
557 | { | |
558 | struct drm_gem_object *obj = vma->vm_private_data; | |
559 | struct drm_device *dev = obj->dev; | |
560 | struct drm_i915_private *dev_priv = dev->dev_private; | |
561 | struct drm_i915_gem_object *obj_priv = obj->driver_private; | |
562 | pgoff_t page_offset; | |
563 | unsigned long pfn; | |
564 | int ret = 0; | |
565 | ||
566 | /* We don't use vmf->pgoff since that has the fake offset */ | |
567 | page_offset = ((unsigned long)vmf->virtual_address - vma->vm_start) >> | |
568 | PAGE_SHIFT; | |
569 | ||
570 | /* Now bind it into the GTT if needed */ | |
571 | mutex_lock(&dev->struct_mutex); | |
572 | if (!obj_priv->gtt_space) { | |
573 | ret = i915_gem_object_bind_to_gtt(obj, obj_priv->gtt_alignment); | |
574 | if (ret) { | |
575 | mutex_unlock(&dev->struct_mutex); | |
576 | return VM_FAULT_SIGBUS; | |
577 | } | |
578 | list_add(&obj_priv->list, &dev_priv->mm.inactive_list); | |
579 | } | |
580 | ||
581 | /* Need a new fence register? */ | |
582 | if (obj_priv->fence_reg == I915_FENCE_REG_NONE && | |
583 | obj_priv->tiling_mode != I915_TILING_NONE) | |
584 | i915_gem_object_get_fence_reg(obj); | |
585 | ||
586 | pfn = ((dev->agp->base + obj_priv->gtt_offset) >> PAGE_SHIFT) + | |
587 | page_offset; | |
588 | ||
589 | /* Finally, remap it using the new GTT offset */ | |
590 | ret = vm_insert_pfn(vma, (unsigned long)vmf->virtual_address, pfn); | |
591 | ||
592 | mutex_unlock(&dev->struct_mutex); | |
593 | ||
594 | switch (ret) { | |
595 | case -ENOMEM: | |
596 | case -EAGAIN: | |
597 | return VM_FAULT_OOM; | |
598 | case -EFAULT: | |
599 | case -EBUSY: | |
600 | DRM_ERROR("can't insert pfn?? fault or busy...\n"); | |
601 | return VM_FAULT_SIGBUS; | |
602 | default: | |
603 | return VM_FAULT_NOPAGE; | |
604 | } | |
605 | } | |
606 | ||
607 | /** | |
608 | * i915_gem_create_mmap_offset - create a fake mmap offset for an object | |
609 | * @obj: obj in question | |
610 | * | |
611 | * GEM memory mapping works by handing back to userspace a fake mmap offset | |
612 | * it can use in a subsequent mmap(2) call. The DRM core code then looks | |
613 | * up the object based on the offset and sets up the various memory mapping | |
614 | * structures. | |
615 | * | |
616 | * This routine allocates and attaches a fake offset for @obj. | |
617 | */ | |
618 | static int | |
619 | i915_gem_create_mmap_offset(struct drm_gem_object *obj) | |
620 | { | |
621 | struct drm_device *dev = obj->dev; | |
622 | struct drm_gem_mm *mm = dev->mm_private; | |
623 | struct drm_i915_gem_object *obj_priv = obj->driver_private; | |
624 | struct drm_map_list *list; | |
625 | struct drm_map *map; | |
626 | int ret = 0; | |
627 | ||
628 | /* Set the object up for mmap'ing */ | |
629 | list = &obj->map_list; | |
630 | list->map = drm_calloc(1, sizeof(struct drm_map_list), | |
631 | DRM_MEM_DRIVER); | |
632 | if (!list->map) | |
633 | return -ENOMEM; | |
634 | ||
635 | map = list->map; | |
636 | map->type = _DRM_GEM; | |
637 | map->size = obj->size; | |
638 | map->handle = obj; | |
639 | ||
640 | /* Get a DRM GEM mmap offset allocated... */ | |
641 | list->file_offset_node = drm_mm_search_free(&mm->offset_manager, | |
642 | obj->size / PAGE_SIZE, 0, 0); | |
643 | if (!list->file_offset_node) { | |
644 | DRM_ERROR("failed to allocate offset for bo %d\n", obj->name); | |
645 | ret = -ENOMEM; | |
646 | goto out_free_list; | |
647 | } | |
648 | ||
649 | list->file_offset_node = drm_mm_get_block(list->file_offset_node, | |
650 | obj->size / PAGE_SIZE, 0); | |
651 | if (!list->file_offset_node) { | |
652 | ret = -ENOMEM; | |
653 | goto out_free_list; | |
654 | } | |
655 | ||
656 | list->hash.key = list->file_offset_node->start; | |
657 | if (drm_ht_insert_item(&mm->offset_hash, &list->hash)) { | |
658 | DRM_ERROR("failed to add to map hash\n"); | |
659 | goto out_free_mm; | |
660 | } | |
661 | ||
662 | /* By now we should be all set, any drm_mmap request on the offset | |
663 | * below will get to our mmap & fault handler */ | |
664 | obj_priv->mmap_offset = ((uint64_t) list->hash.key) << PAGE_SHIFT; | |
665 | ||
666 | return 0; | |
667 | ||
668 | out_free_mm: | |
669 | drm_mm_put_block(list->file_offset_node); | |
670 | out_free_list: | |
671 | drm_free(list->map, sizeof(struct drm_map_list), DRM_MEM_DRIVER); | |
672 | ||
673 | return ret; | |
674 | } | |
675 | ||
676 | /** | |
677 | * i915_gem_get_gtt_alignment - return required GTT alignment for an object | |
678 | * @obj: object to check | |
679 | * | |
680 | * Return the required GTT alignment for an object, taking into account | |
681 | * potential fence register mapping if needed. | |
682 | */ | |
683 | static uint32_t | |
684 | i915_gem_get_gtt_alignment(struct drm_gem_object *obj) | |
685 | { | |
686 | struct drm_device *dev = obj->dev; | |
687 | struct drm_i915_gem_object *obj_priv = obj->driver_private; | |
688 | int start, i; | |
689 | ||
690 | /* | |
691 | * Minimum alignment is 4k (GTT page size), but might be greater | |
692 | * if a fence register is needed for the object. | |
693 | */ | |
694 | if (IS_I965G(dev) || obj_priv->tiling_mode == I915_TILING_NONE) | |
695 | return 4096; | |
696 | ||
697 | /* | |
698 | * Previous chips need to be aligned to the size of the smallest | |
699 | * fence register that can contain the object. | |
700 | */ | |
701 | if (IS_I9XX(dev)) | |
702 | start = 1024*1024; | |
703 | else | |
704 | start = 512*1024; | |
705 | ||
706 | for (i = start; i < obj->size; i <<= 1) | |
707 | ; | |
708 | ||
709 | return i; | |
710 | } | |
711 | ||
712 | /** | |
713 | * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing | |
714 | * @dev: DRM device | |
715 | * @data: GTT mapping ioctl data | |
716 | * @file_priv: GEM object info | |
717 | * | |
718 | * Simply returns the fake offset to userspace so it can mmap it. | |
719 | * The mmap call will end up in drm_gem_mmap(), which will set things | |
720 | * up so we can get faults in the handler above. | |
721 | * | |
722 | * The fault handler will take care of binding the object into the GTT | |
723 | * (since it may have been evicted to make room for something), allocating | |
724 | * a fence register, and mapping the appropriate aperture address into | |
725 | * userspace. | |
726 | */ | |
727 | int | |
728 | i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data, | |
729 | struct drm_file *file_priv) | |
730 | { | |
731 | struct drm_i915_gem_mmap_gtt *args = data; | |
732 | struct drm_i915_private *dev_priv = dev->dev_private; | |
733 | struct drm_gem_object *obj; | |
734 | struct drm_i915_gem_object *obj_priv; | |
735 | int ret; | |
736 | ||
737 | if (!(dev->driver->driver_features & DRIVER_GEM)) | |
738 | return -ENODEV; | |
739 | ||
740 | obj = drm_gem_object_lookup(dev, file_priv, args->handle); | |
741 | if (obj == NULL) | |
742 | return -EBADF; | |
743 | ||
744 | mutex_lock(&dev->struct_mutex); | |
745 | ||
746 | obj_priv = obj->driver_private; | |
747 | ||
748 | if (!obj_priv->mmap_offset) { | |
749 | ret = i915_gem_create_mmap_offset(obj); | |
750 | if (ret) | |
751 | return ret; | |
752 | } | |
753 | ||
754 | args->offset = obj_priv->mmap_offset; | |
755 | ||
756 | obj_priv->gtt_alignment = i915_gem_get_gtt_alignment(obj); | |
757 | ||
758 | /* Make sure the alignment is correct for fence regs etc */ | |
759 | if (obj_priv->agp_mem && | |
760 | (obj_priv->gtt_offset & (obj_priv->gtt_alignment - 1))) { | |
761 | drm_gem_object_unreference(obj); | |
762 | mutex_unlock(&dev->struct_mutex); | |
763 | return -EINVAL; | |
764 | } | |
765 | ||
766 | /* | |
767 | * Pull it into the GTT so that we have a page list (makes the | |
768 | * initial fault faster and any subsequent flushing possible). | |
769 | */ | |
770 | if (!obj_priv->agp_mem) { | |
771 | ret = i915_gem_object_bind_to_gtt(obj, obj_priv->gtt_alignment); | |
772 | if (ret) { | |
773 | drm_gem_object_unreference(obj); | |
774 | mutex_unlock(&dev->struct_mutex); | |
775 | return ret; | |
776 | } | |
777 | list_add(&obj_priv->list, &dev_priv->mm.inactive_list); | |
778 | } | |
779 | ||
780 | drm_gem_object_unreference(obj); | |
781 | mutex_unlock(&dev->struct_mutex); | |
782 | ||
783 | return 0; | |
784 | } | |
785 | ||
673a394b EA |
786 | static void |
787 | i915_gem_object_free_page_list(struct drm_gem_object *obj) | |
788 | { | |
789 | struct drm_i915_gem_object *obj_priv = obj->driver_private; | |
790 | int page_count = obj->size / PAGE_SIZE; | |
791 | int i; | |
792 | ||
793 | if (obj_priv->page_list == NULL) | |
794 | return; | |
795 | ||
796 | ||
797 | for (i = 0; i < page_count; i++) | |
798 | if (obj_priv->page_list[i] != NULL) { | |
799 | if (obj_priv->dirty) | |
800 | set_page_dirty(obj_priv->page_list[i]); | |
801 | mark_page_accessed(obj_priv->page_list[i]); | |
802 | page_cache_release(obj_priv->page_list[i]); | |
803 | } | |
804 | obj_priv->dirty = 0; | |
805 | ||
806 | drm_free(obj_priv->page_list, | |
807 | page_count * sizeof(struct page *), | |
808 | DRM_MEM_DRIVER); | |
809 | obj_priv->page_list = NULL; | |
810 | } | |
811 | ||
812 | static void | |
ce44b0ea | 813 | i915_gem_object_move_to_active(struct drm_gem_object *obj, uint32_t seqno) |
673a394b EA |
814 | { |
815 | struct drm_device *dev = obj->dev; | |
816 | drm_i915_private_t *dev_priv = dev->dev_private; | |
817 | struct drm_i915_gem_object *obj_priv = obj->driver_private; | |
818 | ||
819 | /* Add a reference if we're newly entering the active list. */ | |
820 | if (!obj_priv->active) { | |
821 | drm_gem_object_reference(obj); | |
822 | obj_priv->active = 1; | |
823 | } | |
824 | /* Move from whatever list we were on to the tail of execution. */ | |
825 | list_move_tail(&obj_priv->list, | |
826 | &dev_priv->mm.active_list); | |
ce44b0ea | 827 | obj_priv->last_rendering_seqno = seqno; |
673a394b EA |
828 | } |
829 | ||
ce44b0ea EA |
830 | static void |
831 | i915_gem_object_move_to_flushing(struct drm_gem_object *obj) | |
832 | { | |
833 | struct drm_device *dev = obj->dev; | |
834 | drm_i915_private_t *dev_priv = dev->dev_private; | |
835 | struct drm_i915_gem_object *obj_priv = obj->driver_private; | |
836 | ||
837 | BUG_ON(!obj_priv->active); | |
838 | list_move_tail(&obj_priv->list, &dev_priv->mm.flushing_list); | |
839 | obj_priv->last_rendering_seqno = 0; | |
840 | } | |
673a394b EA |
841 | |
842 | static void | |
843 | i915_gem_object_move_to_inactive(struct drm_gem_object *obj) | |
844 | { | |
845 | struct drm_device *dev = obj->dev; | |
846 | drm_i915_private_t *dev_priv = dev->dev_private; | |
847 | struct drm_i915_gem_object *obj_priv = obj->driver_private; | |
848 | ||
849 | i915_verify_inactive(dev, __FILE__, __LINE__); | |
850 | if (obj_priv->pin_count != 0) | |
851 | list_del_init(&obj_priv->list); | |
852 | else | |
853 | list_move_tail(&obj_priv->list, &dev_priv->mm.inactive_list); | |
854 | ||
ce44b0ea | 855 | obj_priv->last_rendering_seqno = 0; |
673a394b EA |
856 | if (obj_priv->active) { |
857 | obj_priv->active = 0; | |
858 | drm_gem_object_unreference(obj); | |
859 | } | |
860 | i915_verify_inactive(dev, __FILE__, __LINE__); | |
861 | } | |
862 | ||
863 | /** | |
864 | * Creates a new sequence number, emitting a write of it to the status page | |
865 | * plus an interrupt, which will trigger i915_user_interrupt_handler. | |
866 | * | |
867 | * Must be called with struct_lock held. | |
868 | * | |
869 | * Returned sequence numbers are nonzero on success. | |
870 | */ | |
871 | static uint32_t | |
872 | i915_add_request(struct drm_device *dev, uint32_t flush_domains) | |
873 | { | |
874 | drm_i915_private_t *dev_priv = dev->dev_private; | |
875 | struct drm_i915_gem_request *request; | |
876 | uint32_t seqno; | |
877 | int was_empty; | |
878 | RING_LOCALS; | |
879 | ||
880 | request = drm_calloc(1, sizeof(*request), DRM_MEM_DRIVER); | |
881 | if (request == NULL) | |
882 | return 0; | |
883 | ||
884 | /* Grab the seqno we're going to make this request be, and bump the | |
885 | * next (skipping 0 so it can be the reserved no-seqno value). | |
886 | */ | |
887 | seqno = dev_priv->mm.next_gem_seqno; | |
888 | dev_priv->mm.next_gem_seqno++; | |
889 | if (dev_priv->mm.next_gem_seqno == 0) | |
890 | dev_priv->mm.next_gem_seqno++; | |
891 | ||
892 | BEGIN_LP_RING(4); | |
893 | OUT_RING(MI_STORE_DWORD_INDEX); | |
894 | OUT_RING(I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT); | |
895 | OUT_RING(seqno); | |
896 | ||
897 | OUT_RING(MI_USER_INTERRUPT); | |
898 | ADVANCE_LP_RING(); | |
899 | ||
900 | DRM_DEBUG("%d\n", seqno); | |
901 | ||
902 | request->seqno = seqno; | |
903 | request->emitted_jiffies = jiffies; | |
673a394b EA |
904 | was_empty = list_empty(&dev_priv->mm.request_list); |
905 | list_add_tail(&request->list, &dev_priv->mm.request_list); | |
906 | ||
ce44b0ea EA |
907 | /* Associate any objects on the flushing list matching the write |
908 | * domain we're flushing with our flush. | |
909 | */ | |
910 | if (flush_domains != 0) { | |
911 | struct drm_i915_gem_object *obj_priv, *next; | |
912 | ||
913 | list_for_each_entry_safe(obj_priv, next, | |
914 | &dev_priv->mm.flushing_list, list) { | |
915 | struct drm_gem_object *obj = obj_priv->obj; | |
916 | ||
917 | if ((obj->write_domain & flush_domains) == | |
918 | obj->write_domain) { | |
919 | obj->write_domain = 0; | |
920 | i915_gem_object_move_to_active(obj, seqno); | |
921 | } | |
922 | } | |
923 | ||
924 | } | |
925 | ||
6dbe2772 | 926 | if (was_empty && !dev_priv->mm.suspended) |
673a394b EA |
927 | schedule_delayed_work(&dev_priv->mm.retire_work, HZ); |
928 | return seqno; | |
929 | } | |
930 | ||
931 | /** | |
932 | * Command execution barrier | |
933 | * | |
934 | * Ensures that all commands in the ring are finished | |
935 | * before signalling the CPU | |
936 | */ | |
3043c60c | 937 | static uint32_t |
673a394b EA |
938 | i915_retire_commands(struct drm_device *dev) |
939 | { | |
940 | drm_i915_private_t *dev_priv = dev->dev_private; | |
941 | uint32_t cmd = MI_FLUSH | MI_NO_WRITE_FLUSH; | |
942 | uint32_t flush_domains = 0; | |
943 | RING_LOCALS; | |
944 | ||
945 | /* The sampler always gets flushed on i965 (sigh) */ | |
946 | if (IS_I965G(dev)) | |
947 | flush_domains |= I915_GEM_DOMAIN_SAMPLER; | |
948 | BEGIN_LP_RING(2); | |
949 | OUT_RING(cmd); | |
950 | OUT_RING(0); /* noop */ | |
951 | ADVANCE_LP_RING(); | |
952 | return flush_domains; | |
953 | } | |
954 | ||
955 | /** | |
956 | * Moves buffers associated only with the given active seqno from the active | |
957 | * to inactive list, potentially freeing them. | |
958 | */ | |
959 | static void | |
960 | i915_gem_retire_request(struct drm_device *dev, | |
961 | struct drm_i915_gem_request *request) | |
962 | { | |
963 | drm_i915_private_t *dev_priv = dev->dev_private; | |
964 | ||
965 | /* Move any buffers on the active list that are no longer referenced | |
966 | * by the ringbuffer to the flushing/inactive lists as appropriate. | |
967 | */ | |
968 | while (!list_empty(&dev_priv->mm.active_list)) { | |
969 | struct drm_gem_object *obj; | |
970 | struct drm_i915_gem_object *obj_priv; | |
971 | ||
972 | obj_priv = list_first_entry(&dev_priv->mm.active_list, | |
973 | struct drm_i915_gem_object, | |
974 | list); | |
975 | obj = obj_priv->obj; | |
976 | ||
977 | /* If the seqno being retired doesn't match the oldest in the | |
978 | * list, then the oldest in the list must still be newer than | |
979 | * this seqno. | |
980 | */ | |
981 | if (obj_priv->last_rendering_seqno != request->seqno) | |
982 | return; | |
de151cf6 | 983 | |
673a394b EA |
984 | #if WATCH_LRU |
985 | DRM_INFO("%s: retire %d moves to inactive list %p\n", | |
986 | __func__, request->seqno, obj); | |
987 | #endif | |
988 | ||
ce44b0ea EA |
989 | if (obj->write_domain != 0) |
990 | i915_gem_object_move_to_flushing(obj); | |
991 | else | |
673a394b | 992 | i915_gem_object_move_to_inactive(obj); |
673a394b EA |
993 | } |
994 | } | |
995 | ||
996 | /** | |
997 | * Returns true if seq1 is later than seq2. | |
998 | */ | |
999 | static int | |
1000 | i915_seqno_passed(uint32_t seq1, uint32_t seq2) | |
1001 | { | |
1002 | return (int32_t)(seq1 - seq2) >= 0; | |
1003 | } | |
1004 | ||
1005 | uint32_t | |
1006 | i915_get_gem_seqno(struct drm_device *dev) | |
1007 | { | |
1008 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1009 | ||
1010 | return READ_HWSP(dev_priv, I915_GEM_HWS_INDEX); | |
1011 | } | |
1012 | ||
1013 | /** | |
1014 | * This function clears the request list as sequence numbers are passed. | |
1015 | */ | |
1016 | void | |
1017 | i915_gem_retire_requests(struct drm_device *dev) | |
1018 | { | |
1019 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1020 | uint32_t seqno; | |
1021 | ||
1022 | seqno = i915_get_gem_seqno(dev); | |
1023 | ||
1024 | while (!list_empty(&dev_priv->mm.request_list)) { | |
1025 | struct drm_i915_gem_request *request; | |
1026 | uint32_t retiring_seqno; | |
1027 | ||
1028 | request = list_first_entry(&dev_priv->mm.request_list, | |
1029 | struct drm_i915_gem_request, | |
1030 | list); | |
1031 | retiring_seqno = request->seqno; | |
1032 | ||
1033 | if (i915_seqno_passed(seqno, retiring_seqno) || | |
1034 | dev_priv->mm.wedged) { | |
1035 | i915_gem_retire_request(dev, request); | |
1036 | ||
1037 | list_del(&request->list); | |
1038 | drm_free(request, sizeof(*request), DRM_MEM_DRIVER); | |
1039 | } else | |
1040 | break; | |
1041 | } | |
1042 | } | |
1043 | ||
1044 | void | |
1045 | i915_gem_retire_work_handler(struct work_struct *work) | |
1046 | { | |
1047 | drm_i915_private_t *dev_priv; | |
1048 | struct drm_device *dev; | |
1049 | ||
1050 | dev_priv = container_of(work, drm_i915_private_t, | |
1051 | mm.retire_work.work); | |
1052 | dev = dev_priv->dev; | |
1053 | ||
1054 | mutex_lock(&dev->struct_mutex); | |
1055 | i915_gem_retire_requests(dev); | |
6dbe2772 KP |
1056 | if (!dev_priv->mm.suspended && |
1057 | !list_empty(&dev_priv->mm.request_list)) | |
673a394b EA |
1058 | schedule_delayed_work(&dev_priv->mm.retire_work, HZ); |
1059 | mutex_unlock(&dev->struct_mutex); | |
1060 | } | |
1061 | ||
1062 | /** | |
1063 | * Waits for a sequence number to be signaled, and cleans up the | |
1064 | * request and object lists appropriately for that event. | |
1065 | */ | |
3043c60c | 1066 | static int |
673a394b EA |
1067 | i915_wait_request(struct drm_device *dev, uint32_t seqno) |
1068 | { | |
1069 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1070 | int ret = 0; | |
1071 | ||
1072 | BUG_ON(seqno == 0); | |
1073 | ||
1074 | if (!i915_seqno_passed(i915_get_gem_seqno(dev), seqno)) { | |
1075 | dev_priv->mm.waiting_gem_seqno = seqno; | |
1076 | i915_user_irq_get(dev); | |
1077 | ret = wait_event_interruptible(dev_priv->irq_queue, | |
1078 | i915_seqno_passed(i915_get_gem_seqno(dev), | |
1079 | seqno) || | |
1080 | dev_priv->mm.wedged); | |
1081 | i915_user_irq_put(dev); | |
1082 | dev_priv->mm.waiting_gem_seqno = 0; | |
1083 | } | |
1084 | if (dev_priv->mm.wedged) | |
1085 | ret = -EIO; | |
1086 | ||
1087 | if (ret && ret != -ERESTARTSYS) | |
1088 | DRM_ERROR("%s returns %d (awaiting %d at %d)\n", | |
1089 | __func__, ret, seqno, i915_get_gem_seqno(dev)); | |
1090 | ||
1091 | /* Directly dispatch request retiring. While we have the work queue | |
1092 | * to handle this, the waiter on a request often wants an associated | |
1093 | * buffer to have made it to the inactive list, and we would need | |
1094 | * a separate wait queue to handle that. | |
1095 | */ | |
1096 | if (ret == 0) | |
1097 | i915_gem_retire_requests(dev); | |
1098 | ||
1099 | return ret; | |
1100 | } | |
1101 | ||
1102 | static void | |
1103 | i915_gem_flush(struct drm_device *dev, | |
1104 | uint32_t invalidate_domains, | |
1105 | uint32_t flush_domains) | |
1106 | { | |
1107 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1108 | uint32_t cmd; | |
1109 | RING_LOCALS; | |
1110 | ||
1111 | #if WATCH_EXEC | |
1112 | DRM_INFO("%s: invalidate %08x flush %08x\n", __func__, | |
1113 | invalidate_domains, flush_domains); | |
1114 | #endif | |
1115 | ||
1116 | if (flush_domains & I915_GEM_DOMAIN_CPU) | |
1117 | drm_agp_chipset_flush(dev); | |
1118 | ||
1119 | if ((invalidate_domains | flush_domains) & ~(I915_GEM_DOMAIN_CPU | | |
1120 | I915_GEM_DOMAIN_GTT)) { | |
1121 | /* | |
1122 | * read/write caches: | |
1123 | * | |
1124 | * I915_GEM_DOMAIN_RENDER is always invalidated, but is | |
1125 | * only flushed if MI_NO_WRITE_FLUSH is unset. On 965, it is | |
1126 | * also flushed at 2d versus 3d pipeline switches. | |
1127 | * | |
1128 | * read-only caches: | |
1129 | * | |
1130 | * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if | |
1131 | * MI_READ_FLUSH is set, and is always flushed on 965. | |
1132 | * | |
1133 | * I915_GEM_DOMAIN_COMMAND may not exist? | |
1134 | * | |
1135 | * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is | |
1136 | * invalidated when MI_EXE_FLUSH is set. | |
1137 | * | |
1138 | * I915_GEM_DOMAIN_VERTEX, which exists on 965, is | |
1139 | * invalidated with every MI_FLUSH. | |
1140 | * | |
1141 | * TLBs: | |
1142 | * | |
1143 | * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND | |
1144 | * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and | |
1145 | * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER | |
1146 | * are flushed at any MI_FLUSH. | |
1147 | */ | |
1148 | ||
1149 | cmd = MI_FLUSH | MI_NO_WRITE_FLUSH; | |
1150 | if ((invalidate_domains|flush_domains) & | |
1151 | I915_GEM_DOMAIN_RENDER) | |
1152 | cmd &= ~MI_NO_WRITE_FLUSH; | |
1153 | if (!IS_I965G(dev)) { | |
1154 | /* | |
1155 | * On the 965, the sampler cache always gets flushed | |
1156 | * and this bit is reserved. | |
1157 | */ | |
1158 | if (invalidate_domains & I915_GEM_DOMAIN_SAMPLER) | |
1159 | cmd |= MI_READ_FLUSH; | |
1160 | } | |
1161 | if (invalidate_domains & I915_GEM_DOMAIN_INSTRUCTION) | |
1162 | cmd |= MI_EXE_FLUSH; | |
1163 | ||
1164 | #if WATCH_EXEC | |
1165 | DRM_INFO("%s: queue flush %08x to ring\n", __func__, cmd); | |
1166 | #endif | |
1167 | BEGIN_LP_RING(2); | |
1168 | OUT_RING(cmd); | |
1169 | OUT_RING(0); /* noop */ | |
1170 | ADVANCE_LP_RING(); | |
1171 | } | |
1172 | } | |
1173 | ||
1174 | /** | |
1175 | * Ensures that all rendering to the object has completed and the object is | |
1176 | * safe to unbind from the GTT or access from the CPU. | |
1177 | */ | |
1178 | static int | |
1179 | i915_gem_object_wait_rendering(struct drm_gem_object *obj) | |
1180 | { | |
1181 | struct drm_device *dev = obj->dev; | |
1182 | struct drm_i915_gem_object *obj_priv = obj->driver_private; | |
1183 | int ret; | |
1184 | ||
e47c68e9 EA |
1185 | /* This function only exists to support waiting for existing rendering, |
1186 | * not for emitting required flushes. | |
673a394b | 1187 | */ |
e47c68e9 | 1188 | BUG_ON((obj->write_domain & I915_GEM_GPU_DOMAINS) != 0); |
673a394b EA |
1189 | |
1190 | /* If there is rendering queued on the buffer being evicted, wait for | |
1191 | * it. | |
1192 | */ | |
1193 | if (obj_priv->active) { | |
1194 | #if WATCH_BUF | |
1195 | DRM_INFO("%s: object %p wait for seqno %08x\n", | |
1196 | __func__, obj, obj_priv->last_rendering_seqno); | |
1197 | #endif | |
1198 | ret = i915_wait_request(dev, obj_priv->last_rendering_seqno); | |
1199 | if (ret != 0) | |
1200 | return ret; | |
1201 | } | |
1202 | ||
1203 | return 0; | |
1204 | } | |
1205 | ||
1206 | /** | |
1207 | * Unbinds an object from the GTT aperture. | |
1208 | */ | |
1209 | static int | |
1210 | i915_gem_object_unbind(struct drm_gem_object *obj) | |
1211 | { | |
1212 | struct drm_device *dev = obj->dev; | |
1213 | struct drm_i915_gem_object *obj_priv = obj->driver_private; | |
de151cf6 | 1214 | loff_t offset; |
673a394b EA |
1215 | int ret = 0; |
1216 | ||
1217 | #if WATCH_BUF | |
1218 | DRM_INFO("%s:%d %p\n", __func__, __LINE__, obj); | |
1219 | DRM_INFO("gtt_space %p\n", obj_priv->gtt_space); | |
1220 | #endif | |
1221 | if (obj_priv->gtt_space == NULL) | |
1222 | return 0; | |
1223 | ||
1224 | if (obj_priv->pin_count != 0) { | |
1225 | DRM_ERROR("Attempting to unbind pinned buffer\n"); | |
1226 | return -EINVAL; | |
1227 | } | |
1228 | ||
673a394b EA |
1229 | /* Move the object to the CPU domain to ensure that |
1230 | * any possible CPU writes while it's not in the GTT | |
1231 | * are flushed when we go to remap it. This will | |
1232 | * also ensure that all pending GPU writes are finished | |
1233 | * before we unbind. | |
1234 | */ | |
e47c68e9 | 1235 | ret = i915_gem_object_set_to_cpu_domain(obj, 1); |
673a394b | 1236 | if (ret) { |
e47c68e9 EA |
1237 | if (ret != -ERESTARTSYS) |
1238 | DRM_ERROR("set_domain failed: %d\n", ret); | |
673a394b EA |
1239 | return ret; |
1240 | } | |
1241 | ||
1242 | if (obj_priv->agp_mem != NULL) { | |
1243 | drm_unbind_agp(obj_priv->agp_mem); | |
1244 | drm_free_agp(obj_priv->agp_mem, obj->size / PAGE_SIZE); | |
1245 | obj_priv->agp_mem = NULL; | |
1246 | } | |
1247 | ||
1248 | BUG_ON(obj_priv->active); | |
1249 | ||
de151cf6 JB |
1250 | /* blow away mappings if mapped through GTT */ |
1251 | offset = ((loff_t) obj->map_list.hash.key) << PAGE_SHIFT; | |
79e53945 JB |
1252 | if (dev->dev_mapping) |
1253 | unmap_mapping_range(dev->dev_mapping, offset, obj->size, 1); | |
de151cf6 JB |
1254 | |
1255 | if (obj_priv->fence_reg != I915_FENCE_REG_NONE) | |
1256 | i915_gem_clear_fence_reg(obj); | |
1257 | ||
673a394b EA |
1258 | i915_gem_object_free_page_list(obj); |
1259 | ||
1260 | if (obj_priv->gtt_space) { | |
1261 | atomic_dec(&dev->gtt_count); | |
1262 | atomic_sub(obj->size, &dev->gtt_memory); | |
1263 | ||
1264 | drm_mm_put_block(obj_priv->gtt_space); | |
1265 | obj_priv->gtt_space = NULL; | |
1266 | } | |
1267 | ||
1268 | /* Remove ourselves from the LRU list if present. */ | |
1269 | if (!list_empty(&obj_priv->list)) | |
1270 | list_del_init(&obj_priv->list); | |
1271 | ||
1272 | return 0; | |
1273 | } | |
1274 | ||
1275 | static int | |
1276 | i915_gem_evict_something(struct drm_device *dev) | |
1277 | { | |
1278 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1279 | struct drm_gem_object *obj; | |
1280 | struct drm_i915_gem_object *obj_priv; | |
1281 | int ret = 0; | |
1282 | ||
1283 | for (;;) { | |
1284 | /* If there's an inactive buffer available now, grab it | |
1285 | * and be done. | |
1286 | */ | |
1287 | if (!list_empty(&dev_priv->mm.inactive_list)) { | |
1288 | obj_priv = list_first_entry(&dev_priv->mm.inactive_list, | |
1289 | struct drm_i915_gem_object, | |
1290 | list); | |
1291 | obj = obj_priv->obj; | |
1292 | BUG_ON(obj_priv->pin_count != 0); | |
1293 | #if WATCH_LRU | |
1294 | DRM_INFO("%s: evicting %p\n", __func__, obj); | |
1295 | #endif | |
1296 | BUG_ON(obj_priv->active); | |
1297 | ||
1298 | /* Wait on the rendering and unbind the buffer. */ | |
1299 | ret = i915_gem_object_unbind(obj); | |
1300 | break; | |
1301 | } | |
1302 | ||
1303 | /* If we didn't get anything, but the ring is still processing | |
1304 | * things, wait for one of those things to finish and hopefully | |
1305 | * leave us a buffer to evict. | |
1306 | */ | |
1307 | if (!list_empty(&dev_priv->mm.request_list)) { | |
1308 | struct drm_i915_gem_request *request; | |
1309 | ||
1310 | request = list_first_entry(&dev_priv->mm.request_list, | |
1311 | struct drm_i915_gem_request, | |
1312 | list); | |
1313 | ||
1314 | ret = i915_wait_request(dev, request->seqno); | |
1315 | if (ret) | |
1316 | break; | |
1317 | ||
1318 | /* if waiting caused an object to become inactive, | |
1319 | * then loop around and wait for it. Otherwise, we | |
1320 | * assume that waiting freed and unbound something, | |
1321 | * so there should now be some space in the GTT | |
1322 | */ | |
1323 | if (!list_empty(&dev_priv->mm.inactive_list)) | |
1324 | continue; | |
1325 | break; | |
1326 | } | |
1327 | ||
1328 | /* If we didn't have anything on the request list but there | |
1329 | * are buffers awaiting a flush, emit one and try again. | |
1330 | * When we wait on it, those buffers waiting for that flush | |
1331 | * will get moved to inactive. | |
1332 | */ | |
1333 | if (!list_empty(&dev_priv->mm.flushing_list)) { | |
1334 | obj_priv = list_first_entry(&dev_priv->mm.flushing_list, | |
1335 | struct drm_i915_gem_object, | |
1336 | list); | |
1337 | obj = obj_priv->obj; | |
1338 | ||
1339 | i915_gem_flush(dev, | |
1340 | obj->write_domain, | |
1341 | obj->write_domain); | |
1342 | i915_add_request(dev, obj->write_domain); | |
1343 | ||
1344 | obj = NULL; | |
1345 | continue; | |
1346 | } | |
1347 | ||
1348 | DRM_ERROR("inactive empty %d request empty %d " | |
1349 | "flushing empty %d\n", | |
1350 | list_empty(&dev_priv->mm.inactive_list), | |
1351 | list_empty(&dev_priv->mm.request_list), | |
1352 | list_empty(&dev_priv->mm.flushing_list)); | |
1353 | /* If we didn't do any of the above, there's nothing to be done | |
1354 | * and we just can't fit it in. | |
1355 | */ | |
1356 | return -ENOMEM; | |
1357 | } | |
1358 | return ret; | |
1359 | } | |
1360 | ||
ac94a962 KP |
1361 | static int |
1362 | i915_gem_evict_everything(struct drm_device *dev) | |
1363 | { | |
1364 | int ret; | |
1365 | ||
1366 | for (;;) { | |
1367 | ret = i915_gem_evict_something(dev); | |
1368 | if (ret != 0) | |
1369 | break; | |
1370 | } | |
15c35334 OA |
1371 | if (ret == -ENOMEM) |
1372 | return 0; | |
ac94a962 KP |
1373 | return ret; |
1374 | } | |
1375 | ||
673a394b EA |
1376 | static int |
1377 | i915_gem_object_get_page_list(struct drm_gem_object *obj) | |
1378 | { | |
1379 | struct drm_i915_gem_object *obj_priv = obj->driver_private; | |
1380 | int page_count, i; | |
1381 | struct address_space *mapping; | |
1382 | struct inode *inode; | |
1383 | struct page *page; | |
1384 | int ret; | |
1385 | ||
1386 | if (obj_priv->page_list) | |
1387 | return 0; | |
1388 | ||
1389 | /* Get the list of pages out of our struct file. They'll be pinned | |
1390 | * at this point until we release them. | |
1391 | */ | |
1392 | page_count = obj->size / PAGE_SIZE; | |
1393 | BUG_ON(obj_priv->page_list != NULL); | |
1394 | obj_priv->page_list = drm_calloc(page_count, sizeof(struct page *), | |
1395 | DRM_MEM_DRIVER); | |
1396 | if (obj_priv->page_list == NULL) { | |
1397 | DRM_ERROR("Faled to allocate page list\n"); | |
1398 | return -ENOMEM; | |
1399 | } | |
1400 | ||
1401 | inode = obj->filp->f_path.dentry->d_inode; | |
1402 | mapping = inode->i_mapping; | |
1403 | for (i = 0; i < page_count; i++) { | |
1404 | page = read_mapping_page(mapping, i, NULL); | |
1405 | if (IS_ERR(page)) { | |
1406 | ret = PTR_ERR(page); | |
1407 | DRM_ERROR("read_mapping_page failed: %d\n", ret); | |
1408 | i915_gem_object_free_page_list(obj); | |
1409 | return ret; | |
1410 | } | |
1411 | obj_priv->page_list[i] = page; | |
1412 | } | |
1413 | return 0; | |
1414 | } | |
1415 | ||
de151cf6 JB |
1416 | static void i965_write_fence_reg(struct drm_i915_fence_reg *reg) |
1417 | { | |
1418 | struct drm_gem_object *obj = reg->obj; | |
1419 | struct drm_device *dev = obj->dev; | |
1420 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1421 | struct drm_i915_gem_object *obj_priv = obj->driver_private; | |
1422 | int regnum = obj_priv->fence_reg; | |
1423 | uint64_t val; | |
1424 | ||
1425 | val = (uint64_t)((obj_priv->gtt_offset + obj->size - 4096) & | |
1426 | 0xfffff000) << 32; | |
1427 | val |= obj_priv->gtt_offset & 0xfffff000; | |
1428 | val |= ((obj_priv->stride / 128) - 1) << I965_FENCE_PITCH_SHIFT; | |
1429 | if (obj_priv->tiling_mode == I915_TILING_Y) | |
1430 | val |= 1 << I965_FENCE_TILING_Y_SHIFT; | |
1431 | val |= I965_FENCE_REG_VALID; | |
1432 | ||
1433 | I915_WRITE64(FENCE_REG_965_0 + (regnum * 8), val); | |
1434 | } | |
1435 | ||
1436 | static void i915_write_fence_reg(struct drm_i915_fence_reg *reg) | |
1437 | { | |
1438 | struct drm_gem_object *obj = reg->obj; | |
1439 | struct drm_device *dev = obj->dev; | |
1440 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1441 | struct drm_i915_gem_object *obj_priv = obj->driver_private; | |
1442 | int regnum = obj_priv->fence_reg; | |
1443 | uint32_t val; | |
1444 | uint32_t pitch_val; | |
1445 | ||
1446 | if ((obj_priv->gtt_offset & ~I915_FENCE_START_MASK) || | |
1447 | (obj_priv->gtt_offset & (obj->size - 1))) { | |
1448 | WARN(1, "%s: object not 1M or size aligned\n", __FUNCTION__); | |
1449 | return; | |
1450 | } | |
1451 | ||
1452 | if (obj_priv->tiling_mode == I915_TILING_Y && (IS_I945G(dev) || | |
1453 | IS_I945GM(dev) || | |
1454 | IS_G33(dev))) | |
1455 | pitch_val = (obj_priv->stride / 128) - 1; | |
1456 | else | |
1457 | pitch_val = (obj_priv->stride / 512) - 1; | |
1458 | ||
1459 | val = obj_priv->gtt_offset; | |
1460 | if (obj_priv->tiling_mode == I915_TILING_Y) | |
1461 | val |= 1 << I830_FENCE_TILING_Y_SHIFT; | |
1462 | val |= I915_FENCE_SIZE_BITS(obj->size); | |
1463 | val |= pitch_val << I830_FENCE_PITCH_SHIFT; | |
1464 | val |= I830_FENCE_REG_VALID; | |
1465 | ||
1466 | I915_WRITE(FENCE_REG_830_0 + (regnum * 4), val); | |
1467 | } | |
1468 | ||
1469 | static void i830_write_fence_reg(struct drm_i915_fence_reg *reg) | |
1470 | { | |
1471 | struct drm_gem_object *obj = reg->obj; | |
1472 | struct drm_device *dev = obj->dev; | |
1473 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1474 | struct drm_i915_gem_object *obj_priv = obj->driver_private; | |
1475 | int regnum = obj_priv->fence_reg; | |
1476 | uint32_t val; | |
1477 | uint32_t pitch_val; | |
1478 | ||
1479 | if ((obj_priv->gtt_offset & ~I915_FENCE_START_MASK) || | |
1480 | (obj_priv->gtt_offset & (obj->size - 1))) { | |
1481 | WARN(1, "%s: object not 1M or size aligned\n", __FUNCTION__); | |
1482 | return; | |
1483 | } | |
1484 | ||
1485 | pitch_val = (obj_priv->stride / 128) - 1; | |
1486 | ||
1487 | val = obj_priv->gtt_offset; | |
1488 | if (obj_priv->tiling_mode == I915_TILING_Y) | |
1489 | val |= 1 << I830_FENCE_TILING_Y_SHIFT; | |
1490 | val |= I830_FENCE_SIZE_BITS(obj->size); | |
1491 | val |= pitch_val << I830_FENCE_PITCH_SHIFT; | |
1492 | val |= I830_FENCE_REG_VALID; | |
1493 | ||
1494 | I915_WRITE(FENCE_REG_830_0 + (regnum * 4), val); | |
1495 | ||
1496 | } | |
1497 | ||
1498 | /** | |
1499 | * i915_gem_object_get_fence_reg - set up a fence reg for an object | |
1500 | * @obj: object to map through a fence reg | |
1501 | * | |
1502 | * When mapping objects through the GTT, userspace wants to be able to write | |
1503 | * to them without having to worry about swizzling if the object is tiled. | |
1504 | * | |
1505 | * This function walks the fence regs looking for a free one for @obj, | |
1506 | * stealing one if it can't find any. | |
1507 | * | |
1508 | * It then sets up the reg based on the object's properties: address, pitch | |
1509 | * and tiling format. | |
1510 | */ | |
1511 | static void | |
1512 | i915_gem_object_get_fence_reg(struct drm_gem_object *obj) | |
1513 | { | |
1514 | struct drm_device *dev = obj->dev; | |
79e53945 | 1515 | struct drm_i915_private *dev_priv = dev->dev_private; |
de151cf6 JB |
1516 | struct drm_i915_gem_object *obj_priv = obj->driver_private; |
1517 | struct drm_i915_fence_reg *reg = NULL; | |
1518 | int i, ret; | |
1519 | ||
1520 | switch (obj_priv->tiling_mode) { | |
1521 | case I915_TILING_NONE: | |
1522 | WARN(1, "allocating a fence for non-tiled object?\n"); | |
1523 | break; | |
1524 | case I915_TILING_X: | |
1525 | WARN(obj_priv->stride & (512 - 1), | |
1526 | "object is X tiled but has non-512B pitch\n"); | |
1527 | break; | |
1528 | case I915_TILING_Y: | |
1529 | WARN(obj_priv->stride & (128 - 1), | |
1530 | "object is Y tiled but has non-128B pitch\n"); | |
1531 | break; | |
1532 | } | |
1533 | ||
1534 | /* First try to find a free reg */ | |
1535 | for (i = dev_priv->fence_reg_start; i < dev_priv->num_fence_regs; i++) { | |
1536 | reg = &dev_priv->fence_regs[i]; | |
1537 | if (!reg->obj) | |
1538 | break; | |
1539 | } | |
1540 | ||
1541 | /* None available, try to steal one or wait for a user to finish */ | |
1542 | if (i == dev_priv->num_fence_regs) { | |
1543 | struct drm_i915_gem_object *old_obj_priv = NULL; | |
1544 | loff_t offset; | |
1545 | ||
1546 | try_again: | |
1547 | /* Could try to use LRU here instead... */ | |
1548 | for (i = dev_priv->fence_reg_start; | |
1549 | i < dev_priv->num_fence_regs; i++) { | |
1550 | reg = &dev_priv->fence_regs[i]; | |
1551 | old_obj_priv = reg->obj->driver_private; | |
1552 | if (!old_obj_priv->pin_count) | |
1553 | break; | |
1554 | } | |
1555 | ||
1556 | /* | |
1557 | * Now things get ugly... we have to wait for one of the | |
1558 | * objects to finish before trying again. | |
1559 | */ | |
1560 | if (i == dev_priv->num_fence_regs) { | |
1561 | ret = i915_gem_object_wait_rendering(reg->obj); | |
1562 | if (ret) { | |
1563 | WARN(ret, "wait_rendering failed: %d\n", ret); | |
1564 | return; | |
1565 | } | |
1566 | goto try_again; | |
1567 | } | |
1568 | ||
1569 | /* | |
1570 | * Zap this virtual mapping so we can set up a fence again | |
1571 | * for this object next time we need it. | |
1572 | */ | |
1573 | offset = ((loff_t) reg->obj->map_list.hash.key) << PAGE_SHIFT; | |
79e53945 JB |
1574 | if (dev->dev_mapping) |
1575 | unmap_mapping_range(dev->dev_mapping, offset, | |
1576 | reg->obj->size, 1); | |
de151cf6 JB |
1577 | old_obj_priv->fence_reg = I915_FENCE_REG_NONE; |
1578 | } | |
1579 | ||
1580 | obj_priv->fence_reg = i; | |
1581 | reg->obj = obj; | |
1582 | ||
1583 | if (IS_I965G(dev)) | |
1584 | i965_write_fence_reg(reg); | |
1585 | else if (IS_I9XX(dev)) | |
1586 | i915_write_fence_reg(reg); | |
1587 | else | |
1588 | i830_write_fence_reg(reg); | |
1589 | } | |
1590 | ||
1591 | /** | |
1592 | * i915_gem_clear_fence_reg - clear out fence register info | |
1593 | * @obj: object to clear | |
1594 | * | |
1595 | * Zeroes out the fence register itself and clears out the associated | |
1596 | * data structures in dev_priv and obj_priv. | |
1597 | */ | |
1598 | static void | |
1599 | i915_gem_clear_fence_reg(struct drm_gem_object *obj) | |
1600 | { | |
1601 | struct drm_device *dev = obj->dev; | |
79e53945 | 1602 | drm_i915_private_t *dev_priv = dev->dev_private; |
de151cf6 JB |
1603 | struct drm_i915_gem_object *obj_priv = obj->driver_private; |
1604 | ||
1605 | if (IS_I965G(dev)) | |
1606 | I915_WRITE64(FENCE_REG_965_0 + (obj_priv->fence_reg * 8), 0); | |
1607 | else | |
1608 | I915_WRITE(FENCE_REG_830_0 + (obj_priv->fence_reg * 4), 0); | |
1609 | ||
1610 | dev_priv->fence_regs[obj_priv->fence_reg].obj = NULL; | |
1611 | obj_priv->fence_reg = I915_FENCE_REG_NONE; | |
1612 | } | |
1613 | ||
673a394b EA |
1614 | /** |
1615 | * Finds free space in the GTT aperture and binds the object there. | |
1616 | */ | |
1617 | static int | |
1618 | i915_gem_object_bind_to_gtt(struct drm_gem_object *obj, unsigned alignment) | |
1619 | { | |
1620 | struct drm_device *dev = obj->dev; | |
1621 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1622 | struct drm_i915_gem_object *obj_priv = obj->driver_private; | |
1623 | struct drm_mm_node *free_space; | |
1624 | int page_count, ret; | |
1625 | ||
1626 | if (alignment == 0) | |
1627 | alignment = PAGE_SIZE; | |
1628 | if (alignment & (PAGE_SIZE - 1)) { | |
1629 | DRM_ERROR("Invalid object alignment requested %u\n", alignment); | |
1630 | return -EINVAL; | |
1631 | } | |
1632 | ||
1633 | search_free: | |
1634 | free_space = drm_mm_search_free(&dev_priv->mm.gtt_space, | |
1635 | obj->size, alignment, 0); | |
1636 | if (free_space != NULL) { | |
1637 | obj_priv->gtt_space = drm_mm_get_block(free_space, obj->size, | |
1638 | alignment); | |
1639 | if (obj_priv->gtt_space != NULL) { | |
1640 | obj_priv->gtt_space->private = obj; | |
1641 | obj_priv->gtt_offset = obj_priv->gtt_space->start; | |
1642 | } | |
1643 | } | |
1644 | if (obj_priv->gtt_space == NULL) { | |
1645 | /* If the gtt is empty and we're still having trouble | |
1646 | * fitting our object in, we're out of memory. | |
1647 | */ | |
1648 | #if WATCH_LRU | |
1649 | DRM_INFO("%s: GTT full, evicting something\n", __func__); | |
1650 | #endif | |
1651 | if (list_empty(&dev_priv->mm.inactive_list) && | |
1652 | list_empty(&dev_priv->mm.flushing_list) && | |
1653 | list_empty(&dev_priv->mm.active_list)) { | |
1654 | DRM_ERROR("GTT full, but LRU list empty\n"); | |
1655 | return -ENOMEM; | |
1656 | } | |
1657 | ||
1658 | ret = i915_gem_evict_something(dev); | |
1659 | if (ret != 0) { | |
ac94a962 KP |
1660 | if (ret != -ERESTARTSYS) |
1661 | DRM_ERROR("Failed to evict a buffer %d\n", ret); | |
673a394b EA |
1662 | return ret; |
1663 | } | |
1664 | goto search_free; | |
1665 | } | |
1666 | ||
1667 | #if WATCH_BUF | |
1668 | DRM_INFO("Binding object of size %d at 0x%08x\n", | |
1669 | obj->size, obj_priv->gtt_offset); | |
1670 | #endif | |
1671 | ret = i915_gem_object_get_page_list(obj); | |
1672 | if (ret) { | |
1673 | drm_mm_put_block(obj_priv->gtt_space); | |
1674 | obj_priv->gtt_space = NULL; | |
1675 | return ret; | |
1676 | } | |
1677 | ||
1678 | page_count = obj->size / PAGE_SIZE; | |
1679 | /* Create an AGP memory structure pointing at our pages, and bind it | |
1680 | * into the GTT. | |
1681 | */ | |
1682 | obj_priv->agp_mem = drm_agp_bind_pages(dev, | |
1683 | obj_priv->page_list, | |
1684 | page_count, | |
ba1eb1d8 KP |
1685 | obj_priv->gtt_offset, |
1686 | obj_priv->agp_type); | |
673a394b EA |
1687 | if (obj_priv->agp_mem == NULL) { |
1688 | i915_gem_object_free_page_list(obj); | |
1689 | drm_mm_put_block(obj_priv->gtt_space); | |
1690 | obj_priv->gtt_space = NULL; | |
1691 | return -ENOMEM; | |
1692 | } | |
1693 | atomic_inc(&dev->gtt_count); | |
1694 | atomic_add(obj->size, &dev->gtt_memory); | |
1695 | ||
1696 | /* Assert that the object is not currently in any GPU domain. As it | |
1697 | * wasn't in the GTT, there shouldn't be any way it could have been in | |
1698 | * a GPU cache | |
1699 | */ | |
1700 | BUG_ON(obj->read_domains & ~(I915_GEM_DOMAIN_CPU|I915_GEM_DOMAIN_GTT)); | |
1701 | BUG_ON(obj->write_domain & ~(I915_GEM_DOMAIN_CPU|I915_GEM_DOMAIN_GTT)); | |
1702 | ||
1703 | return 0; | |
1704 | } | |
1705 | ||
1706 | void | |
1707 | i915_gem_clflush_object(struct drm_gem_object *obj) | |
1708 | { | |
1709 | struct drm_i915_gem_object *obj_priv = obj->driver_private; | |
1710 | ||
1711 | /* If we don't have a page list set up, then we're not pinned | |
1712 | * to GPU, and we can ignore the cache flush because it'll happen | |
1713 | * again at bind time. | |
1714 | */ | |
1715 | if (obj_priv->page_list == NULL) | |
1716 | return; | |
1717 | ||
1718 | drm_clflush_pages(obj_priv->page_list, obj->size / PAGE_SIZE); | |
1719 | } | |
1720 | ||
e47c68e9 EA |
1721 | /** Flushes any GPU write domain for the object if it's dirty. */ |
1722 | static void | |
1723 | i915_gem_object_flush_gpu_write_domain(struct drm_gem_object *obj) | |
1724 | { | |
1725 | struct drm_device *dev = obj->dev; | |
1726 | uint32_t seqno; | |
1727 | ||
1728 | if ((obj->write_domain & I915_GEM_GPU_DOMAINS) == 0) | |
1729 | return; | |
1730 | ||
1731 | /* Queue the GPU write cache flushing we need. */ | |
1732 | i915_gem_flush(dev, 0, obj->write_domain); | |
1733 | seqno = i915_add_request(dev, obj->write_domain); | |
1734 | obj->write_domain = 0; | |
1735 | i915_gem_object_move_to_active(obj, seqno); | |
1736 | } | |
1737 | ||
1738 | /** Flushes the GTT write domain for the object if it's dirty. */ | |
1739 | static void | |
1740 | i915_gem_object_flush_gtt_write_domain(struct drm_gem_object *obj) | |
1741 | { | |
1742 | if (obj->write_domain != I915_GEM_DOMAIN_GTT) | |
1743 | return; | |
1744 | ||
1745 | /* No actual flushing is required for the GTT write domain. Writes | |
1746 | * to it immediately go to main memory as far as we know, so there's | |
1747 | * no chipset flush. It also doesn't land in render cache. | |
1748 | */ | |
1749 | obj->write_domain = 0; | |
1750 | } | |
1751 | ||
1752 | /** Flushes the CPU write domain for the object if it's dirty. */ | |
1753 | static void | |
1754 | i915_gem_object_flush_cpu_write_domain(struct drm_gem_object *obj) | |
1755 | { | |
1756 | struct drm_device *dev = obj->dev; | |
1757 | ||
1758 | if (obj->write_domain != I915_GEM_DOMAIN_CPU) | |
1759 | return; | |
1760 | ||
1761 | i915_gem_clflush_object(obj); | |
1762 | drm_agp_chipset_flush(dev); | |
1763 | obj->write_domain = 0; | |
1764 | } | |
1765 | ||
2ef7eeaa EA |
1766 | /** |
1767 | * Moves a single object to the GTT read, and possibly write domain. | |
1768 | * | |
1769 | * This function returns when the move is complete, including waiting on | |
1770 | * flushes to occur. | |
1771 | */ | |
79e53945 | 1772 | int |
2ef7eeaa EA |
1773 | i915_gem_object_set_to_gtt_domain(struct drm_gem_object *obj, int write) |
1774 | { | |
2ef7eeaa | 1775 | struct drm_i915_gem_object *obj_priv = obj->driver_private; |
e47c68e9 | 1776 | int ret; |
2ef7eeaa | 1777 | |
02354392 EA |
1778 | /* Not valid to be called on unbound objects. */ |
1779 | if (obj_priv->gtt_space == NULL) | |
1780 | return -EINVAL; | |
1781 | ||
e47c68e9 EA |
1782 | i915_gem_object_flush_gpu_write_domain(obj); |
1783 | /* Wait on any GPU rendering and flushing to occur. */ | |
1784 | ret = i915_gem_object_wait_rendering(obj); | |
1785 | if (ret != 0) | |
1786 | return ret; | |
1787 | ||
1788 | /* If we're writing through the GTT domain, then CPU and GPU caches | |
1789 | * will need to be invalidated at next use. | |
2ef7eeaa | 1790 | */ |
e47c68e9 EA |
1791 | if (write) |
1792 | obj->read_domains &= I915_GEM_DOMAIN_GTT; | |
2ef7eeaa | 1793 | |
e47c68e9 | 1794 | i915_gem_object_flush_cpu_write_domain(obj); |
2ef7eeaa | 1795 | |
e47c68e9 EA |
1796 | /* It should now be out of any other write domains, and we can update |
1797 | * the domain values for our changes. | |
1798 | */ | |
1799 | BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_GTT) != 0); | |
1800 | obj->read_domains |= I915_GEM_DOMAIN_GTT; | |
1801 | if (write) { | |
1802 | obj->write_domain = I915_GEM_DOMAIN_GTT; | |
1803 | obj_priv->dirty = 1; | |
2ef7eeaa EA |
1804 | } |
1805 | ||
e47c68e9 EA |
1806 | return 0; |
1807 | } | |
1808 | ||
1809 | /** | |
1810 | * Moves a single object to the CPU read, and possibly write domain. | |
1811 | * | |
1812 | * This function returns when the move is complete, including waiting on | |
1813 | * flushes to occur. | |
1814 | */ | |
1815 | static int | |
1816 | i915_gem_object_set_to_cpu_domain(struct drm_gem_object *obj, int write) | |
1817 | { | |
1818 | struct drm_device *dev = obj->dev; | |
1819 | int ret; | |
1820 | ||
1821 | i915_gem_object_flush_gpu_write_domain(obj); | |
2ef7eeaa | 1822 | /* Wait on any GPU rendering and flushing to occur. */ |
e47c68e9 EA |
1823 | ret = i915_gem_object_wait_rendering(obj); |
1824 | if (ret != 0) | |
1825 | return ret; | |
2ef7eeaa | 1826 | |
e47c68e9 | 1827 | i915_gem_object_flush_gtt_write_domain(obj); |
2ef7eeaa | 1828 | |
e47c68e9 EA |
1829 | /* If we have a partially-valid cache of the object in the CPU, |
1830 | * finish invalidating it and free the per-page flags. | |
2ef7eeaa | 1831 | */ |
e47c68e9 | 1832 | i915_gem_object_set_to_full_cpu_read_domain(obj); |
2ef7eeaa | 1833 | |
e47c68e9 EA |
1834 | /* Flush the CPU cache if it's still invalid. */ |
1835 | if ((obj->read_domains & I915_GEM_DOMAIN_CPU) == 0) { | |
2ef7eeaa EA |
1836 | i915_gem_clflush_object(obj); |
1837 | drm_agp_chipset_flush(dev); | |
1838 | ||
e47c68e9 | 1839 | obj->read_domains |= I915_GEM_DOMAIN_CPU; |
2ef7eeaa EA |
1840 | } |
1841 | ||
1842 | /* It should now be out of any other write domains, and we can update | |
1843 | * the domain values for our changes. | |
1844 | */ | |
e47c68e9 EA |
1845 | BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_CPU) != 0); |
1846 | ||
1847 | /* If we're writing through the CPU, then the GPU read domains will | |
1848 | * need to be invalidated at next use. | |
1849 | */ | |
1850 | if (write) { | |
1851 | obj->read_domains &= I915_GEM_DOMAIN_CPU; | |
1852 | obj->write_domain = I915_GEM_DOMAIN_CPU; | |
1853 | } | |
2ef7eeaa EA |
1854 | |
1855 | return 0; | |
1856 | } | |
1857 | ||
673a394b EA |
1858 | /* |
1859 | * Set the next domain for the specified object. This | |
1860 | * may not actually perform the necessary flushing/invaliding though, | |
1861 | * as that may want to be batched with other set_domain operations | |
1862 | * | |
1863 | * This is (we hope) the only really tricky part of gem. The goal | |
1864 | * is fairly simple -- track which caches hold bits of the object | |
1865 | * and make sure they remain coherent. A few concrete examples may | |
1866 | * help to explain how it works. For shorthand, we use the notation | |
1867 | * (read_domains, write_domain), e.g. (CPU, CPU) to indicate the | |
1868 | * a pair of read and write domain masks. | |
1869 | * | |
1870 | * Case 1: the batch buffer | |
1871 | * | |
1872 | * 1. Allocated | |
1873 | * 2. Written by CPU | |
1874 | * 3. Mapped to GTT | |
1875 | * 4. Read by GPU | |
1876 | * 5. Unmapped from GTT | |
1877 | * 6. Freed | |
1878 | * | |
1879 | * Let's take these a step at a time | |
1880 | * | |
1881 | * 1. Allocated | |
1882 | * Pages allocated from the kernel may still have | |
1883 | * cache contents, so we set them to (CPU, CPU) always. | |
1884 | * 2. Written by CPU (using pwrite) | |
1885 | * The pwrite function calls set_domain (CPU, CPU) and | |
1886 | * this function does nothing (as nothing changes) | |
1887 | * 3. Mapped by GTT | |
1888 | * This function asserts that the object is not | |
1889 | * currently in any GPU-based read or write domains | |
1890 | * 4. Read by GPU | |
1891 | * i915_gem_execbuffer calls set_domain (COMMAND, 0). | |
1892 | * As write_domain is zero, this function adds in the | |
1893 | * current read domains (CPU+COMMAND, 0). | |
1894 | * flush_domains is set to CPU. | |
1895 | * invalidate_domains is set to COMMAND | |
1896 | * clflush is run to get data out of the CPU caches | |
1897 | * then i915_dev_set_domain calls i915_gem_flush to | |
1898 | * emit an MI_FLUSH and drm_agp_chipset_flush | |
1899 | * 5. Unmapped from GTT | |
1900 | * i915_gem_object_unbind calls set_domain (CPU, CPU) | |
1901 | * flush_domains and invalidate_domains end up both zero | |
1902 | * so no flushing/invalidating happens | |
1903 | * 6. Freed | |
1904 | * yay, done | |
1905 | * | |
1906 | * Case 2: The shared render buffer | |
1907 | * | |
1908 | * 1. Allocated | |
1909 | * 2. Mapped to GTT | |
1910 | * 3. Read/written by GPU | |
1911 | * 4. set_domain to (CPU,CPU) | |
1912 | * 5. Read/written by CPU | |
1913 | * 6. Read/written by GPU | |
1914 | * | |
1915 | * 1. Allocated | |
1916 | * Same as last example, (CPU, CPU) | |
1917 | * 2. Mapped to GTT | |
1918 | * Nothing changes (assertions find that it is not in the GPU) | |
1919 | * 3. Read/written by GPU | |
1920 | * execbuffer calls set_domain (RENDER, RENDER) | |
1921 | * flush_domains gets CPU | |
1922 | * invalidate_domains gets GPU | |
1923 | * clflush (obj) | |
1924 | * MI_FLUSH and drm_agp_chipset_flush | |
1925 | * 4. set_domain (CPU, CPU) | |
1926 | * flush_domains gets GPU | |
1927 | * invalidate_domains gets CPU | |
1928 | * wait_rendering (obj) to make sure all drawing is complete. | |
1929 | * This will include an MI_FLUSH to get the data from GPU | |
1930 | * to memory | |
1931 | * clflush (obj) to invalidate the CPU cache | |
1932 | * Another MI_FLUSH in i915_gem_flush (eliminate this somehow?) | |
1933 | * 5. Read/written by CPU | |
1934 | * cache lines are loaded and dirtied | |
1935 | * 6. Read written by GPU | |
1936 | * Same as last GPU access | |
1937 | * | |
1938 | * Case 3: The constant buffer | |
1939 | * | |
1940 | * 1. Allocated | |
1941 | * 2. Written by CPU | |
1942 | * 3. Read by GPU | |
1943 | * 4. Updated (written) by CPU again | |
1944 | * 5. Read by GPU | |
1945 | * | |
1946 | * 1. Allocated | |
1947 | * (CPU, CPU) | |
1948 | * 2. Written by CPU | |
1949 | * (CPU, CPU) | |
1950 | * 3. Read by GPU | |
1951 | * (CPU+RENDER, 0) | |
1952 | * flush_domains = CPU | |
1953 | * invalidate_domains = RENDER | |
1954 | * clflush (obj) | |
1955 | * MI_FLUSH | |
1956 | * drm_agp_chipset_flush | |
1957 | * 4. Updated (written) by CPU again | |
1958 | * (CPU, CPU) | |
1959 | * flush_domains = 0 (no previous write domain) | |
1960 | * invalidate_domains = 0 (no new read domains) | |
1961 | * 5. Read by GPU | |
1962 | * (CPU+RENDER, 0) | |
1963 | * flush_domains = CPU | |
1964 | * invalidate_domains = RENDER | |
1965 | * clflush (obj) | |
1966 | * MI_FLUSH | |
1967 | * drm_agp_chipset_flush | |
1968 | */ | |
c0d90829 KP |
1969 | static void |
1970 | i915_gem_object_set_to_gpu_domain(struct drm_gem_object *obj, | |
1971 | uint32_t read_domains, | |
1972 | uint32_t write_domain) | |
673a394b EA |
1973 | { |
1974 | struct drm_device *dev = obj->dev; | |
1975 | struct drm_i915_gem_object *obj_priv = obj->driver_private; | |
1976 | uint32_t invalidate_domains = 0; | |
1977 | uint32_t flush_domains = 0; | |
e47c68e9 EA |
1978 | |
1979 | BUG_ON(read_domains & I915_GEM_DOMAIN_CPU); | |
1980 | BUG_ON(write_domain == I915_GEM_DOMAIN_CPU); | |
673a394b EA |
1981 | |
1982 | #if WATCH_BUF | |
1983 | DRM_INFO("%s: object %p read %08x -> %08x write %08x -> %08x\n", | |
1984 | __func__, obj, | |
1985 | obj->read_domains, read_domains, | |
1986 | obj->write_domain, write_domain); | |
1987 | #endif | |
1988 | /* | |
1989 | * If the object isn't moving to a new write domain, | |
1990 | * let the object stay in multiple read domains | |
1991 | */ | |
1992 | if (write_domain == 0) | |
1993 | read_domains |= obj->read_domains; | |
1994 | else | |
1995 | obj_priv->dirty = 1; | |
1996 | ||
1997 | /* | |
1998 | * Flush the current write domain if | |
1999 | * the new read domains don't match. Invalidate | |
2000 | * any read domains which differ from the old | |
2001 | * write domain | |
2002 | */ | |
2003 | if (obj->write_domain && obj->write_domain != read_domains) { | |
2004 | flush_domains |= obj->write_domain; | |
2005 | invalidate_domains |= read_domains & ~obj->write_domain; | |
2006 | } | |
2007 | /* | |
2008 | * Invalidate any read caches which may have | |
2009 | * stale data. That is, any new read domains. | |
2010 | */ | |
2011 | invalidate_domains |= read_domains & ~obj->read_domains; | |
2012 | if ((flush_domains | invalidate_domains) & I915_GEM_DOMAIN_CPU) { | |
2013 | #if WATCH_BUF | |
2014 | DRM_INFO("%s: CPU domain flush %08x invalidate %08x\n", | |
2015 | __func__, flush_domains, invalidate_domains); | |
2016 | #endif | |
673a394b EA |
2017 | i915_gem_clflush_object(obj); |
2018 | } | |
2019 | ||
2020 | if ((write_domain | flush_domains) != 0) | |
2021 | obj->write_domain = write_domain; | |
673a394b EA |
2022 | obj->read_domains = read_domains; |
2023 | ||
2024 | dev->invalidate_domains |= invalidate_domains; | |
2025 | dev->flush_domains |= flush_domains; | |
2026 | #if WATCH_BUF | |
2027 | DRM_INFO("%s: read %08x write %08x invalidate %08x flush %08x\n", | |
2028 | __func__, | |
2029 | obj->read_domains, obj->write_domain, | |
2030 | dev->invalidate_domains, dev->flush_domains); | |
2031 | #endif | |
673a394b EA |
2032 | } |
2033 | ||
2034 | /** | |
e47c68e9 | 2035 | * Moves the object from a partially CPU read to a full one. |
673a394b | 2036 | * |
e47c68e9 EA |
2037 | * Note that this only resolves i915_gem_object_set_cpu_read_domain_range(), |
2038 | * and doesn't handle transitioning from !(read_domains & I915_GEM_DOMAIN_CPU). | |
673a394b | 2039 | */ |
e47c68e9 EA |
2040 | static void |
2041 | i915_gem_object_set_to_full_cpu_read_domain(struct drm_gem_object *obj) | |
673a394b | 2042 | { |
e47c68e9 | 2043 | struct drm_device *dev = obj->dev; |
673a394b | 2044 | struct drm_i915_gem_object *obj_priv = obj->driver_private; |
673a394b | 2045 | |
e47c68e9 EA |
2046 | if (!obj_priv->page_cpu_valid) |
2047 | return; | |
2048 | ||
2049 | /* If we're partially in the CPU read domain, finish moving it in. | |
2050 | */ | |
2051 | if (obj->read_domains & I915_GEM_DOMAIN_CPU) { | |
2052 | int i; | |
2053 | ||
2054 | for (i = 0; i <= (obj->size - 1) / PAGE_SIZE; i++) { | |
2055 | if (obj_priv->page_cpu_valid[i]) | |
2056 | continue; | |
2057 | drm_clflush_pages(obj_priv->page_list + i, 1); | |
2058 | } | |
2059 | drm_agp_chipset_flush(dev); | |
2060 | } | |
2061 | ||
2062 | /* Free the page_cpu_valid mappings which are now stale, whether | |
2063 | * or not we've got I915_GEM_DOMAIN_CPU. | |
2064 | */ | |
2065 | drm_free(obj_priv->page_cpu_valid, obj->size / PAGE_SIZE, | |
2066 | DRM_MEM_DRIVER); | |
2067 | obj_priv->page_cpu_valid = NULL; | |
2068 | } | |
2069 | ||
2070 | /** | |
2071 | * Set the CPU read domain on a range of the object. | |
2072 | * | |
2073 | * The object ends up with I915_GEM_DOMAIN_CPU in its read flags although it's | |
2074 | * not entirely valid. The page_cpu_valid member of the object flags which | |
2075 | * pages have been flushed, and will be respected by | |
2076 | * i915_gem_object_set_to_cpu_domain() if it's called on to get a valid mapping | |
2077 | * of the whole object. | |
2078 | * | |
2079 | * This function returns when the move is complete, including waiting on | |
2080 | * flushes to occur. | |
2081 | */ | |
2082 | static int | |
2083 | i915_gem_object_set_cpu_read_domain_range(struct drm_gem_object *obj, | |
2084 | uint64_t offset, uint64_t size) | |
2085 | { | |
2086 | struct drm_i915_gem_object *obj_priv = obj->driver_private; | |
2087 | int i, ret; | |
673a394b | 2088 | |
e47c68e9 EA |
2089 | if (offset == 0 && size == obj->size) |
2090 | return i915_gem_object_set_to_cpu_domain(obj, 0); | |
673a394b | 2091 | |
e47c68e9 EA |
2092 | i915_gem_object_flush_gpu_write_domain(obj); |
2093 | /* Wait on any GPU rendering and flushing to occur. */ | |
6a47baa6 | 2094 | ret = i915_gem_object_wait_rendering(obj); |
e47c68e9 | 2095 | if (ret != 0) |
6a47baa6 | 2096 | return ret; |
e47c68e9 EA |
2097 | i915_gem_object_flush_gtt_write_domain(obj); |
2098 | ||
2099 | /* If we're already fully in the CPU read domain, we're done. */ | |
2100 | if (obj_priv->page_cpu_valid == NULL && | |
2101 | (obj->read_domains & I915_GEM_DOMAIN_CPU) != 0) | |
2102 | return 0; | |
673a394b | 2103 | |
e47c68e9 EA |
2104 | /* Otherwise, create/clear the per-page CPU read domain flag if we're |
2105 | * newly adding I915_GEM_DOMAIN_CPU | |
2106 | */ | |
673a394b EA |
2107 | if (obj_priv->page_cpu_valid == NULL) { |
2108 | obj_priv->page_cpu_valid = drm_calloc(1, obj->size / PAGE_SIZE, | |
2109 | DRM_MEM_DRIVER); | |
e47c68e9 EA |
2110 | if (obj_priv->page_cpu_valid == NULL) |
2111 | return -ENOMEM; | |
2112 | } else if ((obj->read_domains & I915_GEM_DOMAIN_CPU) == 0) | |
2113 | memset(obj_priv->page_cpu_valid, 0, obj->size / PAGE_SIZE); | |
673a394b EA |
2114 | |
2115 | /* Flush the cache on any pages that are still invalid from the CPU's | |
2116 | * perspective. | |
2117 | */ | |
e47c68e9 EA |
2118 | for (i = offset / PAGE_SIZE; i <= (offset + size - 1) / PAGE_SIZE; |
2119 | i++) { | |
673a394b EA |
2120 | if (obj_priv->page_cpu_valid[i]) |
2121 | continue; | |
2122 | ||
2123 | drm_clflush_pages(obj_priv->page_list + i, 1); | |
2124 | ||
2125 | obj_priv->page_cpu_valid[i] = 1; | |
2126 | } | |
2127 | ||
e47c68e9 EA |
2128 | /* It should now be out of any other write domains, and we can update |
2129 | * the domain values for our changes. | |
2130 | */ | |
2131 | BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_CPU) != 0); | |
2132 | ||
2133 | obj->read_domains |= I915_GEM_DOMAIN_CPU; | |
2134 | ||
673a394b EA |
2135 | return 0; |
2136 | } | |
2137 | ||
673a394b EA |
2138 | /** |
2139 | * Pin an object to the GTT and evaluate the relocations landing in it. | |
2140 | */ | |
2141 | static int | |
2142 | i915_gem_object_pin_and_relocate(struct drm_gem_object *obj, | |
2143 | struct drm_file *file_priv, | |
2144 | struct drm_i915_gem_exec_object *entry) | |
2145 | { | |
2146 | struct drm_device *dev = obj->dev; | |
0839ccb8 | 2147 | drm_i915_private_t *dev_priv = dev->dev_private; |
673a394b EA |
2148 | struct drm_i915_gem_relocation_entry reloc; |
2149 | struct drm_i915_gem_relocation_entry __user *relocs; | |
2150 | struct drm_i915_gem_object *obj_priv = obj->driver_private; | |
2151 | int i, ret; | |
0839ccb8 | 2152 | void __iomem *reloc_page; |
673a394b EA |
2153 | |
2154 | /* Choose the GTT offset for our buffer and put it there. */ | |
2155 | ret = i915_gem_object_pin(obj, (uint32_t) entry->alignment); | |
2156 | if (ret) | |
2157 | return ret; | |
2158 | ||
2159 | entry->offset = obj_priv->gtt_offset; | |
2160 | ||
2161 | relocs = (struct drm_i915_gem_relocation_entry __user *) | |
2162 | (uintptr_t) entry->relocs_ptr; | |
2163 | /* Apply the relocations, using the GTT aperture to avoid cache | |
2164 | * flushing requirements. | |
2165 | */ | |
2166 | for (i = 0; i < entry->relocation_count; i++) { | |
2167 | struct drm_gem_object *target_obj; | |
2168 | struct drm_i915_gem_object *target_obj_priv; | |
3043c60c EA |
2169 | uint32_t reloc_val, reloc_offset; |
2170 | uint32_t __iomem *reloc_entry; | |
673a394b EA |
2171 | |
2172 | ret = copy_from_user(&reloc, relocs + i, sizeof(reloc)); | |
2173 | if (ret != 0) { | |
2174 | i915_gem_object_unpin(obj); | |
2175 | return ret; | |
2176 | } | |
2177 | ||
2178 | target_obj = drm_gem_object_lookup(obj->dev, file_priv, | |
2179 | reloc.target_handle); | |
2180 | if (target_obj == NULL) { | |
2181 | i915_gem_object_unpin(obj); | |
2182 | return -EBADF; | |
2183 | } | |
2184 | target_obj_priv = target_obj->driver_private; | |
2185 | ||
2186 | /* The target buffer should have appeared before us in the | |
2187 | * exec_object list, so it should have a GTT space bound by now. | |
2188 | */ | |
2189 | if (target_obj_priv->gtt_space == NULL) { | |
2190 | DRM_ERROR("No GTT space found for object %d\n", | |
2191 | reloc.target_handle); | |
2192 | drm_gem_object_unreference(target_obj); | |
2193 | i915_gem_object_unpin(obj); | |
2194 | return -EINVAL; | |
2195 | } | |
2196 | ||
2197 | if (reloc.offset > obj->size - 4) { | |
2198 | DRM_ERROR("Relocation beyond object bounds: " | |
2199 | "obj %p target %d offset %d size %d.\n", | |
2200 | obj, reloc.target_handle, | |
2201 | (int) reloc.offset, (int) obj->size); | |
2202 | drm_gem_object_unreference(target_obj); | |
2203 | i915_gem_object_unpin(obj); | |
2204 | return -EINVAL; | |
2205 | } | |
2206 | if (reloc.offset & 3) { | |
2207 | DRM_ERROR("Relocation not 4-byte aligned: " | |
2208 | "obj %p target %d offset %d.\n", | |
2209 | obj, reloc.target_handle, | |
2210 | (int) reloc.offset); | |
2211 | drm_gem_object_unreference(target_obj); | |
2212 | i915_gem_object_unpin(obj); | |
2213 | return -EINVAL; | |
2214 | } | |
2215 | ||
e47c68e9 EA |
2216 | if (reloc.write_domain & I915_GEM_DOMAIN_CPU || |
2217 | reloc.read_domains & I915_GEM_DOMAIN_CPU) { | |
2218 | DRM_ERROR("reloc with read/write CPU domains: " | |
2219 | "obj %p target %d offset %d " | |
2220 | "read %08x write %08x", | |
2221 | obj, reloc.target_handle, | |
2222 | (int) reloc.offset, | |
2223 | reloc.read_domains, | |
2224 | reloc.write_domain); | |
2225 | return -EINVAL; | |
2226 | } | |
2227 | ||
673a394b EA |
2228 | if (reloc.write_domain && target_obj->pending_write_domain && |
2229 | reloc.write_domain != target_obj->pending_write_domain) { | |
2230 | DRM_ERROR("Write domain conflict: " | |
2231 | "obj %p target %d offset %d " | |
2232 | "new %08x old %08x\n", | |
2233 | obj, reloc.target_handle, | |
2234 | (int) reloc.offset, | |
2235 | reloc.write_domain, | |
2236 | target_obj->pending_write_domain); | |
2237 | drm_gem_object_unreference(target_obj); | |
2238 | i915_gem_object_unpin(obj); | |
2239 | return -EINVAL; | |
2240 | } | |
2241 | ||
2242 | #if WATCH_RELOC | |
2243 | DRM_INFO("%s: obj %p offset %08x target %d " | |
2244 | "read %08x write %08x gtt %08x " | |
2245 | "presumed %08x delta %08x\n", | |
2246 | __func__, | |
2247 | obj, | |
2248 | (int) reloc.offset, | |
2249 | (int) reloc.target_handle, | |
2250 | (int) reloc.read_domains, | |
2251 | (int) reloc.write_domain, | |
2252 | (int) target_obj_priv->gtt_offset, | |
2253 | (int) reloc.presumed_offset, | |
2254 | reloc.delta); | |
2255 | #endif | |
2256 | ||
2257 | target_obj->pending_read_domains |= reloc.read_domains; | |
2258 | target_obj->pending_write_domain |= reloc.write_domain; | |
2259 | ||
2260 | /* If the relocation already has the right value in it, no | |
2261 | * more work needs to be done. | |
2262 | */ | |
2263 | if (target_obj_priv->gtt_offset == reloc.presumed_offset) { | |
2264 | drm_gem_object_unreference(target_obj); | |
2265 | continue; | |
2266 | } | |
2267 | ||
2ef7eeaa EA |
2268 | ret = i915_gem_object_set_to_gtt_domain(obj, 1); |
2269 | if (ret != 0) { | |
2270 | drm_gem_object_unreference(target_obj); | |
2271 | i915_gem_object_unpin(obj); | |
2272 | return -EINVAL; | |
673a394b EA |
2273 | } |
2274 | ||
2275 | /* Map the page containing the relocation we're going to | |
2276 | * perform. | |
2277 | */ | |
2278 | reloc_offset = obj_priv->gtt_offset + reloc.offset; | |
0839ccb8 KP |
2279 | reloc_page = io_mapping_map_atomic_wc(dev_priv->mm.gtt_mapping, |
2280 | (reloc_offset & | |
2281 | ~(PAGE_SIZE - 1))); | |
3043c60c | 2282 | reloc_entry = (uint32_t __iomem *)(reloc_page + |
0839ccb8 | 2283 | (reloc_offset & (PAGE_SIZE - 1))); |
673a394b EA |
2284 | reloc_val = target_obj_priv->gtt_offset + reloc.delta; |
2285 | ||
2286 | #if WATCH_BUF | |
2287 | DRM_INFO("Applied relocation: %p@0x%08x %08x -> %08x\n", | |
2288 | obj, (unsigned int) reloc.offset, | |
2289 | readl(reloc_entry), reloc_val); | |
2290 | #endif | |
2291 | writel(reloc_val, reloc_entry); | |
0839ccb8 | 2292 | io_mapping_unmap_atomic(reloc_page); |
673a394b EA |
2293 | |
2294 | /* Write the updated presumed offset for this entry back out | |
2295 | * to the user. | |
2296 | */ | |
2297 | reloc.presumed_offset = target_obj_priv->gtt_offset; | |
2298 | ret = copy_to_user(relocs + i, &reloc, sizeof(reloc)); | |
2299 | if (ret != 0) { | |
2300 | drm_gem_object_unreference(target_obj); | |
2301 | i915_gem_object_unpin(obj); | |
2302 | return ret; | |
2303 | } | |
2304 | ||
2305 | drm_gem_object_unreference(target_obj); | |
2306 | } | |
2307 | ||
673a394b EA |
2308 | #if WATCH_BUF |
2309 | if (0) | |
2310 | i915_gem_dump_object(obj, 128, __func__, ~0); | |
2311 | #endif | |
2312 | return 0; | |
2313 | } | |
2314 | ||
2315 | /** Dispatch a batchbuffer to the ring | |
2316 | */ | |
2317 | static int | |
2318 | i915_dispatch_gem_execbuffer(struct drm_device *dev, | |
2319 | struct drm_i915_gem_execbuffer *exec, | |
2320 | uint64_t exec_offset) | |
2321 | { | |
2322 | drm_i915_private_t *dev_priv = dev->dev_private; | |
2323 | struct drm_clip_rect __user *boxes = (struct drm_clip_rect __user *) | |
2324 | (uintptr_t) exec->cliprects_ptr; | |
2325 | int nbox = exec->num_cliprects; | |
2326 | int i = 0, count; | |
2327 | uint32_t exec_start, exec_len; | |
2328 | RING_LOCALS; | |
2329 | ||
2330 | exec_start = (uint32_t) exec_offset + exec->batch_start_offset; | |
2331 | exec_len = (uint32_t) exec->batch_len; | |
2332 | ||
2333 | if ((exec_start | exec_len) & 0x7) { | |
2334 | DRM_ERROR("alignment\n"); | |
2335 | return -EINVAL; | |
2336 | } | |
2337 | ||
2338 | if (!exec_start) | |
2339 | return -EINVAL; | |
2340 | ||
2341 | count = nbox ? nbox : 1; | |
2342 | ||
2343 | for (i = 0; i < count; i++) { | |
2344 | if (i < nbox) { | |
2345 | int ret = i915_emit_box(dev, boxes, i, | |
2346 | exec->DR1, exec->DR4); | |
2347 | if (ret) | |
2348 | return ret; | |
2349 | } | |
2350 | ||
2351 | if (IS_I830(dev) || IS_845G(dev)) { | |
2352 | BEGIN_LP_RING(4); | |
2353 | OUT_RING(MI_BATCH_BUFFER); | |
2354 | OUT_RING(exec_start | MI_BATCH_NON_SECURE); | |
2355 | OUT_RING(exec_start + exec_len - 4); | |
2356 | OUT_RING(0); | |
2357 | ADVANCE_LP_RING(); | |
2358 | } else { | |
2359 | BEGIN_LP_RING(2); | |
2360 | if (IS_I965G(dev)) { | |
2361 | OUT_RING(MI_BATCH_BUFFER_START | | |
2362 | (2 << 6) | | |
2363 | MI_BATCH_NON_SECURE_I965); | |
2364 | OUT_RING(exec_start); | |
2365 | } else { | |
2366 | OUT_RING(MI_BATCH_BUFFER_START | | |
2367 | (2 << 6)); | |
2368 | OUT_RING(exec_start | MI_BATCH_NON_SECURE); | |
2369 | } | |
2370 | ADVANCE_LP_RING(); | |
2371 | } | |
2372 | } | |
2373 | ||
2374 | /* XXX breadcrumb */ | |
2375 | return 0; | |
2376 | } | |
2377 | ||
2378 | /* Throttle our rendering by waiting until the ring has completed our requests | |
2379 | * emitted over 20 msec ago. | |
2380 | * | |
2381 | * This should get us reasonable parallelism between CPU and GPU but also | |
2382 | * relatively low latency when blocking on a particular request to finish. | |
2383 | */ | |
2384 | static int | |
2385 | i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file_priv) | |
2386 | { | |
2387 | struct drm_i915_file_private *i915_file_priv = file_priv->driver_priv; | |
2388 | int ret = 0; | |
2389 | uint32_t seqno; | |
2390 | ||
2391 | mutex_lock(&dev->struct_mutex); | |
2392 | seqno = i915_file_priv->mm.last_gem_throttle_seqno; | |
2393 | i915_file_priv->mm.last_gem_throttle_seqno = | |
2394 | i915_file_priv->mm.last_gem_seqno; | |
2395 | if (seqno) | |
2396 | ret = i915_wait_request(dev, seqno); | |
2397 | mutex_unlock(&dev->struct_mutex); | |
2398 | return ret; | |
2399 | } | |
2400 | ||
2401 | int | |
2402 | i915_gem_execbuffer(struct drm_device *dev, void *data, | |
2403 | struct drm_file *file_priv) | |
2404 | { | |
2405 | drm_i915_private_t *dev_priv = dev->dev_private; | |
2406 | struct drm_i915_file_private *i915_file_priv = file_priv->driver_priv; | |
2407 | struct drm_i915_gem_execbuffer *args = data; | |
2408 | struct drm_i915_gem_exec_object *exec_list = NULL; | |
2409 | struct drm_gem_object **object_list = NULL; | |
2410 | struct drm_gem_object *batch_obj; | |
2411 | int ret, i, pinned = 0; | |
2412 | uint64_t exec_offset; | |
2413 | uint32_t seqno, flush_domains; | |
ac94a962 | 2414 | int pin_tries; |
673a394b EA |
2415 | |
2416 | #if WATCH_EXEC | |
2417 | DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n", | |
2418 | (int) args->buffers_ptr, args->buffer_count, args->batch_len); | |
2419 | #endif | |
2420 | ||
4f481ed2 EA |
2421 | if (args->buffer_count < 1) { |
2422 | DRM_ERROR("execbuf with %d buffers\n", args->buffer_count); | |
2423 | return -EINVAL; | |
2424 | } | |
673a394b EA |
2425 | /* Copy in the exec list from userland */ |
2426 | exec_list = drm_calloc(sizeof(*exec_list), args->buffer_count, | |
2427 | DRM_MEM_DRIVER); | |
2428 | object_list = drm_calloc(sizeof(*object_list), args->buffer_count, | |
2429 | DRM_MEM_DRIVER); | |
2430 | if (exec_list == NULL || object_list == NULL) { | |
2431 | DRM_ERROR("Failed to allocate exec or object list " | |
2432 | "for %d buffers\n", | |
2433 | args->buffer_count); | |
2434 | ret = -ENOMEM; | |
2435 | goto pre_mutex_err; | |
2436 | } | |
2437 | ret = copy_from_user(exec_list, | |
2438 | (struct drm_i915_relocation_entry __user *) | |
2439 | (uintptr_t) args->buffers_ptr, | |
2440 | sizeof(*exec_list) * args->buffer_count); | |
2441 | if (ret != 0) { | |
2442 | DRM_ERROR("copy %d exec entries failed %d\n", | |
2443 | args->buffer_count, ret); | |
2444 | goto pre_mutex_err; | |
2445 | } | |
2446 | ||
2447 | mutex_lock(&dev->struct_mutex); | |
2448 | ||
2449 | i915_verify_inactive(dev, __FILE__, __LINE__); | |
2450 | ||
2451 | if (dev_priv->mm.wedged) { | |
2452 | DRM_ERROR("Execbuf while wedged\n"); | |
2453 | mutex_unlock(&dev->struct_mutex); | |
2454 | return -EIO; | |
2455 | } | |
2456 | ||
2457 | if (dev_priv->mm.suspended) { | |
2458 | DRM_ERROR("Execbuf while VT-switched.\n"); | |
2459 | mutex_unlock(&dev->struct_mutex); | |
2460 | return -EBUSY; | |
2461 | } | |
2462 | ||
ac94a962 | 2463 | /* Look up object handles */ |
673a394b EA |
2464 | for (i = 0; i < args->buffer_count; i++) { |
2465 | object_list[i] = drm_gem_object_lookup(dev, file_priv, | |
2466 | exec_list[i].handle); | |
2467 | if (object_list[i] == NULL) { | |
2468 | DRM_ERROR("Invalid object handle %d at index %d\n", | |
2469 | exec_list[i].handle, i); | |
2470 | ret = -EBADF; | |
2471 | goto err; | |
2472 | } | |
ac94a962 | 2473 | } |
673a394b | 2474 | |
ac94a962 KP |
2475 | /* Pin and relocate */ |
2476 | for (pin_tries = 0; ; pin_tries++) { | |
2477 | ret = 0; | |
2478 | for (i = 0; i < args->buffer_count; i++) { | |
2479 | object_list[i]->pending_read_domains = 0; | |
2480 | object_list[i]->pending_write_domain = 0; | |
2481 | ret = i915_gem_object_pin_and_relocate(object_list[i], | |
2482 | file_priv, | |
2483 | &exec_list[i]); | |
2484 | if (ret) | |
2485 | break; | |
2486 | pinned = i + 1; | |
2487 | } | |
2488 | /* success */ | |
2489 | if (ret == 0) | |
2490 | break; | |
2491 | ||
2492 | /* error other than GTT full, or we've already tried again */ | |
2493 | if (ret != -ENOMEM || pin_tries >= 1) { | |
2494 | DRM_ERROR("Failed to pin buffers %d\n", ret); | |
673a394b EA |
2495 | goto err; |
2496 | } | |
ac94a962 KP |
2497 | |
2498 | /* unpin all of our buffers */ | |
2499 | for (i = 0; i < pinned; i++) | |
2500 | i915_gem_object_unpin(object_list[i]); | |
b1177636 | 2501 | pinned = 0; |
ac94a962 KP |
2502 | |
2503 | /* evict everyone we can from the aperture */ | |
2504 | ret = i915_gem_evict_everything(dev); | |
2505 | if (ret) | |
2506 | goto err; | |
673a394b EA |
2507 | } |
2508 | ||
2509 | /* Set the pending read domains for the batch buffer to COMMAND */ | |
2510 | batch_obj = object_list[args->buffer_count-1]; | |
2511 | batch_obj->pending_read_domains = I915_GEM_DOMAIN_COMMAND; | |
2512 | batch_obj->pending_write_domain = 0; | |
2513 | ||
2514 | i915_verify_inactive(dev, __FILE__, __LINE__); | |
2515 | ||
646f0f6e KP |
2516 | /* Zero the global flush/invalidate flags. These |
2517 | * will be modified as new domains are computed | |
2518 | * for each object | |
2519 | */ | |
2520 | dev->invalidate_domains = 0; | |
2521 | dev->flush_domains = 0; | |
2522 | ||
673a394b EA |
2523 | for (i = 0; i < args->buffer_count; i++) { |
2524 | struct drm_gem_object *obj = object_list[i]; | |
673a394b | 2525 | |
646f0f6e | 2526 | /* Compute new gpu domains and update invalidate/flush */ |
c0d90829 KP |
2527 | i915_gem_object_set_to_gpu_domain(obj, |
2528 | obj->pending_read_domains, | |
2529 | obj->pending_write_domain); | |
673a394b EA |
2530 | } |
2531 | ||
2532 | i915_verify_inactive(dev, __FILE__, __LINE__); | |
2533 | ||
646f0f6e KP |
2534 | if (dev->invalidate_domains | dev->flush_domains) { |
2535 | #if WATCH_EXEC | |
2536 | DRM_INFO("%s: invalidate_domains %08x flush_domains %08x\n", | |
2537 | __func__, | |
2538 | dev->invalidate_domains, | |
2539 | dev->flush_domains); | |
2540 | #endif | |
2541 | i915_gem_flush(dev, | |
2542 | dev->invalidate_domains, | |
2543 | dev->flush_domains); | |
2544 | if (dev->flush_domains) | |
2545 | (void)i915_add_request(dev, dev->flush_domains); | |
2546 | } | |
673a394b EA |
2547 | |
2548 | i915_verify_inactive(dev, __FILE__, __LINE__); | |
2549 | ||
2550 | #if WATCH_COHERENCY | |
2551 | for (i = 0; i < args->buffer_count; i++) { | |
2552 | i915_gem_object_check_coherency(object_list[i], | |
2553 | exec_list[i].handle); | |
2554 | } | |
2555 | #endif | |
2556 | ||
2557 | exec_offset = exec_list[args->buffer_count - 1].offset; | |
2558 | ||
2559 | #if WATCH_EXEC | |
2560 | i915_gem_dump_object(object_list[args->buffer_count - 1], | |
2561 | args->batch_len, | |
2562 | __func__, | |
2563 | ~0); | |
2564 | #endif | |
2565 | ||
673a394b EA |
2566 | /* Exec the batchbuffer */ |
2567 | ret = i915_dispatch_gem_execbuffer(dev, args, exec_offset); | |
2568 | if (ret) { | |
2569 | DRM_ERROR("dispatch failed %d\n", ret); | |
2570 | goto err; | |
2571 | } | |
2572 | ||
2573 | /* | |
2574 | * Ensure that the commands in the batch buffer are | |
2575 | * finished before the interrupt fires | |
2576 | */ | |
2577 | flush_domains = i915_retire_commands(dev); | |
2578 | ||
2579 | i915_verify_inactive(dev, __FILE__, __LINE__); | |
2580 | ||
2581 | /* | |
2582 | * Get a seqno representing the execution of the current buffer, | |
2583 | * which we can wait on. We would like to mitigate these interrupts, | |
2584 | * likely by only creating seqnos occasionally (so that we have | |
2585 | * *some* interrupts representing completion of buffers that we can | |
2586 | * wait on when trying to clear up gtt space). | |
2587 | */ | |
2588 | seqno = i915_add_request(dev, flush_domains); | |
2589 | BUG_ON(seqno == 0); | |
2590 | i915_file_priv->mm.last_gem_seqno = seqno; | |
2591 | for (i = 0; i < args->buffer_count; i++) { | |
2592 | struct drm_gem_object *obj = object_list[i]; | |
673a394b | 2593 | |
ce44b0ea | 2594 | i915_gem_object_move_to_active(obj, seqno); |
673a394b EA |
2595 | #if WATCH_LRU |
2596 | DRM_INFO("%s: move to exec list %p\n", __func__, obj); | |
2597 | #endif | |
2598 | } | |
2599 | #if WATCH_LRU | |
2600 | i915_dump_lru(dev, __func__); | |
2601 | #endif | |
2602 | ||
2603 | i915_verify_inactive(dev, __FILE__, __LINE__); | |
2604 | ||
2605 | /* Copy the new buffer offsets back to the user's exec list. */ | |
2606 | ret = copy_to_user((struct drm_i915_relocation_entry __user *) | |
2607 | (uintptr_t) args->buffers_ptr, | |
2608 | exec_list, | |
2609 | sizeof(*exec_list) * args->buffer_count); | |
2610 | if (ret) | |
2611 | DRM_ERROR("failed to copy %d exec entries " | |
2612 | "back to user (%d)\n", | |
2613 | args->buffer_count, ret); | |
2614 | err: | |
2615 | if (object_list != NULL) { | |
2616 | for (i = 0; i < pinned; i++) | |
2617 | i915_gem_object_unpin(object_list[i]); | |
2618 | ||
2619 | for (i = 0; i < args->buffer_count; i++) | |
2620 | drm_gem_object_unreference(object_list[i]); | |
2621 | } | |
2622 | mutex_unlock(&dev->struct_mutex); | |
2623 | ||
2624 | pre_mutex_err: | |
2625 | drm_free(object_list, sizeof(*object_list) * args->buffer_count, | |
2626 | DRM_MEM_DRIVER); | |
2627 | drm_free(exec_list, sizeof(*exec_list) * args->buffer_count, | |
2628 | DRM_MEM_DRIVER); | |
2629 | ||
2630 | return ret; | |
2631 | } | |
2632 | ||
2633 | int | |
2634 | i915_gem_object_pin(struct drm_gem_object *obj, uint32_t alignment) | |
2635 | { | |
2636 | struct drm_device *dev = obj->dev; | |
2637 | struct drm_i915_gem_object *obj_priv = obj->driver_private; | |
2638 | int ret; | |
2639 | ||
2640 | i915_verify_inactive(dev, __FILE__, __LINE__); | |
2641 | if (obj_priv->gtt_space == NULL) { | |
2642 | ret = i915_gem_object_bind_to_gtt(obj, alignment); | |
2643 | if (ret != 0) { | |
2644 | DRM_ERROR("Failure to bind: %d", ret); | |
2645 | return ret; | |
2646 | } | |
2647 | } | |
2648 | obj_priv->pin_count++; | |
2649 | ||
2650 | /* If the object is not active and not pending a flush, | |
2651 | * remove it from the inactive list | |
2652 | */ | |
2653 | if (obj_priv->pin_count == 1) { | |
2654 | atomic_inc(&dev->pin_count); | |
2655 | atomic_add(obj->size, &dev->pin_memory); | |
2656 | if (!obj_priv->active && | |
2657 | (obj->write_domain & ~(I915_GEM_DOMAIN_CPU | | |
2658 | I915_GEM_DOMAIN_GTT)) == 0 && | |
2659 | !list_empty(&obj_priv->list)) | |
2660 | list_del_init(&obj_priv->list); | |
2661 | } | |
2662 | i915_verify_inactive(dev, __FILE__, __LINE__); | |
2663 | ||
2664 | return 0; | |
2665 | } | |
2666 | ||
2667 | void | |
2668 | i915_gem_object_unpin(struct drm_gem_object *obj) | |
2669 | { | |
2670 | struct drm_device *dev = obj->dev; | |
2671 | drm_i915_private_t *dev_priv = dev->dev_private; | |
2672 | struct drm_i915_gem_object *obj_priv = obj->driver_private; | |
2673 | ||
2674 | i915_verify_inactive(dev, __FILE__, __LINE__); | |
2675 | obj_priv->pin_count--; | |
2676 | BUG_ON(obj_priv->pin_count < 0); | |
2677 | BUG_ON(obj_priv->gtt_space == NULL); | |
2678 | ||
2679 | /* If the object is no longer pinned, and is | |
2680 | * neither active nor being flushed, then stick it on | |
2681 | * the inactive list | |
2682 | */ | |
2683 | if (obj_priv->pin_count == 0) { | |
2684 | if (!obj_priv->active && | |
2685 | (obj->write_domain & ~(I915_GEM_DOMAIN_CPU | | |
2686 | I915_GEM_DOMAIN_GTT)) == 0) | |
2687 | list_move_tail(&obj_priv->list, | |
2688 | &dev_priv->mm.inactive_list); | |
2689 | atomic_dec(&dev->pin_count); | |
2690 | atomic_sub(obj->size, &dev->pin_memory); | |
2691 | } | |
2692 | i915_verify_inactive(dev, __FILE__, __LINE__); | |
2693 | } | |
2694 | ||
2695 | int | |
2696 | i915_gem_pin_ioctl(struct drm_device *dev, void *data, | |
2697 | struct drm_file *file_priv) | |
2698 | { | |
2699 | struct drm_i915_gem_pin *args = data; | |
2700 | struct drm_gem_object *obj; | |
2701 | struct drm_i915_gem_object *obj_priv; | |
2702 | int ret; | |
2703 | ||
2704 | mutex_lock(&dev->struct_mutex); | |
2705 | ||
2706 | obj = drm_gem_object_lookup(dev, file_priv, args->handle); | |
2707 | if (obj == NULL) { | |
2708 | DRM_ERROR("Bad handle in i915_gem_pin_ioctl(): %d\n", | |
2709 | args->handle); | |
2710 | mutex_unlock(&dev->struct_mutex); | |
2711 | return -EBADF; | |
2712 | } | |
2713 | obj_priv = obj->driver_private; | |
2714 | ||
79e53945 JB |
2715 | if (obj_priv->pin_filp != NULL && obj_priv->pin_filp != file_priv) { |
2716 | DRM_ERROR("Already pinned in i915_gem_pin_ioctl(): %d\n", | |
2717 | args->handle); | |
673a394b | 2718 | mutex_unlock(&dev->struct_mutex); |
79e53945 JB |
2719 | return -EINVAL; |
2720 | } | |
2721 | ||
2722 | obj_priv->user_pin_count++; | |
2723 | obj_priv->pin_filp = file_priv; | |
2724 | if (obj_priv->user_pin_count == 1) { | |
2725 | ret = i915_gem_object_pin(obj, args->alignment); | |
2726 | if (ret != 0) { | |
2727 | drm_gem_object_unreference(obj); | |
2728 | mutex_unlock(&dev->struct_mutex); | |
2729 | return ret; | |
2730 | } | |
673a394b EA |
2731 | } |
2732 | ||
2733 | /* XXX - flush the CPU caches for pinned objects | |
2734 | * as the X server doesn't manage domains yet | |
2735 | */ | |
e47c68e9 | 2736 | i915_gem_object_flush_cpu_write_domain(obj); |
673a394b EA |
2737 | args->offset = obj_priv->gtt_offset; |
2738 | drm_gem_object_unreference(obj); | |
2739 | mutex_unlock(&dev->struct_mutex); | |
2740 | ||
2741 | return 0; | |
2742 | } | |
2743 | ||
2744 | int | |
2745 | i915_gem_unpin_ioctl(struct drm_device *dev, void *data, | |
2746 | struct drm_file *file_priv) | |
2747 | { | |
2748 | struct drm_i915_gem_pin *args = data; | |
2749 | struct drm_gem_object *obj; | |
79e53945 | 2750 | struct drm_i915_gem_object *obj_priv; |
673a394b EA |
2751 | |
2752 | mutex_lock(&dev->struct_mutex); | |
2753 | ||
2754 | obj = drm_gem_object_lookup(dev, file_priv, args->handle); | |
2755 | if (obj == NULL) { | |
2756 | DRM_ERROR("Bad handle in i915_gem_unpin_ioctl(): %d\n", | |
2757 | args->handle); | |
2758 | mutex_unlock(&dev->struct_mutex); | |
2759 | return -EBADF; | |
2760 | } | |
2761 | ||
79e53945 JB |
2762 | obj_priv = obj->driver_private; |
2763 | if (obj_priv->pin_filp != file_priv) { | |
2764 | DRM_ERROR("Not pinned by caller in i915_gem_pin_ioctl(): %d\n", | |
2765 | args->handle); | |
2766 | drm_gem_object_unreference(obj); | |
2767 | mutex_unlock(&dev->struct_mutex); | |
2768 | return -EINVAL; | |
2769 | } | |
2770 | obj_priv->user_pin_count--; | |
2771 | if (obj_priv->user_pin_count == 0) { | |
2772 | obj_priv->pin_filp = NULL; | |
2773 | i915_gem_object_unpin(obj); | |
2774 | } | |
673a394b EA |
2775 | |
2776 | drm_gem_object_unreference(obj); | |
2777 | mutex_unlock(&dev->struct_mutex); | |
2778 | return 0; | |
2779 | } | |
2780 | ||
2781 | int | |
2782 | i915_gem_busy_ioctl(struct drm_device *dev, void *data, | |
2783 | struct drm_file *file_priv) | |
2784 | { | |
2785 | struct drm_i915_gem_busy *args = data; | |
2786 | struct drm_gem_object *obj; | |
2787 | struct drm_i915_gem_object *obj_priv; | |
2788 | ||
2789 | mutex_lock(&dev->struct_mutex); | |
2790 | obj = drm_gem_object_lookup(dev, file_priv, args->handle); | |
2791 | if (obj == NULL) { | |
2792 | DRM_ERROR("Bad handle in i915_gem_busy_ioctl(): %d\n", | |
2793 | args->handle); | |
2794 | mutex_unlock(&dev->struct_mutex); | |
2795 | return -EBADF; | |
2796 | } | |
2797 | ||
2798 | obj_priv = obj->driver_private; | |
c4de0a5d EA |
2799 | /* Don't count being on the flushing list against the object being |
2800 | * done. Otherwise, a buffer left on the flushing list but not getting | |
2801 | * flushed (because nobody's flushing that domain) won't ever return | |
2802 | * unbusy and get reused by libdrm's bo cache. The other expected | |
2803 | * consumer of this interface, OpenGL's occlusion queries, also specs | |
2804 | * that the objects get unbusy "eventually" without any interference. | |
2805 | */ | |
2806 | args->busy = obj_priv->active && obj_priv->last_rendering_seqno != 0; | |
673a394b EA |
2807 | |
2808 | drm_gem_object_unreference(obj); | |
2809 | mutex_unlock(&dev->struct_mutex); | |
2810 | return 0; | |
2811 | } | |
2812 | ||
2813 | int | |
2814 | i915_gem_throttle_ioctl(struct drm_device *dev, void *data, | |
2815 | struct drm_file *file_priv) | |
2816 | { | |
2817 | return i915_gem_ring_throttle(dev, file_priv); | |
2818 | } | |
2819 | ||
2820 | int i915_gem_init_object(struct drm_gem_object *obj) | |
2821 | { | |
2822 | struct drm_i915_gem_object *obj_priv; | |
2823 | ||
2824 | obj_priv = drm_calloc(1, sizeof(*obj_priv), DRM_MEM_DRIVER); | |
2825 | if (obj_priv == NULL) | |
2826 | return -ENOMEM; | |
2827 | ||
2828 | /* | |
2829 | * We've just allocated pages from the kernel, | |
2830 | * so they've just been written by the CPU with | |
2831 | * zeros. They'll need to be clflushed before we | |
2832 | * use them with the GPU. | |
2833 | */ | |
2834 | obj->write_domain = I915_GEM_DOMAIN_CPU; | |
2835 | obj->read_domains = I915_GEM_DOMAIN_CPU; | |
2836 | ||
ba1eb1d8 KP |
2837 | obj_priv->agp_type = AGP_USER_MEMORY; |
2838 | ||
673a394b EA |
2839 | obj->driver_private = obj_priv; |
2840 | obj_priv->obj = obj; | |
de151cf6 | 2841 | obj_priv->fence_reg = I915_FENCE_REG_NONE; |
673a394b | 2842 | INIT_LIST_HEAD(&obj_priv->list); |
de151cf6 | 2843 | |
673a394b EA |
2844 | return 0; |
2845 | } | |
2846 | ||
2847 | void i915_gem_free_object(struct drm_gem_object *obj) | |
2848 | { | |
de151cf6 JB |
2849 | struct drm_device *dev = obj->dev; |
2850 | struct drm_gem_mm *mm = dev->mm_private; | |
2851 | struct drm_map_list *list; | |
2852 | struct drm_map *map; | |
673a394b EA |
2853 | struct drm_i915_gem_object *obj_priv = obj->driver_private; |
2854 | ||
2855 | while (obj_priv->pin_count > 0) | |
2856 | i915_gem_object_unpin(obj); | |
2857 | ||
2858 | i915_gem_object_unbind(obj); | |
2859 | ||
de151cf6 JB |
2860 | list = &obj->map_list; |
2861 | drm_ht_remove_item(&mm->offset_hash, &list->hash); | |
2862 | ||
2863 | if (list->file_offset_node) { | |
2864 | drm_mm_put_block(list->file_offset_node); | |
2865 | list->file_offset_node = NULL; | |
2866 | } | |
2867 | ||
2868 | map = list->map; | |
2869 | if (map) { | |
2870 | drm_free(map, sizeof(*map), DRM_MEM_DRIVER); | |
2871 | list->map = NULL; | |
2872 | } | |
2873 | ||
673a394b EA |
2874 | drm_free(obj_priv->page_cpu_valid, 1, DRM_MEM_DRIVER); |
2875 | drm_free(obj->driver_private, 1, DRM_MEM_DRIVER); | |
2876 | } | |
2877 | ||
673a394b EA |
2878 | /** Unbinds all objects that are on the given buffer list. */ |
2879 | static int | |
2880 | i915_gem_evict_from_list(struct drm_device *dev, struct list_head *head) | |
2881 | { | |
2882 | struct drm_gem_object *obj; | |
2883 | struct drm_i915_gem_object *obj_priv; | |
2884 | int ret; | |
2885 | ||
2886 | while (!list_empty(head)) { | |
2887 | obj_priv = list_first_entry(head, | |
2888 | struct drm_i915_gem_object, | |
2889 | list); | |
2890 | obj = obj_priv->obj; | |
2891 | ||
2892 | if (obj_priv->pin_count != 0) { | |
2893 | DRM_ERROR("Pinned object in unbind list\n"); | |
2894 | mutex_unlock(&dev->struct_mutex); | |
2895 | return -EINVAL; | |
2896 | } | |
2897 | ||
2898 | ret = i915_gem_object_unbind(obj); | |
2899 | if (ret != 0) { | |
2900 | DRM_ERROR("Error unbinding object in LeaveVT: %d\n", | |
2901 | ret); | |
2902 | mutex_unlock(&dev->struct_mutex); | |
2903 | return ret; | |
2904 | } | |
2905 | } | |
2906 | ||
2907 | ||
2908 | return 0; | |
2909 | } | |
2910 | ||
2911 | static int | |
2912 | i915_gem_idle(struct drm_device *dev) | |
2913 | { | |
2914 | drm_i915_private_t *dev_priv = dev->dev_private; | |
2915 | uint32_t seqno, cur_seqno, last_seqno; | |
2916 | int stuck, ret; | |
2917 | ||
6dbe2772 KP |
2918 | mutex_lock(&dev->struct_mutex); |
2919 | ||
2920 | if (dev_priv->mm.suspended || dev_priv->ring.ring_obj == NULL) { | |
2921 | mutex_unlock(&dev->struct_mutex); | |
673a394b | 2922 | return 0; |
6dbe2772 | 2923 | } |
673a394b EA |
2924 | |
2925 | /* Hack! Don't let anybody do execbuf while we don't control the chip. | |
2926 | * We need to replace this with a semaphore, or something. | |
2927 | */ | |
2928 | dev_priv->mm.suspended = 1; | |
2929 | ||
6dbe2772 KP |
2930 | /* Cancel the retire work handler, wait for it to finish if running |
2931 | */ | |
2932 | mutex_unlock(&dev->struct_mutex); | |
2933 | cancel_delayed_work_sync(&dev_priv->mm.retire_work); | |
2934 | mutex_lock(&dev->struct_mutex); | |
2935 | ||
673a394b EA |
2936 | i915_kernel_lost_context(dev); |
2937 | ||
2938 | /* Flush the GPU along with all non-CPU write domains | |
2939 | */ | |
2940 | i915_gem_flush(dev, ~(I915_GEM_DOMAIN_CPU|I915_GEM_DOMAIN_GTT), | |
2941 | ~(I915_GEM_DOMAIN_CPU|I915_GEM_DOMAIN_GTT)); | |
de151cf6 | 2942 | seqno = i915_add_request(dev, ~I915_GEM_DOMAIN_CPU); |
673a394b EA |
2943 | |
2944 | if (seqno == 0) { | |
2945 | mutex_unlock(&dev->struct_mutex); | |
2946 | return -ENOMEM; | |
2947 | } | |
2948 | ||
2949 | dev_priv->mm.waiting_gem_seqno = seqno; | |
2950 | last_seqno = 0; | |
2951 | stuck = 0; | |
2952 | for (;;) { | |
2953 | cur_seqno = i915_get_gem_seqno(dev); | |
2954 | if (i915_seqno_passed(cur_seqno, seqno)) | |
2955 | break; | |
2956 | if (last_seqno == cur_seqno) { | |
2957 | if (stuck++ > 100) { | |
2958 | DRM_ERROR("hardware wedged\n"); | |
2959 | dev_priv->mm.wedged = 1; | |
2960 | DRM_WAKEUP(&dev_priv->irq_queue); | |
2961 | break; | |
2962 | } | |
2963 | } | |
2964 | msleep(10); | |
2965 | last_seqno = cur_seqno; | |
2966 | } | |
2967 | dev_priv->mm.waiting_gem_seqno = 0; | |
2968 | ||
2969 | i915_gem_retire_requests(dev); | |
2970 | ||
28dfe52a EA |
2971 | if (!dev_priv->mm.wedged) { |
2972 | /* Active and flushing should now be empty as we've | |
2973 | * waited for a sequence higher than any pending execbuffer | |
2974 | */ | |
2975 | WARN_ON(!list_empty(&dev_priv->mm.active_list)); | |
2976 | WARN_ON(!list_empty(&dev_priv->mm.flushing_list)); | |
2977 | /* Request should now be empty as we've also waited | |
2978 | * for the last request in the list | |
2979 | */ | |
2980 | WARN_ON(!list_empty(&dev_priv->mm.request_list)); | |
2981 | } | |
673a394b | 2982 | |
28dfe52a EA |
2983 | /* Empty the active and flushing lists to inactive. If there's |
2984 | * anything left at this point, it means that we're wedged and | |
2985 | * nothing good's going to happen by leaving them there. So strip | |
2986 | * the GPU domains and just stuff them onto inactive. | |
673a394b | 2987 | */ |
28dfe52a EA |
2988 | while (!list_empty(&dev_priv->mm.active_list)) { |
2989 | struct drm_i915_gem_object *obj_priv; | |
673a394b | 2990 | |
28dfe52a EA |
2991 | obj_priv = list_first_entry(&dev_priv->mm.active_list, |
2992 | struct drm_i915_gem_object, | |
2993 | list); | |
2994 | obj_priv->obj->write_domain &= ~I915_GEM_GPU_DOMAINS; | |
2995 | i915_gem_object_move_to_inactive(obj_priv->obj); | |
2996 | } | |
2997 | ||
2998 | while (!list_empty(&dev_priv->mm.flushing_list)) { | |
2999 | struct drm_i915_gem_object *obj_priv; | |
3000 | ||
151903d5 | 3001 | obj_priv = list_first_entry(&dev_priv->mm.flushing_list, |
28dfe52a EA |
3002 | struct drm_i915_gem_object, |
3003 | list); | |
3004 | obj_priv->obj->write_domain &= ~I915_GEM_GPU_DOMAINS; | |
3005 | i915_gem_object_move_to_inactive(obj_priv->obj); | |
3006 | } | |
3007 | ||
3008 | ||
3009 | /* Move all inactive buffers out of the GTT. */ | |
673a394b | 3010 | ret = i915_gem_evict_from_list(dev, &dev_priv->mm.inactive_list); |
28dfe52a | 3011 | WARN_ON(!list_empty(&dev_priv->mm.inactive_list)); |
6dbe2772 KP |
3012 | if (ret) { |
3013 | mutex_unlock(&dev->struct_mutex); | |
673a394b | 3014 | return ret; |
6dbe2772 | 3015 | } |
673a394b | 3016 | |
6dbe2772 KP |
3017 | i915_gem_cleanup_ringbuffer(dev); |
3018 | mutex_unlock(&dev->struct_mutex); | |
3019 | ||
673a394b EA |
3020 | return 0; |
3021 | } | |
3022 | ||
3023 | static int | |
3024 | i915_gem_init_hws(struct drm_device *dev) | |
3025 | { | |
3026 | drm_i915_private_t *dev_priv = dev->dev_private; | |
3027 | struct drm_gem_object *obj; | |
3028 | struct drm_i915_gem_object *obj_priv; | |
3029 | int ret; | |
3030 | ||
3031 | /* If we need a physical address for the status page, it's already | |
3032 | * initialized at driver load time. | |
3033 | */ | |
3034 | if (!I915_NEED_GFX_HWS(dev)) | |
3035 | return 0; | |
3036 | ||
3037 | obj = drm_gem_object_alloc(dev, 4096); | |
3038 | if (obj == NULL) { | |
3039 | DRM_ERROR("Failed to allocate status page\n"); | |
3040 | return -ENOMEM; | |
3041 | } | |
3042 | obj_priv = obj->driver_private; | |
ba1eb1d8 | 3043 | obj_priv->agp_type = AGP_USER_CACHED_MEMORY; |
673a394b EA |
3044 | |
3045 | ret = i915_gem_object_pin(obj, 4096); | |
3046 | if (ret != 0) { | |
3047 | drm_gem_object_unreference(obj); | |
3048 | return ret; | |
3049 | } | |
3050 | ||
3051 | dev_priv->status_gfx_addr = obj_priv->gtt_offset; | |
673a394b | 3052 | |
ba1eb1d8 KP |
3053 | dev_priv->hw_status_page = kmap(obj_priv->page_list[0]); |
3054 | if (dev_priv->hw_status_page == NULL) { | |
673a394b EA |
3055 | DRM_ERROR("Failed to map status page.\n"); |
3056 | memset(&dev_priv->hws_map, 0, sizeof(dev_priv->hws_map)); | |
3057 | drm_gem_object_unreference(obj); | |
3058 | return -EINVAL; | |
3059 | } | |
3060 | dev_priv->hws_obj = obj; | |
673a394b EA |
3061 | memset(dev_priv->hw_status_page, 0, PAGE_SIZE); |
3062 | I915_WRITE(HWS_PGA, dev_priv->status_gfx_addr); | |
ba1eb1d8 | 3063 | I915_READ(HWS_PGA); /* posting read */ |
673a394b EA |
3064 | DRM_DEBUG("hws offset: 0x%08x\n", dev_priv->status_gfx_addr); |
3065 | ||
3066 | return 0; | |
3067 | } | |
3068 | ||
79e53945 | 3069 | int |
673a394b EA |
3070 | i915_gem_init_ringbuffer(struct drm_device *dev) |
3071 | { | |
3072 | drm_i915_private_t *dev_priv = dev->dev_private; | |
3073 | struct drm_gem_object *obj; | |
3074 | struct drm_i915_gem_object *obj_priv; | |
79e53945 | 3075 | drm_i915_ring_buffer_t *ring = &dev_priv->ring; |
673a394b | 3076 | int ret; |
50aa253d | 3077 | u32 head; |
673a394b EA |
3078 | |
3079 | ret = i915_gem_init_hws(dev); | |
3080 | if (ret != 0) | |
3081 | return ret; | |
3082 | ||
3083 | obj = drm_gem_object_alloc(dev, 128 * 1024); | |
3084 | if (obj == NULL) { | |
3085 | DRM_ERROR("Failed to allocate ringbuffer\n"); | |
3086 | return -ENOMEM; | |
3087 | } | |
3088 | obj_priv = obj->driver_private; | |
3089 | ||
3090 | ret = i915_gem_object_pin(obj, 4096); | |
3091 | if (ret != 0) { | |
3092 | drm_gem_object_unreference(obj); | |
3093 | return ret; | |
3094 | } | |
3095 | ||
3096 | /* Set up the kernel mapping for the ring. */ | |
79e53945 JB |
3097 | ring->Size = obj->size; |
3098 | ring->tail_mask = obj->size - 1; | |
673a394b | 3099 | |
79e53945 JB |
3100 | ring->map.offset = dev->agp->base + obj_priv->gtt_offset; |
3101 | ring->map.size = obj->size; | |
3102 | ring->map.type = 0; | |
3103 | ring->map.flags = 0; | |
3104 | ring->map.mtrr = 0; | |
673a394b | 3105 | |
79e53945 JB |
3106 | drm_core_ioremap_wc(&ring->map, dev); |
3107 | if (ring->map.handle == NULL) { | |
673a394b EA |
3108 | DRM_ERROR("Failed to map ringbuffer.\n"); |
3109 | memset(&dev_priv->ring, 0, sizeof(dev_priv->ring)); | |
3110 | drm_gem_object_unreference(obj); | |
3111 | return -EINVAL; | |
3112 | } | |
79e53945 JB |
3113 | ring->ring_obj = obj; |
3114 | ring->virtual_start = ring->map.handle; | |
673a394b EA |
3115 | |
3116 | /* Stop the ring if it's running. */ | |
3117 | I915_WRITE(PRB0_CTL, 0); | |
673a394b | 3118 | I915_WRITE(PRB0_TAIL, 0); |
50aa253d | 3119 | I915_WRITE(PRB0_HEAD, 0); |
673a394b EA |
3120 | |
3121 | /* Initialize the ring. */ | |
3122 | I915_WRITE(PRB0_START, obj_priv->gtt_offset); | |
50aa253d KP |
3123 | head = I915_READ(PRB0_HEAD) & HEAD_ADDR; |
3124 | ||
3125 | /* G45 ring initialization fails to reset head to zero */ | |
3126 | if (head != 0) { | |
3127 | DRM_ERROR("Ring head not reset to zero " | |
3128 | "ctl %08x head %08x tail %08x start %08x\n", | |
3129 | I915_READ(PRB0_CTL), | |
3130 | I915_READ(PRB0_HEAD), | |
3131 | I915_READ(PRB0_TAIL), | |
3132 | I915_READ(PRB0_START)); | |
3133 | I915_WRITE(PRB0_HEAD, 0); | |
3134 | ||
3135 | DRM_ERROR("Ring head forced to zero " | |
3136 | "ctl %08x head %08x tail %08x start %08x\n", | |
3137 | I915_READ(PRB0_CTL), | |
3138 | I915_READ(PRB0_HEAD), | |
3139 | I915_READ(PRB0_TAIL), | |
3140 | I915_READ(PRB0_START)); | |
3141 | } | |
3142 | ||
673a394b EA |
3143 | I915_WRITE(PRB0_CTL, |
3144 | ((obj->size - 4096) & RING_NR_PAGES) | | |
3145 | RING_NO_REPORT | | |
3146 | RING_VALID); | |
3147 | ||
50aa253d KP |
3148 | head = I915_READ(PRB0_HEAD) & HEAD_ADDR; |
3149 | ||
3150 | /* If the head is still not zero, the ring is dead */ | |
3151 | if (head != 0) { | |
3152 | DRM_ERROR("Ring initialization failed " | |
3153 | "ctl %08x head %08x tail %08x start %08x\n", | |
3154 | I915_READ(PRB0_CTL), | |
3155 | I915_READ(PRB0_HEAD), | |
3156 | I915_READ(PRB0_TAIL), | |
3157 | I915_READ(PRB0_START)); | |
3158 | return -EIO; | |
3159 | } | |
3160 | ||
673a394b | 3161 | /* Update our cache of the ring state */ |
79e53945 JB |
3162 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) |
3163 | i915_kernel_lost_context(dev); | |
3164 | else { | |
3165 | ring->head = I915_READ(PRB0_HEAD) & HEAD_ADDR; | |
3166 | ring->tail = I915_READ(PRB0_TAIL) & TAIL_ADDR; | |
3167 | ring->space = ring->head - (ring->tail + 8); | |
3168 | if (ring->space < 0) | |
3169 | ring->space += ring->Size; | |
3170 | } | |
673a394b EA |
3171 | |
3172 | return 0; | |
3173 | } | |
3174 | ||
79e53945 | 3175 | void |
673a394b EA |
3176 | i915_gem_cleanup_ringbuffer(struct drm_device *dev) |
3177 | { | |
3178 | drm_i915_private_t *dev_priv = dev->dev_private; | |
3179 | ||
3180 | if (dev_priv->ring.ring_obj == NULL) | |
3181 | return; | |
3182 | ||
3183 | drm_core_ioremapfree(&dev_priv->ring.map, dev); | |
3184 | ||
3185 | i915_gem_object_unpin(dev_priv->ring.ring_obj); | |
3186 | drm_gem_object_unreference(dev_priv->ring.ring_obj); | |
3187 | dev_priv->ring.ring_obj = NULL; | |
3188 | memset(&dev_priv->ring, 0, sizeof(dev_priv->ring)); | |
3189 | ||
3190 | if (dev_priv->hws_obj != NULL) { | |
ba1eb1d8 KP |
3191 | struct drm_gem_object *obj = dev_priv->hws_obj; |
3192 | struct drm_i915_gem_object *obj_priv = obj->driver_private; | |
3193 | ||
3194 | kunmap(obj_priv->page_list[0]); | |
3195 | i915_gem_object_unpin(obj); | |
3196 | drm_gem_object_unreference(obj); | |
673a394b EA |
3197 | dev_priv->hws_obj = NULL; |
3198 | memset(&dev_priv->hws_map, 0, sizeof(dev_priv->hws_map)); | |
ba1eb1d8 | 3199 | dev_priv->hw_status_page = NULL; |
673a394b EA |
3200 | |
3201 | /* Write high address into HWS_PGA when disabling. */ | |
3202 | I915_WRITE(HWS_PGA, 0x1ffff000); | |
3203 | } | |
3204 | } | |
3205 | ||
3206 | int | |
3207 | i915_gem_entervt_ioctl(struct drm_device *dev, void *data, | |
3208 | struct drm_file *file_priv) | |
3209 | { | |
3210 | drm_i915_private_t *dev_priv = dev->dev_private; | |
3211 | int ret; | |
3212 | ||
79e53945 JB |
3213 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
3214 | return 0; | |
3215 | ||
673a394b EA |
3216 | if (dev_priv->mm.wedged) { |
3217 | DRM_ERROR("Reenabling wedged hardware, good luck\n"); | |
3218 | dev_priv->mm.wedged = 0; | |
3219 | } | |
3220 | ||
3221 | ret = i915_gem_init_ringbuffer(dev); | |
3222 | if (ret != 0) | |
3223 | return ret; | |
3224 | ||
0839ccb8 KP |
3225 | dev_priv->mm.gtt_mapping = io_mapping_create_wc(dev->agp->base, |
3226 | dev->agp->agp_info.aper_size | |
3227 | * 1024 * 1024); | |
3228 | ||
673a394b EA |
3229 | mutex_lock(&dev->struct_mutex); |
3230 | BUG_ON(!list_empty(&dev_priv->mm.active_list)); | |
3231 | BUG_ON(!list_empty(&dev_priv->mm.flushing_list)); | |
3232 | BUG_ON(!list_empty(&dev_priv->mm.inactive_list)); | |
3233 | BUG_ON(!list_empty(&dev_priv->mm.request_list)); | |
3234 | dev_priv->mm.suspended = 0; | |
3235 | mutex_unlock(&dev->struct_mutex); | |
dbb19d30 KH |
3236 | |
3237 | drm_irq_install(dev); | |
3238 | ||
673a394b EA |
3239 | return 0; |
3240 | } | |
3241 | ||
3242 | int | |
3243 | i915_gem_leavevt_ioctl(struct drm_device *dev, void *data, | |
3244 | struct drm_file *file_priv) | |
3245 | { | |
0839ccb8 | 3246 | drm_i915_private_t *dev_priv = dev->dev_private; |
673a394b EA |
3247 | int ret; |
3248 | ||
79e53945 JB |
3249 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
3250 | return 0; | |
3251 | ||
673a394b | 3252 | ret = i915_gem_idle(dev); |
dbb19d30 KH |
3253 | drm_irq_uninstall(dev); |
3254 | ||
0839ccb8 | 3255 | io_mapping_free(dev_priv->mm.gtt_mapping); |
6dbe2772 | 3256 | return ret; |
673a394b EA |
3257 | } |
3258 | ||
3259 | void | |
3260 | i915_gem_lastclose(struct drm_device *dev) | |
3261 | { | |
3262 | int ret; | |
673a394b | 3263 | |
6dbe2772 KP |
3264 | ret = i915_gem_idle(dev); |
3265 | if (ret) | |
3266 | DRM_ERROR("failed to idle hardware: %d\n", ret); | |
673a394b EA |
3267 | } |
3268 | ||
3269 | void | |
3270 | i915_gem_load(struct drm_device *dev) | |
3271 | { | |
3272 | drm_i915_private_t *dev_priv = dev->dev_private; | |
3273 | ||
3274 | INIT_LIST_HEAD(&dev_priv->mm.active_list); | |
3275 | INIT_LIST_HEAD(&dev_priv->mm.flushing_list); | |
3276 | INIT_LIST_HEAD(&dev_priv->mm.inactive_list); | |
3277 | INIT_LIST_HEAD(&dev_priv->mm.request_list); | |
3278 | INIT_DELAYED_WORK(&dev_priv->mm.retire_work, | |
3279 | i915_gem_retire_work_handler); | |
3280 | dev_priv->mm.next_gem_seqno = 1; | |
3281 | ||
de151cf6 JB |
3282 | /* Old X drivers will take 0-2 for front, back, depth buffers */ |
3283 | dev_priv->fence_reg_start = 3; | |
3284 | ||
3285 | if (IS_I965G(dev)) | |
3286 | dev_priv->num_fence_regs = 16; | |
3287 | else | |
3288 | dev_priv->num_fence_regs = 8; | |
3289 | ||
673a394b EA |
3290 | i915_gem_detect_bit_6_swizzle(dev); |
3291 | } |