Commit | Line | Data |
---|---|---|
673a394b EA |
1 | /* |
2 | * Copyright © 2008 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | * | |
26 | */ | |
27 | ||
28 | #include "drmP.h" | |
29 | #include "drm.h" | |
30 | #include "i915_drm.h" | |
31 | #include "i915_drv.h" | |
1c5d22f7 | 32 | #include "i915_trace.h" |
652c393a | 33 | #include "intel_drv.h" |
5a0e3ad6 | 34 | #include <linux/slab.h> |
673a394b | 35 | #include <linux/swap.h> |
79e53945 | 36 | #include <linux/pci.h> |
673a394b | 37 | |
88241785 | 38 | static __must_check int i915_gem_object_flush_gpu_write_domain(struct drm_i915_gem_object *obj); |
05394f39 CW |
39 | static void i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj); |
40 | static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj); | |
88241785 CW |
41 | static __must_check int i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, |
42 | bool write); | |
43 | static __must_check int i915_gem_object_set_cpu_read_domain_range(struct drm_i915_gem_object *obj, | |
44 | uint64_t offset, | |
45 | uint64_t size); | |
05394f39 | 46 | static void i915_gem_object_set_to_full_cpu_read_domain(struct drm_i915_gem_object *obj); |
88241785 CW |
47 | static __must_check int i915_gem_object_bind_to_gtt(struct drm_i915_gem_object *obj, |
48 | unsigned alignment, | |
49 | bool map_and_fenceable); | |
d9e86c0e CW |
50 | static void i915_gem_clear_fence_reg(struct drm_device *dev, |
51 | struct drm_i915_fence_reg *reg); | |
05394f39 CW |
52 | static int i915_gem_phys_pwrite(struct drm_device *dev, |
53 | struct drm_i915_gem_object *obj, | |
71acb5eb | 54 | struct drm_i915_gem_pwrite *args, |
05394f39 CW |
55 | struct drm_file *file); |
56 | static void i915_gem_free_object_tail(struct drm_i915_gem_object *obj); | |
673a394b | 57 | |
17250b71 CW |
58 | static int i915_gem_inactive_shrink(struct shrinker *shrinker, |
59 | int nr_to_scan, | |
60 | gfp_t gfp_mask); | |
61 | ||
31169714 | 62 | |
73aa808f CW |
63 | /* some bookkeeping */ |
64 | static void i915_gem_info_add_obj(struct drm_i915_private *dev_priv, | |
65 | size_t size) | |
66 | { | |
67 | dev_priv->mm.object_count++; | |
68 | dev_priv->mm.object_memory += size; | |
69 | } | |
70 | ||
71 | static void i915_gem_info_remove_obj(struct drm_i915_private *dev_priv, | |
72 | size_t size) | |
73 | { | |
74 | dev_priv->mm.object_count--; | |
75 | dev_priv->mm.object_memory -= size; | |
76 | } | |
77 | ||
21dd3734 CW |
78 | static int |
79 | i915_gem_wait_for_error(struct drm_device *dev) | |
30dbf0c0 CW |
80 | { |
81 | struct drm_i915_private *dev_priv = dev->dev_private; | |
82 | struct completion *x = &dev_priv->error_completion; | |
83 | unsigned long flags; | |
84 | int ret; | |
85 | ||
86 | if (!atomic_read(&dev_priv->mm.wedged)) | |
87 | return 0; | |
88 | ||
89 | ret = wait_for_completion_interruptible(x); | |
90 | if (ret) | |
91 | return ret; | |
92 | ||
21dd3734 CW |
93 | if (atomic_read(&dev_priv->mm.wedged)) { |
94 | /* GPU is hung, bump the completion count to account for | |
95 | * the token we just consumed so that we never hit zero and | |
96 | * end up waiting upon a subsequent completion event that | |
97 | * will never happen. | |
98 | */ | |
99 | spin_lock_irqsave(&x->wait.lock, flags); | |
100 | x->done++; | |
101 | spin_unlock_irqrestore(&x->wait.lock, flags); | |
102 | } | |
103 | return 0; | |
30dbf0c0 CW |
104 | } |
105 | ||
54cf91dc | 106 | int i915_mutex_lock_interruptible(struct drm_device *dev) |
76c1dec1 | 107 | { |
76c1dec1 CW |
108 | int ret; |
109 | ||
21dd3734 | 110 | ret = i915_gem_wait_for_error(dev); |
76c1dec1 CW |
111 | if (ret) |
112 | return ret; | |
113 | ||
114 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
115 | if (ret) | |
116 | return ret; | |
117 | ||
23bc5982 | 118 | WARN_ON(i915_verify_lists(dev)); |
76c1dec1 CW |
119 | return 0; |
120 | } | |
30dbf0c0 | 121 | |
7d1c4804 | 122 | static inline bool |
05394f39 | 123 | i915_gem_object_is_inactive(struct drm_i915_gem_object *obj) |
7d1c4804 | 124 | { |
05394f39 | 125 | return obj->gtt_space && !obj->active && obj->pin_count == 0; |
7d1c4804 CW |
126 | } |
127 | ||
2021746e CW |
128 | void i915_gem_do_init(struct drm_device *dev, |
129 | unsigned long start, | |
130 | unsigned long mappable_end, | |
131 | unsigned long end) | |
673a394b EA |
132 | { |
133 | drm_i915_private_t *dev_priv = dev->dev_private; | |
673a394b | 134 | |
bee4a186 | 135 | drm_mm_init(&dev_priv->mm.gtt_space, start, end - start); |
673a394b | 136 | |
bee4a186 CW |
137 | dev_priv->mm.gtt_start = start; |
138 | dev_priv->mm.gtt_mappable_end = mappable_end; | |
139 | dev_priv->mm.gtt_end = end; | |
73aa808f | 140 | dev_priv->mm.gtt_total = end - start; |
fb7d516a | 141 | dev_priv->mm.mappable_gtt_total = min(end, mappable_end) - start; |
bee4a186 CW |
142 | |
143 | /* Take over this portion of the GTT */ | |
144 | intel_gtt_clear_range(start / PAGE_SIZE, (end-start) / PAGE_SIZE); | |
79e53945 | 145 | } |
673a394b | 146 | |
79e53945 JB |
147 | int |
148 | i915_gem_init_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 149 | struct drm_file *file) |
79e53945 JB |
150 | { |
151 | struct drm_i915_gem_init *args = data; | |
2021746e CW |
152 | |
153 | if (args->gtt_start >= args->gtt_end || | |
154 | (args->gtt_end | args->gtt_start) & (PAGE_SIZE - 1)) | |
155 | return -EINVAL; | |
79e53945 JB |
156 | |
157 | mutex_lock(&dev->struct_mutex); | |
2021746e | 158 | i915_gem_do_init(dev, args->gtt_start, args->gtt_end, args->gtt_end); |
673a394b EA |
159 | mutex_unlock(&dev->struct_mutex); |
160 | ||
2021746e | 161 | return 0; |
673a394b EA |
162 | } |
163 | ||
5a125c3c EA |
164 | int |
165 | i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 166 | struct drm_file *file) |
5a125c3c | 167 | { |
73aa808f | 168 | struct drm_i915_private *dev_priv = dev->dev_private; |
5a125c3c | 169 | struct drm_i915_gem_get_aperture *args = data; |
6299f992 CW |
170 | struct drm_i915_gem_object *obj; |
171 | size_t pinned; | |
5a125c3c EA |
172 | |
173 | if (!(dev->driver->driver_features & DRIVER_GEM)) | |
174 | return -ENODEV; | |
175 | ||
6299f992 | 176 | pinned = 0; |
73aa808f | 177 | mutex_lock(&dev->struct_mutex); |
6299f992 CW |
178 | list_for_each_entry(obj, &dev_priv->mm.pinned_list, mm_list) |
179 | pinned += obj->gtt_space->size; | |
73aa808f | 180 | mutex_unlock(&dev->struct_mutex); |
5a125c3c | 181 | |
6299f992 CW |
182 | args->aper_size = dev_priv->mm.gtt_total; |
183 | args->aper_available_size = args->aper_size -pinned; | |
184 | ||
5a125c3c EA |
185 | return 0; |
186 | } | |
187 | ||
ff72145b DA |
188 | static int |
189 | i915_gem_create(struct drm_file *file, | |
190 | struct drm_device *dev, | |
191 | uint64_t size, | |
192 | uint32_t *handle_p) | |
673a394b | 193 | { |
05394f39 | 194 | struct drm_i915_gem_object *obj; |
a1a2d1d3 PP |
195 | int ret; |
196 | u32 handle; | |
673a394b | 197 | |
ff72145b | 198 | size = roundup(size, PAGE_SIZE); |
673a394b EA |
199 | |
200 | /* Allocate the new object */ | |
ff72145b | 201 | obj = i915_gem_alloc_object(dev, size); |
673a394b EA |
202 | if (obj == NULL) |
203 | return -ENOMEM; | |
204 | ||
05394f39 | 205 | ret = drm_gem_handle_create(file, &obj->base, &handle); |
1dfd9754 | 206 | if (ret) { |
05394f39 CW |
207 | drm_gem_object_release(&obj->base); |
208 | i915_gem_info_remove_obj(dev->dev_private, obj->base.size); | |
202f2fef | 209 | kfree(obj); |
673a394b | 210 | return ret; |
1dfd9754 | 211 | } |
673a394b | 212 | |
202f2fef | 213 | /* drop reference from allocate - handle holds it now */ |
05394f39 | 214 | drm_gem_object_unreference(&obj->base); |
202f2fef CW |
215 | trace_i915_gem_object_create(obj); |
216 | ||
ff72145b | 217 | *handle_p = handle; |
673a394b EA |
218 | return 0; |
219 | } | |
220 | ||
ff72145b DA |
221 | int |
222 | i915_gem_dumb_create(struct drm_file *file, | |
223 | struct drm_device *dev, | |
224 | struct drm_mode_create_dumb *args) | |
225 | { | |
226 | /* have to work out size/pitch and return them */ | |
ed0291fd | 227 | args->pitch = ALIGN(args->width * ((args->bpp + 7) / 8), 64); |
ff72145b DA |
228 | args->size = args->pitch * args->height; |
229 | return i915_gem_create(file, dev, | |
230 | args->size, &args->handle); | |
231 | } | |
232 | ||
233 | int i915_gem_dumb_destroy(struct drm_file *file, | |
234 | struct drm_device *dev, | |
235 | uint32_t handle) | |
236 | { | |
237 | return drm_gem_handle_delete(file, handle); | |
238 | } | |
239 | ||
240 | /** | |
241 | * Creates a new mm object and returns a handle to it. | |
242 | */ | |
243 | int | |
244 | i915_gem_create_ioctl(struct drm_device *dev, void *data, | |
245 | struct drm_file *file) | |
246 | { | |
247 | struct drm_i915_gem_create *args = data; | |
248 | return i915_gem_create(file, dev, | |
249 | args->size, &args->handle); | |
250 | } | |
251 | ||
05394f39 | 252 | static int i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj) |
280b713b | 253 | { |
05394f39 | 254 | drm_i915_private_t *dev_priv = obj->base.dev->dev_private; |
280b713b EA |
255 | |
256 | return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 && | |
05394f39 | 257 | obj->tiling_mode != I915_TILING_NONE; |
280b713b EA |
258 | } |
259 | ||
99a03df5 | 260 | static inline void |
40123c1f EA |
261 | slow_shmem_copy(struct page *dst_page, |
262 | int dst_offset, | |
263 | struct page *src_page, | |
264 | int src_offset, | |
265 | int length) | |
266 | { | |
267 | char *dst_vaddr, *src_vaddr; | |
268 | ||
99a03df5 CW |
269 | dst_vaddr = kmap(dst_page); |
270 | src_vaddr = kmap(src_page); | |
40123c1f EA |
271 | |
272 | memcpy(dst_vaddr + dst_offset, src_vaddr + src_offset, length); | |
273 | ||
99a03df5 CW |
274 | kunmap(src_page); |
275 | kunmap(dst_page); | |
40123c1f EA |
276 | } |
277 | ||
99a03df5 | 278 | static inline void |
280b713b EA |
279 | slow_shmem_bit17_copy(struct page *gpu_page, |
280 | int gpu_offset, | |
281 | struct page *cpu_page, | |
282 | int cpu_offset, | |
283 | int length, | |
284 | int is_read) | |
285 | { | |
286 | char *gpu_vaddr, *cpu_vaddr; | |
287 | ||
288 | /* Use the unswizzled path if this page isn't affected. */ | |
289 | if ((page_to_phys(gpu_page) & (1 << 17)) == 0) { | |
290 | if (is_read) | |
291 | return slow_shmem_copy(cpu_page, cpu_offset, | |
292 | gpu_page, gpu_offset, length); | |
293 | else | |
294 | return slow_shmem_copy(gpu_page, gpu_offset, | |
295 | cpu_page, cpu_offset, length); | |
296 | } | |
297 | ||
99a03df5 CW |
298 | gpu_vaddr = kmap(gpu_page); |
299 | cpu_vaddr = kmap(cpu_page); | |
280b713b EA |
300 | |
301 | /* Copy the data, XORing A6 with A17 (1). The user already knows he's | |
302 | * XORing with the other bits (A9 for Y, A9 and A10 for X) | |
303 | */ | |
304 | while (length > 0) { | |
305 | int cacheline_end = ALIGN(gpu_offset + 1, 64); | |
306 | int this_length = min(cacheline_end - gpu_offset, length); | |
307 | int swizzled_gpu_offset = gpu_offset ^ 64; | |
308 | ||
309 | if (is_read) { | |
310 | memcpy(cpu_vaddr + cpu_offset, | |
311 | gpu_vaddr + swizzled_gpu_offset, | |
312 | this_length); | |
313 | } else { | |
314 | memcpy(gpu_vaddr + swizzled_gpu_offset, | |
315 | cpu_vaddr + cpu_offset, | |
316 | this_length); | |
317 | } | |
318 | cpu_offset += this_length; | |
319 | gpu_offset += this_length; | |
320 | length -= this_length; | |
321 | } | |
322 | ||
99a03df5 CW |
323 | kunmap(cpu_page); |
324 | kunmap(gpu_page); | |
280b713b EA |
325 | } |
326 | ||
eb01459f EA |
327 | /** |
328 | * This is the fast shmem pread path, which attempts to copy_from_user directly | |
329 | * from the backing pages of the object to the user's address space. On a | |
330 | * fault, it fails so we can fall back to i915_gem_shmem_pwrite_slow(). | |
331 | */ | |
332 | static int | |
05394f39 CW |
333 | i915_gem_shmem_pread_fast(struct drm_device *dev, |
334 | struct drm_i915_gem_object *obj, | |
eb01459f | 335 | struct drm_i915_gem_pread *args, |
05394f39 | 336 | struct drm_file *file) |
eb01459f | 337 | { |
05394f39 | 338 | struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping; |
eb01459f | 339 | ssize_t remain; |
e5281ccd | 340 | loff_t offset; |
eb01459f EA |
341 | char __user *user_data; |
342 | int page_offset, page_length; | |
eb01459f EA |
343 | |
344 | user_data = (char __user *) (uintptr_t) args->data_ptr; | |
345 | remain = args->size; | |
346 | ||
eb01459f EA |
347 | offset = args->offset; |
348 | ||
349 | while (remain > 0) { | |
e5281ccd CW |
350 | struct page *page; |
351 | char *vaddr; | |
352 | int ret; | |
353 | ||
eb01459f EA |
354 | /* Operation in this page |
355 | * | |
eb01459f EA |
356 | * page_offset = offset within page |
357 | * page_length = bytes to copy for this page | |
358 | */ | |
eb01459f EA |
359 | page_offset = offset & (PAGE_SIZE-1); |
360 | page_length = remain; | |
361 | if ((page_offset + remain) > PAGE_SIZE) | |
362 | page_length = PAGE_SIZE - page_offset; | |
363 | ||
e5281ccd CW |
364 | page = read_cache_page_gfp(mapping, offset >> PAGE_SHIFT, |
365 | GFP_HIGHUSER | __GFP_RECLAIMABLE); | |
366 | if (IS_ERR(page)) | |
367 | return PTR_ERR(page); | |
368 | ||
369 | vaddr = kmap_atomic(page); | |
370 | ret = __copy_to_user_inatomic(user_data, | |
371 | vaddr + page_offset, | |
372 | page_length); | |
373 | kunmap_atomic(vaddr); | |
374 | ||
375 | mark_page_accessed(page); | |
376 | page_cache_release(page); | |
377 | if (ret) | |
4f27b75d | 378 | return -EFAULT; |
eb01459f EA |
379 | |
380 | remain -= page_length; | |
381 | user_data += page_length; | |
382 | offset += page_length; | |
383 | } | |
384 | ||
4f27b75d | 385 | return 0; |
eb01459f EA |
386 | } |
387 | ||
388 | /** | |
389 | * This is the fallback shmem pread path, which allocates temporary storage | |
390 | * in kernel space to copy_to_user into outside of the struct_mutex, so we | |
391 | * can copy out of the object's backing pages while holding the struct mutex | |
392 | * and not take page faults. | |
393 | */ | |
394 | static int | |
05394f39 CW |
395 | i915_gem_shmem_pread_slow(struct drm_device *dev, |
396 | struct drm_i915_gem_object *obj, | |
eb01459f | 397 | struct drm_i915_gem_pread *args, |
05394f39 | 398 | struct drm_file *file) |
eb01459f | 399 | { |
05394f39 | 400 | struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping; |
eb01459f EA |
401 | struct mm_struct *mm = current->mm; |
402 | struct page **user_pages; | |
403 | ssize_t remain; | |
404 | loff_t offset, pinned_pages, i; | |
405 | loff_t first_data_page, last_data_page, num_pages; | |
e5281ccd CW |
406 | int shmem_page_offset; |
407 | int data_page_index, data_page_offset; | |
eb01459f EA |
408 | int page_length; |
409 | int ret; | |
410 | uint64_t data_ptr = args->data_ptr; | |
280b713b | 411 | int do_bit17_swizzling; |
eb01459f EA |
412 | |
413 | remain = args->size; | |
414 | ||
415 | /* Pin the user pages containing the data. We can't fault while | |
416 | * holding the struct mutex, yet we want to hold it while | |
417 | * dereferencing the user data. | |
418 | */ | |
419 | first_data_page = data_ptr / PAGE_SIZE; | |
420 | last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE; | |
421 | num_pages = last_data_page - first_data_page + 1; | |
422 | ||
4f27b75d | 423 | user_pages = drm_malloc_ab(num_pages, sizeof(struct page *)); |
eb01459f EA |
424 | if (user_pages == NULL) |
425 | return -ENOMEM; | |
426 | ||
4f27b75d | 427 | mutex_unlock(&dev->struct_mutex); |
eb01459f EA |
428 | down_read(&mm->mmap_sem); |
429 | pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr, | |
e5e9ecde | 430 | num_pages, 1, 0, user_pages, NULL); |
eb01459f | 431 | up_read(&mm->mmap_sem); |
4f27b75d | 432 | mutex_lock(&dev->struct_mutex); |
eb01459f EA |
433 | if (pinned_pages < num_pages) { |
434 | ret = -EFAULT; | |
4f27b75d | 435 | goto out; |
eb01459f EA |
436 | } |
437 | ||
4f27b75d CW |
438 | ret = i915_gem_object_set_cpu_read_domain_range(obj, |
439 | args->offset, | |
440 | args->size); | |
07f73f69 | 441 | if (ret) |
4f27b75d | 442 | goto out; |
eb01459f | 443 | |
4f27b75d | 444 | do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj); |
eb01459f | 445 | |
eb01459f EA |
446 | offset = args->offset; |
447 | ||
448 | while (remain > 0) { | |
e5281ccd CW |
449 | struct page *page; |
450 | ||
eb01459f EA |
451 | /* Operation in this page |
452 | * | |
eb01459f EA |
453 | * shmem_page_offset = offset within page in shmem file |
454 | * data_page_index = page number in get_user_pages return | |
455 | * data_page_offset = offset with data_page_index page. | |
456 | * page_length = bytes to copy for this page | |
457 | */ | |
eb01459f EA |
458 | shmem_page_offset = offset & ~PAGE_MASK; |
459 | data_page_index = data_ptr / PAGE_SIZE - first_data_page; | |
460 | data_page_offset = data_ptr & ~PAGE_MASK; | |
461 | ||
462 | page_length = remain; | |
463 | if ((shmem_page_offset + page_length) > PAGE_SIZE) | |
464 | page_length = PAGE_SIZE - shmem_page_offset; | |
465 | if ((data_page_offset + page_length) > PAGE_SIZE) | |
466 | page_length = PAGE_SIZE - data_page_offset; | |
467 | ||
e5281ccd CW |
468 | page = read_cache_page_gfp(mapping, offset >> PAGE_SHIFT, |
469 | GFP_HIGHUSER | __GFP_RECLAIMABLE); | |
470 | if (IS_ERR(page)) | |
471 | return PTR_ERR(page); | |
472 | ||
280b713b | 473 | if (do_bit17_swizzling) { |
e5281ccd | 474 | slow_shmem_bit17_copy(page, |
280b713b | 475 | shmem_page_offset, |
99a03df5 CW |
476 | user_pages[data_page_index], |
477 | data_page_offset, | |
478 | page_length, | |
479 | 1); | |
480 | } else { | |
481 | slow_shmem_copy(user_pages[data_page_index], | |
482 | data_page_offset, | |
e5281ccd | 483 | page, |
99a03df5 CW |
484 | shmem_page_offset, |
485 | page_length); | |
280b713b | 486 | } |
eb01459f | 487 | |
e5281ccd CW |
488 | mark_page_accessed(page); |
489 | page_cache_release(page); | |
490 | ||
eb01459f EA |
491 | remain -= page_length; |
492 | data_ptr += page_length; | |
493 | offset += page_length; | |
494 | } | |
495 | ||
4f27b75d | 496 | out: |
eb01459f EA |
497 | for (i = 0; i < pinned_pages; i++) { |
498 | SetPageDirty(user_pages[i]); | |
e5281ccd | 499 | mark_page_accessed(user_pages[i]); |
eb01459f EA |
500 | page_cache_release(user_pages[i]); |
501 | } | |
8e7d2b2c | 502 | drm_free_large(user_pages); |
eb01459f EA |
503 | |
504 | return ret; | |
505 | } | |
506 | ||
673a394b EA |
507 | /** |
508 | * Reads data from the object referenced by handle. | |
509 | * | |
510 | * On error, the contents of *data are undefined. | |
511 | */ | |
512 | int | |
513 | i915_gem_pread_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 514 | struct drm_file *file) |
673a394b EA |
515 | { |
516 | struct drm_i915_gem_pread *args = data; | |
05394f39 | 517 | struct drm_i915_gem_object *obj; |
35b62a89 | 518 | int ret = 0; |
673a394b | 519 | |
51311d0a CW |
520 | if (args->size == 0) |
521 | return 0; | |
522 | ||
523 | if (!access_ok(VERIFY_WRITE, | |
524 | (char __user *)(uintptr_t)args->data_ptr, | |
525 | args->size)) | |
526 | return -EFAULT; | |
527 | ||
528 | ret = fault_in_pages_writeable((char __user *)(uintptr_t)args->data_ptr, | |
529 | args->size); | |
530 | if (ret) | |
531 | return -EFAULT; | |
532 | ||
4f27b75d | 533 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 534 | if (ret) |
4f27b75d | 535 | return ret; |
673a394b | 536 | |
05394f39 | 537 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 538 | if (&obj->base == NULL) { |
1d7cfea1 CW |
539 | ret = -ENOENT; |
540 | goto unlock; | |
4f27b75d | 541 | } |
673a394b | 542 | |
7dcd2499 | 543 | /* Bounds check source. */ |
05394f39 CW |
544 | if (args->offset > obj->base.size || |
545 | args->size > obj->base.size - args->offset) { | |
ce9d419d | 546 | ret = -EINVAL; |
35b62a89 | 547 | goto out; |
ce9d419d CW |
548 | } |
549 | ||
db53a302 CW |
550 | trace_i915_gem_object_pread(obj, args->offset, args->size); |
551 | ||
4f27b75d CW |
552 | ret = i915_gem_object_set_cpu_read_domain_range(obj, |
553 | args->offset, | |
554 | args->size); | |
555 | if (ret) | |
e5281ccd | 556 | goto out; |
4f27b75d CW |
557 | |
558 | ret = -EFAULT; | |
559 | if (!i915_gem_object_needs_bit17_swizzle(obj)) | |
05394f39 | 560 | ret = i915_gem_shmem_pread_fast(dev, obj, args, file); |
4f27b75d | 561 | if (ret == -EFAULT) |
05394f39 | 562 | ret = i915_gem_shmem_pread_slow(dev, obj, args, file); |
673a394b | 563 | |
35b62a89 | 564 | out: |
05394f39 | 565 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 566 | unlock: |
4f27b75d | 567 | mutex_unlock(&dev->struct_mutex); |
eb01459f | 568 | return ret; |
673a394b EA |
569 | } |
570 | ||
0839ccb8 KP |
571 | /* This is the fast write path which cannot handle |
572 | * page faults in the source data | |
9b7530cc | 573 | */ |
0839ccb8 KP |
574 | |
575 | static inline int | |
576 | fast_user_write(struct io_mapping *mapping, | |
577 | loff_t page_base, int page_offset, | |
578 | char __user *user_data, | |
579 | int length) | |
9b7530cc | 580 | { |
9b7530cc | 581 | char *vaddr_atomic; |
0839ccb8 | 582 | unsigned long unwritten; |
9b7530cc | 583 | |
3e4d3af5 | 584 | vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base); |
0839ccb8 KP |
585 | unwritten = __copy_from_user_inatomic_nocache(vaddr_atomic + page_offset, |
586 | user_data, length); | |
3e4d3af5 | 587 | io_mapping_unmap_atomic(vaddr_atomic); |
fbd5a26d | 588 | return unwritten; |
0839ccb8 KP |
589 | } |
590 | ||
591 | /* Here's the write path which can sleep for | |
592 | * page faults | |
593 | */ | |
594 | ||
ab34c226 | 595 | static inline void |
3de09aa3 EA |
596 | slow_kernel_write(struct io_mapping *mapping, |
597 | loff_t gtt_base, int gtt_offset, | |
598 | struct page *user_page, int user_offset, | |
599 | int length) | |
0839ccb8 | 600 | { |
ab34c226 CW |
601 | char __iomem *dst_vaddr; |
602 | char *src_vaddr; | |
0839ccb8 | 603 | |
ab34c226 CW |
604 | dst_vaddr = io_mapping_map_wc(mapping, gtt_base); |
605 | src_vaddr = kmap(user_page); | |
606 | ||
607 | memcpy_toio(dst_vaddr + gtt_offset, | |
608 | src_vaddr + user_offset, | |
609 | length); | |
610 | ||
611 | kunmap(user_page); | |
612 | io_mapping_unmap(dst_vaddr); | |
9b7530cc LT |
613 | } |
614 | ||
3de09aa3 EA |
615 | /** |
616 | * This is the fast pwrite path, where we copy the data directly from the | |
617 | * user into the GTT, uncached. | |
618 | */ | |
673a394b | 619 | static int |
05394f39 CW |
620 | i915_gem_gtt_pwrite_fast(struct drm_device *dev, |
621 | struct drm_i915_gem_object *obj, | |
3de09aa3 | 622 | struct drm_i915_gem_pwrite *args, |
05394f39 | 623 | struct drm_file *file) |
673a394b | 624 | { |
0839ccb8 | 625 | drm_i915_private_t *dev_priv = dev->dev_private; |
673a394b | 626 | ssize_t remain; |
0839ccb8 | 627 | loff_t offset, page_base; |
673a394b | 628 | char __user *user_data; |
0839ccb8 | 629 | int page_offset, page_length; |
673a394b EA |
630 | |
631 | user_data = (char __user *) (uintptr_t) args->data_ptr; | |
632 | remain = args->size; | |
673a394b | 633 | |
05394f39 | 634 | offset = obj->gtt_offset + args->offset; |
673a394b EA |
635 | |
636 | while (remain > 0) { | |
637 | /* Operation in this page | |
638 | * | |
0839ccb8 KP |
639 | * page_base = page offset within aperture |
640 | * page_offset = offset within page | |
641 | * page_length = bytes to copy for this page | |
673a394b | 642 | */ |
0839ccb8 KP |
643 | page_base = (offset & ~(PAGE_SIZE-1)); |
644 | page_offset = offset & (PAGE_SIZE-1); | |
645 | page_length = remain; | |
646 | if ((page_offset + remain) > PAGE_SIZE) | |
647 | page_length = PAGE_SIZE - page_offset; | |
648 | ||
0839ccb8 | 649 | /* If we get a fault while copying data, then (presumably) our |
3de09aa3 EA |
650 | * source page isn't available. Return the error and we'll |
651 | * retry in the slow path. | |
0839ccb8 | 652 | */ |
fbd5a26d CW |
653 | if (fast_user_write(dev_priv->mm.gtt_mapping, page_base, |
654 | page_offset, user_data, page_length)) | |
655 | ||
656 | return -EFAULT; | |
673a394b | 657 | |
0839ccb8 KP |
658 | remain -= page_length; |
659 | user_data += page_length; | |
660 | offset += page_length; | |
673a394b | 661 | } |
673a394b | 662 | |
fbd5a26d | 663 | return 0; |
673a394b EA |
664 | } |
665 | ||
3de09aa3 EA |
666 | /** |
667 | * This is the fallback GTT pwrite path, which uses get_user_pages to pin | |
668 | * the memory and maps it using kmap_atomic for copying. | |
669 | * | |
670 | * This code resulted in x11perf -rgb10text consuming about 10% more CPU | |
671 | * than using i915_gem_gtt_pwrite_fast on a G45 (32-bit). | |
672 | */ | |
3043c60c | 673 | static int |
05394f39 CW |
674 | i915_gem_gtt_pwrite_slow(struct drm_device *dev, |
675 | struct drm_i915_gem_object *obj, | |
3de09aa3 | 676 | struct drm_i915_gem_pwrite *args, |
05394f39 | 677 | struct drm_file *file) |
673a394b | 678 | { |
3de09aa3 EA |
679 | drm_i915_private_t *dev_priv = dev->dev_private; |
680 | ssize_t remain; | |
681 | loff_t gtt_page_base, offset; | |
682 | loff_t first_data_page, last_data_page, num_pages; | |
683 | loff_t pinned_pages, i; | |
684 | struct page **user_pages; | |
685 | struct mm_struct *mm = current->mm; | |
686 | int gtt_page_offset, data_page_offset, data_page_index, page_length; | |
673a394b | 687 | int ret; |
3de09aa3 EA |
688 | uint64_t data_ptr = args->data_ptr; |
689 | ||
690 | remain = args->size; | |
691 | ||
692 | /* Pin the user pages containing the data. We can't fault while | |
693 | * holding the struct mutex, and all of the pwrite implementations | |
694 | * want to hold it while dereferencing the user data. | |
695 | */ | |
696 | first_data_page = data_ptr / PAGE_SIZE; | |
697 | last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE; | |
698 | num_pages = last_data_page - first_data_page + 1; | |
699 | ||
fbd5a26d | 700 | user_pages = drm_malloc_ab(num_pages, sizeof(struct page *)); |
3de09aa3 EA |
701 | if (user_pages == NULL) |
702 | return -ENOMEM; | |
703 | ||
fbd5a26d | 704 | mutex_unlock(&dev->struct_mutex); |
3de09aa3 EA |
705 | down_read(&mm->mmap_sem); |
706 | pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr, | |
707 | num_pages, 0, 0, user_pages, NULL); | |
708 | up_read(&mm->mmap_sem); | |
fbd5a26d | 709 | mutex_lock(&dev->struct_mutex); |
3de09aa3 EA |
710 | if (pinned_pages < num_pages) { |
711 | ret = -EFAULT; | |
712 | goto out_unpin_pages; | |
713 | } | |
673a394b | 714 | |
d9e86c0e CW |
715 | ret = i915_gem_object_set_to_gtt_domain(obj, true); |
716 | if (ret) | |
717 | goto out_unpin_pages; | |
718 | ||
719 | ret = i915_gem_object_put_fence(obj); | |
3de09aa3 | 720 | if (ret) |
fbd5a26d | 721 | goto out_unpin_pages; |
3de09aa3 | 722 | |
05394f39 | 723 | offset = obj->gtt_offset + args->offset; |
3de09aa3 EA |
724 | |
725 | while (remain > 0) { | |
726 | /* Operation in this page | |
727 | * | |
728 | * gtt_page_base = page offset within aperture | |
729 | * gtt_page_offset = offset within page in aperture | |
730 | * data_page_index = page number in get_user_pages return | |
731 | * data_page_offset = offset with data_page_index page. | |
732 | * page_length = bytes to copy for this page | |
733 | */ | |
734 | gtt_page_base = offset & PAGE_MASK; | |
735 | gtt_page_offset = offset & ~PAGE_MASK; | |
736 | data_page_index = data_ptr / PAGE_SIZE - first_data_page; | |
737 | data_page_offset = data_ptr & ~PAGE_MASK; | |
738 | ||
739 | page_length = remain; | |
740 | if ((gtt_page_offset + page_length) > PAGE_SIZE) | |
741 | page_length = PAGE_SIZE - gtt_page_offset; | |
742 | if ((data_page_offset + page_length) > PAGE_SIZE) | |
743 | page_length = PAGE_SIZE - data_page_offset; | |
744 | ||
ab34c226 CW |
745 | slow_kernel_write(dev_priv->mm.gtt_mapping, |
746 | gtt_page_base, gtt_page_offset, | |
747 | user_pages[data_page_index], | |
748 | data_page_offset, | |
749 | page_length); | |
3de09aa3 EA |
750 | |
751 | remain -= page_length; | |
752 | offset += page_length; | |
753 | data_ptr += page_length; | |
754 | } | |
755 | ||
3de09aa3 EA |
756 | out_unpin_pages: |
757 | for (i = 0; i < pinned_pages; i++) | |
758 | page_cache_release(user_pages[i]); | |
8e7d2b2c | 759 | drm_free_large(user_pages); |
3de09aa3 EA |
760 | |
761 | return ret; | |
762 | } | |
763 | ||
40123c1f EA |
764 | /** |
765 | * This is the fast shmem pwrite path, which attempts to directly | |
766 | * copy_from_user into the kmapped pages backing the object. | |
767 | */ | |
3043c60c | 768 | static int |
05394f39 CW |
769 | i915_gem_shmem_pwrite_fast(struct drm_device *dev, |
770 | struct drm_i915_gem_object *obj, | |
40123c1f | 771 | struct drm_i915_gem_pwrite *args, |
05394f39 | 772 | struct drm_file *file) |
673a394b | 773 | { |
05394f39 | 774 | struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping; |
40123c1f | 775 | ssize_t remain; |
e5281ccd | 776 | loff_t offset; |
40123c1f EA |
777 | char __user *user_data; |
778 | int page_offset, page_length; | |
40123c1f EA |
779 | |
780 | user_data = (char __user *) (uintptr_t) args->data_ptr; | |
781 | remain = args->size; | |
673a394b | 782 | |
40123c1f | 783 | offset = args->offset; |
05394f39 | 784 | obj->dirty = 1; |
40123c1f EA |
785 | |
786 | while (remain > 0) { | |
e5281ccd CW |
787 | struct page *page; |
788 | char *vaddr; | |
789 | int ret; | |
790 | ||
40123c1f EA |
791 | /* Operation in this page |
792 | * | |
40123c1f EA |
793 | * page_offset = offset within page |
794 | * page_length = bytes to copy for this page | |
795 | */ | |
40123c1f EA |
796 | page_offset = offset & (PAGE_SIZE-1); |
797 | page_length = remain; | |
798 | if ((page_offset + remain) > PAGE_SIZE) | |
799 | page_length = PAGE_SIZE - page_offset; | |
800 | ||
e5281ccd CW |
801 | page = read_cache_page_gfp(mapping, offset >> PAGE_SHIFT, |
802 | GFP_HIGHUSER | __GFP_RECLAIMABLE); | |
803 | if (IS_ERR(page)) | |
804 | return PTR_ERR(page); | |
805 | ||
806 | vaddr = kmap_atomic(page, KM_USER0); | |
807 | ret = __copy_from_user_inatomic(vaddr + page_offset, | |
808 | user_data, | |
809 | page_length); | |
810 | kunmap_atomic(vaddr, KM_USER0); | |
811 | ||
812 | set_page_dirty(page); | |
813 | mark_page_accessed(page); | |
814 | page_cache_release(page); | |
815 | ||
816 | /* If we get a fault while copying data, then (presumably) our | |
817 | * source page isn't available. Return the error and we'll | |
818 | * retry in the slow path. | |
819 | */ | |
820 | if (ret) | |
fbd5a26d | 821 | return -EFAULT; |
40123c1f EA |
822 | |
823 | remain -= page_length; | |
824 | user_data += page_length; | |
825 | offset += page_length; | |
826 | } | |
827 | ||
fbd5a26d | 828 | return 0; |
40123c1f EA |
829 | } |
830 | ||
831 | /** | |
832 | * This is the fallback shmem pwrite path, which uses get_user_pages to pin | |
833 | * the memory and maps it using kmap_atomic for copying. | |
834 | * | |
835 | * This avoids taking mmap_sem for faulting on the user's address while the | |
836 | * struct_mutex is held. | |
837 | */ | |
838 | static int | |
05394f39 CW |
839 | i915_gem_shmem_pwrite_slow(struct drm_device *dev, |
840 | struct drm_i915_gem_object *obj, | |
40123c1f | 841 | struct drm_i915_gem_pwrite *args, |
05394f39 | 842 | struct drm_file *file) |
40123c1f | 843 | { |
05394f39 | 844 | struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping; |
40123c1f EA |
845 | struct mm_struct *mm = current->mm; |
846 | struct page **user_pages; | |
847 | ssize_t remain; | |
848 | loff_t offset, pinned_pages, i; | |
849 | loff_t first_data_page, last_data_page, num_pages; | |
e5281ccd | 850 | int shmem_page_offset; |
40123c1f EA |
851 | int data_page_index, data_page_offset; |
852 | int page_length; | |
853 | int ret; | |
854 | uint64_t data_ptr = args->data_ptr; | |
280b713b | 855 | int do_bit17_swizzling; |
40123c1f EA |
856 | |
857 | remain = args->size; | |
858 | ||
859 | /* Pin the user pages containing the data. We can't fault while | |
860 | * holding the struct mutex, and all of the pwrite implementations | |
861 | * want to hold it while dereferencing the user data. | |
862 | */ | |
863 | first_data_page = data_ptr / PAGE_SIZE; | |
864 | last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE; | |
865 | num_pages = last_data_page - first_data_page + 1; | |
866 | ||
4f27b75d | 867 | user_pages = drm_malloc_ab(num_pages, sizeof(struct page *)); |
40123c1f EA |
868 | if (user_pages == NULL) |
869 | return -ENOMEM; | |
870 | ||
fbd5a26d | 871 | mutex_unlock(&dev->struct_mutex); |
40123c1f EA |
872 | down_read(&mm->mmap_sem); |
873 | pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr, | |
874 | num_pages, 0, 0, user_pages, NULL); | |
875 | up_read(&mm->mmap_sem); | |
fbd5a26d | 876 | mutex_lock(&dev->struct_mutex); |
40123c1f EA |
877 | if (pinned_pages < num_pages) { |
878 | ret = -EFAULT; | |
fbd5a26d | 879 | goto out; |
673a394b EA |
880 | } |
881 | ||
fbd5a26d | 882 | ret = i915_gem_object_set_to_cpu_domain(obj, 1); |
07f73f69 | 883 | if (ret) |
fbd5a26d | 884 | goto out; |
40123c1f | 885 | |
fbd5a26d | 886 | do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj); |
40123c1f | 887 | |
673a394b | 888 | offset = args->offset; |
05394f39 | 889 | obj->dirty = 1; |
673a394b | 890 | |
40123c1f | 891 | while (remain > 0) { |
e5281ccd CW |
892 | struct page *page; |
893 | ||
40123c1f EA |
894 | /* Operation in this page |
895 | * | |
40123c1f EA |
896 | * shmem_page_offset = offset within page in shmem file |
897 | * data_page_index = page number in get_user_pages return | |
898 | * data_page_offset = offset with data_page_index page. | |
899 | * page_length = bytes to copy for this page | |
900 | */ | |
40123c1f EA |
901 | shmem_page_offset = offset & ~PAGE_MASK; |
902 | data_page_index = data_ptr / PAGE_SIZE - first_data_page; | |
903 | data_page_offset = data_ptr & ~PAGE_MASK; | |
904 | ||
905 | page_length = remain; | |
906 | if ((shmem_page_offset + page_length) > PAGE_SIZE) | |
907 | page_length = PAGE_SIZE - shmem_page_offset; | |
908 | if ((data_page_offset + page_length) > PAGE_SIZE) | |
909 | page_length = PAGE_SIZE - data_page_offset; | |
910 | ||
e5281ccd CW |
911 | page = read_cache_page_gfp(mapping, offset >> PAGE_SHIFT, |
912 | GFP_HIGHUSER | __GFP_RECLAIMABLE); | |
913 | if (IS_ERR(page)) { | |
914 | ret = PTR_ERR(page); | |
915 | goto out; | |
916 | } | |
917 | ||
280b713b | 918 | if (do_bit17_swizzling) { |
e5281ccd | 919 | slow_shmem_bit17_copy(page, |
280b713b EA |
920 | shmem_page_offset, |
921 | user_pages[data_page_index], | |
922 | data_page_offset, | |
99a03df5 CW |
923 | page_length, |
924 | 0); | |
925 | } else { | |
e5281ccd | 926 | slow_shmem_copy(page, |
99a03df5 CW |
927 | shmem_page_offset, |
928 | user_pages[data_page_index], | |
929 | data_page_offset, | |
930 | page_length); | |
280b713b | 931 | } |
40123c1f | 932 | |
e5281ccd CW |
933 | set_page_dirty(page); |
934 | mark_page_accessed(page); | |
935 | page_cache_release(page); | |
936 | ||
40123c1f EA |
937 | remain -= page_length; |
938 | data_ptr += page_length; | |
939 | offset += page_length; | |
673a394b EA |
940 | } |
941 | ||
fbd5a26d | 942 | out: |
40123c1f EA |
943 | for (i = 0; i < pinned_pages; i++) |
944 | page_cache_release(user_pages[i]); | |
8e7d2b2c | 945 | drm_free_large(user_pages); |
673a394b | 946 | |
40123c1f | 947 | return ret; |
673a394b EA |
948 | } |
949 | ||
950 | /** | |
951 | * Writes data to the object referenced by handle. | |
952 | * | |
953 | * On error, the contents of the buffer that were to be modified are undefined. | |
954 | */ | |
955 | int | |
956 | i915_gem_pwrite_ioctl(struct drm_device *dev, void *data, | |
fbd5a26d | 957 | struct drm_file *file) |
673a394b EA |
958 | { |
959 | struct drm_i915_gem_pwrite *args = data; | |
05394f39 | 960 | struct drm_i915_gem_object *obj; |
51311d0a CW |
961 | int ret; |
962 | ||
963 | if (args->size == 0) | |
964 | return 0; | |
965 | ||
966 | if (!access_ok(VERIFY_READ, | |
967 | (char __user *)(uintptr_t)args->data_ptr, | |
968 | args->size)) | |
969 | return -EFAULT; | |
970 | ||
971 | ret = fault_in_pages_readable((char __user *)(uintptr_t)args->data_ptr, | |
972 | args->size); | |
973 | if (ret) | |
974 | return -EFAULT; | |
673a394b | 975 | |
fbd5a26d | 976 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 977 | if (ret) |
fbd5a26d | 978 | return ret; |
1d7cfea1 | 979 | |
05394f39 | 980 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 981 | if (&obj->base == NULL) { |
1d7cfea1 CW |
982 | ret = -ENOENT; |
983 | goto unlock; | |
fbd5a26d | 984 | } |
673a394b | 985 | |
7dcd2499 | 986 | /* Bounds check destination. */ |
05394f39 CW |
987 | if (args->offset > obj->base.size || |
988 | args->size > obj->base.size - args->offset) { | |
ce9d419d | 989 | ret = -EINVAL; |
35b62a89 | 990 | goto out; |
ce9d419d CW |
991 | } |
992 | ||
db53a302 CW |
993 | trace_i915_gem_object_pwrite(obj, args->offset, args->size); |
994 | ||
673a394b EA |
995 | /* We can only do the GTT pwrite on untiled buffers, as otherwise |
996 | * it would end up going through the fenced access, and we'll get | |
997 | * different detiling behavior between reading and writing. | |
998 | * pread/pwrite currently are reading and writing from the CPU | |
999 | * perspective, requiring manual detiling by the client. | |
1000 | */ | |
05394f39 | 1001 | if (obj->phys_obj) |
fbd5a26d | 1002 | ret = i915_gem_phys_pwrite(dev, obj, args, file); |
d9e86c0e | 1003 | else if (obj->gtt_space && |
05394f39 | 1004 | obj->base.write_domain != I915_GEM_DOMAIN_CPU) { |
75e9e915 | 1005 | ret = i915_gem_object_pin(obj, 0, true); |
fbd5a26d CW |
1006 | if (ret) |
1007 | goto out; | |
1008 | ||
d9e86c0e CW |
1009 | ret = i915_gem_object_set_to_gtt_domain(obj, true); |
1010 | if (ret) | |
1011 | goto out_unpin; | |
1012 | ||
1013 | ret = i915_gem_object_put_fence(obj); | |
fbd5a26d CW |
1014 | if (ret) |
1015 | goto out_unpin; | |
1016 | ||
1017 | ret = i915_gem_gtt_pwrite_fast(dev, obj, args, file); | |
1018 | if (ret == -EFAULT) | |
1019 | ret = i915_gem_gtt_pwrite_slow(dev, obj, args, file); | |
1020 | ||
1021 | out_unpin: | |
1022 | i915_gem_object_unpin(obj); | |
40123c1f | 1023 | } else { |
fbd5a26d CW |
1024 | ret = i915_gem_object_set_to_cpu_domain(obj, 1); |
1025 | if (ret) | |
e5281ccd | 1026 | goto out; |
673a394b | 1027 | |
fbd5a26d CW |
1028 | ret = -EFAULT; |
1029 | if (!i915_gem_object_needs_bit17_swizzle(obj)) | |
1030 | ret = i915_gem_shmem_pwrite_fast(dev, obj, args, file); | |
1031 | if (ret == -EFAULT) | |
1032 | ret = i915_gem_shmem_pwrite_slow(dev, obj, args, file); | |
fbd5a26d | 1033 | } |
673a394b | 1034 | |
35b62a89 | 1035 | out: |
05394f39 | 1036 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 1037 | unlock: |
fbd5a26d | 1038 | mutex_unlock(&dev->struct_mutex); |
673a394b EA |
1039 | return ret; |
1040 | } | |
1041 | ||
1042 | /** | |
2ef7eeaa EA |
1043 | * Called when user space prepares to use an object with the CPU, either |
1044 | * through the mmap ioctl's mapping or a GTT mapping. | |
673a394b EA |
1045 | */ |
1046 | int | |
1047 | i915_gem_set_domain_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 1048 | struct drm_file *file) |
673a394b EA |
1049 | { |
1050 | struct drm_i915_gem_set_domain *args = data; | |
05394f39 | 1051 | struct drm_i915_gem_object *obj; |
2ef7eeaa EA |
1052 | uint32_t read_domains = args->read_domains; |
1053 | uint32_t write_domain = args->write_domain; | |
673a394b EA |
1054 | int ret; |
1055 | ||
1056 | if (!(dev->driver->driver_features & DRIVER_GEM)) | |
1057 | return -ENODEV; | |
1058 | ||
2ef7eeaa | 1059 | /* Only handle setting domains to types used by the CPU. */ |
21d509e3 | 1060 | if (write_domain & I915_GEM_GPU_DOMAINS) |
2ef7eeaa EA |
1061 | return -EINVAL; |
1062 | ||
21d509e3 | 1063 | if (read_domains & I915_GEM_GPU_DOMAINS) |
2ef7eeaa EA |
1064 | return -EINVAL; |
1065 | ||
1066 | /* Having something in the write domain implies it's in the read | |
1067 | * domain, and only that read domain. Enforce that in the request. | |
1068 | */ | |
1069 | if (write_domain != 0 && read_domains != write_domain) | |
1070 | return -EINVAL; | |
1071 | ||
76c1dec1 | 1072 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 1073 | if (ret) |
76c1dec1 | 1074 | return ret; |
1d7cfea1 | 1075 | |
05394f39 | 1076 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 1077 | if (&obj->base == NULL) { |
1d7cfea1 CW |
1078 | ret = -ENOENT; |
1079 | goto unlock; | |
76c1dec1 | 1080 | } |
673a394b | 1081 | |
2ef7eeaa EA |
1082 | if (read_domains & I915_GEM_DOMAIN_GTT) { |
1083 | ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0); | |
02354392 EA |
1084 | |
1085 | /* Silently promote "you're not bound, there was nothing to do" | |
1086 | * to success, since the client was just asking us to | |
1087 | * make sure everything was done. | |
1088 | */ | |
1089 | if (ret == -EINVAL) | |
1090 | ret = 0; | |
2ef7eeaa | 1091 | } else { |
e47c68e9 | 1092 | ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0); |
2ef7eeaa EA |
1093 | } |
1094 | ||
05394f39 | 1095 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 1096 | unlock: |
673a394b EA |
1097 | mutex_unlock(&dev->struct_mutex); |
1098 | return ret; | |
1099 | } | |
1100 | ||
1101 | /** | |
1102 | * Called when user space has done writes to this buffer | |
1103 | */ | |
1104 | int | |
1105 | i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 1106 | struct drm_file *file) |
673a394b EA |
1107 | { |
1108 | struct drm_i915_gem_sw_finish *args = data; | |
05394f39 | 1109 | struct drm_i915_gem_object *obj; |
673a394b EA |
1110 | int ret = 0; |
1111 | ||
1112 | if (!(dev->driver->driver_features & DRIVER_GEM)) | |
1113 | return -ENODEV; | |
1114 | ||
76c1dec1 | 1115 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 1116 | if (ret) |
76c1dec1 | 1117 | return ret; |
1d7cfea1 | 1118 | |
05394f39 | 1119 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 1120 | if (&obj->base == NULL) { |
1d7cfea1 CW |
1121 | ret = -ENOENT; |
1122 | goto unlock; | |
673a394b EA |
1123 | } |
1124 | ||
673a394b | 1125 | /* Pinned buffers may be scanout, so flush the cache */ |
05394f39 | 1126 | if (obj->pin_count) |
e47c68e9 EA |
1127 | i915_gem_object_flush_cpu_write_domain(obj); |
1128 | ||
05394f39 | 1129 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 1130 | unlock: |
673a394b EA |
1131 | mutex_unlock(&dev->struct_mutex); |
1132 | return ret; | |
1133 | } | |
1134 | ||
1135 | /** | |
1136 | * Maps the contents of an object, returning the address it is mapped | |
1137 | * into. | |
1138 | * | |
1139 | * While the mapping holds a reference on the contents of the object, it doesn't | |
1140 | * imply a ref on the object itself. | |
1141 | */ | |
1142 | int | |
1143 | i915_gem_mmap_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 1144 | struct drm_file *file) |
673a394b | 1145 | { |
da761a6e | 1146 | struct drm_i915_private *dev_priv = dev->dev_private; |
673a394b EA |
1147 | struct drm_i915_gem_mmap *args = data; |
1148 | struct drm_gem_object *obj; | |
673a394b EA |
1149 | unsigned long addr; |
1150 | ||
1151 | if (!(dev->driver->driver_features & DRIVER_GEM)) | |
1152 | return -ENODEV; | |
1153 | ||
05394f39 | 1154 | obj = drm_gem_object_lookup(dev, file, args->handle); |
673a394b | 1155 | if (obj == NULL) |
bf79cb91 | 1156 | return -ENOENT; |
673a394b | 1157 | |
da761a6e CW |
1158 | if (obj->size > dev_priv->mm.gtt_mappable_end) { |
1159 | drm_gem_object_unreference_unlocked(obj); | |
1160 | return -E2BIG; | |
1161 | } | |
1162 | ||
673a394b EA |
1163 | down_write(¤t->mm->mmap_sem); |
1164 | addr = do_mmap(obj->filp, 0, args->size, | |
1165 | PROT_READ | PROT_WRITE, MAP_SHARED, | |
1166 | args->offset); | |
1167 | up_write(¤t->mm->mmap_sem); | |
bc9025bd | 1168 | drm_gem_object_unreference_unlocked(obj); |
673a394b EA |
1169 | if (IS_ERR((void *)addr)) |
1170 | return addr; | |
1171 | ||
1172 | args->addr_ptr = (uint64_t) addr; | |
1173 | ||
1174 | return 0; | |
1175 | } | |
1176 | ||
de151cf6 JB |
1177 | /** |
1178 | * i915_gem_fault - fault a page into the GTT | |
1179 | * vma: VMA in question | |
1180 | * vmf: fault info | |
1181 | * | |
1182 | * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped | |
1183 | * from userspace. The fault handler takes care of binding the object to | |
1184 | * the GTT (if needed), allocating and programming a fence register (again, | |
1185 | * only if needed based on whether the old reg is still valid or the object | |
1186 | * is tiled) and inserting a new PTE into the faulting process. | |
1187 | * | |
1188 | * Note that the faulting process may involve evicting existing objects | |
1189 | * from the GTT and/or fence registers to make room. So performance may | |
1190 | * suffer if the GTT working set is large or there are few fence registers | |
1191 | * left. | |
1192 | */ | |
1193 | int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf) | |
1194 | { | |
05394f39 CW |
1195 | struct drm_i915_gem_object *obj = to_intel_bo(vma->vm_private_data); |
1196 | struct drm_device *dev = obj->base.dev; | |
7d1c4804 | 1197 | drm_i915_private_t *dev_priv = dev->dev_private; |
de151cf6 JB |
1198 | pgoff_t page_offset; |
1199 | unsigned long pfn; | |
1200 | int ret = 0; | |
0f973f27 | 1201 | bool write = !!(vmf->flags & FAULT_FLAG_WRITE); |
de151cf6 JB |
1202 | |
1203 | /* We don't use vmf->pgoff since that has the fake offset */ | |
1204 | page_offset = ((unsigned long)vmf->virtual_address - vma->vm_start) >> | |
1205 | PAGE_SHIFT; | |
1206 | ||
d9bc7e9f CW |
1207 | ret = i915_mutex_lock_interruptible(dev); |
1208 | if (ret) | |
1209 | goto out; | |
a00b10c3 | 1210 | |
db53a302 CW |
1211 | trace_i915_gem_object_fault(obj, page_offset, true, write); |
1212 | ||
d9bc7e9f | 1213 | /* Now bind it into the GTT if needed */ |
919926ae CW |
1214 | if (!obj->map_and_fenceable) { |
1215 | ret = i915_gem_object_unbind(obj); | |
1216 | if (ret) | |
1217 | goto unlock; | |
a00b10c3 | 1218 | } |
05394f39 | 1219 | if (!obj->gtt_space) { |
75e9e915 | 1220 | ret = i915_gem_object_bind_to_gtt(obj, 0, true); |
c715089f CW |
1221 | if (ret) |
1222 | goto unlock; | |
de151cf6 JB |
1223 | } |
1224 | ||
4a684a41 CW |
1225 | ret = i915_gem_object_set_to_gtt_domain(obj, write); |
1226 | if (ret) | |
1227 | goto unlock; | |
1228 | ||
d9e86c0e CW |
1229 | if (obj->tiling_mode == I915_TILING_NONE) |
1230 | ret = i915_gem_object_put_fence(obj); | |
1231 | else | |
ce453d81 | 1232 | ret = i915_gem_object_get_fence(obj, NULL); |
d9e86c0e CW |
1233 | if (ret) |
1234 | goto unlock; | |
de151cf6 | 1235 | |
05394f39 CW |
1236 | if (i915_gem_object_is_inactive(obj)) |
1237 | list_move_tail(&obj->mm_list, &dev_priv->mm.inactive_list); | |
7d1c4804 | 1238 | |
6299f992 CW |
1239 | obj->fault_mappable = true; |
1240 | ||
05394f39 | 1241 | pfn = ((dev->agp->base + obj->gtt_offset) >> PAGE_SHIFT) + |
de151cf6 JB |
1242 | page_offset; |
1243 | ||
1244 | /* Finally, remap it using the new GTT offset */ | |
1245 | ret = vm_insert_pfn(vma, (unsigned long)vmf->virtual_address, pfn); | |
c715089f | 1246 | unlock: |
de151cf6 | 1247 | mutex_unlock(&dev->struct_mutex); |
d9bc7e9f | 1248 | out: |
de151cf6 | 1249 | switch (ret) { |
d9bc7e9f | 1250 | case -EIO: |
045e769a | 1251 | case -EAGAIN: |
d9bc7e9f CW |
1252 | /* Give the error handler a chance to run and move the |
1253 | * objects off the GPU active list. Next time we service the | |
1254 | * fault, we should be able to transition the page into the | |
1255 | * GTT without touching the GPU (and so avoid further | |
1256 | * EIO/EGAIN). If the GPU is wedged, then there is no issue | |
1257 | * with coherency, just lost writes. | |
1258 | */ | |
045e769a | 1259 | set_need_resched(); |
c715089f CW |
1260 | case 0: |
1261 | case -ERESTARTSYS: | |
bed636ab | 1262 | case -EINTR: |
c715089f | 1263 | return VM_FAULT_NOPAGE; |
de151cf6 | 1264 | case -ENOMEM: |
de151cf6 | 1265 | return VM_FAULT_OOM; |
de151cf6 | 1266 | default: |
c715089f | 1267 | return VM_FAULT_SIGBUS; |
de151cf6 JB |
1268 | } |
1269 | } | |
1270 | ||
1271 | /** | |
1272 | * i915_gem_create_mmap_offset - create a fake mmap offset for an object | |
1273 | * @obj: obj in question | |
1274 | * | |
1275 | * GEM memory mapping works by handing back to userspace a fake mmap offset | |
1276 | * it can use in a subsequent mmap(2) call. The DRM core code then looks | |
1277 | * up the object based on the offset and sets up the various memory mapping | |
1278 | * structures. | |
1279 | * | |
1280 | * This routine allocates and attaches a fake offset for @obj. | |
1281 | */ | |
1282 | static int | |
05394f39 | 1283 | i915_gem_create_mmap_offset(struct drm_i915_gem_object *obj) |
de151cf6 | 1284 | { |
05394f39 | 1285 | struct drm_device *dev = obj->base.dev; |
de151cf6 | 1286 | struct drm_gem_mm *mm = dev->mm_private; |
de151cf6 | 1287 | struct drm_map_list *list; |
f77d390c | 1288 | struct drm_local_map *map; |
de151cf6 JB |
1289 | int ret = 0; |
1290 | ||
1291 | /* Set the object up for mmap'ing */ | |
05394f39 | 1292 | list = &obj->base.map_list; |
9a298b2a | 1293 | list->map = kzalloc(sizeof(struct drm_map_list), GFP_KERNEL); |
de151cf6 JB |
1294 | if (!list->map) |
1295 | return -ENOMEM; | |
1296 | ||
1297 | map = list->map; | |
1298 | map->type = _DRM_GEM; | |
05394f39 | 1299 | map->size = obj->base.size; |
de151cf6 JB |
1300 | map->handle = obj; |
1301 | ||
1302 | /* Get a DRM GEM mmap offset allocated... */ | |
1303 | list->file_offset_node = drm_mm_search_free(&mm->offset_manager, | |
05394f39 CW |
1304 | obj->base.size / PAGE_SIZE, |
1305 | 0, 0); | |
de151cf6 | 1306 | if (!list->file_offset_node) { |
05394f39 CW |
1307 | DRM_ERROR("failed to allocate offset for bo %d\n", |
1308 | obj->base.name); | |
9e0ae534 | 1309 | ret = -ENOSPC; |
de151cf6 JB |
1310 | goto out_free_list; |
1311 | } | |
1312 | ||
1313 | list->file_offset_node = drm_mm_get_block(list->file_offset_node, | |
05394f39 CW |
1314 | obj->base.size / PAGE_SIZE, |
1315 | 0); | |
de151cf6 JB |
1316 | if (!list->file_offset_node) { |
1317 | ret = -ENOMEM; | |
1318 | goto out_free_list; | |
1319 | } | |
1320 | ||
1321 | list->hash.key = list->file_offset_node->start; | |
9e0ae534 CW |
1322 | ret = drm_ht_insert_item(&mm->offset_hash, &list->hash); |
1323 | if (ret) { | |
de151cf6 JB |
1324 | DRM_ERROR("failed to add to map hash\n"); |
1325 | goto out_free_mm; | |
1326 | } | |
1327 | ||
de151cf6 JB |
1328 | return 0; |
1329 | ||
1330 | out_free_mm: | |
1331 | drm_mm_put_block(list->file_offset_node); | |
1332 | out_free_list: | |
9a298b2a | 1333 | kfree(list->map); |
39a01d1f | 1334 | list->map = NULL; |
de151cf6 JB |
1335 | |
1336 | return ret; | |
1337 | } | |
1338 | ||
901782b2 CW |
1339 | /** |
1340 | * i915_gem_release_mmap - remove physical page mappings | |
1341 | * @obj: obj in question | |
1342 | * | |
af901ca1 | 1343 | * Preserve the reservation of the mmapping with the DRM core code, but |
901782b2 CW |
1344 | * relinquish ownership of the pages back to the system. |
1345 | * | |
1346 | * It is vital that we remove the page mapping if we have mapped a tiled | |
1347 | * object through the GTT and then lose the fence register due to | |
1348 | * resource pressure. Similarly if the object has been moved out of the | |
1349 | * aperture, than pages mapped into userspace must be revoked. Removing the | |
1350 | * mapping will then trigger a page fault on the next user access, allowing | |
1351 | * fixup by i915_gem_fault(). | |
1352 | */ | |
d05ca301 | 1353 | void |
05394f39 | 1354 | i915_gem_release_mmap(struct drm_i915_gem_object *obj) |
901782b2 | 1355 | { |
6299f992 CW |
1356 | if (!obj->fault_mappable) |
1357 | return; | |
901782b2 | 1358 | |
f6e47884 CW |
1359 | if (obj->base.dev->dev_mapping) |
1360 | unmap_mapping_range(obj->base.dev->dev_mapping, | |
1361 | (loff_t)obj->base.map_list.hash.key<<PAGE_SHIFT, | |
1362 | obj->base.size, 1); | |
fb7d516a | 1363 | |
6299f992 | 1364 | obj->fault_mappable = false; |
901782b2 CW |
1365 | } |
1366 | ||
ab00b3e5 | 1367 | static void |
05394f39 | 1368 | i915_gem_free_mmap_offset(struct drm_i915_gem_object *obj) |
ab00b3e5 | 1369 | { |
05394f39 | 1370 | struct drm_device *dev = obj->base.dev; |
ab00b3e5 | 1371 | struct drm_gem_mm *mm = dev->mm_private; |
05394f39 | 1372 | struct drm_map_list *list = &obj->base.map_list; |
ab00b3e5 | 1373 | |
ab00b3e5 | 1374 | drm_ht_remove_item(&mm->offset_hash, &list->hash); |
39a01d1f CW |
1375 | drm_mm_put_block(list->file_offset_node); |
1376 | kfree(list->map); | |
1377 | list->map = NULL; | |
ab00b3e5 JB |
1378 | } |
1379 | ||
92b88aeb CW |
1380 | static uint32_t |
1381 | i915_gem_get_gtt_size(struct drm_i915_gem_object *obj) | |
1382 | { | |
1383 | struct drm_device *dev = obj->base.dev; | |
1384 | uint32_t size; | |
1385 | ||
1386 | if (INTEL_INFO(dev)->gen >= 4 || | |
1387 | obj->tiling_mode == I915_TILING_NONE) | |
1388 | return obj->base.size; | |
1389 | ||
1390 | /* Previous chips need a power-of-two fence region when tiling */ | |
1391 | if (INTEL_INFO(dev)->gen == 3) | |
1392 | size = 1024*1024; | |
1393 | else | |
1394 | size = 512*1024; | |
1395 | ||
1396 | while (size < obj->base.size) | |
1397 | size <<= 1; | |
1398 | ||
1399 | return size; | |
1400 | } | |
1401 | ||
de151cf6 JB |
1402 | /** |
1403 | * i915_gem_get_gtt_alignment - return required GTT alignment for an object | |
1404 | * @obj: object to check | |
1405 | * | |
1406 | * Return the required GTT alignment for an object, taking into account | |
5e783301 | 1407 | * potential fence register mapping. |
de151cf6 JB |
1408 | */ |
1409 | static uint32_t | |
05394f39 | 1410 | i915_gem_get_gtt_alignment(struct drm_i915_gem_object *obj) |
de151cf6 | 1411 | { |
05394f39 | 1412 | struct drm_device *dev = obj->base.dev; |
de151cf6 JB |
1413 | |
1414 | /* | |
1415 | * Minimum alignment is 4k (GTT page size), but might be greater | |
1416 | * if a fence register is needed for the object. | |
1417 | */ | |
a00b10c3 | 1418 | if (INTEL_INFO(dev)->gen >= 4 || |
05394f39 | 1419 | obj->tiling_mode == I915_TILING_NONE) |
de151cf6 JB |
1420 | return 4096; |
1421 | ||
a00b10c3 CW |
1422 | /* |
1423 | * Previous chips need to be aligned to the size of the smallest | |
1424 | * fence register that can contain the object. | |
1425 | */ | |
05394f39 | 1426 | return i915_gem_get_gtt_size(obj); |
a00b10c3 CW |
1427 | } |
1428 | ||
5e783301 DV |
1429 | /** |
1430 | * i915_gem_get_unfenced_gtt_alignment - return required GTT alignment for an | |
1431 | * unfenced object | |
1432 | * @obj: object to check | |
1433 | * | |
1434 | * Return the required GTT alignment for an object, only taking into account | |
1435 | * unfenced tiled surface requirements. | |
1436 | */ | |
467cffba | 1437 | uint32_t |
05394f39 | 1438 | i915_gem_get_unfenced_gtt_alignment(struct drm_i915_gem_object *obj) |
5e783301 | 1439 | { |
05394f39 | 1440 | struct drm_device *dev = obj->base.dev; |
5e783301 DV |
1441 | int tile_height; |
1442 | ||
1443 | /* | |
1444 | * Minimum alignment is 4k (GTT page size) for sane hw. | |
1445 | */ | |
1446 | if (INTEL_INFO(dev)->gen >= 4 || IS_G33(dev) || | |
05394f39 | 1447 | obj->tiling_mode == I915_TILING_NONE) |
5e783301 DV |
1448 | return 4096; |
1449 | ||
1450 | /* | |
1451 | * Older chips need unfenced tiled buffers to be aligned to the left | |
1452 | * edge of an even tile row (where tile rows are counted as if the bo is | |
1453 | * placed in a fenced gtt region). | |
1454 | */ | |
1455 | if (IS_GEN2(dev) || | |
05394f39 | 1456 | (obj->tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev))) |
5e783301 DV |
1457 | tile_height = 32; |
1458 | else | |
1459 | tile_height = 8; | |
1460 | ||
05394f39 | 1461 | return tile_height * obj->stride * 2; |
5e783301 DV |
1462 | } |
1463 | ||
de151cf6 | 1464 | int |
ff72145b DA |
1465 | i915_gem_mmap_gtt(struct drm_file *file, |
1466 | struct drm_device *dev, | |
1467 | uint32_t handle, | |
1468 | uint64_t *offset) | |
de151cf6 | 1469 | { |
da761a6e | 1470 | struct drm_i915_private *dev_priv = dev->dev_private; |
05394f39 | 1471 | struct drm_i915_gem_object *obj; |
de151cf6 JB |
1472 | int ret; |
1473 | ||
1474 | if (!(dev->driver->driver_features & DRIVER_GEM)) | |
1475 | return -ENODEV; | |
1476 | ||
76c1dec1 | 1477 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 1478 | if (ret) |
76c1dec1 | 1479 | return ret; |
de151cf6 | 1480 | |
ff72145b | 1481 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle)); |
c8725226 | 1482 | if (&obj->base == NULL) { |
1d7cfea1 CW |
1483 | ret = -ENOENT; |
1484 | goto unlock; | |
1485 | } | |
de151cf6 | 1486 | |
05394f39 | 1487 | if (obj->base.size > dev_priv->mm.gtt_mappable_end) { |
da761a6e CW |
1488 | ret = -E2BIG; |
1489 | goto unlock; | |
1490 | } | |
1491 | ||
05394f39 | 1492 | if (obj->madv != I915_MADV_WILLNEED) { |
ab18282d | 1493 | DRM_ERROR("Attempting to mmap a purgeable buffer\n"); |
1d7cfea1 CW |
1494 | ret = -EINVAL; |
1495 | goto out; | |
ab18282d CW |
1496 | } |
1497 | ||
05394f39 | 1498 | if (!obj->base.map_list.map) { |
de151cf6 | 1499 | ret = i915_gem_create_mmap_offset(obj); |
1d7cfea1 CW |
1500 | if (ret) |
1501 | goto out; | |
de151cf6 JB |
1502 | } |
1503 | ||
ff72145b | 1504 | *offset = (u64)obj->base.map_list.hash.key << PAGE_SHIFT; |
de151cf6 | 1505 | |
1d7cfea1 | 1506 | out: |
05394f39 | 1507 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 1508 | unlock: |
de151cf6 | 1509 | mutex_unlock(&dev->struct_mutex); |
1d7cfea1 | 1510 | return ret; |
de151cf6 JB |
1511 | } |
1512 | ||
ff72145b DA |
1513 | /** |
1514 | * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing | |
1515 | * @dev: DRM device | |
1516 | * @data: GTT mapping ioctl data | |
1517 | * @file: GEM object info | |
1518 | * | |
1519 | * Simply returns the fake offset to userspace so it can mmap it. | |
1520 | * The mmap call will end up in drm_gem_mmap(), which will set things | |
1521 | * up so we can get faults in the handler above. | |
1522 | * | |
1523 | * The fault handler will take care of binding the object into the GTT | |
1524 | * (since it may have been evicted to make room for something), allocating | |
1525 | * a fence register, and mapping the appropriate aperture address into | |
1526 | * userspace. | |
1527 | */ | |
1528 | int | |
1529 | i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data, | |
1530 | struct drm_file *file) | |
1531 | { | |
1532 | struct drm_i915_gem_mmap_gtt *args = data; | |
1533 | ||
1534 | if (!(dev->driver->driver_features & DRIVER_GEM)) | |
1535 | return -ENODEV; | |
1536 | ||
1537 | return i915_gem_mmap_gtt(file, dev, args->handle, &args->offset); | |
1538 | } | |
1539 | ||
1540 | ||
e5281ccd | 1541 | static int |
05394f39 | 1542 | i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj, |
e5281ccd CW |
1543 | gfp_t gfpmask) |
1544 | { | |
e5281ccd CW |
1545 | int page_count, i; |
1546 | struct address_space *mapping; | |
1547 | struct inode *inode; | |
1548 | struct page *page; | |
1549 | ||
1550 | /* Get the list of pages out of our struct file. They'll be pinned | |
1551 | * at this point until we release them. | |
1552 | */ | |
05394f39 CW |
1553 | page_count = obj->base.size / PAGE_SIZE; |
1554 | BUG_ON(obj->pages != NULL); | |
1555 | obj->pages = drm_malloc_ab(page_count, sizeof(struct page *)); | |
1556 | if (obj->pages == NULL) | |
e5281ccd CW |
1557 | return -ENOMEM; |
1558 | ||
05394f39 | 1559 | inode = obj->base.filp->f_path.dentry->d_inode; |
e5281ccd CW |
1560 | mapping = inode->i_mapping; |
1561 | for (i = 0; i < page_count; i++) { | |
1562 | page = read_cache_page_gfp(mapping, i, | |
1563 | GFP_HIGHUSER | | |
1564 | __GFP_COLD | | |
1565 | __GFP_RECLAIMABLE | | |
1566 | gfpmask); | |
1567 | if (IS_ERR(page)) | |
1568 | goto err_pages; | |
1569 | ||
05394f39 | 1570 | obj->pages[i] = page; |
e5281ccd CW |
1571 | } |
1572 | ||
05394f39 | 1573 | if (obj->tiling_mode != I915_TILING_NONE) |
e5281ccd CW |
1574 | i915_gem_object_do_bit_17_swizzle(obj); |
1575 | ||
1576 | return 0; | |
1577 | ||
1578 | err_pages: | |
1579 | while (i--) | |
05394f39 | 1580 | page_cache_release(obj->pages[i]); |
e5281ccd | 1581 | |
05394f39 CW |
1582 | drm_free_large(obj->pages); |
1583 | obj->pages = NULL; | |
e5281ccd CW |
1584 | return PTR_ERR(page); |
1585 | } | |
1586 | ||
5cdf5881 | 1587 | static void |
05394f39 | 1588 | i915_gem_object_put_pages_gtt(struct drm_i915_gem_object *obj) |
673a394b | 1589 | { |
05394f39 | 1590 | int page_count = obj->base.size / PAGE_SIZE; |
673a394b EA |
1591 | int i; |
1592 | ||
05394f39 | 1593 | BUG_ON(obj->madv == __I915_MADV_PURGED); |
673a394b | 1594 | |
05394f39 | 1595 | if (obj->tiling_mode != I915_TILING_NONE) |
280b713b EA |
1596 | i915_gem_object_save_bit_17_swizzle(obj); |
1597 | ||
05394f39 CW |
1598 | if (obj->madv == I915_MADV_DONTNEED) |
1599 | obj->dirty = 0; | |
3ef94daa CW |
1600 | |
1601 | for (i = 0; i < page_count; i++) { | |
05394f39 CW |
1602 | if (obj->dirty) |
1603 | set_page_dirty(obj->pages[i]); | |
3ef94daa | 1604 | |
05394f39 CW |
1605 | if (obj->madv == I915_MADV_WILLNEED) |
1606 | mark_page_accessed(obj->pages[i]); | |
3ef94daa | 1607 | |
05394f39 | 1608 | page_cache_release(obj->pages[i]); |
3ef94daa | 1609 | } |
05394f39 | 1610 | obj->dirty = 0; |
673a394b | 1611 | |
05394f39 CW |
1612 | drm_free_large(obj->pages); |
1613 | obj->pages = NULL; | |
673a394b EA |
1614 | } |
1615 | ||
54cf91dc | 1616 | void |
05394f39 | 1617 | i915_gem_object_move_to_active(struct drm_i915_gem_object *obj, |
1ec14ad3 CW |
1618 | struct intel_ring_buffer *ring, |
1619 | u32 seqno) | |
673a394b | 1620 | { |
05394f39 | 1621 | struct drm_device *dev = obj->base.dev; |
69dc4987 | 1622 | struct drm_i915_private *dev_priv = dev->dev_private; |
617dbe27 | 1623 | |
852835f3 | 1624 | BUG_ON(ring == NULL); |
05394f39 | 1625 | obj->ring = ring; |
673a394b EA |
1626 | |
1627 | /* Add a reference if we're newly entering the active list. */ | |
05394f39 CW |
1628 | if (!obj->active) { |
1629 | drm_gem_object_reference(&obj->base); | |
1630 | obj->active = 1; | |
673a394b | 1631 | } |
e35a41de | 1632 | |
673a394b | 1633 | /* Move from whatever list we were on to the tail of execution. */ |
05394f39 CW |
1634 | list_move_tail(&obj->mm_list, &dev_priv->mm.active_list); |
1635 | list_move_tail(&obj->ring_list, &ring->active_list); | |
caea7476 | 1636 | |
05394f39 | 1637 | obj->last_rendering_seqno = seqno; |
caea7476 CW |
1638 | if (obj->fenced_gpu_access) { |
1639 | struct drm_i915_fence_reg *reg; | |
1640 | ||
1641 | BUG_ON(obj->fence_reg == I915_FENCE_REG_NONE); | |
1642 | ||
1643 | obj->last_fenced_seqno = seqno; | |
1644 | obj->last_fenced_ring = ring; | |
1645 | ||
1646 | reg = &dev_priv->fence_regs[obj->fence_reg]; | |
1647 | list_move_tail(®->lru_list, &dev_priv->mm.fence_list); | |
1648 | } | |
1649 | } | |
1650 | ||
1651 | static void | |
1652 | i915_gem_object_move_off_active(struct drm_i915_gem_object *obj) | |
1653 | { | |
1654 | list_del_init(&obj->ring_list); | |
1655 | obj->last_rendering_seqno = 0; | |
673a394b EA |
1656 | } |
1657 | ||
ce44b0ea | 1658 | static void |
05394f39 | 1659 | i915_gem_object_move_to_flushing(struct drm_i915_gem_object *obj) |
ce44b0ea | 1660 | { |
05394f39 | 1661 | struct drm_device *dev = obj->base.dev; |
ce44b0ea | 1662 | drm_i915_private_t *dev_priv = dev->dev_private; |
ce44b0ea | 1663 | |
05394f39 CW |
1664 | BUG_ON(!obj->active); |
1665 | list_move_tail(&obj->mm_list, &dev_priv->mm.flushing_list); | |
caea7476 CW |
1666 | |
1667 | i915_gem_object_move_off_active(obj); | |
1668 | } | |
1669 | ||
1670 | static void | |
1671 | i915_gem_object_move_to_inactive(struct drm_i915_gem_object *obj) | |
1672 | { | |
1673 | struct drm_device *dev = obj->base.dev; | |
1674 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1675 | ||
1676 | if (obj->pin_count != 0) | |
1677 | list_move_tail(&obj->mm_list, &dev_priv->mm.pinned_list); | |
1678 | else | |
1679 | list_move_tail(&obj->mm_list, &dev_priv->mm.inactive_list); | |
1680 | ||
1681 | BUG_ON(!list_empty(&obj->gpu_write_list)); | |
1682 | BUG_ON(!obj->active); | |
1683 | obj->ring = NULL; | |
1684 | ||
1685 | i915_gem_object_move_off_active(obj); | |
1686 | obj->fenced_gpu_access = false; | |
caea7476 CW |
1687 | |
1688 | obj->active = 0; | |
87ca9c8a | 1689 | obj->pending_gpu_write = false; |
caea7476 CW |
1690 | drm_gem_object_unreference(&obj->base); |
1691 | ||
1692 | WARN_ON(i915_verify_lists(dev)); | |
ce44b0ea | 1693 | } |
673a394b | 1694 | |
963b4836 CW |
1695 | /* Immediately discard the backing storage */ |
1696 | static void | |
05394f39 | 1697 | i915_gem_object_truncate(struct drm_i915_gem_object *obj) |
963b4836 | 1698 | { |
bb6baf76 | 1699 | struct inode *inode; |
963b4836 | 1700 | |
ae9fed6b CW |
1701 | /* Our goal here is to return as much of the memory as |
1702 | * is possible back to the system as we are called from OOM. | |
1703 | * To do this we must instruct the shmfs to drop all of its | |
1704 | * backing pages, *now*. Here we mirror the actions taken | |
1705 | * when by shmem_delete_inode() to release the backing store. | |
1706 | */ | |
05394f39 | 1707 | inode = obj->base.filp->f_path.dentry->d_inode; |
ae9fed6b CW |
1708 | truncate_inode_pages(inode->i_mapping, 0); |
1709 | if (inode->i_op->truncate_range) | |
1710 | inode->i_op->truncate_range(inode, 0, (loff_t)-1); | |
bb6baf76 | 1711 | |
05394f39 | 1712 | obj->madv = __I915_MADV_PURGED; |
963b4836 CW |
1713 | } |
1714 | ||
1715 | static inline int | |
05394f39 | 1716 | i915_gem_object_is_purgeable(struct drm_i915_gem_object *obj) |
963b4836 | 1717 | { |
05394f39 | 1718 | return obj->madv == I915_MADV_DONTNEED; |
963b4836 CW |
1719 | } |
1720 | ||
63560396 | 1721 | static void |
db53a302 CW |
1722 | i915_gem_process_flushing_list(struct intel_ring_buffer *ring, |
1723 | uint32_t flush_domains) | |
63560396 | 1724 | { |
05394f39 | 1725 | struct drm_i915_gem_object *obj, *next; |
63560396 | 1726 | |
05394f39 | 1727 | list_for_each_entry_safe(obj, next, |
64193406 | 1728 | &ring->gpu_write_list, |
63560396 | 1729 | gpu_write_list) { |
05394f39 CW |
1730 | if (obj->base.write_domain & flush_domains) { |
1731 | uint32_t old_write_domain = obj->base.write_domain; | |
63560396 | 1732 | |
05394f39 CW |
1733 | obj->base.write_domain = 0; |
1734 | list_del_init(&obj->gpu_write_list); | |
1ec14ad3 | 1735 | i915_gem_object_move_to_active(obj, ring, |
db53a302 | 1736 | i915_gem_next_request_seqno(ring)); |
63560396 | 1737 | |
63560396 | 1738 | trace_i915_gem_object_change_domain(obj, |
05394f39 | 1739 | obj->base.read_domains, |
63560396 DV |
1740 | old_write_domain); |
1741 | } | |
1742 | } | |
1743 | } | |
8187a2b7 | 1744 | |
3cce469c | 1745 | int |
db53a302 | 1746 | i915_add_request(struct intel_ring_buffer *ring, |
f787a5f5 | 1747 | struct drm_file *file, |
db53a302 | 1748 | struct drm_i915_gem_request *request) |
673a394b | 1749 | { |
db53a302 | 1750 | drm_i915_private_t *dev_priv = ring->dev->dev_private; |
673a394b EA |
1751 | uint32_t seqno; |
1752 | int was_empty; | |
3cce469c CW |
1753 | int ret; |
1754 | ||
1755 | BUG_ON(request == NULL); | |
673a394b | 1756 | |
3cce469c CW |
1757 | ret = ring->add_request(ring, &seqno); |
1758 | if (ret) | |
1759 | return ret; | |
673a394b | 1760 | |
db53a302 | 1761 | trace_i915_gem_request_add(ring, seqno); |
673a394b EA |
1762 | |
1763 | request->seqno = seqno; | |
852835f3 | 1764 | request->ring = ring; |
673a394b | 1765 | request->emitted_jiffies = jiffies; |
852835f3 ZN |
1766 | was_empty = list_empty(&ring->request_list); |
1767 | list_add_tail(&request->list, &ring->request_list); | |
1768 | ||
db53a302 CW |
1769 | if (file) { |
1770 | struct drm_i915_file_private *file_priv = file->driver_priv; | |
1771 | ||
1c25595f | 1772 | spin_lock(&file_priv->mm.lock); |
f787a5f5 | 1773 | request->file_priv = file_priv; |
b962442e | 1774 | list_add_tail(&request->client_list, |
f787a5f5 | 1775 | &file_priv->mm.request_list); |
1c25595f | 1776 | spin_unlock(&file_priv->mm.lock); |
b962442e | 1777 | } |
673a394b | 1778 | |
db53a302 CW |
1779 | ring->outstanding_lazy_request = false; |
1780 | ||
f65d9421 | 1781 | if (!dev_priv->mm.suspended) { |
b3b079db CW |
1782 | mod_timer(&dev_priv->hangcheck_timer, |
1783 | jiffies + msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD)); | |
f65d9421 | 1784 | if (was_empty) |
b3b079db CW |
1785 | queue_delayed_work(dev_priv->wq, |
1786 | &dev_priv->mm.retire_work, HZ); | |
f65d9421 | 1787 | } |
3cce469c | 1788 | return 0; |
673a394b EA |
1789 | } |
1790 | ||
f787a5f5 CW |
1791 | static inline void |
1792 | i915_gem_request_remove_from_client(struct drm_i915_gem_request *request) | |
673a394b | 1793 | { |
1c25595f | 1794 | struct drm_i915_file_private *file_priv = request->file_priv; |
673a394b | 1795 | |
1c25595f CW |
1796 | if (!file_priv) |
1797 | return; | |
1c5d22f7 | 1798 | |
1c25595f | 1799 | spin_lock(&file_priv->mm.lock); |
09bfa517 HRK |
1800 | if (request->file_priv) { |
1801 | list_del(&request->client_list); | |
1802 | request->file_priv = NULL; | |
1803 | } | |
1c25595f | 1804 | spin_unlock(&file_priv->mm.lock); |
673a394b | 1805 | } |
673a394b | 1806 | |
dfaae392 CW |
1807 | static void i915_gem_reset_ring_lists(struct drm_i915_private *dev_priv, |
1808 | struct intel_ring_buffer *ring) | |
9375e446 | 1809 | { |
dfaae392 CW |
1810 | while (!list_empty(&ring->request_list)) { |
1811 | struct drm_i915_gem_request *request; | |
673a394b | 1812 | |
dfaae392 CW |
1813 | request = list_first_entry(&ring->request_list, |
1814 | struct drm_i915_gem_request, | |
1815 | list); | |
de151cf6 | 1816 | |
dfaae392 | 1817 | list_del(&request->list); |
f787a5f5 | 1818 | i915_gem_request_remove_from_client(request); |
dfaae392 CW |
1819 | kfree(request); |
1820 | } | |
673a394b | 1821 | |
dfaae392 | 1822 | while (!list_empty(&ring->active_list)) { |
05394f39 | 1823 | struct drm_i915_gem_object *obj; |
9375e446 | 1824 | |
05394f39 CW |
1825 | obj = list_first_entry(&ring->active_list, |
1826 | struct drm_i915_gem_object, | |
1827 | ring_list); | |
9375e446 | 1828 | |
05394f39 CW |
1829 | obj->base.write_domain = 0; |
1830 | list_del_init(&obj->gpu_write_list); | |
1831 | i915_gem_object_move_to_inactive(obj); | |
673a394b EA |
1832 | } |
1833 | } | |
1834 | ||
312817a3 CW |
1835 | static void i915_gem_reset_fences(struct drm_device *dev) |
1836 | { | |
1837 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1838 | int i; | |
1839 | ||
1840 | for (i = 0; i < 16; i++) { | |
1841 | struct drm_i915_fence_reg *reg = &dev_priv->fence_regs[i]; | |
7d2cb39c CW |
1842 | struct drm_i915_gem_object *obj = reg->obj; |
1843 | ||
1844 | if (!obj) | |
1845 | continue; | |
1846 | ||
1847 | if (obj->tiling_mode) | |
1848 | i915_gem_release_mmap(obj); | |
1849 | ||
d9e86c0e CW |
1850 | reg->obj->fence_reg = I915_FENCE_REG_NONE; |
1851 | reg->obj->fenced_gpu_access = false; | |
1852 | reg->obj->last_fenced_seqno = 0; | |
1853 | reg->obj->last_fenced_ring = NULL; | |
1854 | i915_gem_clear_fence_reg(dev, reg); | |
312817a3 CW |
1855 | } |
1856 | } | |
1857 | ||
069efc1d | 1858 | void i915_gem_reset(struct drm_device *dev) |
673a394b | 1859 | { |
77f01230 | 1860 | struct drm_i915_private *dev_priv = dev->dev_private; |
05394f39 | 1861 | struct drm_i915_gem_object *obj; |
1ec14ad3 | 1862 | int i; |
673a394b | 1863 | |
1ec14ad3 CW |
1864 | for (i = 0; i < I915_NUM_RINGS; i++) |
1865 | i915_gem_reset_ring_lists(dev_priv, &dev_priv->ring[i]); | |
dfaae392 CW |
1866 | |
1867 | /* Remove anything from the flushing lists. The GPU cache is likely | |
1868 | * to be lost on reset along with the data, so simply move the | |
1869 | * lost bo to the inactive list. | |
1870 | */ | |
1871 | while (!list_empty(&dev_priv->mm.flushing_list)) { | |
05394f39 CW |
1872 | obj= list_first_entry(&dev_priv->mm.flushing_list, |
1873 | struct drm_i915_gem_object, | |
1874 | mm_list); | |
dfaae392 | 1875 | |
05394f39 CW |
1876 | obj->base.write_domain = 0; |
1877 | list_del_init(&obj->gpu_write_list); | |
1878 | i915_gem_object_move_to_inactive(obj); | |
dfaae392 CW |
1879 | } |
1880 | ||
1881 | /* Move everything out of the GPU domains to ensure we do any | |
1882 | * necessary invalidation upon reuse. | |
1883 | */ | |
05394f39 | 1884 | list_for_each_entry(obj, |
77f01230 | 1885 | &dev_priv->mm.inactive_list, |
69dc4987 | 1886 | mm_list) |
77f01230 | 1887 | { |
05394f39 | 1888 | obj->base.read_domains &= ~I915_GEM_GPU_DOMAINS; |
77f01230 | 1889 | } |
069efc1d CW |
1890 | |
1891 | /* The fence registers are invalidated so clear them out */ | |
312817a3 | 1892 | i915_gem_reset_fences(dev); |
673a394b EA |
1893 | } |
1894 | ||
1895 | /** | |
1896 | * This function clears the request list as sequence numbers are passed. | |
1897 | */ | |
b09a1fec | 1898 | static void |
db53a302 | 1899 | i915_gem_retire_requests_ring(struct intel_ring_buffer *ring) |
673a394b | 1900 | { |
673a394b | 1901 | uint32_t seqno; |
1ec14ad3 | 1902 | int i; |
673a394b | 1903 | |
db53a302 | 1904 | if (list_empty(&ring->request_list)) |
6c0594a3 KW |
1905 | return; |
1906 | ||
db53a302 | 1907 | WARN_ON(i915_verify_lists(ring->dev)); |
673a394b | 1908 | |
78501eac | 1909 | seqno = ring->get_seqno(ring); |
1ec14ad3 | 1910 | |
076e2c0e | 1911 | for (i = 0; i < ARRAY_SIZE(ring->sync_seqno); i++) |
1ec14ad3 CW |
1912 | if (seqno >= ring->sync_seqno[i]) |
1913 | ring->sync_seqno[i] = 0; | |
1914 | ||
852835f3 | 1915 | while (!list_empty(&ring->request_list)) { |
673a394b | 1916 | struct drm_i915_gem_request *request; |
673a394b | 1917 | |
852835f3 | 1918 | request = list_first_entry(&ring->request_list, |
673a394b EA |
1919 | struct drm_i915_gem_request, |
1920 | list); | |
673a394b | 1921 | |
dfaae392 | 1922 | if (!i915_seqno_passed(seqno, request->seqno)) |
b84d5f0c CW |
1923 | break; |
1924 | ||
db53a302 | 1925 | trace_i915_gem_request_retire(ring, request->seqno); |
b84d5f0c CW |
1926 | |
1927 | list_del(&request->list); | |
f787a5f5 | 1928 | i915_gem_request_remove_from_client(request); |
b84d5f0c CW |
1929 | kfree(request); |
1930 | } | |
673a394b | 1931 | |
b84d5f0c CW |
1932 | /* Move any buffers on the active list that are no longer referenced |
1933 | * by the ringbuffer to the flushing/inactive lists as appropriate. | |
1934 | */ | |
1935 | while (!list_empty(&ring->active_list)) { | |
05394f39 | 1936 | struct drm_i915_gem_object *obj; |
b84d5f0c | 1937 | |
05394f39 CW |
1938 | obj= list_first_entry(&ring->active_list, |
1939 | struct drm_i915_gem_object, | |
1940 | ring_list); | |
673a394b | 1941 | |
05394f39 | 1942 | if (!i915_seqno_passed(seqno, obj->last_rendering_seqno)) |
673a394b | 1943 | break; |
b84d5f0c | 1944 | |
05394f39 | 1945 | if (obj->base.write_domain != 0) |
b84d5f0c CW |
1946 | i915_gem_object_move_to_flushing(obj); |
1947 | else | |
1948 | i915_gem_object_move_to_inactive(obj); | |
673a394b | 1949 | } |
9d34e5db | 1950 | |
db53a302 CW |
1951 | if (unlikely(ring->trace_irq_seqno && |
1952 | i915_seqno_passed(seqno, ring->trace_irq_seqno))) { | |
1ec14ad3 | 1953 | ring->irq_put(ring); |
db53a302 | 1954 | ring->trace_irq_seqno = 0; |
9d34e5db | 1955 | } |
23bc5982 | 1956 | |
db53a302 | 1957 | WARN_ON(i915_verify_lists(ring->dev)); |
673a394b EA |
1958 | } |
1959 | ||
b09a1fec CW |
1960 | void |
1961 | i915_gem_retire_requests(struct drm_device *dev) | |
1962 | { | |
1963 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1ec14ad3 | 1964 | int i; |
b09a1fec | 1965 | |
be72615b | 1966 | if (!list_empty(&dev_priv->mm.deferred_free_list)) { |
05394f39 | 1967 | struct drm_i915_gem_object *obj, *next; |
be72615b CW |
1968 | |
1969 | /* We must be careful that during unbind() we do not | |
1970 | * accidentally infinitely recurse into retire requests. | |
1971 | * Currently: | |
1972 | * retire -> free -> unbind -> wait -> retire_ring | |
1973 | */ | |
05394f39 | 1974 | list_for_each_entry_safe(obj, next, |
be72615b | 1975 | &dev_priv->mm.deferred_free_list, |
69dc4987 | 1976 | mm_list) |
05394f39 | 1977 | i915_gem_free_object_tail(obj); |
be72615b CW |
1978 | } |
1979 | ||
1ec14ad3 | 1980 | for (i = 0; i < I915_NUM_RINGS; i++) |
db53a302 | 1981 | i915_gem_retire_requests_ring(&dev_priv->ring[i]); |
b09a1fec CW |
1982 | } |
1983 | ||
75ef9da2 | 1984 | static void |
673a394b EA |
1985 | i915_gem_retire_work_handler(struct work_struct *work) |
1986 | { | |
1987 | drm_i915_private_t *dev_priv; | |
1988 | struct drm_device *dev; | |
0a58705b CW |
1989 | bool idle; |
1990 | int i; | |
673a394b EA |
1991 | |
1992 | dev_priv = container_of(work, drm_i915_private_t, | |
1993 | mm.retire_work.work); | |
1994 | dev = dev_priv->dev; | |
1995 | ||
891b48cf CW |
1996 | /* Come back later if the device is busy... */ |
1997 | if (!mutex_trylock(&dev->struct_mutex)) { | |
1998 | queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, HZ); | |
1999 | return; | |
2000 | } | |
2001 | ||
b09a1fec | 2002 | i915_gem_retire_requests(dev); |
d1b851fc | 2003 | |
0a58705b CW |
2004 | /* Send a periodic flush down the ring so we don't hold onto GEM |
2005 | * objects indefinitely. | |
2006 | */ | |
2007 | idle = true; | |
2008 | for (i = 0; i < I915_NUM_RINGS; i++) { | |
2009 | struct intel_ring_buffer *ring = &dev_priv->ring[i]; | |
2010 | ||
2011 | if (!list_empty(&ring->gpu_write_list)) { | |
2012 | struct drm_i915_gem_request *request; | |
2013 | int ret; | |
2014 | ||
db53a302 CW |
2015 | ret = i915_gem_flush_ring(ring, |
2016 | 0, I915_GEM_GPU_DOMAINS); | |
0a58705b CW |
2017 | request = kzalloc(sizeof(*request), GFP_KERNEL); |
2018 | if (ret || request == NULL || | |
db53a302 | 2019 | i915_add_request(ring, NULL, request)) |
0a58705b CW |
2020 | kfree(request); |
2021 | } | |
2022 | ||
2023 | idle &= list_empty(&ring->request_list); | |
2024 | } | |
2025 | ||
2026 | if (!dev_priv->mm.suspended && !idle) | |
9c9fe1f8 | 2027 | queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, HZ); |
0a58705b | 2028 | |
673a394b EA |
2029 | mutex_unlock(&dev->struct_mutex); |
2030 | } | |
2031 | ||
db53a302 CW |
2032 | /** |
2033 | * Waits for a sequence number to be signaled, and cleans up the | |
2034 | * request and object lists appropriately for that event. | |
2035 | */ | |
5a5a0c64 | 2036 | int |
db53a302 | 2037 | i915_wait_request(struct intel_ring_buffer *ring, |
ce453d81 | 2038 | uint32_t seqno) |
673a394b | 2039 | { |
db53a302 | 2040 | drm_i915_private_t *dev_priv = ring->dev->dev_private; |
802c7eb6 | 2041 | u32 ier; |
673a394b EA |
2042 | int ret = 0; |
2043 | ||
2044 | BUG_ON(seqno == 0); | |
2045 | ||
d9bc7e9f CW |
2046 | if (atomic_read(&dev_priv->mm.wedged)) { |
2047 | struct completion *x = &dev_priv->error_completion; | |
2048 | bool recovery_complete; | |
2049 | unsigned long flags; | |
2050 | ||
2051 | /* Give the error handler a chance to run. */ | |
2052 | spin_lock_irqsave(&x->wait.lock, flags); | |
2053 | recovery_complete = x->done > 0; | |
2054 | spin_unlock_irqrestore(&x->wait.lock, flags); | |
2055 | ||
2056 | return recovery_complete ? -EIO : -EAGAIN; | |
2057 | } | |
30dbf0c0 | 2058 | |
5d97eb69 | 2059 | if (seqno == ring->outstanding_lazy_request) { |
3cce469c CW |
2060 | struct drm_i915_gem_request *request; |
2061 | ||
2062 | request = kzalloc(sizeof(*request), GFP_KERNEL); | |
2063 | if (request == NULL) | |
e35a41de | 2064 | return -ENOMEM; |
3cce469c | 2065 | |
db53a302 | 2066 | ret = i915_add_request(ring, NULL, request); |
3cce469c CW |
2067 | if (ret) { |
2068 | kfree(request); | |
2069 | return ret; | |
2070 | } | |
2071 | ||
2072 | seqno = request->seqno; | |
e35a41de | 2073 | } |
ffed1d09 | 2074 | |
78501eac | 2075 | if (!i915_seqno_passed(ring->get_seqno(ring), seqno)) { |
db53a302 | 2076 | if (HAS_PCH_SPLIT(ring->dev)) |
036a4a7d ZW |
2077 | ier = I915_READ(DEIER) | I915_READ(GTIER); |
2078 | else | |
2079 | ier = I915_READ(IER); | |
802c7eb6 JB |
2080 | if (!ier) { |
2081 | DRM_ERROR("something (likely vbetool) disabled " | |
2082 | "interrupts, re-enabling\n"); | |
db53a302 CW |
2083 | i915_driver_irq_preinstall(ring->dev); |
2084 | i915_driver_irq_postinstall(ring->dev); | |
802c7eb6 JB |
2085 | } |
2086 | ||
db53a302 | 2087 | trace_i915_gem_request_wait_begin(ring, seqno); |
1c5d22f7 | 2088 | |
b2223497 | 2089 | ring->waiting_seqno = seqno; |
b13c2b96 | 2090 | if (ring->irq_get(ring)) { |
ce453d81 | 2091 | if (dev_priv->mm.interruptible) |
b13c2b96 CW |
2092 | ret = wait_event_interruptible(ring->irq_queue, |
2093 | i915_seqno_passed(ring->get_seqno(ring), seqno) | |
2094 | || atomic_read(&dev_priv->mm.wedged)); | |
2095 | else | |
2096 | wait_event(ring->irq_queue, | |
2097 | i915_seqno_passed(ring->get_seqno(ring), seqno) | |
2098 | || atomic_read(&dev_priv->mm.wedged)); | |
2099 | ||
2100 | ring->irq_put(ring); | |
b5ba177d CW |
2101 | } else if (wait_for(i915_seqno_passed(ring->get_seqno(ring), |
2102 | seqno) || | |
2103 | atomic_read(&dev_priv->mm.wedged), 3000)) | |
2104 | ret = -EBUSY; | |
b2223497 | 2105 | ring->waiting_seqno = 0; |
1c5d22f7 | 2106 | |
db53a302 | 2107 | trace_i915_gem_request_wait_end(ring, seqno); |
673a394b | 2108 | } |
ba1234d1 | 2109 | if (atomic_read(&dev_priv->mm.wedged)) |
30dbf0c0 | 2110 | ret = -EAGAIN; |
673a394b EA |
2111 | |
2112 | if (ret && ret != -ERESTARTSYS) | |
8bff917c | 2113 | DRM_ERROR("%s returns %d (awaiting %d at %d, next %d)\n", |
78501eac | 2114 | __func__, ret, seqno, ring->get_seqno(ring), |
8bff917c | 2115 | dev_priv->next_seqno); |
673a394b EA |
2116 | |
2117 | /* Directly dispatch request retiring. While we have the work queue | |
2118 | * to handle this, the waiter on a request often wants an associated | |
2119 | * buffer to have made it to the inactive list, and we would need | |
2120 | * a separate wait queue to handle that. | |
2121 | */ | |
2122 | if (ret == 0) | |
db53a302 | 2123 | i915_gem_retire_requests_ring(ring); |
673a394b EA |
2124 | |
2125 | return ret; | |
2126 | } | |
2127 | ||
673a394b EA |
2128 | /** |
2129 | * Ensures that all rendering to the object has completed and the object is | |
2130 | * safe to unbind from the GTT or access from the CPU. | |
2131 | */ | |
54cf91dc | 2132 | int |
ce453d81 | 2133 | i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj) |
673a394b | 2134 | { |
673a394b EA |
2135 | int ret; |
2136 | ||
e47c68e9 EA |
2137 | /* This function only exists to support waiting for existing rendering, |
2138 | * not for emitting required flushes. | |
673a394b | 2139 | */ |
05394f39 | 2140 | BUG_ON((obj->base.write_domain & I915_GEM_GPU_DOMAINS) != 0); |
673a394b EA |
2141 | |
2142 | /* If there is rendering queued on the buffer being evicted, wait for | |
2143 | * it. | |
2144 | */ | |
05394f39 | 2145 | if (obj->active) { |
ce453d81 | 2146 | ret = i915_wait_request(obj->ring, obj->last_rendering_seqno); |
2cf34d7b | 2147 | if (ret) |
673a394b EA |
2148 | return ret; |
2149 | } | |
2150 | ||
2151 | return 0; | |
2152 | } | |
2153 | ||
2154 | /** | |
2155 | * Unbinds an object from the GTT aperture. | |
2156 | */ | |
0f973f27 | 2157 | int |
05394f39 | 2158 | i915_gem_object_unbind(struct drm_i915_gem_object *obj) |
673a394b | 2159 | { |
673a394b EA |
2160 | int ret = 0; |
2161 | ||
05394f39 | 2162 | if (obj->gtt_space == NULL) |
673a394b EA |
2163 | return 0; |
2164 | ||
05394f39 | 2165 | if (obj->pin_count != 0) { |
673a394b EA |
2166 | DRM_ERROR("Attempting to unbind pinned buffer\n"); |
2167 | return -EINVAL; | |
2168 | } | |
2169 | ||
5323fd04 EA |
2170 | /* blow away mappings if mapped through GTT */ |
2171 | i915_gem_release_mmap(obj); | |
2172 | ||
673a394b EA |
2173 | /* Move the object to the CPU domain to ensure that |
2174 | * any possible CPU writes while it's not in the GTT | |
2175 | * are flushed when we go to remap it. This will | |
2176 | * also ensure that all pending GPU writes are finished | |
2177 | * before we unbind. | |
2178 | */ | |
e47c68e9 | 2179 | ret = i915_gem_object_set_to_cpu_domain(obj, 1); |
8dc1775d | 2180 | if (ret == -ERESTARTSYS) |
673a394b | 2181 | return ret; |
8dc1775d CW |
2182 | /* Continue on if we fail due to EIO, the GPU is hung so we |
2183 | * should be safe and we need to cleanup or else we might | |
2184 | * cause memory corruption through use-after-free. | |
2185 | */ | |
812ed492 CW |
2186 | if (ret) { |
2187 | i915_gem_clflush_object(obj); | |
05394f39 | 2188 | obj->base.read_domains = obj->base.write_domain = I915_GEM_DOMAIN_CPU; |
812ed492 | 2189 | } |
673a394b | 2190 | |
96b47b65 | 2191 | /* release the fence reg _after_ flushing */ |
d9e86c0e CW |
2192 | ret = i915_gem_object_put_fence(obj); |
2193 | if (ret == -ERESTARTSYS) | |
2194 | return ret; | |
96b47b65 | 2195 | |
db53a302 CW |
2196 | trace_i915_gem_object_unbind(obj); |
2197 | ||
7c2e6fdf | 2198 | i915_gem_gtt_unbind_object(obj); |
e5281ccd | 2199 | i915_gem_object_put_pages_gtt(obj); |
673a394b | 2200 | |
6299f992 | 2201 | list_del_init(&obj->gtt_list); |
05394f39 | 2202 | list_del_init(&obj->mm_list); |
75e9e915 | 2203 | /* Avoid an unnecessary call to unbind on rebind. */ |
05394f39 | 2204 | obj->map_and_fenceable = true; |
673a394b | 2205 | |
05394f39 CW |
2206 | drm_mm_put_block(obj->gtt_space); |
2207 | obj->gtt_space = NULL; | |
2208 | obj->gtt_offset = 0; | |
673a394b | 2209 | |
05394f39 | 2210 | if (i915_gem_object_is_purgeable(obj)) |
963b4836 CW |
2211 | i915_gem_object_truncate(obj); |
2212 | ||
8dc1775d | 2213 | return ret; |
673a394b EA |
2214 | } |
2215 | ||
88241785 | 2216 | int |
db53a302 | 2217 | i915_gem_flush_ring(struct intel_ring_buffer *ring, |
54cf91dc CW |
2218 | uint32_t invalidate_domains, |
2219 | uint32_t flush_domains) | |
2220 | { | |
88241785 CW |
2221 | int ret; |
2222 | ||
36d527de CW |
2223 | if (((invalidate_domains | flush_domains) & I915_GEM_GPU_DOMAINS) == 0) |
2224 | return 0; | |
2225 | ||
db53a302 CW |
2226 | trace_i915_gem_ring_flush(ring, invalidate_domains, flush_domains); |
2227 | ||
88241785 CW |
2228 | ret = ring->flush(ring, invalidate_domains, flush_domains); |
2229 | if (ret) | |
2230 | return ret; | |
2231 | ||
36d527de CW |
2232 | if (flush_domains & I915_GEM_GPU_DOMAINS) |
2233 | i915_gem_process_flushing_list(ring, flush_domains); | |
2234 | ||
88241785 | 2235 | return 0; |
54cf91dc CW |
2236 | } |
2237 | ||
db53a302 | 2238 | static int i915_ring_idle(struct intel_ring_buffer *ring) |
a56ba56c | 2239 | { |
88241785 CW |
2240 | int ret; |
2241 | ||
395b70be | 2242 | if (list_empty(&ring->gpu_write_list) && list_empty(&ring->active_list)) |
64193406 CW |
2243 | return 0; |
2244 | ||
88241785 | 2245 | if (!list_empty(&ring->gpu_write_list)) { |
db53a302 | 2246 | ret = i915_gem_flush_ring(ring, |
0ac74c6b | 2247 | I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS); |
88241785 CW |
2248 | if (ret) |
2249 | return ret; | |
2250 | } | |
2251 | ||
ce453d81 | 2252 | return i915_wait_request(ring, i915_gem_next_request_seqno(ring)); |
a56ba56c CW |
2253 | } |
2254 | ||
b47eb4a2 | 2255 | int |
4df2faf4 DV |
2256 | i915_gpu_idle(struct drm_device *dev) |
2257 | { | |
2258 | drm_i915_private_t *dev_priv = dev->dev_private; | |
2259 | bool lists_empty; | |
1ec14ad3 | 2260 | int ret, i; |
4df2faf4 | 2261 | |
d1b851fc | 2262 | lists_empty = (list_empty(&dev_priv->mm.flushing_list) && |
395b70be | 2263 | list_empty(&dev_priv->mm.active_list)); |
4df2faf4 DV |
2264 | if (lists_empty) |
2265 | return 0; | |
2266 | ||
2267 | /* Flush everything onto the inactive list. */ | |
1ec14ad3 | 2268 | for (i = 0; i < I915_NUM_RINGS; i++) { |
db53a302 | 2269 | ret = i915_ring_idle(&dev_priv->ring[i]); |
1ec14ad3 CW |
2270 | if (ret) |
2271 | return ret; | |
2272 | } | |
4df2faf4 | 2273 | |
8a1a49f9 | 2274 | return 0; |
4df2faf4 DV |
2275 | } |
2276 | ||
c6642782 DV |
2277 | static int sandybridge_write_fence_reg(struct drm_i915_gem_object *obj, |
2278 | struct intel_ring_buffer *pipelined) | |
4e901fdc | 2279 | { |
05394f39 | 2280 | struct drm_device *dev = obj->base.dev; |
4e901fdc | 2281 | drm_i915_private_t *dev_priv = dev->dev_private; |
05394f39 CW |
2282 | u32 size = obj->gtt_space->size; |
2283 | int regnum = obj->fence_reg; | |
4e901fdc EA |
2284 | uint64_t val; |
2285 | ||
05394f39 | 2286 | val = (uint64_t)((obj->gtt_offset + size - 4096) & |
c6642782 | 2287 | 0xfffff000) << 32; |
05394f39 CW |
2288 | val |= obj->gtt_offset & 0xfffff000; |
2289 | val |= (uint64_t)((obj->stride / 128) - 1) << | |
4e901fdc EA |
2290 | SANDYBRIDGE_FENCE_PITCH_SHIFT; |
2291 | ||
05394f39 | 2292 | if (obj->tiling_mode == I915_TILING_Y) |
4e901fdc EA |
2293 | val |= 1 << I965_FENCE_TILING_Y_SHIFT; |
2294 | val |= I965_FENCE_REG_VALID; | |
2295 | ||
c6642782 DV |
2296 | if (pipelined) { |
2297 | int ret = intel_ring_begin(pipelined, 6); | |
2298 | if (ret) | |
2299 | return ret; | |
2300 | ||
2301 | intel_ring_emit(pipelined, MI_NOOP); | |
2302 | intel_ring_emit(pipelined, MI_LOAD_REGISTER_IMM(2)); | |
2303 | intel_ring_emit(pipelined, FENCE_REG_SANDYBRIDGE_0 + regnum*8); | |
2304 | intel_ring_emit(pipelined, (u32)val); | |
2305 | intel_ring_emit(pipelined, FENCE_REG_SANDYBRIDGE_0 + regnum*8 + 4); | |
2306 | intel_ring_emit(pipelined, (u32)(val >> 32)); | |
2307 | intel_ring_advance(pipelined); | |
2308 | } else | |
2309 | I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + regnum * 8, val); | |
2310 | ||
2311 | return 0; | |
4e901fdc EA |
2312 | } |
2313 | ||
c6642782 DV |
2314 | static int i965_write_fence_reg(struct drm_i915_gem_object *obj, |
2315 | struct intel_ring_buffer *pipelined) | |
de151cf6 | 2316 | { |
05394f39 | 2317 | struct drm_device *dev = obj->base.dev; |
de151cf6 | 2318 | drm_i915_private_t *dev_priv = dev->dev_private; |
05394f39 CW |
2319 | u32 size = obj->gtt_space->size; |
2320 | int regnum = obj->fence_reg; | |
de151cf6 JB |
2321 | uint64_t val; |
2322 | ||
05394f39 | 2323 | val = (uint64_t)((obj->gtt_offset + size - 4096) & |
de151cf6 | 2324 | 0xfffff000) << 32; |
05394f39 CW |
2325 | val |= obj->gtt_offset & 0xfffff000; |
2326 | val |= ((obj->stride / 128) - 1) << I965_FENCE_PITCH_SHIFT; | |
2327 | if (obj->tiling_mode == I915_TILING_Y) | |
de151cf6 JB |
2328 | val |= 1 << I965_FENCE_TILING_Y_SHIFT; |
2329 | val |= I965_FENCE_REG_VALID; | |
2330 | ||
c6642782 DV |
2331 | if (pipelined) { |
2332 | int ret = intel_ring_begin(pipelined, 6); | |
2333 | if (ret) | |
2334 | return ret; | |
2335 | ||
2336 | intel_ring_emit(pipelined, MI_NOOP); | |
2337 | intel_ring_emit(pipelined, MI_LOAD_REGISTER_IMM(2)); | |
2338 | intel_ring_emit(pipelined, FENCE_REG_965_0 + regnum*8); | |
2339 | intel_ring_emit(pipelined, (u32)val); | |
2340 | intel_ring_emit(pipelined, FENCE_REG_965_0 + regnum*8 + 4); | |
2341 | intel_ring_emit(pipelined, (u32)(val >> 32)); | |
2342 | intel_ring_advance(pipelined); | |
2343 | } else | |
2344 | I915_WRITE64(FENCE_REG_965_0 + regnum * 8, val); | |
2345 | ||
2346 | return 0; | |
de151cf6 JB |
2347 | } |
2348 | ||
c6642782 DV |
2349 | static int i915_write_fence_reg(struct drm_i915_gem_object *obj, |
2350 | struct intel_ring_buffer *pipelined) | |
de151cf6 | 2351 | { |
05394f39 | 2352 | struct drm_device *dev = obj->base.dev; |
de151cf6 | 2353 | drm_i915_private_t *dev_priv = dev->dev_private; |
05394f39 | 2354 | u32 size = obj->gtt_space->size; |
c6642782 | 2355 | u32 fence_reg, val, pitch_val; |
0f973f27 | 2356 | int tile_width; |
de151cf6 | 2357 | |
c6642782 DV |
2358 | if (WARN((obj->gtt_offset & ~I915_FENCE_START_MASK) || |
2359 | (size & -size) != size || | |
2360 | (obj->gtt_offset & (size - 1)), | |
2361 | "object 0x%08x [fenceable? %d] not 1M or pot-size (0x%08x) aligned\n", | |
2362 | obj->gtt_offset, obj->map_and_fenceable, size)) | |
2363 | return -EINVAL; | |
de151cf6 | 2364 | |
c6642782 | 2365 | if (obj->tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev)) |
0f973f27 | 2366 | tile_width = 128; |
de151cf6 | 2367 | else |
0f973f27 JB |
2368 | tile_width = 512; |
2369 | ||
2370 | /* Note: pitch better be a power of two tile widths */ | |
05394f39 | 2371 | pitch_val = obj->stride / tile_width; |
0f973f27 | 2372 | pitch_val = ffs(pitch_val) - 1; |
de151cf6 | 2373 | |
05394f39 CW |
2374 | val = obj->gtt_offset; |
2375 | if (obj->tiling_mode == I915_TILING_Y) | |
de151cf6 | 2376 | val |= 1 << I830_FENCE_TILING_Y_SHIFT; |
a00b10c3 | 2377 | val |= I915_FENCE_SIZE_BITS(size); |
de151cf6 JB |
2378 | val |= pitch_val << I830_FENCE_PITCH_SHIFT; |
2379 | val |= I830_FENCE_REG_VALID; | |
2380 | ||
05394f39 | 2381 | fence_reg = obj->fence_reg; |
a00b10c3 CW |
2382 | if (fence_reg < 8) |
2383 | fence_reg = FENCE_REG_830_0 + fence_reg * 4; | |
dc529a4f | 2384 | else |
a00b10c3 | 2385 | fence_reg = FENCE_REG_945_8 + (fence_reg - 8) * 4; |
c6642782 DV |
2386 | |
2387 | if (pipelined) { | |
2388 | int ret = intel_ring_begin(pipelined, 4); | |
2389 | if (ret) | |
2390 | return ret; | |
2391 | ||
2392 | intel_ring_emit(pipelined, MI_NOOP); | |
2393 | intel_ring_emit(pipelined, MI_LOAD_REGISTER_IMM(1)); | |
2394 | intel_ring_emit(pipelined, fence_reg); | |
2395 | intel_ring_emit(pipelined, val); | |
2396 | intel_ring_advance(pipelined); | |
2397 | } else | |
2398 | I915_WRITE(fence_reg, val); | |
2399 | ||
2400 | return 0; | |
de151cf6 JB |
2401 | } |
2402 | ||
c6642782 DV |
2403 | static int i830_write_fence_reg(struct drm_i915_gem_object *obj, |
2404 | struct intel_ring_buffer *pipelined) | |
de151cf6 | 2405 | { |
05394f39 | 2406 | struct drm_device *dev = obj->base.dev; |
de151cf6 | 2407 | drm_i915_private_t *dev_priv = dev->dev_private; |
05394f39 CW |
2408 | u32 size = obj->gtt_space->size; |
2409 | int regnum = obj->fence_reg; | |
de151cf6 JB |
2410 | uint32_t val; |
2411 | uint32_t pitch_val; | |
2412 | ||
c6642782 DV |
2413 | if (WARN((obj->gtt_offset & ~I830_FENCE_START_MASK) || |
2414 | (size & -size) != size || | |
2415 | (obj->gtt_offset & (size - 1)), | |
2416 | "object 0x%08x not 512K or pot-size 0x%08x aligned\n", | |
2417 | obj->gtt_offset, size)) | |
2418 | return -EINVAL; | |
de151cf6 | 2419 | |
05394f39 | 2420 | pitch_val = obj->stride / 128; |
e76a16de | 2421 | pitch_val = ffs(pitch_val) - 1; |
e76a16de | 2422 | |
05394f39 CW |
2423 | val = obj->gtt_offset; |
2424 | if (obj->tiling_mode == I915_TILING_Y) | |
de151cf6 | 2425 | val |= 1 << I830_FENCE_TILING_Y_SHIFT; |
c6642782 | 2426 | val |= I830_FENCE_SIZE_BITS(size); |
de151cf6 JB |
2427 | val |= pitch_val << I830_FENCE_PITCH_SHIFT; |
2428 | val |= I830_FENCE_REG_VALID; | |
2429 | ||
c6642782 DV |
2430 | if (pipelined) { |
2431 | int ret = intel_ring_begin(pipelined, 4); | |
2432 | if (ret) | |
2433 | return ret; | |
2434 | ||
2435 | intel_ring_emit(pipelined, MI_NOOP); | |
2436 | intel_ring_emit(pipelined, MI_LOAD_REGISTER_IMM(1)); | |
2437 | intel_ring_emit(pipelined, FENCE_REG_830_0 + regnum*4); | |
2438 | intel_ring_emit(pipelined, val); | |
2439 | intel_ring_advance(pipelined); | |
2440 | } else | |
2441 | I915_WRITE(FENCE_REG_830_0 + regnum * 4, val); | |
2442 | ||
2443 | return 0; | |
de151cf6 JB |
2444 | } |
2445 | ||
d9e86c0e CW |
2446 | static bool ring_passed_seqno(struct intel_ring_buffer *ring, u32 seqno) |
2447 | { | |
2448 | return i915_seqno_passed(ring->get_seqno(ring), seqno); | |
2449 | } | |
2450 | ||
2451 | static int | |
2452 | i915_gem_object_flush_fence(struct drm_i915_gem_object *obj, | |
ce453d81 | 2453 | struct intel_ring_buffer *pipelined) |
d9e86c0e CW |
2454 | { |
2455 | int ret; | |
2456 | ||
2457 | if (obj->fenced_gpu_access) { | |
88241785 | 2458 | if (obj->base.write_domain & I915_GEM_GPU_DOMAINS) { |
db53a302 | 2459 | ret = i915_gem_flush_ring(obj->last_fenced_ring, |
88241785 CW |
2460 | 0, obj->base.write_domain); |
2461 | if (ret) | |
2462 | return ret; | |
2463 | } | |
d9e86c0e CW |
2464 | |
2465 | obj->fenced_gpu_access = false; | |
2466 | } | |
2467 | ||
2468 | if (obj->last_fenced_seqno && pipelined != obj->last_fenced_ring) { | |
2469 | if (!ring_passed_seqno(obj->last_fenced_ring, | |
2470 | obj->last_fenced_seqno)) { | |
db53a302 | 2471 | ret = i915_wait_request(obj->last_fenced_ring, |
ce453d81 | 2472 | obj->last_fenced_seqno); |
d9e86c0e CW |
2473 | if (ret) |
2474 | return ret; | |
2475 | } | |
2476 | ||
2477 | obj->last_fenced_seqno = 0; | |
2478 | obj->last_fenced_ring = NULL; | |
2479 | } | |
2480 | ||
63256ec5 CW |
2481 | /* Ensure that all CPU reads are completed before installing a fence |
2482 | * and all writes before removing the fence. | |
2483 | */ | |
2484 | if (obj->base.read_domains & I915_GEM_DOMAIN_GTT) | |
2485 | mb(); | |
2486 | ||
d9e86c0e CW |
2487 | return 0; |
2488 | } | |
2489 | ||
2490 | int | |
2491 | i915_gem_object_put_fence(struct drm_i915_gem_object *obj) | |
2492 | { | |
2493 | int ret; | |
2494 | ||
2495 | if (obj->tiling_mode) | |
2496 | i915_gem_release_mmap(obj); | |
2497 | ||
ce453d81 | 2498 | ret = i915_gem_object_flush_fence(obj, NULL); |
d9e86c0e CW |
2499 | if (ret) |
2500 | return ret; | |
2501 | ||
2502 | if (obj->fence_reg != I915_FENCE_REG_NONE) { | |
2503 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; | |
2504 | i915_gem_clear_fence_reg(obj->base.dev, | |
2505 | &dev_priv->fence_regs[obj->fence_reg]); | |
2506 | ||
2507 | obj->fence_reg = I915_FENCE_REG_NONE; | |
2508 | } | |
2509 | ||
2510 | return 0; | |
2511 | } | |
2512 | ||
2513 | static struct drm_i915_fence_reg * | |
2514 | i915_find_fence_reg(struct drm_device *dev, | |
2515 | struct intel_ring_buffer *pipelined) | |
ae3db24a | 2516 | { |
ae3db24a | 2517 | struct drm_i915_private *dev_priv = dev->dev_private; |
d9e86c0e CW |
2518 | struct drm_i915_fence_reg *reg, *first, *avail; |
2519 | int i; | |
ae3db24a DV |
2520 | |
2521 | /* First try to find a free reg */ | |
d9e86c0e | 2522 | avail = NULL; |
ae3db24a DV |
2523 | for (i = dev_priv->fence_reg_start; i < dev_priv->num_fence_regs; i++) { |
2524 | reg = &dev_priv->fence_regs[i]; | |
2525 | if (!reg->obj) | |
d9e86c0e | 2526 | return reg; |
ae3db24a | 2527 | |
05394f39 | 2528 | if (!reg->obj->pin_count) |
d9e86c0e | 2529 | avail = reg; |
ae3db24a DV |
2530 | } |
2531 | ||
d9e86c0e CW |
2532 | if (avail == NULL) |
2533 | return NULL; | |
ae3db24a DV |
2534 | |
2535 | /* None available, try to steal one or wait for a user to finish */ | |
d9e86c0e CW |
2536 | avail = first = NULL; |
2537 | list_for_each_entry(reg, &dev_priv->mm.fence_list, lru_list) { | |
2538 | if (reg->obj->pin_count) | |
ae3db24a DV |
2539 | continue; |
2540 | ||
d9e86c0e CW |
2541 | if (first == NULL) |
2542 | first = reg; | |
2543 | ||
2544 | if (!pipelined || | |
2545 | !reg->obj->last_fenced_ring || | |
2546 | reg->obj->last_fenced_ring == pipelined) { | |
2547 | avail = reg; | |
2548 | break; | |
2549 | } | |
ae3db24a DV |
2550 | } |
2551 | ||
d9e86c0e CW |
2552 | if (avail == NULL) |
2553 | avail = first; | |
ae3db24a | 2554 | |
a00b10c3 | 2555 | return avail; |
ae3db24a DV |
2556 | } |
2557 | ||
de151cf6 | 2558 | /** |
d9e86c0e | 2559 | * i915_gem_object_get_fence - set up a fence reg for an object |
de151cf6 | 2560 | * @obj: object to map through a fence reg |
d9e86c0e CW |
2561 | * @pipelined: ring on which to queue the change, or NULL for CPU access |
2562 | * @interruptible: must we wait uninterruptibly for the register to retire? | |
de151cf6 JB |
2563 | * |
2564 | * When mapping objects through the GTT, userspace wants to be able to write | |
2565 | * to them without having to worry about swizzling if the object is tiled. | |
2566 | * | |
2567 | * This function walks the fence regs looking for a free one for @obj, | |
2568 | * stealing one if it can't find any. | |
2569 | * | |
2570 | * It then sets up the reg based on the object's properties: address, pitch | |
2571 | * and tiling format. | |
2572 | */ | |
8c4b8c3f | 2573 | int |
d9e86c0e | 2574 | i915_gem_object_get_fence(struct drm_i915_gem_object *obj, |
ce453d81 | 2575 | struct intel_ring_buffer *pipelined) |
de151cf6 | 2576 | { |
05394f39 | 2577 | struct drm_device *dev = obj->base.dev; |
79e53945 | 2578 | struct drm_i915_private *dev_priv = dev->dev_private; |
d9e86c0e | 2579 | struct drm_i915_fence_reg *reg; |
ae3db24a | 2580 | int ret; |
de151cf6 | 2581 | |
6bda10d1 CW |
2582 | /* XXX disable pipelining. There are bugs. Shocking. */ |
2583 | pipelined = NULL; | |
2584 | ||
d9e86c0e | 2585 | /* Just update our place in the LRU if our fence is getting reused. */ |
05394f39 CW |
2586 | if (obj->fence_reg != I915_FENCE_REG_NONE) { |
2587 | reg = &dev_priv->fence_regs[obj->fence_reg]; | |
007cc8ac | 2588 | list_move_tail(®->lru_list, &dev_priv->mm.fence_list); |
d9e86c0e | 2589 | |
29c5a587 CW |
2590 | if (obj->tiling_changed) { |
2591 | ret = i915_gem_object_flush_fence(obj, pipelined); | |
2592 | if (ret) | |
2593 | return ret; | |
2594 | ||
2595 | if (!obj->fenced_gpu_access && !obj->last_fenced_seqno) | |
2596 | pipelined = NULL; | |
2597 | ||
2598 | if (pipelined) { | |
2599 | reg->setup_seqno = | |
2600 | i915_gem_next_request_seqno(pipelined); | |
2601 | obj->last_fenced_seqno = reg->setup_seqno; | |
2602 | obj->last_fenced_ring = pipelined; | |
2603 | } | |
2604 | ||
2605 | goto update; | |
2606 | } | |
d9e86c0e CW |
2607 | |
2608 | if (!pipelined) { | |
2609 | if (reg->setup_seqno) { | |
2610 | if (!ring_passed_seqno(obj->last_fenced_ring, | |
2611 | reg->setup_seqno)) { | |
db53a302 | 2612 | ret = i915_wait_request(obj->last_fenced_ring, |
ce453d81 | 2613 | reg->setup_seqno); |
d9e86c0e CW |
2614 | if (ret) |
2615 | return ret; | |
2616 | } | |
2617 | ||
2618 | reg->setup_seqno = 0; | |
2619 | } | |
2620 | } else if (obj->last_fenced_ring && | |
2621 | obj->last_fenced_ring != pipelined) { | |
ce453d81 | 2622 | ret = i915_gem_object_flush_fence(obj, pipelined); |
d9e86c0e CW |
2623 | if (ret) |
2624 | return ret; | |
d9e86c0e CW |
2625 | } |
2626 | ||
a09ba7fa EA |
2627 | return 0; |
2628 | } | |
2629 | ||
d9e86c0e CW |
2630 | reg = i915_find_fence_reg(dev, pipelined); |
2631 | if (reg == NULL) | |
2632 | return -ENOSPC; | |
de151cf6 | 2633 | |
ce453d81 | 2634 | ret = i915_gem_object_flush_fence(obj, pipelined); |
d9e86c0e | 2635 | if (ret) |
ae3db24a | 2636 | return ret; |
de151cf6 | 2637 | |
d9e86c0e CW |
2638 | if (reg->obj) { |
2639 | struct drm_i915_gem_object *old = reg->obj; | |
2640 | ||
2641 | drm_gem_object_reference(&old->base); | |
2642 | ||
2643 | if (old->tiling_mode) | |
2644 | i915_gem_release_mmap(old); | |
2645 | ||
ce453d81 | 2646 | ret = i915_gem_object_flush_fence(old, pipelined); |
d9e86c0e CW |
2647 | if (ret) { |
2648 | drm_gem_object_unreference(&old->base); | |
2649 | return ret; | |
2650 | } | |
2651 | ||
2652 | if (old->last_fenced_seqno == 0 && obj->last_fenced_seqno == 0) | |
2653 | pipelined = NULL; | |
2654 | ||
2655 | old->fence_reg = I915_FENCE_REG_NONE; | |
2656 | old->last_fenced_ring = pipelined; | |
2657 | old->last_fenced_seqno = | |
db53a302 | 2658 | pipelined ? i915_gem_next_request_seqno(pipelined) : 0; |
d9e86c0e CW |
2659 | |
2660 | drm_gem_object_unreference(&old->base); | |
2661 | } else if (obj->last_fenced_seqno == 0) | |
2662 | pipelined = NULL; | |
a09ba7fa | 2663 | |
de151cf6 | 2664 | reg->obj = obj; |
d9e86c0e CW |
2665 | list_move_tail(®->lru_list, &dev_priv->mm.fence_list); |
2666 | obj->fence_reg = reg - dev_priv->fence_regs; | |
2667 | obj->last_fenced_ring = pipelined; | |
de151cf6 | 2668 | |
d9e86c0e | 2669 | reg->setup_seqno = |
db53a302 | 2670 | pipelined ? i915_gem_next_request_seqno(pipelined) : 0; |
d9e86c0e CW |
2671 | obj->last_fenced_seqno = reg->setup_seqno; |
2672 | ||
2673 | update: | |
2674 | obj->tiling_changed = false; | |
e259befd CW |
2675 | switch (INTEL_INFO(dev)->gen) { |
2676 | case 6: | |
c6642782 | 2677 | ret = sandybridge_write_fence_reg(obj, pipelined); |
e259befd CW |
2678 | break; |
2679 | case 5: | |
2680 | case 4: | |
c6642782 | 2681 | ret = i965_write_fence_reg(obj, pipelined); |
e259befd CW |
2682 | break; |
2683 | case 3: | |
c6642782 | 2684 | ret = i915_write_fence_reg(obj, pipelined); |
e259befd CW |
2685 | break; |
2686 | case 2: | |
c6642782 | 2687 | ret = i830_write_fence_reg(obj, pipelined); |
e259befd CW |
2688 | break; |
2689 | } | |
d9ddcb96 | 2690 | |
c6642782 | 2691 | return ret; |
de151cf6 JB |
2692 | } |
2693 | ||
2694 | /** | |
2695 | * i915_gem_clear_fence_reg - clear out fence register info | |
2696 | * @obj: object to clear | |
2697 | * | |
2698 | * Zeroes out the fence register itself and clears out the associated | |
05394f39 | 2699 | * data structures in dev_priv and obj. |
de151cf6 JB |
2700 | */ |
2701 | static void | |
d9e86c0e CW |
2702 | i915_gem_clear_fence_reg(struct drm_device *dev, |
2703 | struct drm_i915_fence_reg *reg) | |
de151cf6 | 2704 | { |
79e53945 | 2705 | drm_i915_private_t *dev_priv = dev->dev_private; |
d9e86c0e | 2706 | uint32_t fence_reg = reg - dev_priv->fence_regs; |
de151cf6 | 2707 | |
e259befd CW |
2708 | switch (INTEL_INFO(dev)->gen) { |
2709 | case 6: | |
d9e86c0e | 2710 | I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + fence_reg*8, 0); |
e259befd CW |
2711 | break; |
2712 | case 5: | |
2713 | case 4: | |
d9e86c0e | 2714 | I915_WRITE64(FENCE_REG_965_0 + fence_reg*8, 0); |
e259befd CW |
2715 | break; |
2716 | case 3: | |
d9e86c0e CW |
2717 | if (fence_reg >= 8) |
2718 | fence_reg = FENCE_REG_945_8 + (fence_reg - 8) * 4; | |
dc529a4f | 2719 | else |
e259befd | 2720 | case 2: |
d9e86c0e | 2721 | fence_reg = FENCE_REG_830_0 + fence_reg * 4; |
dc529a4f EA |
2722 | |
2723 | I915_WRITE(fence_reg, 0); | |
e259befd | 2724 | break; |
dc529a4f | 2725 | } |
de151cf6 | 2726 | |
007cc8ac | 2727 | list_del_init(®->lru_list); |
d9e86c0e CW |
2728 | reg->obj = NULL; |
2729 | reg->setup_seqno = 0; | |
52dc7d32 CW |
2730 | } |
2731 | ||
673a394b EA |
2732 | /** |
2733 | * Finds free space in the GTT aperture and binds the object there. | |
2734 | */ | |
2735 | static int | |
05394f39 | 2736 | i915_gem_object_bind_to_gtt(struct drm_i915_gem_object *obj, |
920afa77 | 2737 | unsigned alignment, |
75e9e915 | 2738 | bool map_and_fenceable) |
673a394b | 2739 | { |
05394f39 | 2740 | struct drm_device *dev = obj->base.dev; |
673a394b | 2741 | drm_i915_private_t *dev_priv = dev->dev_private; |
673a394b | 2742 | struct drm_mm_node *free_space; |
a00b10c3 | 2743 | gfp_t gfpmask = __GFP_NORETRY | __GFP_NOWARN; |
5e783301 | 2744 | u32 size, fence_size, fence_alignment, unfenced_alignment; |
75e9e915 | 2745 | bool mappable, fenceable; |
07f73f69 | 2746 | int ret; |
673a394b | 2747 | |
05394f39 | 2748 | if (obj->madv != I915_MADV_WILLNEED) { |
3ef94daa CW |
2749 | DRM_ERROR("Attempting to bind a purgeable object\n"); |
2750 | return -EINVAL; | |
2751 | } | |
2752 | ||
05394f39 CW |
2753 | fence_size = i915_gem_get_gtt_size(obj); |
2754 | fence_alignment = i915_gem_get_gtt_alignment(obj); | |
2755 | unfenced_alignment = i915_gem_get_unfenced_gtt_alignment(obj); | |
a00b10c3 | 2756 | |
673a394b | 2757 | if (alignment == 0) |
5e783301 DV |
2758 | alignment = map_and_fenceable ? fence_alignment : |
2759 | unfenced_alignment; | |
75e9e915 | 2760 | if (map_and_fenceable && alignment & (fence_alignment - 1)) { |
673a394b EA |
2761 | DRM_ERROR("Invalid object alignment requested %u\n", alignment); |
2762 | return -EINVAL; | |
2763 | } | |
2764 | ||
05394f39 | 2765 | size = map_and_fenceable ? fence_size : obj->base.size; |
a00b10c3 | 2766 | |
654fc607 CW |
2767 | /* If the object is bigger than the entire aperture, reject it early |
2768 | * before evicting everything in a vain attempt to find space. | |
2769 | */ | |
05394f39 | 2770 | if (obj->base.size > |
75e9e915 | 2771 | (map_and_fenceable ? dev_priv->mm.gtt_mappable_end : dev_priv->mm.gtt_total)) { |
654fc607 CW |
2772 | DRM_ERROR("Attempting to bind an object larger than the aperture\n"); |
2773 | return -E2BIG; | |
2774 | } | |
2775 | ||
673a394b | 2776 | search_free: |
75e9e915 | 2777 | if (map_and_fenceable) |
920afa77 DV |
2778 | free_space = |
2779 | drm_mm_search_free_in_range(&dev_priv->mm.gtt_space, | |
a00b10c3 | 2780 | size, alignment, 0, |
920afa77 DV |
2781 | dev_priv->mm.gtt_mappable_end, |
2782 | 0); | |
2783 | else | |
2784 | free_space = drm_mm_search_free(&dev_priv->mm.gtt_space, | |
a00b10c3 | 2785 | size, alignment, 0); |
920afa77 DV |
2786 | |
2787 | if (free_space != NULL) { | |
75e9e915 | 2788 | if (map_and_fenceable) |
05394f39 | 2789 | obj->gtt_space = |
920afa77 | 2790 | drm_mm_get_block_range_generic(free_space, |
a00b10c3 | 2791 | size, alignment, 0, |
920afa77 DV |
2792 | dev_priv->mm.gtt_mappable_end, |
2793 | 0); | |
2794 | else | |
05394f39 | 2795 | obj->gtt_space = |
a00b10c3 | 2796 | drm_mm_get_block(free_space, size, alignment); |
920afa77 | 2797 | } |
05394f39 | 2798 | if (obj->gtt_space == NULL) { |
673a394b EA |
2799 | /* If the gtt is empty and we're still having trouble |
2800 | * fitting our object in, we're out of memory. | |
2801 | */ | |
75e9e915 DV |
2802 | ret = i915_gem_evict_something(dev, size, alignment, |
2803 | map_and_fenceable); | |
9731129c | 2804 | if (ret) |
673a394b | 2805 | return ret; |
9731129c | 2806 | |
673a394b EA |
2807 | goto search_free; |
2808 | } | |
2809 | ||
e5281ccd | 2810 | ret = i915_gem_object_get_pages_gtt(obj, gfpmask); |
673a394b | 2811 | if (ret) { |
05394f39 CW |
2812 | drm_mm_put_block(obj->gtt_space); |
2813 | obj->gtt_space = NULL; | |
07f73f69 CW |
2814 | |
2815 | if (ret == -ENOMEM) { | |
809b6334 CW |
2816 | /* first try to reclaim some memory by clearing the GTT */ |
2817 | ret = i915_gem_evict_everything(dev, false); | |
07f73f69 | 2818 | if (ret) { |
07f73f69 | 2819 | /* now try to shrink everyone else */ |
4bdadb97 CW |
2820 | if (gfpmask) { |
2821 | gfpmask = 0; | |
2822 | goto search_free; | |
07f73f69 CW |
2823 | } |
2824 | ||
809b6334 | 2825 | return -ENOMEM; |
07f73f69 CW |
2826 | } |
2827 | ||
2828 | goto search_free; | |
2829 | } | |
2830 | ||
673a394b EA |
2831 | return ret; |
2832 | } | |
2833 | ||
7c2e6fdf DV |
2834 | ret = i915_gem_gtt_bind_object(obj); |
2835 | if (ret) { | |
e5281ccd | 2836 | i915_gem_object_put_pages_gtt(obj); |
05394f39 CW |
2837 | drm_mm_put_block(obj->gtt_space); |
2838 | obj->gtt_space = NULL; | |
07f73f69 | 2839 | |
809b6334 | 2840 | if (i915_gem_evict_everything(dev, false)) |
07f73f69 | 2841 | return ret; |
07f73f69 CW |
2842 | |
2843 | goto search_free; | |
673a394b | 2844 | } |
673a394b | 2845 | |
6299f992 | 2846 | list_add_tail(&obj->gtt_list, &dev_priv->mm.gtt_list); |
05394f39 | 2847 | list_add_tail(&obj->mm_list, &dev_priv->mm.inactive_list); |
bf1a1092 | 2848 | |
673a394b EA |
2849 | /* Assert that the object is not currently in any GPU domain. As it |
2850 | * wasn't in the GTT, there shouldn't be any way it could have been in | |
2851 | * a GPU cache | |
2852 | */ | |
05394f39 CW |
2853 | BUG_ON(obj->base.read_domains & I915_GEM_GPU_DOMAINS); |
2854 | BUG_ON(obj->base.write_domain & I915_GEM_GPU_DOMAINS); | |
673a394b | 2855 | |
6299f992 | 2856 | obj->gtt_offset = obj->gtt_space->start; |
1c5d22f7 | 2857 | |
75e9e915 | 2858 | fenceable = |
05394f39 CW |
2859 | obj->gtt_space->size == fence_size && |
2860 | (obj->gtt_space->start & (fence_alignment -1)) == 0; | |
a00b10c3 | 2861 | |
75e9e915 | 2862 | mappable = |
05394f39 | 2863 | obj->gtt_offset + obj->base.size <= dev_priv->mm.gtt_mappable_end; |
a00b10c3 | 2864 | |
05394f39 | 2865 | obj->map_and_fenceable = mappable && fenceable; |
75e9e915 | 2866 | |
db53a302 | 2867 | trace_i915_gem_object_bind(obj, map_and_fenceable); |
673a394b EA |
2868 | return 0; |
2869 | } | |
2870 | ||
2871 | void | |
05394f39 | 2872 | i915_gem_clflush_object(struct drm_i915_gem_object *obj) |
673a394b | 2873 | { |
673a394b EA |
2874 | /* If we don't have a page list set up, then we're not pinned |
2875 | * to GPU, and we can ignore the cache flush because it'll happen | |
2876 | * again at bind time. | |
2877 | */ | |
05394f39 | 2878 | if (obj->pages == NULL) |
673a394b EA |
2879 | return; |
2880 | ||
9c23f7fc CW |
2881 | /* If the GPU is snooping the contents of the CPU cache, |
2882 | * we do not need to manually clear the CPU cache lines. However, | |
2883 | * the caches are only snooped when the render cache is | |
2884 | * flushed/invalidated. As we always have to emit invalidations | |
2885 | * and flushes when moving into and out of the RENDER domain, correct | |
2886 | * snooping behaviour occurs naturally as the result of our domain | |
2887 | * tracking. | |
2888 | */ | |
2889 | if (obj->cache_level != I915_CACHE_NONE) | |
2890 | return; | |
2891 | ||
1c5d22f7 | 2892 | trace_i915_gem_object_clflush(obj); |
cfa16a0d | 2893 | |
05394f39 | 2894 | drm_clflush_pages(obj->pages, obj->base.size / PAGE_SIZE); |
673a394b EA |
2895 | } |
2896 | ||
e47c68e9 | 2897 | /** Flushes any GPU write domain for the object if it's dirty. */ |
88241785 | 2898 | static int |
3619df03 | 2899 | i915_gem_object_flush_gpu_write_domain(struct drm_i915_gem_object *obj) |
e47c68e9 | 2900 | { |
05394f39 | 2901 | if ((obj->base.write_domain & I915_GEM_GPU_DOMAINS) == 0) |
88241785 | 2902 | return 0; |
e47c68e9 EA |
2903 | |
2904 | /* Queue the GPU write cache flushing we need. */ | |
db53a302 | 2905 | return i915_gem_flush_ring(obj->ring, 0, obj->base.write_domain); |
e47c68e9 EA |
2906 | } |
2907 | ||
2908 | /** Flushes the GTT write domain for the object if it's dirty. */ | |
2909 | static void | |
05394f39 | 2910 | i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj) |
e47c68e9 | 2911 | { |
1c5d22f7 CW |
2912 | uint32_t old_write_domain; |
2913 | ||
05394f39 | 2914 | if (obj->base.write_domain != I915_GEM_DOMAIN_GTT) |
e47c68e9 EA |
2915 | return; |
2916 | ||
63256ec5 | 2917 | /* No actual flushing is required for the GTT write domain. Writes |
e47c68e9 EA |
2918 | * to it immediately go to main memory as far as we know, so there's |
2919 | * no chipset flush. It also doesn't land in render cache. | |
63256ec5 CW |
2920 | * |
2921 | * However, we do have to enforce the order so that all writes through | |
2922 | * the GTT land before any writes to the device, such as updates to | |
2923 | * the GATT itself. | |
e47c68e9 | 2924 | */ |
63256ec5 CW |
2925 | wmb(); |
2926 | ||
4a684a41 CW |
2927 | i915_gem_release_mmap(obj); |
2928 | ||
05394f39 CW |
2929 | old_write_domain = obj->base.write_domain; |
2930 | obj->base.write_domain = 0; | |
1c5d22f7 CW |
2931 | |
2932 | trace_i915_gem_object_change_domain(obj, | |
05394f39 | 2933 | obj->base.read_domains, |
1c5d22f7 | 2934 | old_write_domain); |
e47c68e9 EA |
2935 | } |
2936 | ||
2937 | /** Flushes the CPU write domain for the object if it's dirty. */ | |
2938 | static void | |
05394f39 | 2939 | i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj) |
e47c68e9 | 2940 | { |
1c5d22f7 | 2941 | uint32_t old_write_domain; |
e47c68e9 | 2942 | |
05394f39 | 2943 | if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) |
e47c68e9 EA |
2944 | return; |
2945 | ||
2946 | i915_gem_clflush_object(obj); | |
40ce6575 | 2947 | intel_gtt_chipset_flush(); |
05394f39 CW |
2948 | old_write_domain = obj->base.write_domain; |
2949 | obj->base.write_domain = 0; | |
1c5d22f7 CW |
2950 | |
2951 | trace_i915_gem_object_change_domain(obj, | |
05394f39 | 2952 | obj->base.read_domains, |
1c5d22f7 | 2953 | old_write_domain); |
e47c68e9 EA |
2954 | } |
2955 | ||
2ef7eeaa EA |
2956 | /** |
2957 | * Moves a single object to the GTT read, and possibly write domain. | |
2958 | * | |
2959 | * This function returns when the move is complete, including waiting on | |
2960 | * flushes to occur. | |
2961 | */ | |
79e53945 | 2962 | int |
2021746e | 2963 | i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write) |
2ef7eeaa | 2964 | { |
1c5d22f7 | 2965 | uint32_t old_write_domain, old_read_domains; |
e47c68e9 | 2966 | int ret; |
2ef7eeaa | 2967 | |
02354392 | 2968 | /* Not valid to be called on unbound objects. */ |
05394f39 | 2969 | if (obj->gtt_space == NULL) |
02354392 EA |
2970 | return -EINVAL; |
2971 | ||
8d7e3de1 CW |
2972 | if (obj->base.write_domain == I915_GEM_DOMAIN_GTT) |
2973 | return 0; | |
2974 | ||
88241785 CW |
2975 | ret = i915_gem_object_flush_gpu_write_domain(obj); |
2976 | if (ret) | |
2977 | return ret; | |
2978 | ||
87ca9c8a | 2979 | if (obj->pending_gpu_write || write) { |
ce453d81 | 2980 | ret = i915_gem_object_wait_rendering(obj); |
87ca9c8a CW |
2981 | if (ret) |
2982 | return ret; | |
2983 | } | |
2dafb1e0 | 2984 | |
7213342d | 2985 | i915_gem_object_flush_cpu_write_domain(obj); |
1c5d22f7 | 2986 | |
05394f39 CW |
2987 | old_write_domain = obj->base.write_domain; |
2988 | old_read_domains = obj->base.read_domains; | |
1c5d22f7 | 2989 | |
e47c68e9 EA |
2990 | /* It should now be out of any other write domains, and we can update |
2991 | * the domain values for our changes. | |
2992 | */ | |
05394f39 CW |
2993 | BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_GTT) != 0); |
2994 | obj->base.read_domains |= I915_GEM_DOMAIN_GTT; | |
e47c68e9 | 2995 | if (write) { |
05394f39 CW |
2996 | obj->base.read_domains = I915_GEM_DOMAIN_GTT; |
2997 | obj->base.write_domain = I915_GEM_DOMAIN_GTT; | |
2998 | obj->dirty = 1; | |
2ef7eeaa EA |
2999 | } |
3000 | ||
1c5d22f7 CW |
3001 | trace_i915_gem_object_change_domain(obj, |
3002 | old_read_domains, | |
3003 | old_write_domain); | |
3004 | ||
e47c68e9 EA |
3005 | return 0; |
3006 | } | |
3007 | ||
b9241ea3 ZW |
3008 | /* |
3009 | * Prepare buffer for display plane. Use uninterruptible for possible flush | |
3010 | * wait, as in modesetting process we're not supposed to be interrupted. | |
3011 | */ | |
3012 | int | |
05394f39 | 3013 | i915_gem_object_set_to_display_plane(struct drm_i915_gem_object *obj, |
919926ae | 3014 | struct intel_ring_buffer *pipelined) |
b9241ea3 | 3015 | { |
ba3d8d74 | 3016 | uint32_t old_read_domains; |
b9241ea3 ZW |
3017 | int ret; |
3018 | ||
3019 | /* Not valid to be called on unbound objects. */ | |
05394f39 | 3020 | if (obj->gtt_space == NULL) |
b9241ea3 ZW |
3021 | return -EINVAL; |
3022 | ||
88241785 CW |
3023 | ret = i915_gem_object_flush_gpu_write_domain(obj); |
3024 | if (ret) | |
3025 | return ret; | |
3026 | ||
b9241ea3 | 3027 | |
ced270fa | 3028 | /* Currently, we are always called from an non-interruptible context. */ |
0be73284 | 3029 | if (pipelined != obj->ring) { |
ce453d81 | 3030 | ret = i915_gem_object_wait_rendering(obj); |
ced270fa | 3031 | if (ret) |
b9241ea3 ZW |
3032 | return ret; |
3033 | } | |
3034 | ||
b118c1e3 CW |
3035 | i915_gem_object_flush_cpu_write_domain(obj); |
3036 | ||
05394f39 CW |
3037 | old_read_domains = obj->base.read_domains; |
3038 | obj->base.read_domains |= I915_GEM_DOMAIN_GTT; | |
b9241ea3 ZW |
3039 | |
3040 | trace_i915_gem_object_change_domain(obj, | |
3041 | old_read_domains, | |
05394f39 | 3042 | obj->base.write_domain); |
b9241ea3 ZW |
3043 | |
3044 | return 0; | |
3045 | } | |
3046 | ||
85345517 | 3047 | int |
ce453d81 | 3048 | i915_gem_object_flush_gpu(struct drm_i915_gem_object *obj) |
85345517 | 3049 | { |
88241785 CW |
3050 | int ret; |
3051 | ||
85345517 CW |
3052 | if (!obj->active) |
3053 | return 0; | |
3054 | ||
88241785 | 3055 | if (obj->base.write_domain & I915_GEM_GPU_DOMAINS) { |
db53a302 | 3056 | ret = i915_gem_flush_ring(obj->ring, 0, obj->base.write_domain); |
88241785 CW |
3057 | if (ret) |
3058 | return ret; | |
3059 | } | |
85345517 | 3060 | |
ce453d81 | 3061 | return i915_gem_object_wait_rendering(obj); |
85345517 CW |
3062 | } |
3063 | ||
e47c68e9 EA |
3064 | /** |
3065 | * Moves a single object to the CPU read, and possibly write domain. | |
3066 | * | |
3067 | * This function returns when the move is complete, including waiting on | |
3068 | * flushes to occur. | |
3069 | */ | |
3070 | static int | |
919926ae | 3071 | i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write) |
e47c68e9 | 3072 | { |
1c5d22f7 | 3073 | uint32_t old_write_domain, old_read_domains; |
e47c68e9 EA |
3074 | int ret; |
3075 | ||
8d7e3de1 CW |
3076 | if (obj->base.write_domain == I915_GEM_DOMAIN_CPU) |
3077 | return 0; | |
3078 | ||
88241785 CW |
3079 | ret = i915_gem_object_flush_gpu_write_domain(obj); |
3080 | if (ret) | |
3081 | return ret; | |
3082 | ||
ce453d81 | 3083 | ret = i915_gem_object_wait_rendering(obj); |
de18a29e | 3084 | if (ret) |
e47c68e9 | 3085 | return ret; |
2ef7eeaa | 3086 | |
e47c68e9 | 3087 | i915_gem_object_flush_gtt_write_domain(obj); |
2ef7eeaa | 3088 | |
e47c68e9 EA |
3089 | /* If we have a partially-valid cache of the object in the CPU, |
3090 | * finish invalidating it and free the per-page flags. | |
2ef7eeaa | 3091 | */ |
e47c68e9 | 3092 | i915_gem_object_set_to_full_cpu_read_domain(obj); |
2ef7eeaa | 3093 | |
05394f39 CW |
3094 | old_write_domain = obj->base.write_domain; |
3095 | old_read_domains = obj->base.read_domains; | |
1c5d22f7 | 3096 | |
e47c68e9 | 3097 | /* Flush the CPU cache if it's still invalid. */ |
05394f39 | 3098 | if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0) { |
2ef7eeaa | 3099 | i915_gem_clflush_object(obj); |
2ef7eeaa | 3100 | |
05394f39 | 3101 | obj->base.read_domains |= I915_GEM_DOMAIN_CPU; |
2ef7eeaa EA |
3102 | } |
3103 | ||
3104 | /* It should now be out of any other write domains, and we can update | |
3105 | * the domain values for our changes. | |
3106 | */ | |
05394f39 | 3107 | BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_CPU) != 0); |
e47c68e9 EA |
3108 | |
3109 | /* If we're writing through the CPU, then the GPU read domains will | |
3110 | * need to be invalidated at next use. | |
3111 | */ | |
3112 | if (write) { | |
05394f39 CW |
3113 | obj->base.read_domains = I915_GEM_DOMAIN_CPU; |
3114 | obj->base.write_domain = I915_GEM_DOMAIN_CPU; | |
e47c68e9 | 3115 | } |
2ef7eeaa | 3116 | |
1c5d22f7 CW |
3117 | trace_i915_gem_object_change_domain(obj, |
3118 | old_read_domains, | |
3119 | old_write_domain); | |
3120 | ||
2ef7eeaa EA |
3121 | return 0; |
3122 | } | |
3123 | ||
673a394b | 3124 | /** |
e47c68e9 | 3125 | * Moves the object from a partially CPU read to a full one. |
673a394b | 3126 | * |
e47c68e9 EA |
3127 | * Note that this only resolves i915_gem_object_set_cpu_read_domain_range(), |
3128 | * and doesn't handle transitioning from !(read_domains & I915_GEM_DOMAIN_CPU). | |
673a394b | 3129 | */ |
e47c68e9 | 3130 | static void |
05394f39 | 3131 | i915_gem_object_set_to_full_cpu_read_domain(struct drm_i915_gem_object *obj) |
673a394b | 3132 | { |
05394f39 | 3133 | if (!obj->page_cpu_valid) |
e47c68e9 EA |
3134 | return; |
3135 | ||
3136 | /* If we're partially in the CPU read domain, finish moving it in. | |
3137 | */ | |
05394f39 | 3138 | if (obj->base.read_domains & I915_GEM_DOMAIN_CPU) { |
e47c68e9 EA |
3139 | int i; |
3140 | ||
05394f39 CW |
3141 | for (i = 0; i <= (obj->base.size - 1) / PAGE_SIZE; i++) { |
3142 | if (obj->page_cpu_valid[i]) | |
e47c68e9 | 3143 | continue; |
05394f39 | 3144 | drm_clflush_pages(obj->pages + i, 1); |
e47c68e9 | 3145 | } |
e47c68e9 EA |
3146 | } |
3147 | ||
3148 | /* Free the page_cpu_valid mappings which are now stale, whether | |
3149 | * or not we've got I915_GEM_DOMAIN_CPU. | |
3150 | */ | |
05394f39 CW |
3151 | kfree(obj->page_cpu_valid); |
3152 | obj->page_cpu_valid = NULL; | |
e47c68e9 EA |
3153 | } |
3154 | ||
3155 | /** | |
3156 | * Set the CPU read domain on a range of the object. | |
3157 | * | |
3158 | * The object ends up with I915_GEM_DOMAIN_CPU in its read flags although it's | |
3159 | * not entirely valid. The page_cpu_valid member of the object flags which | |
3160 | * pages have been flushed, and will be respected by | |
3161 | * i915_gem_object_set_to_cpu_domain() if it's called on to get a valid mapping | |
3162 | * of the whole object. | |
3163 | * | |
3164 | * This function returns when the move is complete, including waiting on | |
3165 | * flushes to occur. | |
3166 | */ | |
3167 | static int | |
05394f39 | 3168 | i915_gem_object_set_cpu_read_domain_range(struct drm_i915_gem_object *obj, |
e47c68e9 EA |
3169 | uint64_t offset, uint64_t size) |
3170 | { | |
1c5d22f7 | 3171 | uint32_t old_read_domains; |
e47c68e9 | 3172 | int i, ret; |
673a394b | 3173 | |
05394f39 | 3174 | if (offset == 0 && size == obj->base.size) |
e47c68e9 | 3175 | return i915_gem_object_set_to_cpu_domain(obj, 0); |
673a394b | 3176 | |
88241785 CW |
3177 | ret = i915_gem_object_flush_gpu_write_domain(obj); |
3178 | if (ret) | |
3179 | return ret; | |
3180 | ||
ce453d81 | 3181 | ret = i915_gem_object_wait_rendering(obj); |
de18a29e | 3182 | if (ret) |
6a47baa6 | 3183 | return ret; |
de18a29e | 3184 | |
e47c68e9 EA |
3185 | i915_gem_object_flush_gtt_write_domain(obj); |
3186 | ||
3187 | /* If we're already fully in the CPU read domain, we're done. */ | |
05394f39 CW |
3188 | if (obj->page_cpu_valid == NULL && |
3189 | (obj->base.read_domains & I915_GEM_DOMAIN_CPU) != 0) | |
e47c68e9 | 3190 | return 0; |
673a394b | 3191 | |
e47c68e9 EA |
3192 | /* Otherwise, create/clear the per-page CPU read domain flag if we're |
3193 | * newly adding I915_GEM_DOMAIN_CPU | |
3194 | */ | |
05394f39 CW |
3195 | if (obj->page_cpu_valid == NULL) { |
3196 | obj->page_cpu_valid = kzalloc(obj->base.size / PAGE_SIZE, | |
3197 | GFP_KERNEL); | |
3198 | if (obj->page_cpu_valid == NULL) | |
e47c68e9 | 3199 | return -ENOMEM; |
05394f39 CW |
3200 | } else if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0) |
3201 | memset(obj->page_cpu_valid, 0, obj->base.size / PAGE_SIZE); | |
673a394b EA |
3202 | |
3203 | /* Flush the cache on any pages that are still invalid from the CPU's | |
3204 | * perspective. | |
3205 | */ | |
e47c68e9 EA |
3206 | for (i = offset / PAGE_SIZE; i <= (offset + size - 1) / PAGE_SIZE; |
3207 | i++) { | |
05394f39 | 3208 | if (obj->page_cpu_valid[i]) |
673a394b EA |
3209 | continue; |
3210 | ||
05394f39 | 3211 | drm_clflush_pages(obj->pages + i, 1); |
673a394b | 3212 | |
05394f39 | 3213 | obj->page_cpu_valid[i] = 1; |
673a394b EA |
3214 | } |
3215 | ||
e47c68e9 EA |
3216 | /* It should now be out of any other write domains, and we can update |
3217 | * the domain values for our changes. | |
3218 | */ | |
05394f39 | 3219 | BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_CPU) != 0); |
e47c68e9 | 3220 | |
05394f39 CW |
3221 | old_read_domains = obj->base.read_domains; |
3222 | obj->base.read_domains |= I915_GEM_DOMAIN_CPU; | |
e47c68e9 | 3223 | |
1c5d22f7 CW |
3224 | trace_i915_gem_object_change_domain(obj, |
3225 | old_read_domains, | |
05394f39 | 3226 | obj->base.write_domain); |
1c5d22f7 | 3227 | |
673a394b EA |
3228 | return 0; |
3229 | } | |
3230 | ||
673a394b EA |
3231 | /* Throttle our rendering by waiting until the ring has completed our requests |
3232 | * emitted over 20 msec ago. | |
3233 | * | |
b962442e EA |
3234 | * Note that if we were to use the current jiffies each time around the loop, |
3235 | * we wouldn't escape the function with any frames outstanding if the time to | |
3236 | * render a frame was over 20ms. | |
3237 | * | |
673a394b EA |
3238 | * This should get us reasonable parallelism between CPU and GPU but also |
3239 | * relatively low latency when blocking on a particular request to finish. | |
3240 | */ | |
40a5f0de | 3241 | static int |
f787a5f5 | 3242 | i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file) |
40a5f0de | 3243 | { |
f787a5f5 CW |
3244 | struct drm_i915_private *dev_priv = dev->dev_private; |
3245 | struct drm_i915_file_private *file_priv = file->driver_priv; | |
b962442e | 3246 | unsigned long recent_enough = jiffies - msecs_to_jiffies(20); |
f787a5f5 CW |
3247 | struct drm_i915_gem_request *request; |
3248 | struct intel_ring_buffer *ring = NULL; | |
3249 | u32 seqno = 0; | |
3250 | int ret; | |
93533c29 | 3251 | |
e110e8d6 CW |
3252 | if (atomic_read(&dev_priv->mm.wedged)) |
3253 | return -EIO; | |
3254 | ||
1c25595f | 3255 | spin_lock(&file_priv->mm.lock); |
f787a5f5 | 3256 | list_for_each_entry(request, &file_priv->mm.request_list, client_list) { |
b962442e EA |
3257 | if (time_after_eq(request->emitted_jiffies, recent_enough)) |
3258 | break; | |
40a5f0de | 3259 | |
f787a5f5 CW |
3260 | ring = request->ring; |
3261 | seqno = request->seqno; | |
b962442e | 3262 | } |
1c25595f | 3263 | spin_unlock(&file_priv->mm.lock); |
40a5f0de | 3264 | |
f787a5f5 CW |
3265 | if (seqno == 0) |
3266 | return 0; | |
2bc43b5c | 3267 | |
f787a5f5 | 3268 | ret = 0; |
78501eac | 3269 | if (!i915_seqno_passed(ring->get_seqno(ring), seqno)) { |
f787a5f5 CW |
3270 | /* And wait for the seqno passing without holding any locks and |
3271 | * causing extra latency for others. This is safe as the irq | |
3272 | * generation is designed to be run atomically and so is | |
3273 | * lockless. | |
3274 | */ | |
b13c2b96 CW |
3275 | if (ring->irq_get(ring)) { |
3276 | ret = wait_event_interruptible(ring->irq_queue, | |
3277 | i915_seqno_passed(ring->get_seqno(ring), seqno) | |
3278 | || atomic_read(&dev_priv->mm.wedged)); | |
3279 | ring->irq_put(ring); | |
40a5f0de | 3280 | |
b13c2b96 CW |
3281 | if (ret == 0 && atomic_read(&dev_priv->mm.wedged)) |
3282 | ret = -EIO; | |
3283 | } | |
40a5f0de EA |
3284 | } |
3285 | ||
f787a5f5 CW |
3286 | if (ret == 0) |
3287 | queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, 0); | |
40a5f0de EA |
3288 | |
3289 | return ret; | |
3290 | } | |
3291 | ||
673a394b | 3292 | int |
05394f39 CW |
3293 | i915_gem_object_pin(struct drm_i915_gem_object *obj, |
3294 | uint32_t alignment, | |
75e9e915 | 3295 | bool map_and_fenceable) |
673a394b | 3296 | { |
05394f39 | 3297 | struct drm_device *dev = obj->base.dev; |
f13d3f73 | 3298 | struct drm_i915_private *dev_priv = dev->dev_private; |
673a394b EA |
3299 | int ret; |
3300 | ||
05394f39 | 3301 | BUG_ON(obj->pin_count == DRM_I915_GEM_OBJECT_MAX_PIN_COUNT); |
23bc5982 | 3302 | WARN_ON(i915_verify_lists(dev)); |
ac0c6b5a | 3303 | |
05394f39 CW |
3304 | if (obj->gtt_space != NULL) { |
3305 | if ((alignment && obj->gtt_offset & (alignment - 1)) || | |
3306 | (map_and_fenceable && !obj->map_and_fenceable)) { | |
3307 | WARN(obj->pin_count, | |
ae7d49d8 | 3308 | "bo is already pinned with incorrect alignment:" |
75e9e915 DV |
3309 | " offset=%x, req.alignment=%x, req.map_and_fenceable=%d," |
3310 | " obj->map_and_fenceable=%d\n", | |
05394f39 | 3311 | obj->gtt_offset, alignment, |
75e9e915 | 3312 | map_and_fenceable, |
05394f39 | 3313 | obj->map_and_fenceable); |
ac0c6b5a CW |
3314 | ret = i915_gem_object_unbind(obj); |
3315 | if (ret) | |
3316 | return ret; | |
3317 | } | |
3318 | } | |
3319 | ||
05394f39 | 3320 | if (obj->gtt_space == NULL) { |
a00b10c3 | 3321 | ret = i915_gem_object_bind_to_gtt(obj, alignment, |
75e9e915 | 3322 | map_and_fenceable); |
9731129c | 3323 | if (ret) |
673a394b | 3324 | return ret; |
22c344e9 | 3325 | } |
76446cac | 3326 | |
05394f39 | 3327 | if (obj->pin_count++ == 0) { |
05394f39 CW |
3328 | if (!obj->active) |
3329 | list_move_tail(&obj->mm_list, | |
f13d3f73 | 3330 | &dev_priv->mm.pinned_list); |
673a394b | 3331 | } |
6299f992 | 3332 | obj->pin_mappable |= map_and_fenceable; |
673a394b | 3333 | |
23bc5982 | 3334 | WARN_ON(i915_verify_lists(dev)); |
673a394b EA |
3335 | return 0; |
3336 | } | |
3337 | ||
3338 | void | |
05394f39 | 3339 | i915_gem_object_unpin(struct drm_i915_gem_object *obj) |
673a394b | 3340 | { |
05394f39 | 3341 | struct drm_device *dev = obj->base.dev; |
673a394b | 3342 | drm_i915_private_t *dev_priv = dev->dev_private; |
673a394b | 3343 | |
23bc5982 | 3344 | WARN_ON(i915_verify_lists(dev)); |
05394f39 CW |
3345 | BUG_ON(obj->pin_count == 0); |
3346 | BUG_ON(obj->gtt_space == NULL); | |
673a394b | 3347 | |
05394f39 CW |
3348 | if (--obj->pin_count == 0) { |
3349 | if (!obj->active) | |
3350 | list_move_tail(&obj->mm_list, | |
673a394b | 3351 | &dev_priv->mm.inactive_list); |
6299f992 | 3352 | obj->pin_mappable = false; |
673a394b | 3353 | } |
23bc5982 | 3354 | WARN_ON(i915_verify_lists(dev)); |
673a394b EA |
3355 | } |
3356 | ||
3357 | int | |
3358 | i915_gem_pin_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 3359 | struct drm_file *file) |
673a394b EA |
3360 | { |
3361 | struct drm_i915_gem_pin *args = data; | |
05394f39 | 3362 | struct drm_i915_gem_object *obj; |
673a394b EA |
3363 | int ret; |
3364 | ||
1d7cfea1 CW |
3365 | ret = i915_mutex_lock_interruptible(dev); |
3366 | if (ret) | |
3367 | return ret; | |
673a394b | 3368 | |
05394f39 | 3369 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 3370 | if (&obj->base == NULL) { |
1d7cfea1 CW |
3371 | ret = -ENOENT; |
3372 | goto unlock; | |
673a394b | 3373 | } |
673a394b | 3374 | |
05394f39 | 3375 | if (obj->madv != I915_MADV_WILLNEED) { |
bb6baf76 | 3376 | DRM_ERROR("Attempting to pin a purgeable buffer\n"); |
1d7cfea1 CW |
3377 | ret = -EINVAL; |
3378 | goto out; | |
3ef94daa CW |
3379 | } |
3380 | ||
05394f39 | 3381 | if (obj->pin_filp != NULL && obj->pin_filp != file) { |
79e53945 JB |
3382 | DRM_ERROR("Already pinned in i915_gem_pin_ioctl(): %d\n", |
3383 | args->handle); | |
1d7cfea1 CW |
3384 | ret = -EINVAL; |
3385 | goto out; | |
79e53945 JB |
3386 | } |
3387 | ||
05394f39 CW |
3388 | obj->user_pin_count++; |
3389 | obj->pin_filp = file; | |
3390 | if (obj->user_pin_count == 1) { | |
75e9e915 | 3391 | ret = i915_gem_object_pin(obj, args->alignment, true); |
1d7cfea1 CW |
3392 | if (ret) |
3393 | goto out; | |
673a394b EA |
3394 | } |
3395 | ||
3396 | /* XXX - flush the CPU caches for pinned objects | |
3397 | * as the X server doesn't manage domains yet | |
3398 | */ | |
e47c68e9 | 3399 | i915_gem_object_flush_cpu_write_domain(obj); |
05394f39 | 3400 | args->offset = obj->gtt_offset; |
1d7cfea1 | 3401 | out: |
05394f39 | 3402 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 3403 | unlock: |
673a394b | 3404 | mutex_unlock(&dev->struct_mutex); |
1d7cfea1 | 3405 | return ret; |
673a394b EA |
3406 | } |
3407 | ||
3408 | int | |
3409 | i915_gem_unpin_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 3410 | struct drm_file *file) |
673a394b EA |
3411 | { |
3412 | struct drm_i915_gem_pin *args = data; | |
05394f39 | 3413 | struct drm_i915_gem_object *obj; |
76c1dec1 | 3414 | int ret; |
673a394b | 3415 | |
1d7cfea1 CW |
3416 | ret = i915_mutex_lock_interruptible(dev); |
3417 | if (ret) | |
3418 | return ret; | |
673a394b | 3419 | |
05394f39 | 3420 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 3421 | if (&obj->base == NULL) { |
1d7cfea1 CW |
3422 | ret = -ENOENT; |
3423 | goto unlock; | |
673a394b | 3424 | } |
76c1dec1 | 3425 | |
05394f39 | 3426 | if (obj->pin_filp != file) { |
79e53945 JB |
3427 | DRM_ERROR("Not pinned by caller in i915_gem_pin_ioctl(): %d\n", |
3428 | args->handle); | |
1d7cfea1 CW |
3429 | ret = -EINVAL; |
3430 | goto out; | |
79e53945 | 3431 | } |
05394f39 CW |
3432 | obj->user_pin_count--; |
3433 | if (obj->user_pin_count == 0) { | |
3434 | obj->pin_filp = NULL; | |
79e53945 JB |
3435 | i915_gem_object_unpin(obj); |
3436 | } | |
673a394b | 3437 | |
1d7cfea1 | 3438 | out: |
05394f39 | 3439 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 3440 | unlock: |
673a394b | 3441 | mutex_unlock(&dev->struct_mutex); |
1d7cfea1 | 3442 | return ret; |
673a394b EA |
3443 | } |
3444 | ||
3445 | int | |
3446 | i915_gem_busy_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 3447 | struct drm_file *file) |
673a394b EA |
3448 | { |
3449 | struct drm_i915_gem_busy *args = data; | |
05394f39 | 3450 | struct drm_i915_gem_object *obj; |
30dbf0c0 CW |
3451 | int ret; |
3452 | ||
76c1dec1 | 3453 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 3454 | if (ret) |
76c1dec1 | 3455 | return ret; |
673a394b | 3456 | |
05394f39 | 3457 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 3458 | if (&obj->base == NULL) { |
1d7cfea1 CW |
3459 | ret = -ENOENT; |
3460 | goto unlock; | |
673a394b | 3461 | } |
d1b851fc | 3462 | |
0be555b6 CW |
3463 | /* Count all active objects as busy, even if they are currently not used |
3464 | * by the gpu. Users of this interface expect objects to eventually | |
3465 | * become non-busy without any further actions, therefore emit any | |
3466 | * necessary flushes here. | |
c4de0a5d | 3467 | */ |
05394f39 | 3468 | args->busy = obj->active; |
0be555b6 CW |
3469 | if (args->busy) { |
3470 | /* Unconditionally flush objects, even when the gpu still uses this | |
3471 | * object. Userspace calling this function indicates that it wants to | |
3472 | * use this buffer rather sooner than later, so issuing the required | |
3473 | * flush earlier is beneficial. | |
3474 | */ | |
1a1c6976 | 3475 | if (obj->base.write_domain & I915_GEM_GPU_DOMAINS) { |
db53a302 | 3476 | ret = i915_gem_flush_ring(obj->ring, |
88241785 | 3477 | 0, obj->base.write_domain); |
1a1c6976 CW |
3478 | } else if (obj->ring->outstanding_lazy_request == |
3479 | obj->last_rendering_seqno) { | |
3480 | struct drm_i915_gem_request *request; | |
3481 | ||
7a194876 CW |
3482 | /* This ring is not being cleared by active usage, |
3483 | * so emit a request to do so. | |
3484 | */ | |
1a1c6976 CW |
3485 | request = kzalloc(sizeof(*request), GFP_KERNEL); |
3486 | if (request) | |
db53a302 | 3487 | ret = i915_add_request(obj->ring, NULL,request); |
1a1c6976 | 3488 | else |
7a194876 CW |
3489 | ret = -ENOMEM; |
3490 | } | |
0be555b6 CW |
3491 | |
3492 | /* Update the active list for the hardware's current position. | |
3493 | * Otherwise this only updates on a delayed timer or when irqs | |
3494 | * are actually unmasked, and our working set ends up being | |
3495 | * larger than required. | |
3496 | */ | |
db53a302 | 3497 | i915_gem_retire_requests_ring(obj->ring); |
0be555b6 | 3498 | |
05394f39 | 3499 | args->busy = obj->active; |
0be555b6 | 3500 | } |
673a394b | 3501 | |
05394f39 | 3502 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 3503 | unlock: |
673a394b | 3504 | mutex_unlock(&dev->struct_mutex); |
1d7cfea1 | 3505 | return ret; |
673a394b EA |
3506 | } |
3507 | ||
3508 | int | |
3509 | i915_gem_throttle_ioctl(struct drm_device *dev, void *data, | |
3510 | struct drm_file *file_priv) | |
3511 | { | |
3512 | return i915_gem_ring_throttle(dev, file_priv); | |
3513 | } | |
3514 | ||
3ef94daa CW |
3515 | int |
3516 | i915_gem_madvise_ioctl(struct drm_device *dev, void *data, | |
3517 | struct drm_file *file_priv) | |
3518 | { | |
3519 | struct drm_i915_gem_madvise *args = data; | |
05394f39 | 3520 | struct drm_i915_gem_object *obj; |
76c1dec1 | 3521 | int ret; |
3ef94daa CW |
3522 | |
3523 | switch (args->madv) { | |
3524 | case I915_MADV_DONTNEED: | |
3525 | case I915_MADV_WILLNEED: | |
3526 | break; | |
3527 | default: | |
3528 | return -EINVAL; | |
3529 | } | |
3530 | ||
1d7cfea1 CW |
3531 | ret = i915_mutex_lock_interruptible(dev); |
3532 | if (ret) | |
3533 | return ret; | |
3534 | ||
05394f39 | 3535 | obj = to_intel_bo(drm_gem_object_lookup(dev, file_priv, args->handle)); |
c8725226 | 3536 | if (&obj->base == NULL) { |
1d7cfea1 CW |
3537 | ret = -ENOENT; |
3538 | goto unlock; | |
3ef94daa | 3539 | } |
3ef94daa | 3540 | |
05394f39 | 3541 | if (obj->pin_count) { |
1d7cfea1 CW |
3542 | ret = -EINVAL; |
3543 | goto out; | |
3ef94daa CW |
3544 | } |
3545 | ||
05394f39 CW |
3546 | if (obj->madv != __I915_MADV_PURGED) |
3547 | obj->madv = args->madv; | |
3ef94daa | 3548 | |
2d7ef395 | 3549 | /* if the object is no longer bound, discard its backing storage */ |
05394f39 CW |
3550 | if (i915_gem_object_is_purgeable(obj) && |
3551 | obj->gtt_space == NULL) | |
2d7ef395 CW |
3552 | i915_gem_object_truncate(obj); |
3553 | ||
05394f39 | 3554 | args->retained = obj->madv != __I915_MADV_PURGED; |
bb6baf76 | 3555 | |
1d7cfea1 | 3556 | out: |
05394f39 | 3557 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 3558 | unlock: |
3ef94daa | 3559 | mutex_unlock(&dev->struct_mutex); |
1d7cfea1 | 3560 | return ret; |
3ef94daa CW |
3561 | } |
3562 | ||
05394f39 CW |
3563 | struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev, |
3564 | size_t size) | |
ac52bc56 | 3565 | { |
73aa808f | 3566 | struct drm_i915_private *dev_priv = dev->dev_private; |
c397b908 | 3567 | struct drm_i915_gem_object *obj; |
ac52bc56 | 3568 | |
c397b908 DV |
3569 | obj = kzalloc(sizeof(*obj), GFP_KERNEL); |
3570 | if (obj == NULL) | |
3571 | return NULL; | |
673a394b | 3572 | |
c397b908 DV |
3573 | if (drm_gem_object_init(dev, &obj->base, size) != 0) { |
3574 | kfree(obj); | |
3575 | return NULL; | |
3576 | } | |
673a394b | 3577 | |
73aa808f CW |
3578 | i915_gem_info_add_obj(dev_priv, size); |
3579 | ||
c397b908 DV |
3580 | obj->base.write_domain = I915_GEM_DOMAIN_CPU; |
3581 | obj->base.read_domains = I915_GEM_DOMAIN_CPU; | |
673a394b | 3582 | |
93dfb40c | 3583 | obj->cache_level = I915_CACHE_NONE; |
62b8b215 | 3584 | obj->base.driver_private = NULL; |
c397b908 | 3585 | obj->fence_reg = I915_FENCE_REG_NONE; |
69dc4987 | 3586 | INIT_LIST_HEAD(&obj->mm_list); |
93a37f20 | 3587 | INIT_LIST_HEAD(&obj->gtt_list); |
69dc4987 | 3588 | INIT_LIST_HEAD(&obj->ring_list); |
432e58ed | 3589 | INIT_LIST_HEAD(&obj->exec_list); |
c397b908 | 3590 | INIT_LIST_HEAD(&obj->gpu_write_list); |
c397b908 | 3591 | obj->madv = I915_MADV_WILLNEED; |
75e9e915 DV |
3592 | /* Avoid an unnecessary call to unbind on the first bind. */ |
3593 | obj->map_and_fenceable = true; | |
de151cf6 | 3594 | |
05394f39 | 3595 | return obj; |
c397b908 DV |
3596 | } |
3597 | ||
3598 | int i915_gem_init_object(struct drm_gem_object *obj) | |
3599 | { | |
3600 | BUG(); | |
de151cf6 | 3601 | |
673a394b EA |
3602 | return 0; |
3603 | } | |
3604 | ||
05394f39 | 3605 | static void i915_gem_free_object_tail(struct drm_i915_gem_object *obj) |
673a394b | 3606 | { |
05394f39 | 3607 | struct drm_device *dev = obj->base.dev; |
be72615b | 3608 | drm_i915_private_t *dev_priv = dev->dev_private; |
be72615b | 3609 | int ret; |
673a394b | 3610 | |
be72615b CW |
3611 | ret = i915_gem_object_unbind(obj); |
3612 | if (ret == -ERESTARTSYS) { | |
05394f39 | 3613 | list_move(&obj->mm_list, |
be72615b CW |
3614 | &dev_priv->mm.deferred_free_list); |
3615 | return; | |
3616 | } | |
673a394b | 3617 | |
26e12f89 CW |
3618 | trace_i915_gem_object_destroy(obj); |
3619 | ||
05394f39 | 3620 | if (obj->base.map_list.map) |
7e616158 | 3621 | i915_gem_free_mmap_offset(obj); |
de151cf6 | 3622 | |
05394f39 CW |
3623 | drm_gem_object_release(&obj->base); |
3624 | i915_gem_info_remove_obj(dev_priv, obj->base.size); | |
c397b908 | 3625 | |
05394f39 CW |
3626 | kfree(obj->page_cpu_valid); |
3627 | kfree(obj->bit_17); | |
3628 | kfree(obj); | |
673a394b EA |
3629 | } |
3630 | ||
05394f39 | 3631 | void i915_gem_free_object(struct drm_gem_object *gem_obj) |
be72615b | 3632 | { |
05394f39 CW |
3633 | struct drm_i915_gem_object *obj = to_intel_bo(gem_obj); |
3634 | struct drm_device *dev = obj->base.dev; | |
be72615b | 3635 | |
05394f39 | 3636 | while (obj->pin_count > 0) |
be72615b CW |
3637 | i915_gem_object_unpin(obj); |
3638 | ||
05394f39 | 3639 | if (obj->phys_obj) |
be72615b CW |
3640 | i915_gem_detach_phys_object(dev, obj); |
3641 | ||
3642 | i915_gem_free_object_tail(obj); | |
3643 | } | |
3644 | ||
29105ccc CW |
3645 | int |
3646 | i915_gem_idle(struct drm_device *dev) | |
3647 | { | |
3648 | drm_i915_private_t *dev_priv = dev->dev_private; | |
3649 | int ret; | |
28dfe52a | 3650 | |
29105ccc | 3651 | mutex_lock(&dev->struct_mutex); |
1c5d22f7 | 3652 | |
87acb0a5 | 3653 | if (dev_priv->mm.suspended) { |
29105ccc CW |
3654 | mutex_unlock(&dev->struct_mutex); |
3655 | return 0; | |
28dfe52a EA |
3656 | } |
3657 | ||
29105ccc | 3658 | ret = i915_gpu_idle(dev); |
6dbe2772 KP |
3659 | if (ret) { |
3660 | mutex_unlock(&dev->struct_mutex); | |
673a394b | 3661 | return ret; |
6dbe2772 | 3662 | } |
673a394b | 3663 | |
29105ccc CW |
3664 | /* Under UMS, be paranoid and evict. */ |
3665 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) { | |
5eac3ab4 | 3666 | ret = i915_gem_evict_inactive(dev, false); |
29105ccc CW |
3667 | if (ret) { |
3668 | mutex_unlock(&dev->struct_mutex); | |
3669 | return ret; | |
3670 | } | |
3671 | } | |
3672 | ||
312817a3 CW |
3673 | i915_gem_reset_fences(dev); |
3674 | ||
29105ccc CW |
3675 | /* Hack! Don't let anybody do execbuf while we don't control the chip. |
3676 | * We need to replace this with a semaphore, or something. | |
3677 | * And not confound mm.suspended! | |
3678 | */ | |
3679 | dev_priv->mm.suspended = 1; | |
bc0c7f14 | 3680 | del_timer_sync(&dev_priv->hangcheck_timer); |
29105ccc CW |
3681 | |
3682 | i915_kernel_lost_context(dev); | |
6dbe2772 | 3683 | i915_gem_cleanup_ringbuffer(dev); |
29105ccc | 3684 | |
6dbe2772 KP |
3685 | mutex_unlock(&dev->struct_mutex); |
3686 | ||
29105ccc CW |
3687 | /* Cancel the retire work handler, which should be idle now. */ |
3688 | cancel_delayed_work_sync(&dev_priv->mm.retire_work); | |
3689 | ||
673a394b EA |
3690 | return 0; |
3691 | } | |
3692 | ||
8187a2b7 ZN |
3693 | int |
3694 | i915_gem_init_ringbuffer(struct drm_device *dev) | |
3695 | { | |
3696 | drm_i915_private_t *dev_priv = dev->dev_private; | |
3697 | int ret; | |
68f95ba9 | 3698 | |
5c1143bb | 3699 | ret = intel_init_render_ring_buffer(dev); |
68f95ba9 | 3700 | if (ret) |
b6913e4b | 3701 | return ret; |
68f95ba9 CW |
3702 | |
3703 | if (HAS_BSD(dev)) { | |
5c1143bb | 3704 | ret = intel_init_bsd_ring_buffer(dev); |
68f95ba9 CW |
3705 | if (ret) |
3706 | goto cleanup_render_ring; | |
d1b851fc | 3707 | } |
68f95ba9 | 3708 | |
549f7365 CW |
3709 | if (HAS_BLT(dev)) { |
3710 | ret = intel_init_blt_ring_buffer(dev); | |
3711 | if (ret) | |
3712 | goto cleanup_bsd_ring; | |
3713 | } | |
3714 | ||
6f392d54 CW |
3715 | dev_priv->next_seqno = 1; |
3716 | ||
68f95ba9 CW |
3717 | return 0; |
3718 | ||
549f7365 | 3719 | cleanup_bsd_ring: |
1ec14ad3 | 3720 | intel_cleanup_ring_buffer(&dev_priv->ring[VCS]); |
68f95ba9 | 3721 | cleanup_render_ring: |
1ec14ad3 | 3722 | intel_cleanup_ring_buffer(&dev_priv->ring[RCS]); |
8187a2b7 ZN |
3723 | return ret; |
3724 | } | |
3725 | ||
3726 | void | |
3727 | i915_gem_cleanup_ringbuffer(struct drm_device *dev) | |
3728 | { | |
3729 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1ec14ad3 | 3730 | int i; |
8187a2b7 | 3731 | |
1ec14ad3 CW |
3732 | for (i = 0; i < I915_NUM_RINGS; i++) |
3733 | intel_cleanup_ring_buffer(&dev_priv->ring[i]); | |
8187a2b7 ZN |
3734 | } |
3735 | ||
673a394b EA |
3736 | int |
3737 | i915_gem_entervt_ioctl(struct drm_device *dev, void *data, | |
3738 | struct drm_file *file_priv) | |
3739 | { | |
3740 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1ec14ad3 | 3741 | int ret, i; |
673a394b | 3742 | |
79e53945 JB |
3743 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
3744 | return 0; | |
3745 | ||
ba1234d1 | 3746 | if (atomic_read(&dev_priv->mm.wedged)) { |
673a394b | 3747 | DRM_ERROR("Reenabling wedged hardware, good luck\n"); |
ba1234d1 | 3748 | atomic_set(&dev_priv->mm.wedged, 0); |
673a394b EA |
3749 | } |
3750 | ||
673a394b | 3751 | mutex_lock(&dev->struct_mutex); |
9bb2d6f9 EA |
3752 | dev_priv->mm.suspended = 0; |
3753 | ||
3754 | ret = i915_gem_init_ringbuffer(dev); | |
d816f6ac WF |
3755 | if (ret != 0) { |
3756 | mutex_unlock(&dev->struct_mutex); | |
9bb2d6f9 | 3757 | return ret; |
d816f6ac | 3758 | } |
9bb2d6f9 | 3759 | |
69dc4987 | 3760 | BUG_ON(!list_empty(&dev_priv->mm.active_list)); |
673a394b EA |
3761 | BUG_ON(!list_empty(&dev_priv->mm.flushing_list)); |
3762 | BUG_ON(!list_empty(&dev_priv->mm.inactive_list)); | |
1ec14ad3 CW |
3763 | for (i = 0; i < I915_NUM_RINGS; i++) { |
3764 | BUG_ON(!list_empty(&dev_priv->ring[i].active_list)); | |
3765 | BUG_ON(!list_empty(&dev_priv->ring[i].request_list)); | |
3766 | } | |
673a394b | 3767 | mutex_unlock(&dev->struct_mutex); |
dbb19d30 | 3768 | |
5f35308b CW |
3769 | ret = drm_irq_install(dev); |
3770 | if (ret) | |
3771 | goto cleanup_ringbuffer; | |
dbb19d30 | 3772 | |
673a394b | 3773 | return 0; |
5f35308b CW |
3774 | |
3775 | cleanup_ringbuffer: | |
3776 | mutex_lock(&dev->struct_mutex); | |
3777 | i915_gem_cleanup_ringbuffer(dev); | |
3778 | dev_priv->mm.suspended = 1; | |
3779 | mutex_unlock(&dev->struct_mutex); | |
3780 | ||
3781 | return ret; | |
673a394b EA |
3782 | } |
3783 | ||
3784 | int | |
3785 | i915_gem_leavevt_ioctl(struct drm_device *dev, void *data, | |
3786 | struct drm_file *file_priv) | |
3787 | { | |
79e53945 JB |
3788 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
3789 | return 0; | |
3790 | ||
dbb19d30 | 3791 | drm_irq_uninstall(dev); |
e6890f6f | 3792 | return i915_gem_idle(dev); |
673a394b EA |
3793 | } |
3794 | ||
3795 | void | |
3796 | i915_gem_lastclose(struct drm_device *dev) | |
3797 | { | |
3798 | int ret; | |
673a394b | 3799 | |
e806b495 EA |
3800 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
3801 | return; | |
3802 | ||
6dbe2772 KP |
3803 | ret = i915_gem_idle(dev); |
3804 | if (ret) | |
3805 | DRM_ERROR("failed to idle hardware: %d\n", ret); | |
673a394b EA |
3806 | } |
3807 | ||
64193406 CW |
3808 | static void |
3809 | init_ring_lists(struct intel_ring_buffer *ring) | |
3810 | { | |
3811 | INIT_LIST_HEAD(&ring->active_list); | |
3812 | INIT_LIST_HEAD(&ring->request_list); | |
3813 | INIT_LIST_HEAD(&ring->gpu_write_list); | |
3814 | } | |
3815 | ||
673a394b EA |
3816 | void |
3817 | i915_gem_load(struct drm_device *dev) | |
3818 | { | |
b5aa8a0f | 3819 | int i; |
673a394b EA |
3820 | drm_i915_private_t *dev_priv = dev->dev_private; |
3821 | ||
69dc4987 | 3822 | INIT_LIST_HEAD(&dev_priv->mm.active_list); |
673a394b EA |
3823 | INIT_LIST_HEAD(&dev_priv->mm.flushing_list); |
3824 | INIT_LIST_HEAD(&dev_priv->mm.inactive_list); | |
f13d3f73 | 3825 | INIT_LIST_HEAD(&dev_priv->mm.pinned_list); |
a09ba7fa | 3826 | INIT_LIST_HEAD(&dev_priv->mm.fence_list); |
be72615b | 3827 | INIT_LIST_HEAD(&dev_priv->mm.deferred_free_list); |
93a37f20 | 3828 | INIT_LIST_HEAD(&dev_priv->mm.gtt_list); |
1ec14ad3 CW |
3829 | for (i = 0; i < I915_NUM_RINGS; i++) |
3830 | init_ring_lists(&dev_priv->ring[i]); | |
007cc8ac DV |
3831 | for (i = 0; i < 16; i++) |
3832 | INIT_LIST_HEAD(&dev_priv->fence_regs[i].lru_list); | |
673a394b EA |
3833 | INIT_DELAYED_WORK(&dev_priv->mm.retire_work, |
3834 | i915_gem_retire_work_handler); | |
30dbf0c0 | 3835 | init_completion(&dev_priv->error_completion); |
31169714 | 3836 | |
94400120 DA |
3837 | /* On GEN3 we really need to make sure the ARB C3 LP bit is set */ |
3838 | if (IS_GEN3(dev)) { | |
3839 | u32 tmp = I915_READ(MI_ARB_STATE); | |
3840 | if (!(tmp & MI_ARB_C3_LP_WRITE_ENABLE)) { | |
3841 | /* arb state is a masked write, so set bit + bit in mask */ | |
3842 | tmp = MI_ARB_C3_LP_WRITE_ENABLE | (MI_ARB_C3_LP_WRITE_ENABLE << MI_ARB_MASK_SHIFT); | |
3843 | I915_WRITE(MI_ARB_STATE, tmp); | |
3844 | } | |
3845 | } | |
3846 | ||
72bfa19c CW |
3847 | dev_priv->relative_constants_mode = I915_EXEC_CONSTANTS_REL_GENERAL; |
3848 | ||
de151cf6 | 3849 | /* Old X drivers will take 0-2 for front, back, depth buffers */ |
b397c836 EA |
3850 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) |
3851 | dev_priv->fence_reg_start = 3; | |
de151cf6 | 3852 | |
a6c45cf0 | 3853 | if (INTEL_INFO(dev)->gen >= 4 || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) |
de151cf6 JB |
3854 | dev_priv->num_fence_regs = 16; |
3855 | else | |
3856 | dev_priv->num_fence_regs = 8; | |
3857 | ||
b5aa8a0f | 3858 | /* Initialize fence registers to zero */ |
a6c45cf0 CW |
3859 | switch (INTEL_INFO(dev)->gen) { |
3860 | case 6: | |
3861 | for (i = 0; i < 16; i++) | |
3862 | I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + (i * 8), 0); | |
3863 | break; | |
3864 | case 5: | |
3865 | case 4: | |
b5aa8a0f GH |
3866 | for (i = 0; i < 16; i++) |
3867 | I915_WRITE64(FENCE_REG_965_0 + (i * 8), 0); | |
a6c45cf0 CW |
3868 | break; |
3869 | case 3: | |
b5aa8a0f GH |
3870 | if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) |
3871 | for (i = 0; i < 8; i++) | |
3872 | I915_WRITE(FENCE_REG_945_8 + (i * 4), 0); | |
a6c45cf0 CW |
3873 | case 2: |
3874 | for (i = 0; i < 8; i++) | |
3875 | I915_WRITE(FENCE_REG_830_0 + (i * 4), 0); | |
3876 | break; | |
b5aa8a0f | 3877 | } |
673a394b | 3878 | i915_gem_detect_bit_6_swizzle(dev); |
6b95a207 | 3879 | init_waitqueue_head(&dev_priv->pending_flip_queue); |
17250b71 | 3880 | |
ce453d81 CW |
3881 | dev_priv->mm.interruptible = true; |
3882 | ||
17250b71 CW |
3883 | dev_priv->mm.inactive_shrinker.shrink = i915_gem_inactive_shrink; |
3884 | dev_priv->mm.inactive_shrinker.seeks = DEFAULT_SEEKS; | |
3885 | register_shrinker(&dev_priv->mm.inactive_shrinker); | |
673a394b | 3886 | } |
71acb5eb DA |
3887 | |
3888 | /* | |
3889 | * Create a physically contiguous memory object for this object | |
3890 | * e.g. for cursor + overlay regs | |
3891 | */ | |
995b6762 CW |
3892 | static int i915_gem_init_phys_object(struct drm_device *dev, |
3893 | int id, int size, int align) | |
71acb5eb DA |
3894 | { |
3895 | drm_i915_private_t *dev_priv = dev->dev_private; | |
3896 | struct drm_i915_gem_phys_object *phys_obj; | |
3897 | int ret; | |
3898 | ||
3899 | if (dev_priv->mm.phys_objs[id - 1] || !size) | |
3900 | return 0; | |
3901 | ||
9a298b2a | 3902 | phys_obj = kzalloc(sizeof(struct drm_i915_gem_phys_object), GFP_KERNEL); |
71acb5eb DA |
3903 | if (!phys_obj) |
3904 | return -ENOMEM; | |
3905 | ||
3906 | phys_obj->id = id; | |
3907 | ||
6eeefaf3 | 3908 | phys_obj->handle = drm_pci_alloc(dev, size, align); |
71acb5eb DA |
3909 | if (!phys_obj->handle) { |
3910 | ret = -ENOMEM; | |
3911 | goto kfree_obj; | |
3912 | } | |
3913 | #ifdef CONFIG_X86 | |
3914 | set_memory_wc((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE); | |
3915 | #endif | |
3916 | ||
3917 | dev_priv->mm.phys_objs[id - 1] = phys_obj; | |
3918 | ||
3919 | return 0; | |
3920 | kfree_obj: | |
9a298b2a | 3921 | kfree(phys_obj); |
71acb5eb DA |
3922 | return ret; |
3923 | } | |
3924 | ||
995b6762 | 3925 | static void i915_gem_free_phys_object(struct drm_device *dev, int id) |
71acb5eb DA |
3926 | { |
3927 | drm_i915_private_t *dev_priv = dev->dev_private; | |
3928 | struct drm_i915_gem_phys_object *phys_obj; | |
3929 | ||
3930 | if (!dev_priv->mm.phys_objs[id - 1]) | |
3931 | return; | |
3932 | ||
3933 | phys_obj = dev_priv->mm.phys_objs[id - 1]; | |
3934 | if (phys_obj->cur_obj) { | |
3935 | i915_gem_detach_phys_object(dev, phys_obj->cur_obj); | |
3936 | } | |
3937 | ||
3938 | #ifdef CONFIG_X86 | |
3939 | set_memory_wb((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE); | |
3940 | #endif | |
3941 | drm_pci_free(dev, phys_obj->handle); | |
3942 | kfree(phys_obj); | |
3943 | dev_priv->mm.phys_objs[id - 1] = NULL; | |
3944 | } | |
3945 | ||
3946 | void i915_gem_free_all_phys_object(struct drm_device *dev) | |
3947 | { | |
3948 | int i; | |
3949 | ||
260883c8 | 3950 | for (i = I915_GEM_PHYS_CURSOR_0; i <= I915_MAX_PHYS_OBJECT; i++) |
71acb5eb DA |
3951 | i915_gem_free_phys_object(dev, i); |
3952 | } | |
3953 | ||
3954 | void i915_gem_detach_phys_object(struct drm_device *dev, | |
05394f39 | 3955 | struct drm_i915_gem_object *obj) |
71acb5eb | 3956 | { |
05394f39 | 3957 | struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping; |
e5281ccd | 3958 | char *vaddr; |
71acb5eb | 3959 | int i; |
71acb5eb DA |
3960 | int page_count; |
3961 | ||
05394f39 | 3962 | if (!obj->phys_obj) |
71acb5eb | 3963 | return; |
05394f39 | 3964 | vaddr = obj->phys_obj->handle->vaddr; |
71acb5eb | 3965 | |
05394f39 | 3966 | page_count = obj->base.size / PAGE_SIZE; |
71acb5eb | 3967 | for (i = 0; i < page_count; i++) { |
e5281ccd CW |
3968 | struct page *page = read_cache_page_gfp(mapping, i, |
3969 | GFP_HIGHUSER | __GFP_RECLAIMABLE); | |
3970 | if (!IS_ERR(page)) { | |
3971 | char *dst = kmap_atomic(page); | |
3972 | memcpy(dst, vaddr + i*PAGE_SIZE, PAGE_SIZE); | |
3973 | kunmap_atomic(dst); | |
3974 | ||
3975 | drm_clflush_pages(&page, 1); | |
3976 | ||
3977 | set_page_dirty(page); | |
3978 | mark_page_accessed(page); | |
3979 | page_cache_release(page); | |
3980 | } | |
71acb5eb | 3981 | } |
40ce6575 | 3982 | intel_gtt_chipset_flush(); |
d78b47b9 | 3983 | |
05394f39 CW |
3984 | obj->phys_obj->cur_obj = NULL; |
3985 | obj->phys_obj = NULL; | |
71acb5eb DA |
3986 | } |
3987 | ||
3988 | int | |
3989 | i915_gem_attach_phys_object(struct drm_device *dev, | |
05394f39 | 3990 | struct drm_i915_gem_object *obj, |
6eeefaf3 CW |
3991 | int id, |
3992 | int align) | |
71acb5eb | 3993 | { |
05394f39 | 3994 | struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping; |
71acb5eb | 3995 | drm_i915_private_t *dev_priv = dev->dev_private; |
71acb5eb DA |
3996 | int ret = 0; |
3997 | int page_count; | |
3998 | int i; | |
3999 | ||
4000 | if (id > I915_MAX_PHYS_OBJECT) | |
4001 | return -EINVAL; | |
4002 | ||
05394f39 CW |
4003 | if (obj->phys_obj) { |
4004 | if (obj->phys_obj->id == id) | |
71acb5eb DA |
4005 | return 0; |
4006 | i915_gem_detach_phys_object(dev, obj); | |
4007 | } | |
4008 | ||
71acb5eb DA |
4009 | /* create a new object */ |
4010 | if (!dev_priv->mm.phys_objs[id - 1]) { | |
4011 | ret = i915_gem_init_phys_object(dev, id, | |
05394f39 | 4012 | obj->base.size, align); |
71acb5eb | 4013 | if (ret) { |
05394f39 CW |
4014 | DRM_ERROR("failed to init phys object %d size: %zu\n", |
4015 | id, obj->base.size); | |
e5281ccd | 4016 | return ret; |
71acb5eb DA |
4017 | } |
4018 | } | |
4019 | ||
4020 | /* bind to the object */ | |
05394f39 CW |
4021 | obj->phys_obj = dev_priv->mm.phys_objs[id - 1]; |
4022 | obj->phys_obj->cur_obj = obj; | |
71acb5eb | 4023 | |
05394f39 | 4024 | page_count = obj->base.size / PAGE_SIZE; |
71acb5eb DA |
4025 | |
4026 | for (i = 0; i < page_count; i++) { | |
e5281ccd CW |
4027 | struct page *page; |
4028 | char *dst, *src; | |
4029 | ||
4030 | page = read_cache_page_gfp(mapping, i, | |
4031 | GFP_HIGHUSER | __GFP_RECLAIMABLE); | |
4032 | if (IS_ERR(page)) | |
4033 | return PTR_ERR(page); | |
71acb5eb | 4034 | |
ff75b9bc | 4035 | src = kmap_atomic(page); |
05394f39 | 4036 | dst = obj->phys_obj->handle->vaddr + (i * PAGE_SIZE); |
71acb5eb | 4037 | memcpy(dst, src, PAGE_SIZE); |
3e4d3af5 | 4038 | kunmap_atomic(src); |
71acb5eb | 4039 | |
e5281ccd CW |
4040 | mark_page_accessed(page); |
4041 | page_cache_release(page); | |
4042 | } | |
d78b47b9 | 4043 | |
71acb5eb | 4044 | return 0; |
71acb5eb DA |
4045 | } |
4046 | ||
4047 | static int | |
05394f39 CW |
4048 | i915_gem_phys_pwrite(struct drm_device *dev, |
4049 | struct drm_i915_gem_object *obj, | |
71acb5eb DA |
4050 | struct drm_i915_gem_pwrite *args, |
4051 | struct drm_file *file_priv) | |
4052 | { | |
05394f39 | 4053 | void *vaddr = obj->phys_obj->handle->vaddr + args->offset; |
b47b30cc | 4054 | char __user *user_data = (char __user *) (uintptr_t) args->data_ptr; |
71acb5eb | 4055 | |
b47b30cc CW |
4056 | if (__copy_from_user_inatomic_nocache(vaddr, user_data, args->size)) { |
4057 | unsigned long unwritten; | |
4058 | ||
4059 | /* The physical object once assigned is fixed for the lifetime | |
4060 | * of the obj, so we can safely drop the lock and continue | |
4061 | * to access vaddr. | |
4062 | */ | |
4063 | mutex_unlock(&dev->struct_mutex); | |
4064 | unwritten = copy_from_user(vaddr, user_data, args->size); | |
4065 | mutex_lock(&dev->struct_mutex); | |
4066 | if (unwritten) | |
4067 | return -EFAULT; | |
4068 | } | |
71acb5eb | 4069 | |
40ce6575 | 4070 | intel_gtt_chipset_flush(); |
71acb5eb DA |
4071 | return 0; |
4072 | } | |
b962442e | 4073 | |
f787a5f5 | 4074 | void i915_gem_release(struct drm_device *dev, struct drm_file *file) |
b962442e | 4075 | { |
f787a5f5 | 4076 | struct drm_i915_file_private *file_priv = file->driver_priv; |
b962442e EA |
4077 | |
4078 | /* Clean up our request list when the client is going away, so that | |
4079 | * later retire_requests won't dereference our soon-to-be-gone | |
4080 | * file_priv. | |
4081 | */ | |
1c25595f | 4082 | spin_lock(&file_priv->mm.lock); |
f787a5f5 CW |
4083 | while (!list_empty(&file_priv->mm.request_list)) { |
4084 | struct drm_i915_gem_request *request; | |
4085 | ||
4086 | request = list_first_entry(&file_priv->mm.request_list, | |
4087 | struct drm_i915_gem_request, | |
4088 | client_list); | |
4089 | list_del(&request->client_list); | |
4090 | request->file_priv = NULL; | |
4091 | } | |
1c25595f | 4092 | spin_unlock(&file_priv->mm.lock); |
b962442e | 4093 | } |
31169714 | 4094 | |
1637ef41 CW |
4095 | static int |
4096 | i915_gpu_is_active(struct drm_device *dev) | |
4097 | { | |
4098 | drm_i915_private_t *dev_priv = dev->dev_private; | |
4099 | int lists_empty; | |
4100 | ||
1637ef41 | 4101 | lists_empty = list_empty(&dev_priv->mm.flushing_list) && |
17250b71 | 4102 | list_empty(&dev_priv->mm.active_list); |
1637ef41 CW |
4103 | |
4104 | return !lists_empty; | |
4105 | } | |
4106 | ||
31169714 | 4107 | static int |
17250b71 CW |
4108 | i915_gem_inactive_shrink(struct shrinker *shrinker, |
4109 | int nr_to_scan, | |
4110 | gfp_t gfp_mask) | |
31169714 | 4111 | { |
17250b71 CW |
4112 | struct drm_i915_private *dev_priv = |
4113 | container_of(shrinker, | |
4114 | struct drm_i915_private, | |
4115 | mm.inactive_shrinker); | |
4116 | struct drm_device *dev = dev_priv->dev; | |
4117 | struct drm_i915_gem_object *obj, *next; | |
4118 | int cnt; | |
4119 | ||
4120 | if (!mutex_trylock(&dev->struct_mutex)) | |
bbe2e11a | 4121 | return 0; |
31169714 CW |
4122 | |
4123 | /* "fast-path" to count number of available objects */ | |
4124 | if (nr_to_scan == 0) { | |
17250b71 CW |
4125 | cnt = 0; |
4126 | list_for_each_entry(obj, | |
4127 | &dev_priv->mm.inactive_list, | |
4128 | mm_list) | |
4129 | cnt++; | |
4130 | mutex_unlock(&dev->struct_mutex); | |
4131 | return cnt / 100 * sysctl_vfs_cache_pressure; | |
31169714 CW |
4132 | } |
4133 | ||
1637ef41 | 4134 | rescan: |
31169714 | 4135 | /* first scan for clean buffers */ |
17250b71 | 4136 | i915_gem_retire_requests(dev); |
31169714 | 4137 | |
17250b71 CW |
4138 | list_for_each_entry_safe(obj, next, |
4139 | &dev_priv->mm.inactive_list, | |
4140 | mm_list) { | |
4141 | if (i915_gem_object_is_purgeable(obj)) { | |
2021746e CW |
4142 | if (i915_gem_object_unbind(obj) == 0 && |
4143 | --nr_to_scan == 0) | |
17250b71 | 4144 | break; |
31169714 | 4145 | } |
31169714 CW |
4146 | } |
4147 | ||
4148 | /* second pass, evict/count anything still on the inactive list */ | |
17250b71 CW |
4149 | cnt = 0; |
4150 | list_for_each_entry_safe(obj, next, | |
4151 | &dev_priv->mm.inactive_list, | |
4152 | mm_list) { | |
2021746e CW |
4153 | if (nr_to_scan && |
4154 | i915_gem_object_unbind(obj) == 0) | |
17250b71 | 4155 | nr_to_scan--; |
2021746e | 4156 | else |
17250b71 CW |
4157 | cnt++; |
4158 | } | |
4159 | ||
4160 | if (nr_to_scan && i915_gpu_is_active(dev)) { | |
1637ef41 CW |
4161 | /* |
4162 | * We are desperate for pages, so as a last resort, wait | |
4163 | * for the GPU to finish and discard whatever we can. | |
4164 | * This has a dramatic impact to reduce the number of | |
4165 | * OOM-killer events whilst running the GPU aggressively. | |
4166 | */ | |
17250b71 | 4167 | if (i915_gpu_idle(dev) == 0) |
1637ef41 CW |
4168 | goto rescan; |
4169 | } | |
17250b71 CW |
4170 | mutex_unlock(&dev->struct_mutex); |
4171 | return cnt / 100 * sysctl_vfs_cache_pressure; | |
31169714 | 4172 | } |