Commit | Line | Data |
---|---|---|
673a394b EA |
1 | /* |
2 | * Copyright © 2008 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | * | |
26 | */ | |
27 | ||
28 | #include "drmP.h" | |
29 | #include "drm.h" | |
30 | #include "i915_drm.h" | |
31 | #include "i915_drv.h" | |
1c5d22f7 | 32 | #include "i915_trace.h" |
652c393a | 33 | #include "intel_drv.h" |
5949eac4 | 34 | #include <linux/shmem_fs.h> |
5a0e3ad6 | 35 | #include <linux/slab.h> |
673a394b | 36 | #include <linux/swap.h> |
79e53945 | 37 | #include <linux/pci.h> |
673a394b | 38 | |
88241785 | 39 | static __must_check int i915_gem_object_flush_gpu_write_domain(struct drm_i915_gem_object *obj); |
05394f39 CW |
40 | static void i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj); |
41 | static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj); | |
88241785 CW |
42 | static __must_check int i915_gem_object_bind_to_gtt(struct drm_i915_gem_object *obj, |
43 | unsigned alignment, | |
44 | bool map_and_fenceable); | |
05394f39 CW |
45 | static int i915_gem_phys_pwrite(struct drm_device *dev, |
46 | struct drm_i915_gem_object *obj, | |
71acb5eb | 47 | struct drm_i915_gem_pwrite *args, |
05394f39 | 48 | struct drm_file *file); |
673a394b | 49 | |
61050808 CW |
50 | static void i915_gem_write_fence(struct drm_device *dev, int reg, |
51 | struct drm_i915_gem_object *obj); | |
52 | static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj, | |
53 | struct drm_i915_fence_reg *fence, | |
54 | bool enable); | |
55 | ||
17250b71 | 56 | static int i915_gem_inactive_shrink(struct shrinker *shrinker, |
1495f230 | 57 | struct shrink_control *sc); |
8c59967c | 58 | static void i915_gem_object_truncate(struct drm_i915_gem_object *obj); |
31169714 | 59 | |
61050808 CW |
60 | static inline void i915_gem_object_fence_lost(struct drm_i915_gem_object *obj) |
61 | { | |
62 | if (obj->tiling_mode) | |
63 | i915_gem_release_mmap(obj); | |
64 | ||
65 | /* As we do not have an associated fence register, we will force | |
66 | * a tiling change if we ever need to acquire one. | |
67 | */ | |
5d82e3e6 | 68 | obj->fence_dirty = false; |
61050808 CW |
69 | obj->fence_reg = I915_FENCE_REG_NONE; |
70 | } | |
71 | ||
73aa808f CW |
72 | /* some bookkeeping */ |
73 | static void i915_gem_info_add_obj(struct drm_i915_private *dev_priv, | |
74 | size_t size) | |
75 | { | |
76 | dev_priv->mm.object_count++; | |
77 | dev_priv->mm.object_memory += size; | |
78 | } | |
79 | ||
80 | static void i915_gem_info_remove_obj(struct drm_i915_private *dev_priv, | |
81 | size_t size) | |
82 | { | |
83 | dev_priv->mm.object_count--; | |
84 | dev_priv->mm.object_memory -= size; | |
85 | } | |
86 | ||
21dd3734 CW |
87 | static int |
88 | i915_gem_wait_for_error(struct drm_device *dev) | |
30dbf0c0 CW |
89 | { |
90 | struct drm_i915_private *dev_priv = dev->dev_private; | |
91 | struct completion *x = &dev_priv->error_completion; | |
92 | unsigned long flags; | |
93 | int ret; | |
94 | ||
95 | if (!atomic_read(&dev_priv->mm.wedged)) | |
96 | return 0; | |
97 | ||
98 | ret = wait_for_completion_interruptible(x); | |
99 | if (ret) | |
100 | return ret; | |
101 | ||
21dd3734 CW |
102 | if (atomic_read(&dev_priv->mm.wedged)) { |
103 | /* GPU is hung, bump the completion count to account for | |
104 | * the token we just consumed so that we never hit zero and | |
105 | * end up waiting upon a subsequent completion event that | |
106 | * will never happen. | |
107 | */ | |
108 | spin_lock_irqsave(&x->wait.lock, flags); | |
109 | x->done++; | |
110 | spin_unlock_irqrestore(&x->wait.lock, flags); | |
111 | } | |
112 | return 0; | |
30dbf0c0 CW |
113 | } |
114 | ||
54cf91dc | 115 | int i915_mutex_lock_interruptible(struct drm_device *dev) |
76c1dec1 | 116 | { |
76c1dec1 CW |
117 | int ret; |
118 | ||
21dd3734 | 119 | ret = i915_gem_wait_for_error(dev); |
76c1dec1 CW |
120 | if (ret) |
121 | return ret; | |
122 | ||
123 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
124 | if (ret) | |
125 | return ret; | |
126 | ||
23bc5982 | 127 | WARN_ON(i915_verify_lists(dev)); |
76c1dec1 CW |
128 | return 0; |
129 | } | |
30dbf0c0 | 130 | |
7d1c4804 | 131 | static inline bool |
05394f39 | 132 | i915_gem_object_is_inactive(struct drm_i915_gem_object *obj) |
7d1c4804 | 133 | { |
1b50247a | 134 | return !obj->active; |
7d1c4804 CW |
135 | } |
136 | ||
79e53945 JB |
137 | int |
138 | i915_gem_init_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 139 | struct drm_file *file) |
79e53945 JB |
140 | { |
141 | struct drm_i915_gem_init *args = data; | |
2021746e | 142 | |
7bb6fb8d DV |
143 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
144 | return -ENODEV; | |
145 | ||
2021746e CW |
146 | if (args->gtt_start >= args->gtt_end || |
147 | (args->gtt_end | args->gtt_start) & (PAGE_SIZE - 1)) | |
148 | return -EINVAL; | |
79e53945 | 149 | |
f534bc0b DV |
150 | /* GEM with user mode setting was never supported on ilk and later. */ |
151 | if (INTEL_INFO(dev)->gen >= 5) | |
152 | return -ENODEV; | |
153 | ||
79e53945 | 154 | mutex_lock(&dev->struct_mutex); |
644ec02b DV |
155 | i915_gem_init_global_gtt(dev, args->gtt_start, |
156 | args->gtt_end, args->gtt_end); | |
673a394b EA |
157 | mutex_unlock(&dev->struct_mutex); |
158 | ||
2021746e | 159 | return 0; |
673a394b EA |
160 | } |
161 | ||
5a125c3c EA |
162 | int |
163 | i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 164 | struct drm_file *file) |
5a125c3c | 165 | { |
73aa808f | 166 | struct drm_i915_private *dev_priv = dev->dev_private; |
5a125c3c | 167 | struct drm_i915_gem_get_aperture *args = data; |
6299f992 CW |
168 | struct drm_i915_gem_object *obj; |
169 | size_t pinned; | |
5a125c3c | 170 | |
6299f992 | 171 | pinned = 0; |
73aa808f | 172 | mutex_lock(&dev->struct_mutex); |
1b50247a CW |
173 | list_for_each_entry(obj, &dev_priv->mm.gtt_list, gtt_list) |
174 | if (obj->pin_count) | |
175 | pinned += obj->gtt_space->size; | |
73aa808f | 176 | mutex_unlock(&dev->struct_mutex); |
5a125c3c | 177 | |
6299f992 | 178 | args->aper_size = dev_priv->mm.gtt_total; |
0206e353 | 179 | args->aper_available_size = args->aper_size - pinned; |
6299f992 | 180 | |
5a125c3c EA |
181 | return 0; |
182 | } | |
183 | ||
ff72145b DA |
184 | static int |
185 | i915_gem_create(struct drm_file *file, | |
186 | struct drm_device *dev, | |
187 | uint64_t size, | |
188 | uint32_t *handle_p) | |
673a394b | 189 | { |
05394f39 | 190 | struct drm_i915_gem_object *obj; |
a1a2d1d3 PP |
191 | int ret; |
192 | u32 handle; | |
673a394b | 193 | |
ff72145b | 194 | size = roundup(size, PAGE_SIZE); |
8ffc0246 CW |
195 | if (size == 0) |
196 | return -EINVAL; | |
673a394b EA |
197 | |
198 | /* Allocate the new object */ | |
ff72145b | 199 | obj = i915_gem_alloc_object(dev, size); |
673a394b EA |
200 | if (obj == NULL) |
201 | return -ENOMEM; | |
202 | ||
05394f39 | 203 | ret = drm_gem_handle_create(file, &obj->base, &handle); |
1dfd9754 | 204 | if (ret) { |
05394f39 CW |
205 | drm_gem_object_release(&obj->base); |
206 | i915_gem_info_remove_obj(dev->dev_private, obj->base.size); | |
202f2fef | 207 | kfree(obj); |
673a394b | 208 | return ret; |
1dfd9754 | 209 | } |
673a394b | 210 | |
202f2fef | 211 | /* drop reference from allocate - handle holds it now */ |
05394f39 | 212 | drm_gem_object_unreference(&obj->base); |
202f2fef CW |
213 | trace_i915_gem_object_create(obj); |
214 | ||
ff72145b | 215 | *handle_p = handle; |
673a394b EA |
216 | return 0; |
217 | } | |
218 | ||
ff72145b DA |
219 | int |
220 | i915_gem_dumb_create(struct drm_file *file, | |
221 | struct drm_device *dev, | |
222 | struct drm_mode_create_dumb *args) | |
223 | { | |
224 | /* have to work out size/pitch and return them */ | |
ed0291fd | 225 | args->pitch = ALIGN(args->width * ((args->bpp + 7) / 8), 64); |
ff72145b DA |
226 | args->size = args->pitch * args->height; |
227 | return i915_gem_create(file, dev, | |
228 | args->size, &args->handle); | |
229 | } | |
230 | ||
231 | int i915_gem_dumb_destroy(struct drm_file *file, | |
232 | struct drm_device *dev, | |
233 | uint32_t handle) | |
234 | { | |
235 | return drm_gem_handle_delete(file, handle); | |
236 | } | |
237 | ||
238 | /** | |
239 | * Creates a new mm object and returns a handle to it. | |
240 | */ | |
241 | int | |
242 | i915_gem_create_ioctl(struct drm_device *dev, void *data, | |
243 | struct drm_file *file) | |
244 | { | |
245 | struct drm_i915_gem_create *args = data; | |
63ed2cb2 | 246 | |
ff72145b DA |
247 | return i915_gem_create(file, dev, |
248 | args->size, &args->handle); | |
249 | } | |
250 | ||
05394f39 | 251 | static int i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj) |
280b713b | 252 | { |
05394f39 | 253 | drm_i915_private_t *dev_priv = obj->base.dev->dev_private; |
280b713b EA |
254 | |
255 | return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 && | |
05394f39 | 256 | obj->tiling_mode != I915_TILING_NONE; |
280b713b EA |
257 | } |
258 | ||
8461d226 DV |
259 | static inline int |
260 | __copy_to_user_swizzled(char __user *cpu_vaddr, | |
261 | const char *gpu_vaddr, int gpu_offset, | |
262 | int length) | |
263 | { | |
264 | int ret, cpu_offset = 0; | |
265 | ||
266 | while (length > 0) { | |
267 | int cacheline_end = ALIGN(gpu_offset + 1, 64); | |
268 | int this_length = min(cacheline_end - gpu_offset, length); | |
269 | int swizzled_gpu_offset = gpu_offset ^ 64; | |
270 | ||
271 | ret = __copy_to_user(cpu_vaddr + cpu_offset, | |
272 | gpu_vaddr + swizzled_gpu_offset, | |
273 | this_length); | |
274 | if (ret) | |
275 | return ret + length; | |
276 | ||
277 | cpu_offset += this_length; | |
278 | gpu_offset += this_length; | |
279 | length -= this_length; | |
280 | } | |
281 | ||
282 | return 0; | |
283 | } | |
284 | ||
8c59967c | 285 | static inline int |
4f0c7cfb BW |
286 | __copy_from_user_swizzled(char *gpu_vaddr, int gpu_offset, |
287 | const char __user *cpu_vaddr, | |
8c59967c DV |
288 | int length) |
289 | { | |
290 | int ret, cpu_offset = 0; | |
291 | ||
292 | while (length > 0) { | |
293 | int cacheline_end = ALIGN(gpu_offset + 1, 64); | |
294 | int this_length = min(cacheline_end - gpu_offset, length); | |
295 | int swizzled_gpu_offset = gpu_offset ^ 64; | |
296 | ||
297 | ret = __copy_from_user(gpu_vaddr + swizzled_gpu_offset, | |
298 | cpu_vaddr + cpu_offset, | |
299 | this_length); | |
300 | if (ret) | |
301 | return ret + length; | |
302 | ||
303 | cpu_offset += this_length; | |
304 | gpu_offset += this_length; | |
305 | length -= this_length; | |
306 | } | |
307 | ||
308 | return 0; | |
309 | } | |
310 | ||
d174bd64 DV |
311 | /* Per-page copy function for the shmem pread fastpath. |
312 | * Flushes invalid cachelines before reading the target if | |
313 | * needs_clflush is set. */ | |
eb01459f | 314 | static int |
d174bd64 DV |
315 | shmem_pread_fast(struct page *page, int shmem_page_offset, int page_length, |
316 | char __user *user_data, | |
317 | bool page_do_bit17_swizzling, bool needs_clflush) | |
318 | { | |
319 | char *vaddr; | |
320 | int ret; | |
321 | ||
e7e58eb5 | 322 | if (unlikely(page_do_bit17_swizzling)) |
d174bd64 DV |
323 | return -EINVAL; |
324 | ||
325 | vaddr = kmap_atomic(page); | |
326 | if (needs_clflush) | |
327 | drm_clflush_virt_range(vaddr + shmem_page_offset, | |
328 | page_length); | |
329 | ret = __copy_to_user_inatomic(user_data, | |
330 | vaddr + shmem_page_offset, | |
331 | page_length); | |
332 | kunmap_atomic(vaddr); | |
333 | ||
334 | return ret; | |
335 | } | |
336 | ||
23c18c71 DV |
337 | static void |
338 | shmem_clflush_swizzled_range(char *addr, unsigned long length, | |
339 | bool swizzled) | |
340 | { | |
e7e58eb5 | 341 | if (unlikely(swizzled)) { |
23c18c71 DV |
342 | unsigned long start = (unsigned long) addr; |
343 | unsigned long end = (unsigned long) addr + length; | |
344 | ||
345 | /* For swizzling simply ensure that we always flush both | |
346 | * channels. Lame, but simple and it works. Swizzled | |
347 | * pwrite/pread is far from a hotpath - current userspace | |
348 | * doesn't use it at all. */ | |
349 | start = round_down(start, 128); | |
350 | end = round_up(end, 128); | |
351 | ||
352 | drm_clflush_virt_range((void *)start, end - start); | |
353 | } else { | |
354 | drm_clflush_virt_range(addr, length); | |
355 | } | |
356 | ||
357 | } | |
358 | ||
d174bd64 DV |
359 | /* Only difference to the fast-path function is that this can handle bit17 |
360 | * and uses non-atomic copy and kmap functions. */ | |
361 | static int | |
362 | shmem_pread_slow(struct page *page, int shmem_page_offset, int page_length, | |
363 | char __user *user_data, | |
364 | bool page_do_bit17_swizzling, bool needs_clflush) | |
365 | { | |
366 | char *vaddr; | |
367 | int ret; | |
368 | ||
369 | vaddr = kmap(page); | |
370 | if (needs_clflush) | |
23c18c71 DV |
371 | shmem_clflush_swizzled_range(vaddr + shmem_page_offset, |
372 | page_length, | |
373 | page_do_bit17_swizzling); | |
d174bd64 DV |
374 | |
375 | if (page_do_bit17_swizzling) | |
376 | ret = __copy_to_user_swizzled(user_data, | |
377 | vaddr, shmem_page_offset, | |
378 | page_length); | |
379 | else | |
380 | ret = __copy_to_user(user_data, | |
381 | vaddr + shmem_page_offset, | |
382 | page_length); | |
383 | kunmap(page); | |
384 | ||
385 | return ret; | |
386 | } | |
387 | ||
eb01459f | 388 | static int |
dbf7bff0 DV |
389 | i915_gem_shmem_pread(struct drm_device *dev, |
390 | struct drm_i915_gem_object *obj, | |
391 | struct drm_i915_gem_pread *args, | |
392 | struct drm_file *file) | |
eb01459f | 393 | { |
05394f39 | 394 | struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping; |
8461d226 | 395 | char __user *user_data; |
eb01459f | 396 | ssize_t remain; |
8461d226 | 397 | loff_t offset; |
eb2c0c81 | 398 | int shmem_page_offset, page_length, ret = 0; |
8461d226 | 399 | int obj_do_bit17_swizzling, page_do_bit17_swizzling; |
dbf7bff0 | 400 | int hit_slowpath = 0; |
96d79b52 | 401 | int prefaulted = 0; |
8489731c | 402 | int needs_clflush = 0; |
692a576b | 403 | int release_page; |
eb01459f | 404 | |
8461d226 | 405 | user_data = (char __user *) (uintptr_t) args->data_ptr; |
eb01459f EA |
406 | remain = args->size; |
407 | ||
8461d226 | 408 | obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj); |
eb01459f | 409 | |
8489731c DV |
410 | if (!(obj->base.read_domains & I915_GEM_DOMAIN_CPU)) { |
411 | /* If we're not in the cpu read domain, set ourself into the gtt | |
412 | * read domain and manually flush cachelines (if required). This | |
413 | * optimizes for the case when the gpu will dirty the data | |
414 | * anyway again before the next pread happens. */ | |
415 | if (obj->cache_level == I915_CACHE_NONE) | |
416 | needs_clflush = 1; | |
417 | ret = i915_gem_object_set_to_gtt_domain(obj, false); | |
418 | if (ret) | |
419 | return ret; | |
420 | } | |
eb01459f | 421 | |
8461d226 | 422 | offset = args->offset; |
eb01459f EA |
423 | |
424 | while (remain > 0) { | |
e5281ccd CW |
425 | struct page *page; |
426 | ||
eb01459f EA |
427 | /* Operation in this page |
428 | * | |
eb01459f | 429 | * shmem_page_offset = offset within page in shmem file |
eb01459f EA |
430 | * page_length = bytes to copy for this page |
431 | */ | |
c8cbbb8b | 432 | shmem_page_offset = offset_in_page(offset); |
eb01459f EA |
433 | page_length = remain; |
434 | if ((shmem_page_offset + page_length) > PAGE_SIZE) | |
435 | page_length = PAGE_SIZE - shmem_page_offset; | |
eb01459f | 436 | |
692a576b DV |
437 | if (obj->pages) { |
438 | page = obj->pages[offset >> PAGE_SHIFT]; | |
439 | release_page = 0; | |
440 | } else { | |
441 | page = shmem_read_mapping_page(mapping, offset >> PAGE_SHIFT); | |
442 | if (IS_ERR(page)) { | |
443 | ret = PTR_ERR(page); | |
444 | goto out; | |
445 | } | |
446 | release_page = 1; | |
b65552f0 | 447 | } |
e5281ccd | 448 | |
8461d226 DV |
449 | page_do_bit17_swizzling = obj_do_bit17_swizzling && |
450 | (page_to_phys(page) & (1 << 17)) != 0; | |
451 | ||
d174bd64 DV |
452 | ret = shmem_pread_fast(page, shmem_page_offset, page_length, |
453 | user_data, page_do_bit17_swizzling, | |
454 | needs_clflush); | |
455 | if (ret == 0) | |
456 | goto next_page; | |
dbf7bff0 DV |
457 | |
458 | hit_slowpath = 1; | |
692a576b | 459 | page_cache_get(page); |
dbf7bff0 DV |
460 | mutex_unlock(&dev->struct_mutex); |
461 | ||
96d79b52 | 462 | if (!prefaulted) { |
f56f821f | 463 | ret = fault_in_multipages_writeable(user_data, remain); |
96d79b52 DV |
464 | /* Userspace is tricking us, but we've already clobbered |
465 | * its pages with the prefault and promised to write the | |
466 | * data up to the first fault. Hence ignore any errors | |
467 | * and just continue. */ | |
468 | (void)ret; | |
469 | prefaulted = 1; | |
470 | } | |
eb01459f | 471 | |
d174bd64 DV |
472 | ret = shmem_pread_slow(page, shmem_page_offset, page_length, |
473 | user_data, page_do_bit17_swizzling, | |
474 | needs_clflush); | |
eb01459f | 475 | |
dbf7bff0 | 476 | mutex_lock(&dev->struct_mutex); |
e5281ccd | 477 | page_cache_release(page); |
dbf7bff0 | 478 | next_page: |
e5281ccd | 479 | mark_page_accessed(page); |
692a576b DV |
480 | if (release_page) |
481 | page_cache_release(page); | |
e5281ccd | 482 | |
8461d226 DV |
483 | if (ret) { |
484 | ret = -EFAULT; | |
485 | goto out; | |
486 | } | |
487 | ||
eb01459f | 488 | remain -= page_length; |
8461d226 | 489 | user_data += page_length; |
eb01459f EA |
490 | offset += page_length; |
491 | } | |
492 | ||
4f27b75d | 493 | out: |
dbf7bff0 DV |
494 | if (hit_slowpath) { |
495 | /* Fixup: Kill any reinstated backing storage pages */ | |
496 | if (obj->madv == __I915_MADV_PURGED) | |
497 | i915_gem_object_truncate(obj); | |
498 | } | |
eb01459f EA |
499 | |
500 | return ret; | |
501 | } | |
502 | ||
673a394b EA |
503 | /** |
504 | * Reads data from the object referenced by handle. | |
505 | * | |
506 | * On error, the contents of *data are undefined. | |
507 | */ | |
508 | int | |
509 | i915_gem_pread_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 510 | struct drm_file *file) |
673a394b EA |
511 | { |
512 | struct drm_i915_gem_pread *args = data; | |
05394f39 | 513 | struct drm_i915_gem_object *obj; |
35b62a89 | 514 | int ret = 0; |
673a394b | 515 | |
51311d0a CW |
516 | if (args->size == 0) |
517 | return 0; | |
518 | ||
519 | if (!access_ok(VERIFY_WRITE, | |
520 | (char __user *)(uintptr_t)args->data_ptr, | |
521 | args->size)) | |
522 | return -EFAULT; | |
523 | ||
4f27b75d | 524 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 525 | if (ret) |
4f27b75d | 526 | return ret; |
673a394b | 527 | |
05394f39 | 528 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 529 | if (&obj->base == NULL) { |
1d7cfea1 CW |
530 | ret = -ENOENT; |
531 | goto unlock; | |
4f27b75d | 532 | } |
673a394b | 533 | |
7dcd2499 | 534 | /* Bounds check source. */ |
05394f39 CW |
535 | if (args->offset > obj->base.size || |
536 | args->size > obj->base.size - args->offset) { | |
ce9d419d | 537 | ret = -EINVAL; |
35b62a89 | 538 | goto out; |
ce9d419d CW |
539 | } |
540 | ||
db53a302 CW |
541 | trace_i915_gem_object_pread(obj, args->offset, args->size); |
542 | ||
dbf7bff0 | 543 | ret = i915_gem_shmem_pread(dev, obj, args, file); |
673a394b | 544 | |
35b62a89 | 545 | out: |
05394f39 | 546 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 547 | unlock: |
4f27b75d | 548 | mutex_unlock(&dev->struct_mutex); |
eb01459f | 549 | return ret; |
673a394b EA |
550 | } |
551 | ||
0839ccb8 KP |
552 | /* This is the fast write path which cannot handle |
553 | * page faults in the source data | |
9b7530cc | 554 | */ |
0839ccb8 KP |
555 | |
556 | static inline int | |
557 | fast_user_write(struct io_mapping *mapping, | |
558 | loff_t page_base, int page_offset, | |
559 | char __user *user_data, | |
560 | int length) | |
9b7530cc | 561 | { |
4f0c7cfb BW |
562 | void __iomem *vaddr_atomic; |
563 | void *vaddr; | |
0839ccb8 | 564 | unsigned long unwritten; |
9b7530cc | 565 | |
3e4d3af5 | 566 | vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base); |
4f0c7cfb BW |
567 | /* We can use the cpu mem copy function because this is X86. */ |
568 | vaddr = (void __force*)vaddr_atomic + page_offset; | |
569 | unwritten = __copy_from_user_inatomic_nocache(vaddr, | |
0839ccb8 | 570 | user_data, length); |
3e4d3af5 | 571 | io_mapping_unmap_atomic(vaddr_atomic); |
fbd5a26d | 572 | return unwritten; |
0839ccb8 KP |
573 | } |
574 | ||
3de09aa3 EA |
575 | /** |
576 | * This is the fast pwrite path, where we copy the data directly from the | |
577 | * user into the GTT, uncached. | |
578 | */ | |
673a394b | 579 | static int |
05394f39 CW |
580 | i915_gem_gtt_pwrite_fast(struct drm_device *dev, |
581 | struct drm_i915_gem_object *obj, | |
3de09aa3 | 582 | struct drm_i915_gem_pwrite *args, |
05394f39 | 583 | struct drm_file *file) |
673a394b | 584 | { |
0839ccb8 | 585 | drm_i915_private_t *dev_priv = dev->dev_private; |
673a394b | 586 | ssize_t remain; |
0839ccb8 | 587 | loff_t offset, page_base; |
673a394b | 588 | char __user *user_data; |
935aaa69 DV |
589 | int page_offset, page_length, ret; |
590 | ||
591 | ret = i915_gem_object_pin(obj, 0, true); | |
592 | if (ret) | |
593 | goto out; | |
594 | ||
595 | ret = i915_gem_object_set_to_gtt_domain(obj, true); | |
596 | if (ret) | |
597 | goto out_unpin; | |
598 | ||
599 | ret = i915_gem_object_put_fence(obj); | |
600 | if (ret) | |
601 | goto out_unpin; | |
673a394b EA |
602 | |
603 | user_data = (char __user *) (uintptr_t) args->data_ptr; | |
604 | remain = args->size; | |
673a394b | 605 | |
05394f39 | 606 | offset = obj->gtt_offset + args->offset; |
673a394b EA |
607 | |
608 | while (remain > 0) { | |
609 | /* Operation in this page | |
610 | * | |
0839ccb8 KP |
611 | * page_base = page offset within aperture |
612 | * page_offset = offset within page | |
613 | * page_length = bytes to copy for this page | |
673a394b | 614 | */ |
c8cbbb8b CW |
615 | page_base = offset & PAGE_MASK; |
616 | page_offset = offset_in_page(offset); | |
0839ccb8 KP |
617 | page_length = remain; |
618 | if ((page_offset + remain) > PAGE_SIZE) | |
619 | page_length = PAGE_SIZE - page_offset; | |
620 | ||
0839ccb8 | 621 | /* If we get a fault while copying data, then (presumably) our |
3de09aa3 EA |
622 | * source page isn't available. Return the error and we'll |
623 | * retry in the slow path. | |
0839ccb8 | 624 | */ |
fbd5a26d | 625 | if (fast_user_write(dev_priv->mm.gtt_mapping, page_base, |
935aaa69 DV |
626 | page_offset, user_data, page_length)) { |
627 | ret = -EFAULT; | |
628 | goto out_unpin; | |
629 | } | |
673a394b | 630 | |
0839ccb8 KP |
631 | remain -= page_length; |
632 | user_data += page_length; | |
633 | offset += page_length; | |
673a394b | 634 | } |
673a394b | 635 | |
935aaa69 DV |
636 | out_unpin: |
637 | i915_gem_object_unpin(obj); | |
638 | out: | |
3de09aa3 | 639 | return ret; |
673a394b EA |
640 | } |
641 | ||
d174bd64 DV |
642 | /* Per-page copy function for the shmem pwrite fastpath. |
643 | * Flushes invalid cachelines before writing to the target if | |
644 | * needs_clflush_before is set and flushes out any written cachelines after | |
645 | * writing if needs_clflush is set. */ | |
3043c60c | 646 | static int |
d174bd64 DV |
647 | shmem_pwrite_fast(struct page *page, int shmem_page_offset, int page_length, |
648 | char __user *user_data, | |
649 | bool page_do_bit17_swizzling, | |
650 | bool needs_clflush_before, | |
651 | bool needs_clflush_after) | |
673a394b | 652 | { |
d174bd64 | 653 | char *vaddr; |
673a394b | 654 | int ret; |
3de09aa3 | 655 | |
e7e58eb5 | 656 | if (unlikely(page_do_bit17_swizzling)) |
d174bd64 | 657 | return -EINVAL; |
3de09aa3 | 658 | |
d174bd64 DV |
659 | vaddr = kmap_atomic(page); |
660 | if (needs_clflush_before) | |
661 | drm_clflush_virt_range(vaddr + shmem_page_offset, | |
662 | page_length); | |
663 | ret = __copy_from_user_inatomic_nocache(vaddr + shmem_page_offset, | |
664 | user_data, | |
665 | page_length); | |
666 | if (needs_clflush_after) | |
667 | drm_clflush_virt_range(vaddr + shmem_page_offset, | |
668 | page_length); | |
669 | kunmap_atomic(vaddr); | |
3de09aa3 EA |
670 | |
671 | return ret; | |
672 | } | |
673 | ||
d174bd64 DV |
674 | /* Only difference to the fast-path function is that this can handle bit17 |
675 | * and uses non-atomic copy and kmap functions. */ | |
3043c60c | 676 | static int |
d174bd64 DV |
677 | shmem_pwrite_slow(struct page *page, int shmem_page_offset, int page_length, |
678 | char __user *user_data, | |
679 | bool page_do_bit17_swizzling, | |
680 | bool needs_clflush_before, | |
681 | bool needs_clflush_after) | |
673a394b | 682 | { |
d174bd64 DV |
683 | char *vaddr; |
684 | int ret; | |
e5281ccd | 685 | |
d174bd64 | 686 | vaddr = kmap(page); |
e7e58eb5 | 687 | if (unlikely(needs_clflush_before || page_do_bit17_swizzling)) |
23c18c71 DV |
688 | shmem_clflush_swizzled_range(vaddr + shmem_page_offset, |
689 | page_length, | |
690 | page_do_bit17_swizzling); | |
d174bd64 DV |
691 | if (page_do_bit17_swizzling) |
692 | ret = __copy_from_user_swizzled(vaddr, shmem_page_offset, | |
e5281ccd CW |
693 | user_data, |
694 | page_length); | |
d174bd64 DV |
695 | else |
696 | ret = __copy_from_user(vaddr + shmem_page_offset, | |
697 | user_data, | |
698 | page_length); | |
699 | if (needs_clflush_after) | |
23c18c71 DV |
700 | shmem_clflush_swizzled_range(vaddr + shmem_page_offset, |
701 | page_length, | |
702 | page_do_bit17_swizzling); | |
d174bd64 | 703 | kunmap(page); |
40123c1f | 704 | |
d174bd64 | 705 | return ret; |
40123c1f EA |
706 | } |
707 | ||
40123c1f | 708 | static int |
e244a443 DV |
709 | i915_gem_shmem_pwrite(struct drm_device *dev, |
710 | struct drm_i915_gem_object *obj, | |
711 | struct drm_i915_gem_pwrite *args, | |
712 | struct drm_file *file) | |
40123c1f | 713 | { |
05394f39 | 714 | struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping; |
40123c1f | 715 | ssize_t remain; |
8c59967c DV |
716 | loff_t offset; |
717 | char __user *user_data; | |
eb2c0c81 | 718 | int shmem_page_offset, page_length, ret = 0; |
8c59967c | 719 | int obj_do_bit17_swizzling, page_do_bit17_swizzling; |
e244a443 | 720 | int hit_slowpath = 0; |
58642885 DV |
721 | int needs_clflush_after = 0; |
722 | int needs_clflush_before = 0; | |
692a576b | 723 | int release_page; |
40123c1f | 724 | |
8c59967c | 725 | user_data = (char __user *) (uintptr_t) args->data_ptr; |
40123c1f EA |
726 | remain = args->size; |
727 | ||
8c59967c | 728 | obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj); |
40123c1f | 729 | |
58642885 DV |
730 | if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) { |
731 | /* If we're not in the cpu write domain, set ourself into the gtt | |
732 | * write domain and manually flush cachelines (if required). This | |
733 | * optimizes for the case when the gpu will use the data | |
734 | * right away and we therefore have to clflush anyway. */ | |
735 | if (obj->cache_level == I915_CACHE_NONE) | |
736 | needs_clflush_after = 1; | |
737 | ret = i915_gem_object_set_to_gtt_domain(obj, true); | |
738 | if (ret) | |
739 | return ret; | |
740 | } | |
741 | /* Same trick applies for invalidate partially written cachelines before | |
742 | * writing. */ | |
743 | if (!(obj->base.read_domains & I915_GEM_DOMAIN_CPU) | |
744 | && obj->cache_level == I915_CACHE_NONE) | |
745 | needs_clflush_before = 1; | |
746 | ||
673a394b | 747 | offset = args->offset; |
05394f39 | 748 | obj->dirty = 1; |
673a394b | 749 | |
40123c1f | 750 | while (remain > 0) { |
e5281ccd | 751 | struct page *page; |
58642885 | 752 | int partial_cacheline_write; |
e5281ccd | 753 | |
40123c1f EA |
754 | /* Operation in this page |
755 | * | |
40123c1f | 756 | * shmem_page_offset = offset within page in shmem file |
40123c1f EA |
757 | * page_length = bytes to copy for this page |
758 | */ | |
c8cbbb8b | 759 | shmem_page_offset = offset_in_page(offset); |
40123c1f EA |
760 | |
761 | page_length = remain; | |
762 | if ((shmem_page_offset + page_length) > PAGE_SIZE) | |
763 | page_length = PAGE_SIZE - shmem_page_offset; | |
40123c1f | 764 | |
58642885 DV |
765 | /* If we don't overwrite a cacheline completely we need to be |
766 | * careful to have up-to-date data by first clflushing. Don't | |
767 | * overcomplicate things and flush the entire patch. */ | |
768 | partial_cacheline_write = needs_clflush_before && | |
769 | ((shmem_page_offset | page_length) | |
770 | & (boot_cpu_data.x86_clflush_size - 1)); | |
771 | ||
692a576b DV |
772 | if (obj->pages) { |
773 | page = obj->pages[offset >> PAGE_SHIFT]; | |
774 | release_page = 0; | |
775 | } else { | |
776 | page = shmem_read_mapping_page(mapping, offset >> PAGE_SHIFT); | |
777 | if (IS_ERR(page)) { | |
778 | ret = PTR_ERR(page); | |
779 | goto out; | |
780 | } | |
781 | release_page = 1; | |
e5281ccd CW |
782 | } |
783 | ||
8c59967c DV |
784 | page_do_bit17_swizzling = obj_do_bit17_swizzling && |
785 | (page_to_phys(page) & (1 << 17)) != 0; | |
786 | ||
d174bd64 DV |
787 | ret = shmem_pwrite_fast(page, shmem_page_offset, page_length, |
788 | user_data, page_do_bit17_swizzling, | |
789 | partial_cacheline_write, | |
790 | needs_clflush_after); | |
791 | if (ret == 0) | |
792 | goto next_page; | |
e244a443 DV |
793 | |
794 | hit_slowpath = 1; | |
692a576b | 795 | page_cache_get(page); |
e244a443 DV |
796 | mutex_unlock(&dev->struct_mutex); |
797 | ||
d174bd64 DV |
798 | ret = shmem_pwrite_slow(page, shmem_page_offset, page_length, |
799 | user_data, page_do_bit17_swizzling, | |
800 | partial_cacheline_write, | |
801 | needs_clflush_after); | |
40123c1f | 802 | |
e244a443 | 803 | mutex_lock(&dev->struct_mutex); |
692a576b | 804 | page_cache_release(page); |
e244a443 | 805 | next_page: |
e5281ccd CW |
806 | set_page_dirty(page); |
807 | mark_page_accessed(page); | |
692a576b DV |
808 | if (release_page) |
809 | page_cache_release(page); | |
e5281ccd | 810 | |
8c59967c DV |
811 | if (ret) { |
812 | ret = -EFAULT; | |
813 | goto out; | |
814 | } | |
815 | ||
40123c1f | 816 | remain -= page_length; |
8c59967c | 817 | user_data += page_length; |
40123c1f | 818 | offset += page_length; |
673a394b EA |
819 | } |
820 | ||
fbd5a26d | 821 | out: |
e244a443 DV |
822 | if (hit_slowpath) { |
823 | /* Fixup: Kill any reinstated backing storage pages */ | |
824 | if (obj->madv == __I915_MADV_PURGED) | |
825 | i915_gem_object_truncate(obj); | |
826 | /* and flush dirty cachelines in case the object isn't in the cpu write | |
827 | * domain anymore. */ | |
828 | if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) { | |
829 | i915_gem_clflush_object(obj); | |
830 | intel_gtt_chipset_flush(); | |
831 | } | |
8c59967c | 832 | } |
673a394b | 833 | |
58642885 DV |
834 | if (needs_clflush_after) |
835 | intel_gtt_chipset_flush(); | |
836 | ||
40123c1f | 837 | return ret; |
673a394b EA |
838 | } |
839 | ||
840 | /** | |
841 | * Writes data to the object referenced by handle. | |
842 | * | |
843 | * On error, the contents of the buffer that were to be modified are undefined. | |
844 | */ | |
845 | int | |
846 | i915_gem_pwrite_ioctl(struct drm_device *dev, void *data, | |
fbd5a26d | 847 | struct drm_file *file) |
673a394b EA |
848 | { |
849 | struct drm_i915_gem_pwrite *args = data; | |
05394f39 | 850 | struct drm_i915_gem_object *obj; |
51311d0a CW |
851 | int ret; |
852 | ||
853 | if (args->size == 0) | |
854 | return 0; | |
855 | ||
856 | if (!access_ok(VERIFY_READ, | |
857 | (char __user *)(uintptr_t)args->data_ptr, | |
858 | args->size)) | |
859 | return -EFAULT; | |
860 | ||
f56f821f DV |
861 | ret = fault_in_multipages_readable((char __user *)(uintptr_t)args->data_ptr, |
862 | args->size); | |
51311d0a CW |
863 | if (ret) |
864 | return -EFAULT; | |
673a394b | 865 | |
fbd5a26d | 866 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 867 | if (ret) |
fbd5a26d | 868 | return ret; |
1d7cfea1 | 869 | |
05394f39 | 870 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 871 | if (&obj->base == NULL) { |
1d7cfea1 CW |
872 | ret = -ENOENT; |
873 | goto unlock; | |
fbd5a26d | 874 | } |
673a394b | 875 | |
7dcd2499 | 876 | /* Bounds check destination. */ |
05394f39 CW |
877 | if (args->offset > obj->base.size || |
878 | args->size > obj->base.size - args->offset) { | |
ce9d419d | 879 | ret = -EINVAL; |
35b62a89 | 880 | goto out; |
ce9d419d CW |
881 | } |
882 | ||
db53a302 CW |
883 | trace_i915_gem_object_pwrite(obj, args->offset, args->size); |
884 | ||
935aaa69 | 885 | ret = -EFAULT; |
673a394b EA |
886 | /* We can only do the GTT pwrite on untiled buffers, as otherwise |
887 | * it would end up going through the fenced access, and we'll get | |
888 | * different detiling behavior between reading and writing. | |
889 | * pread/pwrite currently are reading and writing from the CPU | |
890 | * perspective, requiring manual detiling by the client. | |
891 | */ | |
5c0480f2 | 892 | if (obj->phys_obj) { |
fbd5a26d | 893 | ret = i915_gem_phys_pwrite(dev, obj, args, file); |
5c0480f2 DV |
894 | goto out; |
895 | } | |
896 | ||
897 | if (obj->gtt_space && | |
3ae53783 | 898 | obj->cache_level == I915_CACHE_NONE && |
c07496fa | 899 | obj->tiling_mode == I915_TILING_NONE && |
ffc62976 | 900 | obj->map_and_fenceable && |
5c0480f2 | 901 | obj->base.write_domain != I915_GEM_DOMAIN_CPU) { |
fbd5a26d | 902 | ret = i915_gem_gtt_pwrite_fast(dev, obj, args, file); |
935aaa69 DV |
903 | /* Note that the gtt paths might fail with non-page-backed user |
904 | * pointers (e.g. gtt mappings when moving data between | |
905 | * textures). Fallback to the shmem path in that case. */ | |
fbd5a26d | 906 | } |
673a394b | 907 | |
5c0480f2 | 908 | if (ret == -EFAULT) |
935aaa69 | 909 | ret = i915_gem_shmem_pwrite(dev, obj, args, file); |
5c0480f2 | 910 | |
35b62a89 | 911 | out: |
05394f39 | 912 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 913 | unlock: |
fbd5a26d | 914 | mutex_unlock(&dev->struct_mutex); |
673a394b EA |
915 | return ret; |
916 | } | |
917 | ||
918 | /** | |
2ef7eeaa EA |
919 | * Called when user space prepares to use an object with the CPU, either |
920 | * through the mmap ioctl's mapping or a GTT mapping. | |
673a394b EA |
921 | */ |
922 | int | |
923 | i915_gem_set_domain_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 924 | struct drm_file *file) |
673a394b EA |
925 | { |
926 | struct drm_i915_gem_set_domain *args = data; | |
05394f39 | 927 | struct drm_i915_gem_object *obj; |
2ef7eeaa EA |
928 | uint32_t read_domains = args->read_domains; |
929 | uint32_t write_domain = args->write_domain; | |
673a394b EA |
930 | int ret; |
931 | ||
2ef7eeaa | 932 | /* Only handle setting domains to types used by the CPU. */ |
21d509e3 | 933 | if (write_domain & I915_GEM_GPU_DOMAINS) |
2ef7eeaa EA |
934 | return -EINVAL; |
935 | ||
21d509e3 | 936 | if (read_domains & I915_GEM_GPU_DOMAINS) |
2ef7eeaa EA |
937 | return -EINVAL; |
938 | ||
939 | /* Having something in the write domain implies it's in the read | |
940 | * domain, and only that read domain. Enforce that in the request. | |
941 | */ | |
942 | if (write_domain != 0 && read_domains != write_domain) | |
943 | return -EINVAL; | |
944 | ||
76c1dec1 | 945 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 946 | if (ret) |
76c1dec1 | 947 | return ret; |
1d7cfea1 | 948 | |
05394f39 | 949 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 950 | if (&obj->base == NULL) { |
1d7cfea1 CW |
951 | ret = -ENOENT; |
952 | goto unlock; | |
76c1dec1 | 953 | } |
673a394b | 954 | |
2ef7eeaa EA |
955 | if (read_domains & I915_GEM_DOMAIN_GTT) { |
956 | ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0); | |
02354392 EA |
957 | |
958 | /* Silently promote "you're not bound, there was nothing to do" | |
959 | * to success, since the client was just asking us to | |
960 | * make sure everything was done. | |
961 | */ | |
962 | if (ret == -EINVAL) | |
963 | ret = 0; | |
2ef7eeaa | 964 | } else { |
e47c68e9 | 965 | ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0); |
2ef7eeaa EA |
966 | } |
967 | ||
05394f39 | 968 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 969 | unlock: |
673a394b EA |
970 | mutex_unlock(&dev->struct_mutex); |
971 | return ret; | |
972 | } | |
973 | ||
974 | /** | |
975 | * Called when user space has done writes to this buffer | |
976 | */ | |
977 | int | |
978 | i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 979 | struct drm_file *file) |
673a394b EA |
980 | { |
981 | struct drm_i915_gem_sw_finish *args = data; | |
05394f39 | 982 | struct drm_i915_gem_object *obj; |
673a394b EA |
983 | int ret = 0; |
984 | ||
76c1dec1 | 985 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 986 | if (ret) |
76c1dec1 | 987 | return ret; |
1d7cfea1 | 988 | |
05394f39 | 989 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 990 | if (&obj->base == NULL) { |
1d7cfea1 CW |
991 | ret = -ENOENT; |
992 | goto unlock; | |
673a394b EA |
993 | } |
994 | ||
673a394b | 995 | /* Pinned buffers may be scanout, so flush the cache */ |
05394f39 | 996 | if (obj->pin_count) |
e47c68e9 EA |
997 | i915_gem_object_flush_cpu_write_domain(obj); |
998 | ||
05394f39 | 999 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 1000 | unlock: |
673a394b EA |
1001 | mutex_unlock(&dev->struct_mutex); |
1002 | return ret; | |
1003 | } | |
1004 | ||
1005 | /** | |
1006 | * Maps the contents of an object, returning the address it is mapped | |
1007 | * into. | |
1008 | * | |
1009 | * While the mapping holds a reference on the contents of the object, it doesn't | |
1010 | * imply a ref on the object itself. | |
1011 | */ | |
1012 | int | |
1013 | i915_gem_mmap_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 1014 | struct drm_file *file) |
673a394b EA |
1015 | { |
1016 | struct drm_i915_gem_mmap *args = data; | |
1017 | struct drm_gem_object *obj; | |
673a394b EA |
1018 | unsigned long addr; |
1019 | ||
05394f39 | 1020 | obj = drm_gem_object_lookup(dev, file, args->handle); |
673a394b | 1021 | if (obj == NULL) |
bf79cb91 | 1022 | return -ENOENT; |
673a394b | 1023 | |
673a394b EA |
1024 | down_write(¤t->mm->mmap_sem); |
1025 | addr = do_mmap(obj->filp, 0, args->size, | |
1026 | PROT_READ | PROT_WRITE, MAP_SHARED, | |
1027 | args->offset); | |
1028 | up_write(¤t->mm->mmap_sem); | |
bc9025bd | 1029 | drm_gem_object_unreference_unlocked(obj); |
673a394b EA |
1030 | if (IS_ERR((void *)addr)) |
1031 | return addr; | |
1032 | ||
1033 | args->addr_ptr = (uint64_t) addr; | |
1034 | ||
1035 | return 0; | |
1036 | } | |
1037 | ||
de151cf6 JB |
1038 | /** |
1039 | * i915_gem_fault - fault a page into the GTT | |
1040 | * vma: VMA in question | |
1041 | * vmf: fault info | |
1042 | * | |
1043 | * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped | |
1044 | * from userspace. The fault handler takes care of binding the object to | |
1045 | * the GTT (if needed), allocating and programming a fence register (again, | |
1046 | * only if needed based on whether the old reg is still valid or the object | |
1047 | * is tiled) and inserting a new PTE into the faulting process. | |
1048 | * | |
1049 | * Note that the faulting process may involve evicting existing objects | |
1050 | * from the GTT and/or fence registers to make room. So performance may | |
1051 | * suffer if the GTT working set is large or there are few fence registers | |
1052 | * left. | |
1053 | */ | |
1054 | int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf) | |
1055 | { | |
05394f39 CW |
1056 | struct drm_i915_gem_object *obj = to_intel_bo(vma->vm_private_data); |
1057 | struct drm_device *dev = obj->base.dev; | |
7d1c4804 | 1058 | drm_i915_private_t *dev_priv = dev->dev_private; |
de151cf6 JB |
1059 | pgoff_t page_offset; |
1060 | unsigned long pfn; | |
1061 | int ret = 0; | |
0f973f27 | 1062 | bool write = !!(vmf->flags & FAULT_FLAG_WRITE); |
de151cf6 JB |
1063 | |
1064 | /* We don't use vmf->pgoff since that has the fake offset */ | |
1065 | page_offset = ((unsigned long)vmf->virtual_address - vma->vm_start) >> | |
1066 | PAGE_SHIFT; | |
1067 | ||
d9bc7e9f CW |
1068 | ret = i915_mutex_lock_interruptible(dev); |
1069 | if (ret) | |
1070 | goto out; | |
a00b10c3 | 1071 | |
db53a302 CW |
1072 | trace_i915_gem_object_fault(obj, page_offset, true, write); |
1073 | ||
d9bc7e9f | 1074 | /* Now bind it into the GTT if needed */ |
919926ae CW |
1075 | if (!obj->map_and_fenceable) { |
1076 | ret = i915_gem_object_unbind(obj); | |
1077 | if (ret) | |
1078 | goto unlock; | |
a00b10c3 | 1079 | } |
05394f39 | 1080 | if (!obj->gtt_space) { |
75e9e915 | 1081 | ret = i915_gem_object_bind_to_gtt(obj, 0, true); |
c715089f CW |
1082 | if (ret) |
1083 | goto unlock; | |
de151cf6 | 1084 | |
e92d03bf EA |
1085 | ret = i915_gem_object_set_to_gtt_domain(obj, write); |
1086 | if (ret) | |
1087 | goto unlock; | |
1088 | } | |
4a684a41 | 1089 | |
74898d7e DV |
1090 | if (!obj->has_global_gtt_mapping) |
1091 | i915_gem_gtt_bind_object(obj, obj->cache_level); | |
1092 | ||
06d98131 | 1093 | ret = i915_gem_object_get_fence(obj); |
d9e86c0e CW |
1094 | if (ret) |
1095 | goto unlock; | |
de151cf6 | 1096 | |
05394f39 CW |
1097 | if (i915_gem_object_is_inactive(obj)) |
1098 | list_move_tail(&obj->mm_list, &dev_priv->mm.inactive_list); | |
7d1c4804 | 1099 | |
6299f992 CW |
1100 | obj->fault_mappable = true; |
1101 | ||
05394f39 | 1102 | pfn = ((dev->agp->base + obj->gtt_offset) >> PAGE_SHIFT) + |
de151cf6 JB |
1103 | page_offset; |
1104 | ||
1105 | /* Finally, remap it using the new GTT offset */ | |
1106 | ret = vm_insert_pfn(vma, (unsigned long)vmf->virtual_address, pfn); | |
c715089f | 1107 | unlock: |
de151cf6 | 1108 | mutex_unlock(&dev->struct_mutex); |
d9bc7e9f | 1109 | out: |
de151cf6 | 1110 | switch (ret) { |
d9bc7e9f | 1111 | case -EIO: |
045e769a | 1112 | case -EAGAIN: |
d9bc7e9f CW |
1113 | /* Give the error handler a chance to run and move the |
1114 | * objects off the GPU active list. Next time we service the | |
1115 | * fault, we should be able to transition the page into the | |
1116 | * GTT without touching the GPU (and so avoid further | |
1117 | * EIO/EGAIN). If the GPU is wedged, then there is no issue | |
1118 | * with coherency, just lost writes. | |
1119 | */ | |
045e769a | 1120 | set_need_resched(); |
c715089f CW |
1121 | case 0: |
1122 | case -ERESTARTSYS: | |
bed636ab | 1123 | case -EINTR: |
c715089f | 1124 | return VM_FAULT_NOPAGE; |
de151cf6 | 1125 | case -ENOMEM: |
de151cf6 | 1126 | return VM_FAULT_OOM; |
de151cf6 | 1127 | default: |
c715089f | 1128 | return VM_FAULT_SIGBUS; |
de151cf6 JB |
1129 | } |
1130 | } | |
1131 | ||
901782b2 CW |
1132 | /** |
1133 | * i915_gem_release_mmap - remove physical page mappings | |
1134 | * @obj: obj in question | |
1135 | * | |
af901ca1 | 1136 | * Preserve the reservation of the mmapping with the DRM core code, but |
901782b2 CW |
1137 | * relinquish ownership of the pages back to the system. |
1138 | * | |
1139 | * It is vital that we remove the page mapping if we have mapped a tiled | |
1140 | * object through the GTT and then lose the fence register due to | |
1141 | * resource pressure. Similarly if the object has been moved out of the | |
1142 | * aperture, than pages mapped into userspace must be revoked. Removing the | |
1143 | * mapping will then trigger a page fault on the next user access, allowing | |
1144 | * fixup by i915_gem_fault(). | |
1145 | */ | |
d05ca301 | 1146 | void |
05394f39 | 1147 | i915_gem_release_mmap(struct drm_i915_gem_object *obj) |
901782b2 | 1148 | { |
6299f992 CW |
1149 | if (!obj->fault_mappable) |
1150 | return; | |
901782b2 | 1151 | |
f6e47884 CW |
1152 | if (obj->base.dev->dev_mapping) |
1153 | unmap_mapping_range(obj->base.dev->dev_mapping, | |
1154 | (loff_t)obj->base.map_list.hash.key<<PAGE_SHIFT, | |
1155 | obj->base.size, 1); | |
fb7d516a | 1156 | |
6299f992 | 1157 | obj->fault_mappable = false; |
901782b2 CW |
1158 | } |
1159 | ||
92b88aeb | 1160 | static uint32_t |
e28f8711 | 1161 | i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode) |
92b88aeb | 1162 | { |
e28f8711 | 1163 | uint32_t gtt_size; |
92b88aeb CW |
1164 | |
1165 | if (INTEL_INFO(dev)->gen >= 4 || | |
e28f8711 CW |
1166 | tiling_mode == I915_TILING_NONE) |
1167 | return size; | |
92b88aeb CW |
1168 | |
1169 | /* Previous chips need a power-of-two fence region when tiling */ | |
1170 | if (INTEL_INFO(dev)->gen == 3) | |
e28f8711 | 1171 | gtt_size = 1024*1024; |
92b88aeb | 1172 | else |
e28f8711 | 1173 | gtt_size = 512*1024; |
92b88aeb | 1174 | |
e28f8711 CW |
1175 | while (gtt_size < size) |
1176 | gtt_size <<= 1; | |
92b88aeb | 1177 | |
e28f8711 | 1178 | return gtt_size; |
92b88aeb CW |
1179 | } |
1180 | ||
de151cf6 JB |
1181 | /** |
1182 | * i915_gem_get_gtt_alignment - return required GTT alignment for an object | |
1183 | * @obj: object to check | |
1184 | * | |
1185 | * Return the required GTT alignment for an object, taking into account | |
5e783301 | 1186 | * potential fence register mapping. |
de151cf6 JB |
1187 | */ |
1188 | static uint32_t | |
e28f8711 CW |
1189 | i915_gem_get_gtt_alignment(struct drm_device *dev, |
1190 | uint32_t size, | |
1191 | int tiling_mode) | |
de151cf6 | 1192 | { |
de151cf6 JB |
1193 | /* |
1194 | * Minimum alignment is 4k (GTT page size), but might be greater | |
1195 | * if a fence register is needed for the object. | |
1196 | */ | |
a00b10c3 | 1197 | if (INTEL_INFO(dev)->gen >= 4 || |
e28f8711 | 1198 | tiling_mode == I915_TILING_NONE) |
de151cf6 JB |
1199 | return 4096; |
1200 | ||
a00b10c3 CW |
1201 | /* |
1202 | * Previous chips need to be aligned to the size of the smallest | |
1203 | * fence register that can contain the object. | |
1204 | */ | |
e28f8711 | 1205 | return i915_gem_get_gtt_size(dev, size, tiling_mode); |
a00b10c3 CW |
1206 | } |
1207 | ||
5e783301 DV |
1208 | /** |
1209 | * i915_gem_get_unfenced_gtt_alignment - return required GTT alignment for an | |
1210 | * unfenced object | |
e28f8711 CW |
1211 | * @dev: the device |
1212 | * @size: size of the object | |
1213 | * @tiling_mode: tiling mode of the object | |
5e783301 DV |
1214 | * |
1215 | * Return the required GTT alignment for an object, only taking into account | |
1216 | * unfenced tiled surface requirements. | |
1217 | */ | |
467cffba | 1218 | uint32_t |
e28f8711 CW |
1219 | i915_gem_get_unfenced_gtt_alignment(struct drm_device *dev, |
1220 | uint32_t size, | |
1221 | int tiling_mode) | |
5e783301 | 1222 | { |
5e783301 DV |
1223 | /* |
1224 | * Minimum alignment is 4k (GTT page size) for sane hw. | |
1225 | */ | |
1226 | if (INTEL_INFO(dev)->gen >= 4 || IS_G33(dev) || | |
e28f8711 | 1227 | tiling_mode == I915_TILING_NONE) |
5e783301 DV |
1228 | return 4096; |
1229 | ||
e28f8711 CW |
1230 | /* Previous hardware however needs to be aligned to a power-of-two |
1231 | * tile height. The simplest method for determining this is to reuse | |
1232 | * the power-of-tile object size. | |
5e783301 | 1233 | */ |
e28f8711 | 1234 | return i915_gem_get_gtt_size(dev, size, tiling_mode); |
5e783301 DV |
1235 | } |
1236 | ||
de151cf6 | 1237 | int |
ff72145b DA |
1238 | i915_gem_mmap_gtt(struct drm_file *file, |
1239 | struct drm_device *dev, | |
1240 | uint32_t handle, | |
1241 | uint64_t *offset) | |
de151cf6 | 1242 | { |
da761a6e | 1243 | struct drm_i915_private *dev_priv = dev->dev_private; |
05394f39 | 1244 | struct drm_i915_gem_object *obj; |
de151cf6 JB |
1245 | int ret; |
1246 | ||
76c1dec1 | 1247 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 1248 | if (ret) |
76c1dec1 | 1249 | return ret; |
de151cf6 | 1250 | |
ff72145b | 1251 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle)); |
c8725226 | 1252 | if (&obj->base == NULL) { |
1d7cfea1 CW |
1253 | ret = -ENOENT; |
1254 | goto unlock; | |
1255 | } | |
de151cf6 | 1256 | |
05394f39 | 1257 | if (obj->base.size > dev_priv->mm.gtt_mappable_end) { |
da761a6e | 1258 | ret = -E2BIG; |
ff56b0bc | 1259 | goto out; |
da761a6e CW |
1260 | } |
1261 | ||
05394f39 | 1262 | if (obj->madv != I915_MADV_WILLNEED) { |
ab18282d | 1263 | DRM_ERROR("Attempting to mmap a purgeable buffer\n"); |
1d7cfea1 CW |
1264 | ret = -EINVAL; |
1265 | goto out; | |
ab18282d CW |
1266 | } |
1267 | ||
05394f39 | 1268 | if (!obj->base.map_list.map) { |
b464e9a2 | 1269 | ret = drm_gem_create_mmap_offset(&obj->base); |
1d7cfea1 CW |
1270 | if (ret) |
1271 | goto out; | |
de151cf6 JB |
1272 | } |
1273 | ||
ff72145b | 1274 | *offset = (u64)obj->base.map_list.hash.key << PAGE_SHIFT; |
de151cf6 | 1275 | |
1d7cfea1 | 1276 | out: |
05394f39 | 1277 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 1278 | unlock: |
de151cf6 | 1279 | mutex_unlock(&dev->struct_mutex); |
1d7cfea1 | 1280 | return ret; |
de151cf6 JB |
1281 | } |
1282 | ||
ff72145b DA |
1283 | /** |
1284 | * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing | |
1285 | * @dev: DRM device | |
1286 | * @data: GTT mapping ioctl data | |
1287 | * @file: GEM object info | |
1288 | * | |
1289 | * Simply returns the fake offset to userspace so it can mmap it. | |
1290 | * The mmap call will end up in drm_gem_mmap(), which will set things | |
1291 | * up so we can get faults in the handler above. | |
1292 | * | |
1293 | * The fault handler will take care of binding the object into the GTT | |
1294 | * (since it may have been evicted to make room for something), allocating | |
1295 | * a fence register, and mapping the appropriate aperture address into | |
1296 | * userspace. | |
1297 | */ | |
1298 | int | |
1299 | i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data, | |
1300 | struct drm_file *file) | |
1301 | { | |
1302 | struct drm_i915_gem_mmap_gtt *args = data; | |
1303 | ||
ff72145b DA |
1304 | return i915_gem_mmap_gtt(file, dev, args->handle, &args->offset); |
1305 | } | |
1306 | ||
1307 | ||
e5281ccd | 1308 | static int |
05394f39 | 1309 | i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj, |
e5281ccd CW |
1310 | gfp_t gfpmask) |
1311 | { | |
e5281ccd CW |
1312 | int page_count, i; |
1313 | struct address_space *mapping; | |
1314 | struct inode *inode; | |
1315 | struct page *page; | |
1316 | ||
1317 | /* Get the list of pages out of our struct file. They'll be pinned | |
1318 | * at this point until we release them. | |
1319 | */ | |
05394f39 CW |
1320 | page_count = obj->base.size / PAGE_SIZE; |
1321 | BUG_ON(obj->pages != NULL); | |
1322 | obj->pages = drm_malloc_ab(page_count, sizeof(struct page *)); | |
1323 | if (obj->pages == NULL) | |
e5281ccd CW |
1324 | return -ENOMEM; |
1325 | ||
05394f39 | 1326 | inode = obj->base.filp->f_path.dentry->d_inode; |
e5281ccd | 1327 | mapping = inode->i_mapping; |
5949eac4 HD |
1328 | gfpmask |= mapping_gfp_mask(mapping); |
1329 | ||
e5281ccd | 1330 | for (i = 0; i < page_count; i++) { |
5949eac4 | 1331 | page = shmem_read_mapping_page_gfp(mapping, i, gfpmask); |
e5281ccd CW |
1332 | if (IS_ERR(page)) |
1333 | goto err_pages; | |
1334 | ||
05394f39 | 1335 | obj->pages[i] = page; |
e5281ccd CW |
1336 | } |
1337 | ||
6dacfd2f | 1338 | if (i915_gem_object_needs_bit17_swizzle(obj)) |
e5281ccd CW |
1339 | i915_gem_object_do_bit_17_swizzle(obj); |
1340 | ||
1341 | return 0; | |
1342 | ||
1343 | err_pages: | |
1344 | while (i--) | |
05394f39 | 1345 | page_cache_release(obj->pages[i]); |
e5281ccd | 1346 | |
05394f39 CW |
1347 | drm_free_large(obj->pages); |
1348 | obj->pages = NULL; | |
e5281ccd CW |
1349 | return PTR_ERR(page); |
1350 | } | |
1351 | ||
5cdf5881 | 1352 | static void |
05394f39 | 1353 | i915_gem_object_put_pages_gtt(struct drm_i915_gem_object *obj) |
673a394b | 1354 | { |
05394f39 | 1355 | int page_count = obj->base.size / PAGE_SIZE; |
673a394b EA |
1356 | int i; |
1357 | ||
05394f39 | 1358 | BUG_ON(obj->madv == __I915_MADV_PURGED); |
673a394b | 1359 | |
6dacfd2f | 1360 | if (i915_gem_object_needs_bit17_swizzle(obj)) |
280b713b EA |
1361 | i915_gem_object_save_bit_17_swizzle(obj); |
1362 | ||
05394f39 CW |
1363 | if (obj->madv == I915_MADV_DONTNEED) |
1364 | obj->dirty = 0; | |
3ef94daa CW |
1365 | |
1366 | for (i = 0; i < page_count; i++) { | |
05394f39 CW |
1367 | if (obj->dirty) |
1368 | set_page_dirty(obj->pages[i]); | |
3ef94daa | 1369 | |
05394f39 CW |
1370 | if (obj->madv == I915_MADV_WILLNEED) |
1371 | mark_page_accessed(obj->pages[i]); | |
3ef94daa | 1372 | |
05394f39 | 1373 | page_cache_release(obj->pages[i]); |
3ef94daa | 1374 | } |
05394f39 | 1375 | obj->dirty = 0; |
673a394b | 1376 | |
05394f39 CW |
1377 | drm_free_large(obj->pages); |
1378 | obj->pages = NULL; | |
673a394b EA |
1379 | } |
1380 | ||
54cf91dc | 1381 | void |
05394f39 | 1382 | i915_gem_object_move_to_active(struct drm_i915_gem_object *obj, |
1ec14ad3 CW |
1383 | struct intel_ring_buffer *ring, |
1384 | u32 seqno) | |
673a394b | 1385 | { |
05394f39 | 1386 | struct drm_device *dev = obj->base.dev; |
69dc4987 | 1387 | struct drm_i915_private *dev_priv = dev->dev_private; |
617dbe27 | 1388 | |
852835f3 | 1389 | BUG_ON(ring == NULL); |
05394f39 | 1390 | obj->ring = ring; |
673a394b EA |
1391 | |
1392 | /* Add a reference if we're newly entering the active list. */ | |
05394f39 CW |
1393 | if (!obj->active) { |
1394 | drm_gem_object_reference(&obj->base); | |
1395 | obj->active = 1; | |
673a394b | 1396 | } |
e35a41de | 1397 | |
673a394b | 1398 | /* Move from whatever list we were on to the tail of execution. */ |
05394f39 CW |
1399 | list_move_tail(&obj->mm_list, &dev_priv->mm.active_list); |
1400 | list_move_tail(&obj->ring_list, &ring->active_list); | |
caea7476 | 1401 | |
05394f39 | 1402 | obj->last_rendering_seqno = seqno; |
caea7476 | 1403 | |
7dd49065 | 1404 | if (obj->fenced_gpu_access) { |
caea7476 | 1405 | obj->last_fenced_seqno = seqno; |
caea7476 | 1406 | |
7dd49065 CW |
1407 | /* Bump MRU to take account of the delayed flush */ |
1408 | if (obj->fence_reg != I915_FENCE_REG_NONE) { | |
1409 | struct drm_i915_fence_reg *reg; | |
1410 | ||
1411 | reg = &dev_priv->fence_regs[obj->fence_reg]; | |
1412 | list_move_tail(®->lru_list, | |
1413 | &dev_priv->mm.fence_list); | |
1414 | } | |
caea7476 CW |
1415 | } |
1416 | } | |
1417 | ||
1418 | static void | |
1419 | i915_gem_object_move_off_active(struct drm_i915_gem_object *obj) | |
1420 | { | |
1421 | list_del_init(&obj->ring_list); | |
1422 | obj->last_rendering_seqno = 0; | |
15a13bbd | 1423 | obj->last_fenced_seqno = 0; |
673a394b EA |
1424 | } |
1425 | ||
ce44b0ea | 1426 | static void |
05394f39 | 1427 | i915_gem_object_move_to_flushing(struct drm_i915_gem_object *obj) |
ce44b0ea | 1428 | { |
05394f39 | 1429 | struct drm_device *dev = obj->base.dev; |
ce44b0ea | 1430 | drm_i915_private_t *dev_priv = dev->dev_private; |
ce44b0ea | 1431 | |
05394f39 CW |
1432 | BUG_ON(!obj->active); |
1433 | list_move_tail(&obj->mm_list, &dev_priv->mm.flushing_list); | |
caea7476 CW |
1434 | |
1435 | i915_gem_object_move_off_active(obj); | |
1436 | } | |
1437 | ||
1438 | static void | |
1439 | i915_gem_object_move_to_inactive(struct drm_i915_gem_object *obj) | |
1440 | { | |
1441 | struct drm_device *dev = obj->base.dev; | |
1442 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1443 | ||
1b50247a | 1444 | list_move_tail(&obj->mm_list, &dev_priv->mm.inactive_list); |
caea7476 CW |
1445 | |
1446 | BUG_ON(!list_empty(&obj->gpu_write_list)); | |
1447 | BUG_ON(!obj->active); | |
1448 | obj->ring = NULL; | |
1449 | ||
1450 | i915_gem_object_move_off_active(obj); | |
1451 | obj->fenced_gpu_access = false; | |
caea7476 CW |
1452 | |
1453 | obj->active = 0; | |
87ca9c8a | 1454 | obj->pending_gpu_write = false; |
caea7476 CW |
1455 | drm_gem_object_unreference(&obj->base); |
1456 | ||
1457 | WARN_ON(i915_verify_lists(dev)); | |
ce44b0ea | 1458 | } |
673a394b | 1459 | |
963b4836 CW |
1460 | /* Immediately discard the backing storage */ |
1461 | static void | |
05394f39 | 1462 | i915_gem_object_truncate(struct drm_i915_gem_object *obj) |
963b4836 | 1463 | { |
bb6baf76 | 1464 | struct inode *inode; |
963b4836 | 1465 | |
ae9fed6b CW |
1466 | /* Our goal here is to return as much of the memory as |
1467 | * is possible back to the system as we are called from OOM. | |
1468 | * To do this we must instruct the shmfs to drop all of its | |
e2377fe0 | 1469 | * backing pages, *now*. |
ae9fed6b | 1470 | */ |
05394f39 | 1471 | inode = obj->base.filp->f_path.dentry->d_inode; |
e2377fe0 | 1472 | shmem_truncate_range(inode, 0, (loff_t)-1); |
bb6baf76 | 1473 | |
a14917ee CW |
1474 | if (obj->base.map_list.map) |
1475 | drm_gem_free_mmap_offset(&obj->base); | |
1476 | ||
05394f39 | 1477 | obj->madv = __I915_MADV_PURGED; |
963b4836 CW |
1478 | } |
1479 | ||
1480 | static inline int | |
05394f39 | 1481 | i915_gem_object_is_purgeable(struct drm_i915_gem_object *obj) |
963b4836 | 1482 | { |
05394f39 | 1483 | return obj->madv == I915_MADV_DONTNEED; |
963b4836 CW |
1484 | } |
1485 | ||
63560396 | 1486 | static void |
db53a302 CW |
1487 | i915_gem_process_flushing_list(struct intel_ring_buffer *ring, |
1488 | uint32_t flush_domains) | |
63560396 | 1489 | { |
05394f39 | 1490 | struct drm_i915_gem_object *obj, *next; |
63560396 | 1491 | |
05394f39 | 1492 | list_for_each_entry_safe(obj, next, |
64193406 | 1493 | &ring->gpu_write_list, |
63560396 | 1494 | gpu_write_list) { |
05394f39 CW |
1495 | if (obj->base.write_domain & flush_domains) { |
1496 | uint32_t old_write_domain = obj->base.write_domain; | |
63560396 | 1497 | |
05394f39 CW |
1498 | obj->base.write_domain = 0; |
1499 | list_del_init(&obj->gpu_write_list); | |
1ec14ad3 | 1500 | i915_gem_object_move_to_active(obj, ring, |
db53a302 | 1501 | i915_gem_next_request_seqno(ring)); |
63560396 | 1502 | |
63560396 | 1503 | trace_i915_gem_object_change_domain(obj, |
05394f39 | 1504 | obj->base.read_domains, |
63560396 DV |
1505 | old_write_domain); |
1506 | } | |
1507 | } | |
1508 | } | |
8187a2b7 | 1509 | |
53d227f2 DV |
1510 | static u32 |
1511 | i915_gem_get_seqno(struct drm_device *dev) | |
1512 | { | |
1513 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1514 | u32 seqno = dev_priv->next_seqno; | |
1515 | ||
1516 | /* reserve 0 for non-seqno */ | |
1517 | if (++dev_priv->next_seqno == 0) | |
1518 | dev_priv->next_seqno = 1; | |
1519 | ||
1520 | return seqno; | |
1521 | } | |
1522 | ||
1523 | u32 | |
1524 | i915_gem_next_request_seqno(struct intel_ring_buffer *ring) | |
1525 | { | |
1526 | if (ring->outstanding_lazy_request == 0) | |
1527 | ring->outstanding_lazy_request = i915_gem_get_seqno(ring->dev); | |
1528 | ||
1529 | return ring->outstanding_lazy_request; | |
1530 | } | |
1531 | ||
3cce469c | 1532 | int |
db53a302 | 1533 | i915_add_request(struct intel_ring_buffer *ring, |
f787a5f5 | 1534 | struct drm_file *file, |
db53a302 | 1535 | struct drm_i915_gem_request *request) |
673a394b | 1536 | { |
db53a302 | 1537 | drm_i915_private_t *dev_priv = ring->dev->dev_private; |
673a394b | 1538 | uint32_t seqno; |
a71d8d94 | 1539 | u32 request_ring_position; |
673a394b | 1540 | int was_empty; |
3cce469c CW |
1541 | int ret; |
1542 | ||
1543 | BUG_ON(request == NULL); | |
53d227f2 | 1544 | seqno = i915_gem_next_request_seqno(ring); |
673a394b | 1545 | |
a71d8d94 CW |
1546 | /* Record the position of the start of the request so that |
1547 | * should we detect the updated seqno part-way through the | |
1548 | * GPU processing the request, we never over-estimate the | |
1549 | * position of the head. | |
1550 | */ | |
1551 | request_ring_position = intel_ring_get_tail(ring); | |
1552 | ||
3cce469c CW |
1553 | ret = ring->add_request(ring, &seqno); |
1554 | if (ret) | |
1555 | return ret; | |
673a394b | 1556 | |
db53a302 | 1557 | trace_i915_gem_request_add(ring, seqno); |
673a394b EA |
1558 | |
1559 | request->seqno = seqno; | |
852835f3 | 1560 | request->ring = ring; |
a71d8d94 | 1561 | request->tail = request_ring_position; |
673a394b | 1562 | request->emitted_jiffies = jiffies; |
852835f3 ZN |
1563 | was_empty = list_empty(&ring->request_list); |
1564 | list_add_tail(&request->list, &ring->request_list); | |
1565 | ||
db53a302 CW |
1566 | if (file) { |
1567 | struct drm_i915_file_private *file_priv = file->driver_priv; | |
1568 | ||
1c25595f | 1569 | spin_lock(&file_priv->mm.lock); |
f787a5f5 | 1570 | request->file_priv = file_priv; |
b962442e | 1571 | list_add_tail(&request->client_list, |
f787a5f5 | 1572 | &file_priv->mm.request_list); |
1c25595f | 1573 | spin_unlock(&file_priv->mm.lock); |
b962442e | 1574 | } |
673a394b | 1575 | |
5391d0cf | 1576 | ring->outstanding_lazy_request = 0; |
db53a302 | 1577 | |
f65d9421 | 1578 | if (!dev_priv->mm.suspended) { |
3e0dc6b0 BW |
1579 | if (i915_enable_hangcheck) { |
1580 | mod_timer(&dev_priv->hangcheck_timer, | |
1581 | jiffies + | |
1582 | msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD)); | |
1583 | } | |
f65d9421 | 1584 | if (was_empty) |
b3b079db CW |
1585 | queue_delayed_work(dev_priv->wq, |
1586 | &dev_priv->mm.retire_work, HZ); | |
f65d9421 | 1587 | } |
3cce469c | 1588 | return 0; |
673a394b EA |
1589 | } |
1590 | ||
f787a5f5 CW |
1591 | static inline void |
1592 | i915_gem_request_remove_from_client(struct drm_i915_gem_request *request) | |
673a394b | 1593 | { |
1c25595f | 1594 | struct drm_i915_file_private *file_priv = request->file_priv; |
673a394b | 1595 | |
1c25595f CW |
1596 | if (!file_priv) |
1597 | return; | |
1c5d22f7 | 1598 | |
1c25595f | 1599 | spin_lock(&file_priv->mm.lock); |
09bfa517 HRK |
1600 | if (request->file_priv) { |
1601 | list_del(&request->client_list); | |
1602 | request->file_priv = NULL; | |
1603 | } | |
1c25595f | 1604 | spin_unlock(&file_priv->mm.lock); |
673a394b | 1605 | } |
673a394b | 1606 | |
dfaae392 CW |
1607 | static void i915_gem_reset_ring_lists(struct drm_i915_private *dev_priv, |
1608 | struct intel_ring_buffer *ring) | |
9375e446 | 1609 | { |
dfaae392 CW |
1610 | while (!list_empty(&ring->request_list)) { |
1611 | struct drm_i915_gem_request *request; | |
673a394b | 1612 | |
dfaae392 CW |
1613 | request = list_first_entry(&ring->request_list, |
1614 | struct drm_i915_gem_request, | |
1615 | list); | |
de151cf6 | 1616 | |
dfaae392 | 1617 | list_del(&request->list); |
f787a5f5 | 1618 | i915_gem_request_remove_from_client(request); |
dfaae392 CW |
1619 | kfree(request); |
1620 | } | |
673a394b | 1621 | |
dfaae392 | 1622 | while (!list_empty(&ring->active_list)) { |
05394f39 | 1623 | struct drm_i915_gem_object *obj; |
9375e446 | 1624 | |
05394f39 CW |
1625 | obj = list_first_entry(&ring->active_list, |
1626 | struct drm_i915_gem_object, | |
1627 | ring_list); | |
9375e446 | 1628 | |
05394f39 CW |
1629 | obj->base.write_domain = 0; |
1630 | list_del_init(&obj->gpu_write_list); | |
1631 | i915_gem_object_move_to_inactive(obj); | |
673a394b EA |
1632 | } |
1633 | } | |
1634 | ||
312817a3 CW |
1635 | static void i915_gem_reset_fences(struct drm_device *dev) |
1636 | { | |
1637 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1638 | int i; | |
1639 | ||
4b9de737 | 1640 | for (i = 0; i < dev_priv->num_fence_regs; i++) { |
312817a3 | 1641 | struct drm_i915_fence_reg *reg = &dev_priv->fence_regs[i]; |
7d2cb39c | 1642 | |
ada726c7 | 1643 | i915_gem_write_fence(dev, i, NULL); |
7d2cb39c | 1644 | |
ada726c7 CW |
1645 | if (reg->obj) |
1646 | i915_gem_object_fence_lost(reg->obj); | |
7d2cb39c | 1647 | |
ada726c7 CW |
1648 | reg->pin_count = 0; |
1649 | reg->obj = NULL; | |
1650 | INIT_LIST_HEAD(®->lru_list); | |
312817a3 | 1651 | } |
ada726c7 CW |
1652 | |
1653 | INIT_LIST_HEAD(&dev_priv->mm.fence_list); | |
312817a3 CW |
1654 | } |
1655 | ||
069efc1d | 1656 | void i915_gem_reset(struct drm_device *dev) |
673a394b | 1657 | { |
77f01230 | 1658 | struct drm_i915_private *dev_priv = dev->dev_private; |
05394f39 | 1659 | struct drm_i915_gem_object *obj; |
1ec14ad3 | 1660 | int i; |
673a394b | 1661 | |
1ec14ad3 CW |
1662 | for (i = 0; i < I915_NUM_RINGS; i++) |
1663 | i915_gem_reset_ring_lists(dev_priv, &dev_priv->ring[i]); | |
dfaae392 CW |
1664 | |
1665 | /* Remove anything from the flushing lists. The GPU cache is likely | |
1666 | * to be lost on reset along with the data, so simply move the | |
1667 | * lost bo to the inactive list. | |
1668 | */ | |
1669 | while (!list_empty(&dev_priv->mm.flushing_list)) { | |
0206e353 | 1670 | obj = list_first_entry(&dev_priv->mm.flushing_list, |
05394f39 CW |
1671 | struct drm_i915_gem_object, |
1672 | mm_list); | |
dfaae392 | 1673 | |
05394f39 CW |
1674 | obj->base.write_domain = 0; |
1675 | list_del_init(&obj->gpu_write_list); | |
1676 | i915_gem_object_move_to_inactive(obj); | |
dfaae392 CW |
1677 | } |
1678 | ||
1679 | /* Move everything out of the GPU domains to ensure we do any | |
1680 | * necessary invalidation upon reuse. | |
1681 | */ | |
05394f39 | 1682 | list_for_each_entry(obj, |
77f01230 | 1683 | &dev_priv->mm.inactive_list, |
69dc4987 | 1684 | mm_list) |
77f01230 | 1685 | { |
05394f39 | 1686 | obj->base.read_domains &= ~I915_GEM_GPU_DOMAINS; |
77f01230 | 1687 | } |
069efc1d CW |
1688 | |
1689 | /* The fence registers are invalidated so clear them out */ | |
312817a3 | 1690 | i915_gem_reset_fences(dev); |
673a394b EA |
1691 | } |
1692 | ||
1693 | /** | |
1694 | * This function clears the request list as sequence numbers are passed. | |
1695 | */ | |
a71d8d94 | 1696 | void |
db53a302 | 1697 | i915_gem_retire_requests_ring(struct intel_ring_buffer *ring) |
673a394b | 1698 | { |
673a394b | 1699 | uint32_t seqno; |
1ec14ad3 | 1700 | int i; |
673a394b | 1701 | |
db53a302 | 1702 | if (list_empty(&ring->request_list)) |
6c0594a3 KW |
1703 | return; |
1704 | ||
db53a302 | 1705 | WARN_ON(i915_verify_lists(ring->dev)); |
673a394b | 1706 | |
78501eac | 1707 | seqno = ring->get_seqno(ring); |
1ec14ad3 | 1708 | |
076e2c0e | 1709 | for (i = 0; i < ARRAY_SIZE(ring->sync_seqno); i++) |
1ec14ad3 CW |
1710 | if (seqno >= ring->sync_seqno[i]) |
1711 | ring->sync_seqno[i] = 0; | |
1712 | ||
852835f3 | 1713 | while (!list_empty(&ring->request_list)) { |
673a394b | 1714 | struct drm_i915_gem_request *request; |
673a394b | 1715 | |
852835f3 | 1716 | request = list_first_entry(&ring->request_list, |
673a394b EA |
1717 | struct drm_i915_gem_request, |
1718 | list); | |
673a394b | 1719 | |
dfaae392 | 1720 | if (!i915_seqno_passed(seqno, request->seqno)) |
b84d5f0c CW |
1721 | break; |
1722 | ||
db53a302 | 1723 | trace_i915_gem_request_retire(ring, request->seqno); |
a71d8d94 CW |
1724 | /* We know the GPU must have read the request to have |
1725 | * sent us the seqno + interrupt, so use the position | |
1726 | * of tail of the request to update the last known position | |
1727 | * of the GPU head. | |
1728 | */ | |
1729 | ring->last_retired_head = request->tail; | |
b84d5f0c CW |
1730 | |
1731 | list_del(&request->list); | |
f787a5f5 | 1732 | i915_gem_request_remove_from_client(request); |
b84d5f0c CW |
1733 | kfree(request); |
1734 | } | |
673a394b | 1735 | |
b84d5f0c CW |
1736 | /* Move any buffers on the active list that are no longer referenced |
1737 | * by the ringbuffer to the flushing/inactive lists as appropriate. | |
1738 | */ | |
1739 | while (!list_empty(&ring->active_list)) { | |
05394f39 | 1740 | struct drm_i915_gem_object *obj; |
b84d5f0c | 1741 | |
0206e353 | 1742 | obj = list_first_entry(&ring->active_list, |
05394f39 CW |
1743 | struct drm_i915_gem_object, |
1744 | ring_list); | |
673a394b | 1745 | |
05394f39 | 1746 | if (!i915_seqno_passed(seqno, obj->last_rendering_seqno)) |
673a394b | 1747 | break; |
b84d5f0c | 1748 | |
05394f39 | 1749 | if (obj->base.write_domain != 0) |
b84d5f0c CW |
1750 | i915_gem_object_move_to_flushing(obj); |
1751 | else | |
1752 | i915_gem_object_move_to_inactive(obj); | |
673a394b | 1753 | } |
9d34e5db | 1754 | |
db53a302 CW |
1755 | if (unlikely(ring->trace_irq_seqno && |
1756 | i915_seqno_passed(seqno, ring->trace_irq_seqno))) { | |
1ec14ad3 | 1757 | ring->irq_put(ring); |
db53a302 | 1758 | ring->trace_irq_seqno = 0; |
9d34e5db | 1759 | } |
23bc5982 | 1760 | |
db53a302 | 1761 | WARN_ON(i915_verify_lists(ring->dev)); |
673a394b EA |
1762 | } |
1763 | ||
b09a1fec CW |
1764 | void |
1765 | i915_gem_retire_requests(struct drm_device *dev) | |
1766 | { | |
1767 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1ec14ad3 | 1768 | int i; |
b09a1fec | 1769 | |
1ec14ad3 | 1770 | for (i = 0; i < I915_NUM_RINGS; i++) |
db53a302 | 1771 | i915_gem_retire_requests_ring(&dev_priv->ring[i]); |
b09a1fec CW |
1772 | } |
1773 | ||
75ef9da2 | 1774 | static void |
673a394b EA |
1775 | i915_gem_retire_work_handler(struct work_struct *work) |
1776 | { | |
1777 | drm_i915_private_t *dev_priv; | |
1778 | struct drm_device *dev; | |
0a58705b CW |
1779 | bool idle; |
1780 | int i; | |
673a394b EA |
1781 | |
1782 | dev_priv = container_of(work, drm_i915_private_t, | |
1783 | mm.retire_work.work); | |
1784 | dev = dev_priv->dev; | |
1785 | ||
891b48cf CW |
1786 | /* Come back later if the device is busy... */ |
1787 | if (!mutex_trylock(&dev->struct_mutex)) { | |
1788 | queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, HZ); | |
1789 | return; | |
1790 | } | |
1791 | ||
b09a1fec | 1792 | i915_gem_retire_requests(dev); |
d1b851fc | 1793 | |
0a58705b CW |
1794 | /* Send a periodic flush down the ring so we don't hold onto GEM |
1795 | * objects indefinitely. | |
1796 | */ | |
1797 | idle = true; | |
1798 | for (i = 0; i < I915_NUM_RINGS; i++) { | |
1799 | struct intel_ring_buffer *ring = &dev_priv->ring[i]; | |
1800 | ||
1801 | if (!list_empty(&ring->gpu_write_list)) { | |
1802 | struct drm_i915_gem_request *request; | |
1803 | int ret; | |
1804 | ||
db53a302 CW |
1805 | ret = i915_gem_flush_ring(ring, |
1806 | 0, I915_GEM_GPU_DOMAINS); | |
0a58705b CW |
1807 | request = kzalloc(sizeof(*request), GFP_KERNEL); |
1808 | if (ret || request == NULL || | |
db53a302 | 1809 | i915_add_request(ring, NULL, request)) |
0a58705b CW |
1810 | kfree(request); |
1811 | } | |
1812 | ||
1813 | idle &= list_empty(&ring->request_list); | |
1814 | } | |
1815 | ||
1816 | if (!dev_priv->mm.suspended && !idle) | |
9c9fe1f8 | 1817 | queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, HZ); |
0a58705b | 1818 | |
673a394b EA |
1819 | mutex_unlock(&dev->struct_mutex); |
1820 | } | |
1821 | ||
604dd3ec BW |
1822 | static int __wait_seqno(struct intel_ring_buffer *ring, u32 seqno, |
1823 | bool interruptible) | |
1824 | { | |
1825 | drm_i915_private_t *dev_priv = ring->dev->dev_private; | |
1826 | int ret = 0; | |
1827 | ||
1828 | if (i915_seqno_passed(ring->get_seqno(ring), seqno)) | |
1829 | return 0; | |
1830 | ||
1831 | trace_i915_gem_request_wait_begin(ring, seqno); | |
1832 | if (WARN_ON(!ring->irq_get(ring))) | |
1833 | return -ENODEV; | |
1834 | ||
1835 | #define EXIT_COND \ | |
1836 | (i915_seqno_passed(ring->get_seqno(ring), seqno) || \ | |
1837 | atomic_read(&dev_priv->mm.wedged)) | |
1838 | ||
1839 | if (interruptible) | |
1840 | ret = wait_event_interruptible(ring->irq_queue, | |
1841 | EXIT_COND); | |
1842 | else | |
1843 | wait_event(ring->irq_queue, EXIT_COND); | |
1844 | ||
1845 | ring->irq_put(ring); | |
1846 | trace_i915_gem_request_wait_end(ring, seqno); | |
1847 | #undef EXIT_COND | |
1848 | ||
1849 | return ret; | |
1850 | } | |
1851 | ||
db53a302 CW |
1852 | /** |
1853 | * Waits for a sequence number to be signaled, and cleans up the | |
1854 | * request and object lists appropriately for that event. | |
1855 | */ | |
5a5a0c64 | 1856 | int |
db53a302 | 1857 | i915_wait_request(struct intel_ring_buffer *ring, |
b2da9fe5 | 1858 | uint32_t seqno) |
673a394b | 1859 | { |
db53a302 | 1860 | drm_i915_private_t *dev_priv = ring->dev->dev_private; |
673a394b EA |
1861 | int ret = 0; |
1862 | ||
1863 | BUG_ON(seqno == 0); | |
1864 | ||
d9bc7e9f CW |
1865 | if (atomic_read(&dev_priv->mm.wedged)) { |
1866 | struct completion *x = &dev_priv->error_completion; | |
1867 | bool recovery_complete; | |
1868 | unsigned long flags; | |
1869 | ||
1870 | /* Give the error handler a chance to run. */ | |
1871 | spin_lock_irqsave(&x->wait.lock, flags); | |
1872 | recovery_complete = x->done > 0; | |
1873 | spin_unlock_irqrestore(&x->wait.lock, flags); | |
1874 | ||
1875 | return recovery_complete ? -EIO : -EAGAIN; | |
1876 | } | |
30dbf0c0 | 1877 | |
5d97eb69 | 1878 | if (seqno == ring->outstanding_lazy_request) { |
3cce469c CW |
1879 | struct drm_i915_gem_request *request; |
1880 | ||
1881 | request = kzalloc(sizeof(*request), GFP_KERNEL); | |
1882 | if (request == NULL) | |
e35a41de | 1883 | return -ENOMEM; |
3cce469c | 1884 | |
db53a302 | 1885 | ret = i915_add_request(ring, NULL, request); |
3cce469c CW |
1886 | if (ret) { |
1887 | kfree(request); | |
1888 | return ret; | |
1889 | } | |
1890 | ||
1891 | seqno = request->seqno; | |
e35a41de | 1892 | } |
ffed1d09 | 1893 | |
604dd3ec | 1894 | ret = __wait_seqno(ring, seqno, dev_priv->mm.interruptible); |
ba1234d1 | 1895 | if (atomic_read(&dev_priv->mm.wedged)) |
30dbf0c0 | 1896 | ret = -EAGAIN; |
673a394b | 1897 | |
673a394b EA |
1898 | return ret; |
1899 | } | |
1900 | ||
673a394b EA |
1901 | /** |
1902 | * Ensures that all rendering to the object has completed and the object is | |
1903 | * safe to unbind from the GTT or access from the CPU. | |
1904 | */ | |
54cf91dc | 1905 | int |
ce453d81 | 1906 | i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj) |
673a394b | 1907 | { |
673a394b EA |
1908 | int ret; |
1909 | ||
e47c68e9 EA |
1910 | /* This function only exists to support waiting for existing rendering, |
1911 | * not for emitting required flushes. | |
673a394b | 1912 | */ |
05394f39 | 1913 | BUG_ON((obj->base.write_domain & I915_GEM_GPU_DOMAINS) != 0); |
673a394b EA |
1914 | |
1915 | /* If there is rendering queued on the buffer being evicted, wait for | |
1916 | * it. | |
1917 | */ | |
05394f39 | 1918 | if (obj->active) { |
b2da9fe5 | 1919 | ret = i915_wait_request(obj->ring, obj->last_rendering_seqno); |
2cf34d7b | 1920 | if (ret) |
673a394b | 1921 | return ret; |
b2da9fe5 | 1922 | i915_gem_retire_requests_ring(obj->ring); |
673a394b EA |
1923 | } |
1924 | ||
1925 | return 0; | |
1926 | } | |
1927 | ||
5816d648 BW |
1928 | /** |
1929 | * i915_gem_object_sync - sync an object to a ring. | |
1930 | * | |
1931 | * @obj: object which may be in use on another ring. | |
1932 | * @to: ring we wish to use the object on. May be NULL. | |
1933 | * | |
1934 | * This code is meant to abstract object synchronization with the GPU. | |
1935 | * Calling with NULL implies synchronizing the object with the CPU | |
1936 | * rather than a particular GPU ring. | |
1937 | * | |
1938 | * Returns 0 if successful, else propagates up the lower layer error. | |
1939 | */ | |
2911a35b BW |
1940 | int |
1941 | i915_gem_object_sync(struct drm_i915_gem_object *obj, | |
1942 | struct intel_ring_buffer *to) | |
1943 | { | |
1944 | struct intel_ring_buffer *from = obj->ring; | |
1945 | u32 seqno; | |
1946 | int ret, idx; | |
1947 | ||
1948 | if (from == NULL || to == from) | |
1949 | return 0; | |
1950 | ||
5816d648 | 1951 | if (to == NULL || !i915_semaphore_is_enabled(obj->base.dev)) |
2911a35b BW |
1952 | return i915_gem_object_wait_rendering(obj); |
1953 | ||
1954 | idx = intel_ring_sync_index(from, to); | |
1955 | ||
1956 | seqno = obj->last_rendering_seqno; | |
1957 | if (seqno <= from->sync_seqno[idx]) | |
1958 | return 0; | |
1959 | ||
1960 | if (seqno == from->outstanding_lazy_request) { | |
1961 | struct drm_i915_gem_request *request; | |
1962 | ||
1963 | request = kzalloc(sizeof(*request), GFP_KERNEL); | |
1964 | if (request == NULL) | |
1965 | return -ENOMEM; | |
1966 | ||
1967 | ret = i915_add_request(from, NULL, request); | |
1968 | if (ret) { | |
1969 | kfree(request); | |
1970 | return ret; | |
1971 | } | |
1972 | ||
1973 | seqno = request->seqno; | |
1974 | } | |
1975 | ||
2911a35b | 1976 | |
1500f7ea | 1977 | ret = to->sync_to(to, from, seqno); |
e3a5a225 BW |
1978 | if (!ret) |
1979 | from->sync_seqno[idx] = seqno; | |
2911a35b | 1980 | |
e3a5a225 | 1981 | return ret; |
2911a35b BW |
1982 | } |
1983 | ||
b5ffc9bc CW |
1984 | static void i915_gem_object_finish_gtt(struct drm_i915_gem_object *obj) |
1985 | { | |
1986 | u32 old_write_domain, old_read_domains; | |
1987 | ||
b5ffc9bc CW |
1988 | /* Act a barrier for all accesses through the GTT */ |
1989 | mb(); | |
1990 | ||
1991 | /* Force a pagefault for domain tracking on next user access */ | |
1992 | i915_gem_release_mmap(obj); | |
1993 | ||
b97c3d9c KP |
1994 | if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0) |
1995 | return; | |
1996 | ||
b5ffc9bc CW |
1997 | old_read_domains = obj->base.read_domains; |
1998 | old_write_domain = obj->base.write_domain; | |
1999 | ||
2000 | obj->base.read_domains &= ~I915_GEM_DOMAIN_GTT; | |
2001 | obj->base.write_domain &= ~I915_GEM_DOMAIN_GTT; | |
2002 | ||
2003 | trace_i915_gem_object_change_domain(obj, | |
2004 | old_read_domains, | |
2005 | old_write_domain); | |
2006 | } | |
2007 | ||
673a394b EA |
2008 | /** |
2009 | * Unbinds an object from the GTT aperture. | |
2010 | */ | |
0f973f27 | 2011 | int |
05394f39 | 2012 | i915_gem_object_unbind(struct drm_i915_gem_object *obj) |
673a394b | 2013 | { |
7bddb01f | 2014 | drm_i915_private_t *dev_priv = obj->base.dev->dev_private; |
673a394b EA |
2015 | int ret = 0; |
2016 | ||
05394f39 | 2017 | if (obj->gtt_space == NULL) |
673a394b EA |
2018 | return 0; |
2019 | ||
05394f39 | 2020 | if (obj->pin_count != 0) { |
673a394b EA |
2021 | DRM_ERROR("Attempting to unbind pinned buffer\n"); |
2022 | return -EINVAL; | |
2023 | } | |
2024 | ||
a8198eea | 2025 | ret = i915_gem_object_finish_gpu(obj); |
1488fc08 | 2026 | if (ret) |
a8198eea CW |
2027 | return ret; |
2028 | /* Continue on if we fail due to EIO, the GPU is hung so we | |
2029 | * should be safe and we need to cleanup or else we might | |
2030 | * cause memory corruption through use-after-free. | |
2031 | */ | |
2032 | ||
b5ffc9bc | 2033 | i915_gem_object_finish_gtt(obj); |
5323fd04 | 2034 | |
673a394b EA |
2035 | /* Move the object to the CPU domain to ensure that |
2036 | * any possible CPU writes while it's not in the GTT | |
a8198eea | 2037 | * are flushed when we go to remap it. |
673a394b | 2038 | */ |
a8198eea CW |
2039 | if (ret == 0) |
2040 | ret = i915_gem_object_set_to_cpu_domain(obj, 1); | |
8dc1775d | 2041 | if (ret == -ERESTARTSYS) |
673a394b | 2042 | return ret; |
812ed492 | 2043 | if (ret) { |
a8198eea CW |
2044 | /* In the event of a disaster, abandon all caches and |
2045 | * hope for the best. | |
2046 | */ | |
812ed492 | 2047 | i915_gem_clflush_object(obj); |
05394f39 | 2048 | obj->base.read_domains = obj->base.write_domain = I915_GEM_DOMAIN_CPU; |
812ed492 | 2049 | } |
673a394b | 2050 | |
96b47b65 | 2051 | /* release the fence reg _after_ flushing */ |
d9e86c0e | 2052 | ret = i915_gem_object_put_fence(obj); |
1488fc08 | 2053 | if (ret) |
d9e86c0e | 2054 | return ret; |
96b47b65 | 2055 | |
db53a302 CW |
2056 | trace_i915_gem_object_unbind(obj); |
2057 | ||
74898d7e DV |
2058 | if (obj->has_global_gtt_mapping) |
2059 | i915_gem_gtt_unbind_object(obj); | |
7bddb01f DV |
2060 | if (obj->has_aliasing_ppgtt_mapping) { |
2061 | i915_ppgtt_unbind_object(dev_priv->mm.aliasing_ppgtt, obj); | |
2062 | obj->has_aliasing_ppgtt_mapping = 0; | |
2063 | } | |
74163907 | 2064 | i915_gem_gtt_finish_object(obj); |
7bddb01f | 2065 | |
e5281ccd | 2066 | i915_gem_object_put_pages_gtt(obj); |
673a394b | 2067 | |
6299f992 | 2068 | list_del_init(&obj->gtt_list); |
05394f39 | 2069 | list_del_init(&obj->mm_list); |
75e9e915 | 2070 | /* Avoid an unnecessary call to unbind on rebind. */ |
05394f39 | 2071 | obj->map_and_fenceable = true; |
673a394b | 2072 | |
05394f39 CW |
2073 | drm_mm_put_block(obj->gtt_space); |
2074 | obj->gtt_space = NULL; | |
2075 | obj->gtt_offset = 0; | |
673a394b | 2076 | |
05394f39 | 2077 | if (i915_gem_object_is_purgeable(obj)) |
963b4836 CW |
2078 | i915_gem_object_truncate(obj); |
2079 | ||
8dc1775d | 2080 | return ret; |
673a394b EA |
2081 | } |
2082 | ||
88241785 | 2083 | int |
db53a302 | 2084 | i915_gem_flush_ring(struct intel_ring_buffer *ring, |
54cf91dc CW |
2085 | uint32_t invalidate_domains, |
2086 | uint32_t flush_domains) | |
2087 | { | |
88241785 CW |
2088 | int ret; |
2089 | ||
36d527de CW |
2090 | if (((invalidate_domains | flush_domains) & I915_GEM_GPU_DOMAINS) == 0) |
2091 | return 0; | |
2092 | ||
db53a302 CW |
2093 | trace_i915_gem_ring_flush(ring, invalidate_domains, flush_domains); |
2094 | ||
88241785 CW |
2095 | ret = ring->flush(ring, invalidate_domains, flush_domains); |
2096 | if (ret) | |
2097 | return ret; | |
2098 | ||
36d527de CW |
2099 | if (flush_domains & I915_GEM_GPU_DOMAINS) |
2100 | i915_gem_process_flushing_list(ring, flush_domains); | |
2101 | ||
88241785 | 2102 | return 0; |
54cf91dc CW |
2103 | } |
2104 | ||
b2da9fe5 | 2105 | static int i915_ring_idle(struct intel_ring_buffer *ring) |
a56ba56c | 2106 | { |
88241785 CW |
2107 | int ret; |
2108 | ||
395b70be | 2109 | if (list_empty(&ring->gpu_write_list) && list_empty(&ring->active_list)) |
64193406 CW |
2110 | return 0; |
2111 | ||
88241785 | 2112 | if (!list_empty(&ring->gpu_write_list)) { |
db53a302 | 2113 | ret = i915_gem_flush_ring(ring, |
0ac74c6b | 2114 | I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS); |
88241785 CW |
2115 | if (ret) |
2116 | return ret; | |
2117 | } | |
2118 | ||
b2da9fe5 | 2119 | return i915_wait_request(ring, i915_gem_next_request_seqno(ring)); |
a56ba56c CW |
2120 | } |
2121 | ||
b2da9fe5 | 2122 | int i915_gpu_idle(struct drm_device *dev) |
4df2faf4 DV |
2123 | { |
2124 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1ec14ad3 | 2125 | int ret, i; |
4df2faf4 | 2126 | |
4df2faf4 | 2127 | /* Flush everything onto the inactive list. */ |
1ec14ad3 | 2128 | for (i = 0; i < I915_NUM_RINGS; i++) { |
b2da9fe5 | 2129 | ret = i915_ring_idle(&dev_priv->ring[i]); |
1ec14ad3 CW |
2130 | if (ret) |
2131 | return ret; | |
2132 | } | |
4df2faf4 | 2133 | |
8a1a49f9 | 2134 | return 0; |
4df2faf4 DV |
2135 | } |
2136 | ||
9ce079e4 CW |
2137 | static void sandybridge_write_fence_reg(struct drm_device *dev, int reg, |
2138 | struct drm_i915_gem_object *obj) | |
4e901fdc | 2139 | { |
4e901fdc | 2140 | drm_i915_private_t *dev_priv = dev->dev_private; |
4e901fdc EA |
2141 | uint64_t val; |
2142 | ||
9ce079e4 CW |
2143 | if (obj) { |
2144 | u32 size = obj->gtt_space->size; | |
4e901fdc | 2145 | |
9ce079e4 CW |
2146 | val = (uint64_t)((obj->gtt_offset + size - 4096) & |
2147 | 0xfffff000) << 32; | |
2148 | val |= obj->gtt_offset & 0xfffff000; | |
2149 | val |= (uint64_t)((obj->stride / 128) - 1) << | |
2150 | SANDYBRIDGE_FENCE_PITCH_SHIFT; | |
4e901fdc | 2151 | |
9ce079e4 CW |
2152 | if (obj->tiling_mode == I915_TILING_Y) |
2153 | val |= 1 << I965_FENCE_TILING_Y_SHIFT; | |
2154 | val |= I965_FENCE_REG_VALID; | |
2155 | } else | |
2156 | val = 0; | |
c6642782 | 2157 | |
9ce079e4 CW |
2158 | I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + reg * 8, val); |
2159 | POSTING_READ(FENCE_REG_SANDYBRIDGE_0 + reg * 8); | |
4e901fdc EA |
2160 | } |
2161 | ||
9ce079e4 CW |
2162 | static void i965_write_fence_reg(struct drm_device *dev, int reg, |
2163 | struct drm_i915_gem_object *obj) | |
de151cf6 | 2164 | { |
de151cf6 | 2165 | drm_i915_private_t *dev_priv = dev->dev_private; |
de151cf6 JB |
2166 | uint64_t val; |
2167 | ||
9ce079e4 CW |
2168 | if (obj) { |
2169 | u32 size = obj->gtt_space->size; | |
de151cf6 | 2170 | |
9ce079e4 CW |
2171 | val = (uint64_t)((obj->gtt_offset + size - 4096) & |
2172 | 0xfffff000) << 32; | |
2173 | val |= obj->gtt_offset & 0xfffff000; | |
2174 | val |= ((obj->stride / 128) - 1) << I965_FENCE_PITCH_SHIFT; | |
2175 | if (obj->tiling_mode == I915_TILING_Y) | |
2176 | val |= 1 << I965_FENCE_TILING_Y_SHIFT; | |
2177 | val |= I965_FENCE_REG_VALID; | |
2178 | } else | |
2179 | val = 0; | |
c6642782 | 2180 | |
9ce079e4 CW |
2181 | I915_WRITE64(FENCE_REG_965_0 + reg * 8, val); |
2182 | POSTING_READ(FENCE_REG_965_0 + reg * 8); | |
de151cf6 JB |
2183 | } |
2184 | ||
9ce079e4 CW |
2185 | static void i915_write_fence_reg(struct drm_device *dev, int reg, |
2186 | struct drm_i915_gem_object *obj) | |
de151cf6 | 2187 | { |
de151cf6 | 2188 | drm_i915_private_t *dev_priv = dev->dev_private; |
9ce079e4 | 2189 | u32 val; |
de151cf6 | 2190 | |
9ce079e4 CW |
2191 | if (obj) { |
2192 | u32 size = obj->gtt_space->size; | |
2193 | int pitch_val; | |
2194 | int tile_width; | |
c6642782 | 2195 | |
9ce079e4 CW |
2196 | WARN((obj->gtt_offset & ~I915_FENCE_START_MASK) || |
2197 | (size & -size) != size || | |
2198 | (obj->gtt_offset & (size - 1)), | |
2199 | "object 0x%08x [fenceable? %d] not 1M or pot-size (0x%08x) aligned\n", | |
2200 | obj->gtt_offset, obj->map_and_fenceable, size); | |
c6642782 | 2201 | |
9ce079e4 CW |
2202 | if (obj->tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev)) |
2203 | tile_width = 128; | |
2204 | else | |
2205 | tile_width = 512; | |
2206 | ||
2207 | /* Note: pitch better be a power of two tile widths */ | |
2208 | pitch_val = obj->stride / tile_width; | |
2209 | pitch_val = ffs(pitch_val) - 1; | |
2210 | ||
2211 | val = obj->gtt_offset; | |
2212 | if (obj->tiling_mode == I915_TILING_Y) | |
2213 | val |= 1 << I830_FENCE_TILING_Y_SHIFT; | |
2214 | val |= I915_FENCE_SIZE_BITS(size); | |
2215 | val |= pitch_val << I830_FENCE_PITCH_SHIFT; | |
2216 | val |= I830_FENCE_REG_VALID; | |
2217 | } else | |
2218 | val = 0; | |
2219 | ||
2220 | if (reg < 8) | |
2221 | reg = FENCE_REG_830_0 + reg * 4; | |
2222 | else | |
2223 | reg = FENCE_REG_945_8 + (reg - 8) * 4; | |
2224 | ||
2225 | I915_WRITE(reg, val); | |
2226 | POSTING_READ(reg); | |
de151cf6 JB |
2227 | } |
2228 | ||
9ce079e4 CW |
2229 | static void i830_write_fence_reg(struct drm_device *dev, int reg, |
2230 | struct drm_i915_gem_object *obj) | |
de151cf6 | 2231 | { |
de151cf6 | 2232 | drm_i915_private_t *dev_priv = dev->dev_private; |
de151cf6 | 2233 | uint32_t val; |
de151cf6 | 2234 | |
9ce079e4 CW |
2235 | if (obj) { |
2236 | u32 size = obj->gtt_space->size; | |
2237 | uint32_t pitch_val; | |
de151cf6 | 2238 | |
9ce079e4 CW |
2239 | WARN((obj->gtt_offset & ~I830_FENCE_START_MASK) || |
2240 | (size & -size) != size || | |
2241 | (obj->gtt_offset & (size - 1)), | |
2242 | "object 0x%08x not 512K or pot-size 0x%08x aligned\n", | |
2243 | obj->gtt_offset, size); | |
e76a16de | 2244 | |
9ce079e4 CW |
2245 | pitch_val = obj->stride / 128; |
2246 | pitch_val = ffs(pitch_val) - 1; | |
de151cf6 | 2247 | |
9ce079e4 CW |
2248 | val = obj->gtt_offset; |
2249 | if (obj->tiling_mode == I915_TILING_Y) | |
2250 | val |= 1 << I830_FENCE_TILING_Y_SHIFT; | |
2251 | val |= I830_FENCE_SIZE_BITS(size); | |
2252 | val |= pitch_val << I830_FENCE_PITCH_SHIFT; | |
2253 | val |= I830_FENCE_REG_VALID; | |
2254 | } else | |
2255 | val = 0; | |
c6642782 | 2256 | |
9ce079e4 CW |
2257 | I915_WRITE(FENCE_REG_830_0 + reg * 4, val); |
2258 | POSTING_READ(FENCE_REG_830_0 + reg * 4); | |
2259 | } | |
2260 | ||
2261 | static void i915_gem_write_fence(struct drm_device *dev, int reg, | |
2262 | struct drm_i915_gem_object *obj) | |
2263 | { | |
2264 | switch (INTEL_INFO(dev)->gen) { | |
2265 | case 7: | |
2266 | case 6: sandybridge_write_fence_reg(dev, reg, obj); break; | |
2267 | case 5: | |
2268 | case 4: i965_write_fence_reg(dev, reg, obj); break; | |
2269 | case 3: i915_write_fence_reg(dev, reg, obj); break; | |
2270 | case 2: i830_write_fence_reg(dev, reg, obj); break; | |
2271 | default: break; | |
2272 | } | |
de151cf6 JB |
2273 | } |
2274 | ||
61050808 CW |
2275 | static inline int fence_number(struct drm_i915_private *dev_priv, |
2276 | struct drm_i915_fence_reg *fence) | |
2277 | { | |
2278 | return fence - dev_priv->fence_regs; | |
2279 | } | |
2280 | ||
2281 | static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj, | |
2282 | struct drm_i915_fence_reg *fence, | |
2283 | bool enable) | |
2284 | { | |
2285 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; | |
2286 | int reg = fence_number(dev_priv, fence); | |
2287 | ||
2288 | i915_gem_write_fence(obj->base.dev, reg, enable ? obj : NULL); | |
2289 | ||
2290 | if (enable) { | |
2291 | obj->fence_reg = reg; | |
2292 | fence->obj = obj; | |
2293 | list_move_tail(&fence->lru_list, &dev_priv->mm.fence_list); | |
2294 | } else { | |
2295 | obj->fence_reg = I915_FENCE_REG_NONE; | |
2296 | fence->obj = NULL; | |
2297 | list_del_init(&fence->lru_list); | |
2298 | } | |
2299 | } | |
2300 | ||
d9e86c0e | 2301 | static int |
a360bb1a | 2302 | i915_gem_object_flush_fence(struct drm_i915_gem_object *obj) |
d9e86c0e CW |
2303 | { |
2304 | int ret; | |
2305 | ||
2306 | if (obj->fenced_gpu_access) { | |
88241785 | 2307 | if (obj->base.write_domain & I915_GEM_GPU_DOMAINS) { |
1c293ea3 | 2308 | ret = i915_gem_flush_ring(obj->ring, |
88241785 CW |
2309 | 0, obj->base.write_domain); |
2310 | if (ret) | |
2311 | return ret; | |
2312 | } | |
d9e86c0e CW |
2313 | |
2314 | obj->fenced_gpu_access = false; | |
2315 | } | |
2316 | ||
1c293ea3 | 2317 | if (obj->last_fenced_seqno) { |
b2da9fe5 | 2318 | ret = i915_wait_request(obj->ring, obj->last_fenced_seqno); |
18991845 CW |
2319 | if (ret) |
2320 | return ret; | |
d9e86c0e CW |
2321 | |
2322 | obj->last_fenced_seqno = 0; | |
d9e86c0e CW |
2323 | } |
2324 | ||
63256ec5 CW |
2325 | /* Ensure that all CPU reads are completed before installing a fence |
2326 | * and all writes before removing the fence. | |
2327 | */ | |
2328 | if (obj->base.read_domains & I915_GEM_DOMAIN_GTT) | |
2329 | mb(); | |
2330 | ||
d9e86c0e CW |
2331 | return 0; |
2332 | } | |
2333 | ||
2334 | int | |
2335 | i915_gem_object_put_fence(struct drm_i915_gem_object *obj) | |
2336 | { | |
61050808 | 2337 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
d9e86c0e CW |
2338 | int ret; |
2339 | ||
a360bb1a | 2340 | ret = i915_gem_object_flush_fence(obj); |
d9e86c0e CW |
2341 | if (ret) |
2342 | return ret; | |
2343 | ||
61050808 CW |
2344 | if (obj->fence_reg == I915_FENCE_REG_NONE) |
2345 | return 0; | |
d9e86c0e | 2346 | |
61050808 CW |
2347 | i915_gem_object_update_fence(obj, |
2348 | &dev_priv->fence_regs[obj->fence_reg], | |
2349 | false); | |
2350 | i915_gem_object_fence_lost(obj); | |
d9e86c0e CW |
2351 | |
2352 | return 0; | |
2353 | } | |
2354 | ||
2355 | static struct drm_i915_fence_reg * | |
a360bb1a | 2356 | i915_find_fence_reg(struct drm_device *dev) |
ae3db24a | 2357 | { |
ae3db24a | 2358 | struct drm_i915_private *dev_priv = dev->dev_private; |
8fe301ad | 2359 | struct drm_i915_fence_reg *reg, *avail; |
d9e86c0e | 2360 | int i; |
ae3db24a DV |
2361 | |
2362 | /* First try to find a free reg */ | |
d9e86c0e | 2363 | avail = NULL; |
ae3db24a DV |
2364 | for (i = dev_priv->fence_reg_start; i < dev_priv->num_fence_regs; i++) { |
2365 | reg = &dev_priv->fence_regs[i]; | |
2366 | if (!reg->obj) | |
d9e86c0e | 2367 | return reg; |
ae3db24a | 2368 | |
1690e1eb | 2369 | if (!reg->pin_count) |
d9e86c0e | 2370 | avail = reg; |
ae3db24a DV |
2371 | } |
2372 | ||
d9e86c0e CW |
2373 | if (avail == NULL) |
2374 | return NULL; | |
ae3db24a DV |
2375 | |
2376 | /* None available, try to steal one or wait for a user to finish */ | |
d9e86c0e | 2377 | list_for_each_entry(reg, &dev_priv->mm.fence_list, lru_list) { |
1690e1eb | 2378 | if (reg->pin_count) |
ae3db24a DV |
2379 | continue; |
2380 | ||
8fe301ad | 2381 | return reg; |
ae3db24a DV |
2382 | } |
2383 | ||
8fe301ad | 2384 | return NULL; |
ae3db24a DV |
2385 | } |
2386 | ||
de151cf6 | 2387 | /** |
9a5a53b3 | 2388 | * i915_gem_object_get_fence - set up fencing for an object |
de151cf6 JB |
2389 | * @obj: object to map through a fence reg |
2390 | * | |
2391 | * When mapping objects through the GTT, userspace wants to be able to write | |
2392 | * to them without having to worry about swizzling if the object is tiled. | |
de151cf6 JB |
2393 | * This function walks the fence regs looking for a free one for @obj, |
2394 | * stealing one if it can't find any. | |
2395 | * | |
2396 | * It then sets up the reg based on the object's properties: address, pitch | |
2397 | * and tiling format. | |
9a5a53b3 CW |
2398 | * |
2399 | * For an untiled surface, this removes any existing fence. | |
de151cf6 | 2400 | */ |
8c4b8c3f | 2401 | int |
06d98131 | 2402 | i915_gem_object_get_fence(struct drm_i915_gem_object *obj) |
de151cf6 | 2403 | { |
05394f39 | 2404 | struct drm_device *dev = obj->base.dev; |
79e53945 | 2405 | struct drm_i915_private *dev_priv = dev->dev_private; |
14415745 | 2406 | bool enable = obj->tiling_mode != I915_TILING_NONE; |
d9e86c0e | 2407 | struct drm_i915_fence_reg *reg; |
ae3db24a | 2408 | int ret; |
de151cf6 | 2409 | |
14415745 CW |
2410 | /* Have we updated the tiling parameters upon the object and so |
2411 | * will need to serialise the write to the associated fence register? | |
2412 | */ | |
5d82e3e6 | 2413 | if (obj->fence_dirty) { |
14415745 CW |
2414 | ret = i915_gem_object_flush_fence(obj); |
2415 | if (ret) | |
2416 | return ret; | |
2417 | } | |
9a5a53b3 | 2418 | |
d9e86c0e | 2419 | /* Just update our place in the LRU if our fence is getting reused. */ |
05394f39 CW |
2420 | if (obj->fence_reg != I915_FENCE_REG_NONE) { |
2421 | reg = &dev_priv->fence_regs[obj->fence_reg]; | |
5d82e3e6 | 2422 | if (!obj->fence_dirty) { |
14415745 CW |
2423 | list_move_tail(®->lru_list, |
2424 | &dev_priv->mm.fence_list); | |
2425 | return 0; | |
2426 | } | |
2427 | } else if (enable) { | |
2428 | reg = i915_find_fence_reg(dev); | |
2429 | if (reg == NULL) | |
2430 | return -EDEADLK; | |
d9e86c0e | 2431 | |
14415745 CW |
2432 | if (reg->obj) { |
2433 | struct drm_i915_gem_object *old = reg->obj; | |
2434 | ||
2435 | ret = i915_gem_object_flush_fence(old); | |
29c5a587 CW |
2436 | if (ret) |
2437 | return ret; | |
2438 | ||
14415745 | 2439 | i915_gem_object_fence_lost(old); |
29c5a587 | 2440 | } |
14415745 | 2441 | } else |
a09ba7fa | 2442 | return 0; |
a09ba7fa | 2443 | |
14415745 | 2444 | i915_gem_object_update_fence(obj, reg, enable); |
5d82e3e6 | 2445 | obj->fence_dirty = false; |
14415745 | 2446 | |
9ce079e4 | 2447 | return 0; |
de151cf6 JB |
2448 | } |
2449 | ||
673a394b EA |
2450 | /** |
2451 | * Finds free space in the GTT aperture and binds the object there. | |
2452 | */ | |
2453 | static int | |
05394f39 | 2454 | i915_gem_object_bind_to_gtt(struct drm_i915_gem_object *obj, |
920afa77 | 2455 | unsigned alignment, |
75e9e915 | 2456 | bool map_and_fenceable) |
673a394b | 2457 | { |
05394f39 | 2458 | struct drm_device *dev = obj->base.dev; |
673a394b | 2459 | drm_i915_private_t *dev_priv = dev->dev_private; |
673a394b | 2460 | struct drm_mm_node *free_space; |
a00b10c3 | 2461 | gfp_t gfpmask = __GFP_NORETRY | __GFP_NOWARN; |
5e783301 | 2462 | u32 size, fence_size, fence_alignment, unfenced_alignment; |
75e9e915 | 2463 | bool mappable, fenceable; |
07f73f69 | 2464 | int ret; |
673a394b | 2465 | |
05394f39 | 2466 | if (obj->madv != I915_MADV_WILLNEED) { |
3ef94daa CW |
2467 | DRM_ERROR("Attempting to bind a purgeable object\n"); |
2468 | return -EINVAL; | |
2469 | } | |
2470 | ||
e28f8711 CW |
2471 | fence_size = i915_gem_get_gtt_size(dev, |
2472 | obj->base.size, | |
2473 | obj->tiling_mode); | |
2474 | fence_alignment = i915_gem_get_gtt_alignment(dev, | |
2475 | obj->base.size, | |
2476 | obj->tiling_mode); | |
2477 | unfenced_alignment = | |
2478 | i915_gem_get_unfenced_gtt_alignment(dev, | |
2479 | obj->base.size, | |
2480 | obj->tiling_mode); | |
a00b10c3 | 2481 | |
673a394b | 2482 | if (alignment == 0) |
5e783301 DV |
2483 | alignment = map_and_fenceable ? fence_alignment : |
2484 | unfenced_alignment; | |
75e9e915 | 2485 | if (map_and_fenceable && alignment & (fence_alignment - 1)) { |
673a394b EA |
2486 | DRM_ERROR("Invalid object alignment requested %u\n", alignment); |
2487 | return -EINVAL; | |
2488 | } | |
2489 | ||
05394f39 | 2490 | size = map_and_fenceable ? fence_size : obj->base.size; |
a00b10c3 | 2491 | |
654fc607 CW |
2492 | /* If the object is bigger than the entire aperture, reject it early |
2493 | * before evicting everything in a vain attempt to find space. | |
2494 | */ | |
05394f39 | 2495 | if (obj->base.size > |
75e9e915 | 2496 | (map_and_fenceable ? dev_priv->mm.gtt_mappable_end : dev_priv->mm.gtt_total)) { |
654fc607 CW |
2497 | DRM_ERROR("Attempting to bind an object larger than the aperture\n"); |
2498 | return -E2BIG; | |
2499 | } | |
2500 | ||
673a394b | 2501 | search_free: |
75e9e915 | 2502 | if (map_and_fenceable) |
920afa77 DV |
2503 | free_space = |
2504 | drm_mm_search_free_in_range(&dev_priv->mm.gtt_space, | |
a00b10c3 | 2505 | size, alignment, 0, |
920afa77 DV |
2506 | dev_priv->mm.gtt_mappable_end, |
2507 | 0); | |
2508 | else | |
2509 | free_space = drm_mm_search_free(&dev_priv->mm.gtt_space, | |
a00b10c3 | 2510 | size, alignment, 0); |
920afa77 DV |
2511 | |
2512 | if (free_space != NULL) { | |
75e9e915 | 2513 | if (map_and_fenceable) |
05394f39 | 2514 | obj->gtt_space = |
920afa77 | 2515 | drm_mm_get_block_range_generic(free_space, |
a00b10c3 | 2516 | size, alignment, 0, |
920afa77 DV |
2517 | dev_priv->mm.gtt_mappable_end, |
2518 | 0); | |
2519 | else | |
05394f39 | 2520 | obj->gtt_space = |
a00b10c3 | 2521 | drm_mm_get_block(free_space, size, alignment); |
920afa77 | 2522 | } |
05394f39 | 2523 | if (obj->gtt_space == NULL) { |
673a394b EA |
2524 | /* If the gtt is empty and we're still having trouble |
2525 | * fitting our object in, we're out of memory. | |
2526 | */ | |
75e9e915 DV |
2527 | ret = i915_gem_evict_something(dev, size, alignment, |
2528 | map_and_fenceable); | |
9731129c | 2529 | if (ret) |
673a394b | 2530 | return ret; |
9731129c | 2531 | |
673a394b EA |
2532 | goto search_free; |
2533 | } | |
2534 | ||
e5281ccd | 2535 | ret = i915_gem_object_get_pages_gtt(obj, gfpmask); |
673a394b | 2536 | if (ret) { |
05394f39 CW |
2537 | drm_mm_put_block(obj->gtt_space); |
2538 | obj->gtt_space = NULL; | |
07f73f69 CW |
2539 | |
2540 | if (ret == -ENOMEM) { | |
809b6334 CW |
2541 | /* first try to reclaim some memory by clearing the GTT */ |
2542 | ret = i915_gem_evict_everything(dev, false); | |
07f73f69 | 2543 | if (ret) { |
07f73f69 | 2544 | /* now try to shrink everyone else */ |
4bdadb97 CW |
2545 | if (gfpmask) { |
2546 | gfpmask = 0; | |
2547 | goto search_free; | |
07f73f69 CW |
2548 | } |
2549 | ||
809b6334 | 2550 | return -ENOMEM; |
07f73f69 CW |
2551 | } |
2552 | ||
2553 | goto search_free; | |
2554 | } | |
2555 | ||
673a394b EA |
2556 | return ret; |
2557 | } | |
2558 | ||
74163907 | 2559 | ret = i915_gem_gtt_prepare_object(obj); |
7c2e6fdf | 2560 | if (ret) { |
e5281ccd | 2561 | i915_gem_object_put_pages_gtt(obj); |
05394f39 CW |
2562 | drm_mm_put_block(obj->gtt_space); |
2563 | obj->gtt_space = NULL; | |
07f73f69 | 2564 | |
809b6334 | 2565 | if (i915_gem_evict_everything(dev, false)) |
07f73f69 | 2566 | return ret; |
07f73f69 CW |
2567 | |
2568 | goto search_free; | |
673a394b | 2569 | } |
673a394b | 2570 | |
0ebb9829 DV |
2571 | if (!dev_priv->mm.aliasing_ppgtt) |
2572 | i915_gem_gtt_bind_object(obj, obj->cache_level); | |
673a394b | 2573 | |
6299f992 | 2574 | list_add_tail(&obj->gtt_list, &dev_priv->mm.gtt_list); |
05394f39 | 2575 | list_add_tail(&obj->mm_list, &dev_priv->mm.inactive_list); |
bf1a1092 | 2576 | |
673a394b EA |
2577 | /* Assert that the object is not currently in any GPU domain. As it |
2578 | * wasn't in the GTT, there shouldn't be any way it could have been in | |
2579 | * a GPU cache | |
2580 | */ | |
05394f39 CW |
2581 | BUG_ON(obj->base.read_domains & I915_GEM_GPU_DOMAINS); |
2582 | BUG_ON(obj->base.write_domain & I915_GEM_GPU_DOMAINS); | |
673a394b | 2583 | |
6299f992 | 2584 | obj->gtt_offset = obj->gtt_space->start; |
1c5d22f7 | 2585 | |
75e9e915 | 2586 | fenceable = |
05394f39 | 2587 | obj->gtt_space->size == fence_size && |
0206e353 | 2588 | (obj->gtt_space->start & (fence_alignment - 1)) == 0; |
a00b10c3 | 2589 | |
75e9e915 | 2590 | mappable = |
05394f39 | 2591 | obj->gtt_offset + obj->base.size <= dev_priv->mm.gtt_mappable_end; |
a00b10c3 | 2592 | |
05394f39 | 2593 | obj->map_and_fenceable = mappable && fenceable; |
75e9e915 | 2594 | |
db53a302 | 2595 | trace_i915_gem_object_bind(obj, map_and_fenceable); |
673a394b EA |
2596 | return 0; |
2597 | } | |
2598 | ||
2599 | void | |
05394f39 | 2600 | i915_gem_clflush_object(struct drm_i915_gem_object *obj) |
673a394b | 2601 | { |
673a394b EA |
2602 | /* If we don't have a page list set up, then we're not pinned |
2603 | * to GPU, and we can ignore the cache flush because it'll happen | |
2604 | * again at bind time. | |
2605 | */ | |
05394f39 | 2606 | if (obj->pages == NULL) |
673a394b EA |
2607 | return; |
2608 | ||
9c23f7fc CW |
2609 | /* If the GPU is snooping the contents of the CPU cache, |
2610 | * we do not need to manually clear the CPU cache lines. However, | |
2611 | * the caches are only snooped when the render cache is | |
2612 | * flushed/invalidated. As we always have to emit invalidations | |
2613 | * and flushes when moving into and out of the RENDER domain, correct | |
2614 | * snooping behaviour occurs naturally as the result of our domain | |
2615 | * tracking. | |
2616 | */ | |
2617 | if (obj->cache_level != I915_CACHE_NONE) | |
2618 | return; | |
2619 | ||
1c5d22f7 | 2620 | trace_i915_gem_object_clflush(obj); |
cfa16a0d | 2621 | |
05394f39 | 2622 | drm_clflush_pages(obj->pages, obj->base.size / PAGE_SIZE); |
673a394b EA |
2623 | } |
2624 | ||
e47c68e9 | 2625 | /** Flushes any GPU write domain for the object if it's dirty. */ |
88241785 | 2626 | static int |
3619df03 | 2627 | i915_gem_object_flush_gpu_write_domain(struct drm_i915_gem_object *obj) |
e47c68e9 | 2628 | { |
05394f39 | 2629 | if ((obj->base.write_domain & I915_GEM_GPU_DOMAINS) == 0) |
88241785 | 2630 | return 0; |
e47c68e9 EA |
2631 | |
2632 | /* Queue the GPU write cache flushing we need. */ | |
db53a302 | 2633 | return i915_gem_flush_ring(obj->ring, 0, obj->base.write_domain); |
e47c68e9 EA |
2634 | } |
2635 | ||
2636 | /** Flushes the GTT write domain for the object if it's dirty. */ | |
2637 | static void | |
05394f39 | 2638 | i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj) |
e47c68e9 | 2639 | { |
1c5d22f7 CW |
2640 | uint32_t old_write_domain; |
2641 | ||
05394f39 | 2642 | if (obj->base.write_domain != I915_GEM_DOMAIN_GTT) |
e47c68e9 EA |
2643 | return; |
2644 | ||
63256ec5 | 2645 | /* No actual flushing is required for the GTT write domain. Writes |
e47c68e9 EA |
2646 | * to it immediately go to main memory as far as we know, so there's |
2647 | * no chipset flush. It also doesn't land in render cache. | |
63256ec5 CW |
2648 | * |
2649 | * However, we do have to enforce the order so that all writes through | |
2650 | * the GTT land before any writes to the device, such as updates to | |
2651 | * the GATT itself. | |
e47c68e9 | 2652 | */ |
63256ec5 CW |
2653 | wmb(); |
2654 | ||
05394f39 CW |
2655 | old_write_domain = obj->base.write_domain; |
2656 | obj->base.write_domain = 0; | |
1c5d22f7 CW |
2657 | |
2658 | trace_i915_gem_object_change_domain(obj, | |
05394f39 | 2659 | obj->base.read_domains, |
1c5d22f7 | 2660 | old_write_domain); |
e47c68e9 EA |
2661 | } |
2662 | ||
2663 | /** Flushes the CPU write domain for the object if it's dirty. */ | |
2664 | static void | |
05394f39 | 2665 | i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj) |
e47c68e9 | 2666 | { |
1c5d22f7 | 2667 | uint32_t old_write_domain; |
e47c68e9 | 2668 | |
05394f39 | 2669 | if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) |
e47c68e9 EA |
2670 | return; |
2671 | ||
2672 | i915_gem_clflush_object(obj); | |
40ce6575 | 2673 | intel_gtt_chipset_flush(); |
05394f39 CW |
2674 | old_write_domain = obj->base.write_domain; |
2675 | obj->base.write_domain = 0; | |
1c5d22f7 CW |
2676 | |
2677 | trace_i915_gem_object_change_domain(obj, | |
05394f39 | 2678 | obj->base.read_domains, |
1c5d22f7 | 2679 | old_write_domain); |
e47c68e9 EA |
2680 | } |
2681 | ||
2ef7eeaa EA |
2682 | /** |
2683 | * Moves a single object to the GTT read, and possibly write domain. | |
2684 | * | |
2685 | * This function returns when the move is complete, including waiting on | |
2686 | * flushes to occur. | |
2687 | */ | |
79e53945 | 2688 | int |
2021746e | 2689 | i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write) |
2ef7eeaa | 2690 | { |
8325a09d | 2691 | drm_i915_private_t *dev_priv = obj->base.dev->dev_private; |
1c5d22f7 | 2692 | uint32_t old_write_domain, old_read_domains; |
e47c68e9 | 2693 | int ret; |
2ef7eeaa | 2694 | |
02354392 | 2695 | /* Not valid to be called on unbound objects. */ |
05394f39 | 2696 | if (obj->gtt_space == NULL) |
02354392 EA |
2697 | return -EINVAL; |
2698 | ||
8d7e3de1 CW |
2699 | if (obj->base.write_domain == I915_GEM_DOMAIN_GTT) |
2700 | return 0; | |
2701 | ||
88241785 CW |
2702 | ret = i915_gem_object_flush_gpu_write_domain(obj); |
2703 | if (ret) | |
2704 | return ret; | |
2705 | ||
87ca9c8a | 2706 | if (obj->pending_gpu_write || write) { |
ce453d81 | 2707 | ret = i915_gem_object_wait_rendering(obj); |
87ca9c8a CW |
2708 | if (ret) |
2709 | return ret; | |
2710 | } | |
2dafb1e0 | 2711 | |
7213342d | 2712 | i915_gem_object_flush_cpu_write_domain(obj); |
1c5d22f7 | 2713 | |
05394f39 CW |
2714 | old_write_domain = obj->base.write_domain; |
2715 | old_read_domains = obj->base.read_domains; | |
1c5d22f7 | 2716 | |
e47c68e9 EA |
2717 | /* It should now be out of any other write domains, and we can update |
2718 | * the domain values for our changes. | |
2719 | */ | |
05394f39 CW |
2720 | BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_GTT) != 0); |
2721 | obj->base.read_domains |= I915_GEM_DOMAIN_GTT; | |
e47c68e9 | 2722 | if (write) { |
05394f39 CW |
2723 | obj->base.read_domains = I915_GEM_DOMAIN_GTT; |
2724 | obj->base.write_domain = I915_GEM_DOMAIN_GTT; | |
2725 | obj->dirty = 1; | |
2ef7eeaa EA |
2726 | } |
2727 | ||
1c5d22f7 CW |
2728 | trace_i915_gem_object_change_domain(obj, |
2729 | old_read_domains, | |
2730 | old_write_domain); | |
2731 | ||
8325a09d CW |
2732 | /* And bump the LRU for this access */ |
2733 | if (i915_gem_object_is_inactive(obj)) | |
2734 | list_move_tail(&obj->mm_list, &dev_priv->mm.inactive_list); | |
2735 | ||
e47c68e9 EA |
2736 | return 0; |
2737 | } | |
2738 | ||
e4ffd173 CW |
2739 | int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj, |
2740 | enum i915_cache_level cache_level) | |
2741 | { | |
7bddb01f DV |
2742 | struct drm_device *dev = obj->base.dev; |
2743 | drm_i915_private_t *dev_priv = dev->dev_private; | |
e4ffd173 CW |
2744 | int ret; |
2745 | ||
2746 | if (obj->cache_level == cache_level) | |
2747 | return 0; | |
2748 | ||
2749 | if (obj->pin_count) { | |
2750 | DRM_DEBUG("can not change the cache level of pinned objects\n"); | |
2751 | return -EBUSY; | |
2752 | } | |
2753 | ||
2754 | if (obj->gtt_space) { | |
2755 | ret = i915_gem_object_finish_gpu(obj); | |
2756 | if (ret) | |
2757 | return ret; | |
2758 | ||
2759 | i915_gem_object_finish_gtt(obj); | |
2760 | ||
2761 | /* Before SandyBridge, you could not use tiling or fence | |
2762 | * registers with snooped memory, so relinquish any fences | |
2763 | * currently pointing to our region in the aperture. | |
2764 | */ | |
2765 | if (INTEL_INFO(obj->base.dev)->gen < 6) { | |
2766 | ret = i915_gem_object_put_fence(obj); | |
2767 | if (ret) | |
2768 | return ret; | |
2769 | } | |
2770 | ||
74898d7e DV |
2771 | if (obj->has_global_gtt_mapping) |
2772 | i915_gem_gtt_bind_object(obj, cache_level); | |
7bddb01f DV |
2773 | if (obj->has_aliasing_ppgtt_mapping) |
2774 | i915_ppgtt_bind_object(dev_priv->mm.aliasing_ppgtt, | |
2775 | obj, cache_level); | |
e4ffd173 CW |
2776 | } |
2777 | ||
2778 | if (cache_level == I915_CACHE_NONE) { | |
2779 | u32 old_read_domains, old_write_domain; | |
2780 | ||
2781 | /* If we're coming from LLC cached, then we haven't | |
2782 | * actually been tracking whether the data is in the | |
2783 | * CPU cache or not, since we only allow one bit set | |
2784 | * in obj->write_domain and have been skipping the clflushes. | |
2785 | * Just set it to the CPU cache for now. | |
2786 | */ | |
2787 | WARN_ON(obj->base.write_domain & ~I915_GEM_DOMAIN_CPU); | |
2788 | WARN_ON(obj->base.read_domains & ~I915_GEM_DOMAIN_CPU); | |
2789 | ||
2790 | old_read_domains = obj->base.read_domains; | |
2791 | old_write_domain = obj->base.write_domain; | |
2792 | ||
2793 | obj->base.read_domains = I915_GEM_DOMAIN_CPU; | |
2794 | obj->base.write_domain = I915_GEM_DOMAIN_CPU; | |
2795 | ||
2796 | trace_i915_gem_object_change_domain(obj, | |
2797 | old_read_domains, | |
2798 | old_write_domain); | |
2799 | } | |
2800 | ||
2801 | obj->cache_level = cache_level; | |
2802 | return 0; | |
2803 | } | |
2804 | ||
b9241ea3 | 2805 | /* |
2da3b9b9 CW |
2806 | * Prepare buffer for display plane (scanout, cursors, etc). |
2807 | * Can be called from an uninterruptible phase (modesetting) and allows | |
2808 | * any flushes to be pipelined (for pageflips). | |
b9241ea3 ZW |
2809 | */ |
2810 | int | |
2da3b9b9 CW |
2811 | i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj, |
2812 | u32 alignment, | |
919926ae | 2813 | struct intel_ring_buffer *pipelined) |
b9241ea3 | 2814 | { |
2da3b9b9 | 2815 | u32 old_read_domains, old_write_domain; |
b9241ea3 ZW |
2816 | int ret; |
2817 | ||
88241785 CW |
2818 | ret = i915_gem_object_flush_gpu_write_domain(obj); |
2819 | if (ret) | |
2820 | return ret; | |
2821 | ||
0be73284 | 2822 | if (pipelined != obj->ring) { |
2911a35b BW |
2823 | ret = i915_gem_object_sync(obj, pipelined); |
2824 | if (ret) | |
b9241ea3 ZW |
2825 | return ret; |
2826 | } | |
2827 | ||
a7ef0640 EA |
2828 | /* The display engine is not coherent with the LLC cache on gen6. As |
2829 | * a result, we make sure that the pinning that is about to occur is | |
2830 | * done with uncached PTEs. This is lowest common denominator for all | |
2831 | * chipsets. | |
2832 | * | |
2833 | * However for gen6+, we could do better by using the GFDT bit instead | |
2834 | * of uncaching, which would allow us to flush all the LLC-cached data | |
2835 | * with that bit in the PTE to main memory with just one PIPE_CONTROL. | |
2836 | */ | |
2837 | ret = i915_gem_object_set_cache_level(obj, I915_CACHE_NONE); | |
2838 | if (ret) | |
2839 | return ret; | |
2840 | ||
2da3b9b9 CW |
2841 | /* As the user may map the buffer once pinned in the display plane |
2842 | * (e.g. libkms for the bootup splash), we have to ensure that we | |
2843 | * always use map_and_fenceable for all scanout buffers. | |
2844 | */ | |
2845 | ret = i915_gem_object_pin(obj, alignment, true); | |
2846 | if (ret) | |
2847 | return ret; | |
2848 | ||
b118c1e3 CW |
2849 | i915_gem_object_flush_cpu_write_domain(obj); |
2850 | ||
2da3b9b9 | 2851 | old_write_domain = obj->base.write_domain; |
05394f39 | 2852 | old_read_domains = obj->base.read_domains; |
2da3b9b9 CW |
2853 | |
2854 | /* It should now be out of any other write domains, and we can update | |
2855 | * the domain values for our changes. | |
2856 | */ | |
2857 | BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_GTT) != 0); | |
05394f39 | 2858 | obj->base.read_domains |= I915_GEM_DOMAIN_GTT; |
b9241ea3 ZW |
2859 | |
2860 | trace_i915_gem_object_change_domain(obj, | |
2861 | old_read_domains, | |
2da3b9b9 | 2862 | old_write_domain); |
b9241ea3 ZW |
2863 | |
2864 | return 0; | |
2865 | } | |
2866 | ||
85345517 | 2867 | int |
a8198eea | 2868 | i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj) |
85345517 | 2869 | { |
88241785 CW |
2870 | int ret; |
2871 | ||
a8198eea | 2872 | if ((obj->base.read_domains & I915_GEM_GPU_DOMAINS) == 0) |
85345517 CW |
2873 | return 0; |
2874 | ||
88241785 | 2875 | if (obj->base.write_domain & I915_GEM_GPU_DOMAINS) { |
db53a302 | 2876 | ret = i915_gem_flush_ring(obj->ring, 0, obj->base.write_domain); |
88241785 CW |
2877 | if (ret) |
2878 | return ret; | |
2879 | } | |
85345517 | 2880 | |
c501ae7f CW |
2881 | ret = i915_gem_object_wait_rendering(obj); |
2882 | if (ret) | |
2883 | return ret; | |
2884 | ||
a8198eea CW |
2885 | /* Ensure that we invalidate the GPU's caches and TLBs. */ |
2886 | obj->base.read_domains &= ~I915_GEM_GPU_DOMAINS; | |
c501ae7f | 2887 | return 0; |
85345517 CW |
2888 | } |
2889 | ||
e47c68e9 EA |
2890 | /** |
2891 | * Moves a single object to the CPU read, and possibly write domain. | |
2892 | * | |
2893 | * This function returns when the move is complete, including waiting on | |
2894 | * flushes to occur. | |
2895 | */ | |
dabdfe02 | 2896 | int |
919926ae | 2897 | i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write) |
e47c68e9 | 2898 | { |
1c5d22f7 | 2899 | uint32_t old_write_domain, old_read_domains; |
e47c68e9 EA |
2900 | int ret; |
2901 | ||
8d7e3de1 CW |
2902 | if (obj->base.write_domain == I915_GEM_DOMAIN_CPU) |
2903 | return 0; | |
2904 | ||
88241785 CW |
2905 | ret = i915_gem_object_flush_gpu_write_domain(obj); |
2906 | if (ret) | |
2907 | return ret; | |
2908 | ||
f8413190 CW |
2909 | if (write || obj->pending_gpu_write) { |
2910 | ret = i915_gem_object_wait_rendering(obj); | |
2911 | if (ret) | |
2912 | return ret; | |
2913 | } | |
2ef7eeaa | 2914 | |
e47c68e9 | 2915 | i915_gem_object_flush_gtt_write_domain(obj); |
2ef7eeaa | 2916 | |
05394f39 CW |
2917 | old_write_domain = obj->base.write_domain; |
2918 | old_read_domains = obj->base.read_domains; | |
1c5d22f7 | 2919 | |
e47c68e9 | 2920 | /* Flush the CPU cache if it's still invalid. */ |
05394f39 | 2921 | if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0) { |
2ef7eeaa | 2922 | i915_gem_clflush_object(obj); |
2ef7eeaa | 2923 | |
05394f39 | 2924 | obj->base.read_domains |= I915_GEM_DOMAIN_CPU; |
2ef7eeaa EA |
2925 | } |
2926 | ||
2927 | /* It should now be out of any other write domains, and we can update | |
2928 | * the domain values for our changes. | |
2929 | */ | |
05394f39 | 2930 | BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_CPU) != 0); |
e47c68e9 EA |
2931 | |
2932 | /* If we're writing through the CPU, then the GPU read domains will | |
2933 | * need to be invalidated at next use. | |
2934 | */ | |
2935 | if (write) { | |
05394f39 CW |
2936 | obj->base.read_domains = I915_GEM_DOMAIN_CPU; |
2937 | obj->base.write_domain = I915_GEM_DOMAIN_CPU; | |
e47c68e9 | 2938 | } |
2ef7eeaa | 2939 | |
1c5d22f7 CW |
2940 | trace_i915_gem_object_change_domain(obj, |
2941 | old_read_domains, | |
2942 | old_write_domain); | |
2943 | ||
2ef7eeaa EA |
2944 | return 0; |
2945 | } | |
2946 | ||
673a394b EA |
2947 | /* Throttle our rendering by waiting until the ring has completed our requests |
2948 | * emitted over 20 msec ago. | |
2949 | * | |
b962442e EA |
2950 | * Note that if we were to use the current jiffies each time around the loop, |
2951 | * we wouldn't escape the function with any frames outstanding if the time to | |
2952 | * render a frame was over 20ms. | |
2953 | * | |
673a394b EA |
2954 | * This should get us reasonable parallelism between CPU and GPU but also |
2955 | * relatively low latency when blocking on a particular request to finish. | |
2956 | */ | |
40a5f0de | 2957 | static int |
f787a5f5 | 2958 | i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file) |
40a5f0de | 2959 | { |
f787a5f5 CW |
2960 | struct drm_i915_private *dev_priv = dev->dev_private; |
2961 | struct drm_i915_file_private *file_priv = file->driver_priv; | |
b962442e | 2962 | unsigned long recent_enough = jiffies - msecs_to_jiffies(20); |
f787a5f5 CW |
2963 | struct drm_i915_gem_request *request; |
2964 | struct intel_ring_buffer *ring = NULL; | |
2965 | u32 seqno = 0; | |
2966 | int ret; | |
93533c29 | 2967 | |
e110e8d6 CW |
2968 | if (atomic_read(&dev_priv->mm.wedged)) |
2969 | return -EIO; | |
2970 | ||
1c25595f | 2971 | spin_lock(&file_priv->mm.lock); |
f787a5f5 | 2972 | list_for_each_entry(request, &file_priv->mm.request_list, client_list) { |
b962442e EA |
2973 | if (time_after_eq(request->emitted_jiffies, recent_enough)) |
2974 | break; | |
40a5f0de | 2975 | |
f787a5f5 CW |
2976 | ring = request->ring; |
2977 | seqno = request->seqno; | |
b962442e | 2978 | } |
1c25595f | 2979 | spin_unlock(&file_priv->mm.lock); |
40a5f0de | 2980 | |
f787a5f5 CW |
2981 | if (seqno == 0) |
2982 | return 0; | |
2bc43b5c | 2983 | |
3b88cc0d | 2984 | ret = __wait_seqno(ring, seqno, true); |
f787a5f5 CW |
2985 | if (ret == 0) |
2986 | queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, 0); | |
40a5f0de EA |
2987 | |
2988 | return ret; | |
2989 | } | |
2990 | ||
673a394b | 2991 | int |
05394f39 CW |
2992 | i915_gem_object_pin(struct drm_i915_gem_object *obj, |
2993 | uint32_t alignment, | |
75e9e915 | 2994 | bool map_and_fenceable) |
673a394b | 2995 | { |
673a394b EA |
2996 | int ret; |
2997 | ||
05394f39 | 2998 | BUG_ON(obj->pin_count == DRM_I915_GEM_OBJECT_MAX_PIN_COUNT); |
ac0c6b5a | 2999 | |
05394f39 CW |
3000 | if (obj->gtt_space != NULL) { |
3001 | if ((alignment && obj->gtt_offset & (alignment - 1)) || | |
3002 | (map_and_fenceable && !obj->map_and_fenceable)) { | |
3003 | WARN(obj->pin_count, | |
ae7d49d8 | 3004 | "bo is already pinned with incorrect alignment:" |
75e9e915 DV |
3005 | " offset=%x, req.alignment=%x, req.map_and_fenceable=%d," |
3006 | " obj->map_and_fenceable=%d\n", | |
05394f39 | 3007 | obj->gtt_offset, alignment, |
75e9e915 | 3008 | map_and_fenceable, |
05394f39 | 3009 | obj->map_and_fenceable); |
ac0c6b5a CW |
3010 | ret = i915_gem_object_unbind(obj); |
3011 | if (ret) | |
3012 | return ret; | |
3013 | } | |
3014 | } | |
3015 | ||
05394f39 | 3016 | if (obj->gtt_space == NULL) { |
a00b10c3 | 3017 | ret = i915_gem_object_bind_to_gtt(obj, alignment, |
75e9e915 | 3018 | map_and_fenceable); |
9731129c | 3019 | if (ret) |
673a394b | 3020 | return ret; |
22c344e9 | 3021 | } |
76446cac | 3022 | |
74898d7e DV |
3023 | if (!obj->has_global_gtt_mapping && map_and_fenceable) |
3024 | i915_gem_gtt_bind_object(obj, obj->cache_level); | |
3025 | ||
1b50247a | 3026 | obj->pin_count++; |
6299f992 | 3027 | obj->pin_mappable |= map_and_fenceable; |
673a394b EA |
3028 | |
3029 | return 0; | |
3030 | } | |
3031 | ||
3032 | void | |
05394f39 | 3033 | i915_gem_object_unpin(struct drm_i915_gem_object *obj) |
673a394b | 3034 | { |
05394f39 CW |
3035 | BUG_ON(obj->pin_count == 0); |
3036 | BUG_ON(obj->gtt_space == NULL); | |
673a394b | 3037 | |
1b50247a | 3038 | if (--obj->pin_count == 0) |
6299f992 | 3039 | obj->pin_mappable = false; |
673a394b EA |
3040 | } |
3041 | ||
3042 | int | |
3043 | i915_gem_pin_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 3044 | struct drm_file *file) |
673a394b EA |
3045 | { |
3046 | struct drm_i915_gem_pin *args = data; | |
05394f39 | 3047 | struct drm_i915_gem_object *obj; |
673a394b EA |
3048 | int ret; |
3049 | ||
1d7cfea1 CW |
3050 | ret = i915_mutex_lock_interruptible(dev); |
3051 | if (ret) | |
3052 | return ret; | |
673a394b | 3053 | |
05394f39 | 3054 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 3055 | if (&obj->base == NULL) { |
1d7cfea1 CW |
3056 | ret = -ENOENT; |
3057 | goto unlock; | |
673a394b | 3058 | } |
673a394b | 3059 | |
05394f39 | 3060 | if (obj->madv != I915_MADV_WILLNEED) { |
bb6baf76 | 3061 | DRM_ERROR("Attempting to pin a purgeable buffer\n"); |
1d7cfea1 CW |
3062 | ret = -EINVAL; |
3063 | goto out; | |
3ef94daa CW |
3064 | } |
3065 | ||
05394f39 | 3066 | if (obj->pin_filp != NULL && obj->pin_filp != file) { |
79e53945 JB |
3067 | DRM_ERROR("Already pinned in i915_gem_pin_ioctl(): %d\n", |
3068 | args->handle); | |
1d7cfea1 CW |
3069 | ret = -EINVAL; |
3070 | goto out; | |
79e53945 JB |
3071 | } |
3072 | ||
05394f39 CW |
3073 | obj->user_pin_count++; |
3074 | obj->pin_filp = file; | |
3075 | if (obj->user_pin_count == 1) { | |
75e9e915 | 3076 | ret = i915_gem_object_pin(obj, args->alignment, true); |
1d7cfea1 CW |
3077 | if (ret) |
3078 | goto out; | |
673a394b EA |
3079 | } |
3080 | ||
3081 | /* XXX - flush the CPU caches for pinned objects | |
3082 | * as the X server doesn't manage domains yet | |
3083 | */ | |
e47c68e9 | 3084 | i915_gem_object_flush_cpu_write_domain(obj); |
05394f39 | 3085 | args->offset = obj->gtt_offset; |
1d7cfea1 | 3086 | out: |
05394f39 | 3087 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 3088 | unlock: |
673a394b | 3089 | mutex_unlock(&dev->struct_mutex); |
1d7cfea1 | 3090 | return ret; |
673a394b EA |
3091 | } |
3092 | ||
3093 | int | |
3094 | i915_gem_unpin_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 3095 | struct drm_file *file) |
673a394b EA |
3096 | { |
3097 | struct drm_i915_gem_pin *args = data; | |
05394f39 | 3098 | struct drm_i915_gem_object *obj; |
76c1dec1 | 3099 | int ret; |
673a394b | 3100 | |
1d7cfea1 CW |
3101 | ret = i915_mutex_lock_interruptible(dev); |
3102 | if (ret) | |
3103 | return ret; | |
673a394b | 3104 | |
05394f39 | 3105 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 3106 | if (&obj->base == NULL) { |
1d7cfea1 CW |
3107 | ret = -ENOENT; |
3108 | goto unlock; | |
673a394b | 3109 | } |
76c1dec1 | 3110 | |
05394f39 | 3111 | if (obj->pin_filp != file) { |
79e53945 JB |
3112 | DRM_ERROR("Not pinned by caller in i915_gem_pin_ioctl(): %d\n", |
3113 | args->handle); | |
1d7cfea1 CW |
3114 | ret = -EINVAL; |
3115 | goto out; | |
79e53945 | 3116 | } |
05394f39 CW |
3117 | obj->user_pin_count--; |
3118 | if (obj->user_pin_count == 0) { | |
3119 | obj->pin_filp = NULL; | |
79e53945 JB |
3120 | i915_gem_object_unpin(obj); |
3121 | } | |
673a394b | 3122 | |
1d7cfea1 | 3123 | out: |
05394f39 | 3124 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 3125 | unlock: |
673a394b | 3126 | mutex_unlock(&dev->struct_mutex); |
1d7cfea1 | 3127 | return ret; |
673a394b EA |
3128 | } |
3129 | ||
3130 | int | |
3131 | i915_gem_busy_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 3132 | struct drm_file *file) |
673a394b EA |
3133 | { |
3134 | struct drm_i915_gem_busy *args = data; | |
05394f39 | 3135 | struct drm_i915_gem_object *obj; |
30dbf0c0 CW |
3136 | int ret; |
3137 | ||
76c1dec1 | 3138 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 3139 | if (ret) |
76c1dec1 | 3140 | return ret; |
673a394b | 3141 | |
05394f39 | 3142 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 3143 | if (&obj->base == NULL) { |
1d7cfea1 CW |
3144 | ret = -ENOENT; |
3145 | goto unlock; | |
673a394b | 3146 | } |
d1b851fc | 3147 | |
0be555b6 CW |
3148 | /* Count all active objects as busy, even if they are currently not used |
3149 | * by the gpu. Users of this interface expect objects to eventually | |
3150 | * become non-busy without any further actions, therefore emit any | |
3151 | * necessary flushes here. | |
c4de0a5d | 3152 | */ |
05394f39 | 3153 | args->busy = obj->active; |
0be555b6 CW |
3154 | if (args->busy) { |
3155 | /* Unconditionally flush objects, even when the gpu still uses this | |
3156 | * object. Userspace calling this function indicates that it wants to | |
3157 | * use this buffer rather sooner than later, so issuing the required | |
3158 | * flush earlier is beneficial. | |
3159 | */ | |
1a1c6976 | 3160 | if (obj->base.write_domain & I915_GEM_GPU_DOMAINS) { |
db53a302 | 3161 | ret = i915_gem_flush_ring(obj->ring, |
88241785 | 3162 | 0, obj->base.write_domain); |
1a1c6976 CW |
3163 | } else if (obj->ring->outstanding_lazy_request == |
3164 | obj->last_rendering_seqno) { | |
3165 | struct drm_i915_gem_request *request; | |
3166 | ||
7a194876 CW |
3167 | /* This ring is not being cleared by active usage, |
3168 | * so emit a request to do so. | |
3169 | */ | |
1a1c6976 | 3170 | request = kzalloc(sizeof(*request), GFP_KERNEL); |
457eafce | 3171 | if (request) { |
0206e353 | 3172 | ret = i915_add_request(obj->ring, NULL, request); |
457eafce RM |
3173 | if (ret) |
3174 | kfree(request); | |
3175 | } else | |
7a194876 CW |
3176 | ret = -ENOMEM; |
3177 | } | |
0be555b6 CW |
3178 | |
3179 | /* Update the active list for the hardware's current position. | |
3180 | * Otherwise this only updates on a delayed timer or when irqs | |
3181 | * are actually unmasked, and our working set ends up being | |
3182 | * larger than required. | |
3183 | */ | |
db53a302 | 3184 | i915_gem_retire_requests_ring(obj->ring); |
0be555b6 | 3185 | |
05394f39 | 3186 | args->busy = obj->active; |
0be555b6 | 3187 | } |
673a394b | 3188 | |
05394f39 | 3189 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 3190 | unlock: |
673a394b | 3191 | mutex_unlock(&dev->struct_mutex); |
1d7cfea1 | 3192 | return ret; |
673a394b EA |
3193 | } |
3194 | ||
3195 | int | |
3196 | i915_gem_throttle_ioctl(struct drm_device *dev, void *data, | |
3197 | struct drm_file *file_priv) | |
3198 | { | |
0206e353 | 3199 | return i915_gem_ring_throttle(dev, file_priv); |
673a394b EA |
3200 | } |
3201 | ||
3ef94daa CW |
3202 | int |
3203 | i915_gem_madvise_ioctl(struct drm_device *dev, void *data, | |
3204 | struct drm_file *file_priv) | |
3205 | { | |
3206 | struct drm_i915_gem_madvise *args = data; | |
05394f39 | 3207 | struct drm_i915_gem_object *obj; |
76c1dec1 | 3208 | int ret; |
3ef94daa CW |
3209 | |
3210 | switch (args->madv) { | |
3211 | case I915_MADV_DONTNEED: | |
3212 | case I915_MADV_WILLNEED: | |
3213 | break; | |
3214 | default: | |
3215 | return -EINVAL; | |
3216 | } | |
3217 | ||
1d7cfea1 CW |
3218 | ret = i915_mutex_lock_interruptible(dev); |
3219 | if (ret) | |
3220 | return ret; | |
3221 | ||
05394f39 | 3222 | obj = to_intel_bo(drm_gem_object_lookup(dev, file_priv, args->handle)); |
c8725226 | 3223 | if (&obj->base == NULL) { |
1d7cfea1 CW |
3224 | ret = -ENOENT; |
3225 | goto unlock; | |
3ef94daa | 3226 | } |
3ef94daa | 3227 | |
05394f39 | 3228 | if (obj->pin_count) { |
1d7cfea1 CW |
3229 | ret = -EINVAL; |
3230 | goto out; | |
3ef94daa CW |
3231 | } |
3232 | ||
05394f39 CW |
3233 | if (obj->madv != __I915_MADV_PURGED) |
3234 | obj->madv = args->madv; | |
3ef94daa | 3235 | |
2d7ef395 | 3236 | /* if the object is no longer bound, discard its backing storage */ |
05394f39 CW |
3237 | if (i915_gem_object_is_purgeable(obj) && |
3238 | obj->gtt_space == NULL) | |
2d7ef395 CW |
3239 | i915_gem_object_truncate(obj); |
3240 | ||
05394f39 | 3241 | args->retained = obj->madv != __I915_MADV_PURGED; |
bb6baf76 | 3242 | |
1d7cfea1 | 3243 | out: |
05394f39 | 3244 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 3245 | unlock: |
3ef94daa | 3246 | mutex_unlock(&dev->struct_mutex); |
1d7cfea1 | 3247 | return ret; |
3ef94daa CW |
3248 | } |
3249 | ||
05394f39 CW |
3250 | struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev, |
3251 | size_t size) | |
ac52bc56 | 3252 | { |
73aa808f | 3253 | struct drm_i915_private *dev_priv = dev->dev_private; |
c397b908 | 3254 | struct drm_i915_gem_object *obj; |
5949eac4 | 3255 | struct address_space *mapping; |
ac52bc56 | 3256 | |
c397b908 DV |
3257 | obj = kzalloc(sizeof(*obj), GFP_KERNEL); |
3258 | if (obj == NULL) | |
3259 | return NULL; | |
673a394b | 3260 | |
c397b908 DV |
3261 | if (drm_gem_object_init(dev, &obj->base, size) != 0) { |
3262 | kfree(obj); | |
3263 | return NULL; | |
3264 | } | |
673a394b | 3265 | |
5949eac4 HD |
3266 | mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping; |
3267 | mapping_set_gfp_mask(mapping, GFP_HIGHUSER | __GFP_RECLAIMABLE); | |
3268 | ||
73aa808f CW |
3269 | i915_gem_info_add_obj(dev_priv, size); |
3270 | ||
c397b908 DV |
3271 | obj->base.write_domain = I915_GEM_DOMAIN_CPU; |
3272 | obj->base.read_domains = I915_GEM_DOMAIN_CPU; | |
673a394b | 3273 | |
3d29b842 ED |
3274 | if (HAS_LLC(dev)) { |
3275 | /* On some devices, we can have the GPU use the LLC (the CPU | |
a1871112 EA |
3276 | * cache) for about a 10% performance improvement |
3277 | * compared to uncached. Graphics requests other than | |
3278 | * display scanout are coherent with the CPU in | |
3279 | * accessing this cache. This means in this mode we | |
3280 | * don't need to clflush on the CPU side, and on the | |
3281 | * GPU side we only need to flush internal caches to | |
3282 | * get data visible to the CPU. | |
3283 | * | |
3284 | * However, we maintain the display planes as UC, and so | |
3285 | * need to rebind when first used as such. | |
3286 | */ | |
3287 | obj->cache_level = I915_CACHE_LLC; | |
3288 | } else | |
3289 | obj->cache_level = I915_CACHE_NONE; | |
3290 | ||
62b8b215 | 3291 | obj->base.driver_private = NULL; |
c397b908 | 3292 | obj->fence_reg = I915_FENCE_REG_NONE; |
69dc4987 | 3293 | INIT_LIST_HEAD(&obj->mm_list); |
93a37f20 | 3294 | INIT_LIST_HEAD(&obj->gtt_list); |
69dc4987 | 3295 | INIT_LIST_HEAD(&obj->ring_list); |
432e58ed | 3296 | INIT_LIST_HEAD(&obj->exec_list); |
c397b908 | 3297 | INIT_LIST_HEAD(&obj->gpu_write_list); |
c397b908 | 3298 | obj->madv = I915_MADV_WILLNEED; |
75e9e915 DV |
3299 | /* Avoid an unnecessary call to unbind on the first bind. */ |
3300 | obj->map_and_fenceable = true; | |
de151cf6 | 3301 | |
05394f39 | 3302 | return obj; |
c397b908 DV |
3303 | } |
3304 | ||
3305 | int i915_gem_init_object(struct drm_gem_object *obj) | |
3306 | { | |
3307 | BUG(); | |
de151cf6 | 3308 | |
673a394b EA |
3309 | return 0; |
3310 | } | |
3311 | ||
1488fc08 | 3312 | void i915_gem_free_object(struct drm_gem_object *gem_obj) |
673a394b | 3313 | { |
1488fc08 | 3314 | struct drm_i915_gem_object *obj = to_intel_bo(gem_obj); |
05394f39 | 3315 | struct drm_device *dev = obj->base.dev; |
be72615b | 3316 | drm_i915_private_t *dev_priv = dev->dev_private; |
673a394b | 3317 | |
26e12f89 CW |
3318 | trace_i915_gem_object_destroy(obj); |
3319 | ||
1488fc08 CW |
3320 | if (obj->phys_obj) |
3321 | i915_gem_detach_phys_object(dev, obj); | |
3322 | ||
3323 | obj->pin_count = 0; | |
3324 | if (WARN_ON(i915_gem_object_unbind(obj) == -ERESTARTSYS)) { | |
3325 | bool was_interruptible; | |
3326 | ||
3327 | was_interruptible = dev_priv->mm.interruptible; | |
3328 | dev_priv->mm.interruptible = false; | |
3329 | ||
3330 | WARN_ON(i915_gem_object_unbind(obj)); | |
3331 | ||
3332 | dev_priv->mm.interruptible = was_interruptible; | |
3333 | } | |
3334 | ||
05394f39 | 3335 | if (obj->base.map_list.map) |
b464e9a2 | 3336 | drm_gem_free_mmap_offset(&obj->base); |
de151cf6 | 3337 | |
05394f39 CW |
3338 | drm_gem_object_release(&obj->base); |
3339 | i915_gem_info_remove_obj(dev_priv, obj->base.size); | |
c397b908 | 3340 | |
05394f39 CW |
3341 | kfree(obj->bit_17); |
3342 | kfree(obj); | |
673a394b EA |
3343 | } |
3344 | ||
29105ccc CW |
3345 | int |
3346 | i915_gem_idle(struct drm_device *dev) | |
3347 | { | |
3348 | drm_i915_private_t *dev_priv = dev->dev_private; | |
3349 | int ret; | |
28dfe52a | 3350 | |
29105ccc | 3351 | mutex_lock(&dev->struct_mutex); |
1c5d22f7 | 3352 | |
87acb0a5 | 3353 | if (dev_priv->mm.suspended) { |
29105ccc CW |
3354 | mutex_unlock(&dev->struct_mutex); |
3355 | return 0; | |
28dfe52a EA |
3356 | } |
3357 | ||
b2da9fe5 | 3358 | ret = i915_gpu_idle(dev); |
6dbe2772 KP |
3359 | if (ret) { |
3360 | mutex_unlock(&dev->struct_mutex); | |
673a394b | 3361 | return ret; |
6dbe2772 | 3362 | } |
b2da9fe5 | 3363 | i915_gem_retire_requests(dev); |
673a394b | 3364 | |
29105ccc | 3365 | /* Under UMS, be paranoid and evict. */ |
a39d7efc CW |
3366 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) |
3367 | i915_gem_evict_everything(dev, false); | |
29105ccc | 3368 | |
312817a3 CW |
3369 | i915_gem_reset_fences(dev); |
3370 | ||
29105ccc CW |
3371 | /* Hack! Don't let anybody do execbuf while we don't control the chip. |
3372 | * We need to replace this with a semaphore, or something. | |
3373 | * And not confound mm.suspended! | |
3374 | */ | |
3375 | dev_priv->mm.suspended = 1; | |
bc0c7f14 | 3376 | del_timer_sync(&dev_priv->hangcheck_timer); |
29105ccc CW |
3377 | |
3378 | i915_kernel_lost_context(dev); | |
6dbe2772 | 3379 | i915_gem_cleanup_ringbuffer(dev); |
29105ccc | 3380 | |
6dbe2772 KP |
3381 | mutex_unlock(&dev->struct_mutex); |
3382 | ||
29105ccc CW |
3383 | /* Cancel the retire work handler, which should be idle now. */ |
3384 | cancel_delayed_work_sync(&dev_priv->mm.retire_work); | |
3385 | ||
673a394b EA |
3386 | return 0; |
3387 | } | |
3388 | ||
f691e2f4 DV |
3389 | void i915_gem_init_swizzling(struct drm_device *dev) |
3390 | { | |
3391 | drm_i915_private_t *dev_priv = dev->dev_private; | |
3392 | ||
11782b02 | 3393 | if (INTEL_INFO(dev)->gen < 5 || |
f691e2f4 DV |
3394 | dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_NONE) |
3395 | return; | |
3396 | ||
3397 | I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) | | |
3398 | DISP_TILE_SURFACE_SWIZZLING); | |
3399 | ||
11782b02 DV |
3400 | if (IS_GEN5(dev)) |
3401 | return; | |
3402 | ||
f691e2f4 DV |
3403 | I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_SWZCTL); |
3404 | if (IS_GEN6(dev)) | |
6b26c86d | 3405 | I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB)); |
f691e2f4 | 3406 | else |
6b26c86d | 3407 | I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB)); |
f691e2f4 | 3408 | } |
e21af88d DV |
3409 | |
3410 | void i915_gem_init_ppgtt(struct drm_device *dev) | |
3411 | { | |
3412 | drm_i915_private_t *dev_priv = dev->dev_private; | |
3413 | uint32_t pd_offset; | |
3414 | struct intel_ring_buffer *ring; | |
55a254ac DV |
3415 | struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt; |
3416 | uint32_t __iomem *pd_addr; | |
3417 | uint32_t pd_entry; | |
e21af88d DV |
3418 | int i; |
3419 | ||
3420 | if (!dev_priv->mm.aliasing_ppgtt) | |
3421 | return; | |
3422 | ||
55a254ac DV |
3423 | |
3424 | pd_addr = dev_priv->mm.gtt->gtt + ppgtt->pd_offset/sizeof(uint32_t); | |
3425 | for (i = 0; i < ppgtt->num_pd_entries; i++) { | |
3426 | dma_addr_t pt_addr; | |
3427 | ||
3428 | if (dev_priv->mm.gtt->needs_dmar) | |
3429 | pt_addr = ppgtt->pt_dma_addr[i]; | |
3430 | else | |
3431 | pt_addr = page_to_phys(ppgtt->pt_pages[i]); | |
3432 | ||
3433 | pd_entry = GEN6_PDE_ADDR_ENCODE(pt_addr); | |
3434 | pd_entry |= GEN6_PDE_VALID; | |
3435 | ||
3436 | writel(pd_entry, pd_addr + i); | |
3437 | } | |
3438 | readl(pd_addr); | |
3439 | ||
3440 | pd_offset = ppgtt->pd_offset; | |
e21af88d DV |
3441 | pd_offset /= 64; /* in cachelines, */ |
3442 | pd_offset <<= 16; | |
3443 | ||
3444 | if (INTEL_INFO(dev)->gen == 6) { | |
48ecfa10 DV |
3445 | uint32_t ecochk, gab_ctl, ecobits; |
3446 | ||
3447 | ecobits = I915_READ(GAC_ECO_BITS); | |
3448 | I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_PPGTT_CACHE64B); | |
be901a5a DV |
3449 | |
3450 | gab_ctl = I915_READ(GAB_CTL); | |
3451 | I915_WRITE(GAB_CTL, gab_ctl | GAB_CTL_CONT_AFTER_PAGEFAULT); | |
3452 | ||
3453 | ecochk = I915_READ(GAM_ECOCHK); | |
e21af88d DV |
3454 | I915_WRITE(GAM_ECOCHK, ecochk | ECOCHK_SNB_BIT | |
3455 | ECOCHK_PPGTT_CACHE64B); | |
6b26c86d | 3456 | I915_WRITE(GFX_MODE, _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE)); |
e21af88d DV |
3457 | } else if (INTEL_INFO(dev)->gen >= 7) { |
3458 | I915_WRITE(GAM_ECOCHK, ECOCHK_PPGTT_CACHE64B); | |
3459 | /* GFX_MODE is per-ring on gen7+ */ | |
3460 | } | |
3461 | ||
3462 | for (i = 0; i < I915_NUM_RINGS; i++) { | |
3463 | ring = &dev_priv->ring[i]; | |
3464 | ||
3465 | if (INTEL_INFO(dev)->gen >= 7) | |
3466 | I915_WRITE(RING_MODE_GEN7(ring), | |
6b26c86d | 3467 | _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE)); |
e21af88d DV |
3468 | |
3469 | I915_WRITE(RING_PP_DIR_DCLV(ring), PP_DIR_DCLV_2G); | |
3470 | I915_WRITE(RING_PP_DIR_BASE(ring), pd_offset); | |
3471 | } | |
3472 | } | |
3473 | ||
8187a2b7 | 3474 | int |
f691e2f4 | 3475 | i915_gem_init_hw(struct drm_device *dev) |
8187a2b7 ZN |
3476 | { |
3477 | drm_i915_private_t *dev_priv = dev->dev_private; | |
3478 | int ret; | |
68f95ba9 | 3479 | |
f691e2f4 DV |
3480 | i915_gem_init_swizzling(dev); |
3481 | ||
5c1143bb | 3482 | ret = intel_init_render_ring_buffer(dev); |
68f95ba9 | 3483 | if (ret) |
b6913e4b | 3484 | return ret; |
68f95ba9 CW |
3485 | |
3486 | if (HAS_BSD(dev)) { | |
5c1143bb | 3487 | ret = intel_init_bsd_ring_buffer(dev); |
68f95ba9 CW |
3488 | if (ret) |
3489 | goto cleanup_render_ring; | |
d1b851fc | 3490 | } |
68f95ba9 | 3491 | |
549f7365 CW |
3492 | if (HAS_BLT(dev)) { |
3493 | ret = intel_init_blt_ring_buffer(dev); | |
3494 | if (ret) | |
3495 | goto cleanup_bsd_ring; | |
3496 | } | |
3497 | ||
6f392d54 CW |
3498 | dev_priv->next_seqno = 1; |
3499 | ||
e21af88d DV |
3500 | i915_gem_init_ppgtt(dev); |
3501 | ||
68f95ba9 CW |
3502 | return 0; |
3503 | ||
549f7365 | 3504 | cleanup_bsd_ring: |
1ec14ad3 | 3505 | intel_cleanup_ring_buffer(&dev_priv->ring[VCS]); |
68f95ba9 | 3506 | cleanup_render_ring: |
1ec14ad3 | 3507 | intel_cleanup_ring_buffer(&dev_priv->ring[RCS]); |
8187a2b7 ZN |
3508 | return ret; |
3509 | } | |
3510 | ||
1070a42b CW |
3511 | static bool |
3512 | intel_enable_ppgtt(struct drm_device *dev) | |
3513 | { | |
3514 | if (i915_enable_ppgtt >= 0) | |
3515 | return i915_enable_ppgtt; | |
3516 | ||
3517 | #ifdef CONFIG_INTEL_IOMMU | |
3518 | /* Disable ppgtt on SNB if VT-d is on. */ | |
3519 | if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped) | |
3520 | return false; | |
3521 | #endif | |
3522 | ||
3523 | return true; | |
3524 | } | |
3525 | ||
3526 | int i915_gem_init(struct drm_device *dev) | |
3527 | { | |
3528 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3529 | unsigned long gtt_size, mappable_size; | |
3530 | int ret; | |
3531 | ||
3532 | gtt_size = dev_priv->mm.gtt->gtt_total_entries << PAGE_SHIFT; | |
3533 | mappable_size = dev_priv->mm.gtt->gtt_mappable_entries << PAGE_SHIFT; | |
3534 | ||
3535 | mutex_lock(&dev->struct_mutex); | |
3536 | if (intel_enable_ppgtt(dev) && HAS_ALIASING_PPGTT(dev)) { | |
3537 | /* PPGTT pdes are stolen from global gtt ptes, so shrink the | |
3538 | * aperture accordingly when using aliasing ppgtt. */ | |
3539 | gtt_size -= I915_PPGTT_PD_ENTRIES*PAGE_SIZE; | |
3540 | ||
3541 | i915_gem_init_global_gtt(dev, 0, mappable_size, gtt_size); | |
3542 | ||
3543 | ret = i915_gem_init_aliasing_ppgtt(dev); | |
3544 | if (ret) { | |
3545 | mutex_unlock(&dev->struct_mutex); | |
3546 | return ret; | |
3547 | } | |
3548 | } else { | |
3549 | /* Let GEM Manage all of the aperture. | |
3550 | * | |
3551 | * However, leave one page at the end still bound to the scratch | |
3552 | * page. There are a number of places where the hardware | |
3553 | * apparently prefetches past the end of the object, and we've | |
3554 | * seen multiple hangs with the GPU head pointer stuck in a | |
3555 | * batchbuffer bound at the last page of the aperture. One page | |
3556 | * should be enough to keep any prefetching inside of the | |
3557 | * aperture. | |
3558 | */ | |
3559 | i915_gem_init_global_gtt(dev, 0, mappable_size, | |
3560 | gtt_size); | |
3561 | } | |
3562 | ||
3563 | ret = i915_gem_init_hw(dev); | |
3564 | mutex_unlock(&dev->struct_mutex); | |
3565 | if (ret) { | |
3566 | i915_gem_cleanup_aliasing_ppgtt(dev); | |
3567 | return ret; | |
3568 | } | |
3569 | ||
3570 | /* Allow hardware batchbuffers unless told otherwise. */ | |
8781342d | 3571 | dev_priv->dri1.allow_batchbuffer = 1; |
1070a42b CW |
3572 | return 0; |
3573 | } | |
3574 | ||
8187a2b7 ZN |
3575 | void |
3576 | i915_gem_cleanup_ringbuffer(struct drm_device *dev) | |
3577 | { | |
3578 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1ec14ad3 | 3579 | int i; |
8187a2b7 | 3580 | |
1ec14ad3 CW |
3581 | for (i = 0; i < I915_NUM_RINGS; i++) |
3582 | intel_cleanup_ring_buffer(&dev_priv->ring[i]); | |
8187a2b7 ZN |
3583 | } |
3584 | ||
673a394b EA |
3585 | int |
3586 | i915_gem_entervt_ioctl(struct drm_device *dev, void *data, | |
3587 | struct drm_file *file_priv) | |
3588 | { | |
3589 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1ec14ad3 | 3590 | int ret, i; |
673a394b | 3591 | |
79e53945 JB |
3592 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
3593 | return 0; | |
3594 | ||
ba1234d1 | 3595 | if (atomic_read(&dev_priv->mm.wedged)) { |
673a394b | 3596 | DRM_ERROR("Reenabling wedged hardware, good luck\n"); |
ba1234d1 | 3597 | atomic_set(&dev_priv->mm.wedged, 0); |
673a394b EA |
3598 | } |
3599 | ||
673a394b | 3600 | mutex_lock(&dev->struct_mutex); |
9bb2d6f9 EA |
3601 | dev_priv->mm.suspended = 0; |
3602 | ||
f691e2f4 | 3603 | ret = i915_gem_init_hw(dev); |
d816f6ac WF |
3604 | if (ret != 0) { |
3605 | mutex_unlock(&dev->struct_mutex); | |
9bb2d6f9 | 3606 | return ret; |
d816f6ac | 3607 | } |
9bb2d6f9 | 3608 | |
69dc4987 | 3609 | BUG_ON(!list_empty(&dev_priv->mm.active_list)); |
673a394b EA |
3610 | BUG_ON(!list_empty(&dev_priv->mm.flushing_list)); |
3611 | BUG_ON(!list_empty(&dev_priv->mm.inactive_list)); | |
1ec14ad3 CW |
3612 | for (i = 0; i < I915_NUM_RINGS; i++) { |
3613 | BUG_ON(!list_empty(&dev_priv->ring[i].active_list)); | |
3614 | BUG_ON(!list_empty(&dev_priv->ring[i].request_list)); | |
3615 | } | |
673a394b | 3616 | mutex_unlock(&dev->struct_mutex); |
dbb19d30 | 3617 | |
5f35308b CW |
3618 | ret = drm_irq_install(dev); |
3619 | if (ret) | |
3620 | goto cleanup_ringbuffer; | |
dbb19d30 | 3621 | |
673a394b | 3622 | return 0; |
5f35308b CW |
3623 | |
3624 | cleanup_ringbuffer: | |
3625 | mutex_lock(&dev->struct_mutex); | |
3626 | i915_gem_cleanup_ringbuffer(dev); | |
3627 | dev_priv->mm.suspended = 1; | |
3628 | mutex_unlock(&dev->struct_mutex); | |
3629 | ||
3630 | return ret; | |
673a394b EA |
3631 | } |
3632 | ||
3633 | int | |
3634 | i915_gem_leavevt_ioctl(struct drm_device *dev, void *data, | |
3635 | struct drm_file *file_priv) | |
3636 | { | |
79e53945 JB |
3637 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
3638 | return 0; | |
3639 | ||
dbb19d30 | 3640 | drm_irq_uninstall(dev); |
e6890f6f | 3641 | return i915_gem_idle(dev); |
673a394b EA |
3642 | } |
3643 | ||
3644 | void | |
3645 | i915_gem_lastclose(struct drm_device *dev) | |
3646 | { | |
3647 | int ret; | |
673a394b | 3648 | |
e806b495 EA |
3649 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
3650 | return; | |
3651 | ||
6dbe2772 KP |
3652 | ret = i915_gem_idle(dev); |
3653 | if (ret) | |
3654 | DRM_ERROR("failed to idle hardware: %d\n", ret); | |
673a394b EA |
3655 | } |
3656 | ||
64193406 CW |
3657 | static void |
3658 | init_ring_lists(struct intel_ring_buffer *ring) | |
3659 | { | |
3660 | INIT_LIST_HEAD(&ring->active_list); | |
3661 | INIT_LIST_HEAD(&ring->request_list); | |
3662 | INIT_LIST_HEAD(&ring->gpu_write_list); | |
3663 | } | |
3664 | ||
673a394b EA |
3665 | void |
3666 | i915_gem_load(struct drm_device *dev) | |
3667 | { | |
b5aa8a0f | 3668 | int i; |
673a394b EA |
3669 | drm_i915_private_t *dev_priv = dev->dev_private; |
3670 | ||
69dc4987 | 3671 | INIT_LIST_HEAD(&dev_priv->mm.active_list); |
673a394b EA |
3672 | INIT_LIST_HEAD(&dev_priv->mm.flushing_list); |
3673 | INIT_LIST_HEAD(&dev_priv->mm.inactive_list); | |
a09ba7fa | 3674 | INIT_LIST_HEAD(&dev_priv->mm.fence_list); |
93a37f20 | 3675 | INIT_LIST_HEAD(&dev_priv->mm.gtt_list); |
1ec14ad3 CW |
3676 | for (i = 0; i < I915_NUM_RINGS; i++) |
3677 | init_ring_lists(&dev_priv->ring[i]); | |
4b9de737 | 3678 | for (i = 0; i < I915_MAX_NUM_FENCES; i++) |
007cc8ac | 3679 | INIT_LIST_HEAD(&dev_priv->fence_regs[i].lru_list); |
673a394b EA |
3680 | INIT_DELAYED_WORK(&dev_priv->mm.retire_work, |
3681 | i915_gem_retire_work_handler); | |
30dbf0c0 | 3682 | init_completion(&dev_priv->error_completion); |
31169714 | 3683 | |
94400120 DA |
3684 | /* On GEN3 we really need to make sure the ARB C3 LP bit is set */ |
3685 | if (IS_GEN3(dev)) { | |
50743298 DV |
3686 | I915_WRITE(MI_ARB_STATE, |
3687 | _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE)); | |
94400120 DA |
3688 | } |
3689 | ||
72bfa19c CW |
3690 | dev_priv->relative_constants_mode = I915_EXEC_CONSTANTS_REL_GENERAL; |
3691 | ||
de151cf6 | 3692 | /* Old X drivers will take 0-2 for front, back, depth buffers */ |
b397c836 EA |
3693 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) |
3694 | dev_priv->fence_reg_start = 3; | |
de151cf6 | 3695 | |
a6c45cf0 | 3696 | if (INTEL_INFO(dev)->gen >= 4 || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) |
de151cf6 JB |
3697 | dev_priv->num_fence_regs = 16; |
3698 | else | |
3699 | dev_priv->num_fence_regs = 8; | |
3700 | ||
b5aa8a0f | 3701 | /* Initialize fence registers to zero */ |
ada726c7 | 3702 | i915_gem_reset_fences(dev); |
10ed13e4 | 3703 | |
673a394b | 3704 | i915_gem_detect_bit_6_swizzle(dev); |
6b95a207 | 3705 | init_waitqueue_head(&dev_priv->pending_flip_queue); |
17250b71 | 3706 | |
ce453d81 CW |
3707 | dev_priv->mm.interruptible = true; |
3708 | ||
17250b71 CW |
3709 | dev_priv->mm.inactive_shrinker.shrink = i915_gem_inactive_shrink; |
3710 | dev_priv->mm.inactive_shrinker.seeks = DEFAULT_SEEKS; | |
3711 | register_shrinker(&dev_priv->mm.inactive_shrinker); | |
673a394b | 3712 | } |
71acb5eb DA |
3713 | |
3714 | /* | |
3715 | * Create a physically contiguous memory object for this object | |
3716 | * e.g. for cursor + overlay regs | |
3717 | */ | |
995b6762 CW |
3718 | static int i915_gem_init_phys_object(struct drm_device *dev, |
3719 | int id, int size, int align) | |
71acb5eb DA |
3720 | { |
3721 | drm_i915_private_t *dev_priv = dev->dev_private; | |
3722 | struct drm_i915_gem_phys_object *phys_obj; | |
3723 | int ret; | |
3724 | ||
3725 | if (dev_priv->mm.phys_objs[id - 1] || !size) | |
3726 | return 0; | |
3727 | ||
9a298b2a | 3728 | phys_obj = kzalloc(sizeof(struct drm_i915_gem_phys_object), GFP_KERNEL); |
71acb5eb DA |
3729 | if (!phys_obj) |
3730 | return -ENOMEM; | |
3731 | ||
3732 | phys_obj->id = id; | |
3733 | ||
6eeefaf3 | 3734 | phys_obj->handle = drm_pci_alloc(dev, size, align); |
71acb5eb DA |
3735 | if (!phys_obj->handle) { |
3736 | ret = -ENOMEM; | |
3737 | goto kfree_obj; | |
3738 | } | |
3739 | #ifdef CONFIG_X86 | |
3740 | set_memory_wc((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE); | |
3741 | #endif | |
3742 | ||
3743 | dev_priv->mm.phys_objs[id - 1] = phys_obj; | |
3744 | ||
3745 | return 0; | |
3746 | kfree_obj: | |
9a298b2a | 3747 | kfree(phys_obj); |
71acb5eb DA |
3748 | return ret; |
3749 | } | |
3750 | ||
995b6762 | 3751 | static void i915_gem_free_phys_object(struct drm_device *dev, int id) |
71acb5eb DA |
3752 | { |
3753 | drm_i915_private_t *dev_priv = dev->dev_private; | |
3754 | struct drm_i915_gem_phys_object *phys_obj; | |
3755 | ||
3756 | if (!dev_priv->mm.phys_objs[id - 1]) | |
3757 | return; | |
3758 | ||
3759 | phys_obj = dev_priv->mm.phys_objs[id - 1]; | |
3760 | if (phys_obj->cur_obj) { | |
3761 | i915_gem_detach_phys_object(dev, phys_obj->cur_obj); | |
3762 | } | |
3763 | ||
3764 | #ifdef CONFIG_X86 | |
3765 | set_memory_wb((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE); | |
3766 | #endif | |
3767 | drm_pci_free(dev, phys_obj->handle); | |
3768 | kfree(phys_obj); | |
3769 | dev_priv->mm.phys_objs[id - 1] = NULL; | |
3770 | } | |
3771 | ||
3772 | void i915_gem_free_all_phys_object(struct drm_device *dev) | |
3773 | { | |
3774 | int i; | |
3775 | ||
260883c8 | 3776 | for (i = I915_GEM_PHYS_CURSOR_0; i <= I915_MAX_PHYS_OBJECT; i++) |
71acb5eb DA |
3777 | i915_gem_free_phys_object(dev, i); |
3778 | } | |
3779 | ||
3780 | void i915_gem_detach_phys_object(struct drm_device *dev, | |
05394f39 | 3781 | struct drm_i915_gem_object *obj) |
71acb5eb | 3782 | { |
05394f39 | 3783 | struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping; |
e5281ccd | 3784 | char *vaddr; |
71acb5eb | 3785 | int i; |
71acb5eb DA |
3786 | int page_count; |
3787 | ||
05394f39 | 3788 | if (!obj->phys_obj) |
71acb5eb | 3789 | return; |
05394f39 | 3790 | vaddr = obj->phys_obj->handle->vaddr; |
71acb5eb | 3791 | |
05394f39 | 3792 | page_count = obj->base.size / PAGE_SIZE; |
71acb5eb | 3793 | for (i = 0; i < page_count; i++) { |
5949eac4 | 3794 | struct page *page = shmem_read_mapping_page(mapping, i); |
e5281ccd CW |
3795 | if (!IS_ERR(page)) { |
3796 | char *dst = kmap_atomic(page); | |
3797 | memcpy(dst, vaddr + i*PAGE_SIZE, PAGE_SIZE); | |
3798 | kunmap_atomic(dst); | |
3799 | ||
3800 | drm_clflush_pages(&page, 1); | |
3801 | ||
3802 | set_page_dirty(page); | |
3803 | mark_page_accessed(page); | |
3804 | page_cache_release(page); | |
3805 | } | |
71acb5eb | 3806 | } |
40ce6575 | 3807 | intel_gtt_chipset_flush(); |
d78b47b9 | 3808 | |
05394f39 CW |
3809 | obj->phys_obj->cur_obj = NULL; |
3810 | obj->phys_obj = NULL; | |
71acb5eb DA |
3811 | } |
3812 | ||
3813 | int | |
3814 | i915_gem_attach_phys_object(struct drm_device *dev, | |
05394f39 | 3815 | struct drm_i915_gem_object *obj, |
6eeefaf3 CW |
3816 | int id, |
3817 | int align) | |
71acb5eb | 3818 | { |
05394f39 | 3819 | struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping; |
71acb5eb | 3820 | drm_i915_private_t *dev_priv = dev->dev_private; |
71acb5eb DA |
3821 | int ret = 0; |
3822 | int page_count; | |
3823 | int i; | |
3824 | ||
3825 | if (id > I915_MAX_PHYS_OBJECT) | |
3826 | return -EINVAL; | |
3827 | ||
05394f39 CW |
3828 | if (obj->phys_obj) { |
3829 | if (obj->phys_obj->id == id) | |
71acb5eb DA |
3830 | return 0; |
3831 | i915_gem_detach_phys_object(dev, obj); | |
3832 | } | |
3833 | ||
71acb5eb DA |
3834 | /* create a new object */ |
3835 | if (!dev_priv->mm.phys_objs[id - 1]) { | |
3836 | ret = i915_gem_init_phys_object(dev, id, | |
05394f39 | 3837 | obj->base.size, align); |
71acb5eb | 3838 | if (ret) { |
05394f39 CW |
3839 | DRM_ERROR("failed to init phys object %d size: %zu\n", |
3840 | id, obj->base.size); | |
e5281ccd | 3841 | return ret; |
71acb5eb DA |
3842 | } |
3843 | } | |
3844 | ||
3845 | /* bind to the object */ | |
05394f39 CW |
3846 | obj->phys_obj = dev_priv->mm.phys_objs[id - 1]; |
3847 | obj->phys_obj->cur_obj = obj; | |
71acb5eb | 3848 | |
05394f39 | 3849 | page_count = obj->base.size / PAGE_SIZE; |
71acb5eb DA |
3850 | |
3851 | for (i = 0; i < page_count; i++) { | |
e5281ccd CW |
3852 | struct page *page; |
3853 | char *dst, *src; | |
3854 | ||
5949eac4 | 3855 | page = shmem_read_mapping_page(mapping, i); |
e5281ccd CW |
3856 | if (IS_ERR(page)) |
3857 | return PTR_ERR(page); | |
71acb5eb | 3858 | |
ff75b9bc | 3859 | src = kmap_atomic(page); |
05394f39 | 3860 | dst = obj->phys_obj->handle->vaddr + (i * PAGE_SIZE); |
71acb5eb | 3861 | memcpy(dst, src, PAGE_SIZE); |
3e4d3af5 | 3862 | kunmap_atomic(src); |
71acb5eb | 3863 | |
e5281ccd CW |
3864 | mark_page_accessed(page); |
3865 | page_cache_release(page); | |
3866 | } | |
d78b47b9 | 3867 | |
71acb5eb | 3868 | return 0; |
71acb5eb DA |
3869 | } |
3870 | ||
3871 | static int | |
05394f39 CW |
3872 | i915_gem_phys_pwrite(struct drm_device *dev, |
3873 | struct drm_i915_gem_object *obj, | |
71acb5eb DA |
3874 | struct drm_i915_gem_pwrite *args, |
3875 | struct drm_file *file_priv) | |
3876 | { | |
05394f39 | 3877 | void *vaddr = obj->phys_obj->handle->vaddr + args->offset; |
b47b30cc | 3878 | char __user *user_data = (char __user *) (uintptr_t) args->data_ptr; |
71acb5eb | 3879 | |
b47b30cc CW |
3880 | if (__copy_from_user_inatomic_nocache(vaddr, user_data, args->size)) { |
3881 | unsigned long unwritten; | |
3882 | ||
3883 | /* The physical object once assigned is fixed for the lifetime | |
3884 | * of the obj, so we can safely drop the lock and continue | |
3885 | * to access vaddr. | |
3886 | */ | |
3887 | mutex_unlock(&dev->struct_mutex); | |
3888 | unwritten = copy_from_user(vaddr, user_data, args->size); | |
3889 | mutex_lock(&dev->struct_mutex); | |
3890 | if (unwritten) | |
3891 | return -EFAULT; | |
3892 | } | |
71acb5eb | 3893 | |
40ce6575 | 3894 | intel_gtt_chipset_flush(); |
71acb5eb DA |
3895 | return 0; |
3896 | } | |
b962442e | 3897 | |
f787a5f5 | 3898 | void i915_gem_release(struct drm_device *dev, struct drm_file *file) |
b962442e | 3899 | { |
f787a5f5 | 3900 | struct drm_i915_file_private *file_priv = file->driver_priv; |
b962442e EA |
3901 | |
3902 | /* Clean up our request list when the client is going away, so that | |
3903 | * later retire_requests won't dereference our soon-to-be-gone | |
3904 | * file_priv. | |
3905 | */ | |
1c25595f | 3906 | spin_lock(&file_priv->mm.lock); |
f787a5f5 CW |
3907 | while (!list_empty(&file_priv->mm.request_list)) { |
3908 | struct drm_i915_gem_request *request; | |
3909 | ||
3910 | request = list_first_entry(&file_priv->mm.request_list, | |
3911 | struct drm_i915_gem_request, | |
3912 | client_list); | |
3913 | list_del(&request->client_list); | |
3914 | request->file_priv = NULL; | |
3915 | } | |
1c25595f | 3916 | spin_unlock(&file_priv->mm.lock); |
b962442e | 3917 | } |
31169714 | 3918 | |
1637ef41 CW |
3919 | static int |
3920 | i915_gpu_is_active(struct drm_device *dev) | |
3921 | { | |
3922 | drm_i915_private_t *dev_priv = dev->dev_private; | |
3923 | int lists_empty; | |
3924 | ||
1637ef41 | 3925 | lists_empty = list_empty(&dev_priv->mm.flushing_list) && |
17250b71 | 3926 | list_empty(&dev_priv->mm.active_list); |
1637ef41 CW |
3927 | |
3928 | return !lists_empty; | |
3929 | } | |
3930 | ||
31169714 | 3931 | static int |
1495f230 | 3932 | i915_gem_inactive_shrink(struct shrinker *shrinker, struct shrink_control *sc) |
31169714 | 3933 | { |
17250b71 CW |
3934 | struct drm_i915_private *dev_priv = |
3935 | container_of(shrinker, | |
3936 | struct drm_i915_private, | |
3937 | mm.inactive_shrinker); | |
3938 | struct drm_device *dev = dev_priv->dev; | |
3939 | struct drm_i915_gem_object *obj, *next; | |
1495f230 | 3940 | int nr_to_scan = sc->nr_to_scan; |
17250b71 CW |
3941 | int cnt; |
3942 | ||
3943 | if (!mutex_trylock(&dev->struct_mutex)) | |
bbe2e11a | 3944 | return 0; |
31169714 CW |
3945 | |
3946 | /* "fast-path" to count number of available objects */ | |
3947 | if (nr_to_scan == 0) { | |
17250b71 CW |
3948 | cnt = 0; |
3949 | list_for_each_entry(obj, | |
3950 | &dev_priv->mm.inactive_list, | |
3951 | mm_list) | |
3952 | cnt++; | |
3953 | mutex_unlock(&dev->struct_mutex); | |
3954 | return cnt / 100 * sysctl_vfs_cache_pressure; | |
31169714 CW |
3955 | } |
3956 | ||
1637ef41 | 3957 | rescan: |
31169714 | 3958 | /* first scan for clean buffers */ |
17250b71 | 3959 | i915_gem_retire_requests(dev); |
31169714 | 3960 | |
17250b71 CW |
3961 | list_for_each_entry_safe(obj, next, |
3962 | &dev_priv->mm.inactive_list, | |
3963 | mm_list) { | |
3964 | if (i915_gem_object_is_purgeable(obj)) { | |
2021746e CW |
3965 | if (i915_gem_object_unbind(obj) == 0 && |
3966 | --nr_to_scan == 0) | |
17250b71 | 3967 | break; |
31169714 | 3968 | } |
31169714 CW |
3969 | } |
3970 | ||
3971 | /* second pass, evict/count anything still on the inactive list */ | |
17250b71 CW |
3972 | cnt = 0; |
3973 | list_for_each_entry_safe(obj, next, | |
3974 | &dev_priv->mm.inactive_list, | |
3975 | mm_list) { | |
2021746e CW |
3976 | if (nr_to_scan && |
3977 | i915_gem_object_unbind(obj) == 0) | |
17250b71 | 3978 | nr_to_scan--; |
2021746e | 3979 | else |
17250b71 CW |
3980 | cnt++; |
3981 | } | |
3982 | ||
3983 | if (nr_to_scan && i915_gpu_is_active(dev)) { | |
1637ef41 CW |
3984 | /* |
3985 | * We are desperate for pages, so as a last resort, wait | |
3986 | * for the GPU to finish and discard whatever we can. | |
3987 | * This has a dramatic impact to reduce the number of | |
3988 | * OOM-killer events whilst running the GPU aggressively. | |
3989 | */ | |
b2da9fe5 | 3990 | if (i915_gpu_idle(dev) == 0) |
1637ef41 CW |
3991 | goto rescan; |
3992 | } | |
17250b71 CW |
3993 | mutex_unlock(&dev->struct_mutex); |
3994 | return cnt / 100 * sysctl_vfs_cache_pressure; | |
31169714 | 3995 | } |