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agp/intel-gtt: remove dead code
[deliverable/linux.git] / drivers / gpu / drm / i915 / i915_gem.c
CommitLineData
673a394b
EA		 1/*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 *
26 */
27
28#include "drmP.h"
29#include "drm.h"
30#include "i915_drm.h"
31#include "i915_drv.h"
1c5d22f7 32#include "i915_trace.h"
652c393a 33#include "intel_drv.h"
5949eac4 34#include <linux/shmem_fs.h>
5a0e3ad6 35#include <linux/slab.h>
673a394b 36#include <linux/swap.h>
79e53945 37#include <linux/pci.h>
1286ff73 38#include <linux/dma-buf.h>
673a394b 39
88241785 40static __must_check int i915_gem_object_flush_gpu_write_domain(struct drm_i915_gem_object *obj);
05394f39
CW		 41static void i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj);
42static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj);
88241785
CW		 43static __must_check int i915_gem_object_bind_to_gtt(struct drm_i915_gem_object *obj,
44 unsigned alignment,
45 bool map_and_fenceable);
05394f39
CW		 46static int i915_gem_phys_pwrite(struct drm_device *dev,
47 struct drm_i915_gem_object *obj,
71acb5eb 48 struct drm_i915_gem_pwrite *args,
05394f39 49 struct drm_file *file);
673a394b 50
61050808
CW		 51static void i915_gem_write_fence(struct drm_device *dev, int reg,
52 struct drm_i915_gem_object *obj);
53static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj,
54 struct drm_i915_fence_reg *fence,
55 bool enable);
56
17250b71 57static int i915_gem_inactive_shrink(struct shrinker *shrinker,
1495f230 58 struct shrink_control *sc);
8c59967c 59static void i915_gem_object_truncate(struct drm_i915_gem_object *obj);
31169714 60
61050808
CW		 61static inline void i915_gem_object_fence_lost(struct drm_i915_gem_object *obj)
62{
63 if (obj->tiling_mode)
64 i915_gem_release_mmap(obj);
65
66 /* As we do not have an associated fence register, we will force
67 * a tiling change if we ever need to acquire one.
68 */
5d82e3e6 69 obj->fence_dirty = false;
61050808
CW		 70 obj->fence_reg = I915_FENCE_REG_NONE;
71}
72
73aa808f
CW		 73/* some bookkeeping */
74static void i915_gem_info_add_obj(struct drm_i915_private *dev_priv,
75 size_t size)
76{
77 dev_priv->mm.object_count++;
78 dev_priv->mm.object_memory += size;
79}
80
81static void i915_gem_info_remove_obj(struct drm_i915_private *dev_priv,
82 size_t size)
83{
84 dev_priv->mm.object_count--;
85 dev_priv->mm.object_memory -= size;
86}
87
21dd3734
CW		 88static int
89i915_gem_wait_for_error(struct drm_device *dev)
30dbf0c0
CW		 90{
91 struct drm_i915_private *dev_priv = dev->dev_private;
92 struct completion *x = &dev_priv->error_completion;
93 unsigned long flags;
94 int ret;
95
96 if (!atomic_read(&dev_priv->mm.wedged))
97 return 0;
98
99 ret = wait_for_completion_interruptible(x);
100 if (ret)
101 return ret;
102
21dd3734
CW		 103 if (atomic_read(&dev_priv->mm.wedged)) {
104 /* GPU is hung, bump the completion count to account for
105 * the token we just consumed so that we never hit zero and
106 * end up waiting upon a subsequent completion event that
107 * will never happen.
108 */
109 spin_lock_irqsave(&x->wait.lock, flags);
110 x->done++;
111 spin_unlock_irqrestore(&x->wait.lock, flags);
112 }
113 return 0;
30dbf0c0
CW		 114}
115
54cf91dc 116int i915_mutex_lock_interruptible(struct drm_device *dev)
76c1dec1 117{
76c1dec1
CW		 118 int ret;
119
21dd3734 120 ret = i915_gem_wait_for_error(dev);
76c1dec1
CW		 121 if (ret)
122 return ret;
123
124 ret = mutex_lock_interruptible(&dev->struct_mutex);
125 if (ret)
126 return ret;
127
23bc5982 128 WARN_ON(i915_verify_lists(dev));
76c1dec1
CW		 129 return 0;
130}
30dbf0c0 131
7d1c4804 132static inline bool
05394f39 133i915_gem_object_is_inactive(struct drm_i915_gem_object *obj)
7d1c4804 134{
1b50247a 135 return !obj->active;
7d1c4804
CW		 136}
137
79e53945
JB		 138int
139i915_gem_init_ioctl(struct drm_device *dev, void *data,
05394f39 140 struct drm_file *file)
79e53945
JB		 141{
142 struct drm_i915_gem_init *args = data;
2021746e 143
7bb6fb8d
DV		 144 if (drm_core_check_feature(dev, DRIVER_MODESET))
145 return -ENODEV;
146
2021746e
CW		 147 if (args->gtt_start >= args->gtt_end ||
148 (args->gtt_end | args->gtt_start) & (PAGE_SIZE - 1))
149 return -EINVAL;
79e53945 150
f534bc0b
DV		 151 /* GEM with user mode setting was never supported on ilk and later. */
152 if (INTEL_INFO(dev)->gen >= 5)
153 return -ENODEV;
154
79e53945 155 mutex_lock(&dev->struct_mutex);
644ec02b
DV		 156 i915_gem_init_global_gtt(dev, args->gtt_start,
157 args->gtt_end, args->gtt_end);
673a394b
EA		 158 mutex_unlock(&dev->struct_mutex);
159
2021746e 160 return 0;
673a394b
EA		 161}
162
5a125c3c
EA		 163int
164i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
05394f39 165 struct drm_file *file)
5a125c3c 166{
73aa808f 167 struct drm_i915_private *dev_priv = dev->dev_private;
5a125c3c 168 struct drm_i915_gem_get_aperture *args = data;
6299f992
CW		 169 struct drm_i915_gem_object *obj;
170 size_t pinned;
5a125c3c 171
6299f992 172 pinned = 0;
73aa808f 173 mutex_lock(&dev->struct_mutex);
1b50247a
CW		 174 list_for_each_entry(obj, &dev_priv->mm.gtt_list, gtt_list)
175 if (obj->pin_count)
176 pinned += obj->gtt_space->size;
73aa808f 177 mutex_unlock(&dev->struct_mutex);
5a125c3c 178
6299f992 179 args->aper_size = dev_priv->mm.gtt_total;
0206e353 180 args->aper_available_size = args->aper_size - pinned;
6299f992 181
5a125c3c
EA		 182 return 0;
183}
184
ff72145b
DA		 185static int
186i915_gem_create(struct drm_file *file,
187 struct drm_device *dev,
188 uint64_t size,
189 uint32_t *handle_p)
673a394b 190{
05394f39 191 struct drm_i915_gem_object *obj;
a1a2d1d3
PP		 192 int ret;
193 u32 handle;
673a394b 194
ff72145b 195 size = roundup(size, PAGE_SIZE);
8ffc0246
CW		 196 if (size == 0)
197 return -EINVAL;
673a394b
EA		 198
199 /* Allocate the new object */
ff72145b 200 obj = i915_gem_alloc_object(dev, size);
673a394b
EA		 201 if (obj == NULL)
202 return -ENOMEM;
203
05394f39 204 ret = drm_gem_handle_create(file, &obj->base, &handle);
1dfd9754 205 if (ret) {
05394f39
CW		 206 drm_gem_object_release(&obj->base);
207 i915_gem_info_remove_obj(dev->dev_private, obj->base.size);
202f2fef 208 kfree(obj);
673a394b 209 return ret;
1dfd9754 210 }
673a394b 211
202f2fef 212 /* drop reference from allocate - handle holds it now */
05394f39 213 drm_gem_object_unreference(&obj->base);
202f2fef
CW		 214 trace_i915_gem_object_create(obj);
215
ff72145b 216 *handle_p = handle;
673a394b
EA		 217 return 0;
218}
219
ff72145b
DA		 220int
221i915_gem_dumb_create(struct drm_file *file,
222 struct drm_device *dev,
223 struct drm_mode_create_dumb *args)
224{
225 /* have to work out size/pitch and return them */
ed0291fd 226 args->pitch = ALIGN(args->width * ((args->bpp + 7) / 8), 64);
ff72145b
DA		 227 args->size = args->pitch * args->height;
228 return i915_gem_create(file, dev,
229 args->size, &args->handle);
230}
231
232int i915_gem_dumb_destroy(struct drm_file *file,
233 struct drm_device *dev,
234 uint32_t handle)
235{
236 return drm_gem_handle_delete(file, handle);
237}
238
239/**
240 * Creates a new mm object and returns a handle to it.
241 */
242int
243i915_gem_create_ioctl(struct drm_device *dev, void *data,
244 struct drm_file *file)
245{
246 struct drm_i915_gem_create *args = data;
63ed2cb2 247
ff72145b
DA		 248 return i915_gem_create(file, dev,
249 args->size, &args->handle);
250}
251
05394f39 252static int i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj)
280b713b 253{
05394f39 254 drm_i915_private_t *dev_priv = obj->base.dev->dev_private;
280b713b
EA		 255
256 return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
05394f39 257 obj->tiling_mode != I915_TILING_NONE;
280b713b
EA		 258}
259
8461d226
DV		 260static inline int
261__copy_to_user_swizzled(char __user *cpu_vaddr,
262 const char *gpu_vaddr, int gpu_offset,
263 int length)
264{
265 int ret, cpu_offset = 0;
266
267 while (length > 0) {
268 int cacheline_end = ALIGN(gpu_offset + 1, 64);
269 int this_length = min(cacheline_end - gpu_offset, length);
270 int swizzled_gpu_offset = gpu_offset ^ 64;
271
272 ret = __copy_to_user(cpu_vaddr + cpu_offset,
273 gpu_vaddr + swizzled_gpu_offset,
274 this_length);
275 if (ret)
276 return ret + length;
277
278 cpu_offset += this_length;
279 gpu_offset += this_length;
280 length -= this_length;
281 }
282
283 return 0;
284}
285
8c59967c 286static inline int
4f0c7cfb
BW		 287__copy_from_user_swizzled(char *gpu_vaddr, int gpu_offset,
288 const char __user *cpu_vaddr,
8c59967c
DV		 289 int length)
290{
291 int ret, cpu_offset = 0;
292
293 while (length > 0) {
294 int cacheline_end = ALIGN(gpu_offset + 1, 64);
295 int this_length = min(cacheline_end - gpu_offset, length);
296 int swizzled_gpu_offset = gpu_offset ^ 64;
297
298 ret = __copy_from_user(gpu_vaddr + swizzled_gpu_offset,
299 cpu_vaddr + cpu_offset,
300 this_length);
301 if (ret)
302 return ret + length;
303
304 cpu_offset += this_length;
305 gpu_offset += this_length;
306 length -= this_length;
307 }
308
309 return 0;
310}
311
d174bd64
DV		 312/* Per-page copy function for the shmem pread fastpath.
313 * Flushes invalid cachelines before reading the target if
314 * needs_clflush is set. */
eb01459f 315static int
d174bd64
DV		 316shmem_pread_fast(struct page *page, int shmem_page_offset, int page_length,
317 char __user *user_data,
318 bool page_do_bit17_swizzling, bool needs_clflush)
319{
320 char *vaddr;
321 int ret;
322
e7e58eb5 323 if (unlikely(page_do_bit17_swizzling))
d174bd64
DV		 324 return -EINVAL;
325
326 vaddr = kmap_atomic(page);
327 if (needs_clflush)
328 drm_clflush_virt_range(vaddr + shmem_page_offset,
329 page_length);
330 ret = __copy_to_user_inatomic(user_data,
331 vaddr + shmem_page_offset,
332 page_length);
333 kunmap_atomic(vaddr);
334
335 return ret;
336}
337
23c18c71
DV		 338static void
339shmem_clflush_swizzled_range(char *addr, unsigned long length,
340 bool swizzled)
341{
e7e58eb5 342 if (unlikely(swizzled)) {
23c18c71
DV		 343 unsigned long start = (unsigned long) addr;
344 unsigned long end = (unsigned long) addr + length;
345
346 /* For swizzling simply ensure that we always flush both
347 * channels. Lame, but simple and it works. Swizzled
348 * pwrite/pread is far from a hotpath - current userspace
349 * doesn't use it at all. */
350 start = round_down(start, 128);
351 end = round_up(end, 128);
352
353 drm_clflush_virt_range((void *)start, end - start);
354 } else {
355 drm_clflush_virt_range(addr, length);
356 }
357
358}
359
d174bd64
DV		 360/* Only difference to the fast-path function is that this can handle bit17
361 * and uses non-atomic copy and kmap functions. */
362static int
363shmem_pread_slow(struct page *page, int shmem_page_offset, int page_length,
364 char __user *user_data,
365 bool page_do_bit17_swizzling, bool needs_clflush)
366{
367 char *vaddr;
368 int ret;
369
370 vaddr = kmap(page);
371 if (needs_clflush)
23c18c71
DV		 372 shmem_clflush_swizzled_range(vaddr + shmem_page_offset,
373 page_length,
374 page_do_bit17_swizzling);
d174bd64
DV		 375
376 if (page_do_bit17_swizzling)
377 ret = __copy_to_user_swizzled(user_data,
378 vaddr, shmem_page_offset,
379 page_length);
380 else
381 ret = __copy_to_user(user_data,
382 vaddr + shmem_page_offset,
383 page_length);
384 kunmap(page);
385
386 return ret;
387}
388
eb01459f 389static int
dbf7bff0
DV		 390i915_gem_shmem_pread(struct drm_device *dev,
391 struct drm_i915_gem_object *obj,
392 struct drm_i915_gem_pread *args,
393 struct drm_file *file)
eb01459f 394{
05394f39 395 struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping;
8461d226 396 char __user *user_data;
eb01459f 397 ssize_t remain;
8461d226 398 loff_t offset;
eb2c0c81 399 int shmem_page_offset, page_length, ret = 0;
8461d226 400 int obj_do_bit17_swizzling, page_do_bit17_swizzling;
dbf7bff0 401 int hit_slowpath = 0;
96d79b52 402 int prefaulted = 0;
8489731c 403 int needs_clflush = 0;
692a576b 404 int release_page;
eb01459f 405
8461d226 406 user_data = (char __user *) (uintptr_t) args->data_ptr;
eb01459f
EA		 407 remain = args->size;
408
8461d226 409 obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
eb01459f 410
8489731c
DV		 411 if (!(obj->base.read_domains & I915_GEM_DOMAIN_CPU)) {
412 /* If we're not in the cpu read domain, set ourself into the gtt
413 * read domain and manually flush cachelines (if required). This
414 * optimizes for the case when the gpu will dirty the data
415 * anyway again before the next pread happens. */
416 if (obj->cache_level == I915_CACHE_NONE)
417 needs_clflush = 1;
418 ret = i915_gem_object_set_to_gtt_domain(obj, false);
419 if (ret)
420 return ret;
421 }
eb01459f 422
8461d226 423 offset = args->offset;
eb01459f
EA		 424
425 while (remain > 0) {
e5281ccd
CW		 426 struct page *page;
427
eb01459f
EA		 428 /* Operation in this page
429 *
eb01459f 430 * shmem_page_offset = offset within page in shmem file
eb01459f
EA		 431 * page_length = bytes to copy for this page
432 */
c8cbbb8b 433 shmem_page_offset = offset_in_page(offset);
eb01459f
EA		 434 page_length = remain;
435 if ((shmem_page_offset + page_length) > PAGE_SIZE)
436 page_length = PAGE_SIZE - shmem_page_offset;
eb01459f 437
692a576b
DV		 438 if (obj->pages) {
439 page = obj->pages[offset >> PAGE_SHIFT];
440 release_page = 0;
441 } else {
442 page = shmem_read_mapping_page(mapping, offset >> PAGE_SHIFT);
443 if (IS_ERR(page)) {
444 ret = PTR_ERR(page);
445 goto out;
446 }
447 release_page = 1;
b65552f0 448 }
e5281ccd 449
8461d226
DV		 450 page_do_bit17_swizzling = obj_do_bit17_swizzling &&
451 (page_to_phys(page) & (1 << 17)) != 0;
452
d174bd64
DV		 453 ret = shmem_pread_fast(page, shmem_page_offset, page_length,
454 user_data, page_do_bit17_swizzling,
455 needs_clflush);
456 if (ret == 0)
457 goto next_page;
dbf7bff0
DV		 458
459 hit_slowpath = 1;
692a576b 460 page_cache_get(page);
dbf7bff0
DV		 461 mutex_unlock(&dev->struct_mutex);
462
96d79b52 463 if (!prefaulted) {
f56f821f 464 ret = fault_in_multipages_writeable(user_data, remain);
96d79b52
DV		 465 /* Userspace is tricking us, but we've already clobbered
466 * its pages with the prefault and promised to write the
467 * data up to the first fault. Hence ignore any errors
468 * and just continue. */
469 (void)ret;
470 prefaulted = 1;
471 }
eb01459f 472
d174bd64
DV		 473 ret = shmem_pread_slow(page, shmem_page_offset, page_length,
474 user_data, page_do_bit17_swizzling,
475 needs_clflush);
eb01459f 476
dbf7bff0 477 mutex_lock(&dev->struct_mutex);
e5281ccd 478 page_cache_release(page);
dbf7bff0 479next_page:
e5281ccd 480 mark_page_accessed(page);
692a576b
DV		 481 if (release_page)
482 page_cache_release(page);
e5281ccd 483
8461d226
DV		 484 if (ret) {
485 ret = -EFAULT;
486 goto out;
487 }
488
eb01459f 489 remain -= page_length;
8461d226 490 user_data += page_length;
eb01459f
EA		 491 offset += page_length;
492 }
493
4f27b75d 494out:
dbf7bff0
DV		 495 if (hit_slowpath) {
496 /* Fixup: Kill any reinstated backing storage pages */
497 if (obj->madv == __I915_MADV_PURGED)
498 i915_gem_object_truncate(obj);
499 }
eb01459f
EA		 500
501 return ret;
502}
503
673a394b
EA		 504/**
505 * Reads data from the object referenced by handle.
506 *
507 * On error, the contents of *data are undefined.
508 */
509int
510i915_gem_pread_ioctl(struct drm_device *dev, void *data,
05394f39 511 struct drm_file *file)
673a394b
EA		 512{
513 struct drm_i915_gem_pread *args = data;
05394f39 514 struct drm_i915_gem_object *obj;
35b62a89 515 int ret = 0;
673a394b 516
51311d0a
CW		 517 if (args->size == 0)
518 return 0;
519
520 if (!access_ok(VERIFY_WRITE,
521 (char __user *)(uintptr_t)args->data_ptr,
522 args->size))
523 return -EFAULT;
524
4f27b75d 525 ret = i915_mutex_lock_interruptible(dev);
1d7cfea1 526 if (ret)
4f27b75d 527 return ret;
673a394b 528
05394f39 529 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
c8725226 530 if (&obj->base == NULL) {
1d7cfea1
CW		 531 ret = -ENOENT;
532 goto unlock;
4f27b75d 533 }
673a394b 534
7dcd2499 535 /* Bounds check source. */
05394f39
CW		 536 if (args->offset > obj->base.size ||
537 args->size > obj->base.size - args->offset) {
ce9d419d 538 ret = -EINVAL;
35b62a89 539 goto out;
ce9d419d
CW		 540 }
541
1286ff73
DV		 542 /* prime objects have no backing filp to GEM pread/pwrite
543 * pages from.
544 */
545 if (!obj->base.filp) {
546 ret = -EINVAL;
547 goto out;
548 }
549
db53a302
CW		 550 trace_i915_gem_object_pread(obj, args->offset, args->size);
551
dbf7bff0 552 ret = i915_gem_shmem_pread(dev, obj, args, file);
673a394b 553
35b62a89 554out:
05394f39 555 drm_gem_object_unreference(&obj->base);
1d7cfea1 556unlock:
4f27b75d 557 mutex_unlock(&dev->struct_mutex);
eb01459f 558 return ret;
673a394b
EA		 559}
560
0839ccb8
KP		 561/* This is the fast write path which cannot handle
562 * page faults in the source data
9b7530cc 563 */
0839ccb8
KP		 564
565static inline int
566fast_user_write(struct io_mapping *mapping,
567 loff_t page_base, int page_offset,
568 char __user *user_data,
569 int length)
9b7530cc 570{
4f0c7cfb
BW		 571 void __iomem *vaddr_atomic;
572 void *vaddr;
0839ccb8 573 unsigned long unwritten;
9b7530cc 574
3e4d3af5 575 vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base);
4f0c7cfb
BW		 576 /* We can use the cpu mem copy function because this is X86. */
577 vaddr = (void __force*)vaddr_atomic + page_offset;
578 unwritten = __copy_from_user_inatomic_nocache(vaddr,
0839ccb8 579 user_data, length);
3e4d3af5 580 io_mapping_unmap_atomic(vaddr_atomic);
fbd5a26d 581 return unwritten;
0839ccb8
KP		 582}
583
3de09aa3
EA		 584/**
585 * This is the fast pwrite path, where we copy the data directly from the
586 * user into the GTT, uncached.
587 */
673a394b 588static int
05394f39
CW		 589i915_gem_gtt_pwrite_fast(struct drm_device *dev,
590 struct drm_i915_gem_object *obj,
3de09aa3 591 struct drm_i915_gem_pwrite *args,
05394f39 592 struct drm_file *file)
673a394b 593{
0839ccb8 594 drm_i915_private_t *dev_priv = dev->dev_private;
673a394b 595 ssize_t remain;
0839ccb8 596 loff_t offset, page_base;
673a394b 597 char __user *user_data;
935aaa69
DV		 598 int page_offset, page_length, ret;
599
600 ret = i915_gem_object_pin(obj, 0, true);
601 if (ret)
602 goto out;
603
604 ret = i915_gem_object_set_to_gtt_domain(obj, true);
605 if (ret)
606 goto out_unpin;
607
608 ret = i915_gem_object_put_fence(obj);
609 if (ret)
610 goto out_unpin;
673a394b
EA		 611
612 user_data = (char __user *) (uintptr_t) args->data_ptr;
613 remain = args->size;
673a394b 614
05394f39 615 offset = obj->gtt_offset + args->offset;
673a394b
EA		 616
617 while (remain > 0) {
618 /* Operation in this page
619 *
0839ccb8
KP		 620 * page_base = page offset within aperture
621 * page_offset = offset within page
622 * page_length = bytes to copy for this page
673a394b 623 */
c8cbbb8b
CW		 624 page_base = offset & PAGE_MASK;
625 page_offset = offset_in_page(offset);
0839ccb8
KP		 626 page_length = remain;
627 if ((page_offset + remain) > PAGE_SIZE)
628 page_length = PAGE_SIZE - page_offset;
629
0839ccb8 630 /* If we get a fault while copying data, then (presumably) our
3de09aa3
EA		 631 * source page isn't available. Return the error and we'll
632 * retry in the slow path.
0839ccb8 633 */
fbd5a26d 634 if (fast_user_write(dev_priv->mm.gtt_mapping, page_base,
935aaa69
DV		 635 page_offset, user_data, page_length)) {
636 ret = -EFAULT;
637 goto out_unpin;
638 }
673a394b 639
0839ccb8
KP		 640 remain -= page_length;
641 user_data += page_length;
642 offset += page_length;
673a394b 643 }
673a394b 644
935aaa69
DV		 645out_unpin:
646 i915_gem_object_unpin(obj);
647out:
3de09aa3 648 return ret;
673a394b
EA		 649}
650
d174bd64
DV		 651/* Per-page copy function for the shmem pwrite fastpath.
652 * Flushes invalid cachelines before writing to the target if
653 * needs_clflush_before is set and flushes out any written cachelines after
654 * writing if needs_clflush is set. */
3043c60c 655static int
d174bd64
DV		 656shmem_pwrite_fast(struct page *page, int shmem_page_offset, int page_length,
657 char __user *user_data,
658 bool page_do_bit17_swizzling,
659 bool needs_clflush_before,
660 bool needs_clflush_after)
673a394b 661{
d174bd64 662 char *vaddr;
673a394b 663 int ret;
3de09aa3 664
e7e58eb5 665 if (unlikely(page_do_bit17_swizzling))
d174bd64 666 return -EINVAL;
3de09aa3 667
d174bd64
DV		 668 vaddr = kmap_atomic(page);
669 if (needs_clflush_before)
670 drm_clflush_virt_range(vaddr + shmem_page_offset,
671 page_length);
672 ret = __copy_from_user_inatomic_nocache(vaddr + shmem_page_offset,
673 user_data,
674 page_length);
675 if (needs_clflush_after)
676 drm_clflush_virt_range(vaddr + shmem_page_offset,
677 page_length);
678 kunmap_atomic(vaddr);
3de09aa3
EA		 679
680 return ret;
681}
682
d174bd64
DV		 683/* Only difference to the fast-path function is that this can handle bit17
684 * and uses non-atomic copy and kmap functions. */
3043c60c 685static int
d174bd64
DV		 686shmem_pwrite_slow(struct page *page, int shmem_page_offset, int page_length,
687 char __user *user_data,
688 bool page_do_bit17_swizzling,
689 bool needs_clflush_before,
690 bool needs_clflush_after)
673a394b 691{
d174bd64
DV		 692 char *vaddr;
693 int ret;
e5281ccd 694
d174bd64 695 vaddr = kmap(page);
e7e58eb5 696 if (unlikely(needs_clflush_before || page_do_bit17_swizzling))
23c18c71
DV		 697 shmem_clflush_swizzled_range(vaddr + shmem_page_offset,
698 page_length,
699 page_do_bit17_swizzling);
d174bd64
DV		 700 if (page_do_bit17_swizzling)
701 ret = __copy_from_user_swizzled(vaddr, shmem_page_offset,
e5281ccd
CW		 702 user_data,
703 page_length);
d174bd64
DV		 704 else
705 ret = __copy_from_user(vaddr + shmem_page_offset,
706 user_data,
707 page_length);
708 if (needs_clflush_after)
23c18c71
DV		 709 shmem_clflush_swizzled_range(vaddr + shmem_page_offset,
710 page_length,
711 page_do_bit17_swizzling);
d174bd64 712 kunmap(page);
40123c1f 713
d174bd64 714 return ret;
40123c1f
EA		 715}
716
40123c1f 717static int
e244a443
DV		 718i915_gem_shmem_pwrite(struct drm_device *dev,
719 struct drm_i915_gem_object *obj,
720 struct drm_i915_gem_pwrite *args,
721 struct drm_file *file)
40123c1f 722{
05394f39 723 struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping;
40123c1f 724 ssize_t remain;
8c59967c
DV		 725 loff_t offset;
726 char __user *user_data;
eb2c0c81 727 int shmem_page_offset, page_length, ret = 0;
8c59967c 728 int obj_do_bit17_swizzling, page_do_bit17_swizzling;
e244a443 729 int hit_slowpath = 0;
58642885
DV		 730 int needs_clflush_after = 0;
731 int needs_clflush_before = 0;
692a576b 732 int release_page;
40123c1f 733
8c59967c 734 user_data = (char __user *) (uintptr_t) args->data_ptr;
40123c1f
EA		 735 remain = args->size;
736
8c59967c 737 obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
40123c1f 738
58642885
DV		 739 if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) {
740 /* If we're not in the cpu write domain, set ourself into the gtt
741 * write domain and manually flush cachelines (if required). This
742 * optimizes for the case when the gpu will use the data
743 * right away and we therefore have to clflush anyway. */
744 if (obj->cache_level == I915_CACHE_NONE)
745 needs_clflush_after = 1;
746 ret = i915_gem_object_set_to_gtt_domain(obj, true);
747 if (ret)
748 return ret;
749 }
750 /* Same trick applies for invalidate partially written cachelines before
751 * writing. */
752 if (!(obj->base.read_domains & I915_GEM_DOMAIN_CPU)
753 && obj->cache_level == I915_CACHE_NONE)
754 needs_clflush_before = 1;
755
673a394b 756 offset = args->offset;
05394f39 757 obj->dirty = 1;
673a394b 758
40123c1f 759 while (remain > 0) {
e5281ccd 760 struct page *page;
58642885 761 int partial_cacheline_write;
e5281ccd 762
40123c1f
EA		 763 /* Operation in this page
764 *
40123c1f 765 * shmem_page_offset = offset within page in shmem file
40123c1f
EA		 766 * page_length = bytes to copy for this page
767 */
c8cbbb8b 768 shmem_page_offset = offset_in_page(offset);
40123c1f
EA		 769
770 page_length = remain;
771 if ((shmem_page_offset + page_length) > PAGE_SIZE)
772 page_length = PAGE_SIZE - shmem_page_offset;
40123c1f 773
58642885
DV		 774 /* If we don't overwrite a cacheline completely we need to be
775 * careful to have up-to-date data by first clflushing. Don't
776 * overcomplicate things and flush the entire patch. */
777 partial_cacheline_write = needs_clflush_before &&
778 ((shmem_page_offset | page_length)
779 & (boot_cpu_data.x86_clflush_size - 1));
780
692a576b
DV		 781 if (obj->pages) {
782 page = obj->pages[offset >> PAGE_SHIFT];
783 release_page = 0;
784 } else {
785 page = shmem_read_mapping_page(mapping, offset >> PAGE_SHIFT);
786 if (IS_ERR(page)) {
787 ret = PTR_ERR(page);
788 goto out;
789 }
790 release_page = 1;
e5281ccd
CW		 791 }
792
8c59967c
DV		 793 page_do_bit17_swizzling = obj_do_bit17_swizzling &&
794 (page_to_phys(page) & (1 << 17)) != 0;
795
d174bd64
DV		 796 ret = shmem_pwrite_fast(page, shmem_page_offset, page_length,
797 user_data, page_do_bit17_swizzling,
798 partial_cacheline_write,
799 needs_clflush_after);
800 if (ret == 0)
801 goto next_page;
e244a443
DV		 802
803 hit_slowpath = 1;
692a576b 804 page_cache_get(page);
e244a443
DV		 805 mutex_unlock(&dev->struct_mutex);
806
d174bd64
DV		 807 ret = shmem_pwrite_slow(page, shmem_page_offset, page_length,
808 user_data, page_do_bit17_swizzling,
809 partial_cacheline_write,
810 needs_clflush_after);
40123c1f 811
e244a443 812 mutex_lock(&dev->struct_mutex);
692a576b 813 page_cache_release(page);
e244a443 814next_page:
e5281ccd
CW		 815 set_page_dirty(page);
816 mark_page_accessed(page);
692a576b
DV		 817 if (release_page)
818 page_cache_release(page);
e5281ccd 819
8c59967c
DV		 820 if (ret) {
821 ret = -EFAULT;
822 goto out;
823 }
824
40123c1f 825 remain -= page_length;
8c59967c 826 user_data += page_length;
40123c1f 827 offset += page_length;
673a394b
EA		 828 }
829
fbd5a26d 830out:
e244a443
DV		 831 if (hit_slowpath) {
832 /* Fixup: Kill any reinstated backing storage pages */
833 if (obj->madv == __I915_MADV_PURGED)
834 i915_gem_object_truncate(obj);
835 /* and flush dirty cachelines in case the object isn't in the cpu write
836 * domain anymore. */
837 if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) {
838 i915_gem_clflush_object(obj);
839 intel_gtt_chipset_flush();
840 }
8c59967c 841 }
673a394b 842
58642885
DV		 843 if (needs_clflush_after)
844 intel_gtt_chipset_flush();
845
40123c1f 846 return ret;
673a394b
EA		 847}
848
849/**
850 * Writes data to the object referenced by handle.
851 *
852 * On error, the contents of the buffer that were to be modified are undefined.
853 */
854int
855i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
fbd5a26d 856 struct drm_file *file)
673a394b
EA		 857{
858 struct drm_i915_gem_pwrite *args = data;
05394f39 859 struct drm_i915_gem_object *obj;
51311d0a
CW		 860 int ret;
861
862 if (args->size == 0)
863 return 0;
864
865 if (!access_ok(VERIFY_READ,
866 (char __user *)(uintptr_t)args->data_ptr,
867 args->size))
868 return -EFAULT;
869
f56f821f
DV		 870 ret = fault_in_multipages_readable((char __user *)(uintptr_t)args->data_ptr,
871 args->size);
51311d0a
CW		 872 if (ret)
873 return -EFAULT;
673a394b 874
fbd5a26d 875 ret = i915_mutex_lock_interruptible(dev);
1d7cfea1 876 if (ret)
fbd5a26d 877 return ret;
1d7cfea1 878
05394f39 879 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
c8725226 880 if (&obj->base == NULL) {
1d7cfea1
CW		 881 ret = -ENOENT;
882 goto unlock;
fbd5a26d 883 }
673a394b 884
7dcd2499 885 /* Bounds check destination. */
05394f39
CW		 886 if (args->offset > obj->base.size ||
887 args->size > obj->base.size - args->offset) {
ce9d419d 888 ret = -EINVAL;
35b62a89 889 goto out;
ce9d419d
CW		 890 }
891
1286ff73
DV		 892 /* prime objects have no backing filp to GEM pread/pwrite
893 * pages from.
894 */
895 if (!obj->base.filp) {
896 ret = -EINVAL;
897 goto out;
898 }
899
db53a302
CW		 900 trace_i915_gem_object_pwrite(obj, args->offset, args->size);
901
935aaa69 902 ret = -EFAULT;
673a394b
EA		 903 /* We can only do the GTT pwrite on untiled buffers, as otherwise
904 * it would end up going through the fenced access, and we'll get
905 * different detiling behavior between reading and writing.
906 * pread/pwrite currently are reading and writing from the CPU
907 * perspective, requiring manual detiling by the client.
908 */
5c0480f2 909 if (obj->phys_obj) {
fbd5a26d 910 ret = i915_gem_phys_pwrite(dev, obj, args, file);
5c0480f2
DV		 911 goto out;
912 }
913
914 if (obj->gtt_space &&
3ae53783 915 obj->cache_level == I915_CACHE_NONE &&
c07496fa 916 obj->tiling_mode == I915_TILING_NONE &&
ffc62976 917 obj->map_and_fenceable &&
5c0480f2 918 obj->base.write_domain != I915_GEM_DOMAIN_CPU) {
fbd5a26d 919 ret = i915_gem_gtt_pwrite_fast(dev, obj, args, file);
935aaa69
DV		 920 /* Note that the gtt paths might fail with non-page-backed user
921 * pointers (e.g. gtt mappings when moving data between
922 * textures). Fallback to the shmem path in that case. */
fbd5a26d 923 }
673a394b 924
5c0480f2 925 if (ret == -EFAULT)
935aaa69 926 ret = i915_gem_shmem_pwrite(dev, obj, args, file);
5c0480f2 927
35b62a89 928out:
05394f39 929 drm_gem_object_unreference(&obj->base);
1d7cfea1 930unlock:
fbd5a26d 931 mutex_unlock(&dev->struct_mutex);
673a394b
EA		 932 return ret;
933}
934
935/**
2ef7eeaa
EA		 936 * Called when user space prepares to use an object with the CPU, either
937 * through the mmap ioctl's mapping or a GTT mapping.
673a394b
EA		 938 */
939int
940i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
05394f39 941 struct drm_file *file)
673a394b
EA		 942{
943 struct drm_i915_gem_set_domain *args = data;
05394f39 944 struct drm_i915_gem_object *obj;
2ef7eeaa
EA		 945 uint32_t read_domains = args->read_domains;
946 uint32_t write_domain = args->write_domain;
673a394b
EA		 947 int ret;
948
2ef7eeaa 949 /* Only handle setting domains to types used by the CPU. */
21d509e3 950 if (write_domain & I915_GEM_GPU_DOMAINS)
2ef7eeaa
EA		 951 return -EINVAL;
952
21d509e3 953 if (read_domains & I915_GEM_GPU_DOMAINS)
2ef7eeaa
EA		 954 return -EINVAL;
955
956 /* Having something in the write domain implies it's in the read
957 * domain, and only that read domain. Enforce that in the request.
958 */
959 if (write_domain != 0 && read_domains != write_domain)
960 return -EINVAL;
961
76c1dec1 962 ret = i915_mutex_lock_interruptible(dev);
1d7cfea1 963 if (ret)
76c1dec1 964 return ret;
1d7cfea1 965
05394f39 966 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
c8725226 967 if (&obj->base == NULL) {
1d7cfea1
CW		 968 ret = -ENOENT;
969 goto unlock;
76c1dec1 970 }
673a394b 971
2ef7eeaa
EA		 972 if (read_domains & I915_GEM_DOMAIN_GTT) {
973 ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0);
02354392
EA		 974
975 /* Silently promote "you're not bound, there was nothing to do"
976 * to success, since the client was just asking us to
977 * make sure everything was done.
978 */
979 if (ret == -EINVAL)
980 ret = 0;
2ef7eeaa 981 } else {
e47c68e9 982 ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0);
2ef7eeaa
EA		 983 }
984
05394f39 985 drm_gem_object_unreference(&obj->base);
1d7cfea1 986unlock:
673a394b
EA		 987 mutex_unlock(&dev->struct_mutex);
988 return ret;
989}
990
991/**
992 * Called when user space has done writes to this buffer
993 */
994int
995i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
05394f39 996 struct drm_file *file)
673a394b
EA		 997{
998 struct drm_i915_gem_sw_finish *args = data;
05394f39 999 struct drm_i915_gem_object *obj;
673a394b
EA		 1000 int ret = 0;
1001
76c1dec1 1002 ret = i915_mutex_lock_interruptible(dev);
1d7cfea1 1003 if (ret)
76c1dec1 1004 return ret;
1d7cfea1 1005
05394f39 1006 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
c8725226 1007 if (&obj->base == NULL) {
1d7cfea1
CW		 1008 ret = -ENOENT;
1009 goto unlock;
673a394b
EA		 1010 }
1011
673a394b 1012 /* Pinned buffers may be scanout, so flush the cache */
05394f39 1013 if (obj->pin_count)
e47c68e9
EA		 1014 i915_gem_object_flush_cpu_write_domain(obj);
1015
05394f39 1016 drm_gem_object_unreference(&obj->base);
1d7cfea1 1017unlock:
673a394b
EA		 1018 mutex_unlock(&dev->struct_mutex);
1019 return ret;
1020}
1021
1022/**
1023 * Maps the contents of an object, returning the address it is mapped
1024 * into.
1025 *
1026 * While the mapping holds a reference on the contents of the object, it doesn't
1027 * imply a ref on the object itself.
1028 */
1029int
1030i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
05394f39 1031 struct drm_file *file)
673a394b
EA		 1032{
1033 struct drm_i915_gem_mmap *args = data;
1034 struct drm_gem_object *obj;
673a394b
EA		 1035 unsigned long addr;
1036
05394f39 1037 obj = drm_gem_object_lookup(dev, file, args->handle);
673a394b 1038 if (obj == NULL)
bf79cb91 1039 return -ENOENT;
673a394b 1040
1286ff73
DV		 1041 /* prime objects have no backing filp to GEM mmap
1042 * pages from.
1043 */
1044 if (!obj->filp) {
1045 drm_gem_object_unreference_unlocked(obj);
1046 return -EINVAL;
1047 }
1048
6be5ceb0 1049 addr = vm_mmap(obj->filp, 0, args->size,
673a394b
EA		 1050 PROT_READ | PROT_WRITE, MAP_SHARED,
1051 args->offset);
bc9025bd 1052 drm_gem_object_unreference_unlocked(obj);
673a394b
EA		 1053 if (IS_ERR((void *)addr))
1054 return addr;
1055
1056 args->addr_ptr = (uint64_t) addr;
1057
1058 return 0;
1059}
1060
de151cf6
JB		 1061/**
1062 * i915_gem_fault - fault a page into the GTT
1063 * vma: VMA in question
1064 * vmf: fault info
1065 *
1066 * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped
1067 * from userspace. The fault handler takes care of binding the object to
1068 * the GTT (if needed), allocating and programming a fence register (again,
1069 * only if needed based on whether the old reg is still valid or the object
1070 * is tiled) and inserting a new PTE into the faulting process.
1071 *
1072 * Note that the faulting process may involve evicting existing objects
1073 * from the GTT and/or fence registers to make room. So performance may
1074 * suffer if the GTT working set is large or there are few fence registers
1075 * left.
1076 */
1077int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf)
1078{
05394f39
CW		 1079 struct drm_i915_gem_object *obj = to_intel_bo(vma->vm_private_data);
1080 struct drm_device *dev = obj->base.dev;
7d1c4804 1081 drm_i915_private_t *dev_priv = dev->dev_private;
de151cf6
JB		 1082 pgoff_t page_offset;
1083 unsigned long pfn;
1084 int ret = 0;
0f973f27 1085 bool write = !!(vmf->flags & FAULT_FLAG_WRITE);
de151cf6
JB		 1086
1087 /* We don't use vmf->pgoff since that has the fake offset */
1088 page_offset = ((unsigned long)vmf->virtual_address - vma->vm_start) >>
1089 PAGE_SHIFT;
1090
d9bc7e9f
CW		 1091 ret = i915_mutex_lock_interruptible(dev);
1092 if (ret)
1093 goto out;
a00b10c3 1094
db53a302
CW		 1095 trace_i915_gem_object_fault(obj, page_offset, true, write);
1096
d9bc7e9f 1097 /* Now bind it into the GTT if needed */
919926ae
CW		 1098 if (!obj->map_and_fenceable) {
1099 ret = i915_gem_object_unbind(obj);
1100 if (ret)
1101 goto unlock;
a00b10c3 1102 }
05394f39 1103 if (!obj->gtt_space) {
75e9e915 1104 ret = i915_gem_object_bind_to_gtt(obj, 0, true);
c715089f
CW		 1105 if (ret)
1106 goto unlock;
de151cf6 1107
e92d03bf
EA		 1108 ret = i915_gem_object_set_to_gtt_domain(obj, write);
1109 if (ret)
1110 goto unlock;
1111 }
4a684a41 1112
74898d7e
DV		 1113 if (!obj->has_global_gtt_mapping)
1114 i915_gem_gtt_bind_object(obj, obj->cache_level);
1115
06d98131 1116 ret = i915_gem_object_get_fence(obj);
d9e86c0e
CW		 1117 if (ret)
1118 goto unlock;
de151cf6 1119
05394f39
CW		 1120 if (i915_gem_object_is_inactive(obj))
1121 list_move_tail(&obj->mm_list, &dev_priv->mm.inactive_list);
7d1c4804 1122
6299f992
CW		 1123 obj->fault_mappable = true;
1124
05394f39 1125 pfn = ((dev->agp->base + obj->gtt_offset) >> PAGE_SHIFT) +
de151cf6
JB		 1126 page_offset;
1127
1128 /* Finally, remap it using the new GTT offset */
1129 ret = vm_insert_pfn(vma, (unsigned long)vmf->virtual_address, pfn);
c715089f 1130unlock:
de151cf6 1131 mutex_unlock(&dev->struct_mutex);
d9bc7e9f 1132out:
de151cf6 1133 switch (ret) {
d9bc7e9f 1134 case -EIO:
045e769a 1135 case -EAGAIN:
d9bc7e9f
CW		 1136 /* Give the error handler a chance to run and move the
1137 * objects off the GPU active list. Next time we service the
1138 * fault, we should be able to transition the page into the
1139 * GTT without touching the GPU (and so avoid further
1140 * EIO/EGAIN). If the GPU is wedged, then there is no issue
1141 * with coherency, just lost writes.
1142 */
045e769a 1143 set_need_resched();
c715089f
CW		 1144 case 0:
1145 case -ERESTARTSYS:
bed636ab 1146 case -EINTR:
c715089f 1147 return VM_FAULT_NOPAGE;
de151cf6 1148 case -ENOMEM:
de151cf6 1149 return VM_FAULT_OOM;
de151cf6 1150 default:
c715089f 1151 return VM_FAULT_SIGBUS;
de151cf6
JB		 1152 }
1153}
1154
901782b2
CW		 1155/**
1156 * i915_gem_release_mmap - remove physical page mappings
1157 * @obj: obj in question
1158 *
af901ca1 1159 * Preserve the reservation of the mmapping with the DRM core code, but
901782b2
CW		 1160 * relinquish ownership of the pages back to the system.
1161 *
1162 * It is vital that we remove the page mapping if we have mapped a tiled
1163 * object through the GTT and then lose the fence register due to
1164 * resource pressure. Similarly if the object has been moved out of the
1165 * aperture, than pages mapped into userspace must be revoked. Removing the
1166 * mapping will then trigger a page fault on the next user access, allowing
1167 * fixup by i915_gem_fault().
1168 */
d05ca301 1169void
05394f39 1170i915_gem_release_mmap(struct drm_i915_gem_object *obj)
901782b2 1171{
6299f992
CW		 1172 if (!obj->fault_mappable)
1173 return;
901782b2 1174
f6e47884
CW		 1175 if (obj->base.dev->dev_mapping)
1176 unmap_mapping_range(obj->base.dev->dev_mapping,
1177 (loff_t)obj->base.map_list.hash.key<<PAGE_SHIFT,
1178 obj->base.size, 1);
fb7d516a 1179
6299f992 1180 obj->fault_mappable = false;
901782b2
CW		 1181}
1182
92b88aeb 1183static uint32_t
e28f8711 1184i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode)
92b88aeb 1185{
e28f8711 1186 uint32_t gtt_size;
92b88aeb
CW		 1187
1188 if (INTEL_INFO(dev)->gen >= 4 ||
e28f8711
CW		 1189 tiling_mode == I915_TILING_NONE)
1190 return size;
92b88aeb
CW		 1191
1192 /* Previous chips need a power-of-two fence region when tiling */
1193 if (INTEL_INFO(dev)->gen == 3)
e28f8711 1194 gtt_size = 1024*1024;
92b88aeb 1195 else
e28f8711 1196 gtt_size = 512*1024;
92b88aeb 1197
e28f8711
CW		 1198 while (gtt_size < size)
1199 gtt_size <<= 1;
92b88aeb 1200
e28f8711 1201 return gtt_size;
92b88aeb
CW		 1202}
1203
de151cf6
JB		 1204/**
1205 * i915_gem_get_gtt_alignment - return required GTT alignment for an object
1206 * @obj: object to check
1207 *
1208 * Return the required GTT alignment for an object, taking into account
5e783301 1209 * potential fence register mapping.
de151cf6
JB		 1210 */
1211static uint32_t
e28f8711
CW		 1212i915_gem_get_gtt_alignment(struct drm_device *dev,
1213 uint32_t size,
1214 int tiling_mode)
de151cf6 1215{
de151cf6
JB		 1216 /*
1217 * Minimum alignment is 4k (GTT page size), but might be greater
1218 * if a fence register is needed for the object.
1219 */
a00b10c3 1220 if (INTEL_INFO(dev)->gen >= 4 ||
e28f8711 1221 tiling_mode == I915_TILING_NONE)
de151cf6
JB		 1222 return 4096;
1223
a00b10c3
CW		 1224 /*
1225 * Previous chips need to be aligned to the size of the smallest
1226 * fence register that can contain the object.
1227 */
e28f8711 1228 return i915_gem_get_gtt_size(dev, size, tiling_mode);
a00b10c3
CW		 1229}
1230
5e783301
DV		 1231/**
1232 * i915_gem_get_unfenced_gtt_alignment - return required GTT alignment for an
1233 * unfenced object
e28f8711
CW		 1234 * @dev: the device
1235 * @size: size of the object
1236 * @tiling_mode: tiling mode of the object
5e783301
DV		 1237 *
1238 * Return the required GTT alignment for an object, only taking into account
1239 * unfenced tiled surface requirements.
1240 */
467cffba 1241uint32_t
e28f8711
CW		 1242i915_gem_get_unfenced_gtt_alignment(struct drm_device *dev,
1243 uint32_t size,
1244 int tiling_mode)
5e783301 1245{
5e783301
DV		 1246 /*
1247 * Minimum alignment is 4k (GTT page size) for sane hw.
1248 */
1249 if (INTEL_INFO(dev)->gen >= 4 || IS_G33(dev) ||
e28f8711 1250 tiling_mode == I915_TILING_NONE)
5e783301
DV		 1251 return 4096;
1252
e28f8711
CW		 1253 /* Previous hardware however needs to be aligned to a power-of-two
1254 * tile height. The simplest method for determining this is to reuse
1255 * the power-of-tile object size.
5e783301 1256 */
e28f8711 1257 return i915_gem_get_gtt_size(dev, size, tiling_mode);
5e783301
DV		 1258}
1259
de151cf6 1260int
ff72145b
DA		 1261i915_gem_mmap_gtt(struct drm_file *file,
1262 struct drm_device *dev,
1263 uint32_t handle,
1264 uint64_t *offset)
de151cf6 1265{
da761a6e 1266 struct drm_i915_private *dev_priv = dev->dev_private;
05394f39 1267 struct drm_i915_gem_object *obj;
de151cf6
JB		 1268 int ret;
1269
76c1dec1 1270 ret = i915_mutex_lock_interruptible(dev);
1d7cfea1 1271 if (ret)
76c1dec1 1272 return ret;
de151cf6 1273
ff72145b 1274 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
c8725226 1275 if (&obj->base == NULL) {
1d7cfea1
CW		 1276 ret = -ENOENT;
1277 goto unlock;
1278 }
de151cf6 1279
05394f39 1280 if (obj->base.size > dev_priv->mm.gtt_mappable_end) {
da761a6e 1281 ret = -E2BIG;
ff56b0bc 1282 goto out;
da761a6e
CW		 1283 }
1284
05394f39 1285 if (obj->madv != I915_MADV_WILLNEED) {
ab18282d 1286 DRM_ERROR("Attempting to mmap a purgeable buffer\n");
1d7cfea1
CW		 1287 ret = -EINVAL;
1288 goto out;
ab18282d
CW		 1289 }
1290
05394f39 1291 if (!obj->base.map_list.map) {
b464e9a2 1292 ret = drm_gem_create_mmap_offset(&obj->base);
1d7cfea1
CW		 1293 if (ret)
1294 goto out;
de151cf6
JB		 1295 }
1296
ff72145b 1297 *offset = (u64)obj->base.map_list.hash.key << PAGE_SHIFT;
de151cf6 1298
1d7cfea1 1299out:
05394f39 1300 drm_gem_object_unreference(&obj->base);
1d7cfea1 1301unlock:
de151cf6 1302 mutex_unlock(&dev->struct_mutex);
1d7cfea1 1303 return ret;
de151cf6
JB		 1304}
1305
ff72145b
DA		 1306/**
1307 * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing
1308 * @dev: DRM device
1309 * @data: GTT mapping ioctl data
1310 * @file: GEM object info
1311 *
1312 * Simply returns the fake offset to userspace so it can mmap it.
1313 * The mmap call will end up in drm_gem_mmap(), which will set things
1314 * up so we can get faults in the handler above.
1315 *
1316 * The fault handler will take care of binding the object into the GTT
1317 * (since it may have been evicted to make room for something), allocating
1318 * a fence register, and mapping the appropriate aperture address into
1319 * userspace.
1320 */
1321int
1322i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
1323 struct drm_file *file)
1324{
1325 struct drm_i915_gem_mmap_gtt *args = data;
1326
ff72145b
DA		 1327 return i915_gem_mmap_gtt(file, dev, args->handle, &args->offset);
1328}
1329
1286ff73 1330int
05394f39 1331i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj,
e5281ccd
CW		 1332 gfp_t gfpmask)
1333{
e5281ccd
CW		 1334 int page_count, i;
1335 struct address_space *mapping;
1336 struct inode *inode;
1337 struct page *page;
1338
1286ff73
DV		 1339 if (obj->pages || obj->sg_table)
1340 return 0;
1341
e5281ccd
CW		 1342 /* Get the list of pages out of our struct file. They'll be pinned
1343 * at this point until we release them.
1344 */
05394f39
CW		 1345 page_count = obj->base.size / PAGE_SIZE;
1346 BUG_ON(obj->pages != NULL);
1347 obj->pages = drm_malloc_ab(page_count, sizeof(struct page *));
1348 if (obj->pages == NULL)
e5281ccd
CW		 1349 return -ENOMEM;
1350
05394f39 1351 inode = obj->base.filp->f_path.dentry->d_inode;
e5281ccd 1352 mapping = inode->i_mapping;
5949eac4
HD		 1353 gfpmask |= mapping_gfp_mask(mapping);
1354
e5281ccd 1355 for (i = 0; i < page_count; i++) {
5949eac4 1356 page = shmem_read_mapping_page_gfp(mapping, i, gfpmask);
e5281ccd
CW		 1357 if (IS_ERR(page))
1358 goto err_pages;
1359
05394f39 1360 obj->pages[i] = page;
e5281ccd
CW		 1361 }
1362
6dacfd2f 1363 if (i915_gem_object_needs_bit17_swizzle(obj))
e5281ccd
CW		 1364 i915_gem_object_do_bit_17_swizzle(obj);
1365
1366 return 0;
1367
1368err_pages:
1369 while (i--)
05394f39 1370 page_cache_release(obj->pages[i]);
e5281ccd 1371
05394f39
CW		 1372 drm_free_large(obj->pages);
1373 obj->pages = NULL;
e5281ccd
CW		 1374 return PTR_ERR(page);
1375}
1376
5cdf5881 1377static void
05394f39 1378i915_gem_object_put_pages_gtt(struct drm_i915_gem_object *obj)
673a394b 1379{
05394f39 1380 int page_count = obj->base.size / PAGE_SIZE;
673a394b
EA		 1381 int i;
1382
1286ff73
DV		 1383 if (!obj->pages)
1384 return;
1385
05394f39 1386 BUG_ON(obj->madv == __I915_MADV_PURGED);
673a394b 1387
6dacfd2f 1388 if (i915_gem_object_needs_bit17_swizzle(obj))
280b713b
EA		 1389 i915_gem_object_save_bit_17_swizzle(obj);
1390
05394f39
CW		 1391 if (obj->madv == I915_MADV_DONTNEED)
1392 obj->dirty = 0;
3ef94daa
CW		 1393
1394 for (i = 0; i < page_count; i++) {
05394f39
CW		 1395 if (obj->dirty)
1396 set_page_dirty(obj->pages[i]);
3ef94daa 1397
05394f39
CW		 1398 if (obj->madv == I915_MADV_WILLNEED)
1399 mark_page_accessed(obj->pages[i]);
3ef94daa 1400
05394f39 1401 page_cache_release(obj->pages[i]);
3ef94daa 1402 }
05394f39 1403 obj->dirty = 0;
673a394b 1404
05394f39
CW		 1405 drm_free_large(obj->pages);
1406 obj->pages = NULL;
673a394b
EA		 1407}
1408
54cf91dc 1409void
05394f39 1410i915_gem_object_move_to_active(struct drm_i915_gem_object *obj,
1ec14ad3
CW		 1411 struct intel_ring_buffer *ring,
1412 u32 seqno)
673a394b 1413{
05394f39 1414 struct drm_device *dev = obj->base.dev;
69dc4987 1415 struct drm_i915_private *dev_priv = dev->dev_private;
617dbe27 1416
852835f3 1417 BUG_ON(ring == NULL);
05394f39 1418 obj->ring = ring;
673a394b
EA		 1419
1420 /* Add a reference if we're newly entering the active list. */
05394f39
CW		 1421 if (!obj->active) {
1422 drm_gem_object_reference(&obj->base);
1423 obj->active = 1;
673a394b 1424 }
e35a41de 1425
673a394b 1426 /* Move from whatever list we were on to the tail of execution. */
05394f39
CW		 1427 list_move_tail(&obj->mm_list, &dev_priv->mm.active_list);
1428 list_move_tail(&obj->ring_list, &ring->active_list);
caea7476 1429
05394f39 1430 obj->last_rendering_seqno = seqno;
caea7476 1431
7dd49065 1432 if (obj->fenced_gpu_access) {
caea7476 1433 obj->last_fenced_seqno = seqno;
caea7476 1434
7dd49065
CW		 1435 /* Bump MRU to take account of the delayed flush */
1436 if (obj->fence_reg != I915_FENCE_REG_NONE) {
1437 struct drm_i915_fence_reg *reg;
1438
1439 reg = &dev_priv->fence_regs[obj->fence_reg];
1440 list_move_tail(&reg->lru_list,
1441 &dev_priv->mm.fence_list);
1442 }
caea7476
CW		 1443 }
1444}
1445
1446static void
1447i915_gem_object_move_off_active(struct drm_i915_gem_object *obj)
1448{
1449 list_del_init(&obj->ring_list);
1450 obj->last_rendering_seqno = 0;
15a13bbd 1451 obj->last_fenced_seqno = 0;
673a394b
EA		 1452}
1453
ce44b0ea 1454static void
05394f39 1455i915_gem_object_move_to_flushing(struct drm_i915_gem_object *obj)
ce44b0ea 1456{
05394f39 1457 struct drm_device *dev = obj->base.dev;
ce44b0ea 1458 drm_i915_private_t *dev_priv = dev->dev_private;
ce44b0ea 1459
05394f39
CW		 1460 BUG_ON(!obj->active);
1461 list_move_tail(&obj->mm_list, &dev_priv->mm.flushing_list);
caea7476
CW		 1462
1463 i915_gem_object_move_off_active(obj);
1464}
1465
1466static void
1467i915_gem_object_move_to_inactive(struct drm_i915_gem_object *obj)
1468{
1469 struct drm_device *dev = obj->base.dev;
1470 struct drm_i915_private *dev_priv = dev->dev_private;
1471
1b50247a 1472 list_move_tail(&obj->mm_list, &dev_priv->mm.inactive_list);
caea7476
CW		 1473
1474 BUG_ON(!list_empty(&obj->gpu_write_list));
1475 BUG_ON(!obj->active);
1476 obj->ring = NULL;
1477
1478 i915_gem_object_move_off_active(obj);
1479 obj->fenced_gpu_access = false;
caea7476
CW		 1480
1481 obj->active = 0;
87ca9c8a 1482 obj->pending_gpu_write = false;
caea7476
CW		 1483 drm_gem_object_unreference(&obj->base);
1484
1485 WARN_ON(i915_verify_lists(dev));
ce44b0ea 1486}
673a394b 1487
963b4836
CW		 1488/* Immediately discard the backing storage */
1489static void
05394f39 1490i915_gem_object_truncate(struct drm_i915_gem_object *obj)
963b4836 1491{
bb6baf76 1492 struct inode *inode;
963b4836 1493
ae9fed6b
CW		 1494 /* Our goal here is to return as much of the memory as
1495 * is possible back to the system as we are called from OOM.
1496 * To do this we must instruct the shmfs to drop all of its
e2377fe0 1497 * backing pages, *now*.
ae9fed6b 1498 */
05394f39 1499 inode = obj->base.filp->f_path.dentry->d_inode;
e2377fe0 1500 shmem_truncate_range(inode, 0, (loff_t)-1);
bb6baf76 1501
a14917ee
CW		 1502 if (obj->base.map_list.map)
1503 drm_gem_free_mmap_offset(&obj->base);
1504
05394f39 1505 obj->madv = __I915_MADV_PURGED;
963b4836
CW		 1506}
1507
1508static inline int
05394f39 1509i915_gem_object_is_purgeable(struct drm_i915_gem_object *obj)
963b4836 1510{
05394f39 1511 return obj->madv == I915_MADV_DONTNEED;
963b4836
CW		 1512}
1513
63560396 1514static void
db53a302
CW		 1515i915_gem_process_flushing_list(struct intel_ring_buffer *ring,
1516 uint32_t flush_domains)
63560396 1517{
05394f39 1518 struct drm_i915_gem_object *obj, *next;
63560396 1519
05394f39 1520 list_for_each_entry_safe(obj, next,
64193406 1521 &ring->gpu_write_list,
63560396 1522 gpu_write_list) {
05394f39
CW		 1523 if (obj->base.write_domain & flush_domains) {
1524 uint32_t old_write_domain = obj->base.write_domain;
63560396 1525
05394f39
CW		 1526 obj->base.write_domain = 0;
1527 list_del_init(&obj->gpu_write_list);
1ec14ad3 1528 i915_gem_object_move_to_active(obj, ring,
db53a302 1529 i915_gem_next_request_seqno(ring));
63560396 1530
63560396 1531 trace_i915_gem_object_change_domain(obj,
05394f39 1532 obj->base.read_domains,
63560396
DV		 1533 old_write_domain);
1534 }
1535 }
1536}
8187a2b7 1537
53d227f2
DV		 1538static u32
1539i915_gem_get_seqno(struct drm_device *dev)
1540{
1541 drm_i915_private_t *dev_priv = dev->dev_private;
1542 u32 seqno = dev_priv->next_seqno;
1543
1544 /* reserve 0 for non-seqno */
1545 if (++dev_priv->next_seqno == 0)
1546 dev_priv->next_seqno = 1;
1547
1548 return seqno;
1549}
1550
1551u32
1552i915_gem_next_request_seqno(struct intel_ring_buffer *ring)
1553{
1554 if (ring->outstanding_lazy_request == 0)
1555 ring->outstanding_lazy_request = i915_gem_get_seqno(ring->dev);
1556
1557 return ring->outstanding_lazy_request;
1558}
1559
3cce469c 1560int
db53a302 1561i915_add_request(struct intel_ring_buffer *ring,
f787a5f5 1562 struct drm_file *file,
db53a302 1563 struct drm_i915_gem_request *request)
673a394b 1564{
db53a302 1565 drm_i915_private_t *dev_priv = ring->dev->dev_private;
673a394b 1566 uint32_t seqno;
a71d8d94 1567 u32 request_ring_position;
673a394b 1568 int was_empty;
3cce469c
CW		 1569 int ret;
1570
1571 BUG_ON(request == NULL);
53d227f2 1572 seqno = i915_gem_next_request_seqno(ring);
673a394b 1573
a71d8d94
CW		 1574 /* Record the position of the start of the request so that
1575 * should we detect the updated seqno part-way through the
1576 * GPU processing the request, we never over-estimate the
1577 * position of the head.
1578 */
1579 request_ring_position = intel_ring_get_tail(ring);
1580
3cce469c
CW		 1581 ret = ring->add_request(ring, &seqno);
1582 if (ret)
1583 return ret;
673a394b 1584
db53a302 1585 trace_i915_gem_request_add(ring, seqno);
673a394b
EA		 1586
1587 request->seqno = seqno;
852835f3 1588 request->ring = ring;
a71d8d94 1589 request->tail = request_ring_position;
673a394b 1590 request->emitted_jiffies = jiffies;
852835f3
ZN		 1591 was_empty = list_empty(&ring->request_list);
1592 list_add_tail(&request->list, &ring->request_list);
1593
db53a302
CW		 1594 if (file) {
1595 struct drm_i915_file_private *file_priv = file->driver_priv;
1596
1c25595f 1597 spin_lock(&file_priv->mm.lock);
f787a5f5 1598 request->file_priv = file_priv;
b962442e 1599 list_add_tail(&request->client_list,
f787a5f5 1600 &file_priv->mm.request_list);
1c25595f 1601 spin_unlock(&file_priv->mm.lock);
b962442e 1602 }
673a394b 1603
5391d0cf 1604 ring->outstanding_lazy_request = 0;
db53a302 1605
f65d9421 1606 if (!dev_priv->mm.suspended) {
3e0dc6b0
BW		 1607 if (i915_enable_hangcheck) {
1608 mod_timer(&dev_priv->hangcheck_timer,
1609 jiffies +
1610 msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD));
1611 }
f65d9421 1612 if (was_empty)
b3b079db
CW		 1613 queue_delayed_work(dev_priv->wq,
1614 &dev_priv->mm.retire_work, HZ);
f65d9421 1615 }
3cce469c 1616 return 0;
673a394b
EA		 1617}
1618
f787a5f5
CW		 1619static inline void
1620i915_gem_request_remove_from_client(struct drm_i915_gem_request *request)
673a394b 1621{
1c25595f 1622 struct drm_i915_file_private *file_priv = request->file_priv;
673a394b 1623
1c25595f
CW		 1624 if (!file_priv)
1625 return;
1c5d22f7 1626
1c25595f 1627 spin_lock(&file_priv->mm.lock);
09bfa517
HRK		 1628 if (request->file_priv) {
1629 list_del(&request->client_list);
1630 request->file_priv = NULL;
1631 }
1c25595f 1632 spin_unlock(&file_priv->mm.lock);
673a394b 1633}
673a394b 1634
dfaae392
CW		 1635static void i915_gem_reset_ring_lists(struct drm_i915_private *dev_priv,
1636 struct intel_ring_buffer *ring)
9375e446 1637{
dfaae392
CW		 1638 while (!list_empty(&ring->request_list)) {
1639 struct drm_i915_gem_request *request;
673a394b 1640
dfaae392
CW		 1641 request = list_first_entry(&ring->request_list,
1642 struct drm_i915_gem_request,
1643 list);
de151cf6 1644
dfaae392 1645 list_del(&request->list);
f787a5f5 1646 i915_gem_request_remove_from_client(request);
dfaae392
CW		 1647 kfree(request);
1648 }
673a394b 1649
dfaae392 1650 while (!list_empty(&ring->active_list)) {
05394f39 1651 struct drm_i915_gem_object *obj;
9375e446 1652
05394f39
CW		 1653 obj = list_first_entry(&ring->active_list,
1654 struct drm_i915_gem_object,
1655 ring_list);
9375e446 1656
05394f39
CW		 1657 obj->base.write_domain = 0;
1658 list_del_init(&obj->gpu_write_list);
1659 i915_gem_object_move_to_inactive(obj);
673a394b
EA		 1660 }
1661}
1662
312817a3
CW		 1663static void i915_gem_reset_fences(struct drm_device *dev)
1664{
1665 struct drm_i915_private *dev_priv = dev->dev_private;
1666 int i;
1667
4b9de737 1668 for (i = 0; i < dev_priv->num_fence_regs; i++) {
312817a3 1669 struct drm_i915_fence_reg *reg = &dev_priv->fence_regs[i];
7d2cb39c 1670
ada726c7 1671 i915_gem_write_fence(dev, i, NULL);
7d2cb39c 1672
ada726c7
CW		 1673 if (reg->obj)
1674 i915_gem_object_fence_lost(reg->obj);
7d2cb39c 1675
ada726c7
CW		 1676 reg->pin_count = 0;
1677 reg->obj = NULL;
1678 INIT_LIST_HEAD(&reg->lru_list);
312817a3 1679 }
ada726c7
CW		 1680
1681 INIT_LIST_HEAD(&dev_priv->mm.fence_list);
312817a3
CW		 1682}
1683
069efc1d 1684void i915_gem_reset(struct drm_device *dev)
673a394b 1685{
77f01230 1686 struct drm_i915_private *dev_priv = dev->dev_private;
05394f39 1687 struct drm_i915_gem_object *obj;
b4519513 1688 struct intel_ring_buffer *ring;
1ec14ad3 1689 int i;
673a394b 1690
b4519513
CW		 1691 for_each_ring(ring, dev_priv, i)
1692 i915_gem_reset_ring_lists(dev_priv, ring);
dfaae392
CW		 1693
1694 /* Remove anything from the flushing lists. The GPU cache is likely
1695 * to be lost on reset along with the data, so simply move the
1696 * lost bo to the inactive list.
1697 */
1698 while (!list_empty(&dev_priv->mm.flushing_list)) {
0206e353 1699 obj = list_first_entry(&dev_priv->mm.flushing_list,
05394f39
CW		 1700 struct drm_i915_gem_object,
1701 mm_list);
dfaae392 1702
05394f39
CW		 1703 obj->base.write_domain = 0;
1704 list_del_init(&obj->gpu_write_list);
1705 i915_gem_object_move_to_inactive(obj);
dfaae392
CW		 1706 }
1707
1708 /* Move everything out of the GPU domains to ensure we do any
1709 * necessary invalidation upon reuse.
1710 */
05394f39 1711 list_for_each_entry(obj,
77f01230 1712 &dev_priv->mm.inactive_list,
69dc4987 1713 mm_list)
77f01230 1714 {
05394f39 1715 obj->base.read_domains &= ~I915_GEM_GPU_DOMAINS;
77f01230 1716 }
069efc1d
CW		 1717
1718 /* The fence registers are invalidated so clear them out */
312817a3 1719 i915_gem_reset_fences(dev);
673a394b
EA		 1720}
1721
1722/**
1723 * This function clears the request list as sequence numbers are passed.
1724 */
a71d8d94 1725void
db53a302 1726i915_gem_retire_requests_ring(struct intel_ring_buffer *ring)
673a394b 1727{
673a394b 1728 uint32_t seqno;
1ec14ad3 1729 int i;
673a394b 1730
db53a302 1731 if (list_empty(&ring->request_list))
6c0594a3
KW		 1732 return;
1733
db53a302 1734 WARN_ON(i915_verify_lists(ring->dev));
673a394b 1735
78501eac 1736 seqno = ring->get_seqno(ring);
1ec14ad3 1737
076e2c0e 1738 for (i = 0; i < ARRAY_SIZE(ring->sync_seqno); i++)
1ec14ad3
CW		 1739 if (seqno >= ring->sync_seqno[i])
1740 ring->sync_seqno[i] = 0;
1741
852835f3 1742 while (!list_empty(&ring->request_list)) {
673a394b 1743 struct drm_i915_gem_request *request;
673a394b 1744
852835f3 1745 request = list_first_entry(&ring->request_list,
673a394b
EA		 1746 struct drm_i915_gem_request,
1747 list);
673a394b 1748
dfaae392 1749 if (!i915_seqno_passed(seqno, request->seqno))
b84d5f0c
CW		 1750 break;
1751
db53a302 1752 trace_i915_gem_request_retire(ring, request->seqno);
a71d8d94
CW		 1753 /* We know the GPU must have read the request to have
1754 * sent us the seqno + interrupt, so use the position
1755 * of tail of the request to update the last known position
1756 * of the GPU head.
1757 */
1758 ring->last_retired_head = request->tail;
b84d5f0c
CW		 1759
1760 list_del(&request->list);
f787a5f5 1761 i915_gem_request_remove_from_client(request);
b84d5f0c
CW		 1762 kfree(request);
1763 }
673a394b 1764
b84d5f0c
CW		 1765 /* Move any buffers on the active list that are no longer referenced
1766 * by the ringbuffer to the flushing/inactive lists as appropriate.
1767 */
1768 while (!list_empty(&ring->active_list)) {
05394f39 1769 struct drm_i915_gem_object *obj;
b84d5f0c 1770
0206e353 1771 obj = list_first_entry(&ring->active_list,
05394f39
CW		 1772 struct drm_i915_gem_object,
1773 ring_list);
673a394b 1774
05394f39 1775 if (!i915_seqno_passed(seqno, obj->last_rendering_seqno))
673a394b 1776 break;
b84d5f0c 1777
05394f39 1778 if (obj->base.write_domain != 0)
b84d5f0c
CW		 1779 i915_gem_object_move_to_flushing(obj);
1780 else
1781 i915_gem_object_move_to_inactive(obj);
673a394b 1782 }
9d34e5db 1783
db53a302
CW		 1784 if (unlikely(ring->trace_irq_seqno &&
1785 i915_seqno_passed(seqno, ring->trace_irq_seqno))) {
1ec14ad3 1786 ring->irq_put(ring);
db53a302 1787 ring->trace_irq_seqno = 0;
9d34e5db 1788 }
23bc5982 1789
db53a302 1790 WARN_ON(i915_verify_lists(ring->dev));
673a394b
EA		 1791}
1792
b09a1fec
CW		 1793void
1794i915_gem_retire_requests(struct drm_device *dev)
1795{
1796 drm_i915_private_t *dev_priv = dev->dev_private;
b4519513 1797 struct intel_ring_buffer *ring;
1ec14ad3 1798 int i;
b09a1fec 1799
b4519513
CW		 1800 for_each_ring(ring, dev_priv, i)
1801 i915_gem_retire_requests_ring(ring);
b09a1fec
CW		 1802}
1803
75ef9da2 1804static void
673a394b
EA		 1805i915_gem_retire_work_handler(struct work_struct *work)
1806{
1807 drm_i915_private_t *dev_priv;
1808 struct drm_device *dev;
b4519513 1809 struct intel_ring_buffer *ring;
0a58705b
CW		 1810 bool idle;
1811 int i;
673a394b
EA		 1812
1813 dev_priv = container_of(work, drm_i915_private_t,
1814 mm.retire_work.work);
1815 dev = dev_priv->dev;
1816
891b48cf
CW		 1817 /* Come back later if the device is busy... */
1818 if (!mutex_trylock(&dev->struct_mutex)) {
1819 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, HZ);
1820 return;
1821 }
1822
b09a1fec 1823 i915_gem_retire_requests(dev);
d1b851fc 1824
0a58705b
CW		 1825 /* Send a periodic flush down the ring so we don't hold onto GEM
1826 * objects indefinitely.
1827 */
1828 idle = true;
b4519513 1829 for_each_ring(ring, dev_priv, i) {
0a58705b
CW		 1830 if (!list_empty(&ring->gpu_write_list)) {
1831 struct drm_i915_gem_request *request;
1832 int ret;
1833
db53a302
CW		 1834 ret = i915_gem_flush_ring(ring,
1835 0, I915_GEM_GPU_DOMAINS);
0a58705b
CW		 1836 request = kzalloc(sizeof(*request), GFP_KERNEL);
1837 if (ret || request == NULL ||
db53a302 1838 i915_add_request(ring, NULL, request))
0a58705b
CW		 1839 kfree(request);
1840 }
1841
1842 idle &= list_empty(&ring->request_list);
1843 }
1844
1845 if (!dev_priv->mm.suspended && !idle)
9c9fe1f8 1846 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, HZ);
0a58705b 1847
673a394b
EA		 1848 mutex_unlock(&dev->struct_mutex);
1849}
1850
b4aca010
BW		 1851static int
1852i915_gem_check_wedge(struct drm_i915_private *dev_priv)
1853{
1854 BUG_ON(!mutex_is_locked(&dev_priv->dev->struct_mutex));
1855
1856 if (atomic_read(&dev_priv->mm.wedged)) {
1857 struct completion *x = &dev_priv->error_completion;
1858 bool recovery_complete;
1859 unsigned long flags;
1860
1861 /* Give the error handler a chance to run. */
1862 spin_lock_irqsave(&x->wait.lock, flags);
1863 recovery_complete = x->done > 0;
1864 spin_unlock_irqrestore(&x->wait.lock, flags);
1865
1866 return recovery_complete ? -EIO : -EAGAIN;
1867 }
1868
1869 return 0;
1870}
1871
1872/*
1873 * Compare seqno against outstanding lazy request. Emit a request if they are
1874 * equal.
1875 */
1876static int
1877i915_gem_check_olr(struct intel_ring_buffer *ring, u32 seqno)
1878{
1879 int ret = 0;
1880
1881 BUG_ON(!mutex_is_locked(&ring->dev->struct_mutex));
1882
1883 if (seqno == ring->outstanding_lazy_request) {
1884 struct drm_i915_gem_request *request;
1885
1886 request = kzalloc(sizeof(*request), GFP_KERNEL);
1887 if (request == NULL)
1888 return -ENOMEM;
1889
1890 ret = i915_add_request(ring, NULL, request);
1891 if (ret) {
1892 kfree(request);
1893 return ret;
1894 }
1895
1896 BUG_ON(seqno != request->seqno);
1897 }
1898
1899 return ret;
1900}
1901
5c81fe85
BW		 1902/**
1903 * __wait_seqno - wait until execution of seqno has finished
1904 * @ring: the ring expected to report seqno
1905 * @seqno: duh!
1906 * @interruptible: do an interruptible wait (normally yes)
1907 * @timeout: in - how long to wait (NULL forever); out - how much time remaining
1908 *
1909 * Returns 0 if the seqno was found within the alloted time. Else returns the
1910 * errno with remaining time filled in timeout argument.
1911 */
604dd3ec 1912static int __wait_seqno(struct intel_ring_buffer *ring, u32 seqno,
5c81fe85 1913 bool interruptible, struct timespec *timeout)
604dd3ec
BW		 1914{
1915 drm_i915_private_t *dev_priv = ring->dev->dev_private;
5c81fe85
BW		 1916 struct timespec before, now, wait_time={1,0};
1917 unsigned long timeout_jiffies;
1918 long end;
1919 bool wait_forever = true;
604dd3ec
BW		 1920
1921 if (i915_seqno_passed(ring->get_seqno(ring), seqno))
1922 return 0;
1923
1924 trace_i915_gem_request_wait_begin(ring, seqno);
5c81fe85
BW		 1925
1926 if (timeout != NULL) {
1927 wait_time = *timeout;
1928 wait_forever = false;
1929 }
1930
1931 timeout_jiffies = timespec_to_jiffies(&wait_time);
1932
604dd3ec
BW		 1933 if (WARN_ON(!ring->irq_get(ring)))
1934 return -ENODEV;
1935
5c81fe85
BW		 1936 /* Record current time in case interrupted by signal, or wedged * */
1937 getrawmonotonic(&before);
1938
604dd3ec
BW		 1939#define EXIT_COND \
1940 (i915_seqno_passed(ring->get_seqno(ring), seqno) || \
1941 atomic_read(&dev_priv->mm.wedged))
5c81fe85
BW		 1942 do {
1943 if (interruptible)
1944 end = wait_event_interruptible_timeout(ring->irq_queue,
1945 EXIT_COND,
1946 timeout_jiffies);
1947 else
1948 end = wait_event_timeout(ring->irq_queue, EXIT_COND,
1949 timeout_jiffies);
604dd3ec 1950
5c81fe85
BW		 1951 if (atomic_read(&dev_priv->mm.wedged))
1952 end = -EAGAIN;
1953 } while (end == 0 && wait_forever);
1954
1955 getrawmonotonic(&now);
604dd3ec
BW		 1956
1957 ring->irq_put(ring);
1958 trace_i915_gem_request_wait_end(ring, seqno);
1959#undef EXIT_COND
1960
5c81fe85
BW		 1961 if (timeout) {
1962 struct timespec sleep_time = timespec_sub(now, before);
1963 *timeout = timespec_sub(*timeout, sleep_time);
1964 }
1965
1966 switch (end) {
1967 case -EAGAIN: /* Wedged */
1968 case -ERESTARTSYS: /* Signal */
1969 return (int)end;
1970 case 0: /* Timeout */
1971 if (timeout)
1972 set_normalized_timespec(timeout, 0, 0);
1973 return -ETIME;
1974 default: /* Completed */
1975 WARN_ON(end < 0); /* We're not aware of other errors */
1976 return 0;
1977 }
604dd3ec
BW		 1978}
1979
db53a302
CW		 1980/**
1981 * Waits for a sequence number to be signaled, and cleans up the
1982 * request and object lists appropriately for that event.
1983 */
5a5a0c64 1984int
199b2bc2 1985i915_wait_seqno(struct intel_ring_buffer *ring, uint32_t seqno)
673a394b 1986{
db53a302 1987 drm_i915_private_t *dev_priv = ring->dev->dev_private;
673a394b
EA		 1988 int ret = 0;
1989
1990 BUG_ON(seqno == 0);
1991
b4aca010
BW		 1992 ret = i915_gem_check_wedge(dev_priv);
1993 if (ret)
1994 return ret;
3cce469c 1995
b4aca010
BW		 1996 ret = i915_gem_check_olr(ring, seqno);
1997 if (ret)
1998 return ret;
ffed1d09 1999
5c81fe85 2000 ret = __wait_seqno(ring, seqno, dev_priv->mm.interruptible, NULL);
673a394b 2001
673a394b
EA		 2002 return ret;
2003}
2004
673a394b
EA		 2005/**
2006 * Ensures that all rendering to the object has completed and the object is
2007 * safe to unbind from the GTT or access from the CPU.
2008 */
54cf91dc 2009int
ce453d81 2010i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj)
673a394b 2011{
673a394b
EA		 2012 int ret;
2013
e47c68e9
EA		 2014 /* This function only exists to support waiting for existing rendering,
2015 * not for emitting required flushes.
673a394b 2016 */
05394f39 2017 BUG_ON((obj->base.write_domain & I915_GEM_GPU_DOMAINS) != 0);
673a394b
EA		 2018
2019 /* If there is rendering queued on the buffer being evicted, wait for
2020 * it.
2021 */
05394f39 2022 if (obj->active) {
199b2bc2 2023 ret = i915_wait_seqno(obj->ring, obj->last_rendering_seqno);
2cf34d7b 2024 if (ret)
673a394b 2025 return ret;
b2da9fe5 2026 i915_gem_retire_requests_ring(obj->ring);
673a394b
EA		 2027 }
2028
2029 return 0;
2030}
2031
30dfebf3
DV		 2032/**
2033 * Ensures that an object will eventually get non-busy by flushing any required
2034 * write domains, emitting any outstanding lazy request and retiring and
2035 * completed requests.
2036 */
2037static int
2038i915_gem_object_flush_active(struct drm_i915_gem_object *obj)
2039{
2040 int ret;
2041
2042 if (obj->active) {
2043 ret = i915_gem_object_flush_gpu_write_domain(obj);
2044 if (ret)
2045 return ret;
2046
2047 ret = i915_gem_check_olr(obj->ring,
2048 obj->last_rendering_seqno);
2049 if (ret)
2050 return ret;
2051 i915_gem_retire_requests_ring(obj->ring);
2052 }
2053
2054 return 0;
2055}
2056
23ba4fd0
BW		 2057/**
2058 * i915_gem_wait_ioctl - implements DRM_IOCTL_I915_GEM_WAIT
2059 * @DRM_IOCTL_ARGS: standard ioctl arguments
2060 *
2061 * Returns 0 if successful, else an error is returned with the remaining time in
2062 * the timeout parameter.
2063 * -ETIME: object is still busy after timeout
2064 * -ERESTARTSYS: signal interrupted the wait
2065 * -ENONENT: object doesn't exist
2066 * Also possible, but rare:
2067 * -EAGAIN: GPU wedged
2068 * -ENOMEM: damn
2069 * -ENODEV: Internal IRQ fail
2070 * -E?: The add request failed
2071 *
2072 * The wait ioctl with a timeout of 0 reimplements the busy ioctl. With any
2073 * non-zero timeout parameter the wait ioctl will wait for the given number of
2074 * nanoseconds on an object becoming unbusy. Since the wait itself does so
2075 * without holding struct_mutex the object may become re-busied before this
2076 * function completes. A similar but shorter * race condition exists in the busy
2077 * ioctl
2078 */
2079int
2080i915_gem_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *file)
2081{
2082 struct drm_i915_gem_wait *args = data;
2083 struct drm_i915_gem_object *obj;
2084 struct intel_ring_buffer *ring = NULL;
eac1f14f 2085 struct timespec timeout_stack, *timeout = NULL;
23ba4fd0
BW		 2086 u32 seqno = 0;
2087 int ret = 0;
2088
eac1f14f
BW		 2089 if (args->timeout_ns >= 0) {
2090 timeout_stack = ns_to_timespec(args->timeout_ns);
2091 timeout = &timeout_stack;
2092 }
23ba4fd0
BW		 2093
2094 ret = i915_mutex_lock_interruptible(dev);
2095 if (ret)
2096 return ret;
2097
2098 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->bo_handle));
2099 if (&obj->base == NULL) {
2100 mutex_unlock(&dev->struct_mutex);
2101 return -ENOENT;
2102 }
2103
30dfebf3
DV		 2104 /* Need to make sure the object gets inactive eventually. */
2105 ret = i915_gem_object_flush_active(obj);
23ba4fd0
BW		 2106 if (ret)
2107 goto out;
2108
2109 if (obj->active) {
2110 seqno = obj->last_rendering_seqno;
2111 ring = obj->ring;
2112 }
2113
2114 if (seqno == 0)
2115 goto out;
2116
23ba4fd0
BW		 2117 /* Do this after OLR check to make sure we make forward progress polling
2118 * on this IOCTL with a 0 timeout (like busy ioctl)
2119 */
2120 if (!args->timeout_ns) {
2121 ret = -ETIME;
2122 goto out;
2123 }
2124
2125 drm_gem_object_unreference(&obj->base);
2126 mutex_unlock(&dev->struct_mutex);
2127
eac1f14f
BW		 2128 ret = __wait_seqno(ring, seqno, true, timeout);
2129 if (timeout) {
2130 WARN_ON(!timespec_valid(timeout));
2131 args->timeout_ns = timespec_to_ns(timeout);
2132 }
23ba4fd0
BW		 2133 return ret;
2134
2135out:
2136 drm_gem_object_unreference(&obj->base);
2137 mutex_unlock(&dev->struct_mutex);
2138 return ret;
2139}
2140
5816d648
BW		 2141/**
2142 * i915_gem_object_sync - sync an object to a ring.
2143 *
2144 * @obj: object which may be in use on another ring.
2145 * @to: ring we wish to use the object on. May be NULL.
2146 *
2147 * This code is meant to abstract object synchronization with the GPU.
2148 * Calling with NULL implies synchronizing the object with the CPU
2149 * rather than a particular GPU ring.
2150 *
2151 * Returns 0 if successful, else propagates up the lower layer error.
2152 */
2911a35b
BW		 2153int
2154i915_gem_object_sync(struct drm_i915_gem_object *obj,
2155 struct intel_ring_buffer *to)
2156{
2157 struct intel_ring_buffer *from = obj->ring;
2158 u32 seqno;
2159 int ret, idx;
2160
2161 if (from == NULL || to == from)
2162 return 0;
2163
5816d648 2164 if (to == NULL || !i915_semaphore_is_enabled(obj->base.dev))
2911a35b
BW		 2165 return i915_gem_object_wait_rendering(obj);
2166
2167 idx = intel_ring_sync_index(from, to);
2168
2169 seqno = obj->last_rendering_seqno;
2170 if (seqno <= from->sync_seqno[idx])
2171 return 0;
2172
b4aca010
BW		 2173 ret = i915_gem_check_olr(obj->ring, seqno);
2174 if (ret)
2175 return ret;
2911a35b 2176
1500f7ea 2177 ret = to->sync_to(to, from, seqno);
e3a5a225
BW		 2178 if (!ret)
2179 from->sync_seqno[idx] = seqno;
2911a35b 2180
e3a5a225 2181 return ret;
2911a35b
BW		 2182}
2183
b5ffc9bc
CW		 2184static void i915_gem_object_finish_gtt(struct drm_i915_gem_object *obj)
2185{
2186 u32 old_write_domain, old_read_domains;
2187
b5ffc9bc
CW		 2188 /* Act a barrier for all accesses through the GTT */
2189 mb();
2190
2191 /* Force a pagefault for domain tracking on next user access */
2192 i915_gem_release_mmap(obj);
2193
b97c3d9c
KP		 2194 if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0)
2195 return;
2196
b5ffc9bc
CW		 2197 old_read_domains = obj->base.read_domains;
2198 old_write_domain = obj->base.write_domain;
2199
2200 obj->base.read_domains &= ~I915_GEM_DOMAIN_GTT;
2201 obj->base.write_domain &= ~I915_GEM_DOMAIN_GTT;
2202
2203 trace_i915_gem_object_change_domain(obj,
2204 old_read_domains,
2205 old_write_domain);
2206}
2207
673a394b
EA		 2208/**
2209 * Unbinds an object from the GTT aperture.
2210 */
0f973f27 2211int
05394f39 2212i915_gem_object_unbind(struct drm_i915_gem_object *obj)
673a394b 2213{
7bddb01f 2214 drm_i915_private_t *dev_priv = obj->base.dev->dev_private;
673a394b
EA		 2215 int ret = 0;
2216
05394f39 2217 if (obj->gtt_space == NULL)
673a394b
EA		 2218 return 0;
2219
31d8d651
CW		 2220 if (obj->pin_count)
2221 return -EBUSY;
673a394b 2222
a8198eea 2223 ret = i915_gem_object_finish_gpu(obj);
1488fc08 2224 if (ret)
a8198eea
CW		 2225 return ret;
2226 /* Continue on if we fail due to EIO, the GPU is hung so we
2227 * should be safe and we need to cleanup or else we might
2228 * cause memory corruption through use-after-free.
2229 */
2230
b5ffc9bc 2231 i915_gem_object_finish_gtt(obj);
5323fd04 2232
673a394b
EA		 2233 /* Move the object to the CPU domain to ensure that
2234 * any possible CPU writes while it's not in the GTT
a8198eea 2235 * are flushed when we go to remap it.
673a394b 2236 */
a8198eea
CW		 2237 if (ret == 0)
2238 ret = i915_gem_object_set_to_cpu_domain(obj, 1);
8dc1775d 2239 if (ret == -ERESTARTSYS)
673a394b 2240 return ret;
812ed492 2241 if (ret) {
a8198eea
CW		 2242 /* In the event of a disaster, abandon all caches and
2243 * hope for the best.
2244 */
812ed492 2245 i915_gem_clflush_object(obj);
05394f39 2246 obj->base.read_domains = obj->base.write_domain = I915_GEM_DOMAIN_CPU;
812ed492 2247 }
673a394b 2248
96b47b65 2249 /* release the fence reg _after_ flushing */
d9e86c0e 2250 ret = i915_gem_object_put_fence(obj);
1488fc08 2251 if (ret)
d9e86c0e 2252 return ret;
96b47b65 2253
db53a302
CW		 2254 trace_i915_gem_object_unbind(obj);
2255
74898d7e
DV		 2256 if (obj->has_global_gtt_mapping)
2257 i915_gem_gtt_unbind_object(obj);
7bddb01f
DV		 2258 if (obj->has_aliasing_ppgtt_mapping) {
2259 i915_ppgtt_unbind_object(dev_priv->mm.aliasing_ppgtt, obj);
2260 obj->has_aliasing_ppgtt_mapping = 0;
2261 }
74163907 2262 i915_gem_gtt_finish_object(obj);
7bddb01f 2263
e5281ccd 2264 i915_gem_object_put_pages_gtt(obj);
673a394b 2265
6299f992 2266 list_del_init(&obj->gtt_list);
05394f39 2267 list_del_init(&obj->mm_list);
75e9e915 2268 /* Avoid an unnecessary call to unbind on rebind. */
05394f39 2269 obj->map_and_fenceable = true;
673a394b 2270
05394f39
CW		 2271 drm_mm_put_block(obj->gtt_space);
2272 obj->gtt_space = NULL;
2273 obj->gtt_offset = 0;
673a394b 2274
05394f39 2275 if (i915_gem_object_is_purgeable(obj))
963b4836
CW		 2276 i915_gem_object_truncate(obj);
2277
8dc1775d 2278 return ret;
673a394b
EA		 2279}
2280
88241785 2281int
db53a302 2282i915_gem_flush_ring(struct intel_ring_buffer *ring,
54cf91dc
CW		 2283 uint32_t invalidate_domains,
2284 uint32_t flush_domains)
2285{
88241785
CW		 2286 int ret;
2287
36d527de
CW		 2288 if (((invalidate_domains | flush_domains) & I915_GEM_GPU_DOMAINS) == 0)
2289 return 0;
2290
db53a302
CW		 2291 trace_i915_gem_ring_flush(ring, invalidate_domains, flush_domains);
2292
88241785
CW		 2293 ret = ring->flush(ring, invalidate_domains, flush_domains);
2294 if (ret)
2295 return ret;
2296
36d527de
CW		 2297 if (flush_domains & I915_GEM_GPU_DOMAINS)
2298 i915_gem_process_flushing_list(ring, flush_domains);
2299
88241785 2300 return 0;
54cf91dc
CW		 2301}
2302
b2da9fe5 2303static int i915_ring_idle(struct intel_ring_buffer *ring)
a56ba56c 2304{
88241785
CW		 2305 int ret;
2306
395b70be 2307 if (list_empty(&ring->gpu_write_list) && list_empty(&ring->active_list))
64193406
CW		 2308 return 0;
2309
88241785 2310 if (!list_empty(&ring->gpu_write_list)) {
db53a302 2311 ret = i915_gem_flush_ring(ring,
0ac74c6b 2312 I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);
88241785
CW		 2313 if (ret)
2314 return ret;
2315 }
2316
199b2bc2 2317 return i915_wait_seqno(ring, i915_gem_next_request_seqno(ring));
a56ba56c
CW		 2318}
2319
b2da9fe5 2320int i915_gpu_idle(struct drm_device *dev)
4df2faf4
DV		 2321{
2322 drm_i915_private_t *dev_priv = dev->dev_private;
b4519513 2323 struct intel_ring_buffer *ring;
1ec14ad3 2324 int ret, i;
4df2faf4 2325
4df2faf4 2326 /* Flush everything onto the inactive list. */
b4519513
CW		 2327 for_each_ring(ring, dev_priv, i) {
2328 ret = i915_ring_idle(ring);
1ec14ad3
CW		 2329 if (ret)
2330 return ret;
b4519513
CW		 2331
2332 /* Is the device fubar? */
2333 if (WARN_ON(!list_empty(&ring->gpu_write_list)))
2334 return -EBUSY;
1ec14ad3 2335 }
4df2faf4 2336
8a1a49f9 2337 return 0;
4df2faf4
DV		 2338}
2339
9ce079e4
CW		 2340static void sandybridge_write_fence_reg(struct drm_device *dev, int reg,
2341 struct drm_i915_gem_object *obj)
4e901fdc 2342{
4e901fdc 2343 drm_i915_private_t *dev_priv = dev->dev_private;
4e901fdc
EA		 2344 uint64_t val;
2345
9ce079e4
CW		 2346 if (obj) {
2347 u32 size = obj->gtt_space->size;
4e901fdc 2348
9ce079e4
CW		 2349 val = (uint64_t)((obj->gtt_offset + size - 4096) &
2350 0xfffff000) << 32;
2351 val |= obj->gtt_offset & 0xfffff000;
2352 val |= (uint64_t)((obj->stride / 128) - 1) <<
2353 SANDYBRIDGE_FENCE_PITCH_SHIFT;
4e901fdc 2354
9ce079e4
CW		 2355 if (obj->tiling_mode == I915_TILING_Y)
2356 val |= 1 << I965_FENCE_TILING_Y_SHIFT;
2357 val |= I965_FENCE_REG_VALID;
2358 } else
2359 val = 0;
c6642782 2360
9ce079e4
CW		 2361 I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + reg * 8, val);
2362 POSTING_READ(FENCE_REG_SANDYBRIDGE_0 + reg * 8);
4e901fdc
EA		 2363}
2364
9ce079e4
CW		 2365static void i965_write_fence_reg(struct drm_device *dev, int reg,
2366 struct drm_i915_gem_object *obj)
de151cf6 2367{
de151cf6 2368 drm_i915_private_t *dev_priv = dev->dev_private;
de151cf6
JB		 2369 uint64_t val;
2370
9ce079e4
CW		 2371 if (obj) {
2372 u32 size = obj->gtt_space->size;
de151cf6 2373
9ce079e4
CW		 2374 val = (uint64_t)((obj->gtt_offset + size - 4096) &
2375 0xfffff000) << 32;
2376 val |= obj->gtt_offset & 0xfffff000;
2377 val |= ((obj->stride / 128) - 1) << I965_FENCE_PITCH_SHIFT;
2378 if (obj->tiling_mode == I915_TILING_Y)
2379 val |= 1 << I965_FENCE_TILING_Y_SHIFT;
2380 val |= I965_FENCE_REG_VALID;
2381 } else
2382 val = 0;
c6642782 2383
9ce079e4
CW		 2384 I915_WRITE64(FENCE_REG_965_0 + reg * 8, val);
2385 POSTING_READ(FENCE_REG_965_0 + reg * 8);
de151cf6
JB		 2386}
2387
9ce079e4
CW		 2388static void i915_write_fence_reg(struct drm_device *dev, int reg,
2389 struct drm_i915_gem_object *obj)
de151cf6 2390{
de151cf6 2391 drm_i915_private_t *dev_priv = dev->dev_private;
9ce079e4 2392 u32 val;
de151cf6 2393
9ce079e4
CW		 2394 if (obj) {
2395 u32 size = obj->gtt_space->size;
2396 int pitch_val;
2397 int tile_width;
c6642782 2398
9ce079e4
CW		 2399 WARN((obj->gtt_offset & ~I915_FENCE_START_MASK) ||
2400 (size & -size) != size ||
2401 (obj->gtt_offset & (size - 1)),
2402 "object 0x%08x [fenceable? %d] not 1M or pot-size (0x%08x) aligned\n",
2403 obj->gtt_offset, obj->map_and_fenceable, size);
c6642782 2404
9ce079e4
CW		 2405 if (obj->tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev))
2406 tile_width = 128;
2407 else
2408 tile_width = 512;
2409
2410 /* Note: pitch better be a power of two tile widths */
2411 pitch_val = obj->stride / tile_width;
2412 pitch_val = ffs(pitch_val) - 1;
2413
2414 val = obj->gtt_offset;
2415 if (obj->tiling_mode == I915_TILING_Y)
2416 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
2417 val |= I915_FENCE_SIZE_BITS(size);
2418 val |= pitch_val << I830_FENCE_PITCH_SHIFT;
2419 val |= I830_FENCE_REG_VALID;
2420 } else
2421 val = 0;
2422
2423 if (reg < 8)
2424 reg = FENCE_REG_830_0 + reg * 4;
2425 else
2426 reg = FENCE_REG_945_8 + (reg - 8) * 4;
2427
2428 I915_WRITE(reg, val);
2429 POSTING_READ(reg);
de151cf6
JB		 2430}
2431
9ce079e4
CW		 2432static void i830_write_fence_reg(struct drm_device *dev, int reg,
2433 struct drm_i915_gem_object *obj)
de151cf6 2434{
de151cf6 2435 drm_i915_private_t *dev_priv = dev->dev_private;
de151cf6 2436 uint32_t val;
de151cf6 2437
9ce079e4
CW		 2438 if (obj) {
2439 u32 size = obj->gtt_space->size;
2440 uint32_t pitch_val;
de151cf6 2441
9ce079e4
CW		 2442 WARN((obj->gtt_offset & ~I830_FENCE_START_MASK) ||
2443 (size & -size) != size ||
2444 (obj->gtt_offset & (size - 1)),
2445 "object 0x%08x not 512K or pot-size 0x%08x aligned\n",
2446 obj->gtt_offset, size);
e76a16de 2447
9ce079e4
CW		 2448 pitch_val = obj->stride / 128;
2449 pitch_val = ffs(pitch_val) - 1;
de151cf6 2450
9ce079e4
CW		 2451 val = obj->gtt_offset;
2452 if (obj->tiling_mode == I915_TILING_Y)
2453 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
2454 val |= I830_FENCE_SIZE_BITS(size);
2455 val |= pitch_val << I830_FENCE_PITCH_SHIFT;
2456 val |= I830_FENCE_REG_VALID;
2457 } else
2458 val = 0;
c6642782 2459
9ce079e4
CW		 2460 I915_WRITE(FENCE_REG_830_0 + reg * 4, val);
2461 POSTING_READ(FENCE_REG_830_0 + reg * 4);
2462}
2463
2464static void i915_gem_write_fence(struct drm_device *dev, int reg,
2465 struct drm_i915_gem_object *obj)
2466{
2467 switch (INTEL_INFO(dev)->gen) {
2468 case 7:
2469 case 6: sandybridge_write_fence_reg(dev, reg, obj); break;
2470 case 5:
2471 case 4: i965_write_fence_reg(dev, reg, obj); break;
2472 case 3: i915_write_fence_reg(dev, reg, obj); break;
2473 case 2: i830_write_fence_reg(dev, reg, obj); break;
2474 default: break;
2475 }
de151cf6
JB		 2476}
2477
61050808
CW		 2478static inline int fence_number(struct drm_i915_private *dev_priv,
2479 struct drm_i915_fence_reg *fence)
2480{
2481 return fence - dev_priv->fence_regs;
2482}
2483
2484static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj,
2485 struct drm_i915_fence_reg *fence,
2486 bool enable)
2487{
2488 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2489 int reg = fence_number(dev_priv, fence);
2490
2491 i915_gem_write_fence(obj->base.dev, reg, enable ? obj : NULL);
2492
2493 if (enable) {
2494 obj->fence_reg = reg;
2495 fence->obj = obj;
2496 list_move_tail(&fence->lru_list, &dev_priv->mm.fence_list);
2497 } else {
2498 obj->fence_reg = I915_FENCE_REG_NONE;
2499 fence->obj = NULL;
2500 list_del_init(&fence->lru_list);
2501 }
2502}
2503
d9e86c0e 2504static int
a360bb1a 2505i915_gem_object_flush_fence(struct drm_i915_gem_object *obj)
d9e86c0e
CW		 2506{
2507 int ret;
2508
2509 if (obj->fenced_gpu_access) {
88241785 2510 if (obj->base.write_domain & I915_GEM_GPU_DOMAINS) {
1c293ea3 2511 ret = i915_gem_flush_ring(obj->ring,
88241785
CW		 2512 0, obj->base.write_domain);
2513 if (ret)
2514 return ret;
2515 }
d9e86c0e
CW		 2516
2517 obj->fenced_gpu_access = false;
2518 }
2519
1c293ea3 2520 if (obj->last_fenced_seqno) {
199b2bc2 2521 ret = i915_wait_seqno(obj->ring, obj->last_fenced_seqno);
18991845
CW		 2522 if (ret)
2523 return ret;
d9e86c0e
CW		 2524
2525 obj->last_fenced_seqno = 0;
d9e86c0e
CW		 2526 }
2527
63256ec5
CW		 2528 /* Ensure that all CPU reads are completed before installing a fence
2529 * and all writes before removing the fence.
2530 */
2531 if (obj->base.read_domains & I915_GEM_DOMAIN_GTT)
2532 mb();
2533
d9e86c0e
CW		 2534 return 0;
2535}
2536
2537int
2538i915_gem_object_put_fence(struct drm_i915_gem_object *obj)
2539{
61050808 2540 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
d9e86c0e
CW		 2541 int ret;
2542
a360bb1a 2543 ret = i915_gem_object_flush_fence(obj);
d9e86c0e
CW		 2544 if (ret)
2545 return ret;
2546
61050808
CW		 2547 if (obj->fence_reg == I915_FENCE_REG_NONE)
2548 return 0;
d9e86c0e 2549
61050808
CW		 2550 i915_gem_object_update_fence(obj,
2551 &dev_priv->fence_regs[obj->fence_reg],
2552 false);
2553 i915_gem_object_fence_lost(obj);
d9e86c0e
CW		 2554
2555 return 0;
2556}
2557
2558static struct drm_i915_fence_reg *
a360bb1a 2559i915_find_fence_reg(struct drm_device *dev)
ae3db24a 2560{
ae3db24a 2561 struct drm_i915_private *dev_priv = dev->dev_private;
8fe301ad 2562 struct drm_i915_fence_reg *reg, *avail;
d9e86c0e 2563 int i;
ae3db24a
DV		 2564
2565 /* First try to find a free reg */
d9e86c0e 2566 avail = NULL;
ae3db24a
DV		 2567 for (i = dev_priv->fence_reg_start; i < dev_priv->num_fence_regs; i++) {
2568 reg = &dev_priv->fence_regs[i];
2569 if (!reg->obj)
d9e86c0e 2570 return reg;
ae3db24a 2571
1690e1eb 2572 if (!reg->pin_count)
d9e86c0e 2573 avail = reg;
ae3db24a
DV		 2574 }
2575
d9e86c0e
CW		 2576 if (avail == NULL)
2577 return NULL;
ae3db24a
DV		 2578
2579 /* None available, try to steal one or wait for a user to finish */
d9e86c0e 2580 list_for_each_entry(reg, &dev_priv->mm.fence_list, lru_list) {
1690e1eb 2581 if (reg->pin_count)
ae3db24a
DV		 2582 continue;
2583
8fe301ad 2584 return reg;
ae3db24a
DV		 2585 }
2586
8fe301ad 2587 return NULL;
ae3db24a
DV		 2588}
2589
de151cf6 2590/**
9a5a53b3 2591 * i915_gem_object_get_fence - set up fencing for an object
de151cf6
JB		 2592 * @obj: object to map through a fence reg
2593 *
2594 * When mapping objects through the GTT, userspace wants to be able to write
2595 * to them without having to worry about swizzling if the object is tiled.
de151cf6
JB		 2596 * This function walks the fence regs looking for a free one for @obj,
2597 * stealing one if it can't find any.
2598 *
2599 * It then sets up the reg based on the object's properties: address, pitch
2600 * and tiling format.
9a5a53b3
CW		 2601 *
2602 * For an untiled surface, this removes any existing fence.
de151cf6 2603 */
8c4b8c3f 2604int
06d98131 2605i915_gem_object_get_fence(struct drm_i915_gem_object *obj)
de151cf6 2606{
05394f39 2607 struct drm_device *dev = obj->base.dev;
79e53945 2608 struct drm_i915_private *dev_priv = dev->dev_private;
14415745 2609 bool enable = obj->tiling_mode != I915_TILING_NONE;
d9e86c0e 2610 struct drm_i915_fence_reg *reg;
ae3db24a 2611 int ret;
de151cf6 2612
14415745
CW		 2613 /* Have we updated the tiling parameters upon the object and so
2614 * will need to serialise the write to the associated fence register?
2615 */
5d82e3e6 2616 if (obj->fence_dirty) {
14415745
CW		 2617 ret = i915_gem_object_flush_fence(obj);
2618 if (ret)
2619 return ret;
2620 }
9a5a53b3 2621
d9e86c0e 2622 /* Just update our place in the LRU if our fence is getting reused. */
05394f39
CW		 2623 if (obj->fence_reg != I915_FENCE_REG_NONE) {
2624 reg = &dev_priv->fence_regs[obj->fence_reg];
5d82e3e6 2625 if (!obj->fence_dirty) {
14415745
CW		 2626 list_move_tail(&reg->lru_list,
2627 &dev_priv->mm.fence_list);
2628 return 0;
2629 }
2630 } else if (enable) {
2631 reg = i915_find_fence_reg(dev);
2632 if (reg == NULL)
2633 return -EDEADLK;
d9e86c0e 2634
14415745
CW		 2635 if (reg->obj) {
2636 struct drm_i915_gem_object *old = reg->obj;
2637
2638 ret = i915_gem_object_flush_fence(old);
29c5a587
CW		 2639 if (ret)
2640 return ret;
2641
14415745 2642 i915_gem_object_fence_lost(old);
29c5a587 2643 }
14415745 2644 } else
a09ba7fa 2645 return 0;
a09ba7fa 2646
14415745 2647 i915_gem_object_update_fence(obj, reg, enable);
5d82e3e6 2648 obj->fence_dirty = false;
14415745 2649
9ce079e4 2650 return 0;
de151cf6
JB		 2651}
2652
673a394b
EA		 2653/**
2654 * Finds free space in the GTT aperture and binds the object there.
2655 */
2656static int
05394f39 2657i915_gem_object_bind_to_gtt(struct drm_i915_gem_object *obj,
920afa77 2658 unsigned alignment,
75e9e915 2659 bool map_and_fenceable)
673a394b 2660{
05394f39 2661 struct drm_device *dev = obj->base.dev;
673a394b 2662 drm_i915_private_t *dev_priv = dev->dev_private;
673a394b 2663 struct drm_mm_node *free_space;
a00b10c3 2664 gfp_t gfpmask = __GFP_NORETRY | __GFP_NOWARN;
5e783301 2665 u32 size, fence_size, fence_alignment, unfenced_alignment;
75e9e915 2666 bool mappable, fenceable;
07f73f69 2667 int ret;
673a394b 2668
05394f39 2669 if (obj->madv != I915_MADV_WILLNEED) {
3ef94daa
CW		 2670 DRM_ERROR("Attempting to bind a purgeable object\n");
2671 return -EINVAL;
2672 }
2673
e28f8711
CW		 2674 fence_size = i915_gem_get_gtt_size(dev,
2675 obj->base.size,
2676 obj->tiling_mode);
2677 fence_alignment = i915_gem_get_gtt_alignment(dev,
2678 obj->base.size,
2679 obj->tiling_mode);
2680 unfenced_alignment =
2681 i915_gem_get_unfenced_gtt_alignment(dev,
2682 obj->base.size,
2683 obj->tiling_mode);
a00b10c3 2684
673a394b 2685 if (alignment == 0)
5e783301
DV		 2686 alignment = map_and_fenceable ? fence_alignment :
2687 unfenced_alignment;
75e9e915 2688 if (map_and_fenceable && alignment & (fence_alignment - 1)) {
673a394b
EA		 2689 DRM_ERROR("Invalid object alignment requested %u\n", alignment);
2690 return -EINVAL;
2691 }
2692
05394f39 2693 size = map_and_fenceable ? fence_size : obj->base.size;
a00b10c3 2694
654fc607
CW		 2695 /* If the object is bigger than the entire aperture, reject it early
2696 * before evicting everything in a vain attempt to find space.
2697 */
05394f39 2698 if (obj->base.size >
75e9e915 2699 (map_and_fenceable ? dev_priv->mm.gtt_mappable_end : dev_priv->mm.gtt_total)) {
654fc607
CW		 2700 DRM_ERROR("Attempting to bind an object larger than the aperture\n");
2701 return -E2BIG;
2702 }
2703
673a394b 2704 search_free:
75e9e915 2705 if (map_and_fenceable)
920afa77
DV		 2706 free_space =
2707 drm_mm_search_free_in_range(&dev_priv->mm.gtt_space,
a00b10c3 2708 size, alignment, 0,
920afa77
DV		 2709 dev_priv->mm.gtt_mappable_end,
2710 0);
2711 else
2712 free_space = drm_mm_search_free(&dev_priv->mm.gtt_space,
a00b10c3 2713 size, alignment, 0);
920afa77
DV		 2714
2715 if (free_space != NULL) {
75e9e915 2716 if (map_and_fenceable)
05394f39 2717 obj->gtt_space =
920afa77 2718 drm_mm_get_block_range_generic(free_space,
a00b10c3 2719 size, alignment, 0,
920afa77
DV		 2720 dev_priv->mm.gtt_mappable_end,
2721 0);
2722 else
05394f39 2723 obj->gtt_space =
a00b10c3 2724 drm_mm_get_block(free_space, size, alignment);
920afa77 2725 }
05394f39 2726 if (obj->gtt_space == NULL) {
673a394b
EA		 2727 /* If the gtt is empty and we're still having trouble
2728 * fitting our object in, we're out of memory.
2729 */
75e9e915
DV		 2730 ret = i915_gem_evict_something(dev, size, alignment,
2731 map_and_fenceable);
9731129c 2732 if (ret)
673a394b 2733 return ret;
9731129c 2734
673a394b
EA		 2735 goto search_free;
2736 }
2737
e5281ccd 2738 ret = i915_gem_object_get_pages_gtt(obj, gfpmask);
673a394b 2739 if (ret) {
05394f39
CW		 2740 drm_mm_put_block(obj->gtt_space);
2741 obj->gtt_space = NULL;
07f73f69
CW		 2742
2743 if (ret == -ENOMEM) {
809b6334
CW		 2744 /* first try to reclaim some memory by clearing the GTT */
2745 ret = i915_gem_evict_everything(dev, false);
07f73f69 2746 if (ret) {
07f73f69 2747 /* now try to shrink everyone else */
4bdadb97
CW		 2748 if (gfpmask) {
2749 gfpmask = 0;
2750 goto search_free;
07f73f69
CW		 2751 }
2752
809b6334 2753 return -ENOMEM;
07f73f69
CW		 2754 }
2755
2756 goto search_free;
2757 }
2758
673a394b
EA		 2759 return ret;
2760 }
2761
74163907 2762 ret = i915_gem_gtt_prepare_object(obj);
7c2e6fdf 2763 if (ret) {
e5281ccd 2764 i915_gem_object_put_pages_gtt(obj);
05394f39
CW		 2765 drm_mm_put_block(obj->gtt_space);
2766 obj->gtt_space = NULL;
07f73f69 2767
809b6334 2768 if (i915_gem_evict_everything(dev, false))
07f73f69 2769 return ret;
07f73f69
CW		 2770
2771 goto search_free;
673a394b 2772 }
673a394b 2773
0ebb9829
DV		 2774 if (!dev_priv->mm.aliasing_ppgtt)
2775 i915_gem_gtt_bind_object(obj, obj->cache_level);
673a394b 2776
6299f992 2777 list_add_tail(&obj->gtt_list, &dev_priv->mm.gtt_list);
05394f39 2778 list_add_tail(&obj->mm_list, &dev_priv->mm.inactive_list);
bf1a1092 2779
673a394b
EA		 2780 /* Assert that the object is not currently in any GPU domain. As it
2781 * wasn't in the GTT, there shouldn't be any way it could have been in
2782 * a GPU cache
2783 */
05394f39
CW		 2784 BUG_ON(obj->base.read_domains & I915_GEM_GPU_DOMAINS);
2785 BUG_ON(obj->base.write_domain & I915_GEM_GPU_DOMAINS);
673a394b 2786
6299f992 2787 obj->gtt_offset = obj->gtt_space->start;
1c5d22f7 2788
75e9e915 2789 fenceable =
05394f39 2790 obj->gtt_space->size == fence_size &&
0206e353 2791 (obj->gtt_space->start & (fence_alignment - 1)) == 0;
a00b10c3 2792
75e9e915 2793 mappable =
05394f39 2794 obj->gtt_offset + obj->base.size <= dev_priv->mm.gtt_mappable_end;
a00b10c3 2795
05394f39 2796 obj->map_and_fenceable = mappable && fenceable;
75e9e915 2797
db53a302 2798 trace_i915_gem_object_bind(obj, map_and_fenceable);
673a394b
EA		 2799 return 0;
2800}
2801
2802void
05394f39 2803i915_gem_clflush_object(struct drm_i915_gem_object *obj)
673a394b 2804{
673a394b
EA		 2805 /* If we don't have a page list set up, then we're not pinned
2806 * to GPU, and we can ignore the cache flush because it'll happen
2807 * again at bind time.
2808 */
05394f39 2809 if (obj->pages == NULL)
673a394b
EA		 2810 return;
2811
9c23f7fc
CW		 2812 /* If the GPU is snooping the contents of the CPU cache,
2813 * we do not need to manually clear the CPU cache lines. However,
2814 * the caches are only snooped when the render cache is
2815 * flushed/invalidated. As we always have to emit invalidations
2816 * and flushes when moving into and out of the RENDER domain, correct
2817 * snooping behaviour occurs naturally as the result of our domain
2818 * tracking.
2819 */
2820 if (obj->cache_level != I915_CACHE_NONE)
2821 return;
2822
1c5d22f7 2823 trace_i915_gem_object_clflush(obj);
cfa16a0d 2824
05394f39 2825 drm_clflush_pages(obj->pages, obj->base.size / PAGE_SIZE);
673a394b
EA		 2826}
2827
e47c68e9 2828/** Flushes any GPU write domain for the object if it's dirty. */
88241785 2829static int
3619df03 2830i915_gem_object_flush_gpu_write_domain(struct drm_i915_gem_object *obj)
e47c68e9 2831{
05394f39 2832 if ((obj->base.write_domain & I915_GEM_GPU_DOMAINS) == 0)
88241785 2833 return 0;
e47c68e9
EA		 2834
2835 /* Queue the GPU write cache flushing we need. */
db53a302 2836 return i915_gem_flush_ring(obj->ring, 0, obj->base.write_domain);
e47c68e9
EA		 2837}
2838
2839/** Flushes the GTT write domain for the object if it's dirty. */
2840static void
05394f39 2841i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj)
e47c68e9 2842{
1c5d22f7
CW		 2843 uint32_t old_write_domain;
2844
05394f39 2845 if (obj->base.write_domain != I915_GEM_DOMAIN_GTT)
e47c68e9
EA		 2846 return;
2847
63256ec5 2848 /* No actual flushing is required for the GTT write domain. Writes
e47c68e9
EA		 2849 * to it immediately go to main memory as far as we know, so there's
2850 * no chipset flush. It also doesn't land in render cache.
63256ec5
CW		 2851 *
2852 * However, we do have to enforce the order so that all writes through
2853 * the GTT land before any writes to the device, such as updates to
2854 * the GATT itself.
e47c68e9 2855 */
63256ec5
CW		 2856 wmb();
2857
05394f39
CW		 2858 old_write_domain = obj->base.write_domain;
2859 obj->base.write_domain = 0;
1c5d22f7
CW		 2860
2861 trace_i915_gem_object_change_domain(obj,
05394f39 2862 obj->base.read_domains,
1c5d22f7 2863 old_write_domain);
e47c68e9
EA		 2864}
2865
2866/** Flushes the CPU write domain for the object if it's dirty. */
2867static void
05394f39 2868i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj)
e47c68e9 2869{
1c5d22f7 2870 uint32_t old_write_domain;
e47c68e9 2871
05394f39 2872 if (obj->base.write_domain != I915_GEM_DOMAIN_CPU)
e47c68e9
EA		 2873 return;
2874
2875 i915_gem_clflush_object(obj);
40ce6575 2876 intel_gtt_chipset_flush();
05394f39
CW		 2877 old_write_domain = obj->base.write_domain;
2878 obj->base.write_domain = 0;
1c5d22f7
CW		 2879
2880 trace_i915_gem_object_change_domain(obj,
05394f39 2881 obj->base.read_domains,
1c5d22f7 2882 old_write_domain);
e47c68e9
EA		 2883}
2884
2ef7eeaa
EA		 2885/**
2886 * Moves a single object to the GTT read, and possibly write domain.
2887 *
2888 * This function returns when the move is complete, including waiting on
2889 * flushes to occur.
2890 */
79e53945 2891int
2021746e 2892i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write)
2ef7eeaa 2893{
8325a09d 2894 drm_i915_private_t *dev_priv = obj->base.dev->dev_private;
1c5d22f7 2895 uint32_t old_write_domain, old_read_domains;
e47c68e9 2896 int ret;
2ef7eeaa 2897
02354392 2898 /* Not valid to be called on unbound objects. */
05394f39 2899 if (obj->gtt_space == NULL)
02354392
EA		 2900 return -EINVAL;
2901
8d7e3de1
CW		 2902 if (obj->base.write_domain == I915_GEM_DOMAIN_GTT)
2903 return 0;
2904
88241785
CW		 2905 ret = i915_gem_object_flush_gpu_write_domain(obj);
2906 if (ret)
2907 return ret;
2908
87ca9c8a 2909 if (obj->pending_gpu_write || write) {
ce453d81 2910 ret = i915_gem_object_wait_rendering(obj);
87ca9c8a
CW		 2911 if (ret)
2912 return ret;
2913 }
2dafb1e0 2914
7213342d 2915 i915_gem_object_flush_cpu_write_domain(obj);
1c5d22f7 2916
05394f39
CW		 2917 old_write_domain = obj->base.write_domain;
2918 old_read_domains = obj->base.read_domains;
1c5d22f7 2919
e47c68e9
EA		 2920 /* It should now be out of any other write domains, and we can update
2921 * the domain values for our changes.
2922 */
05394f39
CW		 2923 BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_GTT) != 0);
2924 obj->base.read_domains |= I915_GEM_DOMAIN_GTT;
e47c68e9 2925 if (write) {
05394f39
CW		 2926 obj->base.read_domains = I915_GEM_DOMAIN_GTT;
2927 obj->base.write_domain = I915_GEM_DOMAIN_GTT;
2928 obj->dirty = 1;
2ef7eeaa
EA		 2929 }
2930
1c5d22f7
CW		 2931 trace_i915_gem_object_change_domain(obj,
2932 old_read_domains,
2933 old_write_domain);
2934
8325a09d
CW		 2935 /* And bump the LRU for this access */
2936 if (i915_gem_object_is_inactive(obj))
2937 list_move_tail(&obj->mm_list, &dev_priv->mm.inactive_list);
2938
e47c68e9
EA		 2939 return 0;
2940}
2941
e4ffd173
CW		 2942int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
2943 enum i915_cache_level cache_level)
2944{
7bddb01f
DV		 2945 struct drm_device *dev = obj->base.dev;
2946 drm_i915_private_t *dev_priv = dev->dev_private;
e4ffd173
CW		 2947 int ret;
2948
2949 if (obj->cache_level == cache_level)
2950 return 0;
2951
2952 if (obj->pin_count) {
2953 DRM_DEBUG("can not change the cache level of pinned objects\n");
2954 return -EBUSY;
2955 }
2956
2957 if (obj->gtt_space) {
2958 ret = i915_gem_object_finish_gpu(obj);
2959 if (ret)
2960 return ret;
2961
2962 i915_gem_object_finish_gtt(obj);
2963
2964 /* Before SandyBridge, you could not use tiling or fence
2965 * registers with snooped memory, so relinquish any fences
2966 * currently pointing to our region in the aperture.
2967 */
2968 if (INTEL_INFO(obj->base.dev)->gen < 6) {
2969 ret = i915_gem_object_put_fence(obj);
2970 if (ret)
2971 return ret;
2972 }
2973
74898d7e
DV		 2974 if (obj->has_global_gtt_mapping)
2975 i915_gem_gtt_bind_object(obj, cache_level);
7bddb01f
DV		 2976 if (obj->has_aliasing_ppgtt_mapping)
2977 i915_ppgtt_bind_object(dev_priv->mm.aliasing_ppgtt,
2978 obj, cache_level);
e4ffd173
CW		 2979 }
2980
2981 if (cache_level == I915_CACHE_NONE) {
2982 u32 old_read_domains, old_write_domain;
2983
2984 /* If we're coming from LLC cached, then we haven't
2985 * actually been tracking whether the data is in the
2986 * CPU cache or not, since we only allow one bit set
2987 * in obj->write_domain and have been skipping the clflushes.
2988 * Just set it to the CPU cache for now.
2989 */
2990 WARN_ON(obj->base.write_domain & ~I915_GEM_DOMAIN_CPU);
2991 WARN_ON(obj->base.read_domains & ~I915_GEM_DOMAIN_CPU);
2992
2993 old_read_domains = obj->base.read_domains;
2994 old_write_domain = obj->base.write_domain;
2995
2996 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
2997 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
2998
2999 trace_i915_gem_object_change_domain(obj,
3000 old_read_domains,
3001 old_write_domain);
3002 }
3003
3004 obj->cache_level = cache_level;
3005 return 0;
3006}
3007
b9241ea3 3008/*
2da3b9b9
CW		 3009 * Prepare buffer for display plane (scanout, cursors, etc).
3010 * Can be called from an uninterruptible phase (modesetting) and allows
3011 * any flushes to be pipelined (for pageflips).
b9241ea3
ZW		 3012 */
3013int
2da3b9b9
CW		 3014i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
3015 u32 alignment,
919926ae 3016 struct intel_ring_buffer *pipelined)
b9241ea3 3017{
2da3b9b9 3018 u32 old_read_domains, old_write_domain;
b9241ea3
ZW		 3019 int ret;
3020
88241785
CW		 3021 ret = i915_gem_object_flush_gpu_write_domain(obj);
3022 if (ret)
3023 return ret;
3024
0be73284 3025 if (pipelined != obj->ring) {
2911a35b
BW		 3026 ret = i915_gem_object_sync(obj, pipelined);
3027 if (ret)
b9241ea3
ZW		 3028 return ret;
3029 }
3030
a7ef0640
EA		 3031 /* The display engine is not coherent with the LLC cache on gen6. As
3032 * a result, we make sure that the pinning that is about to occur is
3033 * done with uncached PTEs. This is lowest common denominator for all
3034 * chipsets.
3035 *
3036 * However for gen6+, we could do better by using the GFDT bit instead
3037 * of uncaching, which would allow us to flush all the LLC-cached data
3038 * with that bit in the PTE to main memory with just one PIPE_CONTROL.
3039 */
3040 ret = i915_gem_object_set_cache_level(obj, I915_CACHE_NONE);
3041 if (ret)
3042 return ret;
3043
2da3b9b9
CW		 3044 /* As the user may map the buffer once pinned in the display plane
3045 * (e.g. libkms for the bootup splash), we have to ensure that we
3046 * always use map_and_fenceable for all scanout buffers.
3047 */
3048 ret = i915_gem_object_pin(obj, alignment, true);
3049 if (ret)
3050 return ret;
3051
b118c1e3
CW		 3052 i915_gem_object_flush_cpu_write_domain(obj);
3053
2da3b9b9 3054 old_write_domain = obj->base.write_domain;
05394f39 3055 old_read_domains = obj->base.read_domains;
2da3b9b9
CW		 3056
3057 /* It should now be out of any other write domains, and we can update
3058 * the domain values for our changes.
3059 */
3060 BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_GTT) != 0);
05394f39 3061 obj->base.read_domains |= I915_GEM_DOMAIN_GTT;
b9241ea3
ZW		 3062
3063 trace_i915_gem_object_change_domain(obj,
3064 old_read_domains,
2da3b9b9 3065 old_write_domain);
b9241ea3
ZW		 3066
3067 return 0;
3068}
3069
85345517 3070int
a8198eea 3071i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj)
85345517 3072{
88241785
CW		 3073 int ret;
3074
a8198eea 3075 if ((obj->base.read_domains & I915_GEM_GPU_DOMAINS) == 0)
85345517
CW		 3076 return 0;
3077
88241785 3078 if (obj->base.write_domain & I915_GEM_GPU_DOMAINS) {
db53a302 3079 ret = i915_gem_flush_ring(obj->ring, 0, obj->base.write_domain);
88241785
CW		 3080 if (ret)
3081 return ret;
3082 }
85345517 3083
c501ae7f
CW		 3084 ret = i915_gem_object_wait_rendering(obj);
3085 if (ret)
3086 return ret;
3087
a8198eea
CW		 3088 /* Ensure that we invalidate the GPU's caches and TLBs. */
3089 obj->base.read_domains &= ~I915_GEM_GPU_DOMAINS;
c501ae7f 3090 return 0;
85345517
CW		 3091}
3092
e47c68e9
EA		 3093/**
3094 * Moves a single object to the CPU read, and possibly write domain.
3095 *
3096 * This function returns when the move is complete, including waiting on
3097 * flushes to occur.
3098 */
dabdfe02 3099int
919926ae 3100i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write)
e47c68e9 3101{
1c5d22f7 3102 uint32_t old_write_domain, old_read_domains;
e47c68e9
EA		 3103 int ret;
3104
8d7e3de1
CW		 3105 if (obj->base.write_domain == I915_GEM_DOMAIN_CPU)
3106 return 0;
3107
88241785
CW		 3108 ret = i915_gem_object_flush_gpu_write_domain(obj);
3109 if (ret)
3110 return ret;
3111
f8413190
CW		 3112 if (write || obj->pending_gpu_write) {
3113 ret = i915_gem_object_wait_rendering(obj);
3114 if (ret)
3115 return ret;
3116 }
2ef7eeaa 3117
e47c68e9 3118 i915_gem_object_flush_gtt_write_domain(obj);
2ef7eeaa 3119
05394f39
CW		 3120 old_write_domain = obj->base.write_domain;
3121 old_read_domains = obj->base.read_domains;
1c5d22f7 3122
e47c68e9 3123 /* Flush the CPU cache if it's still invalid. */
05394f39 3124 if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0) {
2ef7eeaa 3125 i915_gem_clflush_object(obj);
2ef7eeaa 3126
05394f39 3127 obj->base.read_domains |= I915_GEM_DOMAIN_CPU;
2ef7eeaa
EA		 3128 }
3129
3130 /* It should now be out of any other write domains, and we can update
3131 * the domain values for our changes.
3132 */
05394f39 3133 BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_CPU) != 0);
e47c68e9
EA		 3134
3135 /* If we're writing through the CPU, then the GPU read domains will
3136 * need to be invalidated at next use.
3137 */
3138 if (write) {
05394f39
CW		 3139 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
3140 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
e47c68e9 3141 }
2ef7eeaa 3142
1c5d22f7
CW		 3143 trace_i915_gem_object_change_domain(obj,
3144 old_read_domains,
3145 old_write_domain);
3146
2ef7eeaa
EA		 3147 return 0;
3148}
3149
673a394b
EA		 3150/* Throttle our rendering by waiting until the ring has completed our requests
3151 * emitted over 20 msec ago.
3152 *
b962442e
EA		 3153 * Note that if we were to use the current jiffies each time around the loop,
3154 * we wouldn't escape the function with any frames outstanding if the time to
3155 * render a frame was over 20ms.
3156 *
673a394b
EA		 3157 * This should get us reasonable parallelism between CPU and GPU but also
3158 * relatively low latency when blocking on a particular request to finish.
3159 */
40a5f0de 3160static int
f787a5f5 3161i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file)
40a5f0de 3162{
f787a5f5
CW		 3163 struct drm_i915_private *dev_priv = dev->dev_private;
3164 struct drm_i915_file_private *file_priv = file->driver_priv;
b962442e 3165 unsigned long recent_enough = jiffies - msecs_to_jiffies(20);
f787a5f5
CW		 3166 struct drm_i915_gem_request *request;
3167 struct intel_ring_buffer *ring = NULL;
3168 u32 seqno = 0;
3169 int ret;
93533c29 3170
e110e8d6
CW		 3171 if (atomic_read(&dev_priv->mm.wedged))
3172 return -EIO;
3173
1c25595f 3174 spin_lock(&file_priv->mm.lock);
f787a5f5 3175 list_for_each_entry(request, &file_priv->mm.request_list, client_list) {
b962442e
EA		 3176 if (time_after_eq(request->emitted_jiffies, recent_enough))
3177 break;
40a5f0de 3178
f787a5f5
CW		 3179 ring = request->ring;
3180 seqno = request->seqno;
b962442e 3181 }
1c25595f 3182 spin_unlock(&file_priv->mm.lock);
40a5f0de 3183
f787a5f5
CW		 3184 if (seqno == 0)
3185 return 0;
2bc43b5c 3186
5c81fe85 3187 ret = __wait_seqno(ring, seqno, true, NULL);
f787a5f5
CW		 3188 if (ret == 0)
3189 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, 0);
40a5f0de
EA		 3190
3191 return ret;
3192}
3193
673a394b 3194int
05394f39
CW		 3195i915_gem_object_pin(struct drm_i915_gem_object *obj,
3196 uint32_t alignment,
75e9e915 3197 bool map_and_fenceable)
673a394b 3198{
673a394b
EA		 3199 int ret;
3200
05394f39 3201 BUG_ON(obj->pin_count == DRM_I915_GEM_OBJECT_MAX_PIN_COUNT);
ac0c6b5a 3202
05394f39
CW		 3203 if (obj->gtt_space != NULL) {
3204 if ((alignment && obj->gtt_offset & (alignment - 1)) ||
3205 (map_and_fenceable && !obj->map_and_fenceable)) {
3206 WARN(obj->pin_count,
ae7d49d8 3207 "bo is already pinned with incorrect alignment:"
75e9e915
DV		 3208 " offset=%x, req.alignment=%x, req.map_and_fenceable=%d,"
3209 " obj->map_and_fenceable=%d\n",
05394f39 3210 obj->gtt_offset, alignment,
75e9e915 3211 map_and_fenceable,
05394f39 3212 obj->map_and_fenceable);
ac0c6b5a
CW		 3213 ret = i915_gem_object_unbind(obj);
3214 if (ret)
3215 return ret;
3216 }
3217 }
3218
05394f39 3219 if (obj->gtt_space == NULL) {
a00b10c3 3220 ret = i915_gem_object_bind_to_gtt(obj, alignment,
75e9e915 3221 map_and_fenceable);
9731129c 3222 if (ret)
673a394b 3223 return ret;
22c344e9 3224 }
76446cac 3225
74898d7e
DV		 3226 if (!obj->has_global_gtt_mapping && map_and_fenceable)
3227 i915_gem_gtt_bind_object(obj, obj->cache_level);
3228
1b50247a 3229 obj->pin_count++;
6299f992 3230 obj->pin_mappable |= map_and_fenceable;
673a394b
EA		 3231
3232 return 0;
3233}
3234
3235void
05394f39 3236i915_gem_object_unpin(struct drm_i915_gem_object *obj)
673a394b 3237{
05394f39
CW		 3238 BUG_ON(obj->pin_count == 0);
3239 BUG_ON(obj->gtt_space == NULL);
673a394b 3240
1b50247a 3241 if (--obj->pin_count == 0)
6299f992 3242 obj->pin_mappable = false;
673a394b
EA		 3243}
3244
3245int
3246i915_gem_pin_ioctl(struct drm_device *dev, void *data,
05394f39 3247 struct drm_file *file)
673a394b
EA		 3248{
3249 struct drm_i915_gem_pin *args = data;
05394f39 3250 struct drm_i915_gem_object *obj;
673a394b
EA		 3251 int ret;
3252
1d7cfea1
CW		 3253 ret = i915_mutex_lock_interruptible(dev);
3254 if (ret)
3255 return ret;
673a394b 3256
05394f39 3257 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
c8725226 3258 if (&obj->base == NULL) {
1d7cfea1
CW		 3259 ret = -ENOENT;
3260 goto unlock;
673a394b 3261 }
673a394b 3262
05394f39 3263 if (obj->madv != I915_MADV_WILLNEED) {
bb6baf76 3264 DRM_ERROR("Attempting to pin a purgeable buffer\n");
1d7cfea1
CW		 3265 ret = -EINVAL;
3266 goto out;
3ef94daa
CW		 3267 }
3268
05394f39 3269 if (obj->pin_filp != NULL && obj->pin_filp != file) {
79e53945
JB		 3270 DRM_ERROR("Already pinned in i915_gem_pin_ioctl(): %d\n",
3271 args->handle);
1d7cfea1
CW		 3272 ret = -EINVAL;
3273 goto out;
79e53945
JB		 3274 }
3275
05394f39
CW		 3276 obj->user_pin_count++;
3277 obj->pin_filp = file;
3278 if (obj->user_pin_count == 1) {
75e9e915 3279 ret = i915_gem_object_pin(obj, args->alignment, true);
1d7cfea1
CW		 3280 if (ret)
3281 goto out;
673a394b
EA		 3282 }
3283
3284 /* XXX - flush the CPU caches for pinned objects
3285 * as the X server doesn't manage domains yet
3286 */
e47c68e9 3287 i915_gem_object_flush_cpu_write_domain(obj);
05394f39 3288 args->offset = obj->gtt_offset;
1d7cfea1 3289out:
05394f39 3290 drm_gem_object_unreference(&obj->base);
1d7cfea1 3291unlock:
673a394b 3292 mutex_unlock(&dev->struct_mutex);
1d7cfea1 3293 return ret;
673a394b
EA		 3294}
3295
3296int
3297i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
05394f39 3298 struct drm_file *file)
673a394b
EA		 3299{
3300 struct drm_i915_gem_pin *args = data;
05394f39 3301 struct drm_i915_gem_object *obj;
76c1dec1 3302 int ret;
673a394b 3303
1d7cfea1
CW		 3304 ret = i915_mutex_lock_interruptible(dev);
3305 if (ret)
3306 return ret;
673a394b 3307
05394f39 3308 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
c8725226 3309 if (&obj->base == NULL) {
1d7cfea1
CW		 3310 ret = -ENOENT;
3311 goto unlock;
673a394b 3312 }
76c1dec1 3313
05394f39 3314 if (obj->pin_filp != file) {
79e53945
JB		 3315 DRM_ERROR("Not pinned by caller in i915_gem_pin_ioctl(): %d\n",
3316 args->handle);
1d7cfea1
CW		 3317 ret = -EINVAL;
3318 goto out;
79e53945 3319 }
05394f39
CW		 3320 obj->user_pin_count--;
3321 if (obj->user_pin_count == 0) {
3322 obj->pin_filp = NULL;
79e53945
JB		 3323 i915_gem_object_unpin(obj);
3324 }
673a394b 3325
1d7cfea1 3326out:
05394f39 3327 drm_gem_object_unreference(&obj->base);
1d7cfea1 3328unlock:
673a394b 3329 mutex_unlock(&dev->struct_mutex);
1d7cfea1 3330 return ret;
673a394b
EA		 3331}
3332
3333int
3334i915_gem_busy_ioctl(struct drm_device *dev, void *data,
05394f39 3335 struct drm_file *file)
673a394b
EA		 3336{
3337 struct drm_i915_gem_busy *args = data;
05394f39 3338 struct drm_i915_gem_object *obj;
30dbf0c0
CW		 3339 int ret;
3340
76c1dec1 3341 ret = i915_mutex_lock_interruptible(dev);
1d7cfea1 3342 if (ret)
76c1dec1 3343 return ret;
673a394b 3344
05394f39 3345 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
c8725226 3346 if (&obj->base == NULL) {
1d7cfea1
CW		 3347 ret = -ENOENT;
3348 goto unlock;
673a394b 3349 }
d1b851fc 3350
0be555b6
CW		 3351 /* Count all active objects as busy, even if they are currently not used
3352 * by the gpu. Users of this interface expect objects to eventually
3353 * become non-busy without any further actions, therefore emit any
3354 * necessary flushes here.
c4de0a5d 3355 */
30dfebf3 3356 ret = i915_gem_object_flush_active(obj);
0be555b6 3357
30dfebf3 3358 args->busy = obj->active;
673a394b 3359
05394f39 3360 drm_gem_object_unreference(&obj->base);
1d7cfea1 3361unlock:
673a394b 3362 mutex_unlock(&dev->struct_mutex);
1d7cfea1 3363 return ret;
673a394b
EA		 3364}
3365
3366int
3367i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
3368 struct drm_file *file_priv)
3369{
0206e353 3370 return i915_gem_ring_throttle(dev, file_priv);
673a394b
EA		 3371}
3372
3ef94daa
CW		 3373int
3374i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
3375 struct drm_file *file_priv)
3376{
3377 struct drm_i915_gem_madvise *args = data;
05394f39 3378 struct drm_i915_gem_object *obj;
76c1dec1 3379 int ret;
3ef94daa
CW		 3380
3381 switch (args->madv) {
3382 case I915_MADV_DONTNEED:
3383 case I915_MADV_WILLNEED:
3384 break;
3385 default:
3386 return -EINVAL;
3387 }
3388
1d7cfea1
CW		 3389 ret = i915_mutex_lock_interruptible(dev);
3390 if (ret)
3391 return ret;
3392
05394f39 3393 obj = to_intel_bo(drm_gem_object_lookup(dev, file_priv, args->handle));
c8725226 3394 if (&obj->base == NULL) {
1d7cfea1
CW		 3395 ret = -ENOENT;
3396 goto unlock;
3ef94daa 3397 }
3ef94daa 3398
05394f39 3399 if (obj->pin_count) {
1d7cfea1
CW		 3400 ret = -EINVAL;
3401 goto out;
3ef94daa
CW		 3402 }
3403
05394f39
CW		 3404 if (obj->madv != __I915_MADV_PURGED)
3405 obj->madv = args->madv;
3ef94daa 3406
2d7ef395 3407 /* if the object is no longer bound, discard its backing storage */
05394f39
CW		 3408 if (i915_gem_object_is_purgeable(obj) &&
3409 obj->gtt_space == NULL)
2d7ef395
CW		 3410 i915_gem_object_truncate(obj);
3411
05394f39 3412 args->retained = obj->madv != __I915_MADV_PURGED;
bb6baf76 3413
1d7cfea1 3414out:
05394f39 3415 drm_gem_object_unreference(&obj->base);
1d7cfea1 3416unlock:
3ef94daa 3417 mutex_unlock(&dev->struct_mutex);
1d7cfea1 3418 return ret;
3ef94daa
CW		 3419}
3420
05394f39
CW		 3421struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev,
3422 size_t size)
ac52bc56 3423{
73aa808f 3424 struct drm_i915_private *dev_priv = dev->dev_private;
c397b908 3425 struct drm_i915_gem_object *obj;
5949eac4 3426 struct address_space *mapping;
bed1ea95 3427 u32 mask;
ac52bc56 3428
c397b908
DV		 3429 obj = kzalloc(sizeof(*obj), GFP_KERNEL);
3430 if (obj == NULL)
3431 return NULL;
673a394b 3432
c397b908
DV		 3433 if (drm_gem_object_init(dev, &obj->base, size) != 0) {
3434 kfree(obj);
3435 return NULL;
3436 }
673a394b 3437
bed1ea95
CW		 3438 mask = GFP_HIGHUSER | __GFP_RECLAIMABLE;
3439 if (IS_CRESTLINE(dev) || IS_BROADWATER(dev)) {
3440 /* 965gm cannot relocate objects above 4GiB. */
3441 mask &= ~__GFP_HIGHMEM;
3442 mask |= __GFP_DMA32;
3443 }
3444
5949eac4 3445 mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping;
bed1ea95 3446 mapping_set_gfp_mask(mapping, mask);
5949eac4 3447
73aa808f
CW		 3448 i915_gem_info_add_obj(dev_priv, size);
3449
c397b908
DV		 3450 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
3451 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
673a394b 3452
3d29b842
ED		 3453 if (HAS_LLC(dev)) {
3454 /* On some devices, we can have the GPU use the LLC (the CPU
a1871112
EA		 3455 * cache) for about a 10% performance improvement
3456 * compared to uncached. Graphics requests other than
3457 * display scanout are coherent with the CPU in
3458 * accessing this cache. This means in this mode we
3459 * don't need to clflush on the CPU side, and on the
3460 * GPU side we only need to flush internal caches to
3461 * get data visible to the CPU.
3462 *
3463 * However, we maintain the display planes as UC, and so
3464 * need to rebind when first used as such.
3465 */
3466 obj->cache_level = I915_CACHE_LLC;
3467 } else
3468 obj->cache_level = I915_CACHE_NONE;
3469
62b8b215 3470 obj->base.driver_private = NULL;
c397b908 3471 obj->fence_reg = I915_FENCE_REG_NONE;
69dc4987 3472 INIT_LIST_HEAD(&obj->mm_list);
93a37f20 3473 INIT_LIST_HEAD(&obj->gtt_list);
69dc4987 3474 INIT_LIST_HEAD(&obj->ring_list);
432e58ed 3475 INIT_LIST_HEAD(&obj->exec_list);
c397b908 3476 INIT_LIST_HEAD(&obj->gpu_write_list);
c397b908 3477 obj->madv = I915_MADV_WILLNEED;
75e9e915
DV		 3478 /* Avoid an unnecessary call to unbind on the first bind. */
3479 obj->map_and_fenceable = true;
de151cf6 3480
05394f39 3481 return obj;
c397b908
DV		 3482}
3483
3484int i915_gem_init_object(struct drm_gem_object *obj)
3485{
3486 BUG();
de151cf6 3487
673a394b
EA		 3488 return 0;
3489}
3490
1488fc08 3491void i915_gem_free_object(struct drm_gem_object *gem_obj)
673a394b 3492{
1488fc08 3493 struct drm_i915_gem_object *obj = to_intel_bo(gem_obj);
05394f39 3494 struct drm_device *dev = obj->base.dev;
be72615b 3495 drm_i915_private_t *dev_priv = dev->dev_private;
673a394b 3496
26e12f89
CW		 3497 trace_i915_gem_object_destroy(obj);
3498
1286ff73
DV		 3499 if (gem_obj->import_attach)
3500 drm_prime_gem_destroy(gem_obj, obj->sg_table);
3501
1488fc08
CW		 3502 if (obj->phys_obj)
3503 i915_gem_detach_phys_object(dev, obj);
3504
3505 obj->pin_count = 0;
3506 if (WARN_ON(i915_gem_object_unbind(obj) == -ERESTARTSYS)) {
3507 bool was_interruptible;
3508
3509 was_interruptible = dev_priv->mm.interruptible;
3510 dev_priv->mm.interruptible = false;
3511
3512 WARN_ON(i915_gem_object_unbind(obj));
3513
3514 dev_priv->mm.interruptible = was_interruptible;
3515 }
3516
05394f39 3517 if (obj->base.map_list.map)
b464e9a2 3518 drm_gem_free_mmap_offset(&obj->base);
de151cf6 3519
05394f39
CW		 3520 drm_gem_object_release(&obj->base);
3521 i915_gem_info_remove_obj(dev_priv, obj->base.size);
c397b908 3522
05394f39
CW		 3523 kfree(obj->bit_17);
3524 kfree(obj);
673a394b
EA		 3525}
3526
29105ccc
CW		 3527int
3528i915_gem_idle(struct drm_device *dev)
3529{
3530 drm_i915_private_t *dev_priv = dev->dev_private;
3531 int ret;
28dfe52a 3532
29105ccc 3533 mutex_lock(&dev->struct_mutex);
1c5d22f7 3534
87acb0a5 3535 if (dev_priv->mm.suspended) {
29105ccc
CW		 3536 mutex_unlock(&dev->struct_mutex);
3537 return 0;
28dfe52a
EA		 3538 }
3539
b2da9fe5 3540 ret = i915_gpu_idle(dev);
6dbe2772
KP		 3541 if (ret) {
3542 mutex_unlock(&dev->struct_mutex);
673a394b 3543 return ret;
6dbe2772 3544 }
b2da9fe5 3545 i915_gem_retire_requests(dev);
673a394b 3546
29105ccc 3547 /* Under UMS, be paranoid and evict. */
a39d7efc
CW		 3548 if (!drm_core_check_feature(dev, DRIVER_MODESET))
3549 i915_gem_evict_everything(dev, false);
29105ccc 3550
312817a3
CW		 3551 i915_gem_reset_fences(dev);
3552
29105ccc
CW		 3553 /* Hack! Don't let anybody do execbuf while we don't control the chip.
3554 * We need to replace this with a semaphore, or something.
3555 * And not confound mm.suspended!
3556 */
3557 dev_priv->mm.suspended = 1;
bc0c7f14 3558 del_timer_sync(&dev_priv->hangcheck_timer);
29105ccc
CW		 3559
3560 i915_kernel_lost_context(dev);
6dbe2772 3561 i915_gem_cleanup_ringbuffer(dev);
29105ccc 3562
6dbe2772
KP		 3563 mutex_unlock(&dev->struct_mutex);
3564
29105ccc
CW		 3565 /* Cancel the retire work handler, which should be idle now. */
3566 cancel_delayed_work_sync(&dev_priv->mm.retire_work);
3567
673a394b
EA		 3568 return 0;
3569}
3570
b9524a1e
BW		 3571void i915_gem_l3_remap(struct drm_device *dev)
3572{
3573 drm_i915_private_t *dev_priv = dev->dev_private;
3574 u32 misccpctl;
3575 int i;
3576
3577 if (!IS_IVYBRIDGE(dev))
3578 return;
3579
3580 if (!dev_priv->mm.l3_remap_info)
3581 return;
3582
3583 misccpctl = I915_READ(GEN7_MISCCPCTL);
3584 I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
3585 POSTING_READ(GEN7_MISCCPCTL);
3586
3587 for (i = 0; i < GEN7_L3LOG_SIZE; i += 4) {
3588 u32 remap = I915_READ(GEN7_L3LOG_BASE + i);
3589 if (remap && remap != dev_priv->mm.l3_remap_info[i/4])
3590 DRM_DEBUG("0x%x was already programmed to %x\n",
3591 GEN7_L3LOG_BASE + i, remap);
3592 if (remap && !dev_priv->mm.l3_remap_info[i/4])
3593 DRM_DEBUG_DRIVER("Clearing remapped register\n");
3594 I915_WRITE(GEN7_L3LOG_BASE + i, dev_priv->mm.l3_remap_info[i/4]);
3595 }
3596
3597 /* Make sure all the writes land before disabling dop clock gating */
3598 POSTING_READ(GEN7_L3LOG_BASE);
3599
3600 I915_WRITE(GEN7_MISCCPCTL, misccpctl);
3601}
3602
f691e2f4
DV		 3603void i915_gem_init_swizzling(struct drm_device *dev)
3604{
3605 drm_i915_private_t *dev_priv = dev->dev_private;
3606
11782b02 3607 if (INTEL_INFO(dev)->gen < 5 ||
f691e2f4
DV		 3608 dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_NONE)
3609 return;
3610
3611 I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) |
3612 DISP_TILE_SURFACE_SWIZZLING);
3613
11782b02
DV		 3614 if (IS_GEN5(dev))
3615 return;
3616
f691e2f4
DV		 3617 I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_SWZCTL);
3618 if (IS_GEN6(dev))
6b26c86d 3619 I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB));
f691e2f4 3620 else
6b26c86d 3621 I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB));
f691e2f4 3622}
e21af88d
DV		 3623
3624void i915_gem_init_ppgtt(struct drm_device *dev)
3625{
3626 drm_i915_private_t *dev_priv = dev->dev_private;
3627 uint32_t pd_offset;
3628 struct intel_ring_buffer *ring;
55a254ac
DV		 3629 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
3630 uint32_t __iomem *pd_addr;
3631 uint32_t pd_entry;
e21af88d
DV		 3632 int i;
3633
3634 if (!dev_priv->mm.aliasing_ppgtt)
3635 return;
3636
55a254ac
DV		 3637
3638 pd_addr = dev_priv->mm.gtt->gtt + ppgtt->pd_offset/sizeof(uint32_t);
3639 for (i = 0; i < ppgtt->num_pd_entries; i++) {
3640 dma_addr_t pt_addr;
3641
3642 if (dev_priv->mm.gtt->needs_dmar)
3643 pt_addr = ppgtt->pt_dma_addr[i];
3644 else
3645 pt_addr = page_to_phys(ppgtt->pt_pages[i]);
3646
3647 pd_entry = GEN6_PDE_ADDR_ENCODE(pt_addr);
3648 pd_entry |= GEN6_PDE_VALID;
3649
3650 writel(pd_entry, pd_addr + i);
3651 }
3652 readl(pd_addr);
3653
3654 pd_offset = ppgtt->pd_offset;
e21af88d
DV		 3655 pd_offset /= 64; /* in cachelines, */
3656 pd_offset <<= 16;
3657
3658 if (INTEL_INFO(dev)->gen == 6) {
48ecfa10
DV		 3659 uint32_t ecochk, gab_ctl, ecobits;
3660
3661 ecobits = I915_READ(GAC_ECO_BITS);
3662 I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_PPGTT_CACHE64B);
be901a5a
DV		 3663
3664 gab_ctl = I915_READ(GAB_CTL);
3665 I915_WRITE(GAB_CTL, gab_ctl | GAB_CTL_CONT_AFTER_PAGEFAULT);
3666
3667 ecochk = I915_READ(GAM_ECOCHK);
e21af88d
DV		 3668 I915_WRITE(GAM_ECOCHK, ecochk | ECOCHK_SNB_BIT |
3669 ECOCHK_PPGTT_CACHE64B);
6b26c86d 3670 I915_WRITE(GFX_MODE, _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
e21af88d
DV		 3671 } else if (INTEL_INFO(dev)->gen >= 7) {
3672 I915_WRITE(GAM_ECOCHK, ECOCHK_PPGTT_CACHE64B);
3673 /* GFX_MODE is per-ring on gen7+ */
3674 }
3675
b4519513 3676 for_each_ring(ring, dev_priv, i) {
e21af88d
DV		 3677 if (INTEL_INFO(dev)->gen >= 7)
3678 I915_WRITE(RING_MODE_GEN7(ring),
6b26c86d 3679 _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
e21af88d
DV		 3680
3681 I915_WRITE(RING_PP_DIR_DCLV(ring), PP_DIR_DCLV_2G);
3682 I915_WRITE(RING_PP_DIR_BASE(ring), pd_offset);
3683 }
3684}
3685
8187a2b7 3686int
f691e2f4 3687i915_gem_init_hw(struct drm_device *dev)
8187a2b7
ZN		 3688{
3689 drm_i915_private_t *dev_priv = dev->dev_private;
3690 int ret;
68f95ba9 3691
b9524a1e
BW		 3692 i915_gem_l3_remap(dev);
3693
f691e2f4
DV		 3694 i915_gem_init_swizzling(dev);
3695
5c1143bb 3696 ret = intel_init_render_ring_buffer(dev);
68f95ba9 3697 if (ret)
b6913e4b 3698 return ret;
68f95ba9
CW		 3699
3700 if (HAS_BSD(dev)) {
5c1143bb 3701 ret = intel_init_bsd_ring_buffer(dev);
68f95ba9
CW		 3702 if (ret)
3703 goto cleanup_render_ring;
d1b851fc 3704 }
68f95ba9 3705
549f7365
CW		 3706 if (HAS_BLT(dev)) {
3707 ret = intel_init_blt_ring_buffer(dev);
3708 if (ret)
3709 goto cleanup_bsd_ring;
3710 }
3711
6f392d54
CW		 3712 dev_priv->next_seqno = 1;
3713
e21af88d
DV		 3714 i915_gem_init_ppgtt(dev);
3715
68f95ba9
CW		 3716 return 0;
3717
549f7365 3718cleanup_bsd_ring:
1ec14ad3 3719 intel_cleanup_ring_buffer(&dev_priv->ring[VCS]);
68f95ba9 3720cleanup_render_ring:
1ec14ad3 3721 intel_cleanup_ring_buffer(&dev_priv->ring[RCS]);
8187a2b7
ZN		 3722 return ret;
3723}
3724
1070a42b
CW		 3725static bool
3726intel_enable_ppgtt(struct drm_device *dev)
3727{
3728 if (i915_enable_ppgtt >= 0)
3729 return i915_enable_ppgtt;
3730
3731#ifdef CONFIG_INTEL_IOMMU
3732 /* Disable ppgtt on SNB if VT-d is on. */
3733 if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped)
3734 return false;
3735#endif
3736
3737 return true;
3738}
3739
3740int i915_gem_init(struct drm_device *dev)
3741{
3742 struct drm_i915_private *dev_priv = dev->dev_private;
3743 unsigned long gtt_size, mappable_size;
3744 int ret;
3745
3746 gtt_size = dev_priv->mm.gtt->gtt_total_entries << PAGE_SHIFT;
3747 mappable_size = dev_priv->mm.gtt->gtt_mappable_entries << PAGE_SHIFT;
3748
3749 mutex_lock(&dev->struct_mutex);
3750 if (intel_enable_ppgtt(dev) && HAS_ALIASING_PPGTT(dev)) {
3751 /* PPGTT pdes are stolen from global gtt ptes, so shrink the
3752 * aperture accordingly when using aliasing ppgtt. */
3753 gtt_size -= I915_PPGTT_PD_ENTRIES*PAGE_SIZE;
3754
3755 i915_gem_init_global_gtt(dev, 0, mappable_size, gtt_size);
3756
3757 ret = i915_gem_init_aliasing_ppgtt(dev);
3758 if (ret) {
3759 mutex_unlock(&dev->struct_mutex);
3760 return ret;
3761 }
3762 } else {
3763 /* Let GEM Manage all of the aperture.
3764 *
3765 * However, leave one page at the end still bound to the scratch
3766 * page. There are a number of places where the hardware
3767 * apparently prefetches past the end of the object, and we've
3768 * seen multiple hangs with the GPU head pointer stuck in a
3769 * batchbuffer bound at the last page of the aperture. One page
3770 * should be enough to keep any prefetching inside of the
3771 * aperture.
3772 */
3773 i915_gem_init_global_gtt(dev, 0, mappable_size,
3774 gtt_size);
3775 }
3776
3777 ret = i915_gem_init_hw(dev);
3778 mutex_unlock(&dev->struct_mutex);
3779 if (ret) {
3780 i915_gem_cleanup_aliasing_ppgtt(dev);
3781 return ret;
3782 }
3783
53ca26ca
DV		 3784 /* Allow hardware batchbuffers unless told otherwise, but not for KMS. */
3785 if (!drm_core_check_feature(dev, DRIVER_MODESET))
3786 dev_priv->dri1.allow_batchbuffer = 1;
1070a42b
CW		 3787 return 0;
3788}
3789
8187a2b7
ZN		 3790void
3791i915_gem_cleanup_ringbuffer(struct drm_device *dev)
3792{
3793 drm_i915_private_t *dev_priv = dev->dev_private;
b4519513 3794 struct intel_ring_buffer *ring;
1ec14ad3 3795 int i;
8187a2b7 3796
b4519513
CW		 3797 for_each_ring(ring, dev_priv, i)
3798 intel_cleanup_ring_buffer(ring);
8187a2b7
ZN		 3799}
3800
673a394b
EA		 3801int
3802i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
3803 struct drm_file *file_priv)
3804{
3805 drm_i915_private_t *dev_priv = dev->dev_private;
b4519513 3806 int ret;
673a394b 3807
79e53945
JB		 3808 if (drm_core_check_feature(dev, DRIVER_MODESET))
3809 return 0;
3810
ba1234d1 3811 if (atomic_read(&dev_priv->mm.wedged)) {
673a394b 3812 DRM_ERROR("Reenabling wedged hardware, good luck\n");
ba1234d1 3813 atomic_set(&dev_priv->mm.wedged, 0);
673a394b
EA		 3814 }
3815
673a394b 3816 mutex_lock(&dev->struct_mutex);
9bb2d6f9
EA		 3817 dev_priv->mm.suspended = 0;
3818
f691e2f4 3819 ret = i915_gem_init_hw(dev);
d816f6ac
WF		 3820 if (ret != 0) {
3821 mutex_unlock(&dev->struct_mutex);
9bb2d6f9 3822 return ret;
d816f6ac 3823 }
9bb2d6f9 3824
69dc4987 3825 BUG_ON(!list_empty(&dev_priv->mm.active_list));
673a394b
EA		 3826 BUG_ON(!list_empty(&dev_priv->mm.flushing_list));
3827 BUG_ON(!list_empty(&dev_priv->mm.inactive_list));
673a394b 3828 mutex_unlock(&dev->struct_mutex);
dbb19d30 3829
5f35308b
CW		 3830 ret = drm_irq_install(dev);
3831 if (ret)
3832 goto cleanup_ringbuffer;
dbb19d30 3833
673a394b 3834 return 0;
5f35308b
CW		 3835
3836cleanup_ringbuffer:
3837 mutex_lock(&dev->struct_mutex);
3838 i915_gem_cleanup_ringbuffer(dev);
3839 dev_priv->mm.suspended = 1;
3840 mutex_unlock(&dev->struct_mutex);
3841
3842 return ret;
673a394b
EA		 3843}
3844
3845int
3846i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
3847 struct drm_file *file_priv)
3848{
79e53945
JB		 3849 if (drm_core_check_feature(dev, DRIVER_MODESET))
3850 return 0;
3851
dbb19d30 3852 drm_irq_uninstall(dev);
e6890f6f 3853 return i915_gem_idle(dev);
673a394b
EA		 3854}
3855
3856void
3857i915_gem_lastclose(struct drm_device *dev)
3858{
3859 int ret;
673a394b 3860
e806b495
EA		 3861 if (drm_core_check_feature(dev, DRIVER_MODESET))
3862 return;
3863
6dbe2772
KP		 3864 ret = i915_gem_idle(dev);
3865 if (ret)
3866 DRM_ERROR("failed to idle hardware: %d\n", ret);
673a394b
EA		 3867}
3868
64193406
CW		 3869static void
3870init_ring_lists(struct intel_ring_buffer *ring)
3871{
3872 INIT_LIST_HEAD(&ring->active_list);
3873 INIT_LIST_HEAD(&ring->request_list);
3874 INIT_LIST_HEAD(&ring->gpu_write_list);
3875}
3876
673a394b
EA		 3877void
3878i915_gem_load(struct drm_device *dev)
3879{
b5aa8a0f 3880 int i;
673a394b
EA		 3881 drm_i915_private_t *dev_priv = dev->dev_private;
3882
69dc4987 3883 INIT_LIST_HEAD(&dev_priv->mm.active_list);
673a394b
EA		 3884 INIT_LIST_HEAD(&dev_priv->mm.flushing_list);
3885 INIT_LIST_HEAD(&dev_priv->mm.inactive_list);
a09ba7fa 3886 INIT_LIST_HEAD(&dev_priv->mm.fence_list);
93a37f20 3887 INIT_LIST_HEAD(&dev_priv->mm.gtt_list);
1ec14ad3
CW		 3888 for (i = 0; i < I915_NUM_RINGS; i++)
3889 init_ring_lists(&dev_priv->ring[i]);
4b9de737 3890 for (i = 0; i < I915_MAX_NUM_FENCES; i++)
007cc8ac 3891 INIT_LIST_HEAD(&dev_priv->fence_regs[i].lru_list);
673a394b
EA		 3892 INIT_DELAYED_WORK(&dev_priv->mm.retire_work,
3893 i915_gem_retire_work_handler);
30dbf0c0 3894 init_completion(&dev_priv->error_completion);
31169714 3895
94400120
DA		 3896 /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
3897 if (IS_GEN3(dev)) {
50743298
DV		 3898 I915_WRITE(MI_ARB_STATE,
3899 _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE));
94400120
DA		 3900 }
3901
72bfa19c
CW		 3902 dev_priv->relative_constants_mode = I915_EXEC_CONSTANTS_REL_GENERAL;
3903
de151cf6 3904 /* Old X drivers will take 0-2 for front, back, depth buffers */
b397c836
EA		 3905 if (!drm_core_check_feature(dev, DRIVER_MODESET))
3906 dev_priv->fence_reg_start = 3;
de151cf6 3907
a6c45cf0 3908 if (INTEL_INFO(dev)->gen >= 4 || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
de151cf6
JB		 3909 dev_priv->num_fence_regs = 16;
3910 else
3911 dev_priv->num_fence_regs = 8;
3912
b5aa8a0f 3913 /* Initialize fence registers to zero */
ada726c7 3914 i915_gem_reset_fences(dev);
10ed13e4 3915
673a394b 3916 i915_gem_detect_bit_6_swizzle(dev);
6b95a207 3917 init_waitqueue_head(&dev_priv->pending_flip_queue);
17250b71 3918
ce453d81
CW		 3919 dev_priv->mm.interruptible = true;
3920
17250b71
CW		 3921 dev_priv->mm.inactive_shrinker.shrink = i915_gem_inactive_shrink;
3922 dev_priv->mm.inactive_shrinker.seeks = DEFAULT_SEEKS;
3923 register_shrinker(&dev_priv->mm.inactive_shrinker);
673a394b 3924}
71acb5eb
DA		 3925
3926/*
3927 * Create a physically contiguous memory object for this object
3928 * e.g. for cursor + overlay regs
3929 */
995b6762
CW		 3930static int i915_gem_init_phys_object(struct drm_device *dev,
3931 int id, int size, int align)
71acb5eb
DA		 3932{
3933 drm_i915_private_t *dev_priv = dev->dev_private;
3934 struct drm_i915_gem_phys_object *phys_obj;
3935 int ret;
3936
3937 if (dev_priv->mm.phys_objs[id - 1] || !size)
3938 return 0;
3939
9a298b2a 3940 phys_obj = kzalloc(sizeof(struct drm_i915_gem_phys_object), GFP_KERNEL);
71acb5eb
DA		 3941 if (!phys_obj)
3942 return -ENOMEM;
3943
3944 phys_obj->id = id;
3945
6eeefaf3 3946 phys_obj->handle = drm_pci_alloc(dev, size, align);
71acb5eb
DA		 3947 if (!phys_obj->handle) {
3948 ret = -ENOMEM;
3949 goto kfree_obj;
3950 }
3951#ifdef CONFIG_X86
3952 set_memory_wc((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE);
3953#endif
3954
3955 dev_priv->mm.phys_objs[id - 1] = phys_obj;
3956
3957 return 0;
3958kfree_obj:
9a298b2a 3959 kfree(phys_obj);
71acb5eb
DA		 3960 return ret;
3961}
3962
995b6762 3963static void i915_gem_free_phys_object(struct drm_device *dev, int id)
71acb5eb
DA		 3964{
3965 drm_i915_private_t *dev_priv = dev->dev_private;
3966 struct drm_i915_gem_phys_object *phys_obj;
3967
3968 if (!dev_priv->mm.phys_objs[id - 1])
3969 return;
3970
3971 phys_obj = dev_priv->mm.phys_objs[id - 1];
3972 if (phys_obj->cur_obj) {
3973 i915_gem_detach_phys_object(dev, phys_obj->cur_obj);
3974 }
3975
3976#ifdef CONFIG_X86
3977 set_memory_wb((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE);
3978#endif
3979 drm_pci_free(dev, phys_obj->handle);
3980 kfree(phys_obj);
3981 dev_priv->mm.phys_objs[id - 1] = NULL;
3982}
3983
3984void i915_gem_free_all_phys_object(struct drm_device *dev)
3985{
3986 int i;
3987
260883c8 3988 for (i = I915_GEM_PHYS_CURSOR_0; i <= I915_MAX_PHYS_OBJECT; i++)
71acb5eb
DA		 3989 i915_gem_free_phys_object(dev, i);
3990}
3991
3992void i915_gem_detach_phys_object(struct drm_device *dev,
05394f39 3993 struct drm_i915_gem_object *obj)
71acb5eb 3994{
05394f39 3995 struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping;
e5281ccd 3996 char *vaddr;
71acb5eb 3997 int i;
71acb5eb
DA		 3998 int page_count;
3999
05394f39 4000 if (!obj->phys_obj)
71acb5eb 4001 return;
05394f39 4002 vaddr = obj->phys_obj->handle->vaddr;
71acb5eb 4003
05394f39 4004 page_count = obj->base.size / PAGE_SIZE;
71acb5eb 4005 for (i = 0; i < page_count; i++) {
5949eac4 4006 struct page *page = shmem_read_mapping_page(mapping, i);
e5281ccd
CW		 4007 if (!IS_ERR(page)) {
4008 char *dst = kmap_atomic(page);
4009 memcpy(dst, vaddr + i*PAGE_SIZE, PAGE_SIZE);
4010 kunmap_atomic(dst);
4011
4012 drm_clflush_pages(&page, 1);
4013
4014 set_page_dirty(page);
4015 mark_page_accessed(page);
4016 page_cache_release(page);
4017 }
71acb5eb 4018 }
40ce6575 4019 intel_gtt_chipset_flush();
d78b47b9 4020
05394f39
CW		 4021 obj->phys_obj->cur_obj = NULL;
4022 obj->phys_obj = NULL;
71acb5eb
DA		 4023}
4024
4025int
4026i915_gem_attach_phys_object(struct drm_device *dev,
05394f39 4027 struct drm_i915_gem_object *obj,
6eeefaf3
CW		 4028 int id,
4029 int align)
71acb5eb 4030{
05394f39 4031 struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping;
71acb5eb 4032 drm_i915_private_t *dev_priv = dev->dev_private;
71acb5eb
DA		 4033 int ret = 0;
4034 int page_count;
4035 int i;
4036
4037 if (id > I915_MAX_PHYS_OBJECT)
4038 return -EINVAL;
4039
05394f39
CW		 4040 if (obj->phys_obj) {
4041 if (obj->phys_obj->id == id)
71acb5eb
DA		 4042 return 0;
4043 i915_gem_detach_phys_object(dev, obj);
4044 }
4045
71acb5eb
DA		 4046 /* create a new object */
4047 if (!dev_priv->mm.phys_objs[id - 1]) {
4048 ret = i915_gem_init_phys_object(dev, id,
05394f39 4049 obj->base.size, align);
71acb5eb 4050 if (ret) {
05394f39
CW		 4051 DRM_ERROR("failed to init phys object %d size: %zu\n",
4052 id, obj->base.size);
e5281ccd 4053 return ret;
71acb5eb
DA		 4054 }
4055 }
4056
4057 /* bind to the object */
05394f39
CW		 4058 obj->phys_obj = dev_priv->mm.phys_objs[id - 1];
4059 obj->phys_obj->cur_obj = obj;
71acb5eb 4060
05394f39 4061 page_count = obj->base.size / PAGE_SIZE;
71acb5eb
DA		 4062
4063 for (i = 0; i < page_count; i++) {
e5281ccd
CW		 4064 struct page *page;
4065 char *dst, *src;
4066
5949eac4 4067 page = shmem_read_mapping_page(mapping, i);
e5281ccd
CW		 4068 if (IS_ERR(page))
4069 return PTR_ERR(page);
71acb5eb 4070
ff75b9bc 4071 src = kmap_atomic(page);
05394f39 4072 dst = obj->phys_obj->handle->vaddr + (i * PAGE_SIZE);
71acb5eb 4073 memcpy(dst, src, PAGE_SIZE);
3e4d3af5 4074 kunmap_atomic(src);
71acb5eb 4075
e5281ccd
CW		 4076 mark_page_accessed(page);
4077 page_cache_release(page);
4078 }
d78b47b9 4079
71acb5eb 4080 return 0;
71acb5eb
DA		 4081}
4082
4083static int
05394f39
CW		 4084i915_gem_phys_pwrite(struct drm_device *dev,
4085 struct drm_i915_gem_object *obj,
71acb5eb
DA		 4086 struct drm_i915_gem_pwrite *args,
4087 struct drm_file *file_priv)
4088{
05394f39 4089 void *vaddr = obj->phys_obj->handle->vaddr + args->offset;
b47b30cc 4090 char __user *user_data = (char __user *) (uintptr_t) args->data_ptr;
71acb5eb 4091
b47b30cc
CW		 4092 if (__copy_from_user_inatomic_nocache(vaddr, user_data, args->size)) {
4093 unsigned long unwritten;
4094
4095 /* The physical object once assigned is fixed for the lifetime
4096 * of the obj, so we can safely drop the lock and continue
4097 * to access vaddr.
4098 */
4099 mutex_unlock(&dev->struct_mutex);
4100 unwritten = copy_from_user(vaddr, user_data, args->size);
4101 mutex_lock(&dev->struct_mutex);
4102 if (unwritten)
4103 return -EFAULT;
4104 }
71acb5eb 4105
40ce6575 4106 intel_gtt_chipset_flush();
71acb5eb
DA		 4107 return 0;
4108}
b962442e 4109
f787a5f5 4110void i915_gem_release(struct drm_device *dev, struct drm_file *file)
b962442e 4111{
f787a5f5 4112 struct drm_i915_file_private *file_priv = file->driver_priv;
b962442e
EA		 4113
4114 /* Clean up our request list when the client is going away, so that
4115 * later retire_requests won't dereference our soon-to-be-gone
4116 * file_priv.
4117 */
1c25595f 4118 spin_lock(&file_priv->mm.lock);
f787a5f5
CW		 4119 while (!list_empty(&file_priv->mm.request_list)) {
4120 struct drm_i915_gem_request *request;
4121
4122 request = list_first_entry(&file_priv->mm.request_list,
4123 struct drm_i915_gem_request,
4124 client_list);
4125 list_del(&request->client_list);
4126 request->file_priv = NULL;
4127 }
1c25595f 4128 spin_unlock(&file_priv->mm.lock);
b962442e 4129}
31169714 4130
1637ef41
CW		 4131static int
4132i915_gpu_is_active(struct drm_device *dev)
4133{
4134 drm_i915_private_t *dev_priv = dev->dev_private;
4135 int lists_empty;
4136
1637ef41 4137 lists_empty = list_empty(&dev_priv->mm.flushing_list) &&
17250b71 4138 list_empty(&dev_priv->mm.active_list);
1637ef41
CW		 4139
4140 return !lists_empty;
4141}
4142
31169714 4143static int
1495f230 4144i915_gem_inactive_shrink(struct shrinker *shrinker, struct shrink_control *sc)
31169714 4145{
17250b71
CW		 4146 struct drm_i915_private *dev_priv =
4147 container_of(shrinker,
4148 struct drm_i915_private,
4149 mm.inactive_shrinker);
4150 struct drm_device *dev = dev_priv->dev;
4151 struct drm_i915_gem_object *obj, *next;
1495f230 4152 int nr_to_scan = sc->nr_to_scan;
17250b71
CW		 4153 int cnt;
4154
4155 if (!mutex_trylock(&dev->struct_mutex))
bbe2e11a 4156 return 0;
31169714
CW		 4157
4158 /* "fast-path" to count number of available objects */
4159 if (nr_to_scan == 0) {
17250b71
CW		 4160 cnt = 0;
4161 list_for_each_entry(obj,
4162 &dev_priv->mm.inactive_list,
4163 mm_list)
4164 cnt++;
4165 mutex_unlock(&dev->struct_mutex);
4166 return cnt / 100 * sysctl_vfs_cache_pressure;
31169714
CW		 4167 }
4168
1637ef41 4169rescan:
31169714 4170 /* first scan for clean buffers */
17250b71 4171 i915_gem_retire_requests(dev);
31169714 4172
17250b71
CW		 4173 list_for_each_entry_safe(obj, next,
4174 &dev_priv->mm.inactive_list,
4175 mm_list) {
4176 if (i915_gem_object_is_purgeable(obj)) {
2021746e
CW		 4177 if (i915_gem_object_unbind(obj) == 0 &&
4178 --nr_to_scan == 0)
17250b71 4179 break;
31169714 4180 }
31169714
CW		 4181 }
4182
4183 /* second pass, evict/count anything still on the inactive list */
17250b71
CW		 4184 cnt = 0;
4185 list_for_each_entry_safe(obj, next,
4186 &dev_priv->mm.inactive_list,
4187 mm_list) {
2021746e
CW		 4188 if (nr_to_scan &&
4189 i915_gem_object_unbind(obj) == 0)
17250b71 4190 nr_to_scan--;
2021746e 4191 else
17250b71
CW		 4192 cnt++;
4193 }
4194
4195 if (nr_to_scan && i915_gpu_is_active(dev)) {
1637ef41
CW		 4196 /*
4197 * We are desperate for pages, so as a last resort, wait
4198 * for the GPU to finish and discard whatever we can.
4199 * This has a dramatic impact to reduce the number of
4200 * OOM-killer events whilst running the GPU aggressively.
4201 */
b2da9fe5 4202 if (i915_gpu_idle(dev) == 0)
1637ef41
CW		 4203 goto rescan;
4204 }
17250b71
CW		 4205 mutex_unlock(&dev->struct_mutex);
4206 return cnt / 100 * sysctl_vfs_cache_pressure;
31169714 4207}
Linux kernel - Deliverables
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