Commit | Line | Data |
---|---|---|
673a394b EA |
1 | /* |
2 | * Copyright © 2008 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | * | |
26 | */ | |
27 | ||
28 | #include "drmP.h" | |
29 | #include "drm.h" | |
30 | #include "i915_drm.h" | |
31 | #include "i915_drv.h" | |
1c5d22f7 | 32 | #include "i915_trace.h" |
652c393a | 33 | #include "intel_drv.h" |
5949eac4 | 34 | #include <linux/shmem_fs.h> |
5a0e3ad6 | 35 | #include <linux/slab.h> |
673a394b | 36 | #include <linux/swap.h> |
79e53945 | 37 | #include <linux/pci.h> |
1286ff73 | 38 | #include <linux/dma-buf.h> |
673a394b | 39 | |
05394f39 CW |
40 | static void i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj); |
41 | static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj); | |
88241785 CW |
42 | static __must_check int i915_gem_object_bind_to_gtt(struct drm_i915_gem_object *obj, |
43 | unsigned alignment, | |
86a1ee26 CW |
44 | bool map_and_fenceable, |
45 | bool nonblocking); | |
05394f39 CW |
46 | static int i915_gem_phys_pwrite(struct drm_device *dev, |
47 | struct drm_i915_gem_object *obj, | |
71acb5eb | 48 | struct drm_i915_gem_pwrite *args, |
05394f39 | 49 | struct drm_file *file); |
673a394b | 50 | |
61050808 CW |
51 | static void i915_gem_write_fence(struct drm_device *dev, int reg, |
52 | struct drm_i915_gem_object *obj); | |
53 | static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj, | |
54 | struct drm_i915_fence_reg *fence, | |
55 | bool enable); | |
56 | ||
17250b71 | 57 | static int i915_gem_inactive_shrink(struct shrinker *shrinker, |
1495f230 | 58 | struct shrink_control *sc); |
6c085a72 CW |
59 | static long i915_gem_purge(struct drm_i915_private *dev_priv, long target); |
60 | static void i915_gem_shrink_all(struct drm_i915_private *dev_priv); | |
8c59967c | 61 | static void i915_gem_object_truncate(struct drm_i915_gem_object *obj); |
31169714 | 62 | |
61050808 CW |
63 | static inline void i915_gem_object_fence_lost(struct drm_i915_gem_object *obj) |
64 | { | |
65 | if (obj->tiling_mode) | |
66 | i915_gem_release_mmap(obj); | |
67 | ||
68 | /* As we do not have an associated fence register, we will force | |
69 | * a tiling change if we ever need to acquire one. | |
70 | */ | |
5d82e3e6 | 71 | obj->fence_dirty = false; |
61050808 CW |
72 | obj->fence_reg = I915_FENCE_REG_NONE; |
73 | } | |
74 | ||
73aa808f CW |
75 | /* some bookkeeping */ |
76 | static void i915_gem_info_add_obj(struct drm_i915_private *dev_priv, | |
77 | size_t size) | |
78 | { | |
79 | dev_priv->mm.object_count++; | |
80 | dev_priv->mm.object_memory += size; | |
81 | } | |
82 | ||
83 | static void i915_gem_info_remove_obj(struct drm_i915_private *dev_priv, | |
84 | size_t size) | |
85 | { | |
86 | dev_priv->mm.object_count--; | |
87 | dev_priv->mm.object_memory -= size; | |
88 | } | |
89 | ||
21dd3734 CW |
90 | static int |
91 | i915_gem_wait_for_error(struct drm_device *dev) | |
30dbf0c0 CW |
92 | { |
93 | struct drm_i915_private *dev_priv = dev->dev_private; | |
94 | struct completion *x = &dev_priv->error_completion; | |
95 | unsigned long flags; | |
96 | int ret; | |
97 | ||
98 | if (!atomic_read(&dev_priv->mm.wedged)) | |
99 | return 0; | |
100 | ||
0a6759c6 DV |
101 | /* |
102 | * Only wait 10 seconds for the gpu reset to complete to avoid hanging | |
103 | * userspace. If it takes that long something really bad is going on and | |
104 | * we should simply try to bail out and fail as gracefully as possible. | |
105 | */ | |
106 | ret = wait_for_completion_interruptible_timeout(x, 10*HZ); | |
107 | if (ret == 0) { | |
108 | DRM_ERROR("Timed out waiting for the gpu reset to complete\n"); | |
109 | return -EIO; | |
110 | } else if (ret < 0) { | |
30dbf0c0 | 111 | return ret; |
0a6759c6 | 112 | } |
30dbf0c0 | 113 | |
21dd3734 CW |
114 | if (atomic_read(&dev_priv->mm.wedged)) { |
115 | /* GPU is hung, bump the completion count to account for | |
116 | * the token we just consumed so that we never hit zero and | |
117 | * end up waiting upon a subsequent completion event that | |
118 | * will never happen. | |
119 | */ | |
120 | spin_lock_irqsave(&x->wait.lock, flags); | |
121 | x->done++; | |
122 | spin_unlock_irqrestore(&x->wait.lock, flags); | |
123 | } | |
124 | return 0; | |
30dbf0c0 CW |
125 | } |
126 | ||
54cf91dc | 127 | int i915_mutex_lock_interruptible(struct drm_device *dev) |
76c1dec1 | 128 | { |
76c1dec1 CW |
129 | int ret; |
130 | ||
21dd3734 | 131 | ret = i915_gem_wait_for_error(dev); |
76c1dec1 CW |
132 | if (ret) |
133 | return ret; | |
134 | ||
135 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
136 | if (ret) | |
137 | return ret; | |
138 | ||
23bc5982 | 139 | WARN_ON(i915_verify_lists(dev)); |
76c1dec1 CW |
140 | return 0; |
141 | } | |
30dbf0c0 | 142 | |
7d1c4804 | 143 | static inline bool |
05394f39 | 144 | i915_gem_object_is_inactive(struct drm_i915_gem_object *obj) |
7d1c4804 | 145 | { |
6c085a72 | 146 | return obj->gtt_space && !obj->active; |
7d1c4804 CW |
147 | } |
148 | ||
79e53945 JB |
149 | int |
150 | i915_gem_init_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 151 | struct drm_file *file) |
79e53945 JB |
152 | { |
153 | struct drm_i915_gem_init *args = data; | |
2021746e | 154 | |
7bb6fb8d DV |
155 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
156 | return -ENODEV; | |
157 | ||
2021746e CW |
158 | if (args->gtt_start >= args->gtt_end || |
159 | (args->gtt_end | args->gtt_start) & (PAGE_SIZE - 1)) | |
160 | return -EINVAL; | |
79e53945 | 161 | |
f534bc0b DV |
162 | /* GEM with user mode setting was never supported on ilk and later. */ |
163 | if (INTEL_INFO(dev)->gen >= 5) | |
164 | return -ENODEV; | |
165 | ||
79e53945 | 166 | mutex_lock(&dev->struct_mutex); |
644ec02b DV |
167 | i915_gem_init_global_gtt(dev, args->gtt_start, |
168 | args->gtt_end, args->gtt_end); | |
673a394b EA |
169 | mutex_unlock(&dev->struct_mutex); |
170 | ||
2021746e | 171 | return 0; |
673a394b EA |
172 | } |
173 | ||
5a125c3c EA |
174 | int |
175 | i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 176 | struct drm_file *file) |
5a125c3c | 177 | { |
73aa808f | 178 | struct drm_i915_private *dev_priv = dev->dev_private; |
5a125c3c | 179 | struct drm_i915_gem_get_aperture *args = data; |
6299f992 CW |
180 | struct drm_i915_gem_object *obj; |
181 | size_t pinned; | |
5a125c3c | 182 | |
6299f992 | 183 | pinned = 0; |
73aa808f | 184 | mutex_lock(&dev->struct_mutex); |
6c085a72 | 185 | list_for_each_entry(obj, &dev_priv->mm.bound_list, gtt_list) |
1b50247a CW |
186 | if (obj->pin_count) |
187 | pinned += obj->gtt_space->size; | |
73aa808f | 188 | mutex_unlock(&dev->struct_mutex); |
5a125c3c | 189 | |
6299f992 | 190 | args->aper_size = dev_priv->mm.gtt_total; |
0206e353 | 191 | args->aper_available_size = args->aper_size - pinned; |
6299f992 | 192 | |
5a125c3c EA |
193 | return 0; |
194 | } | |
195 | ||
ff72145b DA |
196 | static int |
197 | i915_gem_create(struct drm_file *file, | |
198 | struct drm_device *dev, | |
199 | uint64_t size, | |
200 | uint32_t *handle_p) | |
673a394b | 201 | { |
05394f39 | 202 | struct drm_i915_gem_object *obj; |
a1a2d1d3 PP |
203 | int ret; |
204 | u32 handle; | |
673a394b | 205 | |
ff72145b | 206 | size = roundup(size, PAGE_SIZE); |
8ffc0246 CW |
207 | if (size == 0) |
208 | return -EINVAL; | |
673a394b EA |
209 | |
210 | /* Allocate the new object */ | |
ff72145b | 211 | obj = i915_gem_alloc_object(dev, size); |
673a394b EA |
212 | if (obj == NULL) |
213 | return -ENOMEM; | |
214 | ||
05394f39 | 215 | ret = drm_gem_handle_create(file, &obj->base, &handle); |
1dfd9754 | 216 | if (ret) { |
05394f39 CW |
217 | drm_gem_object_release(&obj->base); |
218 | i915_gem_info_remove_obj(dev->dev_private, obj->base.size); | |
202f2fef | 219 | kfree(obj); |
673a394b | 220 | return ret; |
1dfd9754 | 221 | } |
673a394b | 222 | |
202f2fef | 223 | /* drop reference from allocate - handle holds it now */ |
05394f39 | 224 | drm_gem_object_unreference(&obj->base); |
202f2fef CW |
225 | trace_i915_gem_object_create(obj); |
226 | ||
ff72145b | 227 | *handle_p = handle; |
673a394b EA |
228 | return 0; |
229 | } | |
230 | ||
ff72145b DA |
231 | int |
232 | i915_gem_dumb_create(struct drm_file *file, | |
233 | struct drm_device *dev, | |
234 | struct drm_mode_create_dumb *args) | |
235 | { | |
236 | /* have to work out size/pitch and return them */ | |
ed0291fd | 237 | args->pitch = ALIGN(args->width * ((args->bpp + 7) / 8), 64); |
ff72145b DA |
238 | args->size = args->pitch * args->height; |
239 | return i915_gem_create(file, dev, | |
240 | args->size, &args->handle); | |
241 | } | |
242 | ||
243 | int i915_gem_dumb_destroy(struct drm_file *file, | |
244 | struct drm_device *dev, | |
245 | uint32_t handle) | |
246 | { | |
247 | return drm_gem_handle_delete(file, handle); | |
248 | } | |
249 | ||
250 | /** | |
251 | * Creates a new mm object and returns a handle to it. | |
252 | */ | |
253 | int | |
254 | i915_gem_create_ioctl(struct drm_device *dev, void *data, | |
255 | struct drm_file *file) | |
256 | { | |
257 | struct drm_i915_gem_create *args = data; | |
63ed2cb2 | 258 | |
ff72145b DA |
259 | return i915_gem_create(file, dev, |
260 | args->size, &args->handle); | |
261 | } | |
262 | ||
05394f39 | 263 | static int i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj) |
280b713b | 264 | { |
05394f39 | 265 | drm_i915_private_t *dev_priv = obj->base.dev->dev_private; |
280b713b EA |
266 | |
267 | return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 && | |
05394f39 | 268 | obj->tiling_mode != I915_TILING_NONE; |
280b713b EA |
269 | } |
270 | ||
8461d226 DV |
271 | static inline int |
272 | __copy_to_user_swizzled(char __user *cpu_vaddr, | |
273 | const char *gpu_vaddr, int gpu_offset, | |
274 | int length) | |
275 | { | |
276 | int ret, cpu_offset = 0; | |
277 | ||
278 | while (length > 0) { | |
279 | int cacheline_end = ALIGN(gpu_offset + 1, 64); | |
280 | int this_length = min(cacheline_end - gpu_offset, length); | |
281 | int swizzled_gpu_offset = gpu_offset ^ 64; | |
282 | ||
283 | ret = __copy_to_user(cpu_vaddr + cpu_offset, | |
284 | gpu_vaddr + swizzled_gpu_offset, | |
285 | this_length); | |
286 | if (ret) | |
287 | return ret + length; | |
288 | ||
289 | cpu_offset += this_length; | |
290 | gpu_offset += this_length; | |
291 | length -= this_length; | |
292 | } | |
293 | ||
294 | return 0; | |
295 | } | |
296 | ||
8c59967c | 297 | static inline int |
4f0c7cfb BW |
298 | __copy_from_user_swizzled(char *gpu_vaddr, int gpu_offset, |
299 | const char __user *cpu_vaddr, | |
8c59967c DV |
300 | int length) |
301 | { | |
302 | int ret, cpu_offset = 0; | |
303 | ||
304 | while (length > 0) { | |
305 | int cacheline_end = ALIGN(gpu_offset + 1, 64); | |
306 | int this_length = min(cacheline_end - gpu_offset, length); | |
307 | int swizzled_gpu_offset = gpu_offset ^ 64; | |
308 | ||
309 | ret = __copy_from_user(gpu_vaddr + swizzled_gpu_offset, | |
310 | cpu_vaddr + cpu_offset, | |
311 | this_length); | |
312 | if (ret) | |
313 | return ret + length; | |
314 | ||
315 | cpu_offset += this_length; | |
316 | gpu_offset += this_length; | |
317 | length -= this_length; | |
318 | } | |
319 | ||
320 | return 0; | |
321 | } | |
322 | ||
d174bd64 DV |
323 | /* Per-page copy function for the shmem pread fastpath. |
324 | * Flushes invalid cachelines before reading the target if | |
325 | * needs_clflush is set. */ | |
eb01459f | 326 | static int |
d174bd64 DV |
327 | shmem_pread_fast(struct page *page, int shmem_page_offset, int page_length, |
328 | char __user *user_data, | |
329 | bool page_do_bit17_swizzling, bool needs_clflush) | |
330 | { | |
331 | char *vaddr; | |
332 | int ret; | |
333 | ||
e7e58eb5 | 334 | if (unlikely(page_do_bit17_swizzling)) |
d174bd64 DV |
335 | return -EINVAL; |
336 | ||
337 | vaddr = kmap_atomic(page); | |
338 | if (needs_clflush) | |
339 | drm_clflush_virt_range(vaddr + shmem_page_offset, | |
340 | page_length); | |
341 | ret = __copy_to_user_inatomic(user_data, | |
342 | vaddr + shmem_page_offset, | |
343 | page_length); | |
344 | kunmap_atomic(vaddr); | |
345 | ||
346 | return ret; | |
347 | } | |
348 | ||
23c18c71 DV |
349 | static void |
350 | shmem_clflush_swizzled_range(char *addr, unsigned long length, | |
351 | bool swizzled) | |
352 | { | |
e7e58eb5 | 353 | if (unlikely(swizzled)) { |
23c18c71 DV |
354 | unsigned long start = (unsigned long) addr; |
355 | unsigned long end = (unsigned long) addr + length; | |
356 | ||
357 | /* For swizzling simply ensure that we always flush both | |
358 | * channels. Lame, but simple and it works. Swizzled | |
359 | * pwrite/pread is far from a hotpath - current userspace | |
360 | * doesn't use it at all. */ | |
361 | start = round_down(start, 128); | |
362 | end = round_up(end, 128); | |
363 | ||
364 | drm_clflush_virt_range((void *)start, end - start); | |
365 | } else { | |
366 | drm_clflush_virt_range(addr, length); | |
367 | } | |
368 | ||
369 | } | |
370 | ||
d174bd64 DV |
371 | /* Only difference to the fast-path function is that this can handle bit17 |
372 | * and uses non-atomic copy and kmap functions. */ | |
373 | static int | |
374 | shmem_pread_slow(struct page *page, int shmem_page_offset, int page_length, | |
375 | char __user *user_data, | |
376 | bool page_do_bit17_swizzling, bool needs_clflush) | |
377 | { | |
378 | char *vaddr; | |
379 | int ret; | |
380 | ||
381 | vaddr = kmap(page); | |
382 | if (needs_clflush) | |
23c18c71 DV |
383 | shmem_clflush_swizzled_range(vaddr + shmem_page_offset, |
384 | page_length, | |
385 | page_do_bit17_swizzling); | |
d174bd64 DV |
386 | |
387 | if (page_do_bit17_swizzling) | |
388 | ret = __copy_to_user_swizzled(user_data, | |
389 | vaddr, shmem_page_offset, | |
390 | page_length); | |
391 | else | |
392 | ret = __copy_to_user(user_data, | |
393 | vaddr + shmem_page_offset, | |
394 | page_length); | |
395 | kunmap(page); | |
396 | ||
397 | return ret; | |
398 | } | |
399 | ||
eb01459f | 400 | static int |
dbf7bff0 DV |
401 | i915_gem_shmem_pread(struct drm_device *dev, |
402 | struct drm_i915_gem_object *obj, | |
403 | struct drm_i915_gem_pread *args, | |
404 | struct drm_file *file) | |
eb01459f | 405 | { |
05394f39 | 406 | struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping; |
8461d226 | 407 | char __user *user_data; |
eb01459f | 408 | ssize_t remain; |
8461d226 | 409 | loff_t offset; |
eb2c0c81 | 410 | int shmem_page_offset, page_length, ret = 0; |
8461d226 | 411 | int obj_do_bit17_swizzling, page_do_bit17_swizzling; |
dbf7bff0 | 412 | int hit_slowpath = 0; |
96d79b52 | 413 | int prefaulted = 0; |
8489731c | 414 | int needs_clflush = 0; |
692a576b | 415 | int release_page; |
eb01459f | 416 | |
8461d226 | 417 | user_data = (char __user *) (uintptr_t) args->data_ptr; |
eb01459f EA |
418 | remain = args->size; |
419 | ||
8461d226 | 420 | obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj); |
eb01459f | 421 | |
8489731c DV |
422 | if (!(obj->base.read_domains & I915_GEM_DOMAIN_CPU)) { |
423 | /* If we're not in the cpu read domain, set ourself into the gtt | |
424 | * read domain and manually flush cachelines (if required). This | |
425 | * optimizes for the case when the gpu will dirty the data | |
426 | * anyway again before the next pread happens. */ | |
427 | if (obj->cache_level == I915_CACHE_NONE) | |
428 | needs_clflush = 1; | |
6c085a72 CW |
429 | if (obj->gtt_space) { |
430 | ret = i915_gem_object_set_to_gtt_domain(obj, false); | |
431 | if (ret) | |
432 | return ret; | |
433 | } | |
8489731c | 434 | } |
eb01459f | 435 | |
8461d226 | 436 | offset = args->offset; |
eb01459f EA |
437 | |
438 | while (remain > 0) { | |
e5281ccd CW |
439 | struct page *page; |
440 | ||
eb01459f EA |
441 | /* Operation in this page |
442 | * | |
eb01459f | 443 | * shmem_page_offset = offset within page in shmem file |
eb01459f EA |
444 | * page_length = bytes to copy for this page |
445 | */ | |
c8cbbb8b | 446 | shmem_page_offset = offset_in_page(offset); |
eb01459f EA |
447 | page_length = remain; |
448 | if ((shmem_page_offset + page_length) > PAGE_SIZE) | |
449 | page_length = PAGE_SIZE - shmem_page_offset; | |
eb01459f | 450 | |
692a576b DV |
451 | if (obj->pages) { |
452 | page = obj->pages[offset >> PAGE_SHIFT]; | |
453 | release_page = 0; | |
454 | } else { | |
455 | page = shmem_read_mapping_page(mapping, offset >> PAGE_SHIFT); | |
456 | if (IS_ERR(page)) { | |
457 | ret = PTR_ERR(page); | |
458 | goto out; | |
459 | } | |
460 | release_page = 1; | |
b65552f0 | 461 | } |
e5281ccd | 462 | |
8461d226 DV |
463 | page_do_bit17_swizzling = obj_do_bit17_swizzling && |
464 | (page_to_phys(page) & (1 << 17)) != 0; | |
465 | ||
d174bd64 DV |
466 | ret = shmem_pread_fast(page, shmem_page_offset, page_length, |
467 | user_data, page_do_bit17_swizzling, | |
468 | needs_clflush); | |
469 | if (ret == 0) | |
470 | goto next_page; | |
dbf7bff0 DV |
471 | |
472 | hit_slowpath = 1; | |
692a576b | 473 | page_cache_get(page); |
dbf7bff0 DV |
474 | mutex_unlock(&dev->struct_mutex); |
475 | ||
96d79b52 | 476 | if (!prefaulted) { |
f56f821f | 477 | ret = fault_in_multipages_writeable(user_data, remain); |
96d79b52 DV |
478 | /* Userspace is tricking us, but we've already clobbered |
479 | * its pages with the prefault and promised to write the | |
480 | * data up to the first fault. Hence ignore any errors | |
481 | * and just continue. */ | |
482 | (void)ret; | |
483 | prefaulted = 1; | |
484 | } | |
eb01459f | 485 | |
d174bd64 DV |
486 | ret = shmem_pread_slow(page, shmem_page_offset, page_length, |
487 | user_data, page_do_bit17_swizzling, | |
488 | needs_clflush); | |
eb01459f | 489 | |
dbf7bff0 | 490 | mutex_lock(&dev->struct_mutex); |
e5281ccd | 491 | page_cache_release(page); |
dbf7bff0 | 492 | next_page: |
e5281ccd | 493 | mark_page_accessed(page); |
692a576b DV |
494 | if (release_page) |
495 | page_cache_release(page); | |
e5281ccd | 496 | |
8461d226 DV |
497 | if (ret) { |
498 | ret = -EFAULT; | |
499 | goto out; | |
500 | } | |
501 | ||
eb01459f | 502 | remain -= page_length; |
8461d226 | 503 | user_data += page_length; |
eb01459f EA |
504 | offset += page_length; |
505 | } | |
506 | ||
4f27b75d | 507 | out: |
dbf7bff0 DV |
508 | if (hit_slowpath) { |
509 | /* Fixup: Kill any reinstated backing storage pages */ | |
510 | if (obj->madv == __I915_MADV_PURGED) | |
511 | i915_gem_object_truncate(obj); | |
512 | } | |
eb01459f EA |
513 | |
514 | return ret; | |
515 | } | |
516 | ||
673a394b EA |
517 | /** |
518 | * Reads data from the object referenced by handle. | |
519 | * | |
520 | * On error, the contents of *data are undefined. | |
521 | */ | |
522 | int | |
523 | i915_gem_pread_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 524 | struct drm_file *file) |
673a394b EA |
525 | { |
526 | struct drm_i915_gem_pread *args = data; | |
05394f39 | 527 | struct drm_i915_gem_object *obj; |
35b62a89 | 528 | int ret = 0; |
673a394b | 529 | |
51311d0a CW |
530 | if (args->size == 0) |
531 | return 0; | |
532 | ||
533 | if (!access_ok(VERIFY_WRITE, | |
534 | (char __user *)(uintptr_t)args->data_ptr, | |
535 | args->size)) | |
536 | return -EFAULT; | |
537 | ||
4f27b75d | 538 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 539 | if (ret) |
4f27b75d | 540 | return ret; |
673a394b | 541 | |
05394f39 | 542 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 543 | if (&obj->base == NULL) { |
1d7cfea1 CW |
544 | ret = -ENOENT; |
545 | goto unlock; | |
4f27b75d | 546 | } |
673a394b | 547 | |
7dcd2499 | 548 | /* Bounds check source. */ |
05394f39 CW |
549 | if (args->offset > obj->base.size || |
550 | args->size > obj->base.size - args->offset) { | |
ce9d419d | 551 | ret = -EINVAL; |
35b62a89 | 552 | goto out; |
ce9d419d CW |
553 | } |
554 | ||
1286ff73 DV |
555 | /* prime objects have no backing filp to GEM pread/pwrite |
556 | * pages from. | |
557 | */ | |
558 | if (!obj->base.filp) { | |
559 | ret = -EINVAL; | |
560 | goto out; | |
561 | } | |
562 | ||
db53a302 CW |
563 | trace_i915_gem_object_pread(obj, args->offset, args->size); |
564 | ||
dbf7bff0 | 565 | ret = i915_gem_shmem_pread(dev, obj, args, file); |
673a394b | 566 | |
35b62a89 | 567 | out: |
05394f39 | 568 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 569 | unlock: |
4f27b75d | 570 | mutex_unlock(&dev->struct_mutex); |
eb01459f | 571 | return ret; |
673a394b EA |
572 | } |
573 | ||
0839ccb8 KP |
574 | /* This is the fast write path which cannot handle |
575 | * page faults in the source data | |
9b7530cc | 576 | */ |
0839ccb8 KP |
577 | |
578 | static inline int | |
579 | fast_user_write(struct io_mapping *mapping, | |
580 | loff_t page_base, int page_offset, | |
581 | char __user *user_data, | |
582 | int length) | |
9b7530cc | 583 | { |
4f0c7cfb BW |
584 | void __iomem *vaddr_atomic; |
585 | void *vaddr; | |
0839ccb8 | 586 | unsigned long unwritten; |
9b7530cc | 587 | |
3e4d3af5 | 588 | vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base); |
4f0c7cfb BW |
589 | /* We can use the cpu mem copy function because this is X86. */ |
590 | vaddr = (void __force*)vaddr_atomic + page_offset; | |
591 | unwritten = __copy_from_user_inatomic_nocache(vaddr, | |
0839ccb8 | 592 | user_data, length); |
3e4d3af5 | 593 | io_mapping_unmap_atomic(vaddr_atomic); |
fbd5a26d | 594 | return unwritten; |
0839ccb8 KP |
595 | } |
596 | ||
3de09aa3 EA |
597 | /** |
598 | * This is the fast pwrite path, where we copy the data directly from the | |
599 | * user into the GTT, uncached. | |
600 | */ | |
673a394b | 601 | static int |
05394f39 CW |
602 | i915_gem_gtt_pwrite_fast(struct drm_device *dev, |
603 | struct drm_i915_gem_object *obj, | |
3de09aa3 | 604 | struct drm_i915_gem_pwrite *args, |
05394f39 | 605 | struct drm_file *file) |
673a394b | 606 | { |
0839ccb8 | 607 | drm_i915_private_t *dev_priv = dev->dev_private; |
673a394b | 608 | ssize_t remain; |
0839ccb8 | 609 | loff_t offset, page_base; |
673a394b | 610 | char __user *user_data; |
935aaa69 DV |
611 | int page_offset, page_length, ret; |
612 | ||
86a1ee26 | 613 | ret = i915_gem_object_pin(obj, 0, true, true); |
935aaa69 DV |
614 | if (ret) |
615 | goto out; | |
616 | ||
617 | ret = i915_gem_object_set_to_gtt_domain(obj, true); | |
618 | if (ret) | |
619 | goto out_unpin; | |
620 | ||
621 | ret = i915_gem_object_put_fence(obj); | |
622 | if (ret) | |
623 | goto out_unpin; | |
673a394b EA |
624 | |
625 | user_data = (char __user *) (uintptr_t) args->data_ptr; | |
626 | remain = args->size; | |
673a394b | 627 | |
05394f39 | 628 | offset = obj->gtt_offset + args->offset; |
673a394b EA |
629 | |
630 | while (remain > 0) { | |
631 | /* Operation in this page | |
632 | * | |
0839ccb8 KP |
633 | * page_base = page offset within aperture |
634 | * page_offset = offset within page | |
635 | * page_length = bytes to copy for this page | |
673a394b | 636 | */ |
c8cbbb8b CW |
637 | page_base = offset & PAGE_MASK; |
638 | page_offset = offset_in_page(offset); | |
0839ccb8 KP |
639 | page_length = remain; |
640 | if ((page_offset + remain) > PAGE_SIZE) | |
641 | page_length = PAGE_SIZE - page_offset; | |
642 | ||
0839ccb8 | 643 | /* If we get a fault while copying data, then (presumably) our |
3de09aa3 EA |
644 | * source page isn't available. Return the error and we'll |
645 | * retry in the slow path. | |
0839ccb8 | 646 | */ |
fbd5a26d | 647 | if (fast_user_write(dev_priv->mm.gtt_mapping, page_base, |
935aaa69 DV |
648 | page_offset, user_data, page_length)) { |
649 | ret = -EFAULT; | |
650 | goto out_unpin; | |
651 | } | |
673a394b | 652 | |
0839ccb8 KP |
653 | remain -= page_length; |
654 | user_data += page_length; | |
655 | offset += page_length; | |
673a394b | 656 | } |
673a394b | 657 | |
935aaa69 DV |
658 | out_unpin: |
659 | i915_gem_object_unpin(obj); | |
660 | out: | |
3de09aa3 | 661 | return ret; |
673a394b EA |
662 | } |
663 | ||
d174bd64 DV |
664 | /* Per-page copy function for the shmem pwrite fastpath. |
665 | * Flushes invalid cachelines before writing to the target if | |
666 | * needs_clflush_before is set and flushes out any written cachelines after | |
667 | * writing if needs_clflush is set. */ | |
3043c60c | 668 | static int |
d174bd64 DV |
669 | shmem_pwrite_fast(struct page *page, int shmem_page_offset, int page_length, |
670 | char __user *user_data, | |
671 | bool page_do_bit17_swizzling, | |
672 | bool needs_clflush_before, | |
673 | bool needs_clflush_after) | |
673a394b | 674 | { |
d174bd64 | 675 | char *vaddr; |
673a394b | 676 | int ret; |
3de09aa3 | 677 | |
e7e58eb5 | 678 | if (unlikely(page_do_bit17_swizzling)) |
d174bd64 | 679 | return -EINVAL; |
3de09aa3 | 680 | |
d174bd64 DV |
681 | vaddr = kmap_atomic(page); |
682 | if (needs_clflush_before) | |
683 | drm_clflush_virt_range(vaddr + shmem_page_offset, | |
684 | page_length); | |
685 | ret = __copy_from_user_inatomic_nocache(vaddr + shmem_page_offset, | |
686 | user_data, | |
687 | page_length); | |
688 | if (needs_clflush_after) | |
689 | drm_clflush_virt_range(vaddr + shmem_page_offset, | |
690 | page_length); | |
691 | kunmap_atomic(vaddr); | |
3de09aa3 EA |
692 | |
693 | return ret; | |
694 | } | |
695 | ||
d174bd64 DV |
696 | /* Only difference to the fast-path function is that this can handle bit17 |
697 | * and uses non-atomic copy and kmap functions. */ | |
3043c60c | 698 | static int |
d174bd64 DV |
699 | shmem_pwrite_slow(struct page *page, int shmem_page_offset, int page_length, |
700 | char __user *user_data, | |
701 | bool page_do_bit17_swizzling, | |
702 | bool needs_clflush_before, | |
703 | bool needs_clflush_after) | |
673a394b | 704 | { |
d174bd64 DV |
705 | char *vaddr; |
706 | int ret; | |
e5281ccd | 707 | |
d174bd64 | 708 | vaddr = kmap(page); |
e7e58eb5 | 709 | if (unlikely(needs_clflush_before || page_do_bit17_swizzling)) |
23c18c71 DV |
710 | shmem_clflush_swizzled_range(vaddr + shmem_page_offset, |
711 | page_length, | |
712 | page_do_bit17_swizzling); | |
d174bd64 DV |
713 | if (page_do_bit17_swizzling) |
714 | ret = __copy_from_user_swizzled(vaddr, shmem_page_offset, | |
e5281ccd CW |
715 | user_data, |
716 | page_length); | |
d174bd64 DV |
717 | else |
718 | ret = __copy_from_user(vaddr + shmem_page_offset, | |
719 | user_data, | |
720 | page_length); | |
721 | if (needs_clflush_after) | |
23c18c71 DV |
722 | shmem_clflush_swizzled_range(vaddr + shmem_page_offset, |
723 | page_length, | |
724 | page_do_bit17_swizzling); | |
d174bd64 | 725 | kunmap(page); |
40123c1f | 726 | |
d174bd64 | 727 | return ret; |
40123c1f EA |
728 | } |
729 | ||
40123c1f | 730 | static int |
e244a443 DV |
731 | i915_gem_shmem_pwrite(struct drm_device *dev, |
732 | struct drm_i915_gem_object *obj, | |
733 | struct drm_i915_gem_pwrite *args, | |
734 | struct drm_file *file) | |
40123c1f | 735 | { |
05394f39 | 736 | struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping; |
40123c1f | 737 | ssize_t remain; |
8c59967c DV |
738 | loff_t offset; |
739 | char __user *user_data; | |
eb2c0c81 | 740 | int shmem_page_offset, page_length, ret = 0; |
8c59967c | 741 | int obj_do_bit17_swizzling, page_do_bit17_swizzling; |
e244a443 | 742 | int hit_slowpath = 0; |
58642885 DV |
743 | int needs_clflush_after = 0; |
744 | int needs_clflush_before = 0; | |
692a576b | 745 | int release_page; |
40123c1f | 746 | |
8c59967c | 747 | user_data = (char __user *) (uintptr_t) args->data_ptr; |
40123c1f EA |
748 | remain = args->size; |
749 | ||
8c59967c | 750 | obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj); |
40123c1f | 751 | |
58642885 DV |
752 | if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) { |
753 | /* If we're not in the cpu write domain, set ourself into the gtt | |
754 | * write domain and manually flush cachelines (if required). This | |
755 | * optimizes for the case when the gpu will use the data | |
756 | * right away and we therefore have to clflush anyway. */ | |
757 | if (obj->cache_level == I915_CACHE_NONE) | |
758 | needs_clflush_after = 1; | |
6c085a72 CW |
759 | if (obj->gtt_space) { |
760 | ret = i915_gem_object_set_to_gtt_domain(obj, true); | |
761 | if (ret) | |
762 | return ret; | |
763 | } | |
58642885 DV |
764 | } |
765 | /* Same trick applies for invalidate partially written cachelines before | |
766 | * writing. */ | |
767 | if (!(obj->base.read_domains & I915_GEM_DOMAIN_CPU) | |
768 | && obj->cache_level == I915_CACHE_NONE) | |
769 | needs_clflush_before = 1; | |
770 | ||
673a394b | 771 | offset = args->offset; |
05394f39 | 772 | obj->dirty = 1; |
673a394b | 773 | |
40123c1f | 774 | while (remain > 0) { |
e5281ccd | 775 | struct page *page; |
58642885 | 776 | int partial_cacheline_write; |
e5281ccd | 777 | |
40123c1f EA |
778 | /* Operation in this page |
779 | * | |
40123c1f | 780 | * shmem_page_offset = offset within page in shmem file |
40123c1f EA |
781 | * page_length = bytes to copy for this page |
782 | */ | |
c8cbbb8b | 783 | shmem_page_offset = offset_in_page(offset); |
40123c1f EA |
784 | |
785 | page_length = remain; | |
786 | if ((shmem_page_offset + page_length) > PAGE_SIZE) | |
787 | page_length = PAGE_SIZE - shmem_page_offset; | |
40123c1f | 788 | |
58642885 DV |
789 | /* If we don't overwrite a cacheline completely we need to be |
790 | * careful to have up-to-date data by first clflushing. Don't | |
791 | * overcomplicate things and flush the entire patch. */ | |
792 | partial_cacheline_write = needs_clflush_before && | |
793 | ((shmem_page_offset | page_length) | |
794 | & (boot_cpu_data.x86_clflush_size - 1)); | |
795 | ||
692a576b DV |
796 | if (obj->pages) { |
797 | page = obj->pages[offset >> PAGE_SHIFT]; | |
798 | release_page = 0; | |
799 | } else { | |
800 | page = shmem_read_mapping_page(mapping, offset >> PAGE_SHIFT); | |
801 | if (IS_ERR(page)) { | |
802 | ret = PTR_ERR(page); | |
803 | goto out; | |
804 | } | |
805 | release_page = 1; | |
e5281ccd CW |
806 | } |
807 | ||
8c59967c DV |
808 | page_do_bit17_swizzling = obj_do_bit17_swizzling && |
809 | (page_to_phys(page) & (1 << 17)) != 0; | |
810 | ||
d174bd64 DV |
811 | ret = shmem_pwrite_fast(page, shmem_page_offset, page_length, |
812 | user_data, page_do_bit17_swizzling, | |
813 | partial_cacheline_write, | |
814 | needs_clflush_after); | |
815 | if (ret == 0) | |
816 | goto next_page; | |
e244a443 DV |
817 | |
818 | hit_slowpath = 1; | |
692a576b | 819 | page_cache_get(page); |
e244a443 DV |
820 | mutex_unlock(&dev->struct_mutex); |
821 | ||
d174bd64 DV |
822 | ret = shmem_pwrite_slow(page, shmem_page_offset, page_length, |
823 | user_data, page_do_bit17_swizzling, | |
824 | partial_cacheline_write, | |
825 | needs_clflush_after); | |
40123c1f | 826 | |
e244a443 | 827 | mutex_lock(&dev->struct_mutex); |
692a576b | 828 | page_cache_release(page); |
e244a443 | 829 | next_page: |
e5281ccd CW |
830 | set_page_dirty(page); |
831 | mark_page_accessed(page); | |
692a576b DV |
832 | if (release_page) |
833 | page_cache_release(page); | |
e5281ccd | 834 | |
8c59967c DV |
835 | if (ret) { |
836 | ret = -EFAULT; | |
837 | goto out; | |
838 | } | |
839 | ||
40123c1f | 840 | remain -= page_length; |
8c59967c | 841 | user_data += page_length; |
40123c1f | 842 | offset += page_length; |
673a394b EA |
843 | } |
844 | ||
fbd5a26d | 845 | out: |
e244a443 DV |
846 | if (hit_slowpath) { |
847 | /* Fixup: Kill any reinstated backing storage pages */ | |
848 | if (obj->madv == __I915_MADV_PURGED) | |
849 | i915_gem_object_truncate(obj); | |
850 | /* and flush dirty cachelines in case the object isn't in the cpu write | |
851 | * domain anymore. */ | |
852 | if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) { | |
853 | i915_gem_clflush_object(obj); | |
854 | intel_gtt_chipset_flush(); | |
855 | } | |
8c59967c | 856 | } |
673a394b | 857 | |
58642885 DV |
858 | if (needs_clflush_after) |
859 | intel_gtt_chipset_flush(); | |
860 | ||
40123c1f | 861 | return ret; |
673a394b EA |
862 | } |
863 | ||
864 | /** | |
865 | * Writes data to the object referenced by handle. | |
866 | * | |
867 | * On error, the contents of the buffer that were to be modified are undefined. | |
868 | */ | |
869 | int | |
870 | i915_gem_pwrite_ioctl(struct drm_device *dev, void *data, | |
fbd5a26d | 871 | struct drm_file *file) |
673a394b EA |
872 | { |
873 | struct drm_i915_gem_pwrite *args = data; | |
05394f39 | 874 | struct drm_i915_gem_object *obj; |
51311d0a CW |
875 | int ret; |
876 | ||
877 | if (args->size == 0) | |
878 | return 0; | |
879 | ||
880 | if (!access_ok(VERIFY_READ, | |
881 | (char __user *)(uintptr_t)args->data_ptr, | |
882 | args->size)) | |
883 | return -EFAULT; | |
884 | ||
f56f821f DV |
885 | ret = fault_in_multipages_readable((char __user *)(uintptr_t)args->data_ptr, |
886 | args->size); | |
51311d0a CW |
887 | if (ret) |
888 | return -EFAULT; | |
673a394b | 889 | |
fbd5a26d | 890 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 891 | if (ret) |
fbd5a26d | 892 | return ret; |
1d7cfea1 | 893 | |
05394f39 | 894 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 895 | if (&obj->base == NULL) { |
1d7cfea1 CW |
896 | ret = -ENOENT; |
897 | goto unlock; | |
fbd5a26d | 898 | } |
673a394b | 899 | |
7dcd2499 | 900 | /* Bounds check destination. */ |
05394f39 CW |
901 | if (args->offset > obj->base.size || |
902 | args->size > obj->base.size - args->offset) { | |
ce9d419d | 903 | ret = -EINVAL; |
35b62a89 | 904 | goto out; |
ce9d419d CW |
905 | } |
906 | ||
1286ff73 DV |
907 | /* prime objects have no backing filp to GEM pread/pwrite |
908 | * pages from. | |
909 | */ | |
910 | if (!obj->base.filp) { | |
911 | ret = -EINVAL; | |
912 | goto out; | |
913 | } | |
914 | ||
db53a302 CW |
915 | trace_i915_gem_object_pwrite(obj, args->offset, args->size); |
916 | ||
935aaa69 | 917 | ret = -EFAULT; |
673a394b EA |
918 | /* We can only do the GTT pwrite on untiled buffers, as otherwise |
919 | * it would end up going through the fenced access, and we'll get | |
920 | * different detiling behavior between reading and writing. | |
921 | * pread/pwrite currently are reading and writing from the CPU | |
922 | * perspective, requiring manual detiling by the client. | |
923 | */ | |
5c0480f2 | 924 | if (obj->phys_obj) { |
fbd5a26d | 925 | ret = i915_gem_phys_pwrite(dev, obj, args, file); |
5c0480f2 DV |
926 | goto out; |
927 | } | |
928 | ||
86a1ee26 | 929 | if (obj->cache_level == I915_CACHE_NONE && |
c07496fa | 930 | obj->tiling_mode == I915_TILING_NONE && |
5c0480f2 | 931 | obj->base.write_domain != I915_GEM_DOMAIN_CPU) { |
fbd5a26d | 932 | ret = i915_gem_gtt_pwrite_fast(dev, obj, args, file); |
935aaa69 DV |
933 | /* Note that the gtt paths might fail with non-page-backed user |
934 | * pointers (e.g. gtt mappings when moving data between | |
935 | * textures). Fallback to the shmem path in that case. */ | |
fbd5a26d | 936 | } |
673a394b | 937 | |
86a1ee26 | 938 | if (ret == -EFAULT || ret == -ENOSPC) |
935aaa69 | 939 | ret = i915_gem_shmem_pwrite(dev, obj, args, file); |
5c0480f2 | 940 | |
35b62a89 | 941 | out: |
05394f39 | 942 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 943 | unlock: |
fbd5a26d | 944 | mutex_unlock(&dev->struct_mutex); |
673a394b EA |
945 | return ret; |
946 | } | |
947 | ||
b361237b CW |
948 | int |
949 | i915_gem_check_wedge(struct drm_i915_private *dev_priv, | |
950 | bool interruptible) | |
951 | { | |
952 | if (atomic_read(&dev_priv->mm.wedged)) { | |
953 | struct completion *x = &dev_priv->error_completion; | |
954 | bool recovery_complete; | |
955 | unsigned long flags; | |
956 | ||
957 | /* Give the error handler a chance to run. */ | |
958 | spin_lock_irqsave(&x->wait.lock, flags); | |
959 | recovery_complete = x->done > 0; | |
960 | spin_unlock_irqrestore(&x->wait.lock, flags); | |
961 | ||
962 | /* Non-interruptible callers can't handle -EAGAIN, hence return | |
963 | * -EIO unconditionally for these. */ | |
964 | if (!interruptible) | |
965 | return -EIO; | |
966 | ||
967 | /* Recovery complete, but still wedged means reset failure. */ | |
968 | if (recovery_complete) | |
969 | return -EIO; | |
970 | ||
971 | return -EAGAIN; | |
972 | } | |
973 | ||
974 | return 0; | |
975 | } | |
976 | ||
977 | /* | |
978 | * Compare seqno against outstanding lazy request. Emit a request if they are | |
979 | * equal. | |
980 | */ | |
981 | static int | |
982 | i915_gem_check_olr(struct intel_ring_buffer *ring, u32 seqno) | |
983 | { | |
984 | int ret; | |
985 | ||
986 | BUG_ON(!mutex_is_locked(&ring->dev->struct_mutex)); | |
987 | ||
988 | ret = 0; | |
989 | if (seqno == ring->outstanding_lazy_request) | |
990 | ret = i915_add_request(ring, NULL, NULL); | |
991 | ||
992 | return ret; | |
993 | } | |
994 | ||
995 | /** | |
996 | * __wait_seqno - wait until execution of seqno has finished | |
997 | * @ring: the ring expected to report seqno | |
998 | * @seqno: duh! | |
999 | * @interruptible: do an interruptible wait (normally yes) | |
1000 | * @timeout: in - how long to wait (NULL forever); out - how much time remaining | |
1001 | * | |
1002 | * Returns 0 if the seqno was found within the alloted time. Else returns the | |
1003 | * errno with remaining time filled in timeout argument. | |
1004 | */ | |
1005 | static int __wait_seqno(struct intel_ring_buffer *ring, u32 seqno, | |
1006 | bool interruptible, struct timespec *timeout) | |
1007 | { | |
1008 | drm_i915_private_t *dev_priv = ring->dev->dev_private; | |
1009 | struct timespec before, now, wait_time={1,0}; | |
1010 | unsigned long timeout_jiffies; | |
1011 | long end; | |
1012 | bool wait_forever = true; | |
1013 | int ret; | |
1014 | ||
1015 | if (i915_seqno_passed(ring->get_seqno(ring, true), seqno)) | |
1016 | return 0; | |
1017 | ||
1018 | trace_i915_gem_request_wait_begin(ring, seqno); | |
1019 | ||
1020 | if (timeout != NULL) { | |
1021 | wait_time = *timeout; | |
1022 | wait_forever = false; | |
1023 | } | |
1024 | ||
1025 | timeout_jiffies = timespec_to_jiffies(&wait_time); | |
1026 | ||
1027 | if (WARN_ON(!ring->irq_get(ring))) | |
1028 | return -ENODEV; | |
1029 | ||
1030 | /* Record current time in case interrupted by signal, or wedged * */ | |
1031 | getrawmonotonic(&before); | |
1032 | ||
1033 | #define EXIT_COND \ | |
1034 | (i915_seqno_passed(ring->get_seqno(ring, false), seqno) || \ | |
1035 | atomic_read(&dev_priv->mm.wedged)) | |
1036 | do { | |
1037 | if (interruptible) | |
1038 | end = wait_event_interruptible_timeout(ring->irq_queue, | |
1039 | EXIT_COND, | |
1040 | timeout_jiffies); | |
1041 | else | |
1042 | end = wait_event_timeout(ring->irq_queue, EXIT_COND, | |
1043 | timeout_jiffies); | |
1044 | ||
1045 | ret = i915_gem_check_wedge(dev_priv, interruptible); | |
1046 | if (ret) | |
1047 | end = ret; | |
1048 | } while (end == 0 && wait_forever); | |
1049 | ||
1050 | getrawmonotonic(&now); | |
1051 | ||
1052 | ring->irq_put(ring); | |
1053 | trace_i915_gem_request_wait_end(ring, seqno); | |
1054 | #undef EXIT_COND | |
1055 | ||
1056 | if (timeout) { | |
1057 | struct timespec sleep_time = timespec_sub(now, before); | |
1058 | *timeout = timespec_sub(*timeout, sleep_time); | |
1059 | } | |
1060 | ||
1061 | switch (end) { | |
1062 | case -EIO: | |
1063 | case -EAGAIN: /* Wedged */ | |
1064 | case -ERESTARTSYS: /* Signal */ | |
1065 | return (int)end; | |
1066 | case 0: /* Timeout */ | |
1067 | if (timeout) | |
1068 | set_normalized_timespec(timeout, 0, 0); | |
1069 | return -ETIME; | |
1070 | default: /* Completed */ | |
1071 | WARN_ON(end < 0); /* We're not aware of other errors */ | |
1072 | return 0; | |
1073 | } | |
1074 | } | |
1075 | ||
1076 | /** | |
1077 | * Waits for a sequence number to be signaled, and cleans up the | |
1078 | * request and object lists appropriately for that event. | |
1079 | */ | |
1080 | int | |
1081 | i915_wait_seqno(struct intel_ring_buffer *ring, uint32_t seqno) | |
1082 | { | |
1083 | struct drm_device *dev = ring->dev; | |
1084 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1085 | bool interruptible = dev_priv->mm.interruptible; | |
1086 | int ret; | |
1087 | ||
1088 | BUG_ON(!mutex_is_locked(&dev->struct_mutex)); | |
1089 | BUG_ON(seqno == 0); | |
1090 | ||
1091 | ret = i915_gem_check_wedge(dev_priv, interruptible); | |
1092 | if (ret) | |
1093 | return ret; | |
1094 | ||
1095 | ret = i915_gem_check_olr(ring, seqno); | |
1096 | if (ret) | |
1097 | return ret; | |
1098 | ||
1099 | return __wait_seqno(ring, seqno, interruptible, NULL); | |
1100 | } | |
1101 | ||
1102 | /** | |
1103 | * Ensures that all rendering to the object has completed and the object is | |
1104 | * safe to unbind from the GTT or access from the CPU. | |
1105 | */ | |
1106 | static __must_check int | |
1107 | i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj, | |
1108 | bool readonly) | |
1109 | { | |
1110 | struct intel_ring_buffer *ring = obj->ring; | |
1111 | u32 seqno; | |
1112 | int ret; | |
1113 | ||
1114 | seqno = readonly ? obj->last_write_seqno : obj->last_read_seqno; | |
1115 | if (seqno == 0) | |
1116 | return 0; | |
1117 | ||
1118 | ret = i915_wait_seqno(ring, seqno); | |
1119 | if (ret) | |
1120 | return ret; | |
1121 | ||
1122 | i915_gem_retire_requests_ring(ring); | |
1123 | ||
1124 | /* Manually manage the write flush as we may have not yet | |
1125 | * retired the buffer. | |
1126 | */ | |
1127 | if (obj->last_write_seqno && | |
1128 | i915_seqno_passed(seqno, obj->last_write_seqno)) { | |
1129 | obj->last_write_seqno = 0; | |
1130 | obj->base.write_domain &= ~I915_GEM_GPU_DOMAINS; | |
1131 | } | |
1132 | ||
1133 | return 0; | |
1134 | } | |
1135 | ||
3236f57a CW |
1136 | /* A nonblocking variant of the above wait. This is a highly dangerous routine |
1137 | * as the object state may change during this call. | |
1138 | */ | |
1139 | static __must_check int | |
1140 | i915_gem_object_wait_rendering__nonblocking(struct drm_i915_gem_object *obj, | |
1141 | bool readonly) | |
1142 | { | |
1143 | struct drm_device *dev = obj->base.dev; | |
1144 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1145 | struct intel_ring_buffer *ring = obj->ring; | |
1146 | u32 seqno; | |
1147 | int ret; | |
1148 | ||
1149 | BUG_ON(!mutex_is_locked(&dev->struct_mutex)); | |
1150 | BUG_ON(!dev_priv->mm.interruptible); | |
1151 | ||
1152 | seqno = readonly ? obj->last_write_seqno : obj->last_read_seqno; | |
1153 | if (seqno == 0) | |
1154 | return 0; | |
1155 | ||
1156 | ret = i915_gem_check_wedge(dev_priv, true); | |
1157 | if (ret) | |
1158 | return ret; | |
1159 | ||
1160 | ret = i915_gem_check_olr(ring, seqno); | |
1161 | if (ret) | |
1162 | return ret; | |
1163 | ||
1164 | mutex_unlock(&dev->struct_mutex); | |
1165 | ret = __wait_seqno(ring, seqno, true, NULL); | |
1166 | mutex_lock(&dev->struct_mutex); | |
1167 | ||
1168 | i915_gem_retire_requests_ring(ring); | |
1169 | ||
1170 | /* Manually manage the write flush as we may have not yet | |
1171 | * retired the buffer. | |
1172 | */ | |
1173 | if (obj->last_write_seqno && | |
1174 | i915_seqno_passed(seqno, obj->last_write_seqno)) { | |
1175 | obj->last_write_seqno = 0; | |
1176 | obj->base.write_domain &= ~I915_GEM_GPU_DOMAINS; | |
1177 | } | |
1178 | ||
1179 | return ret; | |
1180 | } | |
1181 | ||
673a394b | 1182 | /** |
2ef7eeaa EA |
1183 | * Called when user space prepares to use an object with the CPU, either |
1184 | * through the mmap ioctl's mapping or a GTT mapping. | |
673a394b EA |
1185 | */ |
1186 | int | |
1187 | i915_gem_set_domain_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 1188 | struct drm_file *file) |
673a394b EA |
1189 | { |
1190 | struct drm_i915_gem_set_domain *args = data; | |
05394f39 | 1191 | struct drm_i915_gem_object *obj; |
2ef7eeaa EA |
1192 | uint32_t read_domains = args->read_domains; |
1193 | uint32_t write_domain = args->write_domain; | |
673a394b EA |
1194 | int ret; |
1195 | ||
2ef7eeaa | 1196 | /* Only handle setting domains to types used by the CPU. */ |
21d509e3 | 1197 | if (write_domain & I915_GEM_GPU_DOMAINS) |
2ef7eeaa EA |
1198 | return -EINVAL; |
1199 | ||
21d509e3 | 1200 | if (read_domains & I915_GEM_GPU_DOMAINS) |
2ef7eeaa EA |
1201 | return -EINVAL; |
1202 | ||
1203 | /* Having something in the write domain implies it's in the read | |
1204 | * domain, and only that read domain. Enforce that in the request. | |
1205 | */ | |
1206 | if (write_domain != 0 && read_domains != write_domain) | |
1207 | return -EINVAL; | |
1208 | ||
76c1dec1 | 1209 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 1210 | if (ret) |
76c1dec1 | 1211 | return ret; |
1d7cfea1 | 1212 | |
05394f39 | 1213 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 1214 | if (&obj->base == NULL) { |
1d7cfea1 CW |
1215 | ret = -ENOENT; |
1216 | goto unlock; | |
76c1dec1 | 1217 | } |
673a394b | 1218 | |
3236f57a CW |
1219 | /* Try to flush the object off the GPU without holding the lock. |
1220 | * We will repeat the flush holding the lock in the normal manner | |
1221 | * to catch cases where we are gazumped. | |
1222 | */ | |
1223 | ret = i915_gem_object_wait_rendering__nonblocking(obj, !write_domain); | |
1224 | if (ret) | |
1225 | goto unref; | |
1226 | ||
2ef7eeaa EA |
1227 | if (read_domains & I915_GEM_DOMAIN_GTT) { |
1228 | ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0); | |
02354392 EA |
1229 | |
1230 | /* Silently promote "you're not bound, there was nothing to do" | |
1231 | * to success, since the client was just asking us to | |
1232 | * make sure everything was done. | |
1233 | */ | |
1234 | if (ret == -EINVAL) | |
1235 | ret = 0; | |
2ef7eeaa | 1236 | } else { |
e47c68e9 | 1237 | ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0); |
2ef7eeaa EA |
1238 | } |
1239 | ||
3236f57a | 1240 | unref: |
05394f39 | 1241 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 1242 | unlock: |
673a394b EA |
1243 | mutex_unlock(&dev->struct_mutex); |
1244 | return ret; | |
1245 | } | |
1246 | ||
1247 | /** | |
1248 | * Called when user space has done writes to this buffer | |
1249 | */ | |
1250 | int | |
1251 | i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 1252 | struct drm_file *file) |
673a394b EA |
1253 | { |
1254 | struct drm_i915_gem_sw_finish *args = data; | |
05394f39 | 1255 | struct drm_i915_gem_object *obj; |
673a394b EA |
1256 | int ret = 0; |
1257 | ||
76c1dec1 | 1258 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 1259 | if (ret) |
76c1dec1 | 1260 | return ret; |
1d7cfea1 | 1261 | |
05394f39 | 1262 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 1263 | if (&obj->base == NULL) { |
1d7cfea1 CW |
1264 | ret = -ENOENT; |
1265 | goto unlock; | |
673a394b EA |
1266 | } |
1267 | ||
673a394b | 1268 | /* Pinned buffers may be scanout, so flush the cache */ |
05394f39 | 1269 | if (obj->pin_count) |
e47c68e9 EA |
1270 | i915_gem_object_flush_cpu_write_domain(obj); |
1271 | ||
05394f39 | 1272 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 1273 | unlock: |
673a394b EA |
1274 | mutex_unlock(&dev->struct_mutex); |
1275 | return ret; | |
1276 | } | |
1277 | ||
1278 | /** | |
1279 | * Maps the contents of an object, returning the address it is mapped | |
1280 | * into. | |
1281 | * | |
1282 | * While the mapping holds a reference on the contents of the object, it doesn't | |
1283 | * imply a ref on the object itself. | |
1284 | */ | |
1285 | int | |
1286 | i915_gem_mmap_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 1287 | struct drm_file *file) |
673a394b EA |
1288 | { |
1289 | struct drm_i915_gem_mmap *args = data; | |
1290 | struct drm_gem_object *obj; | |
673a394b EA |
1291 | unsigned long addr; |
1292 | ||
05394f39 | 1293 | obj = drm_gem_object_lookup(dev, file, args->handle); |
673a394b | 1294 | if (obj == NULL) |
bf79cb91 | 1295 | return -ENOENT; |
673a394b | 1296 | |
1286ff73 DV |
1297 | /* prime objects have no backing filp to GEM mmap |
1298 | * pages from. | |
1299 | */ | |
1300 | if (!obj->filp) { | |
1301 | drm_gem_object_unreference_unlocked(obj); | |
1302 | return -EINVAL; | |
1303 | } | |
1304 | ||
6be5ceb0 | 1305 | addr = vm_mmap(obj->filp, 0, args->size, |
673a394b EA |
1306 | PROT_READ | PROT_WRITE, MAP_SHARED, |
1307 | args->offset); | |
bc9025bd | 1308 | drm_gem_object_unreference_unlocked(obj); |
673a394b EA |
1309 | if (IS_ERR((void *)addr)) |
1310 | return addr; | |
1311 | ||
1312 | args->addr_ptr = (uint64_t) addr; | |
1313 | ||
1314 | return 0; | |
1315 | } | |
1316 | ||
de151cf6 JB |
1317 | /** |
1318 | * i915_gem_fault - fault a page into the GTT | |
1319 | * vma: VMA in question | |
1320 | * vmf: fault info | |
1321 | * | |
1322 | * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped | |
1323 | * from userspace. The fault handler takes care of binding the object to | |
1324 | * the GTT (if needed), allocating and programming a fence register (again, | |
1325 | * only if needed based on whether the old reg is still valid or the object | |
1326 | * is tiled) and inserting a new PTE into the faulting process. | |
1327 | * | |
1328 | * Note that the faulting process may involve evicting existing objects | |
1329 | * from the GTT and/or fence registers to make room. So performance may | |
1330 | * suffer if the GTT working set is large or there are few fence registers | |
1331 | * left. | |
1332 | */ | |
1333 | int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf) | |
1334 | { | |
05394f39 CW |
1335 | struct drm_i915_gem_object *obj = to_intel_bo(vma->vm_private_data); |
1336 | struct drm_device *dev = obj->base.dev; | |
7d1c4804 | 1337 | drm_i915_private_t *dev_priv = dev->dev_private; |
de151cf6 JB |
1338 | pgoff_t page_offset; |
1339 | unsigned long pfn; | |
1340 | int ret = 0; | |
0f973f27 | 1341 | bool write = !!(vmf->flags & FAULT_FLAG_WRITE); |
de151cf6 JB |
1342 | |
1343 | /* We don't use vmf->pgoff since that has the fake offset */ | |
1344 | page_offset = ((unsigned long)vmf->virtual_address - vma->vm_start) >> | |
1345 | PAGE_SHIFT; | |
1346 | ||
d9bc7e9f CW |
1347 | ret = i915_mutex_lock_interruptible(dev); |
1348 | if (ret) | |
1349 | goto out; | |
a00b10c3 | 1350 | |
db53a302 CW |
1351 | trace_i915_gem_object_fault(obj, page_offset, true, write); |
1352 | ||
d9bc7e9f | 1353 | /* Now bind it into the GTT if needed */ |
919926ae CW |
1354 | if (!obj->map_and_fenceable) { |
1355 | ret = i915_gem_object_unbind(obj); | |
1356 | if (ret) | |
1357 | goto unlock; | |
a00b10c3 | 1358 | } |
05394f39 | 1359 | if (!obj->gtt_space) { |
86a1ee26 | 1360 | ret = i915_gem_object_bind_to_gtt(obj, 0, true, false); |
c715089f CW |
1361 | if (ret) |
1362 | goto unlock; | |
de151cf6 | 1363 | |
e92d03bf EA |
1364 | ret = i915_gem_object_set_to_gtt_domain(obj, write); |
1365 | if (ret) | |
1366 | goto unlock; | |
1367 | } | |
4a684a41 | 1368 | |
74898d7e DV |
1369 | if (!obj->has_global_gtt_mapping) |
1370 | i915_gem_gtt_bind_object(obj, obj->cache_level); | |
1371 | ||
06d98131 | 1372 | ret = i915_gem_object_get_fence(obj); |
d9e86c0e CW |
1373 | if (ret) |
1374 | goto unlock; | |
de151cf6 | 1375 | |
05394f39 CW |
1376 | if (i915_gem_object_is_inactive(obj)) |
1377 | list_move_tail(&obj->mm_list, &dev_priv->mm.inactive_list); | |
7d1c4804 | 1378 | |
6299f992 CW |
1379 | obj->fault_mappable = true; |
1380 | ||
dd2757f8 | 1381 | pfn = ((dev_priv->mm.gtt_base_addr + obj->gtt_offset) >> PAGE_SHIFT) + |
de151cf6 JB |
1382 | page_offset; |
1383 | ||
1384 | /* Finally, remap it using the new GTT offset */ | |
1385 | ret = vm_insert_pfn(vma, (unsigned long)vmf->virtual_address, pfn); | |
c715089f | 1386 | unlock: |
de151cf6 | 1387 | mutex_unlock(&dev->struct_mutex); |
d9bc7e9f | 1388 | out: |
de151cf6 | 1389 | switch (ret) { |
d9bc7e9f | 1390 | case -EIO: |
a9340cca DV |
1391 | /* If this -EIO is due to a gpu hang, give the reset code a |
1392 | * chance to clean up the mess. Otherwise return the proper | |
1393 | * SIGBUS. */ | |
1394 | if (!atomic_read(&dev_priv->mm.wedged)) | |
1395 | return VM_FAULT_SIGBUS; | |
045e769a | 1396 | case -EAGAIN: |
d9bc7e9f CW |
1397 | /* Give the error handler a chance to run and move the |
1398 | * objects off the GPU active list. Next time we service the | |
1399 | * fault, we should be able to transition the page into the | |
1400 | * GTT without touching the GPU (and so avoid further | |
1401 | * EIO/EGAIN). If the GPU is wedged, then there is no issue | |
1402 | * with coherency, just lost writes. | |
1403 | */ | |
045e769a | 1404 | set_need_resched(); |
c715089f CW |
1405 | case 0: |
1406 | case -ERESTARTSYS: | |
bed636ab | 1407 | case -EINTR: |
c715089f | 1408 | return VM_FAULT_NOPAGE; |
de151cf6 | 1409 | case -ENOMEM: |
de151cf6 | 1410 | return VM_FAULT_OOM; |
de151cf6 | 1411 | default: |
c715089f | 1412 | return VM_FAULT_SIGBUS; |
de151cf6 JB |
1413 | } |
1414 | } | |
1415 | ||
901782b2 CW |
1416 | /** |
1417 | * i915_gem_release_mmap - remove physical page mappings | |
1418 | * @obj: obj in question | |
1419 | * | |
af901ca1 | 1420 | * Preserve the reservation of the mmapping with the DRM core code, but |
901782b2 CW |
1421 | * relinquish ownership of the pages back to the system. |
1422 | * | |
1423 | * It is vital that we remove the page mapping if we have mapped a tiled | |
1424 | * object through the GTT and then lose the fence register due to | |
1425 | * resource pressure. Similarly if the object has been moved out of the | |
1426 | * aperture, than pages mapped into userspace must be revoked. Removing the | |
1427 | * mapping will then trigger a page fault on the next user access, allowing | |
1428 | * fixup by i915_gem_fault(). | |
1429 | */ | |
d05ca301 | 1430 | void |
05394f39 | 1431 | i915_gem_release_mmap(struct drm_i915_gem_object *obj) |
901782b2 | 1432 | { |
6299f992 CW |
1433 | if (!obj->fault_mappable) |
1434 | return; | |
901782b2 | 1435 | |
f6e47884 CW |
1436 | if (obj->base.dev->dev_mapping) |
1437 | unmap_mapping_range(obj->base.dev->dev_mapping, | |
1438 | (loff_t)obj->base.map_list.hash.key<<PAGE_SHIFT, | |
1439 | obj->base.size, 1); | |
fb7d516a | 1440 | |
6299f992 | 1441 | obj->fault_mappable = false; |
901782b2 CW |
1442 | } |
1443 | ||
92b88aeb | 1444 | static uint32_t |
e28f8711 | 1445 | i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode) |
92b88aeb | 1446 | { |
e28f8711 | 1447 | uint32_t gtt_size; |
92b88aeb CW |
1448 | |
1449 | if (INTEL_INFO(dev)->gen >= 4 || | |
e28f8711 CW |
1450 | tiling_mode == I915_TILING_NONE) |
1451 | return size; | |
92b88aeb CW |
1452 | |
1453 | /* Previous chips need a power-of-two fence region when tiling */ | |
1454 | if (INTEL_INFO(dev)->gen == 3) | |
e28f8711 | 1455 | gtt_size = 1024*1024; |
92b88aeb | 1456 | else |
e28f8711 | 1457 | gtt_size = 512*1024; |
92b88aeb | 1458 | |
e28f8711 CW |
1459 | while (gtt_size < size) |
1460 | gtt_size <<= 1; | |
92b88aeb | 1461 | |
e28f8711 | 1462 | return gtt_size; |
92b88aeb CW |
1463 | } |
1464 | ||
de151cf6 JB |
1465 | /** |
1466 | * i915_gem_get_gtt_alignment - return required GTT alignment for an object | |
1467 | * @obj: object to check | |
1468 | * | |
1469 | * Return the required GTT alignment for an object, taking into account | |
5e783301 | 1470 | * potential fence register mapping. |
de151cf6 JB |
1471 | */ |
1472 | static uint32_t | |
e28f8711 CW |
1473 | i915_gem_get_gtt_alignment(struct drm_device *dev, |
1474 | uint32_t size, | |
1475 | int tiling_mode) | |
de151cf6 | 1476 | { |
de151cf6 JB |
1477 | /* |
1478 | * Minimum alignment is 4k (GTT page size), but might be greater | |
1479 | * if a fence register is needed for the object. | |
1480 | */ | |
a00b10c3 | 1481 | if (INTEL_INFO(dev)->gen >= 4 || |
e28f8711 | 1482 | tiling_mode == I915_TILING_NONE) |
de151cf6 JB |
1483 | return 4096; |
1484 | ||
a00b10c3 CW |
1485 | /* |
1486 | * Previous chips need to be aligned to the size of the smallest | |
1487 | * fence register that can contain the object. | |
1488 | */ | |
e28f8711 | 1489 | return i915_gem_get_gtt_size(dev, size, tiling_mode); |
a00b10c3 CW |
1490 | } |
1491 | ||
5e783301 DV |
1492 | /** |
1493 | * i915_gem_get_unfenced_gtt_alignment - return required GTT alignment for an | |
1494 | * unfenced object | |
e28f8711 CW |
1495 | * @dev: the device |
1496 | * @size: size of the object | |
1497 | * @tiling_mode: tiling mode of the object | |
5e783301 DV |
1498 | * |
1499 | * Return the required GTT alignment for an object, only taking into account | |
1500 | * unfenced tiled surface requirements. | |
1501 | */ | |
467cffba | 1502 | uint32_t |
e28f8711 CW |
1503 | i915_gem_get_unfenced_gtt_alignment(struct drm_device *dev, |
1504 | uint32_t size, | |
1505 | int tiling_mode) | |
5e783301 | 1506 | { |
5e783301 DV |
1507 | /* |
1508 | * Minimum alignment is 4k (GTT page size) for sane hw. | |
1509 | */ | |
1510 | if (INTEL_INFO(dev)->gen >= 4 || IS_G33(dev) || | |
e28f8711 | 1511 | tiling_mode == I915_TILING_NONE) |
5e783301 DV |
1512 | return 4096; |
1513 | ||
e28f8711 CW |
1514 | /* Previous hardware however needs to be aligned to a power-of-two |
1515 | * tile height. The simplest method for determining this is to reuse | |
1516 | * the power-of-tile object size. | |
5e783301 | 1517 | */ |
e28f8711 | 1518 | return i915_gem_get_gtt_size(dev, size, tiling_mode); |
5e783301 DV |
1519 | } |
1520 | ||
d8cb5086 CW |
1521 | static int i915_gem_object_create_mmap_offset(struct drm_i915_gem_object *obj) |
1522 | { | |
1523 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; | |
1524 | int ret; | |
1525 | ||
1526 | if (obj->base.map_list.map) | |
1527 | return 0; | |
1528 | ||
1529 | ret = drm_gem_create_mmap_offset(&obj->base); | |
1530 | if (ret != -ENOSPC) | |
1531 | return ret; | |
1532 | ||
1533 | /* Badly fragmented mmap space? The only way we can recover | |
1534 | * space is by destroying unwanted objects. We can't randomly release | |
1535 | * mmap_offsets as userspace expects them to be persistent for the | |
1536 | * lifetime of the objects. The closest we can is to release the | |
1537 | * offsets on purgeable objects by truncating it and marking it purged, | |
1538 | * which prevents userspace from ever using that object again. | |
1539 | */ | |
1540 | i915_gem_purge(dev_priv, obj->base.size >> PAGE_SHIFT); | |
1541 | ret = drm_gem_create_mmap_offset(&obj->base); | |
1542 | if (ret != -ENOSPC) | |
1543 | return ret; | |
1544 | ||
1545 | i915_gem_shrink_all(dev_priv); | |
1546 | return drm_gem_create_mmap_offset(&obj->base); | |
1547 | } | |
1548 | ||
1549 | static void i915_gem_object_free_mmap_offset(struct drm_i915_gem_object *obj) | |
1550 | { | |
1551 | if (!obj->base.map_list.map) | |
1552 | return; | |
1553 | ||
1554 | drm_gem_free_mmap_offset(&obj->base); | |
1555 | } | |
1556 | ||
de151cf6 | 1557 | int |
ff72145b DA |
1558 | i915_gem_mmap_gtt(struct drm_file *file, |
1559 | struct drm_device *dev, | |
1560 | uint32_t handle, | |
1561 | uint64_t *offset) | |
de151cf6 | 1562 | { |
da761a6e | 1563 | struct drm_i915_private *dev_priv = dev->dev_private; |
05394f39 | 1564 | struct drm_i915_gem_object *obj; |
de151cf6 JB |
1565 | int ret; |
1566 | ||
76c1dec1 | 1567 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 1568 | if (ret) |
76c1dec1 | 1569 | return ret; |
de151cf6 | 1570 | |
ff72145b | 1571 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle)); |
c8725226 | 1572 | if (&obj->base == NULL) { |
1d7cfea1 CW |
1573 | ret = -ENOENT; |
1574 | goto unlock; | |
1575 | } | |
de151cf6 | 1576 | |
05394f39 | 1577 | if (obj->base.size > dev_priv->mm.gtt_mappable_end) { |
da761a6e | 1578 | ret = -E2BIG; |
ff56b0bc | 1579 | goto out; |
da761a6e CW |
1580 | } |
1581 | ||
05394f39 | 1582 | if (obj->madv != I915_MADV_WILLNEED) { |
ab18282d | 1583 | DRM_ERROR("Attempting to mmap a purgeable buffer\n"); |
1d7cfea1 CW |
1584 | ret = -EINVAL; |
1585 | goto out; | |
ab18282d CW |
1586 | } |
1587 | ||
d8cb5086 CW |
1588 | ret = i915_gem_object_create_mmap_offset(obj); |
1589 | if (ret) | |
1590 | goto out; | |
de151cf6 | 1591 | |
ff72145b | 1592 | *offset = (u64)obj->base.map_list.hash.key << PAGE_SHIFT; |
de151cf6 | 1593 | |
1d7cfea1 | 1594 | out: |
05394f39 | 1595 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 1596 | unlock: |
de151cf6 | 1597 | mutex_unlock(&dev->struct_mutex); |
1d7cfea1 | 1598 | return ret; |
de151cf6 JB |
1599 | } |
1600 | ||
ff72145b DA |
1601 | /** |
1602 | * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing | |
1603 | * @dev: DRM device | |
1604 | * @data: GTT mapping ioctl data | |
1605 | * @file: GEM object info | |
1606 | * | |
1607 | * Simply returns the fake offset to userspace so it can mmap it. | |
1608 | * The mmap call will end up in drm_gem_mmap(), which will set things | |
1609 | * up so we can get faults in the handler above. | |
1610 | * | |
1611 | * The fault handler will take care of binding the object into the GTT | |
1612 | * (since it may have been evicted to make room for something), allocating | |
1613 | * a fence register, and mapping the appropriate aperture address into | |
1614 | * userspace. | |
1615 | */ | |
1616 | int | |
1617 | i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data, | |
1618 | struct drm_file *file) | |
1619 | { | |
1620 | struct drm_i915_gem_mmap_gtt *args = data; | |
1621 | ||
ff72145b DA |
1622 | return i915_gem_mmap_gtt(file, dev, args->handle, &args->offset); |
1623 | } | |
1624 | ||
225067ee DV |
1625 | /* Immediately discard the backing storage */ |
1626 | static void | |
1627 | i915_gem_object_truncate(struct drm_i915_gem_object *obj) | |
1628 | { | |
1629 | struct inode *inode; | |
1630 | ||
4d6294bf CW |
1631 | i915_gem_object_free_mmap_offset(obj); |
1632 | ||
1633 | if (obj->base.filp == NULL) | |
1634 | return; | |
1635 | ||
225067ee DV |
1636 | /* Our goal here is to return as much of the memory as |
1637 | * is possible back to the system as we are called from OOM. | |
1638 | * To do this we must instruct the shmfs to drop all of its | |
1639 | * backing pages, *now*. | |
1640 | */ | |
1641 | inode = obj->base.filp->f_path.dentry->d_inode; | |
1642 | shmem_truncate_range(inode, 0, (loff_t)-1); | |
1643 | ||
225067ee DV |
1644 | obj->madv = __I915_MADV_PURGED; |
1645 | } | |
1646 | ||
1647 | static inline int | |
1648 | i915_gem_object_is_purgeable(struct drm_i915_gem_object *obj) | |
1649 | { | |
1650 | return obj->madv == I915_MADV_DONTNEED; | |
1651 | } | |
1652 | ||
6c085a72 | 1653 | static int |
225067ee DV |
1654 | i915_gem_object_put_pages_gtt(struct drm_i915_gem_object *obj) |
1655 | { | |
1656 | int page_count = obj->base.size / PAGE_SIZE; | |
6c085a72 | 1657 | int ret, i; |
225067ee | 1658 | |
c4670ad0 CW |
1659 | BUG_ON(obj->gtt_space); |
1660 | ||
6c085a72 CW |
1661 | if (obj->pages == NULL) |
1662 | return 0; | |
225067ee | 1663 | |
6c085a72 | 1664 | BUG_ON(obj->gtt_space); |
225067ee DV |
1665 | BUG_ON(obj->madv == __I915_MADV_PURGED); |
1666 | ||
6c085a72 CW |
1667 | ret = i915_gem_object_set_to_cpu_domain(obj, true); |
1668 | if (ret) { | |
1669 | /* In the event of a disaster, abandon all caches and | |
1670 | * hope for the best. | |
1671 | */ | |
1672 | WARN_ON(ret != -EIO); | |
1673 | i915_gem_clflush_object(obj); | |
1674 | obj->base.read_domains = obj->base.write_domain = I915_GEM_DOMAIN_CPU; | |
1675 | } | |
1676 | ||
225067ee DV |
1677 | if (i915_gem_object_needs_bit17_swizzle(obj)) |
1678 | i915_gem_object_save_bit_17_swizzle(obj); | |
1679 | ||
1680 | if (obj->madv == I915_MADV_DONTNEED) | |
1681 | obj->dirty = 0; | |
1682 | ||
1683 | for (i = 0; i < page_count; i++) { | |
1684 | if (obj->dirty) | |
1685 | set_page_dirty(obj->pages[i]); | |
1686 | ||
1687 | if (obj->madv == I915_MADV_WILLNEED) | |
1688 | mark_page_accessed(obj->pages[i]); | |
1689 | ||
1690 | page_cache_release(obj->pages[i]); | |
1691 | } | |
1692 | obj->dirty = 0; | |
1693 | ||
1694 | drm_free_large(obj->pages); | |
1695 | obj->pages = NULL; | |
6c085a72 CW |
1696 | |
1697 | list_del(&obj->gtt_list); | |
1698 | ||
1699 | if (i915_gem_object_is_purgeable(obj)) | |
1700 | i915_gem_object_truncate(obj); | |
1701 | ||
1702 | return 0; | |
1703 | } | |
1704 | ||
1705 | static long | |
1706 | i915_gem_purge(struct drm_i915_private *dev_priv, long target) | |
1707 | { | |
1708 | struct drm_i915_gem_object *obj, *next; | |
1709 | long count = 0; | |
1710 | ||
1711 | list_for_each_entry_safe(obj, next, | |
1712 | &dev_priv->mm.unbound_list, | |
1713 | gtt_list) { | |
1714 | if (i915_gem_object_is_purgeable(obj) && | |
1715 | i915_gem_object_put_pages_gtt(obj) == 0) { | |
1716 | count += obj->base.size >> PAGE_SHIFT; | |
1717 | if (count >= target) | |
1718 | return count; | |
1719 | } | |
1720 | } | |
1721 | ||
1722 | list_for_each_entry_safe(obj, next, | |
1723 | &dev_priv->mm.inactive_list, | |
1724 | mm_list) { | |
1725 | if (i915_gem_object_is_purgeable(obj) && | |
1726 | i915_gem_object_unbind(obj) == 0 && | |
1727 | i915_gem_object_put_pages_gtt(obj) == 0) { | |
1728 | count += obj->base.size >> PAGE_SHIFT; | |
1729 | if (count >= target) | |
1730 | return count; | |
1731 | } | |
1732 | } | |
1733 | ||
1734 | return count; | |
1735 | } | |
1736 | ||
1737 | static void | |
1738 | i915_gem_shrink_all(struct drm_i915_private *dev_priv) | |
1739 | { | |
1740 | struct drm_i915_gem_object *obj, *next; | |
1741 | ||
1742 | i915_gem_evict_everything(dev_priv->dev); | |
1743 | ||
1744 | list_for_each_entry_safe(obj, next, &dev_priv->mm.unbound_list, gtt_list) | |
1745 | i915_gem_object_put_pages_gtt(obj); | |
225067ee DV |
1746 | } |
1747 | ||
1286ff73 | 1748 | int |
6c085a72 | 1749 | i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj) |
e5281ccd | 1750 | { |
6c085a72 | 1751 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
e5281ccd CW |
1752 | int page_count, i; |
1753 | struct address_space *mapping; | |
e5281ccd | 1754 | struct page *page; |
6c085a72 | 1755 | gfp_t gfp; |
e5281ccd | 1756 | |
1286ff73 DV |
1757 | if (obj->pages || obj->sg_table) |
1758 | return 0; | |
1759 | ||
6c085a72 CW |
1760 | /* Assert that the object is not currently in any GPU domain. As it |
1761 | * wasn't in the GTT, there shouldn't be any way it could have been in | |
1762 | * a GPU cache | |
1763 | */ | |
1764 | BUG_ON(obj->base.read_domains & I915_GEM_GPU_DOMAINS); | |
1765 | BUG_ON(obj->base.write_domain & I915_GEM_GPU_DOMAINS); | |
1766 | ||
e5281ccd CW |
1767 | /* Get the list of pages out of our struct file. They'll be pinned |
1768 | * at this point until we release them. | |
1769 | */ | |
05394f39 | 1770 | page_count = obj->base.size / PAGE_SIZE; |
05394f39 CW |
1771 | obj->pages = drm_malloc_ab(page_count, sizeof(struct page *)); |
1772 | if (obj->pages == NULL) | |
e5281ccd CW |
1773 | return -ENOMEM; |
1774 | ||
6c085a72 CW |
1775 | /* Fail silently without starting the shrinker */ |
1776 | mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping; | |
1777 | gfp = mapping_gfp_mask(mapping); | |
1778 | gfp |= __GFP_NORETRY | __GFP_NOWARN | __GFP_NO_KSWAPD; | |
1779 | gfp &= ~(__GFP_IO | __GFP_WAIT); | |
e5281ccd | 1780 | for (i = 0; i < page_count; i++) { |
6c085a72 CW |
1781 | page = shmem_read_mapping_page_gfp(mapping, i, gfp); |
1782 | if (IS_ERR(page)) { | |
1783 | i915_gem_purge(dev_priv, page_count); | |
1784 | page = shmem_read_mapping_page_gfp(mapping, i, gfp); | |
1785 | } | |
1786 | if (IS_ERR(page)) { | |
1787 | /* We've tried hard to allocate the memory by reaping | |
1788 | * our own buffer, now let the real VM do its job and | |
1789 | * go down in flames if truly OOM. | |
1790 | */ | |
1791 | gfp &= ~(__GFP_NORETRY | __GFP_NOWARN | __GFP_NO_KSWAPD); | |
1792 | gfp |= __GFP_IO | __GFP_WAIT; | |
1793 | ||
1794 | i915_gem_shrink_all(dev_priv); | |
1795 | page = shmem_read_mapping_page_gfp(mapping, i, gfp); | |
1796 | if (IS_ERR(page)) | |
1797 | goto err_pages; | |
1798 | ||
1799 | gfp |= __GFP_NORETRY | __GFP_NOWARN | __GFP_NO_KSWAPD; | |
1800 | gfp &= ~(__GFP_IO | __GFP_WAIT); | |
1801 | } | |
e5281ccd | 1802 | |
05394f39 | 1803 | obj->pages[i] = page; |
e5281ccd CW |
1804 | } |
1805 | ||
6dacfd2f | 1806 | if (i915_gem_object_needs_bit17_swizzle(obj)) |
e5281ccd CW |
1807 | i915_gem_object_do_bit_17_swizzle(obj); |
1808 | ||
6c085a72 | 1809 | list_add_tail(&obj->gtt_list, &dev_priv->mm.unbound_list); |
e5281ccd CW |
1810 | return 0; |
1811 | ||
1812 | err_pages: | |
1813 | while (i--) | |
05394f39 | 1814 | page_cache_release(obj->pages[i]); |
e5281ccd | 1815 | |
05394f39 CW |
1816 | drm_free_large(obj->pages); |
1817 | obj->pages = NULL; | |
e5281ccd CW |
1818 | return PTR_ERR(page); |
1819 | } | |
1820 | ||
54cf91dc | 1821 | void |
05394f39 | 1822 | i915_gem_object_move_to_active(struct drm_i915_gem_object *obj, |
1ec14ad3 CW |
1823 | struct intel_ring_buffer *ring, |
1824 | u32 seqno) | |
673a394b | 1825 | { |
05394f39 | 1826 | struct drm_device *dev = obj->base.dev; |
69dc4987 | 1827 | struct drm_i915_private *dev_priv = dev->dev_private; |
617dbe27 | 1828 | |
852835f3 | 1829 | BUG_ON(ring == NULL); |
05394f39 | 1830 | obj->ring = ring; |
673a394b EA |
1831 | |
1832 | /* Add a reference if we're newly entering the active list. */ | |
05394f39 CW |
1833 | if (!obj->active) { |
1834 | drm_gem_object_reference(&obj->base); | |
1835 | obj->active = 1; | |
673a394b | 1836 | } |
e35a41de | 1837 | |
673a394b | 1838 | /* Move from whatever list we were on to the tail of execution. */ |
05394f39 CW |
1839 | list_move_tail(&obj->mm_list, &dev_priv->mm.active_list); |
1840 | list_move_tail(&obj->ring_list, &ring->active_list); | |
caea7476 | 1841 | |
0201f1ec | 1842 | obj->last_read_seqno = seqno; |
caea7476 | 1843 | |
7dd49065 | 1844 | if (obj->fenced_gpu_access) { |
caea7476 | 1845 | obj->last_fenced_seqno = seqno; |
caea7476 | 1846 | |
7dd49065 CW |
1847 | /* Bump MRU to take account of the delayed flush */ |
1848 | if (obj->fence_reg != I915_FENCE_REG_NONE) { | |
1849 | struct drm_i915_fence_reg *reg; | |
1850 | ||
1851 | reg = &dev_priv->fence_regs[obj->fence_reg]; | |
1852 | list_move_tail(®->lru_list, | |
1853 | &dev_priv->mm.fence_list); | |
1854 | } | |
caea7476 CW |
1855 | } |
1856 | } | |
1857 | ||
caea7476 CW |
1858 | static void |
1859 | i915_gem_object_move_to_inactive(struct drm_i915_gem_object *obj) | |
1860 | { | |
1861 | struct drm_device *dev = obj->base.dev; | |
1862 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1863 | ||
65ce3027 | 1864 | BUG_ON(obj->base.write_domain & ~I915_GEM_GPU_DOMAINS); |
caea7476 | 1865 | BUG_ON(!obj->active); |
65ce3027 | 1866 | |
f047e395 CW |
1867 | if (obj->pin_count) /* are we a framebuffer? */ |
1868 | intel_mark_fb_idle(obj); | |
1869 | ||
1870 | list_move_tail(&obj->mm_list, &dev_priv->mm.inactive_list); | |
1871 | ||
65ce3027 | 1872 | list_del_init(&obj->ring_list); |
caea7476 CW |
1873 | obj->ring = NULL; |
1874 | ||
65ce3027 CW |
1875 | obj->last_read_seqno = 0; |
1876 | obj->last_write_seqno = 0; | |
1877 | obj->base.write_domain = 0; | |
1878 | ||
1879 | obj->last_fenced_seqno = 0; | |
caea7476 | 1880 | obj->fenced_gpu_access = false; |
caea7476 CW |
1881 | |
1882 | obj->active = 0; | |
1883 | drm_gem_object_unreference(&obj->base); | |
1884 | ||
1885 | WARN_ON(i915_verify_lists(dev)); | |
ce44b0ea | 1886 | } |
673a394b | 1887 | |
53d227f2 DV |
1888 | static u32 |
1889 | i915_gem_get_seqno(struct drm_device *dev) | |
1890 | { | |
1891 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1892 | u32 seqno = dev_priv->next_seqno; | |
1893 | ||
1894 | /* reserve 0 for non-seqno */ | |
1895 | if (++dev_priv->next_seqno == 0) | |
1896 | dev_priv->next_seqno = 1; | |
1897 | ||
1898 | return seqno; | |
1899 | } | |
1900 | ||
1901 | u32 | |
1902 | i915_gem_next_request_seqno(struct intel_ring_buffer *ring) | |
1903 | { | |
1904 | if (ring->outstanding_lazy_request == 0) | |
1905 | ring->outstanding_lazy_request = i915_gem_get_seqno(ring->dev); | |
1906 | ||
1907 | return ring->outstanding_lazy_request; | |
1908 | } | |
1909 | ||
3cce469c | 1910 | int |
db53a302 | 1911 | i915_add_request(struct intel_ring_buffer *ring, |
f787a5f5 | 1912 | struct drm_file *file, |
db53a302 | 1913 | struct drm_i915_gem_request *request) |
673a394b | 1914 | { |
db53a302 | 1915 | drm_i915_private_t *dev_priv = ring->dev->dev_private; |
673a394b | 1916 | uint32_t seqno; |
a71d8d94 | 1917 | u32 request_ring_position; |
673a394b | 1918 | int was_empty; |
3cce469c CW |
1919 | int ret; |
1920 | ||
cc889e0f DV |
1921 | /* |
1922 | * Emit any outstanding flushes - execbuf can fail to emit the flush | |
1923 | * after having emitted the batchbuffer command. Hence we need to fix | |
1924 | * things up similar to emitting the lazy request. The difference here | |
1925 | * is that the flush _must_ happen before the next request, no matter | |
1926 | * what. | |
1927 | */ | |
a7b9761d CW |
1928 | ret = intel_ring_flush_all_caches(ring); |
1929 | if (ret) | |
1930 | return ret; | |
cc889e0f | 1931 | |
3bb73aba CW |
1932 | if (request == NULL) { |
1933 | request = kmalloc(sizeof(*request), GFP_KERNEL); | |
1934 | if (request == NULL) | |
1935 | return -ENOMEM; | |
1936 | } | |
1937 | ||
53d227f2 | 1938 | seqno = i915_gem_next_request_seqno(ring); |
673a394b | 1939 | |
a71d8d94 CW |
1940 | /* Record the position of the start of the request so that |
1941 | * should we detect the updated seqno part-way through the | |
1942 | * GPU processing the request, we never over-estimate the | |
1943 | * position of the head. | |
1944 | */ | |
1945 | request_ring_position = intel_ring_get_tail(ring); | |
1946 | ||
3cce469c | 1947 | ret = ring->add_request(ring, &seqno); |
3bb73aba CW |
1948 | if (ret) { |
1949 | kfree(request); | |
1950 | return ret; | |
1951 | } | |
673a394b | 1952 | |
db53a302 | 1953 | trace_i915_gem_request_add(ring, seqno); |
673a394b EA |
1954 | |
1955 | request->seqno = seqno; | |
852835f3 | 1956 | request->ring = ring; |
a71d8d94 | 1957 | request->tail = request_ring_position; |
673a394b | 1958 | request->emitted_jiffies = jiffies; |
852835f3 ZN |
1959 | was_empty = list_empty(&ring->request_list); |
1960 | list_add_tail(&request->list, &ring->request_list); | |
3bb73aba | 1961 | request->file_priv = NULL; |
852835f3 | 1962 | |
db53a302 CW |
1963 | if (file) { |
1964 | struct drm_i915_file_private *file_priv = file->driver_priv; | |
1965 | ||
1c25595f | 1966 | spin_lock(&file_priv->mm.lock); |
f787a5f5 | 1967 | request->file_priv = file_priv; |
b962442e | 1968 | list_add_tail(&request->client_list, |
f787a5f5 | 1969 | &file_priv->mm.request_list); |
1c25595f | 1970 | spin_unlock(&file_priv->mm.lock); |
b962442e | 1971 | } |
673a394b | 1972 | |
5391d0cf | 1973 | ring->outstanding_lazy_request = 0; |
db53a302 | 1974 | |
f65d9421 | 1975 | if (!dev_priv->mm.suspended) { |
3e0dc6b0 BW |
1976 | if (i915_enable_hangcheck) { |
1977 | mod_timer(&dev_priv->hangcheck_timer, | |
1978 | jiffies + | |
1979 | msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD)); | |
1980 | } | |
f047e395 | 1981 | if (was_empty) { |
b3b079db CW |
1982 | queue_delayed_work(dev_priv->wq, |
1983 | &dev_priv->mm.retire_work, HZ); | |
f047e395 CW |
1984 | intel_mark_busy(dev_priv->dev); |
1985 | } | |
f65d9421 | 1986 | } |
cc889e0f | 1987 | |
3cce469c | 1988 | return 0; |
673a394b EA |
1989 | } |
1990 | ||
f787a5f5 CW |
1991 | static inline void |
1992 | i915_gem_request_remove_from_client(struct drm_i915_gem_request *request) | |
673a394b | 1993 | { |
1c25595f | 1994 | struct drm_i915_file_private *file_priv = request->file_priv; |
673a394b | 1995 | |
1c25595f CW |
1996 | if (!file_priv) |
1997 | return; | |
1c5d22f7 | 1998 | |
1c25595f | 1999 | spin_lock(&file_priv->mm.lock); |
09bfa517 HRK |
2000 | if (request->file_priv) { |
2001 | list_del(&request->client_list); | |
2002 | request->file_priv = NULL; | |
2003 | } | |
1c25595f | 2004 | spin_unlock(&file_priv->mm.lock); |
673a394b | 2005 | } |
673a394b | 2006 | |
dfaae392 CW |
2007 | static void i915_gem_reset_ring_lists(struct drm_i915_private *dev_priv, |
2008 | struct intel_ring_buffer *ring) | |
9375e446 | 2009 | { |
dfaae392 CW |
2010 | while (!list_empty(&ring->request_list)) { |
2011 | struct drm_i915_gem_request *request; | |
673a394b | 2012 | |
dfaae392 CW |
2013 | request = list_first_entry(&ring->request_list, |
2014 | struct drm_i915_gem_request, | |
2015 | list); | |
de151cf6 | 2016 | |
dfaae392 | 2017 | list_del(&request->list); |
f787a5f5 | 2018 | i915_gem_request_remove_from_client(request); |
dfaae392 CW |
2019 | kfree(request); |
2020 | } | |
673a394b | 2021 | |
dfaae392 | 2022 | while (!list_empty(&ring->active_list)) { |
05394f39 | 2023 | struct drm_i915_gem_object *obj; |
9375e446 | 2024 | |
05394f39 CW |
2025 | obj = list_first_entry(&ring->active_list, |
2026 | struct drm_i915_gem_object, | |
2027 | ring_list); | |
9375e446 | 2028 | |
05394f39 | 2029 | i915_gem_object_move_to_inactive(obj); |
673a394b EA |
2030 | } |
2031 | } | |
2032 | ||
312817a3 CW |
2033 | static void i915_gem_reset_fences(struct drm_device *dev) |
2034 | { | |
2035 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2036 | int i; | |
2037 | ||
4b9de737 | 2038 | for (i = 0; i < dev_priv->num_fence_regs; i++) { |
312817a3 | 2039 | struct drm_i915_fence_reg *reg = &dev_priv->fence_regs[i]; |
7d2cb39c | 2040 | |
ada726c7 | 2041 | i915_gem_write_fence(dev, i, NULL); |
7d2cb39c | 2042 | |
ada726c7 CW |
2043 | if (reg->obj) |
2044 | i915_gem_object_fence_lost(reg->obj); | |
7d2cb39c | 2045 | |
ada726c7 CW |
2046 | reg->pin_count = 0; |
2047 | reg->obj = NULL; | |
2048 | INIT_LIST_HEAD(®->lru_list); | |
312817a3 | 2049 | } |
ada726c7 CW |
2050 | |
2051 | INIT_LIST_HEAD(&dev_priv->mm.fence_list); | |
312817a3 CW |
2052 | } |
2053 | ||
069efc1d | 2054 | void i915_gem_reset(struct drm_device *dev) |
673a394b | 2055 | { |
77f01230 | 2056 | struct drm_i915_private *dev_priv = dev->dev_private; |
05394f39 | 2057 | struct drm_i915_gem_object *obj; |
b4519513 | 2058 | struct intel_ring_buffer *ring; |
1ec14ad3 | 2059 | int i; |
673a394b | 2060 | |
b4519513 CW |
2061 | for_each_ring(ring, dev_priv, i) |
2062 | i915_gem_reset_ring_lists(dev_priv, ring); | |
dfaae392 | 2063 | |
dfaae392 CW |
2064 | /* Move everything out of the GPU domains to ensure we do any |
2065 | * necessary invalidation upon reuse. | |
2066 | */ | |
05394f39 | 2067 | list_for_each_entry(obj, |
77f01230 | 2068 | &dev_priv->mm.inactive_list, |
69dc4987 | 2069 | mm_list) |
77f01230 | 2070 | { |
05394f39 | 2071 | obj->base.read_domains &= ~I915_GEM_GPU_DOMAINS; |
77f01230 | 2072 | } |
069efc1d | 2073 | |
6c085a72 | 2074 | |
069efc1d | 2075 | /* The fence registers are invalidated so clear them out */ |
312817a3 | 2076 | i915_gem_reset_fences(dev); |
673a394b EA |
2077 | } |
2078 | ||
2079 | /** | |
2080 | * This function clears the request list as sequence numbers are passed. | |
2081 | */ | |
a71d8d94 | 2082 | void |
db53a302 | 2083 | i915_gem_retire_requests_ring(struct intel_ring_buffer *ring) |
673a394b | 2084 | { |
673a394b | 2085 | uint32_t seqno; |
1ec14ad3 | 2086 | int i; |
673a394b | 2087 | |
db53a302 | 2088 | if (list_empty(&ring->request_list)) |
6c0594a3 KW |
2089 | return; |
2090 | ||
db53a302 | 2091 | WARN_ON(i915_verify_lists(ring->dev)); |
673a394b | 2092 | |
b2eadbc8 | 2093 | seqno = ring->get_seqno(ring, true); |
1ec14ad3 | 2094 | |
076e2c0e | 2095 | for (i = 0; i < ARRAY_SIZE(ring->sync_seqno); i++) |
1ec14ad3 CW |
2096 | if (seqno >= ring->sync_seqno[i]) |
2097 | ring->sync_seqno[i] = 0; | |
2098 | ||
852835f3 | 2099 | while (!list_empty(&ring->request_list)) { |
673a394b | 2100 | struct drm_i915_gem_request *request; |
673a394b | 2101 | |
852835f3 | 2102 | request = list_first_entry(&ring->request_list, |
673a394b EA |
2103 | struct drm_i915_gem_request, |
2104 | list); | |
673a394b | 2105 | |
dfaae392 | 2106 | if (!i915_seqno_passed(seqno, request->seqno)) |
b84d5f0c CW |
2107 | break; |
2108 | ||
db53a302 | 2109 | trace_i915_gem_request_retire(ring, request->seqno); |
a71d8d94 CW |
2110 | /* We know the GPU must have read the request to have |
2111 | * sent us the seqno + interrupt, so use the position | |
2112 | * of tail of the request to update the last known position | |
2113 | * of the GPU head. | |
2114 | */ | |
2115 | ring->last_retired_head = request->tail; | |
b84d5f0c CW |
2116 | |
2117 | list_del(&request->list); | |
f787a5f5 | 2118 | i915_gem_request_remove_from_client(request); |
b84d5f0c CW |
2119 | kfree(request); |
2120 | } | |
673a394b | 2121 | |
b84d5f0c CW |
2122 | /* Move any buffers on the active list that are no longer referenced |
2123 | * by the ringbuffer to the flushing/inactive lists as appropriate. | |
2124 | */ | |
2125 | while (!list_empty(&ring->active_list)) { | |
05394f39 | 2126 | struct drm_i915_gem_object *obj; |
b84d5f0c | 2127 | |
0206e353 | 2128 | obj = list_first_entry(&ring->active_list, |
05394f39 CW |
2129 | struct drm_i915_gem_object, |
2130 | ring_list); | |
673a394b | 2131 | |
0201f1ec | 2132 | if (!i915_seqno_passed(seqno, obj->last_read_seqno)) |
673a394b | 2133 | break; |
b84d5f0c | 2134 | |
65ce3027 | 2135 | i915_gem_object_move_to_inactive(obj); |
673a394b | 2136 | } |
9d34e5db | 2137 | |
db53a302 CW |
2138 | if (unlikely(ring->trace_irq_seqno && |
2139 | i915_seqno_passed(seqno, ring->trace_irq_seqno))) { | |
1ec14ad3 | 2140 | ring->irq_put(ring); |
db53a302 | 2141 | ring->trace_irq_seqno = 0; |
9d34e5db | 2142 | } |
23bc5982 | 2143 | |
db53a302 | 2144 | WARN_ON(i915_verify_lists(ring->dev)); |
673a394b EA |
2145 | } |
2146 | ||
b09a1fec CW |
2147 | void |
2148 | i915_gem_retire_requests(struct drm_device *dev) | |
2149 | { | |
2150 | drm_i915_private_t *dev_priv = dev->dev_private; | |
b4519513 | 2151 | struct intel_ring_buffer *ring; |
1ec14ad3 | 2152 | int i; |
b09a1fec | 2153 | |
b4519513 CW |
2154 | for_each_ring(ring, dev_priv, i) |
2155 | i915_gem_retire_requests_ring(ring); | |
b09a1fec CW |
2156 | } |
2157 | ||
75ef9da2 | 2158 | static void |
673a394b EA |
2159 | i915_gem_retire_work_handler(struct work_struct *work) |
2160 | { | |
2161 | drm_i915_private_t *dev_priv; | |
2162 | struct drm_device *dev; | |
b4519513 | 2163 | struct intel_ring_buffer *ring; |
0a58705b CW |
2164 | bool idle; |
2165 | int i; | |
673a394b EA |
2166 | |
2167 | dev_priv = container_of(work, drm_i915_private_t, | |
2168 | mm.retire_work.work); | |
2169 | dev = dev_priv->dev; | |
2170 | ||
891b48cf CW |
2171 | /* Come back later if the device is busy... */ |
2172 | if (!mutex_trylock(&dev->struct_mutex)) { | |
2173 | queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, HZ); | |
2174 | return; | |
2175 | } | |
2176 | ||
b09a1fec | 2177 | i915_gem_retire_requests(dev); |
d1b851fc | 2178 | |
0a58705b CW |
2179 | /* Send a periodic flush down the ring so we don't hold onto GEM |
2180 | * objects indefinitely. | |
2181 | */ | |
2182 | idle = true; | |
b4519513 | 2183 | for_each_ring(ring, dev_priv, i) { |
3bb73aba CW |
2184 | if (ring->gpu_caches_dirty) |
2185 | i915_add_request(ring, NULL, NULL); | |
0a58705b CW |
2186 | |
2187 | idle &= list_empty(&ring->request_list); | |
2188 | } | |
2189 | ||
2190 | if (!dev_priv->mm.suspended && !idle) | |
9c9fe1f8 | 2191 | queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, HZ); |
f047e395 CW |
2192 | if (idle) |
2193 | intel_mark_idle(dev); | |
0a58705b | 2194 | |
673a394b EA |
2195 | mutex_unlock(&dev->struct_mutex); |
2196 | } | |
2197 | ||
30dfebf3 DV |
2198 | /** |
2199 | * Ensures that an object will eventually get non-busy by flushing any required | |
2200 | * write domains, emitting any outstanding lazy request and retiring and | |
2201 | * completed requests. | |
2202 | */ | |
2203 | static int | |
2204 | i915_gem_object_flush_active(struct drm_i915_gem_object *obj) | |
2205 | { | |
2206 | int ret; | |
2207 | ||
2208 | if (obj->active) { | |
0201f1ec | 2209 | ret = i915_gem_check_olr(obj->ring, obj->last_read_seqno); |
30dfebf3 DV |
2210 | if (ret) |
2211 | return ret; | |
0201f1ec | 2212 | |
30dfebf3 DV |
2213 | i915_gem_retire_requests_ring(obj->ring); |
2214 | } | |
2215 | ||
2216 | return 0; | |
2217 | } | |
2218 | ||
23ba4fd0 BW |
2219 | /** |
2220 | * i915_gem_wait_ioctl - implements DRM_IOCTL_I915_GEM_WAIT | |
2221 | * @DRM_IOCTL_ARGS: standard ioctl arguments | |
2222 | * | |
2223 | * Returns 0 if successful, else an error is returned with the remaining time in | |
2224 | * the timeout parameter. | |
2225 | * -ETIME: object is still busy after timeout | |
2226 | * -ERESTARTSYS: signal interrupted the wait | |
2227 | * -ENONENT: object doesn't exist | |
2228 | * Also possible, but rare: | |
2229 | * -EAGAIN: GPU wedged | |
2230 | * -ENOMEM: damn | |
2231 | * -ENODEV: Internal IRQ fail | |
2232 | * -E?: The add request failed | |
2233 | * | |
2234 | * The wait ioctl with a timeout of 0 reimplements the busy ioctl. With any | |
2235 | * non-zero timeout parameter the wait ioctl will wait for the given number of | |
2236 | * nanoseconds on an object becoming unbusy. Since the wait itself does so | |
2237 | * without holding struct_mutex the object may become re-busied before this | |
2238 | * function completes. A similar but shorter * race condition exists in the busy | |
2239 | * ioctl | |
2240 | */ | |
2241 | int | |
2242 | i915_gem_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *file) | |
2243 | { | |
2244 | struct drm_i915_gem_wait *args = data; | |
2245 | struct drm_i915_gem_object *obj; | |
2246 | struct intel_ring_buffer *ring = NULL; | |
eac1f14f | 2247 | struct timespec timeout_stack, *timeout = NULL; |
23ba4fd0 BW |
2248 | u32 seqno = 0; |
2249 | int ret = 0; | |
2250 | ||
eac1f14f BW |
2251 | if (args->timeout_ns >= 0) { |
2252 | timeout_stack = ns_to_timespec(args->timeout_ns); | |
2253 | timeout = &timeout_stack; | |
2254 | } | |
23ba4fd0 BW |
2255 | |
2256 | ret = i915_mutex_lock_interruptible(dev); | |
2257 | if (ret) | |
2258 | return ret; | |
2259 | ||
2260 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->bo_handle)); | |
2261 | if (&obj->base == NULL) { | |
2262 | mutex_unlock(&dev->struct_mutex); | |
2263 | return -ENOENT; | |
2264 | } | |
2265 | ||
30dfebf3 DV |
2266 | /* Need to make sure the object gets inactive eventually. */ |
2267 | ret = i915_gem_object_flush_active(obj); | |
23ba4fd0 BW |
2268 | if (ret) |
2269 | goto out; | |
2270 | ||
2271 | if (obj->active) { | |
0201f1ec | 2272 | seqno = obj->last_read_seqno; |
23ba4fd0 BW |
2273 | ring = obj->ring; |
2274 | } | |
2275 | ||
2276 | if (seqno == 0) | |
2277 | goto out; | |
2278 | ||
23ba4fd0 BW |
2279 | /* Do this after OLR check to make sure we make forward progress polling |
2280 | * on this IOCTL with a 0 timeout (like busy ioctl) | |
2281 | */ | |
2282 | if (!args->timeout_ns) { | |
2283 | ret = -ETIME; | |
2284 | goto out; | |
2285 | } | |
2286 | ||
2287 | drm_gem_object_unreference(&obj->base); | |
2288 | mutex_unlock(&dev->struct_mutex); | |
2289 | ||
eac1f14f BW |
2290 | ret = __wait_seqno(ring, seqno, true, timeout); |
2291 | if (timeout) { | |
2292 | WARN_ON(!timespec_valid(timeout)); | |
2293 | args->timeout_ns = timespec_to_ns(timeout); | |
2294 | } | |
23ba4fd0 BW |
2295 | return ret; |
2296 | ||
2297 | out: | |
2298 | drm_gem_object_unreference(&obj->base); | |
2299 | mutex_unlock(&dev->struct_mutex); | |
2300 | return ret; | |
2301 | } | |
2302 | ||
5816d648 BW |
2303 | /** |
2304 | * i915_gem_object_sync - sync an object to a ring. | |
2305 | * | |
2306 | * @obj: object which may be in use on another ring. | |
2307 | * @to: ring we wish to use the object on. May be NULL. | |
2308 | * | |
2309 | * This code is meant to abstract object synchronization with the GPU. | |
2310 | * Calling with NULL implies synchronizing the object with the CPU | |
2311 | * rather than a particular GPU ring. | |
2312 | * | |
2313 | * Returns 0 if successful, else propagates up the lower layer error. | |
2314 | */ | |
2911a35b BW |
2315 | int |
2316 | i915_gem_object_sync(struct drm_i915_gem_object *obj, | |
2317 | struct intel_ring_buffer *to) | |
2318 | { | |
2319 | struct intel_ring_buffer *from = obj->ring; | |
2320 | u32 seqno; | |
2321 | int ret, idx; | |
2322 | ||
2323 | if (from == NULL || to == from) | |
2324 | return 0; | |
2325 | ||
5816d648 | 2326 | if (to == NULL || !i915_semaphore_is_enabled(obj->base.dev)) |
0201f1ec | 2327 | return i915_gem_object_wait_rendering(obj, false); |
2911a35b BW |
2328 | |
2329 | idx = intel_ring_sync_index(from, to); | |
2330 | ||
0201f1ec | 2331 | seqno = obj->last_read_seqno; |
2911a35b BW |
2332 | if (seqno <= from->sync_seqno[idx]) |
2333 | return 0; | |
2334 | ||
b4aca010 BW |
2335 | ret = i915_gem_check_olr(obj->ring, seqno); |
2336 | if (ret) | |
2337 | return ret; | |
2911a35b | 2338 | |
1500f7ea | 2339 | ret = to->sync_to(to, from, seqno); |
e3a5a225 BW |
2340 | if (!ret) |
2341 | from->sync_seqno[idx] = seqno; | |
2911a35b | 2342 | |
e3a5a225 | 2343 | return ret; |
2911a35b BW |
2344 | } |
2345 | ||
b5ffc9bc CW |
2346 | static void i915_gem_object_finish_gtt(struct drm_i915_gem_object *obj) |
2347 | { | |
2348 | u32 old_write_domain, old_read_domains; | |
2349 | ||
b5ffc9bc CW |
2350 | /* Act a barrier for all accesses through the GTT */ |
2351 | mb(); | |
2352 | ||
2353 | /* Force a pagefault for domain tracking on next user access */ | |
2354 | i915_gem_release_mmap(obj); | |
2355 | ||
b97c3d9c KP |
2356 | if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0) |
2357 | return; | |
2358 | ||
b5ffc9bc CW |
2359 | old_read_domains = obj->base.read_domains; |
2360 | old_write_domain = obj->base.write_domain; | |
2361 | ||
2362 | obj->base.read_domains &= ~I915_GEM_DOMAIN_GTT; | |
2363 | obj->base.write_domain &= ~I915_GEM_DOMAIN_GTT; | |
2364 | ||
2365 | trace_i915_gem_object_change_domain(obj, | |
2366 | old_read_domains, | |
2367 | old_write_domain); | |
2368 | } | |
2369 | ||
673a394b EA |
2370 | /** |
2371 | * Unbinds an object from the GTT aperture. | |
2372 | */ | |
0f973f27 | 2373 | int |
05394f39 | 2374 | i915_gem_object_unbind(struct drm_i915_gem_object *obj) |
673a394b | 2375 | { |
7bddb01f | 2376 | drm_i915_private_t *dev_priv = obj->base.dev->dev_private; |
673a394b EA |
2377 | int ret = 0; |
2378 | ||
05394f39 | 2379 | if (obj->gtt_space == NULL) |
673a394b EA |
2380 | return 0; |
2381 | ||
31d8d651 CW |
2382 | if (obj->pin_count) |
2383 | return -EBUSY; | |
673a394b | 2384 | |
c4670ad0 CW |
2385 | BUG_ON(obj->pages == NULL); |
2386 | ||
a8198eea | 2387 | ret = i915_gem_object_finish_gpu(obj); |
1488fc08 | 2388 | if (ret) |
a8198eea CW |
2389 | return ret; |
2390 | /* Continue on if we fail due to EIO, the GPU is hung so we | |
2391 | * should be safe and we need to cleanup or else we might | |
2392 | * cause memory corruption through use-after-free. | |
2393 | */ | |
2394 | ||
b5ffc9bc | 2395 | i915_gem_object_finish_gtt(obj); |
5323fd04 | 2396 | |
96b47b65 | 2397 | /* release the fence reg _after_ flushing */ |
d9e86c0e | 2398 | ret = i915_gem_object_put_fence(obj); |
1488fc08 | 2399 | if (ret) |
d9e86c0e | 2400 | return ret; |
96b47b65 | 2401 | |
db53a302 CW |
2402 | trace_i915_gem_object_unbind(obj); |
2403 | ||
74898d7e DV |
2404 | if (obj->has_global_gtt_mapping) |
2405 | i915_gem_gtt_unbind_object(obj); | |
7bddb01f DV |
2406 | if (obj->has_aliasing_ppgtt_mapping) { |
2407 | i915_ppgtt_unbind_object(dev_priv->mm.aliasing_ppgtt, obj); | |
2408 | obj->has_aliasing_ppgtt_mapping = 0; | |
2409 | } | |
74163907 | 2410 | i915_gem_gtt_finish_object(obj); |
7bddb01f | 2411 | |
6c085a72 CW |
2412 | list_del(&obj->mm_list); |
2413 | list_move_tail(&obj->gtt_list, &dev_priv->mm.unbound_list); | |
75e9e915 | 2414 | /* Avoid an unnecessary call to unbind on rebind. */ |
05394f39 | 2415 | obj->map_and_fenceable = true; |
673a394b | 2416 | |
05394f39 CW |
2417 | drm_mm_put_block(obj->gtt_space); |
2418 | obj->gtt_space = NULL; | |
2419 | obj->gtt_offset = 0; | |
673a394b | 2420 | |
6c085a72 | 2421 | return 0; |
673a394b EA |
2422 | } |
2423 | ||
b2da9fe5 | 2424 | static int i915_ring_idle(struct intel_ring_buffer *ring) |
a56ba56c | 2425 | { |
69c2fc89 | 2426 | if (list_empty(&ring->active_list)) |
64193406 CW |
2427 | return 0; |
2428 | ||
199b2bc2 | 2429 | return i915_wait_seqno(ring, i915_gem_next_request_seqno(ring)); |
a56ba56c CW |
2430 | } |
2431 | ||
b2da9fe5 | 2432 | int i915_gpu_idle(struct drm_device *dev) |
4df2faf4 DV |
2433 | { |
2434 | drm_i915_private_t *dev_priv = dev->dev_private; | |
b4519513 | 2435 | struct intel_ring_buffer *ring; |
1ec14ad3 | 2436 | int ret, i; |
4df2faf4 | 2437 | |
4df2faf4 | 2438 | /* Flush everything onto the inactive list. */ |
b4519513 CW |
2439 | for_each_ring(ring, dev_priv, i) { |
2440 | ret = i915_ring_idle(ring); | |
1ec14ad3 CW |
2441 | if (ret) |
2442 | return ret; | |
b4519513 | 2443 | |
f2ef6eb1 BW |
2444 | ret = i915_switch_context(ring, NULL, DEFAULT_CONTEXT_ID); |
2445 | if (ret) | |
2446 | return ret; | |
1ec14ad3 | 2447 | } |
4df2faf4 | 2448 | |
8a1a49f9 | 2449 | return 0; |
4df2faf4 DV |
2450 | } |
2451 | ||
9ce079e4 CW |
2452 | static void sandybridge_write_fence_reg(struct drm_device *dev, int reg, |
2453 | struct drm_i915_gem_object *obj) | |
4e901fdc | 2454 | { |
4e901fdc | 2455 | drm_i915_private_t *dev_priv = dev->dev_private; |
4e901fdc EA |
2456 | uint64_t val; |
2457 | ||
9ce079e4 CW |
2458 | if (obj) { |
2459 | u32 size = obj->gtt_space->size; | |
4e901fdc | 2460 | |
9ce079e4 CW |
2461 | val = (uint64_t)((obj->gtt_offset + size - 4096) & |
2462 | 0xfffff000) << 32; | |
2463 | val |= obj->gtt_offset & 0xfffff000; | |
2464 | val |= (uint64_t)((obj->stride / 128) - 1) << | |
2465 | SANDYBRIDGE_FENCE_PITCH_SHIFT; | |
4e901fdc | 2466 | |
9ce079e4 CW |
2467 | if (obj->tiling_mode == I915_TILING_Y) |
2468 | val |= 1 << I965_FENCE_TILING_Y_SHIFT; | |
2469 | val |= I965_FENCE_REG_VALID; | |
2470 | } else | |
2471 | val = 0; | |
c6642782 | 2472 | |
9ce079e4 CW |
2473 | I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + reg * 8, val); |
2474 | POSTING_READ(FENCE_REG_SANDYBRIDGE_0 + reg * 8); | |
4e901fdc EA |
2475 | } |
2476 | ||
9ce079e4 CW |
2477 | static void i965_write_fence_reg(struct drm_device *dev, int reg, |
2478 | struct drm_i915_gem_object *obj) | |
de151cf6 | 2479 | { |
de151cf6 | 2480 | drm_i915_private_t *dev_priv = dev->dev_private; |
de151cf6 JB |
2481 | uint64_t val; |
2482 | ||
9ce079e4 CW |
2483 | if (obj) { |
2484 | u32 size = obj->gtt_space->size; | |
de151cf6 | 2485 | |
9ce079e4 CW |
2486 | val = (uint64_t)((obj->gtt_offset + size - 4096) & |
2487 | 0xfffff000) << 32; | |
2488 | val |= obj->gtt_offset & 0xfffff000; | |
2489 | val |= ((obj->stride / 128) - 1) << I965_FENCE_PITCH_SHIFT; | |
2490 | if (obj->tiling_mode == I915_TILING_Y) | |
2491 | val |= 1 << I965_FENCE_TILING_Y_SHIFT; | |
2492 | val |= I965_FENCE_REG_VALID; | |
2493 | } else | |
2494 | val = 0; | |
c6642782 | 2495 | |
9ce079e4 CW |
2496 | I915_WRITE64(FENCE_REG_965_0 + reg * 8, val); |
2497 | POSTING_READ(FENCE_REG_965_0 + reg * 8); | |
de151cf6 JB |
2498 | } |
2499 | ||
9ce079e4 CW |
2500 | static void i915_write_fence_reg(struct drm_device *dev, int reg, |
2501 | struct drm_i915_gem_object *obj) | |
de151cf6 | 2502 | { |
de151cf6 | 2503 | drm_i915_private_t *dev_priv = dev->dev_private; |
9ce079e4 | 2504 | u32 val; |
de151cf6 | 2505 | |
9ce079e4 CW |
2506 | if (obj) { |
2507 | u32 size = obj->gtt_space->size; | |
2508 | int pitch_val; | |
2509 | int tile_width; | |
c6642782 | 2510 | |
9ce079e4 CW |
2511 | WARN((obj->gtt_offset & ~I915_FENCE_START_MASK) || |
2512 | (size & -size) != size || | |
2513 | (obj->gtt_offset & (size - 1)), | |
2514 | "object 0x%08x [fenceable? %d] not 1M or pot-size (0x%08x) aligned\n", | |
2515 | obj->gtt_offset, obj->map_and_fenceable, size); | |
c6642782 | 2516 | |
9ce079e4 CW |
2517 | if (obj->tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev)) |
2518 | tile_width = 128; | |
2519 | else | |
2520 | tile_width = 512; | |
2521 | ||
2522 | /* Note: pitch better be a power of two tile widths */ | |
2523 | pitch_val = obj->stride / tile_width; | |
2524 | pitch_val = ffs(pitch_val) - 1; | |
2525 | ||
2526 | val = obj->gtt_offset; | |
2527 | if (obj->tiling_mode == I915_TILING_Y) | |
2528 | val |= 1 << I830_FENCE_TILING_Y_SHIFT; | |
2529 | val |= I915_FENCE_SIZE_BITS(size); | |
2530 | val |= pitch_val << I830_FENCE_PITCH_SHIFT; | |
2531 | val |= I830_FENCE_REG_VALID; | |
2532 | } else | |
2533 | val = 0; | |
2534 | ||
2535 | if (reg < 8) | |
2536 | reg = FENCE_REG_830_0 + reg * 4; | |
2537 | else | |
2538 | reg = FENCE_REG_945_8 + (reg - 8) * 4; | |
2539 | ||
2540 | I915_WRITE(reg, val); | |
2541 | POSTING_READ(reg); | |
de151cf6 JB |
2542 | } |
2543 | ||
9ce079e4 CW |
2544 | static void i830_write_fence_reg(struct drm_device *dev, int reg, |
2545 | struct drm_i915_gem_object *obj) | |
de151cf6 | 2546 | { |
de151cf6 | 2547 | drm_i915_private_t *dev_priv = dev->dev_private; |
de151cf6 | 2548 | uint32_t val; |
de151cf6 | 2549 | |
9ce079e4 CW |
2550 | if (obj) { |
2551 | u32 size = obj->gtt_space->size; | |
2552 | uint32_t pitch_val; | |
de151cf6 | 2553 | |
9ce079e4 CW |
2554 | WARN((obj->gtt_offset & ~I830_FENCE_START_MASK) || |
2555 | (size & -size) != size || | |
2556 | (obj->gtt_offset & (size - 1)), | |
2557 | "object 0x%08x not 512K or pot-size 0x%08x aligned\n", | |
2558 | obj->gtt_offset, size); | |
e76a16de | 2559 | |
9ce079e4 CW |
2560 | pitch_val = obj->stride / 128; |
2561 | pitch_val = ffs(pitch_val) - 1; | |
de151cf6 | 2562 | |
9ce079e4 CW |
2563 | val = obj->gtt_offset; |
2564 | if (obj->tiling_mode == I915_TILING_Y) | |
2565 | val |= 1 << I830_FENCE_TILING_Y_SHIFT; | |
2566 | val |= I830_FENCE_SIZE_BITS(size); | |
2567 | val |= pitch_val << I830_FENCE_PITCH_SHIFT; | |
2568 | val |= I830_FENCE_REG_VALID; | |
2569 | } else | |
2570 | val = 0; | |
c6642782 | 2571 | |
9ce079e4 CW |
2572 | I915_WRITE(FENCE_REG_830_0 + reg * 4, val); |
2573 | POSTING_READ(FENCE_REG_830_0 + reg * 4); | |
2574 | } | |
2575 | ||
2576 | static void i915_gem_write_fence(struct drm_device *dev, int reg, | |
2577 | struct drm_i915_gem_object *obj) | |
2578 | { | |
2579 | switch (INTEL_INFO(dev)->gen) { | |
2580 | case 7: | |
2581 | case 6: sandybridge_write_fence_reg(dev, reg, obj); break; | |
2582 | case 5: | |
2583 | case 4: i965_write_fence_reg(dev, reg, obj); break; | |
2584 | case 3: i915_write_fence_reg(dev, reg, obj); break; | |
2585 | case 2: i830_write_fence_reg(dev, reg, obj); break; | |
2586 | default: break; | |
2587 | } | |
de151cf6 JB |
2588 | } |
2589 | ||
61050808 CW |
2590 | static inline int fence_number(struct drm_i915_private *dev_priv, |
2591 | struct drm_i915_fence_reg *fence) | |
2592 | { | |
2593 | return fence - dev_priv->fence_regs; | |
2594 | } | |
2595 | ||
2596 | static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj, | |
2597 | struct drm_i915_fence_reg *fence, | |
2598 | bool enable) | |
2599 | { | |
2600 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; | |
2601 | int reg = fence_number(dev_priv, fence); | |
2602 | ||
2603 | i915_gem_write_fence(obj->base.dev, reg, enable ? obj : NULL); | |
2604 | ||
2605 | if (enable) { | |
2606 | obj->fence_reg = reg; | |
2607 | fence->obj = obj; | |
2608 | list_move_tail(&fence->lru_list, &dev_priv->mm.fence_list); | |
2609 | } else { | |
2610 | obj->fence_reg = I915_FENCE_REG_NONE; | |
2611 | fence->obj = NULL; | |
2612 | list_del_init(&fence->lru_list); | |
2613 | } | |
2614 | } | |
2615 | ||
d9e86c0e | 2616 | static int |
a360bb1a | 2617 | i915_gem_object_flush_fence(struct drm_i915_gem_object *obj) |
d9e86c0e | 2618 | { |
1c293ea3 | 2619 | if (obj->last_fenced_seqno) { |
86d5bc37 | 2620 | int ret = i915_wait_seqno(obj->ring, obj->last_fenced_seqno); |
18991845 CW |
2621 | if (ret) |
2622 | return ret; | |
d9e86c0e CW |
2623 | |
2624 | obj->last_fenced_seqno = 0; | |
d9e86c0e CW |
2625 | } |
2626 | ||
63256ec5 CW |
2627 | /* Ensure that all CPU reads are completed before installing a fence |
2628 | * and all writes before removing the fence. | |
2629 | */ | |
2630 | if (obj->base.read_domains & I915_GEM_DOMAIN_GTT) | |
2631 | mb(); | |
2632 | ||
86d5bc37 | 2633 | obj->fenced_gpu_access = false; |
d9e86c0e CW |
2634 | return 0; |
2635 | } | |
2636 | ||
2637 | int | |
2638 | i915_gem_object_put_fence(struct drm_i915_gem_object *obj) | |
2639 | { | |
61050808 | 2640 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
d9e86c0e CW |
2641 | int ret; |
2642 | ||
a360bb1a | 2643 | ret = i915_gem_object_flush_fence(obj); |
d9e86c0e CW |
2644 | if (ret) |
2645 | return ret; | |
2646 | ||
61050808 CW |
2647 | if (obj->fence_reg == I915_FENCE_REG_NONE) |
2648 | return 0; | |
d9e86c0e | 2649 | |
61050808 CW |
2650 | i915_gem_object_update_fence(obj, |
2651 | &dev_priv->fence_regs[obj->fence_reg], | |
2652 | false); | |
2653 | i915_gem_object_fence_lost(obj); | |
d9e86c0e CW |
2654 | |
2655 | return 0; | |
2656 | } | |
2657 | ||
2658 | static struct drm_i915_fence_reg * | |
a360bb1a | 2659 | i915_find_fence_reg(struct drm_device *dev) |
ae3db24a | 2660 | { |
ae3db24a | 2661 | struct drm_i915_private *dev_priv = dev->dev_private; |
8fe301ad | 2662 | struct drm_i915_fence_reg *reg, *avail; |
d9e86c0e | 2663 | int i; |
ae3db24a DV |
2664 | |
2665 | /* First try to find a free reg */ | |
d9e86c0e | 2666 | avail = NULL; |
ae3db24a DV |
2667 | for (i = dev_priv->fence_reg_start; i < dev_priv->num_fence_regs; i++) { |
2668 | reg = &dev_priv->fence_regs[i]; | |
2669 | if (!reg->obj) | |
d9e86c0e | 2670 | return reg; |
ae3db24a | 2671 | |
1690e1eb | 2672 | if (!reg->pin_count) |
d9e86c0e | 2673 | avail = reg; |
ae3db24a DV |
2674 | } |
2675 | ||
d9e86c0e CW |
2676 | if (avail == NULL) |
2677 | return NULL; | |
ae3db24a DV |
2678 | |
2679 | /* None available, try to steal one or wait for a user to finish */ | |
d9e86c0e | 2680 | list_for_each_entry(reg, &dev_priv->mm.fence_list, lru_list) { |
1690e1eb | 2681 | if (reg->pin_count) |
ae3db24a DV |
2682 | continue; |
2683 | ||
8fe301ad | 2684 | return reg; |
ae3db24a DV |
2685 | } |
2686 | ||
8fe301ad | 2687 | return NULL; |
ae3db24a DV |
2688 | } |
2689 | ||
de151cf6 | 2690 | /** |
9a5a53b3 | 2691 | * i915_gem_object_get_fence - set up fencing for an object |
de151cf6 JB |
2692 | * @obj: object to map through a fence reg |
2693 | * | |
2694 | * When mapping objects through the GTT, userspace wants to be able to write | |
2695 | * to them without having to worry about swizzling if the object is tiled. | |
de151cf6 JB |
2696 | * This function walks the fence regs looking for a free one for @obj, |
2697 | * stealing one if it can't find any. | |
2698 | * | |
2699 | * It then sets up the reg based on the object's properties: address, pitch | |
2700 | * and tiling format. | |
9a5a53b3 CW |
2701 | * |
2702 | * For an untiled surface, this removes any existing fence. | |
de151cf6 | 2703 | */ |
8c4b8c3f | 2704 | int |
06d98131 | 2705 | i915_gem_object_get_fence(struct drm_i915_gem_object *obj) |
de151cf6 | 2706 | { |
05394f39 | 2707 | struct drm_device *dev = obj->base.dev; |
79e53945 | 2708 | struct drm_i915_private *dev_priv = dev->dev_private; |
14415745 | 2709 | bool enable = obj->tiling_mode != I915_TILING_NONE; |
d9e86c0e | 2710 | struct drm_i915_fence_reg *reg; |
ae3db24a | 2711 | int ret; |
de151cf6 | 2712 | |
14415745 CW |
2713 | /* Have we updated the tiling parameters upon the object and so |
2714 | * will need to serialise the write to the associated fence register? | |
2715 | */ | |
5d82e3e6 | 2716 | if (obj->fence_dirty) { |
14415745 CW |
2717 | ret = i915_gem_object_flush_fence(obj); |
2718 | if (ret) | |
2719 | return ret; | |
2720 | } | |
9a5a53b3 | 2721 | |
d9e86c0e | 2722 | /* Just update our place in the LRU if our fence is getting reused. */ |
05394f39 CW |
2723 | if (obj->fence_reg != I915_FENCE_REG_NONE) { |
2724 | reg = &dev_priv->fence_regs[obj->fence_reg]; | |
5d82e3e6 | 2725 | if (!obj->fence_dirty) { |
14415745 CW |
2726 | list_move_tail(®->lru_list, |
2727 | &dev_priv->mm.fence_list); | |
2728 | return 0; | |
2729 | } | |
2730 | } else if (enable) { | |
2731 | reg = i915_find_fence_reg(dev); | |
2732 | if (reg == NULL) | |
2733 | return -EDEADLK; | |
d9e86c0e | 2734 | |
14415745 CW |
2735 | if (reg->obj) { |
2736 | struct drm_i915_gem_object *old = reg->obj; | |
2737 | ||
2738 | ret = i915_gem_object_flush_fence(old); | |
29c5a587 CW |
2739 | if (ret) |
2740 | return ret; | |
2741 | ||
14415745 | 2742 | i915_gem_object_fence_lost(old); |
29c5a587 | 2743 | } |
14415745 | 2744 | } else |
a09ba7fa | 2745 | return 0; |
a09ba7fa | 2746 | |
14415745 | 2747 | i915_gem_object_update_fence(obj, reg, enable); |
5d82e3e6 | 2748 | obj->fence_dirty = false; |
14415745 | 2749 | |
9ce079e4 | 2750 | return 0; |
de151cf6 JB |
2751 | } |
2752 | ||
42d6ab48 CW |
2753 | static bool i915_gem_valid_gtt_space(struct drm_device *dev, |
2754 | struct drm_mm_node *gtt_space, | |
2755 | unsigned long cache_level) | |
2756 | { | |
2757 | struct drm_mm_node *other; | |
2758 | ||
2759 | /* On non-LLC machines we have to be careful when putting differing | |
2760 | * types of snoopable memory together to avoid the prefetcher | |
2761 | * crossing memory domains and dieing. | |
2762 | */ | |
2763 | if (HAS_LLC(dev)) | |
2764 | return true; | |
2765 | ||
2766 | if (gtt_space == NULL) | |
2767 | return true; | |
2768 | ||
2769 | if (list_empty(>t_space->node_list)) | |
2770 | return true; | |
2771 | ||
2772 | other = list_entry(gtt_space->node_list.prev, struct drm_mm_node, node_list); | |
2773 | if (other->allocated && !other->hole_follows && other->color != cache_level) | |
2774 | return false; | |
2775 | ||
2776 | other = list_entry(gtt_space->node_list.next, struct drm_mm_node, node_list); | |
2777 | if (other->allocated && !gtt_space->hole_follows && other->color != cache_level) | |
2778 | return false; | |
2779 | ||
2780 | return true; | |
2781 | } | |
2782 | ||
2783 | static void i915_gem_verify_gtt(struct drm_device *dev) | |
2784 | { | |
2785 | #if WATCH_GTT | |
2786 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2787 | struct drm_i915_gem_object *obj; | |
2788 | int err = 0; | |
2789 | ||
2790 | list_for_each_entry(obj, &dev_priv->mm.gtt_list, gtt_list) { | |
2791 | if (obj->gtt_space == NULL) { | |
2792 | printk(KERN_ERR "object found on GTT list with no space reserved\n"); | |
2793 | err++; | |
2794 | continue; | |
2795 | } | |
2796 | ||
2797 | if (obj->cache_level != obj->gtt_space->color) { | |
2798 | printk(KERN_ERR "object reserved space [%08lx, %08lx] with wrong color, cache_level=%x, color=%lx\n", | |
2799 | obj->gtt_space->start, | |
2800 | obj->gtt_space->start + obj->gtt_space->size, | |
2801 | obj->cache_level, | |
2802 | obj->gtt_space->color); | |
2803 | err++; | |
2804 | continue; | |
2805 | } | |
2806 | ||
2807 | if (!i915_gem_valid_gtt_space(dev, | |
2808 | obj->gtt_space, | |
2809 | obj->cache_level)) { | |
2810 | printk(KERN_ERR "invalid GTT space found at [%08lx, %08lx] - color=%x\n", | |
2811 | obj->gtt_space->start, | |
2812 | obj->gtt_space->start + obj->gtt_space->size, | |
2813 | obj->cache_level); | |
2814 | err++; | |
2815 | continue; | |
2816 | } | |
2817 | } | |
2818 | ||
2819 | WARN_ON(err); | |
2820 | #endif | |
2821 | } | |
2822 | ||
673a394b EA |
2823 | /** |
2824 | * Finds free space in the GTT aperture and binds the object there. | |
2825 | */ | |
2826 | static int | |
05394f39 | 2827 | i915_gem_object_bind_to_gtt(struct drm_i915_gem_object *obj, |
920afa77 | 2828 | unsigned alignment, |
86a1ee26 CW |
2829 | bool map_and_fenceable, |
2830 | bool nonblocking) | |
673a394b | 2831 | { |
05394f39 | 2832 | struct drm_device *dev = obj->base.dev; |
673a394b | 2833 | drm_i915_private_t *dev_priv = dev->dev_private; |
673a394b | 2834 | struct drm_mm_node *free_space; |
5e783301 | 2835 | u32 size, fence_size, fence_alignment, unfenced_alignment; |
75e9e915 | 2836 | bool mappable, fenceable; |
07f73f69 | 2837 | int ret; |
673a394b | 2838 | |
05394f39 | 2839 | if (obj->madv != I915_MADV_WILLNEED) { |
3ef94daa CW |
2840 | DRM_ERROR("Attempting to bind a purgeable object\n"); |
2841 | return -EINVAL; | |
2842 | } | |
2843 | ||
e28f8711 CW |
2844 | fence_size = i915_gem_get_gtt_size(dev, |
2845 | obj->base.size, | |
2846 | obj->tiling_mode); | |
2847 | fence_alignment = i915_gem_get_gtt_alignment(dev, | |
2848 | obj->base.size, | |
2849 | obj->tiling_mode); | |
2850 | unfenced_alignment = | |
2851 | i915_gem_get_unfenced_gtt_alignment(dev, | |
2852 | obj->base.size, | |
2853 | obj->tiling_mode); | |
a00b10c3 | 2854 | |
673a394b | 2855 | if (alignment == 0) |
5e783301 DV |
2856 | alignment = map_and_fenceable ? fence_alignment : |
2857 | unfenced_alignment; | |
75e9e915 | 2858 | if (map_and_fenceable && alignment & (fence_alignment - 1)) { |
673a394b EA |
2859 | DRM_ERROR("Invalid object alignment requested %u\n", alignment); |
2860 | return -EINVAL; | |
2861 | } | |
2862 | ||
05394f39 | 2863 | size = map_and_fenceable ? fence_size : obj->base.size; |
a00b10c3 | 2864 | |
654fc607 CW |
2865 | /* If the object is bigger than the entire aperture, reject it early |
2866 | * before evicting everything in a vain attempt to find space. | |
2867 | */ | |
05394f39 | 2868 | if (obj->base.size > |
75e9e915 | 2869 | (map_and_fenceable ? dev_priv->mm.gtt_mappable_end : dev_priv->mm.gtt_total)) { |
654fc607 CW |
2870 | DRM_ERROR("Attempting to bind an object larger than the aperture\n"); |
2871 | return -E2BIG; | |
2872 | } | |
2873 | ||
6c085a72 CW |
2874 | ret = i915_gem_object_get_pages_gtt(obj); |
2875 | if (ret) | |
2876 | return ret; | |
2877 | ||
673a394b | 2878 | search_free: |
75e9e915 | 2879 | if (map_and_fenceable) |
920afa77 | 2880 | free_space = |
42d6ab48 CW |
2881 | drm_mm_search_free_in_range_color(&dev_priv->mm.gtt_space, |
2882 | size, alignment, obj->cache_level, | |
2883 | 0, dev_priv->mm.gtt_mappable_end, | |
2884 | false); | |
920afa77 | 2885 | else |
42d6ab48 CW |
2886 | free_space = drm_mm_search_free_color(&dev_priv->mm.gtt_space, |
2887 | size, alignment, obj->cache_level, | |
2888 | false); | |
920afa77 DV |
2889 | |
2890 | if (free_space != NULL) { | |
75e9e915 | 2891 | if (map_and_fenceable) |
05394f39 | 2892 | obj->gtt_space = |
920afa77 | 2893 | drm_mm_get_block_range_generic(free_space, |
42d6ab48 | 2894 | size, alignment, obj->cache_level, |
6b9d89b4 | 2895 | 0, dev_priv->mm.gtt_mappable_end, |
42d6ab48 | 2896 | false); |
920afa77 | 2897 | else |
05394f39 | 2898 | obj->gtt_space = |
42d6ab48 CW |
2899 | drm_mm_get_block_generic(free_space, |
2900 | size, alignment, obj->cache_level, | |
2901 | false); | |
920afa77 | 2902 | } |
05394f39 | 2903 | if (obj->gtt_space == NULL) { |
75e9e915 | 2904 | ret = i915_gem_evict_something(dev, size, alignment, |
42d6ab48 | 2905 | obj->cache_level, |
86a1ee26 CW |
2906 | map_and_fenceable, |
2907 | nonblocking); | |
9731129c | 2908 | if (ret) |
673a394b | 2909 | return ret; |
9731129c | 2910 | |
673a394b EA |
2911 | goto search_free; |
2912 | } | |
42d6ab48 CW |
2913 | if (WARN_ON(!i915_gem_valid_gtt_space(dev, |
2914 | obj->gtt_space, | |
2915 | obj->cache_level))) { | |
2916 | drm_mm_put_block(obj->gtt_space); | |
2917 | obj->gtt_space = NULL; | |
2918 | return -EINVAL; | |
2919 | } | |
673a394b | 2920 | |
673a394b | 2921 | |
74163907 | 2922 | ret = i915_gem_gtt_prepare_object(obj); |
7c2e6fdf | 2923 | if (ret) { |
05394f39 CW |
2924 | drm_mm_put_block(obj->gtt_space); |
2925 | obj->gtt_space = NULL; | |
6c085a72 | 2926 | return ret; |
673a394b | 2927 | } |
673a394b | 2928 | |
0ebb9829 DV |
2929 | if (!dev_priv->mm.aliasing_ppgtt) |
2930 | i915_gem_gtt_bind_object(obj, obj->cache_level); | |
673a394b | 2931 | |
6c085a72 | 2932 | list_move_tail(&obj->gtt_list, &dev_priv->mm.bound_list); |
05394f39 | 2933 | list_add_tail(&obj->mm_list, &dev_priv->mm.inactive_list); |
bf1a1092 | 2934 | |
6299f992 | 2935 | obj->gtt_offset = obj->gtt_space->start; |
1c5d22f7 | 2936 | |
75e9e915 | 2937 | fenceable = |
05394f39 | 2938 | obj->gtt_space->size == fence_size && |
0206e353 | 2939 | (obj->gtt_space->start & (fence_alignment - 1)) == 0; |
a00b10c3 | 2940 | |
75e9e915 | 2941 | mappable = |
05394f39 | 2942 | obj->gtt_offset + obj->base.size <= dev_priv->mm.gtt_mappable_end; |
a00b10c3 | 2943 | |
05394f39 | 2944 | obj->map_and_fenceable = mappable && fenceable; |
75e9e915 | 2945 | |
db53a302 | 2946 | trace_i915_gem_object_bind(obj, map_and_fenceable); |
42d6ab48 | 2947 | i915_gem_verify_gtt(dev); |
673a394b EA |
2948 | return 0; |
2949 | } | |
2950 | ||
2951 | void | |
05394f39 | 2952 | i915_gem_clflush_object(struct drm_i915_gem_object *obj) |
673a394b | 2953 | { |
673a394b EA |
2954 | /* If we don't have a page list set up, then we're not pinned |
2955 | * to GPU, and we can ignore the cache flush because it'll happen | |
2956 | * again at bind time. | |
2957 | */ | |
05394f39 | 2958 | if (obj->pages == NULL) |
673a394b EA |
2959 | return; |
2960 | ||
9c23f7fc CW |
2961 | /* If the GPU is snooping the contents of the CPU cache, |
2962 | * we do not need to manually clear the CPU cache lines. However, | |
2963 | * the caches are only snooped when the render cache is | |
2964 | * flushed/invalidated. As we always have to emit invalidations | |
2965 | * and flushes when moving into and out of the RENDER domain, correct | |
2966 | * snooping behaviour occurs naturally as the result of our domain | |
2967 | * tracking. | |
2968 | */ | |
2969 | if (obj->cache_level != I915_CACHE_NONE) | |
2970 | return; | |
2971 | ||
1c5d22f7 | 2972 | trace_i915_gem_object_clflush(obj); |
cfa16a0d | 2973 | |
05394f39 | 2974 | drm_clflush_pages(obj->pages, obj->base.size / PAGE_SIZE); |
673a394b EA |
2975 | } |
2976 | ||
e47c68e9 EA |
2977 | /** Flushes the GTT write domain for the object if it's dirty. */ |
2978 | static void | |
05394f39 | 2979 | i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj) |
e47c68e9 | 2980 | { |
1c5d22f7 CW |
2981 | uint32_t old_write_domain; |
2982 | ||
05394f39 | 2983 | if (obj->base.write_domain != I915_GEM_DOMAIN_GTT) |
e47c68e9 EA |
2984 | return; |
2985 | ||
63256ec5 | 2986 | /* No actual flushing is required for the GTT write domain. Writes |
e47c68e9 EA |
2987 | * to it immediately go to main memory as far as we know, so there's |
2988 | * no chipset flush. It also doesn't land in render cache. | |
63256ec5 CW |
2989 | * |
2990 | * However, we do have to enforce the order so that all writes through | |
2991 | * the GTT land before any writes to the device, such as updates to | |
2992 | * the GATT itself. | |
e47c68e9 | 2993 | */ |
63256ec5 CW |
2994 | wmb(); |
2995 | ||
05394f39 CW |
2996 | old_write_domain = obj->base.write_domain; |
2997 | obj->base.write_domain = 0; | |
1c5d22f7 CW |
2998 | |
2999 | trace_i915_gem_object_change_domain(obj, | |
05394f39 | 3000 | obj->base.read_domains, |
1c5d22f7 | 3001 | old_write_domain); |
e47c68e9 EA |
3002 | } |
3003 | ||
3004 | /** Flushes the CPU write domain for the object if it's dirty. */ | |
3005 | static void | |
05394f39 | 3006 | i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj) |
e47c68e9 | 3007 | { |
1c5d22f7 | 3008 | uint32_t old_write_domain; |
e47c68e9 | 3009 | |
05394f39 | 3010 | if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) |
e47c68e9 EA |
3011 | return; |
3012 | ||
3013 | i915_gem_clflush_object(obj); | |
40ce6575 | 3014 | intel_gtt_chipset_flush(); |
05394f39 CW |
3015 | old_write_domain = obj->base.write_domain; |
3016 | obj->base.write_domain = 0; | |
1c5d22f7 CW |
3017 | |
3018 | trace_i915_gem_object_change_domain(obj, | |
05394f39 | 3019 | obj->base.read_domains, |
1c5d22f7 | 3020 | old_write_domain); |
e47c68e9 EA |
3021 | } |
3022 | ||
2ef7eeaa EA |
3023 | /** |
3024 | * Moves a single object to the GTT read, and possibly write domain. | |
3025 | * | |
3026 | * This function returns when the move is complete, including waiting on | |
3027 | * flushes to occur. | |
3028 | */ | |
79e53945 | 3029 | int |
2021746e | 3030 | i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write) |
2ef7eeaa | 3031 | { |
8325a09d | 3032 | drm_i915_private_t *dev_priv = obj->base.dev->dev_private; |
1c5d22f7 | 3033 | uint32_t old_write_domain, old_read_domains; |
e47c68e9 | 3034 | int ret; |
2ef7eeaa | 3035 | |
02354392 | 3036 | /* Not valid to be called on unbound objects. */ |
05394f39 | 3037 | if (obj->gtt_space == NULL) |
02354392 EA |
3038 | return -EINVAL; |
3039 | ||
8d7e3de1 CW |
3040 | if (obj->base.write_domain == I915_GEM_DOMAIN_GTT) |
3041 | return 0; | |
3042 | ||
0201f1ec CW |
3043 | ret = i915_gem_object_wait_rendering(obj, !write); |
3044 | if (ret) | |
3045 | return ret; | |
2dafb1e0 | 3046 | |
7213342d | 3047 | i915_gem_object_flush_cpu_write_domain(obj); |
1c5d22f7 | 3048 | |
05394f39 CW |
3049 | old_write_domain = obj->base.write_domain; |
3050 | old_read_domains = obj->base.read_domains; | |
1c5d22f7 | 3051 | |
e47c68e9 EA |
3052 | /* It should now be out of any other write domains, and we can update |
3053 | * the domain values for our changes. | |
3054 | */ | |
05394f39 CW |
3055 | BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_GTT) != 0); |
3056 | obj->base.read_domains |= I915_GEM_DOMAIN_GTT; | |
e47c68e9 | 3057 | if (write) { |
05394f39 CW |
3058 | obj->base.read_domains = I915_GEM_DOMAIN_GTT; |
3059 | obj->base.write_domain = I915_GEM_DOMAIN_GTT; | |
3060 | obj->dirty = 1; | |
2ef7eeaa EA |
3061 | } |
3062 | ||
1c5d22f7 CW |
3063 | trace_i915_gem_object_change_domain(obj, |
3064 | old_read_domains, | |
3065 | old_write_domain); | |
3066 | ||
8325a09d CW |
3067 | /* And bump the LRU for this access */ |
3068 | if (i915_gem_object_is_inactive(obj)) | |
3069 | list_move_tail(&obj->mm_list, &dev_priv->mm.inactive_list); | |
3070 | ||
e47c68e9 EA |
3071 | return 0; |
3072 | } | |
3073 | ||
e4ffd173 CW |
3074 | int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj, |
3075 | enum i915_cache_level cache_level) | |
3076 | { | |
7bddb01f DV |
3077 | struct drm_device *dev = obj->base.dev; |
3078 | drm_i915_private_t *dev_priv = dev->dev_private; | |
e4ffd173 CW |
3079 | int ret; |
3080 | ||
3081 | if (obj->cache_level == cache_level) | |
3082 | return 0; | |
3083 | ||
3084 | if (obj->pin_count) { | |
3085 | DRM_DEBUG("can not change the cache level of pinned objects\n"); | |
3086 | return -EBUSY; | |
3087 | } | |
3088 | ||
42d6ab48 CW |
3089 | if (!i915_gem_valid_gtt_space(dev, obj->gtt_space, cache_level)) { |
3090 | ret = i915_gem_object_unbind(obj); | |
3091 | if (ret) | |
3092 | return ret; | |
3093 | } | |
3094 | ||
e4ffd173 CW |
3095 | if (obj->gtt_space) { |
3096 | ret = i915_gem_object_finish_gpu(obj); | |
3097 | if (ret) | |
3098 | return ret; | |
3099 | ||
3100 | i915_gem_object_finish_gtt(obj); | |
3101 | ||
3102 | /* Before SandyBridge, you could not use tiling or fence | |
3103 | * registers with snooped memory, so relinquish any fences | |
3104 | * currently pointing to our region in the aperture. | |
3105 | */ | |
42d6ab48 | 3106 | if (INTEL_INFO(dev)->gen < 6) { |
e4ffd173 CW |
3107 | ret = i915_gem_object_put_fence(obj); |
3108 | if (ret) | |
3109 | return ret; | |
3110 | } | |
3111 | ||
74898d7e DV |
3112 | if (obj->has_global_gtt_mapping) |
3113 | i915_gem_gtt_bind_object(obj, cache_level); | |
7bddb01f DV |
3114 | if (obj->has_aliasing_ppgtt_mapping) |
3115 | i915_ppgtt_bind_object(dev_priv->mm.aliasing_ppgtt, | |
3116 | obj, cache_level); | |
42d6ab48 CW |
3117 | |
3118 | obj->gtt_space->color = cache_level; | |
e4ffd173 CW |
3119 | } |
3120 | ||
3121 | if (cache_level == I915_CACHE_NONE) { | |
3122 | u32 old_read_domains, old_write_domain; | |
3123 | ||
3124 | /* If we're coming from LLC cached, then we haven't | |
3125 | * actually been tracking whether the data is in the | |
3126 | * CPU cache or not, since we only allow one bit set | |
3127 | * in obj->write_domain and have been skipping the clflushes. | |
3128 | * Just set it to the CPU cache for now. | |
3129 | */ | |
3130 | WARN_ON(obj->base.write_domain & ~I915_GEM_DOMAIN_CPU); | |
3131 | WARN_ON(obj->base.read_domains & ~I915_GEM_DOMAIN_CPU); | |
3132 | ||
3133 | old_read_domains = obj->base.read_domains; | |
3134 | old_write_domain = obj->base.write_domain; | |
3135 | ||
3136 | obj->base.read_domains = I915_GEM_DOMAIN_CPU; | |
3137 | obj->base.write_domain = I915_GEM_DOMAIN_CPU; | |
3138 | ||
3139 | trace_i915_gem_object_change_domain(obj, | |
3140 | old_read_domains, | |
3141 | old_write_domain); | |
3142 | } | |
3143 | ||
3144 | obj->cache_level = cache_level; | |
42d6ab48 | 3145 | i915_gem_verify_gtt(dev); |
e4ffd173 CW |
3146 | return 0; |
3147 | } | |
3148 | ||
e6994aee CW |
3149 | int i915_gem_get_cacheing_ioctl(struct drm_device *dev, void *data, |
3150 | struct drm_file *file) | |
3151 | { | |
3152 | struct drm_i915_gem_cacheing *args = data; | |
3153 | struct drm_i915_gem_object *obj; | |
3154 | int ret; | |
3155 | ||
3156 | ret = i915_mutex_lock_interruptible(dev); | |
3157 | if (ret) | |
3158 | return ret; | |
3159 | ||
3160 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); | |
3161 | if (&obj->base == NULL) { | |
3162 | ret = -ENOENT; | |
3163 | goto unlock; | |
3164 | } | |
3165 | ||
3166 | args->cacheing = obj->cache_level != I915_CACHE_NONE; | |
3167 | ||
3168 | drm_gem_object_unreference(&obj->base); | |
3169 | unlock: | |
3170 | mutex_unlock(&dev->struct_mutex); | |
3171 | return ret; | |
3172 | } | |
3173 | ||
3174 | int i915_gem_set_cacheing_ioctl(struct drm_device *dev, void *data, | |
3175 | struct drm_file *file) | |
3176 | { | |
3177 | struct drm_i915_gem_cacheing *args = data; | |
3178 | struct drm_i915_gem_object *obj; | |
3179 | enum i915_cache_level level; | |
3180 | int ret; | |
3181 | ||
3182 | ret = i915_mutex_lock_interruptible(dev); | |
3183 | if (ret) | |
3184 | return ret; | |
3185 | ||
3186 | switch (args->cacheing) { | |
3187 | case I915_CACHEING_NONE: | |
3188 | level = I915_CACHE_NONE; | |
3189 | break; | |
3190 | case I915_CACHEING_CACHED: | |
3191 | level = I915_CACHE_LLC; | |
3192 | break; | |
3193 | default: | |
3194 | return -EINVAL; | |
3195 | } | |
3196 | ||
3197 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); | |
3198 | if (&obj->base == NULL) { | |
3199 | ret = -ENOENT; | |
3200 | goto unlock; | |
3201 | } | |
3202 | ||
3203 | ret = i915_gem_object_set_cache_level(obj, level); | |
3204 | ||
3205 | drm_gem_object_unreference(&obj->base); | |
3206 | unlock: | |
3207 | mutex_unlock(&dev->struct_mutex); | |
3208 | return ret; | |
3209 | } | |
3210 | ||
b9241ea3 | 3211 | /* |
2da3b9b9 CW |
3212 | * Prepare buffer for display plane (scanout, cursors, etc). |
3213 | * Can be called from an uninterruptible phase (modesetting) and allows | |
3214 | * any flushes to be pipelined (for pageflips). | |
b9241ea3 ZW |
3215 | */ |
3216 | int | |
2da3b9b9 CW |
3217 | i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj, |
3218 | u32 alignment, | |
919926ae | 3219 | struct intel_ring_buffer *pipelined) |
b9241ea3 | 3220 | { |
2da3b9b9 | 3221 | u32 old_read_domains, old_write_domain; |
b9241ea3 ZW |
3222 | int ret; |
3223 | ||
0be73284 | 3224 | if (pipelined != obj->ring) { |
2911a35b BW |
3225 | ret = i915_gem_object_sync(obj, pipelined); |
3226 | if (ret) | |
b9241ea3 ZW |
3227 | return ret; |
3228 | } | |
3229 | ||
a7ef0640 EA |
3230 | /* The display engine is not coherent with the LLC cache on gen6. As |
3231 | * a result, we make sure that the pinning that is about to occur is | |
3232 | * done with uncached PTEs. This is lowest common denominator for all | |
3233 | * chipsets. | |
3234 | * | |
3235 | * However for gen6+, we could do better by using the GFDT bit instead | |
3236 | * of uncaching, which would allow us to flush all the LLC-cached data | |
3237 | * with that bit in the PTE to main memory with just one PIPE_CONTROL. | |
3238 | */ | |
3239 | ret = i915_gem_object_set_cache_level(obj, I915_CACHE_NONE); | |
3240 | if (ret) | |
3241 | return ret; | |
3242 | ||
2da3b9b9 CW |
3243 | /* As the user may map the buffer once pinned in the display plane |
3244 | * (e.g. libkms for the bootup splash), we have to ensure that we | |
3245 | * always use map_and_fenceable for all scanout buffers. | |
3246 | */ | |
86a1ee26 | 3247 | ret = i915_gem_object_pin(obj, alignment, true, false); |
2da3b9b9 CW |
3248 | if (ret) |
3249 | return ret; | |
3250 | ||
b118c1e3 CW |
3251 | i915_gem_object_flush_cpu_write_domain(obj); |
3252 | ||
2da3b9b9 | 3253 | old_write_domain = obj->base.write_domain; |
05394f39 | 3254 | old_read_domains = obj->base.read_domains; |
2da3b9b9 CW |
3255 | |
3256 | /* It should now be out of any other write domains, and we can update | |
3257 | * the domain values for our changes. | |
3258 | */ | |
e5f1d962 | 3259 | obj->base.write_domain = 0; |
05394f39 | 3260 | obj->base.read_domains |= I915_GEM_DOMAIN_GTT; |
b9241ea3 ZW |
3261 | |
3262 | trace_i915_gem_object_change_domain(obj, | |
3263 | old_read_domains, | |
2da3b9b9 | 3264 | old_write_domain); |
b9241ea3 ZW |
3265 | |
3266 | return 0; | |
3267 | } | |
3268 | ||
85345517 | 3269 | int |
a8198eea | 3270 | i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj) |
85345517 | 3271 | { |
88241785 CW |
3272 | int ret; |
3273 | ||
a8198eea | 3274 | if ((obj->base.read_domains & I915_GEM_GPU_DOMAINS) == 0) |
85345517 CW |
3275 | return 0; |
3276 | ||
0201f1ec | 3277 | ret = i915_gem_object_wait_rendering(obj, false); |
c501ae7f CW |
3278 | if (ret) |
3279 | return ret; | |
3280 | ||
a8198eea CW |
3281 | /* Ensure that we invalidate the GPU's caches and TLBs. */ |
3282 | obj->base.read_domains &= ~I915_GEM_GPU_DOMAINS; | |
c501ae7f | 3283 | return 0; |
85345517 CW |
3284 | } |
3285 | ||
e47c68e9 EA |
3286 | /** |
3287 | * Moves a single object to the CPU read, and possibly write domain. | |
3288 | * | |
3289 | * This function returns when the move is complete, including waiting on | |
3290 | * flushes to occur. | |
3291 | */ | |
dabdfe02 | 3292 | int |
919926ae | 3293 | i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write) |
e47c68e9 | 3294 | { |
1c5d22f7 | 3295 | uint32_t old_write_domain, old_read_domains; |
e47c68e9 EA |
3296 | int ret; |
3297 | ||
8d7e3de1 CW |
3298 | if (obj->base.write_domain == I915_GEM_DOMAIN_CPU) |
3299 | return 0; | |
3300 | ||
0201f1ec CW |
3301 | ret = i915_gem_object_wait_rendering(obj, !write); |
3302 | if (ret) | |
3303 | return ret; | |
2ef7eeaa | 3304 | |
e47c68e9 | 3305 | i915_gem_object_flush_gtt_write_domain(obj); |
2ef7eeaa | 3306 | |
05394f39 CW |
3307 | old_write_domain = obj->base.write_domain; |
3308 | old_read_domains = obj->base.read_domains; | |
1c5d22f7 | 3309 | |
e47c68e9 | 3310 | /* Flush the CPU cache if it's still invalid. */ |
05394f39 | 3311 | if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0) { |
2ef7eeaa | 3312 | i915_gem_clflush_object(obj); |
2ef7eeaa | 3313 | |
05394f39 | 3314 | obj->base.read_domains |= I915_GEM_DOMAIN_CPU; |
2ef7eeaa EA |
3315 | } |
3316 | ||
3317 | /* It should now be out of any other write domains, and we can update | |
3318 | * the domain values for our changes. | |
3319 | */ | |
05394f39 | 3320 | BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_CPU) != 0); |
e47c68e9 EA |
3321 | |
3322 | /* If we're writing through the CPU, then the GPU read domains will | |
3323 | * need to be invalidated at next use. | |
3324 | */ | |
3325 | if (write) { | |
05394f39 CW |
3326 | obj->base.read_domains = I915_GEM_DOMAIN_CPU; |
3327 | obj->base.write_domain = I915_GEM_DOMAIN_CPU; | |
e47c68e9 | 3328 | } |
2ef7eeaa | 3329 | |
1c5d22f7 CW |
3330 | trace_i915_gem_object_change_domain(obj, |
3331 | old_read_domains, | |
3332 | old_write_domain); | |
3333 | ||
2ef7eeaa EA |
3334 | return 0; |
3335 | } | |
3336 | ||
673a394b EA |
3337 | /* Throttle our rendering by waiting until the ring has completed our requests |
3338 | * emitted over 20 msec ago. | |
3339 | * | |
b962442e EA |
3340 | * Note that if we were to use the current jiffies each time around the loop, |
3341 | * we wouldn't escape the function with any frames outstanding if the time to | |
3342 | * render a frame was over 20ms. | |
3343 | * | |
673a394b EA |
3344 | * This should get us reasonable parallelism between CPU and GPU but also |
3345 | * relatively low latency when blocking on a particular request to finish. | |
3346 | */ | |
40a5f0de | 3347 | static int |
f787a5f5 | 3348 | i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file) |
40a5f0de | 3349 | { |
f787a5f5 CW |
3350 | struct drm_i915_private *dev_priv = dev->dev_private; |
3351 | struct drm_i915_file_private *file_priv = file->driver_priv; | |
b962442e | 3352 | unsigned long recent_enough = jiffies - msecs_to_jiffies(20); |
f787a5f5 CW |
3353 | struct drm_i915_gem_request *request; |
3354 | struct intel_ring_buffer *ring = NULL; | |
3355 | u32 seqno = 0; | |
3356 | int ret; | |
93533c29 | 3357 | |
e110e8d6 CW |
3358 | if (atomic_read(&dev_priv->mm.wedged)) |
3359 | return -EIO; | |
3360 | ||
1c25595f | 3361 | spin_lock(&file_priv->mm.lock); |
f787a5f5 | 3362 | list_for_each_entry(request, &file_priv->mm.request_list, client_list) { |
b962442e EA |
3363 | if (time_after_eq(request->emitted_jiffies, recent_enough)) |
3364 | break; | |
40a5f0de | 3365 | |
f787a5f5 CW |
3366 | ring = request->ring; |
3367 | seqno = request->seqno; | |
b962442e | 3368 | } |
1c25595f | 3369 | spin_unlock(&file_priv->mm.lock); |
40a5f0de | 3370 | |
f787a5f5 CW |
3371 | if (seqno == 0) |
3372 | return 0; | |
2bc43b5c | 3373 | |
5c81fe85 | 3374 | ret = __wait_seqno(ring, seqno, true, NULL); |
f787a5f5 CW |
3375 | if (ret == 0) |
3376 | queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, 0); | |
40a5f0de EA |
3377 | |
3378 | return ret; | |
3379 | } | |
3380 | ||
673a394b | 3381 | int |
05394f39 CW |
3382 | i915_gem_object_pin(struct drm_i915_gem_object *obj, |
3383 | uint32_t alignment, | |
86a1ee26 CW |
3384 | bool map_and_fenceable, |
3385 | bool nonblocking) | |
673a394b | 3386 | { |
673a394b EA |
3387 | int ret; |
3388 | ||
05394f39 | 3389 | BUG_ON(obj->pin_count == DRM_I915_GEM_OBJECT_MAX_PIN_COUNT); |
ac0c6b5a | 3390 | |
05394f39 CW |
3391 | if (obj->gtt_space != NULL) { |
3392 | if ((alignment && obj->gtt_offset & (alignment - 1)) || | |
3393 | (map_and_fenceable && !obj->map_and_fenceable)) { | |
3394 | WARN(obj->pin_count, | |
ae7d49d8 | 3395 | "bo is already pinned with incorrect alignment:" |
75e9e915 DV |
3396 | " offset=%x, req.alignment=%x, req.map_and_fenceable=%d," |
3397 | " obj->map_and_fenceable=%d\n", | |
05394f39 | 3398 | obj->gtt_offset, alignment, |
75e9e915 | 3399 | map_and_fenceable, |
05394f39 | 3400 | obj->map_and_fenceable); |
ac0c6b5a CW |
3401 | ret = i915_gem_object_unbind(obj); |
3402 | if (ret) | |
3403 | return ret; | |
3404 | } | |
3405 | } | |
3406 | ||
05394f39 | 3407 | if (obj->gtt_space == NULL) { |
a00b10c3 | 3408 | ret = i915_gem_object_bind_to_gtt(obj, alignment, |
86a1ee26 CW |
3409 | map_and_fenceable, |
3410 | nonblocking); | |
9731129c | 3411 | if (ret) |
673a394b | 3412 | return ret; |
22c344e9 | 3413 | } |
76446cac | 3414 | |
74898d7e DV |
3415 | if (!obj->has_global_gtt_mapping && map_and_fenceable) |
3416 | i915_gem_gtt_bind_object(obj, obj->cache_level); | |
3417 | ||
1b50247a | 3418 | obj->pin_count++; |
6299f992 | 3419 | obj->pin_mappable |= map_and_fenceable; |
673a394b EA |
3420 | |
3421 | return 0; | |
3422 | } | |
3423 | ||
3424 | void | |
05394f39 | 3425 | i915_gem_object_unpin(struct drm_i915_gem_object *obj) |
673a394b | 3426 | { |
05394f39 CW |
3427 | BUG_ON(obj->pin_count == 0); |
3428 | BUG_ON(obj->gtt_space == NULL); | |
673a394b | 3429 | |
1b50247a | 3430 | if (--obj->pin_count == 0) |
6299f992 | 3431 | obj->pin_mappable = false; |
673a394b EA |
3432 | } |
3433 | ||
3434 | int | |
3435 | i915_gem_pin_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 3436 | struct drm_file *file) |
673a394b EA |
3437 | { |
3438 | struct drm_i915_gem_pin *args = data; | |
05394f39 | 3439 | struct drm_i915_gem_object *obj; |
673a394b EA |
3440 | int ret; |
3441 | ||
1d7cfea1 CW |
3442 | ret = i915_mutex_lock_interruptible(dev); |
3443 | if (ret) | |
3444 | return ret; | |
673a394b | 3445 | |
05394f39 | 3446 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 3447 | if (&obj->base == NULL) { |
1d7cfea1 CW |
3448 | ret = -ENOENT; |
3449 | goto unlock; | |
673a394b | 3450 | } |
673a394b | 3451 | |
05394f39 | 3452 | if (obj->madv != I915_MADV_WILLNEED) { |
bb6baf76 | 3453 | DRM_ERROR("Attempting to pin a purgeable buffer\n"); |
1d7cfea1 CW |
3454 | ret = -EINVAL; |
3455 | goto out; | |
3ef94daa CW |
3456 | } |
3457 | ||
05394f39 | 3458 | if (obj->pin_filp != NULL && obj->pin_filp != file) { |
79e53945 JB |
3459 | DRM_ERROR("Already pinned in i915_gem_pin_ioctl(): %d\n", |
3460 | args->handle); | |
1d7cfea1 CW |
3461 | ret = -EINVAL; |
3462 | goto out; | |
79e53945 JB |
3463 | } |
3464 | ||
05394f39 CW |
3465 | obj->user_pin_count++; |
3466 | obj->pin_filp = file; | |
3467 | if (obj->user_pin_count == 1) { | |
86a1ee26 | 3468 | ret = i915_gem_object_pin(obj, args->alignment, true, false); |
1d7cfea1 CW |
3469 | if (ret) |
3470 | goto out; | |
673a394b EA |
3471 | } |
3472 | ||
3473 | /* XXX - flush the CPU caches for pinned objects | |
3474 | * as the X server doesn't manage domains yet | |
3475 | */ | |
e47c68e9 | 3476 | i915_gem_object_flush_cpu_write_domain(obj); |
05394f39 | 3477 | args->offset = obj->gtt_offset; |
1d7cfea1 | 3478 | out: |
05394f39 | 3479 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 3480 | unlock: |
673a394b | 3481 | mutex_unlock(&dev->struct_mutex); |
1d7cfea1 | 3482 | return ret; |
673a394b EA |
3483 | } |
3484 | ||
3485 | int | |
3486 | i915_gem_unpin_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 3487 | struct drm_file *file) |
673a394b EA |
3488 | { |
3489 | struct drm_i915_gem_pin *args = data; | |
05394f39 | 3490 | struct drm_i915_gem_object *obj; |
76c1dec1 | 3491 | int ret; |
673a394b | 3492 | |
1d7cfea1 CW |
3493 | ret = i915_mutex_lock_interruptible(dev); |
3494 | if (ret) | |
3495 | return ret; | |
673a394b | 3496 | |
05394f39 | 3497 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 3498 | if (&obj->base == NULL) { |
1d7cfea1 CW |
3499 | ret = -ENOENT; |
3500 | goto unlock; | |
673a394b | 3501 | } |
76c1dec1 | 3502 | |
05394f39 | 3503 | if (obj->pin_filp != file) { |
79e53945 JB |
3504 | DRM_ERROR("Not pinned by caller in i915_gem_pin_ioctl(): %d\n", |
3505 | args->handle); | |
1d7cfea1 CW |
3506 | ret = -EINVAL; |
3507 | goto out; | |
79e53945 | 3508 | } |
05394f39 CW |
3509 | obj->user_pin_count--; |
3510 | if (obj->user_pin_count == 0) { | |
3511 | obj->pin_filp = NULL; | |
79e53945 JB |
3512 | i915_gem_object_unpin(obj); |
3513 | } | |
673a394b | 3514 | |
1d7cfea1 | 3515 | out: |
05394f39 | 3516 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 3517 | unlock: |
673a394b | 3518 | mutex_unlock(&dev->struct_mutex); |
1d7cfea1 | 3519 | return ret; |
673a394b EA |
3520 | } |
3521 | ||
3522 | int | |
3523 | i915_gem_busy_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 3524 | struct drm_file *file) |
673a394b EA |
3525 | { |
3526 | struct drm_i915_gem_busy *args = data; | |
05394f39 | 3527 | struct drm_i915_gem_object *obj; |
30dbf0c0 CW |
3528 | int ret; |
3529 | ||
76c1dec1 | 3530 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 3531 | if (ret) |
76c1dec1 | 3532 | return ret; |
673a394b | 3533 | |
05394f39 | 3534 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 3535 | if (&obj->base == NULL) { |
1d7cfea1 CW |
3536 | ret = -ENOENT; |
3537 | goto unlock; | |
673a394b | 3538 | } |
d1b851fc | 3539 | |
0be555b6 CW |
3540 | /* Count all active objects as busy, even if they are currently not used |
3541 | * by the gpu. Users of this interface expect objects to eventually | |
3542 | * become non-busy without any further actions, therefore emit any | |
3543 | * necessary flushes here. | |
c4de0a5d | 3544 | */ |
30dfebf3 | 3545 | ret = i915_gem_object_flush_active(obj); |
0be555b6 | 3546 | |
30dfebf3 | 3547 | args->busy = obj->active; |
e9808edd CW |
3548 | if (obj->ring) { |
3549 | BUILD_BUG_ON(I915_NUM_RINGS > 16); | |
3550 | args->busy |= intel_ring_flag(obj->ring) << 16; | |
3551 | } | |
673a394b | 3552 | |
05394f39 | 3553 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 3554 | unlock: |
673a394b | 3555 | mutex_unlock(&dev->struct_mutex); |
1d7cfea1 | 3556 | return ret; |
673a394b EA |
3557 | } |
3558 | ||
3559 | int | |
3560 | i915_gem_throttle_ioctl(struct drm_device *dev, void *data, | |
3561 | struct drm_file *file_priv) | |
3562 | { | |
0206e353 | 3563 | return i915_gem_ring_throttle(dev, file_priv); |
673a394b EA |
3564 | } |
3565 | ||
3ef94daa CW |
3566 | int |
3567 | i915_gem_madvise_ioctl(struct drm_device *dev, void *data, | |
3568 | struct drm_file *file_priv) | |
3569 | { | |
3570 | struct drm_i915_gem_madvise *args = data; | |
05394f39 | 3571 | struct drm_i915_gem_object *obj; |
76c1dec1 | 3572 | int ret; |
3ef94daa CW |
3573 | |
3574 | switch (args->madv) { | |
3575 | case I915_MADV_DONTNEED: | |
3576 | case I915_MADV_WILLNEED: | |
3577 | break; | |
3578 | default: | |
3579 | return -EINVAL; | |
3580 | } | |
3581 | ||
1d7cfea1 CW |
3582 | ret = i915_mutex_lock_interruptible(dev); |
3583 | if (ret) | |
3584 | return ret; | |
3585 | ||
05394f39 | 3586 | obj = to_intel_bo(drm_gem_object_lookup(dev, file_priv, args->handle)); |
c8725226 | 3587 | if (&obj->base == NULL) { |
1d7cfea1 CW |
3588 | ret = -ENOENT; |
3589 | goto unlock; | |
3ef94daa | 3590 | } |
3ef94daa | 3591 | |
05394f39 | 3592 | if (obj->pin_count) { |
1d7cfea1 CW |
3593 | ret = -EINVAL; |
3594 | goto out; | |
3ef94daa CW |
3595 | } |
3596 | ||
05394f39 CW |
3597 | if (obj->madv != __I915_MADV_PURGED) |
3598 | obj->madv = args->madv; | |
3ef94daa | 3599 | |
6c085a72 CW |
3600 | /* if the object is no longer attached, discard its backing storage */ |
3601 | if (i915_gem_object_is_purgeable(obj) && obj->pages == NULL) | |
2d7ef395 CW |
3602 | i915_gem_object_truncate(obj); |
3603 | ||
05394f39 | 3604 | args->retained = obj->madv != __I915_MADV_PURGED; |
bb6baf76 | 3605 | |
1d7cfea1 | 3606 | out: |
05394f39 | 3607 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 3608 | unlock: |
3ef94daa | 3609 | mutex_unlock(&dev->struct_mutex); |
1d7cfea1 | 3610 | return ret; |
3ef94daa CW |
3611 | } |
3612 | ||
0327d6ba CW |
3613 | void i915_gem_object_init(struct drm_i915_gem_object *obj) |
3614 | { | |
3615 | obj->base.driver_private = NULL; | |
3616 | ||
3617 | INIT_LIST_HEAD(&obj->mm_list); | |
3618 | INIT_LIST_HEAD(&obj->gtt_list); | |
3619 | INIT_LIST_HEAD(&obj->ring_list); | |
3620 | INIT_LIST_HEAD(&obj->exec_list); | |
3621 | ||
3622 | obj->fence_reg = I915_FENCE_REG_NONE; | |
3623 | obj->madv = I915_MADV_WILLNEED; | |
3624 | /* Avoid an unnecessary call to unbind on the first bind. */ | |
3625 | obj->map_and_fenceable = true; | |
3626 | ||
3627 | i915_gem_info_add_obj(obj->base.dev->dev_private, obj->base.size); | |
3628 | } | |
3629 | ||
05394f39 CW |
3630 | struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev, |
3631 | size_t size) | |
ac52bc56 | 3632 | { |
c397b908 | 3633 | struct drm_i915_gem_object *obj; |
5949eac4 | 3634 | struct address_space *mapping; |
bed1ea95 | 3635 | u32 mask; |
ac52bc56 | 3636 | |
c397b908 DV |
3637 | obj = kzalloc(sizeof(*obj), GFP_KERNEL); |
3638 | if (obj == NULL) | |
3639 | return NULL; | |
673a394b | 3640 | |
c397b908 DV |
3641 | if (drm_gem_object_init(dev, &obj->base, size) != 0) { |
3642 | kfree(obj); | |
3643 | return NULL; | |
3644 | } | |
673a394b | 3645 | |
bed1ea95 CW |
3646 | mask = GFP_HIGHUSER | __GFP_RECLAIMABLE; |
3647 | if (IS_CRESTLINE(dev) || IS_BROADWATER(dev)) { | |
3648 | /* 965gm cannot relocate objects above 4GiB. */ | |
3649 | mask &= ~__GFP_HIGHMEM; | |
3650 | mask |= __GFP_DMA32; | |
3651 | } | |
3652 | ||
5949eac4 | 3653 | mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping; |
bed1ea95 | 3654 | mapping_set_gfp_mask(mapping, mask); |
5949eac4 | 3655 | |
0327d6ba | 3656 | i915_gem_object_init(obj); |
73aa808f | 3657 | |
c397b908 DV |
3658 | obj->base.write_domain = I915_GEM_DOMAIN_CPU; |
3659 | obj->base.read_domains = I915_GEM_DOMAIN_CPU; | |
673a394b | 3660 | |
3d29b842 ED |
3661 | if (HAS_LLC(dev)) { |
3662 | /* On some devices, we can have the GPU use the LLC (the CPU | |
a1871112 EA |
3663 | * cache) for about a 10% performance improvement |
3664 | * compared to uncached. Graphics requests other than | |
3665 | * display scanout are coherent with the CPU in | |
3666 | * accessing this cache. This means in this mode we | |
3667 | * don't need to clflush on the CPU side, and on the | |
3668 | * GPU side we only need to flush internal caches to | |
3669 | * get data visible to the CPU. | |
3670 | * | |
3671 | * However, we maintain the display planes as UC, and so | |
3672 | * need to rebind when first used as such. | |
3673 | */ | |
3674 | obj->cache_level = I915_CACHE_LLC; | |
3675 | } else | |
3676 | obj->cache_level = I915_CACHE_NONE; | |
3677 | ||
05394f39 | 3678 | return obj; |
c397b908 DV |
3679 | } |
3680 | ||
3681 | int i915_gem_init_object(struct drm_gem_object *obj) | |
3682 | { | |
3683 | BUG(); | |
de151cf6 | 3684 | |
673a394b EA |
3685 | return 0; |
3686 | } | |
3687 | ||
1488fc08 | 3688 | void i915_gem_free_object(struct drm_gem_object *gem_obj) |
673a394b | 3689 | { |
1488fc08 | 3690 | struct drm_i915_gem_object *obj = to_intel_bo(gem_obj); |
05394f39 | 3691 | struct drm_device *dev = obj->base.dev; |
be72615b | 3692 | drm_i915_private_t *dev_priv = dev->dev_private; |
673a394b | 3693 | |
26e12f89 CW |
3694 | trace_i915_gem_object_destroy(obj); |
3695 | ||
1286ff73 DV |
3696 | if (gem_obj->import_attach) |
3697 | drm_prime_gem_destroy(gem_obj, obj->sg_table); | |
3698 | ||
1488fc08 CW |
3699 | if (obj->phys_obj) |
3700 | i915_gem_detach_phys_object(dev, obj); | |
3701 | ||
3702 | obj->pin_count = 0; | |
3703 | if (WARN_ON(i915_gem_object_unbind(obj) == -ERESTARTSYS)) { | |
3704 | bool was_interruptible; | |
3705 | ||
3706 | was_interruptible = dev_priv->mm.interruptible; | |
3707 | dev_priv->mm.interruptible = false; | |
3708 | ||
3709 | WARN_ON(i915_gem_object_unbind(obj)); | |
3710 | ||
3711 | dev_priv->mm.interruptible = was_interruptible; | |
3712 | } | |
3713 | ||
6c085a72 | 3714 | i915_gem_object_put_pages_gtt(obj); |
d8cb5086 | 3715 | i915_gem_object_free_mmap_offset(obj); |
de151cf6 | 3716 | |
05394f39 CW |
3717 | drm_gem_object_release(&obj->base); |
3718 | i915_gem_info_remove_obj(dev_priv, obj->base.size); | |
c397b908 | 3719 | |
05394f39 CW |
3720 | kfree(obj->bit_17); |
3721 | kfree(obj); | |
673a394b EA |
3722 | } |
3723 | ||
29105ccc CW |
3724 | int |
3725 | i915_gem_idle(struct drm_device *dev) | |
3726 | { | |
3727 | drm_i915_private_t *dev_priv = dev->dev_private; | |
3728 | int ret; | |
28dfe52a | 3729 | |
29105ccc | 3730 | mutex_lock(&dev->struct_mutex); |
1c5d22f7 | 3731 | |
87acb0a5 | 3732 | if (dev_priv->mm.suspended) { |
29105ccc CW |
3733 | mutex_unlock(&dev->struct_mutex); |
3734 | return 0; | |
28dfe52a EA |
3735 | } |
3736 | ||
b2da9fe5 | 3737 | ret = i915_gpu_idle(dev); |
6dbe2772 KP |
3738 | if (ret) { |
3739 | mutex_unlock(&dev->struct_mutex); | |
673a394b | 3740 | return ret; |
6dbe2772 | 3741 | } |
b2da9fe5 | 3742 | i915_gem_retire_requests(dev); |
673a394b | 3743 | |
29105ccc | 3744 | /* Under UMS, be paranoid and evict. */ |
a39d7efc | 3745 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) |
6c085a72 | 3746 | i915_gem_evict_everything(dev); |
29105ccc | 3747 | |
312817a3 CW |
3748 | i915_gem_reset_fences(dev); |
3749 | ||
29105ccc CW |
3750 | /* Hack! Don't let anybody do execbuf while we don't control the chip. |
3751 | * We need to replace this with a semaphore, or something. | |
3752 | * And not confound mm.suspended! | |
3753 | */ | |
3754 | dev_priv->mm.suspended = 1; | |
bc0c7f14 | 3755 | del_timer_sync(&dev_priv->hangcheck_timer); |
29105ccc CW |
3756 | |
3757 | i915_kernel_lost_context(dev); | |
6dbe2772 | 3758 | i915_gem_cleanup_ringbuffer(dev); |
29105ccc | 3759 | |
6dbe2772 KP |
3760 | mutex_unlock(&dev->struct_mutex); |
3761 | ||
29105ccc CW |
3762 | /* Cancel the retire work handler, which should be idle now. */ |
3763 | cancel_delayed_work_sync(&dev_priv->mm.retire_work); | |
3764 | ||
673a394b EA |
3765 | return 0; |
3766 | } | |
3767 | ||
b9524a1e BW |
3768 | void i915_gem_l3_remap(struct drm_device *dev) |
3769 | { | |
3770 | drm_i915_private_t *dev_priv = dev->dev_private; | |
3771 | u32 misccpctl; | |
3772 | int i; | |
3773 | ||
3774 | if (!IS_IVYBRIDGE(dev)) | |
3775 | return; | |
3776 | ||
3777 | if (!dev_priv->mm.l3_remap_info) | |
3778 | return; | |
3779 | ||
3780 | misccpctl = I915_READ(GEN7_MISCCPCTL); | |
3781 | I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE); | |
3782 | POSTING_READ(GEN7_MISCCPCTL); | |
3783 | ||
3784 | for (i = 0; i < GEN7_L3LOG_SIZE; i += 4) { | |
3785 | u32 remap = I915_READ(GEN7_L3LOG_BASE + i); | |
3786 | if (remap && remap != dev_priv->mm.l3_remap_info[i/4]) | |
3787 | DRM_DEBUG("0x%x was already programmed to %x\n", | |
3788 | GEN7_L3LOG_BASE + i, remap); | |
3789 | if (remap && !dev_priv->mm.l3_remap_info[i/4]) | |
3790 | DRM_DEBUG_DRIVER("Clearing remapped register\n"); | |
3791 | I915_WRITE(GEN7_L3LOG_BASE + i, dev_priv->mm.l3_remap_info[i/4]); | |
3792 | } | |
3793 | ||
3794 | /* Make sure all the writes land before disabling dop clock gating */ | |
3795 | POSTING_READ(GEN7_L3LOG_BASE); | |
3796 | ||
3797 | I915_WRITE(GEN7_MISCCPCTL, misccpctl); | |
3798 | } | |
3799 | ||
f691e2f4 DV |
3800 | void i915_gem_init_swizzling(struct drm_device *dev) |
3801 | { | |
3802 | drm_i915_private_t *dev_priv = dev->dev_private; | |
3803 | ||
11782b02 | 3804 | if (INTEL_INFO(dev)->gen < 5 || |
f691e2f4 DV |
3805 | dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_NONE) |
3806 | return; | |
3807 | ||
3808 | I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) | | |
3809 | DISP_TILE_SURFACE_SWIZZLING); | |
3810 | ||
11782b02 DV |
3811 | if (IS_GEN5(dev)) |
3812 | return; | |
3813 | ||
f691e2f4 DV |
3814 | I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_SWZCTL); |
3815 | if (IS_GEN6(dev)) | |
6b26c86d | 3816 | I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB)); |
f691e2f4 | 3817 | else |
6b26c86d | 3818 | I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB)); |
f691e2f4 | 3819 | } |
e21af88d DV |
3820 | |
3821 | void i915_gem_init_ppgtt(struct drm_device *dev) | |
3822 | { | |
3823 | drm_i915_private_t *dev_priv = dev->dev_private; | |
3824 | uint32_t pd_offset; | |
3825 | struct intel_ring_buffer *ring; | |
55a254ac DV |
3826 | struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt; |
3827 | uint32_t __iomem *pd_addr; | |
3828 | uint32_t pd_entry; | |
e21af88d DV |
3829 | int i; |
3830 | ||
3831 | if (!dev_priv->mm.aliasing_ppgtt) | |
3832 | return; | |
3833 | ||
55a254ac DV |
3834 | |
3835 | pd_addr = dev_priv->mm.gtt->gtt + ppgtt->pd_offset/sizeof(uint32_t); | |
3836 | for (i = 0; i < ppgtt->num_pd_entries; i++) { | |
3837 | dma_addr_t pt_addr; | |
3838 | ||
3839 | if (dev_priv->mm.gtt->needs_dmar) | |
3840 | pt_addr = ppgtt->pt_dma_addr[i]; | |
3841 | else | |
3842 | pt_addr = page_to_phys(ppgtt->pt_pages[i]); | |
3843 | ||
3844 | pd_entry = GEN6_PDE_ADDR_ENCODE(pt_addr); | |
3845 | pd_entry |= GEN6_PDE_VALID; | |
3846 | ||
3847 | writel(pd_entry, pd_addr + i); | |
3848 | } | |
3849 | readl(pd_addr); | |
3850 | ||
3851 | pd_offset = ppgtt->pd_offset; | |
e21af88d DV |
3852 | pd_offset /= 64; /* in cachelines, */ |
3853 | pd_offset <<= 16; | |
3854 | ||
3855 | if (INTEL_INFO(dev)->gen == 6) { | |
48ecfa10 DV |
3856 | uint32_t ecochk, gab_ctl, ecobits; |
3857 | ||
3858 | ecobits = I915_READ(GAC_ECO_BITS); | |
3859 | I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_PPGTT_CACHE64B); | |
be901a5a DV |
3860 | |
3861 | gab_ctl = I915_READ(GAB_CTL); | |
3862 | I915_WRITE(GAB_CTL, gab_ctl | GAB_CTL_CONT_AFTER_PAGEFAULT); | |
3863 | ||
3864 | ecochk = I915_READ(GAM_ECOCHK); | |
e21af88d DV |
3865 | I915_WRITE(GAM_ECOCHK, ecochk | ECOCHK_SNB_BIT | |
3866 | ECOCHK_PPGTT_CACHE64B); | |
6b26c86d | 3867 | I915_WRITE(GFX_MODE, _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE)); |
e21af88d DV |
3868 | } else if (INTEL_INFO(dev)->gen >= 7) { |
3869 | I915_WRITE(GAM_ECOCHK, ECOCHK_PPGTT_CACHE64B); | |
3870 | /* GFX_MODE is per-ring on gen7+ */ | |
3871 | } | |
3872 | ||
b4519513 | 3873 | for_each_ring(ring, dev_priv, i) { |
e21af88d DV |
3874 | if (INTEL_INFO(dev)->gen >= 7) |
3875 | I915_WRITE(RING_MODE_GEN7(ring), | |
6b26c86d | 3876 | _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE)); |
e21af88d DV |
3877 | |
3878 | I915_WRITE(RING_PP_DIR_DCLV(ring), PP_DIR_DCLV_2G); | |
3879 | I915_WRITE(RING_PP_DIR_BASE(ring), pd_offset); | |
3880 | } | |
3881 | } | |
3882 | ||
67b1b571 CW |
3883 | static bool |
3884 | intel_enable_blt(struct drm_device *dev) | |
3885 | { | |
3886 | if (!HAS_BLT(dev)) | |
3887 | return false; | |
3888 | ||
3889 | /* The blitter was dysfunctional on early prototypes */ | |
3890 | if (IS_GEN6(dev) && dev->pdev->revision < 8) { | |
3891 | DRM_INFO("BLT not supported on this pre-production hardware;" | |
3892 | " graphics performance will be degraded.\n"); | |
3893 | return false; | |
3894 | } | |
3895 | ||
3896 | return true; | |
3897 | } | |
3898 | ||
8187a2b7 | 3899 | int |
f691e2f4 | 3900 | i915_gem_init_hw(struct drm_device *dev) |
8187a2b7 ZN |
3901 | { |
3902 | drm_i915_private_t *dev_priv = dev->dev_private; | |
3903 | int ret; | |
68f95ba9 | 3904 | |
8ecd1a66 DV |
3905 | if (!intel_enable_gtt()) |
3906 | return -EIO; | |
3907 | ||
b9524a1e BW |
3908 | i915_gem_l3_remap(dev); |
3909 | ||
f691e2f4 DV |
3910 | i915_gem_init_swizzling(dev); |
3911 | ||
5c1143bb | 3912 | ret = intel_init_render_ring_buffer(dev); |
68f95ba9 | 3913 | if (ret) |
b6913e4b | 3914 | return ret; |
68f95ba9 CW |
3915 | |
3916 | if (HAS_BSD(dev)) { | |
5c1143bb | 3917 | ret = intel_init_bsd_ring_buffer(dev); |
68f95ba9 CW |
3918 | if (ret) |
3919 | goto cleanup_render_ring; | |
d1b851fc | 3920 | } |
68f95ba9 | 3921 | |
67b1b571 | 3922 | if (intel_enable_blt(dev)) { |
549f7365 CW |
3923 | ret = intel_init_blt_ring_buffer(dev); |
3924 | if (ret) | |
3925 | goto cleanup_bsd_ring; | |
3926 | } | |
3927 | ||
6f392d54 CW |
3928 | dev_priv->next_seqno = 1; |
3929 | ||
254f965c BW |
3930 | /* |
3931 | * XXX: There was some w/a described somewhere suggesting loading | |
3932 | * contexts before PPGTT. | |
3933 | */ | |
3934 | i915_gem_context_init(dev); | |
e21af88d DV |
3935 | i915_gem_init_ppgtt(dev); |
3936 | ||
68f95ba9 CW |
3937 | return 0; |
3938 | ||
549f7365 | 3939 | cleanup_bsd_ring: |
1ec14ad3 | 3940 | intel_cleanup_ring_buffer(&dev_priv->ring[VCS]); |
68f95ba9 | 3941 | cleanup_render_ring: |
1ec14ad3 | 3942 | intel_cleanup_ring_buffer(&dev_priv->ring[RCS]); |
8187a2b7 ZN |
3943 | return ret; |
3944 | } | |
3945 | ||
1070a42b CW |
3946 | static bool |
3947 | intel_enable_ppgtt(struct drm_device *dev) | |
3948 | { | |
3949 | if (i915_enable_ppgtt >= 0) | |
3950 | return i915_enable_ppgtt; | |
3951 | ||
3952 | #ifdef CONFIG_INTEL_IOMMU | |
3953 | /* Disable ppgtt on SNB if VT-d is on. */ | |
3954 | if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped) | |
3955 | return false; | |
3956 | #endif | |
3957 | ||
3958 | return true; | |
3959 | } | |
3960 | ||
3961 | int i915_gem_init(struct drm_device *dev) | |
3962 | { | |
3963 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3964 | unsigned long gtt_size, mappable_size; | |
3965 | int ret; | |
3966 | ||
3967 | gtt_size = dev_priv->mm.gtt->gtt_total_entries << PAGE_SHIFT; | |
3968 | mappable_size = dev_priv->mm.gtt->gtt_mappable_entries << PAGE_SHIFT; | |
3969 | ||
3970 | mutex_lock(&dev->struct_mutex); | |
3971 | if (intel_enable_ppgtt(dev) && HAS_ALIASING_PPGTT(dev)) { | |
3972 | /* PPGTT pdes are stolen from global gtt ptes, so shrink the | |
3973 | * aperture accordingly when using aliasing ppgtt. */ | |
3974 | gtt_size -= I915_PPGTT_PD_ENTRIES*PAGE_SIZE; | |
3975 | ||
3976 | i915_gem_init_global_gtt(dev, 0, mappable_size, gtt_size); | |
3977 | ||
3978 | ret = i915_gem_init_aliasing_ppgtt(dev); | |
3979 | if (ret) { | |
3980 | mutex_unlock(&dev->struct_mutex); | |
3981 | return ret; | |
3982 | } | |
3983 | } else { | |
3984 | /* Let GEM Manage all of the aperture. | |
3985 | * | |
3986 | * However, leave one page at the end still bound to the scratch | |
3987 | * page. There are a number of places where the hardware | |
3988 | * apparently prefetches past the end of the object, and we've | |
3989 | * seen multiple hangs with the GPU head pointer stuck in a | |
3990 | * batchbuffer bound at the last page of the aperture. One page | |
3991 | * should be enough to keep any prefetching inside of the | |
3992 | * aperture. | |
3993 | */ | |
3994 | i915_gem_init_global_gtt(dev, 0, mappable_size, | |
3995 | gtt_size); | |
3996 | } | |
3997 | ||
3998 | ret = i915_gem_init_hw(dev); | |
3999 | mutex_unlock(&dev->struct_mutex); | |
4000 | if (ret) { | |
4001 | i915_gem_cleanup_aliasing_ppgtt(dev); | |
4002 | return ret; | |
4003 | } | |
4004 | ||
53ca26ca DV |
4005 | /* Allow hardware batchbuffers unless told otherwise, but not for KMS. */ |
4006 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) | |
4007 | dev_priv->dri1.allow_batchbuffer = 1; | |
1070a42b CW |
4008 | return 0; |
4009 | } | |
4010 | ||
8187a2b7 ZN |
4011 | void |
4012 | i915_gem_cleanup_ringbuffer(struct drm_device *dev) | |
4013 | { | |
4014 | drm_i915_private_t *dev_priv = dev->dev_private; | |
b4519513 | 4015 | struct intel_ring_buffer *ring; |
1ec14ad3 | 4016 | int i; |
8187a2b7 | 4017 | |
b4519513 CW |
4018 | for_each_ring(ring, dev_priv, i) |
4019 | intel_cleanup_ring_buffer(ring); | |
8187a2b7 ZN |
4020 | } |
4021 | ||
673a394b EA |
4022 | int |
4023 | i915_gem_entervt_ioctl(struct drm_device *dev, void *data, | |
4024 | struct drm_file *file_priv) | |
4025 | { | |
4026 | drm_i915_private_t *dev_priv = dev->dev_private; | |
b4519513 | 4027 | int ret; |
673a394b | 4028 | |
79e53945 JB |
4029 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
4030 | return 0; | |
4031 | ||
ba1234d1 | 4032 | if (atomic_read(&dev_priv->mm.wedged)) { |
673a394b | 4033 | DRM_ERROR("Reenabling wedged hardware, good luck\n"); |
ba1234d1 | 4034 | atomic_set(&dev_priv->mm.wedged, 0); |
673a394b EA |
4035 | } |
4036 | ||
673a394b | 4037 | mutex_lock(&dev->struct_mutex); |
9bb2d6f9 EA |
4038 | dev_priv->mm.suspended = 0; |
4039 | ||
f691e2f4 | 4040 | ret = i915_gem_init_hw(dev); |
d816f6ac WF |
4041 | if (ret != 0) { |
4042 | mutex_unlock(&dev->struct_mutex); | |
9bb2d6f9 | 4043 | return ret; |
d816f6ac | 4044 | } |
9bb2d6f9 | 4045 | |
69dc4987 | 4046 | BUG_ON(!list_empty(&dev_priv->mm.active_list)); |
673a394b | 4047 | BUG_ON(!list_empty(&dev_priv->mm.inactive_list)); |
673a394b | 4048 | mutex_unlock(&dev->struct_mutex); |
dbb19d30 | 4049 | |
5f35308b CW |
4050 | ret = drm_irq_install(dev); |
4051 | if (ret) | |
4052 | goto cleanup_ringbuffer; | |
dbb19d30 | 4053 | |
673a394b | 4054 | return 0; |
5f35308b CW |
4055 | |
4056 | cleanup_ringbuffer: | |
4057 | mutex_lock(&dev->struct_mutex); | |
4058 | i915_gem_cleanup_ringbuffer(dev); | |
4059 | dev_priv->mm.suspended = 1; | |
4060 | mutex_unlock(&dev->struct_mutex); | |
4061 | ||
4062 | return ret; | |
673a394b EA |
4063 | } |
4064 | ||
4065 | int | |
4066 | i915_gem_leavevt_ioctl(struct drm_device *dev, void *data, | |
4067 | struct drm_file *file_priv) | |
4068 | { | |
79e53945 JB |
4069 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
4070 | return 0; | |
4071 | ||
dbb19d30 | 4072 | drm_irq_uninstall(dev); |
e6890f6f | 4073 | return i915_gem_idle(dev); |
673a394b EA |
4074 | } |
4075 | ||
4076 | void | |
4077 | i915_gem_lastclose(struct drm_device *dev) | |
4078 | { | |
4079 | int ret; | |
673a394b | 4080 | |
e806b495 EA |
4081 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
4082 | return; | |
4083 | ||
6dbe2772 KP |
4084 | ret = i915_gem_idle(dev); |
4085 | if (ret) | |
4086 | DRM_ERROR("failed to idle hardware: %d\n", ret); | |
673a394b EA |
4087 | } |
4088 | ||
64193406 CW |
4089 | static void |
4090 | init_ring_lists(struct intel_ring_buffer *ring) | |
4091 | { | |
4092 | INIT_LIST_HEAD(&ring->active_list); | |
4093 | INIT_LIST_HEAD(&ring->request_list); | |
64193406 CW |
4094 | } |
4095 | ||
673a394b EA |
4096 | void |
4097 | i915_gem_load(struct drm_device *dev) | |
4098 | { | |
b5aa8a0f | 4099 | int i; |
673a394b EA |
4100 | drm_i915_private_t *dev_priv = dev->dev_private; |
4101 | ||
69dc4987 | 4102 | INIT_LIST_HEAD(&dev_priv->mm.active_list); |
673a394b | 4103 | INIT_LIST_HEAD(&dev_priv->mm.inactive_list); |
6c085a72 CW |
4104 | INIT_LIST_HEAD(&dev_priv->mm.unbound_list); |
4105 | INIT_LIST_HEAD(&dev_priv->mm.bound_list); | |
a09ba7fa | 4106 | INIT_LIST_HEAD(&dev_priv->mm.fence_list); |
1ec14ad3 CW |
4107 | for (i = 0; i < I915_NUM_RINGS; i++) |
4108 | init_ring_lists(&dev_priv->ring[i]); | |
4b9de737 | 4109 | for (i = 0; i < I915_MAX_NUM_FENCES; i++) |
007cc8ac | 4110 | INIT_LIST_HEAD(&dev_priv->fence_regs[i].lru_list); |
673a394b EA |
4111 | INIT_DELAYED_WORK(&dev_priv->mm.retire_work, |
4112 | i915_gem_retire_work_handler); | |
30dbf0c0 | 4113 | init_completion(&dev_priv->error_completion); |
31169714 | 4114 | |
94400120 DA |
4115 | /* On GEN3 we really need to make sure the ARB C3 LP bit is set */ |
4116 | if (IS_GEN3(dev)) { | |
50743298 DV |
4117 | I915_WRITE(MI_ARB_STATE, |
4118 | _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE)); | |
94400120 DA |
4119 | } |
4120 | ||
72bfa19c CW |
4121 | dev_priv->relative_constants_mode = I915_EXEC_CONSTANTS_REL_GENERAL; |
4122 | ||
de151cf6 | 4123 | /* Old X drivers will take 0-2 for front, back, depth buffers */ |
b397c836 EA |
4124 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) |
4125 | dev_priv->fence_reg_start = 3; | |
de151cf6 | 4126 | |
a6c45cf0 | 4127 | if (INTEL_INFO(dev)->gen >= 4 || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) |
de151cf6 JB |
4128 | dev_priv->num_fence_regs = 16; |
4129 | else | |
4130 | dev_priv->num_fence_regs = 8; | |
4131 | ||
b5aa8a0f | 4132 | /* Initialize fence registers to zero */ |
ada726c7 | 4133 | i915_gem_reset_fences(dev); |
10ed13e4 | 4134 | |
673a394b | 4135 | i915_gem_detect_bit_6_swizzle(dev); |
6b95a207 | 4136 | init_waitqueue_head(&dev_priv->pending_flip_queue); |
17250b71 | 4137 | |
ce453d81 CW |
4138 | dev_priv->mm.interruptible = true; |
4139 | ||
17250b71 CW |
4140 | dev_priv->mm.inactive_shrinker.shrink = i915_gem_inactive_shrink; |
4141 | dev_priv->mm.inactive_shrinker.seeks = DEFAULT_SEEKS; | |
4142 | register_shrinker(&dev_priv->mm.inactive_shrinker); | |
673a394b | 4143 | } |
71acb5eb DA |
4144 | |
4145 | /* | |
4146 | * Create a physically contiguous memory object for this object | |
4147 | * e.g. for cursor + overlay regs | |
4148 | */ | |
995b6762 CW |
4149 | static int i915_gem_init_phys_object(struct drm_device *dev, |
4150 | int id, int size, int align) | |
71acb5eb DA |
4151 | { |
4152 | drm_i915_private_t *dev_priv = dev->dev_private; | |
4153 | struct drm_i915_gem_phys_object *phys_obj; | |
4154 | int ret; | |
4155 | ||
4156 | if (dev_priv->mm.phys_objs[id - 1] || !size) | |
4157 | return 0; | |
4158 | ||
9a298b2a | 4159 | phys_obj = kzalloc(sizeof(struct drm_i915_gem_phys_object), GFP_KERNEL); |
71acb5eb DA |
4160 | if (!phys_obj) |
4161 | return -ENOMEM; | |
4162 | ||
4163 | phys_obj->id = id; | |
4164 | ||
6eeefaf3 | 4165 | phys_obj->handle = drm_pci_alloc(dev, size, align); |
71acb5eb DA |
4166 | if (!phys_obj->handle) { |
4167 | ret = -ENOMEM; | |
4168 | goto kfree_obj; | |
4169 | } | |
4170 | #ifdef CONFIG_X86 | |
4171 | set_memory_wc((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE); | |
4172 | #endif | |
4173 | ||
4174 | dev_priv->mm.phys_objs[id - 1] = phys_obj; | |
4175 | ||
4176 | return 0; | |
4177 | kfree_obj: | |
9a298b2a | 4178 | kfree(phys_obj); |
71acb5eb DA |
4179 | return ret; |
4180 | } | |
4181 | ||
995b6762 | 4182 | static void i915_gem_free_phys_object(struct drm_device *dev, int id) |
71acb5eb DA |
4183 | { |
4184 | drm_i915_private_t *dev_priv = dev->dev_private; | |
4185 | struct drm_i915_gem_phys_object *phys_obj; | |
4186 | ||
4187 | if (!dev_priv->mm.phys_objs[id - 1]) | |
4188 | return; | |
4189 | ||
4190 | phys_obj = dev_priv->mm.phys_objs[id - 1]; | |
4191 | if (phys_obj->cur_obj) { | |
4192 | i915_gem_detach_phys_object(dev, phys_obj->cur_obj); | |
4193 | } | |
4194 | ||
4195 | #ifdef CONFIG_X86 | |
4196 | set_memory_wb((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE); | |
4197 | #endif | |
4198 | drm_pci_free(dev, phys_obj->handle); | |
4199 | kfree(phys_obj); | |
4200 | dev_priv->mm.phys_objs[id - 1] = NULL; | |
4201 | } | |
4202 | ||
4203 | void i915_gem_free_all_phys_object(struct drm_device *dev) | |
4204 | { | |
4205 | int i; | |
4206 | ||
260883c8 | 4207 | for (i = I915_GEM_PHYS_CURSOR_0; i <= I915_MAX_PHYS_OBJECT; i++) |
71acb5eb DA |
4208 | i915_gem_free_phys_object(dev, i); |
4209 | } | |
4210 | ||
4211 | void i915_gem_detach_phys_object(struct drm_device *dev, | |
05394f39 | 4212 | struct drm_i915_gem_object *obj) |
71acb5eb | 4213 | { |
05394f39 | 4214 | struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping; |
e5281ccd | 4215 | char *vaddr; |
71acb5eb | 4216 | int i; |
71acb5eb DA |
4217 | int page_count; |
4218 | ||
05394f39 | 4219 | if (!obj->phys_obj) |
71acb5eb | 4220 | return; |
05394f39 | 4221 | vaddr = obj->phys_obj->handle->vaddr; |
71acb5eb | 4222 | |
05394f39 | 4223 | page_count = obj->base.size / PAGE_SIZE; |
71acb5eb | 4224 | for (i = 0; i < page_count; i++) { |
5949eac4 | 4225 | struct page *page = shmem_read_mapping_page(mapping, i); |
e5281ccd CW |
4226 | if (!IS_ERR(page)) { |
4227 | char *dst = kmap_atomic(page); | |
4228 | memcpy(dst, vaddr + i*PAGE_SIZE, PAGE_SIZE); | |
4229 | kunmap_atomic(dst); | |
4230 | ||
4231 | drm_clflush_pages(&page, 1); | |
4232 | ||
4233 | set_page_dirty(page); | |
4234 | mark_page_accessed(page); | |
4235 | page_cache_release(page); | |
4236 | } | |
71acb5eb | 4237 | } |
40ce6575 | 4238 | intel_gtt_chipset_flush(); |
d78b47b9 | 4239 | |
05394f39 CW |
4240 | obj->phys_obj->cur_obj = NULL; |
4241 | obj->phys_obj = NULL; | |
71acb5eb DA |
4242 | } |
4243 | ||
4244 | int | |
4245 | i915_gem_attach_phys_object(struct drm_device *dev, | |
05394f39 | 4246 | struct drm_i915_gem_object *obj, |
6eeefaf3 CW |
4247 | int id, |
4248 | int align) | |
71acb5eb | 4249 | { |
05394f39 | 4250 | struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping; |
71acb5eb | 4251 | drm_i915_private_t *dev_priv = dev->dev_private; |
71acb5eb DA |
4252 | int ret = 0; |
4253 | int page_count; | |
4254 | int i; | |
4255 | ||
4256 | if (id > I915_MAX_PHYS_OBJECT) | |
4257 | return -EINVAL; | |
4258 | ||
05394f39 CW |
4259 | if (obj->phys_obj) { |
4260 | if (obj->phys_obj->id == id) | |
71acb5eb DA |
4261 | return 0; |
4262 | i915_gem_detach_phys_object(dev, obj); | |
4263 | } | |
4264 | ||
71acb5eb DA |
4265 | /* create a new object */ |
4266 | if (!dev_priv->mm.phys_objs[id - 1]) { | |
4267 | ret = i915_gem_init_phys_object(dev, id, | |
05394f39 | 4268 | obj->base.size, align); |
71acb5eb | 4269 | if (ret) { |
05394f39 CW |
4270 | DRM_ERROR("failed to init phys object %d size: %zu\n", |
4271 | id, obj->base.size); | |
e5281ccd | 4272 | return ret; |
71acb5eb DA |
4273 | } |
4274 | } | |
4275 | ||
4276 | /* bind to the object */ | |
05394f39 CW |
4277 | obj->phys_obj = dev_priv->mm.phys_objs[id - 1]; |
4278 | obj->phys_obj->cur_obj = obj; | |
71acb5eb | 4279 | |
05394f39 | 4280 | page_count = obj->base.size / PAGE_SIZE; |
71acb5eb DA |
4281 | |
4282 | for (i = 0; i < page_count; i++) { | |
e5281ccd CW |
4283 | struct page *page; |
4284 | char *dst, *src; | |
4285 | ||
5949eac4 | 4286 | page = shmem_read_mapping_page(mapping, i); |
e5281ccd CW |
4287 | if (IS_ERR(page)) |
4288 | return PTR_ERR(page); | |
71acb5eb | 4289 | |
ff75b9bc | 4290 | src = kmap_atomic(page); |
05394f39 | 4291 | dst = obj->phys_obj->handle->vaddr + (i * PAGE_SIZE); |
71acb5eb | 4292 | memcpy(dst, src, PAGE_SIZE); |
3e4d3af5 | 4293 | kunmap_atomic(src); |
71acb5eb | 4294 | |
e5281ccd CW |
4295 | mark_page_accessed(page); |
4296 | page_cache_release(page); | |
4297 | } | |
d78b47b9 | 4298 | |
71acb5eb | 4299 | return 0; |
71acb5eb DA |
4300 | } |
4301 | ||
4302 | static int | |
05394f39 CW |
4303 | i915_gem_phys_pwrite(struct drm_device *dev, |
4304 | struct drm_i915_gem_object *obj, | |
71acb5eb DA |
4305 | struct drm_i915_gem_pwrite *args, |
4306 | struct drm_file *file_priv) | |
4307 | { | |
05394f39 | 4308 | void *vaddr = obj->phys_obj->handle->vaddr + args->offset; |
b47b30cc | 4309 | char __user *user_data = (char __user *) (uintptr_t) args->data_ptr; |
71acb5eb | 4310 | |
b47b30cc CW |
4311 | if (__copy_from_user_inatomic_nocache(vaddr, user_data, args->size)) { |
4312 | unsigned long unwritten; | |
4313 | ||
4314 | /* The physical object once assigned is fixed for the lifetime | |
4315 | * of the obj, so we can safely drop the lock and continue | |
4316 | * to access vaddr. | |
4317 | */ | |
4318 | mutex_unlock(&dev->struct_mutex); | |
4319 | unwritten = copy_from_user(vaddr, user_data, args->size); | |
4320 | mutex_lock(&dev->struct_mutex); | |
4321 | if (unwritten) | |
4322 | return -EFAULT; | |
4323 | } | |
71acb5eb | 4324 | |
40ce6575 | 4325 | intel_gtt_chipset_flush(); |
71acb5eb DA |
4326 | return 0; |
4327 | } | |
b962442e | 4328 | |
f787a5f5 | 4329 | void i915_gem_release(struct drm_device *dev, struct drm_file *file) |
b962442e | 4330 | { |
f787a5f5 | 4331 | struct drm_i915_file_private *file_priv = file->driver_priv; |
b962442e EA |
4332 | |
4333 | /* Clean up our request list when the client is going away, so that | |
4334 | * later retire_requests won't dereference our soon-to-be-gone | |
4335 | * file_priv. | |
4336 | */ | |
1c25595f | 4337 | spin_lock(&file_priv->mm.lock); |
f787a5f5 CW |
4338 | while (!list_empty(&file_priv->mm.request_list)) { |
4339 | struct drm_i915_gem_request *request; | |
4340 | ||
4341 | request = list_first_entry(&file_priv->mm.request_list, | |
4342 | struct drm_i915_gem_request, | |
4343 | client_list); | |
4344 | list_del(&request->client_list); | |
4345 | request->file_priv = NULL; | |
4346 | } | |
1c25595f | 4347 | spin_unlock(&file_priv->mm.lock); |
b962442e | 4348 | } |
31169714 | 4349 | |
31169714 | 4350 | static int |
1495f230 | 4351 | i915_gem_inactive_shrink(struct shrinker *shrinker, struct shrink_control *sc) |
31169714 | 4352 | { |
17250b71 CW |
4353 | struct drm_i915_private *dev_priv = |
4354 | container_of(shrinker, | |
4355 | struct drm_i915_private, | |
4356 | mm.inactive_shrinker); | |
4357 | struct drm_device *dev = dev_priv->dev; | |
6c085a72 | 4358 | struct drm_i915_gem_object *obj; |
1495f230 | 4359 | int nr_to_scan = sc->nr_to_scan; |
17250b71 CW |
4360 | int cnt; |
4361 | ||
4362 | if (!mutex_trylock(&dev->struct_mutex)) | |
bbe2e11a | 4363 | return 0; |
31169714 | 4364 | |
6c085a72 CW |
4365 | if (nr_to_scan) { |
4366 | nr_to_scan -= i915_gem_purge(dev_priv, nr_to_scan); | |
4367 | if (nr_to_scan > 0) | |
4368 | i915_gem_shrink_all(dev_priv); | |
31169714 CW |
4369 | } |
4370 | ||
17250b71 | 4371 | cnt = 0; |
6c085a72 CW |
4372 | list_for_each_entry(obj, &dev_priv->mm.unbound_list, gtt_list) |
4373 | cnt += obj->base.size >> PAGE_SHIFT; | |
4374 | list_for_each_entry(obj, &dev_priv->mm.bound_list, gtt_list) | |
4375 | if (obj->pin_count == 0) | |
4376 | cnt += obj->base.size >> PAGE_SHIFT; | |
17250b71 | 4377 | |
17250b71 | 4378 | mutex_unlock(&dev->struct_mutex); |
6c085a72 | 4379 | return cnt; |
31169714 | 4380 | } |