Commit | Line | Data |
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673a394b EA |
1 | /* |
2 | * Copyright © 2008 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | * | |
26 | */ | |
27 | ||
760285e7 | 28 | #include <drm/drmP.h> |
0de23977 | 29 | #include <drm/drm_vma_manager.h> |
760285e7 | 30 | #include <drm/i915_drm.h> |
673a394b | 31 | #include "i915_drv.h" |
1c5d22f7 | 32 | #include "i915_trace.h" |
652c393a | 33 | #include "intel_drv.h" |
2cfcd32a | 34 | #include <linux/oom.h> |
5949eac4 | 35 | #include <linux/shmem_fs.h> |
5a0e3ad6 | 36 | #include <linux/slab.h> |
673a394b | 37 | #include <linux/swap.h> |
79e53945 | 38 | #include <linux/pci.h> |
1286ff73 | 39 | #include <linux/dma-buf.h> |
673a394b | 40 | |
05394f39 | 41 | static void i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj); |
2c22569b CW |
42 | static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj, |
43 | bool force); | |
07fe0b12 | 44 | static __must_check int |
23f54483 BW |
45 | i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj, |
46 | bool readonly); | |
c8725f3d CW |
47 | static void |
48 | i915_gem_object_retire(struct drm_i915_gem_object *obj); | |
49 | ||
61050808 CW |
50 | static void i915_gem_write_fence(struct drm_device *dev, int reg, |
51 | struct drm_i915_gem_object *obj); | |
52 | static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj, | |
53 | struct drm_i915_fence_reg *fence, | |
54 | bool enable); | |
55 | ||
ceabbba5 | 56 | static unsigned long i915_gem_shrinker_count(struct shrinker *shrinker, |
7dc19d5a | 57 | struct shrink_control *sc); |
ceabbba5 | 58 | static unsigned long i915_gem_shrinker_scan(struct shrinker *shrinker, |
7dc19d5a | 59 | struct shrink_control *sc); |
2cfcd32a CW |
60 | static int i915_gem_shrinker_oom(struct notifier_block *nb, |
61 | unsigned long event, | |
62 | void *ptr); | |
d9973b43 CW |
63 | static unsigned long i915_gem_purge(struct drm_i915_private *dev_priv, long target); |
64 | static unsigned long i915_gem_shrink_all(struct drm_i915_private *dev_priv); | |
31169714 | 65 | |
c76ce038 CW |
66 | static bool cpu_cache_is_coherent(struct drm_device *dev, |
67 | enum i915_cache_level level) | |
68 | { | |
69 | return HAS_LLC(dev) || level != I915_CACHE_NONE; | |
70 | } | |
71 | ||
2c22569b CW |
72 | static bool cpu_write_needs_clflush(struct drm_i915_gem_object *obj) |
73 | { | |
74 | if (!cpu_cache_is_coherent(obj->base.dev, obj->cache_level)) | |
75 | return true; | |
76 | ||
77 | return obj->pin_display; | |
78 | } | |
79 | ||
61050808 CW |
80 | static inline void i915_gem_object_fence_lost(struct drm_i915_gem_object *obj) |
81 | { | |
82 | if (obj->tiling_mode) | |
83 | i915_gem_release_mmap(obj); | |
84 | ||
85 | /* As we do not have an associated fence register, we will force | |
86 | * a tiling change if we ever need to acquire one. | |
87 | */ | |
5d82e3e6 | 88 | obj->fence_dirty = false; |
61050808 CW |
89 | obj->fence_reg = I915_FENCE_REG_NONE; |
90 | } | |
91 | ||
73aa808f CW |
92 | /* some bookkeeping */ |
93 | static void i915_gem_info_add_obj(struct drm_i915_private *dev_priv, | |
94 | size_t size) | |
95 | { | |
c20e8355 | 96 | spin_lock(&dev_priv->mm.object_stat_lock); |
73aa808f CW |
97 | dev_priv->mm.object_count++; |
98 | dev_priv->mm.object_memory += size; | |
c20e8355 | 99 | spin_unlock(&dev_priv->mm.object_stat_lock); |
73aa808f CW |
100 | } |
101 | ||
102 | static void i915_gem_info_remove_obj(struct drm_i915_private *dev_priv, | |
103 | size_t size) | |
104 | { | |
c20e8355 | 105 | spin_lock(&dev_priv->mm.object_stat_lock); |
73aa808f CW |
106 | dev_priv->mm.object_count--; |
107 | dev_priv->mm.object_memory -= size; | |
c20e8355 | 108 | spin_unlock(&dev_priv->mm.object_stat_lock); |
73aa808f CW |
109 | } |
110 | ||
21dd3734 | 111 | static int |
33196ded | 112 | i915_gem_wait_for_error(struct i915_gpu_error *error) |
30dbf0c0 | 113 | { |
30dbf0c0 CW |
114 | int ret; |
115 | ||
7abb690a DV |
116 | #define EXIT_COND (!i915_reset_in_progress(error) || \ |
117 | i915_terminally_wedged(error)) | |
1f83fee0 | 118 | if (EXIT_COND) |
30dbf0c0 CW |
119 | return 0; |
120 | ||
0a6759c6 DV |
121 | /* |
122 | * Only wait 10 seconds for the gpu reset to complete to avoid hanging | |
123 | * userspace. If it takes that long something really bad is going on and | |
124 | * we should simply try to bail out and fail as gracefully as possible. | |
125 | */ | |
1f83fee0 DV |
126 | ret = wait_event_interruptible_timeout(error->reset_queue, |
127 | EXIT_COND, | |
128 | 10*HZ); | |
0a6759c6 DV |
129 | if (ret == 0) { |
130 | DRM_ERROR("Timed out waiting for the gpu reset to complete\n"); | |
131 | return -EIO; | |
132 | } else if (ret < 0) { | |
30dbf0c0 | 133 | return ret; |
0a6759c6 | 134 | } |
1f83fee0 | 135 | #undef EXIT_COND |
30dbf0c0 | 136 | |
21dd3734 | 137 | return 0; |
30dbf0c0 CW |
138 | } |
139 | ||
54cf91dc | 140 | int i915_mutex_lock_interruptible(struct drm_device *dev) |
76c1dec1 | 141 | { |
33196ded | 142 | struct drm_i915_private *dev_priv = dev->dev_private; |
76c1dec1 CW |
143 | int ret; |
144 | ||
33196ded | 145 | ret = i915_gem_wait_for_error(&dev_priv->gpu_error); |
76c1dec1 CW |
146 | if (ret) |
147 | return ret; | |
148 | ||
149 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
150 | if (ret) | |
151 | return ret; | |
152 | ||
23bc5982 | 153 | WARN_ON(i915_verify_lists(dev)); |
76c1dec1 CW |
154 | return 0; |
155 | } | |
30dbf0c0 | 156 | |
7d1c4804 | 157 | static inline bool |
05394f39 | 158 | i915_gem_object_is_inactive(struct drm_i915_gem_object *obj) |
7d1c4804 | 159 | { |
9843877d | 160 | return i915_gem_obj_bound_any(obj) && !obj->active; |
7d1c4804 CW |
161 | } |
162 | ||
79e53945 JB |
163 | int |
164 | i915_gem_init_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 165 | struct drm_file *file) |
79e53945 | 166 | { |
93d18799 | 167 | struct drm_i915_private *dev_priv = dev->dev_private; |
79e53945 | 168 | struct drm_i915_gem_init *args = data; |
2021746e | 169 | |
7bb6fb8d DV |
170 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
171 | return -ENODEV; | |
172 | ||
2021746e CW |
173 | if (args->gtt_start >= args->gtt_end || |
174 | (args->gtt_end | args->gtt_start) & (PAGE_SIZE - 1)) | |
175 | return -EINVAL; | |
79e53945 | 176 | |
f534bc0b DV |
177 | /* GEM with user mode setting was never supported on ilk and later. */ |
178 | if (INTEL_INFO(dev)->gen >= 5) | |
179 | return -ENODEV; | |
180 | ||
79e53945 | 181 | mutex_lock(&dev->struct_mutex); |
d7e5008f BW |
182 | i915_gem_setup_global_gtt(dev, args->gtt_start, args->gtt_end, |
183 | args->gtt_end); | |
93d18799 | 184 | dev_priv->gtt.mappable_end = args->gtt_end; |
673a394b EA |
185 | mutex_unlock(&dev->struct_mutex); |
186 | ||
2021746e | 187 | return 0; |
673a394b EA |
188 | } |
189 | ||
5a125c3c EA |
190 | int |
191 | i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 192 | struct drm_file *file) |
5a125c3c | 193 | { |
73aa808f | 194 | struct drm_i915_private *dev_priv = dev->dev_private; |
5a125c3c | 195 | struct drm_i915_gem_get_aperture *args = data; |
6299f992 CW |
196 | struct drm_i915_gem_object *obj; |
197 | size_t pinned; | |
5a125c3c | 198 | |
6299f992 | 199 | pinned = 0; |
73aa808f | 200 | mutex_lock(&dev->struct_mutex); |
35c20a60 | 201 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) |
d7f46fc4 | 202 | if (i915_gem_obj_is_pinned(obj)) |
f343c5f6 | 203 | pinned += i915_gem_obj_ggtt_size(obj); |
73aa808f | 204 | mutex_unlock(&dev->struct_mutex); |
5a125c3c | 205 | |
853ba5d2 | 206 | args->aper_size = dev_priv->gtt.base.total; |
0206e353 | 207 | args->aper_available_size = args->aper_size - pinned; |
6299f992 | 208 | |
5a125c3c EA |
209 | return 0; |
210 | } | |
211 | ||
00731155 CW |
212 | static void i915_gem_object_detach_phys(struct drm_i915_gem_object *obj) |
213 | { | |
214 | drm_dma_handle_t *phys = obj->phys_handle; | |
215 | ||
216 | if (!phys) | |
217 | return; | |
218 | ||
219 | if (obj->madv == I915_MADV_WILLNEED) { | |
220 | struct address_space *mapping = file_inode(obj->base.filp)->i_mapping; | |
221 | char *vaddr = phys->vaddr; | |
222 | int i; | |
223 | ||
224 | for (i = 0; i < obj->base.size / PAGE_SIZE; i++) { | |
225 | struct page *page = shmem_read_mapping_page(mapping, i); | |
226 | if (!IS_ERR(page)) { | |
227 | char *dst = kmap_atomic(page); | |
228 | memcpy(dst, vaddr, PAGE_SIZE); | |
229 | drm_clflush_virt_range(dst, PAGE_SIZE); | |
230 | kunmap_atomic(dst); | |
231 | ||
232 | set_page_dirty(page); | |
233 | mark_page_accessed(page); | |
234 | page_cache_release(page); | |
235 | } | |
236 | vaddr += PAGE_SIZE; | |
237 | } | |
238 | i915_gem_chipset_flush(obj->base.dev); | |
239 | } | |
240 | ||
241 | #ifdef CONFIG_X86 | |
242 | set_memory_wb((unsigned long)phys->vaddr, phys->size / PAGE_SIZE); | |
243 | #endif | |
244 | drm_pci_free(obj->base.dev, phys); | |
245 | obj->phys_handle = NULL; | |
246 | } | |
247 | ||
248 | int | |
249 | i915_gem_object_attach_phys(struct drm_i915_gem_object *obj, | |
250 | int align) | |
251 | { | |
252 | drm_dma_handle_t *phys; | |
253 | struct address_space *mapping; | |
254 | char *vaddr; | |
255 | int i; | |
256 | ||
257 | if (obj->phys_handle) { | |
258 | if ((unsigned long)obj->phys_handle->vaddr & (align -1)) | |
259 | return -EBUSY; | |
260 | ||
261 | return 0; | |
262 | } | |
263 | ||
264 | if (obj->madv != I915_MADV_WILLNEED) | |
265 | return -EFAULT; | |
266 | ||
267 | if (obj->base.filp == NULL) | |
268 | return -EINVAL; | |
269 | ||
270 | /* create a new object */ | |
271 | phys = drm_pci_alloc(obj->base.dev, obj->base.size, align); | |
272 | if (!phys) | |
273 | return -ENOMEM; | |
274 | ||
275 | vaddr = phys->vaddr; | |
276 | #ifdef CONFIG_X86 | |
277 | set_memory_wc((unsigned long)vaddr, phys->size / PAGE_SIZE); | |
278 | #endif | |
279 | mapping = file_inode(obj->base.filp)->i_mapping; | |
280 | for (i = 0; i < obj->base.size / PAGE_SIZE; i++) { | |
281 | struct page *page; | |
282 | char *src; | |
283 | ||
284 | page = shmem_read_mapping_page(mapping, i); | |
285 | if (IS_ERR(page)) { | |
286 | #ifdef CONFIG_X86 | |
287 | set_memory_wb((unsigned long)phys->vaddr, phys->size / PAGE_SIZE); | |
288 | #endif | |
289 | drm_pci_free(obj->base.dev, phys); | |
290 | return PTR_ERR(page); | |
291 | } | |
292 | ||
293 | src = kmap_atomic(page); | |
294 | memcpy(vaddr, src, PAGE_SIZE); | |
295 | kunmap_atomic(src); | |
296 | ||
297 | mark_page_accessed(page); | |
298 | page_cache_release(page); | |
299 | ||
300 | vaddr += PAGE_SIZE; | |
301 | } | |
302 | ||
303 | obj->phys_handle = phys; | |
304 | return 0; | |
305 | } | |
306 | ||
307 | static int | |
308 | i915_gem_phys_pwrite(struct drm_i915_gem_object *obj, | |
309 | struct drm_i915_gem_pwrite *args, | |
310 | struct drm_file *file_priv) | |
311 | { | |
312 | struct drm_device *dev = obj->base.dev; | |
313 | void *vaddr = obj->phys_handle->vaddr + args->offset; | |
314 | char __user *user_data = to_user_ptr(args->data_ptr); | |
315 | ||
316 | if (__copy_from_user_inatomic_nocache(vaddr, user_data, args->size)) { | |
317 | unsigned long unwritten; | |
318 | ||
319 | /* The physical object once assigned is fixed for the lifetime | |
320 | * of the obj, so we can safely drop the lock and continue | |
321 | * to access vaddr. | |
322 | */ | |
323 | mutex_unlock(&dev->struct_mutex); | |
324 | unwritten = copy_from_user(vaddr, user_data, args->size); | |
325 | mutex_lock(&dev->struct_mutex); | |
326 | if (unwritten) | |
327 | return -EFAULT; | |
328 | } | |
329 | ||
330 | i915_gem_chipset_flush(dev); | |
331 | return 0; | |
332 | } | |
333 | ||
42dcedd4 CW |
334 | void *i915_gem_object_alloc(struct drm_device *dev) |
335 | { | |
336 | struct drm_i915_private *dev_priv = dev->dev_private; | |
fac15c10 | 337 | return kmem_cache_zalloc(dev_priv->slab, GFP_KERNEL); |
42dcedd4 CW |
338 | } |
339 | ||
340 | void i915_gem_object_free(struct drm_i915_gem_object *obj) | |
341 | { | |
342 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; | |
343 | kmem_cache_free(dev_priv->slab, obj); | |
344 | } | |
345 | ||
ff72145b DA |
346 | static int |
347 | i915_gem_create(struct drm_file *file, | |
348 | struct drm_device *dev, | |
349 | uint64_t size, | |
350 | uint32_t *handle_p) | |
673a394b | 351 | { |
05394f39 | 352 | struct drm_i915_gem_object *obj; |
a1a2d1d3 PP |
353 | int ret; |
354 | u32 handle; | |
673a394b | 355 | |
ff72145b | 356 | size = roundup(size, PAGE_SIZE); |
8ffc0246 CW |
357 | if (size == 0) |
358 | return -EINVAL; | |
673a394b EA |
359 | |
360 | /* Allocate the new object */ | |
ff72145b | 361 | obj = i915_gem_alloc_object(dev, size); |
673a394b EA |
362 | if (obj == NULL) |
363 | return -ENOMEM; | |
364 | ||
05394f39 | 365 | ret = drm_gem_handle_create(file, &obj->base, &handle); |
202f2fef | 366 | /* drop reference from allocate - handle holds it now */ |
d861e338 DV |
367 | drm_gem_object_unreference_unlocked(&obj->base); |
368 | if (ret) | |
369 | return ret; | |
202f2fef | 370 | |
ff72145b | 371 | *handle_p = handle; |
673a394b EA |
372 | return 0; |
373 | } | |
374 | ||
ff72145b DA |
375 | int |
376 | i915_gem_dumb_create(struct drm_file *file, | |
377 | struct drm_device *dev, | |
378 | struct drm_mode_create_dumb *args) | |
379 | { | |
380 | /* have to work out size/pitch and return them */ | |
de45eaf7 | 381 | args->pitch = ALIGN(args->width * DIV_ROUND_UP(args->bpp, 8), 64); |
ff72145b DA |
382 | args->size = args->pitch * args->height; |
383 | return i915_gem_create(file, dev, | |
384 | args->size, &args->handle); | |
385 | } | |
386 | ||
ff72145b DA |
387 | /** |
388 | * Creates a new mm object and returns a handle to it. | |
389 | */ | |
390 | int | |
391 | i915_gem_create_ioctl(struct drm_device *dev, void *data, | |
392 | struct drm_file *file) | |
393 | { | |
394 | struct drm_i915_gem_create *args = data; | |
63ed2cb2 | 395 | |
ff72145b DA |
396 | return i915_gem_create(file, dev, |
397 | args->size, &args->handle); | |
398 | } | |
399 | ||
8461d226 DV |
400 | static inline int |
401 | __copy_to_user_swizzled(char __user *cpu_vaddr, | |
402 | const char *gpu_vaddr, int gpu_offset, | |
403 | int length) | |
404 | { | |
405 | int ret, cpu_offset = 0; | |
406 | ||
407 | while (length > 0) { | |
408 | int cacheline_end = ALIGN(gpu_offset + 1, 64); | |
409 | int this_length = min(cacheline_end - gpu_offset, length); | |
410 | int swizzled_gpu_offset = gpu_offset ^ 64; | |
411 | ||
412 | ret = __copy_to_user(cpu_vaddr + cpu_offset, | |
413 | gpu_vaddr + swizzled_gpu_offset, | |
414 | this_length); | |
415 | if (ret) | |
416 | return ret + length; | |
417 | ||
418 | cpu_offset += this_length; | |
419 | gpu_offset += this_length; | |
420 | length -= this_length; | |
421 | } | |
422 | ||
423 | return 0; | |
424 | } | |
425 | ||
8c59967c | 426 | static inline int |
4f0c7cfb BW |
427 | __copy_from_user_swizzled(char *gpu_vaddr, int gpu_offset, |
428 | const char __user *cpu_vaddr, | |
8c59967c DV |
429 | int length) |
430 | { | |
431 | int ret, cpu_offset = 0; | |
432 | ||
433 | while (length > 0) { | |
434 | int cacheline_end = ALIGN(gpu_offset + 1, 64); | |
435 | int this_length = min(cacheline_end - gpu_offset, length); | |
436 | int swizzled_gpu_offset = gpu_offset ^ 64; | |
437 | ||
438 | ret = __copy_from_user(gpu_vaddr + swizzled_gpu_offset, | |
439 | cpu_vaddr + cpu_offset, | |
440 | this_length); | |
441 | if (ret) | |
442 | return ret + length; | |
443 | ||
444 | cpu_offset += this_length; | |
445 | gpu_offset += this_length; | |
446 | length -= this_length; | |
447 | } | |
448 | ||
449 | return 0; | |
450 | } | |
451 | ||
4c914c0c BV |
452 | /* |
453 | * Pins the specified object's pages and synchronizes the object with | |
454 | * GPU accesses. Sets needs_clflush to non-zero if the caller should | |
455 | * flush the object from the CPU cache. | |
456 | */ | |
457 | int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object *obj, | |
458 | int *needs_clflush) | |
459 | { | |
460 | int ret; | |
461 | ||
462 | *needs_clflush = 0; | |
463 | ||
464 | if (!obj->base.filp) | |
465 | return -EINVAL; | |
466 | ||
467 | if (!(obj->base.read_domains & I915_GEM_DOMAIN_CPU)) { | |
468 | /* If we're not in the cpu read domain, set ourself into the gtt | |
469 | * read domain and manually flush cachelines (if required). This | |
470 | * optimizes for the case when the gpu will dirty the data | |
471 | * anyway again before the next pread happens. */ | |
472 | *needs_clflush = !cpu_cache_is_coherent(obj->base.dev, | |
473 | obj->cache_level); | |
474 | ret = i915_gem_object_wait_rendering(obj, true); | |
475 | if (ret) | |
476 | return ret; | |
c8725f3d CW |
477 | |
478 | i915_gem_object_retire(obj); | |
4c914c0c BV |
479 | } |
480 | ||
481 | ret = i915_gem_object_get_pages(obj); | |
482 | if (ret) | |
483 | return ret; | |
484 | ||
485 | i915_gem_object_pin_pages(obj); | |
486 | ||
487 | return ret; | |
488 | } | |
489 | ||
d174bd64 DV |
490 | /* Per-page copy function for the shmem pread fastpath. |
491 | * Flushes invalid cachelines before reading the target if | |
492 | * needs_clflush is set. */ | |
eb01459f | 493 | static int |
d174bd64 DV |
494 | shmem_pread_fast(struct page *page, int shmem_page_offset, int page_length, |
495 | char __user *user_data, | |
496 | bool page_do_bit17_swizzling, bool needs_clflush) | |
497 | { | |
498 | char *vaddr; | |
499 | int ret; | |
500 | ||
e7e58eb5 | 501 | if (unlikely(page_do_bit17_swizzling)) |
d174bd64 DV |
502 | return -EINVAL; |
503 | ||
504 | vaddr = kmap_atomic(page); | |
505 | if (needs_clflush) | |
506 | drm_clflush_virt_range(vaddr + shmem_page_offset, | |
507 | page_length); | |
508 | ret = __copy_to_user_inatomic(user_data, | |
509 | vaddr + shmem_page_offset, | |
510 | page_length); | |
511 | kunmap_atomic(vaddr); | |
512 | ||
f60d7f0c | 513 | return ret ? -EFAULT : 0; |
d174bd64 DV |
514 | } |
515 | ||
23c18c71 DV |
516 | static void |
517 | shmem_clflush_swizzled_range(char *addr, unsigned long length, | |
518 | bool swizzled) | |
519 | { | |
e7e58eb5 | 520 | if (unlikely(swizzled)) { |
23c18c71 DV |
521 | unsigned long start = (unsigned long) addr; |
522 | unsigned long end = (unsigned long) addr + length; | |
523 | ||
524 | /* For swizzling simply ensure that we always flush both | |
525 | * channels. Lame, but simple and it works. Swizzled | |
526 | * pwrite/pread is far from a hotpath - current userspace | |
527 | * doesn't use it at all. */ | |
528 | start = round_down(start, 128); | |
529 | end = round_up(end, 128); | |
530 | ||
531 | drm_clflush_virt_range((void *)start, end - start); | |
532 | } else { | |
533 | drm_clflush_virt_range(addr, length); | |
534 | } | |
535 | ||
536 | } | |
537 | ||
d174bd64 DV |
538 | /* Only difference to the fast-path function is that this can handle bit17 |
539 | * and uses non-atomic copy and kmap functions. */ | |
540 | static int | |
541 | shmem_pread_slow(struct page *page, int shmem_page_offset, int page_length, | |
542 | char __user *user_data, | |
543 | bool page_do_bit17_swizzling, bool needs_clflush) | |
544 | { | |
545 | char *vaddr; | |
546 | int ret; | |
547 | ||
548 | vaddr = kmap(page); | |
549 | if (needs_clflush) | |
23c18c71 DV |
550 | shmem_clflush_swizzled_range(vaddr + shmem_page_offset, |
551 | page_length, | |
552 | page_do_bit17_swizzling); | |
d174bd64 DV |
553 | |
554 | if (page_do_bit17_swizzling) | |
555 | ret = __copy_to_user_swizzled(user_data, | |
556 | vaddr, shmem_page_offset, | |
557 | page_length); | |
558 | else | |
559 | ret = __copy_to_user(user_data, | |
560 | vaddr + shmem_page_offset, | |
561 | page_length); | |
562 | kunmap(page); | |
563 | ||
f60d7f0c | 564 | return ret ? - EFAULT : 0; |
d174bd64 DV |
565 | } |
566 | ||
eb01459f | 567 | static int |
dbf7bff0 DV |
568 | i915_gem_shmem_pread(struct drm_device *dev, |
569 | struct drm_i915_gem_object *obj, | |
570 | struct drm_i915_gem_pread *args, | |
571 | struct drm_file *file) | |
eb01459f | 572 | { |
8461d226 | 573 | char __user *user_data; |
eb01459f | 574 | ssize_t remain; |
8461d226 | 575 | loff_t offset; |
eb2c0c81 | 576 | int shmem_page_offset, page_length, ret = 0; |
8461d226 | 577 | int obj_do_bit17_swizzling, page_do_bit17_swizzling; |
96d79b52 | 578 | int prefaulted = 0; |
8489731c | 579 | int needs_clflush = 0; |
67d5a50c | 580 | struct sg_page_iter sg_iter; |
eb01459f | 581 | |
2bb4629a | 582 | user_data = to_user_ptr(args->data_ptr); |
eb01459f EA |
583 | remain = args->size; |
584 | ||
8461d226 | 585 | obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj); |
eb01459f | 586 | |
4c914c0c | 587 | ret = i915_gem_obj_prepare_shmem_read(obj, &needs_clflush); |
f60d7f0c CW |
588 | if (ret) |
589 | return ret; | |
590 | ||
8461d226 | 591 | offset = args->offset; |
eb01459f | 592 | |
67d5a50c ID |
593 | for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, |
594 | offset >> PAGE_SHIFT) { | |
2db76d7c | 595 | struct page *page = sg_page_iter_page(&sg_iter); |
9da3da66 CW |
596 | |
597 | if (remain <= 0) | |
598 | break; | |
599 | ||
eb01459f EA |
600 | /* Operation in this page |
601 | * | |
eb01459f | 602 | * shmem_page_offset = offset within page in shmem file |
eb01459f EA |
603 | * page_length = bytes to copy for this page |
604 | */ | |
c8cbbb8b | 605 | shmem_page_offset = offset_in_page(offset); |
eb01459f EA |
606 | page_length = remain; |
607 | if ((shmem_page_offset + page_length) > PAGE_SIZE) | |
608 | page_length = PAGE_SIZE - shmem_page_offset; | |
eb01459f | 609 | |
8461d226 DV |
610 | page_do_bit17_swizzling = obj_do_bit17_swizzling && |
611 | (page_to_phys(page) & (1 << 17)) != 0; | |
612 | ||
d174bd64 DV |
613 | ret = shmem_pread_fast(page, shmem_page_offset, page_length, |
614 | user_data, page_do_bit17_swizzling, | |
615 | needs_clflush); | |
616 | if (ret == 0) | |
617 | goto next_page; | |
dbf7bff0 | 618 | |
dbf7bff0 DV |
619 | mutex_unlock(&dev->struct_mutex); |
620 | ||
d330a953 | 621 | if (likely(!i915.prefault_disable) && !prefaulted) { |
f56f821f | 622 | ret = fault_in_multipages_writeable(user_data, remain); |
96d79b52 DV |
623 | /* Userspace is tricking us, but we've already clobbered |
624 | * its pages with the prefault and promised to write the | |
625 | * data up to the first fault. Hence ignore any errors | |
626 | * and just continue. */ | |
627 | (void)ret; | |
628 | prefaulted = 1; | |
629 | } | |
eb01459f | 630 | |
d174bd64 DV |
631 | ret = shmem_pread_slow(page, shmem_page_offset, page_length, |
632 | user_data, page_do_bit17_swizzling, | |
633 | needs_clflush); | |
eb01459f | 634 | |
dbf7bff0 | 635 | mutex_lock(&dev->struct_mutex); |
f60d7f0c | 636 | |
f60d7f0c | 637 | if (ret) |
8461d226 | 638 | goto out; |
8461d226 | 639 | |
17793c9a | 640 | next_page: |
eb01459f | 641 | remain -= page_length; |
8461d226 | 642 | user_data += page_length; |
eb01459f EA |
643 | offset += page_length; |
644 | } | |
645 | ||
4f27b75d | 646 | out: |
f60d7f0c CW |
647 | i915_gem_object_unpin_pages(obj); |
648 | ||
eb01459f EA |
649 | return ret; |
650 | } | |
651 | ||
673a394b EA |
652 | /** |
653 | * Reads data from the object referenced by handle. | |
654 | * | |
655 | * On error, the contents of *data are undefined. | |
656 | */ | |
657 | int | |
658 | i915_gem_pread_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 659 | struct drm_file *file) |
673a394b EA |
660 | { |
661 | struct drm_i915_gem_pread *args = data; | |
05394f39 | 662 | struct drm_i915_gem_object *obj; |
35b62a89 | 663 | int ret = 0; |
673a394b | 664 | |
51311d0a CW |
665 | if (args->size == 0) |
666 | return 0; | |
667 | ||
668 | if (!access_ok(VERIFY_WRITE, | |
2bb4629a | 669 | to_user_ptr(args->data_ptr), |
51311d0a CW |
670 | args->size)) |
671 | return -EFAULT; | |
672 | ||
4f27b75d | 673 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 674 | if (ret) |
4f27b75d | 675 | return ret; |
673a394b | 676 | |
05394f39 | 677 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 678 | if (&obj->base == NULL) { |
1d7cfea1 CW |
679 | ret = -ENOENT; |
680 | goto unlock; | |
4f27b75d | 681 | } |
673a394b | 682 | |
7dcd2499 | 683 | /* Bounds check source. */ |
05394f39 CW |
684 | if (args->offset > obj->base.size || |
685 | args->size > obj->base.size - args->offset) { | |
ce9d419d | 686 | ret = -EINVAL; |
35b62a89 | 687 | goto out; |
ce9d419d CW |
688 | } |
689 | ||
1286ff73 DV |
690 | /* prime objects have no backing filp to GEM pread/pwrite |
691 | * pages from. | |
692 | */ | |
693 | if (!obj->base.filp) { | |
694 | ret = -EINVAL; | |
695 | goto out; | |
696 | } | |
697 | ||
db53a302 CW |
698 | trace_i915_gem_object_pread(obj, args->offset, args->size); |
699 | ||
dbf7bff0 | 700 | ret = i915_gem_shmem_pread(dev, obj, args, file); |
673a394b | 701 | |
35b62a89 | 702 | out: |
05394f39 | 703 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 704 | unlock: |
4f27b75d | 705 | mutex_unlock(&dev->struct_mutex); |
eb01459f | 706 | return ret; |
673a394b EA |
707 | } |
708 | ||
0839ccb8 KP |
709 | /* This is the fast write path which cannot handle |
710 | * page faults in the source data | |
9b7530cc | 711 | */ |
0839ccb8 KP |
712 | |
713 | static inline int | |
714 | fast_user_write(struct io_mapping *mapping, | |
715 | loff_t page_base, int page_offset, | |
716 | char __user *user_data, | |
717 | int length) | |
9b7530cc | 718 | { |
4f0c7cfb BW |
719 | void __iomem *vaddr_atomic; |
720 | void *vaddr; | |
0839ccb8 | 721 | unsigned long unwritten; |
9b7530cc | 722 | |
3e4d3af5 | 723 | vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base); |
4f0c7cfb BW |
724 | /* We can use the cpu mem copy function because this is X86. */ |
725 | vaddr = (void __force*)vaddr_atomic + page_offset; | |
726 | unwritten = __copy_from_user_inatomic_nocache(vaddr, | |
0839ccb8 | 727 | user_data, length); |
3e4d3af5 | 728 | io_mapping_unmap_atomic(vaddr_atomic); |
fbd5a26d | 729 | return unwritten; |
0839ccb8 KP |
730 | } |
731 | ||
3de09aa3 EA |
732 | /** |
733 | * This is the fast pwrite path, where we copy the data directly from the | |
734 | * user into the GTT, uncached. | |
735 | */ | |
673a394b | 736 | static int |
05394f39 CW |
737 | i915_gem_gtt_pwrite_fast(struct drm_device *dev, |
738 | struct drm_i915_gem_object *obj, | |
3de09aa3 | 739 | struct drm_i915_gem_pwrite *args, |
05394f39 | 740 | struct drm_file *file) |
673a394b | 741 | { |
3e31c6c0 | 742 | struct drm_i915_private *dev_priv = dev->dev_private; |
673a394b | 743 | ssize_t remain; |
0839ccb8 | 744 | loff_t offset, page_base; |
673a394b | 745 | char __user *user_data; |
935aaa69 DV |
746 | int page_offset, page_length, ret; |
747 | ||
1ec9e26d | 748 | ret = i915_gem_obj_ggtt_pin(obj, 0, PIN_MAPPABLE | PIN_NONBLOCK); |
935aaa69 DV |
749 | if (ret) |
750 | goto out; | |
751 | ||
752 | ret = i915_gem_object_set_to_gtt_domain(obj, true); | |
753 | if (ret) | |
754 | goto out_unpin; | |
755 | ||
756 | ret = i915_gem_object_put_fence(obj); | |
757 | if (ret) | |
758 | goto out_unpin; | |
673a394b | 759 | |
2bb4629a | 760 | user_data = to_user_ptr(args->data_ptr); |
673a394b | 761 | remain = args->size; |
673a394b | 762 | |
f343c5f6 | 763 | offset = i915_gem_obj_ggtt_offset(obj) + args->offset; |
673a394b EA |
764 | |
765 | while (remain > 0) { | |
766 | /* Operation in this page | |
767 | * | |
0839ccb8 KP |
768 | * page_base = page offset within aperture |
769 | * page_offset = offset within page | |
770 | * page_length = bytes to copy for this page | |
673a394b | 771 | */ |
c8cbbb8b CW |
772 | page_base = offset & PAGE_MASK; |
773 | page_offset = offset_in_page(offset); | |
0839ccb8 KP |
774 | page_length = remain; |
775 | if ((page_offset + remain) > PAGE_SIZE) | |
776 | page_length = PAGE_SIZE - page_offset; | |
777 | ||
0839ccb8 | 778 | /* If we get a fault while copying data, then (presumably) our |
3de09aa3 EA |
779 | * source page isn't available. Return the error and we'll |
780 | * retry in the slow path. | |
0839ccb8 | 781 | */ |
5d4545ae | 782 | if (fast_user_write(dev_priv->gtt.mappable, page_base, |
935aaa69 DV |
783 | page_offset, user_data, page_length)) { |
784 | ret = -EFAULT; | |
785 | goto out_unpin; | |
786 | } | |
673a394b | 787 | |
0839ccb8 KP |
788 | remain -= page_length; |
789 | user_data += page_length; | |
790 | offset += page_length; | |
673a394b | 791 | } |
673a394b | 792 | |
935aaa69 | 793 | out_unpin: |
d7f46fc4 | 794 | i915_gem_object_ggtt_unpin(obj); |
935aaa69 | 795 | out: |
3de09aa3 | 796 | return ret; |
673a394b EA |
797 | } |
798 | ||
d174bd64 DV |
799 | /* Per-page copy function for the shmem pwrite fastpath. |
800 | * Flushes invalid cachelines before writing to the target if | |
801 | * needs_clflush_before is set and flushes out any written cachelines after | |
802 | * writing if needs_clflush is set. */ | |
3043c60c | 803 | static int |
d174bd64 DV |
804 | shmem_pwrite_fast(struct page *page, int shmem_page_offset, int page_length, |
805 | char __user *user_data, | |
806 | bool page_do_bit17_swizzling, | |
807 | bool needs_clflush_before, | |
808 | bool needs_clflush_after) | |
673a394b | 809 | { |
d174bd64 | 810 | char *vaddr; |
673a394b | 811 | int ret; |
3de09aa3 | 812 | |
e7e58eb5 | 813 | if (unlikely(page_do_bit17_swizzling)) |
d174bd64 | 814 | return -EINVAL; |
3de09aa3 | 815 | |
d174bd64 DV |
816 | vaddr = kmap_atomic(page); |
817 | if (needs_clflush_before) | |
818 | drm_clflush_virt_range(vaddr + shmem_page_offset, | |
819 | page_length); | |
c2831a94 CW |
820 | ret = __copy_from_user_inatomic(vaddr + shmem_page_offset, |
821 | user_data, page_length); | |
d174bd64 DV |
822 | if (needs_clflush_after) |
823 | drm_clflush_virt_range(vaddr + shmem_page_offset, | |
824 | page_length); | |
825 | kunmap_atomic(vaddr); | |
3de09aa3 | 826 | |
755d2218 | 827 | return ret ? -EFAULT : 0; |
3de09aa3 EA |
828 | } |
829 | ||
d174bd64 DV |
830 | /* Only difference to the fast-path function is that this can handle bit17 |
831 | * and uses non-atomic copy and kmap functions. */ | |
3043c60c | 832 | static int |
d174bd64 DV |
833 | shmem_pwrite_slow(struct page *page, int shmem_page_offset, int page_length, |
834 | char __user *user_data, | |
835 | bool page_do_bit17_swizzling, | |
836 | bool needs_clflush_before, | |
837 | bool needs_clflush_after) | |
673a394b | 838 | { |
d174bd64 DV |
839 | char *vaddr; |
840 | int ret; | |
e5281ccd | 841 | |
d174bd64 | 842 | vaddr = kmap(page); |
e7e58eb5 | 843 | if (unlikely(needs_clflush_before || page_do_bit17_swizzling)) |
23c18c71 DV |
844 | shmem_clflush_swizzled_range(vaddr + shmem_page_offset, |
845 | page_length, | |
846 | page_do_bit17_swizzling); | |
d174bd64 DV |
847 | if (page_do_bit17_swizzling) |
848 | ret = __copy_from_user_swizzled(vaddr, shmem_page_offset, | |
e5281ccd CW |
849 | user_data, |
850 | page_length); | |
d174bd64 DV |
851 | else |
852 | ret = __copy_from_user(vaddr + shmem_page_offset, | |
853 | user_data, | |
854 | page_length); | |
855 | if (needs_clflush_after) | |
23c18c71 DV |
856 | shmem_clflush_swizzled_range(vaddr + shmem_page_offset, |
857 | page_length, | |
858 | page_do_bit17_swizzling); | |
d174bd64 | 859 | kunmap(page); |
40123c1f | 860 | |
755d2218 | 861 | return ret ? -EFAULT : 0; |
40123c1f EA |
862 | } |
863 | ||
40123c1f | 864 | static int |
e244a443 DV |
865 | i915_gem_shmem_pwrite(struct drm_device *dev, |
866 | struct drm_i915_gem_object *obj, | |
867 | struct drm_i915_gem_pwrite *args, | |
868 | struct drm_file *file) | |
40123c1f | 869 | { |
40123c1f | 870 | ssize_t remain; |
8c59967c DV |
871 | loff_t offset; |
872 | char __user *user_data; | |
eb2c0c81 | 873 | int shmem_page_offset, page_length, ret = 0; |
8c59967c | 874 | int obj_do_bit17_swizzling, page_do_bit17_swizzling; |
e244a443 | 875 | int hit_slowpath = 0; |
58642885 DV |
876 | int needs_clflush_after = 0; |
877 | int needs_clflush_before = 0; | |
67d5a50c | 878 | struct sg_page_iter sg_iter; |
40123c1f | 879 | |
2bb4629a | 880 | user_data = to_user_ptr(args->data_ptr); |
40123c1f EA |
881 | remain = args->size; |
882 | ||
8c59967c | 883 | obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj); |
40123c1f | 884 | |
58642885 DV |
885 | if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) { |
886 | /* If we're not in the cpu write domain, set ourself into the gtt | |
887 | * write domain and manually flush cachelines (if required). This | |
888 | * optimizes for the case when the gpu will use the data | |
889 | * right away and we therefore have to clflush anyway. */ | |
2c22569b | 890 | needs_clflush_after = cpu_write_needs_clflush(obj); |
23f54483 BW |
891 | ret = i915_gem_object_wait_rendering(obj, false); |
892 | if (ret) | |
893 | return ret; | |
c8725f3d CW |
894 | |
895 | i915_gem_object_retire(obj); | |
58642885 | 896 | } |
c76ce038 CW |
897 | /* Same trick applies to invalidate partially written cachelines read |
898 | * before writing. */ | |
899 | if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0) | |
900 | needs_clflush_before = | |
901 | !cpu_cache_is_coherent(dev, obj->cache_level); | |
58642885 | 902 | |
755d2218 CW |
903 | ret = i915_gem_object_get_pages(obj); |
904 | if (ret) | |
905 | return ret; | |
906 | ||
907 | i915_gem_object_pin_pages(obj); | |
908 | ||
673a394b | 909 | offset = args->offset; |
05394f39 | 910 | obj->dirty = 1; |
673a394b | 911 | |
67d5a50c ID |
912 | for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, |
913 | offset >> PAGE_SHIFT) { | |
2db76d7c | 914 | struct page *page = sg_page_iter_page(&sg_iter); |
58642885 | 915 | int partial_cacheline_write; |
e5281ccd | 916 | |
9da3da66 CW |
917 | if (remain <= 0) |
918 | break; | |
919 | ||
40123c1f EA |
920 | /* Operation in this page |
921 | * | |
40123c1f | 922 | * shmem_page_offset = offset within page in shmem file |
40123c1f EA |
923 | * page_length = bytes to copy for this page |
924 | */ | |
c8cbbb8b | 925 | shmem_page_offset = offset_in_page(offset); |
40123c1f EA |
926 | |
927 | page_length = remain; | |
928 | if ((shmem_page_offset + page_length) > PAGE_SIZE) | |
929 | page_length = PAGE_SIZE - shmem_page_offset; | |
40123c1f | 930 | |
58642885 DV |
931 | /* If we don't overwrite a cacheline completely we need to be |
932 | * careful to have up-to-date data by first clflushing. Don't | |
933 | * overcomplicate things and flush the entire patch. */ | |
934 | partial_cacheline_write = needs_clflush_before && | |
935 | ((shmem_page_offset | page_length) | |
936 | & (boot_cpu_data.x86_clflush_size - 1)); | |
937 | ||
8c59967c DV |
938 | page_do_bit17_swizzling = obj_do_bit17_swizzling && |
939 | (page_to_phys(page) & (1 << 17)) != 0; | |
940 | ||
d174bd64 DV |
941 | ret = shmem_pwrite_fast(page, shmem_page_offset, page_length, |
942 | user_data, page_do_bit17_swizzling, | |
943 | partial_cacheline_write, | |
944 | needs_clflush_after); | |
945 | if (ret == 0) | |
946 | goto next_page; | |
e244a443 DV |
947 | |
948 | hit_slowpath = 1; | |
e244a443 | 949 | mutex_unlock(&dev->struct_mutex); |
d174bd64 DV |
950 | ret = shmem_pwrite_slow(page, shmem_page_offset, page_length, |
951 | user_data, page_do_bit17_swizzling, | |
952 | partial_cacheline_write, | |
953 | needs_clflush_after); | |
40123c1f | 954 | |
e244a443 | 955 | mutex_lock(&dev->struct_mutex); |
755d2218 | 956 | |
755d2218 | 957 | if (ret) |
8c59967c | 958 | goto out; |
8c59967c | 959 | |
17793c9a | 960 | next_page: |
40123c1f | 961 | remain -= page_length; |
8c59967c | 962 | user_data += page_length; |
40123c1f | 963 | offset += page_length; |
673a394b EA |
964 | } |
965 | ||
fbd5a26d | 966 | out: |
755d2218 CW |
967 | i915_gem_object_unpin_pages(obj); |
968 | ||
e244a443 | 969 | if (hit_slowpath) { |
8dcf015e DV |
970 | /* |
971 | * Fixup: Flush cpu caches in case we didn't flush the dirty | |
972 | * cachelines in-line while writing and the object moved | |
973 | * out of the cpu write domain while we've dropped the lock. | |
974 | */ | |
975 | if (!needs_clflush_after && | |
976 | obj->base.write_domain != I915_GEM_DOMAIN_CPU) { | |
000433b6 CW |
977 | if (i915_gem_clflush_object(obj, obj->pin_display)) |
978 | i915_gem_chipset_flush(dev); | |
e244a443 | 979 | } |
8c59967c | 980 | } |
673a394b | 981 | |
58642885 | 982 | if (needs_clflush_after) |
e76e9aeb | 983 | i915_gem_chipset_flush(dev); |
58642885 | 984 | |
40123c1f | 985 | return ret; |
673a394b EA |
986 | } |
987 | ||
988 | /** | |
989 | * Writes data to the object referenced by handle. | |
990 | * | |
991 | * On error, the contents of the buffer that were to be modified are undefined. | |
992 | */ | |
993 | int | |
994 | i915_gem_pwrite_ioctl(struct drm_device *dev, void *data, | |
fbd5a26d | 995 | struct drm_file *file) |
673a394b EA |
996 | { |
997 | struct drm_i915_gem_pwrite *args = data; | |
05394f39 | 998 | struct drm_i915_gem_object *obj; |
51311d0a CW |
999 | int ret; |
1000 | ||
1001 | if (args->size == 0) | |
1002 | return 0; | |
1003 | ||
1004 | if (!access_ok(VERIFY_READ, | |
2bb4629a | 1005 | to_user_ptr(args->data_ptr), |
51311d0a CW |
1006 | args->size)) |
1007 | return -EFAULT; | |
1008 | ||
d330a953 | 1009 | if (likely(!i915.prefault_disable)) { |
0b74b508 XZ |
1010 | ret = fault_in_multipages_readable(to_user_ptr(args->data_ptr), |
1011 | args->size); | |
1012 | if (ret) | |
1013 | return -EFAULT; | |
1014 | } | |
673a394b | 1015 | |
fbd5a26d | 1016 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 1017 | if (ret) |
fbd5a26d | 1018 | return ret; |
1d7cfea1 | 1019 | |
05394f39 | 1020 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 1021 | if (&obj->base == NULL) { |
1d7cfea1 CW |
1022 | ret = -ENOENT; |
1023 | goto unlock; | |
fbd5a26d | 1024 | } |
673a394b | 1025 | |
7dcd2499 | 1026 | /* Bounds check destination. */ |
05394f39 CW |
1027 | if (args->offset > obj->base.size || |
1028 | args->size > obj->base.size - args->offset) { | |
ce9d419d | 1029 | ret = -EINVAL; |
35b62a89 | 1030 | goto out; |
ce9d419d CW |
1031 | } |
1032 | ||
1286ff73 DV |
1033 | /* prime objects have no backing filp to GEM pread/pwrite |
1034 | * pages from. | |
1035 | */ | |
1036 | if (!obj->base.filp) { | |
1037 | ret = -EINVAL; | |
1038 | goto out; | |
1039 | } | |
1040 | ||
db53a302 CW |
1041 | trace_i915_gem_object_pwrite(obj, args->offset, args->size); |
1042 | ||
935aaa69 | 1043 | ret = -EFAULT; |
673a394b EA |
1044 | /* We can only do the GTT pwrite on untiled buffers, as otherwise |
1045 | * it would end up going through the fenced access, and we'll get | |
1046 | * different detiling behavior between reading and writing. | |
1047 | * pread/pwrite currently are reading and writing from the CPU | |
1048 | * perspective, requiring manual detiling by the client. | |
1049 | */ | |
00731155 CW |
1050 | if (obj->phys_handle) { |
1051 | ret = i915_gem_phys_pwrite(obj, args, file); | |
5c0480f2 DV |
1052 | goto out; |
1053 | } | |
1054 | ||
2c22569b CW |
1055 | if (obj->tiling_mode == I915_TILING_NONE && |
1056 | obj->base.write_domain != I915_GEM_DOMAIN_CPU && | |
1057 | cpu_write_needs_clflush(obj)) { | |
fbd5a26d | 1058 | ret = i915_gem_gtt_pwrite_fast(dev, obj, args, file); |
935aaa69 DV |
1059 | /* Note that the gtt paths might fail with non-page-backed user |
1060 | * pointers (e.g. gtt mappings when moving data between | |
1061 | * textures). Fallback to the shmem path in that case. */ | |
fbd5a26d | 1062 | } |
673a394b | 1063 | |
86a1ee26 | 1064 | if (ret == -EFAULT || ret == -ENOSPC) |
935aaa69 | 1065 | ret = i915_gem_shmem_pwrite(dev, obj, args, file); |
5c0480f2 | 1066 | |
35b62a89 | 1067 | out: |
05394f39 | 1068 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 1069 | unlock: |
fbd5a26d | 1070 | mutex_unlock(&dev->struct_mutex); |
673a394b EA |
1071 | return ret; |
1072 | } | |
1073 | ||
b361237b | 1074 | int |
33196ded | 1075 | i915_gem_check_wedge(struct i915_gpu_error *error, |
b361237b CW |
1076 | bool interruptible) |
1077 | { | |
1f83fee0 | 1078 | if (i915_reset_in_progress(error)) { |
b361237b CW |
1079 | /* Non-interruptible callers can't handle -EAGAIN, hence return |
1080 | * -EIO unconditionally for these. */ | |
1081 | if (!interruptible) | |
1082 | return -EIO; | |
1083 | ||
1f83fee0 DV |
1084 | /* Recovery complete, but the reset failed ... */ |
1085 | if (i915_terminally_wedged(error)) | |
b361237b CW |
1086 | return -EIO; |
1087 | ||
1088 | return -EAGAIN; | |
1089 | } | |
1090 | ||
1091 | return 0; | |
1092 | } | |
1093 | ||
1094 | /* | |
1095 | * Compare seqno against outstanding lazy request. Emit a request if they are | |
1096 | * equal. | |
1097 | */ | |
1098 | static int | |
a4872ba6 | 1099 | i915_gem_check_olr(struct intel_engine_cs *ring, u32 seqno) |
b361237b CW |
1100 | { |
1101 | int ret; | |
1102 | ||
1103 | BUG_ON(!mutex_is_locked(&ring->dev->struct_mutex)); | |
1104 | ||
1105 | ret = 0; | |
1823521d | 1106 | if (seqno == ring->outstanding_lazy_seqno) |
0025c077 | 1107 | ret = i915_add_request(ring, NULL); |
b361237b CW |
1108 | |
1109 | return ret; | |
1110 | } | |
1111 | ||
094f9a54 CW |
1112 | static void fake_irq(unsigned long data) |
1113 | { | |
1114 | wake_up_process((struct task_struct *)data); | |
1115 | } | |
1116 | ||
1117 | static bool missed_irq(struct drm_i915_private *dev_priv, | |
a4872ba6 | 1118 | struct intel_engine_cs *ring) |
094f9a54 CW |
1119 | { |
1120 | return test_bit(ring->id, &dev_priv->gpu_error.missed_irq_rings); | |
1121 | } | |
1122 | ||
b29c19b6 CW |
1123 | static bool can_wait_boost(struct drm_i915_file_private *file_priv) |
1124 | { | |
1125 | if (file_priv == NULL) | |
1126 | return true; | |
1127 | ||
1128 | return !atomic_xchg(&file_priv->rps_wait_boost, true); | |
1129 | } | |
1130 | ||
b361237b CW |
1131 | /** |
1132 | * __wait_seqno - wait until execution of seqno has finished | |
1133 | * @ring: the ring expected to report seqno | |
1134 | * @seqno: duh! | |
f69061be | 1135 | * @reset_counter: reset sequence associated with the given seqno |
b361237b CW |
1136 | * @interruptible: do an interruptible wait (normally yes) |
1137 | * @timeout: in - how long to wait (NULL forever); out - how much time remaining | |
1138 | * | |
f69061be DV |
1139 | * Note: It is of utmost importance that the passed in seqno and reset_counter |
1140 | * values have been read by the caller in an smp safe manner. Where read-side | |
1141 | * locks are involved, it is sufficient to read the reset_counter before | |
1142 | * unlocking the lock that protects the seqno. For lockless tricks, the | |
1143 | * reset_counter _must_ be read before, and an appropriate smp_rmb must be | |
1144 | * inserted. | |
1145 | * | |
b361237b CW |
1146 | * Returns 0 if the seqno was found within the alloted time. Else returns the |
1147 | * errno with remaining time filled in timeout argument. | |
1148 | */ | |
a4872ba6 | 1149 | static int __wait_seqno(struct intel_engine_cs *ring, u32 seqno, |
f69061be | 1150 | unsigned reset_counter, |
b29c19b6 CW |
1151 | bool interruptible, |
1152 | struct timespec *timeout, | |
1153 | struct drm_i915_file_private *file_priv) | |
b361237b | 1154 | { |
3d13ef2e | 1155 | struct drm_device *dev = ring->dev; |
3e31c6c0 | 1156 | struct drm_i915_private *dev_priv = dev->dev_private; |
168c3f21 MK |
1157 | const bool irq_test_in_progress = |
1158 | ACCESS_ONCE(dev_priv->gpu_error.test_irq_rings) & intel_ring_flag(ring); | |
094f9a54 CW |
1159 | struct timespec before, now; |
1160 | DEFINE_WAIT(wait); | |
47e9766d | 1161 | unsigned long timeout_expire; |
b361237b CW |
1162 | int ret; |
1163 | ||
5d584b2e | 1164 | WARN(dev_priv->pm.irqs_disabled, "IRQs disabled\n"); |
c67a470b | 1165 | |
b361237b CW |
1166 | if (i915_seqno_passed(ring->get_seqno(ring, true), seqno)) |
1167 | return 0; | |
1168 | ||
47e9766d | 1169 | timeout_expire = timeout ? jiffies + timespec_to_jiffies_timeout(timeout) : 0; |
b361237b | 1170 | |
3d13ef2e | 1171 | if (INTEL_INFO(dev)->gen >= 6 && can_wait_boost(file_priv)) { |
b29c19b6 CW |
1172 | gen6_rps_boost(dev_priv); |
1173 | if (file_priv) | |
1174 | mod_delayed_work(dev_priv->wq, | |
1175 | &file_priv->mm.idle_work, | |
1176 | msecs_to_jiffies(100)); | |
1177 | } | |
1178 | ||
168c3f21 | 1179 | if (!irq_test_in_progress && WARN_ON(!ring->irq_get(ring))) |
b361237b CW |
1180 | return -ENODEV; |
1181 | ||
094f9a54 CW |
1182 | /* Record current time in case interrupted by signal, or wedged */ |
1183 | trace_i915_gem_request_wait_begin(ring, seqno); | |
b361237b | 1184 | getrawmonotonic(&before); |
094f9a54 CW |
1185 | for (;;) { |
1186 | struct timer_list timer; | |
b361237b | 1187 | |
094f9a54 CW |
1188 | prepare_to_wait(&ring->irq_queue, &wait, |
1189 | interruptible ? TASK_INTERRUPTIBLE : TASK_UNINTERRUPTIBLE); | |
b361237b | 1190 | |
f69061be DV |
1191 | /* We need to check whether any gpu reset happened in between |
1192 | * the caller grabbing the seqno and now ... */ | |
094f9a54 CW |
1193 | if (reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter)) { |
1194 | /* ... but upgrade the -EAGAIN to an -EIO if the gpu | |
1195 | * is truely gone. */ | |
1196 | ret = i915_gem_check_wedge(&dev_priv->gpu_error, interruptible); | |
1197 | if (ret == 0) | |
1198 | ret = -EAGAIN; | |
1199 | break; | |
1200 | } | |
f69061be | 1201 | |
094f9a54 CW |
1202 | if (i915_seqno_passed(ring->get_seqno(ring, false), seqno)) { |
1203 | ret = 0; | |
1204 | break; | |
1205 | } | |
b361237b | 1206 | |
094f9a54 CW |
1207 | if (interruptible && signal_pending(current)) { |
1208 | ret = -ERESTARTSYS; | |
1209 | break; | |
1210 | } | |
1211 | ||
47e9766d | 1212 | if (timeout && time_after_eq(jiffies, timeout_expire)) { |
094f9a54 CW |
1213 | ret = -ETIME; |
1214 | break; | |
1215 | } | |
1216 | ||
1217 | timer.function = NULL; | |
1218 | if (timeout || missed_irq(dev_priv, ring)) { | |
47e9766d MK |
1219 | unsigned long expire; |
1220 | ||
094f9a54 | 1221 | setup_timer_on_stack(&timer, fake_irq, (unsigned long)current); |
47e9766d | 1222 | expire = missed_irq(dev_priv, ring) ? jiffies + 1 : timeout_expire; |
094f9a54 CW |
1223 | mod_timer(&timer, expire); |
1224 | } | |
1225 | ||
5035c275 | 1226 | io_schedule(); |
094f9a54 | 1227 | |
094f9a54 CW |
1228 | if (timer.function) { |
1229 | del_singleshot_timer_sync(&timer); | |
1230 | destroy_timer_on_stack(&timer); | |
1231 | } | |
1232 | } | |
b361237b | 1233 | getrawmonotonic(&now); |
094f9a54 | 1234 | trace_i915_gem_request_wait_end(ring, seqno); |
b361237b | 1235 | |
168c3f21 MK |
1236 | if (!irq_test_in_progress) |
1237 | ring->irq_put(ring); | |
094f9a54 CW |
1238 | |
1239 | finish_wait(&ring->irq_queue, &wait); | |
b361237b CW |
1240 | |
1241 | if (timeout) { | |
1242 | struct timespec sleep_time = timespec_sub(now, before); | |
1243 | *timeout = timespec_sub(*timeout, sleep_time); | |
4f42f4ef CW |
1244 | if (!timespec_valid(timeout)) /* i.e. negative time remains */ |
1245 | set_normalized_timespec(timeout, 0, 0); | |
b361237b CW |
1246 | } |
1247 | ||
094f9a54 | 1248 | return ret; |
b361237b CW |
1249 | } |
1250 | ||
1251 | /** | |
1252 | * Waits for a sequence number to be signaled, and cleans up the | |
1253 | * request and object lists appropriately for that event. | |
1254 | */ | |
1255 | int | |
a4872ba6 | 1256 | i915_wait_seqno(struct intel_engine_cs *ring, uint32_t seqno) |
b361237b CW |
1257 | { |
1258 | struct drm_device *dev = ring->dev; | |
1259 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1260 | bool interruptible = dev_priv->mm.interruptible; | |
1261 | int ret; | |
1262 | ||
1263 | BUG_ON(!mutex_is_locked(&dev->struct_mutex)); | |
1264 | BUG_ON(seqno == 0); | |
1265 | ||
33196ded | 1266 | ret = i915_gem_check_wedge(&dev_priv->gpu_error, interruptible); |
b361237b CW |
1267 | if (ret) |
1268 | return ret; | |
1269 | ||
1270 | ret = i915_gem_check_olr(ring, seqno); | |
1271 | if (ret) | |
1272 | return ret; | |
1273 | ||
f69061be DV |
1274 | return __wait_seqno(ring, seqno, |
1275 | atomic_read(&dev_priv->gpu_error.reset_counter), | |
b29c19b6 | 1276 | interruptible, NULL, NULL); |
b361237b CW |
1277 | } |
1278 | ||
d26e3af8 CW |
1279 | static int |
1280 | i915_gem_object_wait_rendering__tail(struct drm_i915_gem_object *obj, | |
a4872ba6 | 1281 | struct intel_engine_cs *ring) |
d26e3af8 | 1282 | { |
c8725f3d CW |
1283 | if (!obj->active) |
1284 | return 0; | |
d26e3af8 CW |
1285 | |
1286 | /* Manually manage the write flush as we may have not yet | |
1287 | * retired the buffer. | |
1288 | * | |
1289 | * Note that the last_write_seqno is always the earlier of | |
1290 | * the two (read/write) seqno, so if we haved successfully waited, | |
1291 | * we know we have passed the last write. | |
1292 | */ | |
1293 | obj->last_write_seqno = 0; | |
d26e3af8 CW |
1294 | |
1295 | return 0; | |
1296 | } | |
1297 | ||
b361237b CW |
1298 | /** |
1299 | * Ensures that all rendering to the object has completed and the object is | |
1300 | * safe to unbind from the GTT or access from the CPU. | |
1301 | */ | |
1302 | static __must_check int | |
1303 | i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj, | |
1304 | bool readonly) | |
1305 | { | |
a4872ba6 | 1306 | struct intel_engine_cs *ring = obj->ring; |
b361237b CW |
1307 | u32 seqno; |
1308 | int ret; | |
1309 | ||
1310 | seqno = readonly ? obj->last_write_seqno : obj->last_read_seqno; | |
1311 | if (seqno == 0) | |
1312 | return 0; | |
1313 | ||
1314 | ret = i915_wait_seqno(ring, seqno); | |
1315 | if (ret) | |
1316 | return ret; | |
1317 | ||
d26e3af8 | 1318 | return i915_gem_object_wait_rendering__tail(obj, ring); |
b361237b CW |
1319 | } |
1320 | ||
3236f57a CW |
1321 | /* A nonblocking variant of the above wait. This is a highly dangerous routine |
1322 | * as the object state may change during this call. | |
1323 | */ | |
1324 | static __must_check int | |
1325 | i915_gem_object_wait_rendering__nonblocking(struct drm_i915_gem_object *obj, | |
6e4930f6 | 1326 | struct drm_i915_file_private *file_priv, |
3236f57a CW |
1327 | bool readonly) |
1328 | { | |
1329 | struct drm_device *dev = obj->base.dev; | |
1330 | struct drm_i915_private *dev_priv = dev->dev_private; | |
a4872ba6 | 1331 | struct intel_engine_cs *ring = obj->ring; |
f69061be | 1332 | unsigned reset_counter; |
3236f57a CW |
1333 | u32 seqno; |
1334 | int ret; | |
1335 | ||
1336 | BUG_ON(!mutex_is_locked(&dev->struct_mutex)); | |
1337 | BUG_ON(!dev_priv->mm.interruptible); | |
1338 | ||
1339 | seqno = readonly ? obj->last_write_seqno : obj->last_read_seqno; | |
1340 | if (seqno == 0) | |
1341 | return 0; | |
1342 | ||
33196ded | 1343 | ret = i915_gem_check_wedge(&dev_priv->gpu_error, true); |
3236f57a CW |
1344 | if (ret) |
1345 | return ret; | |
1346 | ||
1347 | ret = i915_gem_check_olr(ring, seqno); | |
1348 | if (ret) | |
1349 | return ret; | |
1350 | ||
f69061be | 1351 | reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter); |
3236f57a | 1352 | mutex_unlock(&dev->struct_mutex); |
6e4930f6 | 1353 | ret = __wait_seqno(ring, seqno, reset_counter, true, NULL, file_priv); |
3236f57a | 1354 | mutex_lock(&dev->struct_mutex); |
d26e3af8 CW |
1355 | if (ret) |
1356 | return ret; | |
3236f57a | 1357 | |
d26e3af8 | 1358 | return i915_gem_object_wait_rendering__tail(obj, ring); |
3236f57a CW |
1359 | } |
1360 | ||
673a394b | 1361 | /** |
2ef7eeaa EA |
1362 | * Called when user space prepares to use an object with the CPU, either |
1363 | * through the mmap ioctl's mapping or a GTT mapping. | |
673a394b EA |
1364 | */ |
1365 | int | |
1366 | i915_gem_set_domain_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 1367 | struct drm_file *file) |
673a394b EA |
1368 | { |
1369 | struct drm_i915_gem_set_domain *args = data; | |
05394f39 | 1370 | struct drm_i915_gem_object *obj; |
2ef7eeaa EA |
1371 | uint32_t read_domains = args->read_domains; |
1372 | uint32_t write_domain = args->write_domain; | |
673a394b EA |
1373 | int ret; |
1374 | ||
2ef7eeaa | 1375 | /* Only handle setting domains to types used by the CPU. */ |
21d509e3 | 1376 | if (write_domain & I915_GEM_GPU_DOMAINS) |
2ef7eeaa EA |
1377 | return -EINVAL; |
1378 | ||
21d509e3 | 1379 | if (read_domains & I915_GEM_GPU_DOMAINS) |
2ef7eeaa EA |
1380 | return -EINVAL; |
1381 | ||
1382 | /* Having something in the write domain implies it's in the read | |
1383 | * domain, and only that read domain. Enforce that in the request. | |
1384 | */ | |
1385 | if (write_domain != 0 && read_domains != write_domain) | |
1386 | return -EINVAL; | |
1387 | ||
76c1dec1 | 1388 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 1389 | if (ret) |
76c1dec1 | 1390 | return ret; |
1d7cfea1 | 1391 | |
05394f39 | 1392 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 1393 | if (&obj->base == NULL) { |
1d7cfea1 CW |
1394 | ret = -ENOENT; |
1395 | goto unlock; | |
76c1dec1 | 1396 | } |
673a394b | 1397 | |
3236f57a CW |
1398 | /* Try to flush the object off the GPU without holding the lock. |
1399 | * We will repeat the flush holding the lock in the normal manner | |
1400 | * to catch cases where we are gazumped. | |
1401 | */ | |
6e4930f6 CW |
1402 | ret = i915_gem_object_wait_rendering__nonblocking(obj, |
1403 | file->driver_priv, | |
1404 | !write_domain); | |
3236f57a CW |
1405 | if (ret) |
1406 | goto unref; | |
1407 | ||
2ef7eeaa EA |
1408 | if (read_domains & I915_GEM_DOMAIN_GTT) { |
1409 | ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0); | |
02354392 EA |
1410 | |
1411 | /* Silently promote "you're not bound, there was nothing to do" | |
1412 | * to success, since the client was just asking us to | |
1413 | * make sure everything was done. | |
1414 | */ | |
1415 | if (ret == -EINVAL) | |
1416 | ret = 0; | |
2ef7eeaa | 1417 | } else { |
e47c68e9 | 1418 | ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0); |
2ef7eeaa EA |
1419 | } |
1420 | ||
3236f57a | 1421 | unref: |
05394f39 | 1422 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 1423 | unlock: |
673a394b EA |
1424 | mutex_unlock(&dev->struct_mutex); |
1425 | return ret; | |
1426 | } | |
1427 | ||
1428 | /** | |
1429 | * Called when user space has done writes to this buffer | |
1430 | */ | |
1431 | int | |
1432 | i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 1433 | struct drm_file *file) |
673a394b EA |
1434 | { |
1435 | struct drm_i915_gem_sw_finish *args = data; | |
05394f39 | 1436 | struct drm_i915_gem_object *obj; |
673a394b EA |
1437 | int ret = 0; |
1438 | ||
76c1dec1 | 1439 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 1440 | if (ret) |
76c1dec1 | 1441 | return ret; |
1d7cfea1 | 1442 | |
05394f39 | 1443 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 1444 | if (&obj->base == NULL) { |
1d7cfea1 CW |
1445 | ret = -ENOENT; |
1446 | goto unlock; | |
673a394b EA |
1447 | } |
1448 | ||
673a394b | 1449 | /* Pinned buffers may be scanout, so flush the cache */ |
2c22569b CW |
1450 | if (obj->pin_display) |
1451 | i915_gem_object_flush_cpu_write_domain(obj, true); | |
e47c68e9 | 1452 | |
05394f39 | 1453 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 1454 | unlock: |
673a394b EA |
1455 | mutex_unlock(&dev->struct_mutex); |
1456 | return ret; | |
1457 | } | |
1458 | ||
1459 | /** | |
1460 | * Maps the contents of an object, returning the address it is mapped | |
1461 | * into. | |
1462 | * | |
1463 | * While the mapping holds a reference on the contents of the object, it doesn't | |
1464 | * imply a ref on the object itself. | |
1465 | */ | |
1466 | int | |
1467 | i915_gem_mmap_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 1468 | struct drm_file *file) |
673a394b EA |
1469 | { |
1470 | struct drm_i915_gem_mmap *args = data; | |
1471 | struct drm_gem_object *obj; | |
673a394b EA |
1472 | unsigned long addr; |
1473 | ||
05394f39 | 1474 | obj = drm_gem_object_lookup(dev, file, args->handle); |
673a394b | 1475 | if (obj == NULL) |
bf79cb91 | 1476 | return -ENOENT; |
673a394b | 1477 | |
1286ff73 DV |
1478 | /* prime objects have no backing filp to GEM mmap |
1479 | * pages from. | |
1480 | */ | |
1481 | if (!obj->filp) { | |
1482 | drm_gem_object_unreference_unlocked(obj); | |
1483 | return -EINVAL; | |
1484 | } | |
1485 | ||
6be5ceb0 | 1486 | addr = vm_mmap(obj->filp, 0, args->size, |
673a394b EA |
1487 | PROT_READ | PROT_WRITE, MAP_SHARED, |
1488 | args->offset); | |
bc9025bd | 1489 | drm_gem_object_unreference_unlocked(obj); |
673a394b EA |
1490 | if (IS_ERR((void *)addr)) |
1491 | return addr; | |
1492 | ||
1493 | args->addr_ptr = (uint64_t) addr; | |
1494 | ||
1495 | return 0; | |
1496 | } | |
1497 | ||
de151cf6 JB |
1498 | /** |
1499 | * i915_gem_fault - fault a page into the GTT | |
1500 | * vma: VMA in question | |
1501 | * vmf: fault info | |
1502 | * | |
1503 | * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped | |
1504 | * from userspace. The fault handler takes care of binding the object to | |
1505 | * the GTT (if needed), allocating and programming a fence register (again, | |
1506 | * only if needed based on whether the old reg is still valid or the object | |
1507 | * is tiled) and inserting a new PTE into the faulting process. | |
1508 | * | |
1509 | * Note that the faulting process may involve evicting existing objects | |
1510 | * from the GTT and/or fence registers to make room. So performance may | |
1511 | * suffer if the GTT working set is large or there are few fence registers | |
1512 | * left. | |
1513 | */ | |
1514 | int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf) | |
1515 | { | |
05394f39 CW |
1516 | struct drm_i915_gem_object *obj = to_intel_bo(vma->vm_private_data); |
1517 | struct drm_device *dev = obj->base.dev; | |
3e31c6c0 | 1518 | struct drm_i915_private *dev_priv = dev->dev_private; |
de151cf6 JB |
1519 | pgoff_t page_offset; |
1520 | unsigned long pfn; | |
1521 | int ret = 0; | |
0f973f27 | 1522 | bool write = !!(vmf->flags & FAULT_FLAG_WRITE); |
de151cf6 | 1523 | |
f65c9168 PZ |
1524 | intel_runtime_pm_get(dev_priv); |
1525 | ||
de151cf6 JB |
1526 | /* We don't use vmf->pgoff since that has the fake offset */ |
1527 | page_offset = ((unsigned long)vmf->virtual_address - vma->vm_start) >> | |
1528 | PAGE_SHIFT; | |
1529 | ||
d9bc7e9f CW |
1530 | ret = i915_mutex_lock_interruptible(dev); |
1531 | if (ret) | |
1532 | goto out; | |
a00b10c3 | 1533 | |
db53a302 CW |
1534 | trace_i915_gem_object_fault(obj, page_offset, true, write); |
1535 | ||
6e4930f6 CW |
1536 | /* Try to flush the object off the GPU first without holding the lock. |
1537 | * Upon reacquiring the lock, we will perform our sanity checks and then | |
1538 | * repeat the flush holding the lock in the normal manner to catch cases | |
1539 | * where we are gazumped. | |
1540 | */ | |
1541 | ret = i915_gem_object_wait_rendering__nonblocking(obj, NULL, !write); | |
1542 | if (ret) | |
1543 | goto unlock; | |
1544 | ||
eb119bd6 CW |
1545 | /* Access to snoopable pages through the GTT is incoherent. */ |
1546 | if (obj->cache_level != I915_CACHE_NONE && !HAS_LLC(dev)) { | |
ddeff6ee | 1547 | ret = -EFAULT; |
eb119bd6 CW |
1548 | goto unlock; |
1549 | } | |
1550 | ||
d9bc7e9f | 1551 | /* Now bind it into the GTT if needed */ |
1ec9e26d | 1552 | ret = i915_gem_obj_ggtt_pin(obj, 0, PIN_MAPPABLE); |
c9839303 CW |
1553 | if (ret) |
1554 | goto unlock; | |
4a684a41 | 1555 | |
c9839303 CW |
1556 | ret = i915_gem_object_set_to_gtt_domain(obj, write); |
1557 | if (ret) | |
1558 | goto unpin; | |
74898d7e | 1559 | |
06d98131 | 1560 | ret = i915_gem_object_get_fence(obj); |
d9e86c0e | 1561 | if (ret) |
c9839303 | 1562 | goto unpin; |
7d1c4804 | 1563 | |
6299f992 CW |
1564 | obj->fault_mappable = true; |
1565 | ||
f343c5f6 BW |
1566 | pfn = dev_priv->gtt.mappable_base + i915_gem_obj_ggtt_offset(obj); |
1567 | pfn >>= PAGE_SHIFT; | |
1568 | pfn += page_offset; | |
de151cf6 JB |
1569 | |
1570 | /* Finally, remap it using the new GTT offset */ | |
1571 | ret = vm_insert_pfn(vma, (unsigned long)vmf->virtual_address, pfn); | |
c9839303 | 1572 | unpin: |
d7f46fc4 | 1573 | i915_gem_object_ggtt_unpin(obj); |
c715089f | 1574 | unlock: |
de151cf6 | 1575 | mutex_unlock(&dev->struct_mutex); |
d9bc7e9f | 1576 | out: |
de151cf6 | 1577 | switch (ret) { |
d9bc7e9f | 1578 | case -EIO: |
a9340cca DV |
1579 | /* If this -EIO is due to a gpu hang, give the reset code a |
1580 | * chance to clean up the mess. Otherwise return the proper | |
1581 | * SIGBUS. */ | |
f65c9168 PZ |
1582 | if (i915_terminally_wedged(&dev_priv->gpu_error)) { |
1583 | ret = VM_FAULT_SIGBUS; | |
1584 | break; | |
1585 | } | |
045e769a | 1586 | case -EAGAIN: |
571c608d DV |
1587 | /* |
1588 | * EAGAIN means the gpu is hung and we'll wait for the error | |
1589 | * handler to reset everything when re-faulting in | |
1590 | * i915_mutex_lock_interruptible. | |
d9bc7e9f | 1591 | */ |
c715089f CW |
1592 | case 0: |
1593 | case -ERESTARTSYS: | |
bed636ab | 1594 | case -EINTR: |
e79e0fe3 DR |
1595 | case -EBUSY: |
1596 | /* | |
1597 | * EBUSY is ok: this just means that another thread | |
1598 | * already did the job. | |
1599 | */ | |
f65c9168 PZ |
1600 | ret = VM_FAULT_NOPAGE; |
1601 | break; | |
de151cf6 | 1602 | case -ENOMEM: |
f65c9168 PZ |
1603 | ret = VM_FAULT_OOM; |
1604 | break; | |
a7c2e1aa | 1605 | case -ENOSPC: |
45d67817 | 1606 | case -EFAULT: |
f65c9168 PZ |
1607 | ret = VM_FAULT_SIGBUS; |
1608 | break; | |
de151cf6 | 1609 | default: |
a7c2e1aa | 1610 | WARN_ONCE(ret, "unhandled error in i915_gem_fault: %i\n", ret); |
f65c9168 PZ |
1611 | ret = VM_FAULT_SIGBUS; |
1612 | break; | |
de151cf6 | 1613 | } |
f65c9168 PZ |
1614 | |
1615 | intel_runtime_pm_put(dev_priv); | |
1616 | return ret; | |
de151cf6 JB |
1617 | } |
1618 | ||
48018a57 PZ |
1619 | void i915_gem_release_all_mmaps(struct drm_i915_private *dev_priv) |
1620 | { | |
1621 | struct i915_vma *vma; | |
1622 | ||
1623 | /* | |
1624 | * Only the global gtt is relevant for gtt memory mappings, so restrict | |
1625 | * list traversal to objects bound into the global address space. Note | |
1626 | * that the active list should be empty, but better safe than sorry. | |
1627 | */ | |
1628 | WARN_ON(!list_empty(&dev_priv->gtt.base.active_list)); | |
1629 | list_for_each_entry(vma, &dev_priv->gtt.base.active_list, mm_list) | |
1630 | i915_gem_release_mmap(vma->obj); | |
1631 | list_for_each_entry(vma, &dev_priv->gtt.base.inactive_list, mm_list) | |
1632 | i915_gem_release_mmap(vma->obj); | |
1633 | } | |
1634 | ||
901782b2 CW |
1635 | /** |
1636 | * i915_gem_release_mmap - remove physical page mappings | |
1637 | * @obj: obj in question | |
1638 | * | |
af901ca1 | 1639 | * Preserve the reservation of the mmapping with the DRM core code, but |
901782b2 CW |
1640 | * relinquish ownership of the pages back to the system. |
1641 | * | |
1642 | * It is vital that we remove the page mapping if we have mapped a tiled | |
1643 | * object through the GTT and then lose the fence register due to | |
1644 | * resource pressure. Similarly if the object has been moved out of the | |
1645 | * aperture, than pages mapped into userspace must be revoked. Removing the | |
1646 | * mapping will then trigger a page fault on the next user access, allowing | |
1647 | * fixup by i915_gem_fault(). | |
1648 | */ | |
d05ca301 | 1649 | void |
05394f39 | 1650 | i915_gem_release_mmap(struct drm_i915_gem_object *obj) |
901782b2 | 1651 | { |
6299f992 CW |
1652 | if (!obj->fault_mappable) |
1653 | return; | |
901782b2 | 1654 | |
6796cb16 DH |
1655 | drm_vma_node_unmap(&obj->base.vma_node, |
1656 | obj->base.dev->anon_inode->i_mapping); | |
6299f992 | 1657 | obj->fault_mappable = false; |
901782b2 CW |
1658 | } |
1659 | ||
0fa87796 | 1660 | uint32_t |
e28f8711 | 1661 | i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode) |
92b88aeb | 1662 | { |
e28f8711 | 1663 | uint32_t gtt_size; |
92b88aeb CW |
1664 | |
1665 | if (INTEL_INFO(dev)->gen >= 4 || | |
e28f8711 CW |
1666 | tiling_mode == I915_TILING_NONE) |
1667 | return size; | |
92b88aeb CW |
1668 | |
1669 | /* Previous chips need a power-of-two fence region when tiling */ | |
1670 | if (INTEL_INFO(dev)->gen == 3) | |
e28f8711 | 1671 | gtt_size = 1024*1024; |
92b88aeb | 1672 | else |
e28f8711 | 1673 | gtt_size = 512*1024; |
92b88aeb | 1674 | |
e28f8711 CW |
1675 | while (gtt_size < size) |
1676 | gtt_size <<= 1; | |
92b88aeb | 1677 | |
e28f8711 | 1678 | return gtt_size; |
92b88aeb CW |
1679 | } |
1680 | ||
de151cf6 JB |
1681 | /** |
1682 | * i915_gem_get_gtt_alignment - return required GTT alignment for an object | |
1683 | * @obj: object to check | |
1684 | * | |
1685 | * Return the required GTT alignment for an object, taking into account | |
5e783301 | 1686 | * potential fence register mapping. |
de151cf6 | 1687 | */ |
d865110c ID |
1688 | uint32_t |
1689 | i915_gem_get_gtt_alignment(struct drm_device *dev, uint32_t size, | |
1690 | int tiling_mode, bool fenced) | |
de151cf6 | 1691 | { |
de151cf6 JB |
1692 | /* |
1693 | * Minimum alignment is 4k (GTT page size), but might be greater | |
1694 | * if a fence register is needed for the object. | |
1695 | */ | |
d865110c | 1696 | if (INTEL_INFO(dev)->gen >= 4 || (!fenced && IS_G33(dev)) || |
e28f8711 | 1697 | tiling_mode == I915_TILING_NONE) |
de151cf6 JB |
1698 | return 4096; |
1699 | ||
a00b10c3 CW |
1700 | /* |
1701 | * Previous chips need to be aligned to the size of the smallest | |
1702 | * fence register that can contain the object. | |
1703 | */ | |
e28f8711 | 1704 | return i915_gem_get_gtt_size(dev, size, tiling_mode); |
a00b10c3 CW |
1705 | } |
1706 | ||
d8cb5086 CW |
1707 | static int i915_gem_object_create_mmap_offset(struct drm_i915_gem_object *obj) |
1708 | { | |
1709 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; | |
1710 | int ret; | |
1711 | ||
0de23977 | 1712 | if (drm_vma_node_has_offset(&obj->base.vma_node)) |
d8cb5086 CW |
1713 | return 0; |
1714 | ||
da494d7c DV |
1715 | dev_priv->mm.shrinker_no_lock_stealing = true; |
1716 | ||
d8cb5086 CW |
1717 | ret = drm_gem_create_mmap_offset(&obj->base); |
1718 | if (ret != -ENOSPC) | |
da494d7c | 1719 | goto out; |
d8cb5086 CW |
1720 | |
1721 | /* Badly fragmented mmap space? The only way we can recover | |
1722 | * space is by destroying unwanted objects. We can't randomly release | |
1723 | * mmap_offsets as userspace expects them to be persistent for the | |
1724 | * lifetime of the objects. The closest we can is to release the | |
1725 | * offsets on purgeable objects by truncating it and marking it purged, | |
1726 | * which prevents userspace from ever using that object again. | |
1727 | */ | |
1728 | i915_gem_purge(dev_priv, obj->base.size >> PAGE_SHIFT); | |
1729 | ret = drm_gem_create_mmap_offset(&obj->base); | |
1730 | if (ret != -ENOSPC) | |
da494d7c | 1731 | goto out; |
d8cb5086 CW |
1732 | |
1733 | i915_gem_shrink_all(dev_priv); | |
da494d7c DV |
1734 | ret = drm_gem_create_mmap_offset(&obj->base); |
1735 | out: | |
1736 | dev_priv->mm.shrinker_no_lock_stealing = false; | |
1737 | ||
1738 | return ret; | |
d8cb5086 CW |
1739 | } |
1740 | ||
1741 | static void i915_gem_object_free_mmap_offset(struct drm_i915_gem_object *obj) | |
1742 | { | |
d8cb5086 CW |
1743 | drm_gem_free_mmap_offset(&obj->base); |
1744 | } | |
1745 | ||
de151cf6 | 1746 | int |
ff72145b DA |
1747 | i915_gem_mmap_gtt(struct drm_file *file, |
1748 | struct drm_device *dev, | |
1749 | uint32_t handle, | |
1750 | uint64_t *offset) | |
de151cf6 | 1751 | { |
da761a6e | 1752 | struct drm_i915_private *dev_priv = dev->dev_private; |
05394f39 | 1753 | struct drm_i915_gem_object *obj; |
de151cf6 JB |
1754 | int ret; |
1755 | ||
76c1dec1 | 1756 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 1757 | if (ret) |
76c1dec1 | 1758 | return ret; |
de151cf6 | 1759 | |
ff72145b | 1760 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle)); |
c8725226 | 1761 | if (&obj->base == NULL) { |
1d7cfea1 CW |
1762 | ret = -ENOENT; |
1763 | goto unlock; | |
1764 | } | |
de151cf6 | 1765 | |
5d4545ae | 1766 | if (obj->base.size > dev_priv->gtt.mappable_end) { |
da761a6e | 1767 | ret = -E2BIG; |
ff56b0bc | 1768 | goto out; |
da761a6e CW |
1769 | } |
1770 | ||
05394f39 | 1771 | if (obj->madv != I915_MADV_WILLNEED) { |
bd9b6a4e | 1772 | DRM_DEBUG("Attempting to mmap a purgeable buffer\n"); |
8c99e57d | 1773 | ret = -EFAULT; |
1d7cfea1 | 1774 | goto out; |
ab18282d CW |
1775 | } |
1776 | ||
d8cb5086 CW |
1777 | ret = i915_gem_object_create_mmap_offset(obj); |
1778 | if (ret) | |
1779 | goto out; | |
de151cf6 | 1780 | |
0de23977 | 1781 | *offset = drm_vma_node_offset_addr(&obj->base.vma_node); |
de151cf6 | 1782 | |
1d7cfea1 | 1783 | out: |
05394f39 | 1784 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 1785 | unlock: |
de151cf6 | 1786 | mutex_unlock(&dev->struct_mutex); |
1d7cfea1 | 1787 | return ret; |
de151cf6 JB |
1788 | } |
1789 | ||
ff72145b DA |
1790 | /** |
1791 | * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing | |
1792 | * @dev: DRM device | |
1793 | * @data: GTT mapping ioctl data | |
1794 | * @file: GEM object info | |
1795 | * | |
1796 | * Simply returns the fake offset to userspace so it can mmap it. | |
1797 | * The mmap call will end up in drm_gem_mmap(), which will set things | |
1798 | * up so we can get faults in the handler above. | |
1799 | * | |
1800 | * The fault handler will take care of binding the object into the GTT | |
1801 | * (since it may have been evicted to make room for something), allocating | |
1802 | * a fence register, and mapping the appropriate aperture address into | |
1803 | * userspace. | |
1804 | */ | |
1805 | int | |
1806 | i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data, | |
1807 | struct drm_file *file) | |
1808 | { | |
1809 | struct drm_i915_gem_mmap_gtt *args = data; | |
1810 | ||
ff72145b DA |
1811 | return i915_gem_mmap_gtt(file, dev, args->handle, &args->offset); |
1812 | } | |
1813 | ||
5537252b CW |
1814 | static inline int |
1815 | i915_gem_object_is_purgeable(struct drm_i915_gem_object *obj) | |
1816 | { | |
1817 | return obj->madv == I915_MADV_DONTNEED; | |
1818 | } | |
1819 | ||
225067ee DV |
1820 | /* Immediately discard the backing storage */ |
1821 | static void | |
1822 | i915_gem_object_truncate(struct drm_i915_gem_object *obj) | |
e5281ccd | 1823 | { |
4d6294bf | 1824 | i915_gem_object_free_mmap_offset(obj); |
1286ff73 | 1825 | |
4d6294bf CW |
1826 | if (obj->base.filp == NULL) |
1827 | return; | |
e5281ccd | 1828 | |
225067ee DV |
1829 | /* Our goal here is to return as much of the memory as |
1830 | * is possible back to the system as we are called from OOM. | |
1831 | * To do this we must instruct the shmfs to drop all of its | |
1832 | * backing pages, *now*. | |
1833 | */ | |
5537252b | 1834 | shmem_truncate_range(file_inode(obj->base.filp), 0, (loff_t)-1); |
225067ee DV |
1835 | obj->madv = __I915_MADV_PURGED; |
1836 | } | |
e5281ccd | 1837 | |
5537252b CW |
1838 | /* Try to discard unwanted pages */ |
1839 | static void | |
1840 | i915_gem_object_invalidate(struct drm_i915_gem_object *obj) | |
225067ee | 1841 | { |
5537252b CW |
1842 | struct address_space *mapping; |
1843 | ||
1844 | switch (obj->madv) { | |
1845 | case I915_MADV_DONTNEED: | |
1846 | i915_gem_object_truncate(obj); | |
1847 | case __I915_MADV_PURGED: | |
1848 | return; | |
1849 | } | |
1850 | ||
1851 | if (obj->base.filp == NULL) | |
1852 | return; | |
1853 | ||
1854 | mapping = file_inode(obj->base.filp)->i_mapping, | |
1855 | invalidate_mapping_pages(mapping, 0, (loff_t)-1); | |
e5281ccd CW |
1856 | } |
1857 | ||
5cdf5881 | 1858 | static void |
05394f39 | 1859 | i915_gem_object_put_pages_gtt(struct drm_i915_gem_object *obj) |
673a394b | 1860 | { |
90797e6d ID |
1861 | struct sg_page_iter sg_iter; |
1862 | int ret; | |
1286ff73 | 1863 | |
05394f39 | 1864 | BUG_ON(obj->madv == __I915_MADV_PURGED); |
673a394b | 1865 | |
6c085a72 CW |
1866 | ret = i915_gem_object_set_to_cpu_domain(obj, true); |
1867 | if (ret) { | |
1868 | /* In the event of a disaster, abandon all caches and | |
1869 | * hope for the best. | |
1870 | */ | |
1871 | WARN_ON(ret != -EIO); | |
2c22569b | 1872 | i915_gem_clflush_object(obj, true); |
6c085a72 CW |
1873 | obj->base.read_domains = obj->base.write_domain = I915_GEM_DOMAIN_CPU; |
1874 | } | |
1875 | ||
6dacfd2f | 1876 | if (i915_gem_object_needs_bit17_swizzle(obj)) |
280b713b EA |
1877 | i915_gem_object_save_bit_17_swizzle(obj); |
1878 | ||
05394f39 CW |
1879 | if (obj->madv == I915_MADV_DONTNEED) |
1880 | obj->dirty = 0; | |
3ef94daa | 1881 | |
90797e6d | 1882 | for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, 0) { |
2db76d7c | 1883 | struct page *page = sg_page_iter_page(&sg_iter); |
9da3da66 | 1884 | |
05394f39 | 1885 | if (obj->dirty) |
9da3da66 | 1886 | set_page_dirty(page); |
3ef94daa | 1887 | |
05394f39 | 1888 | if (obj->madv == I915_MADV_WILLNEED) |
9da3da66 | 1889 | mark_page_accessed(page); |
3ef94daa | 1890 | |
9da3da66 | 1891 | page_cache_release(page); |
3ef94daa | 1892 | } |
05394f39 | 1893 | obj->dirty = 0; |
673a394b | 1894 | |
9da3da66 CW |
1895 | sg_free_table(obj->pages); |
1896 | kfree(obj->pages); | |
37e680a1 | 1897 | } |
6c085a72 | 1898 | |
dd624afd | 1899 | int |
37e680a1 CW |
1900 | i915_gem_object_put_pages(struct drm_i915_gem_object *obj) |
1901 | { | |
1902 | const struct drm_i915_gem_object_ops *ops = obj->ops; | |
1903 | ||
2f745ad3 | 1904 | if (obj->pages == NULL) |
37e680a1 CW |
1905 | return 0; |
1906 | ||
a5570178 CW |
1907 | if (obj->pages_pin_count) |
1908 | return -EBUSY; | |
1909 | ||
9843877d | 1910 | BUG_ON(i915_gem_obj_bound_any(obj)); |
3e123027 | 1911 | |
a2165e31 CW |
1912 | /* ->put_pages might need to allocate memory for the bit17 swizzle |
1913 | * array, hence protect them from being reaped by removing them from gtt | |
1914 | * lists early. */ | |
35c20a60 | 1915 | list_del(&obj->global_list); |
a2165e31 | 1916 | |
37e680a1 | 1917 | ops->put_pages(obj); |
05394f39 | 1918 | obj->pages = NULL; |
37e680a1 | 1919 | |
5537252b | 1920 | i915_gem_object_invalidate(obj); |
6c085a72 CW |
1921 | |
1922 | return 0; | |
1923 | } | |
1924 | ||
d9973b43 | 1925 | static unsigned long |
93927ca5 DV |
1926 | __i915_gem_shrink(struct drm_i915_private *dev_priv, long target, |
1927 | bool purgeable_only) | |
6c085a72 | 1928 | { |
c8725f3d CW |
1929 | struct list_head still_in_list; |
1930 | struct drm_i915_gem_object *obj; | |
d9973b43 | 1931 | unsigned long count = 0; |
6c085a72 | 1932 | |
57094f82 | 1933 | /* |
c8725f3d | 1934 | * As we may completely rewrite the (un)bound list whilst unbinding |
57094f82 CW |
1935 | * (due to retiring requests) we have to strictly process only |
1936 | * one element of the list at the time, and recheck the list | |
1937 | * on every iteration. | |
c8725f3d CW |
1938 | * |
1939 | * In particular, we must hold a reference whilst removing the | |
1940 | * object as we may end up waiting for and/or retiring the objects. | |
1941 | * This might release the final reference (held by the active list) | |
1942 | * and result in the object being freed from under us. This is | |
1943 | * similar to the precautions the eviction code must take whilst | |
1944 | * removing objects. | |
1945 | * | |
1946 | * Also note that although these lists do not hold a reference to | |
1947 | * the object we can safely grab one here: The final object | |
1948 | * unreferencing and the bound_list are both protected by the | |
1949 | * dev->struct_mutex and so we won't ever be able to observe an | |
1950 | * object on the bound_list with a reference count equals 0. | |
57094f82 | 1951 | */ |
c8725f3d CW |
1952 | INIT_LIST_HEAD(&still_in_list); |
1953 | while (count < target && !list_empty(&dev_priv->mm.unbound_list)) { | |
1954 | obj = list_first_entry(&dev_priv->mm.unbound_list, | |
1955 | typeof(*obj), global_list); | |
1956 | list_move_tail(&obj->global_list, &still_in_list); | |
1957 | ||
1958 | if (!i915_gem_object_is_purgeable(obj) && purgeable_only) | |
1959 | continue; | |
1960 | ||
1961 | drm_gem_object_reference(&obj->base); | |
1962 | ||
1963 | if (i915_gem_object_put_pages(obj) == 0) | |
1964 | count += obj->base.size >> PAGE_SHIFT; | |
1965 | ||
1966 | drm_gem_object_unreference(&obj->base); | |
1967 | } | |
1968 | list_splice(&still_in_list, &dev_priv->mm.unbound_list); | |
1969 | ||
1970 | INIT_LIST_HEAD(&still_in_list); | |
57094f82 | 1971 | while (count < target && !list_empty(&dev_priv->mm.bound_list)) { |
07fe0b12 | 1972 | struct i915_vma *vma, *v; |
80dcfdbd | 1973 | |
57094f82 CW |
1974 | obj = list_first_entry(&dev_priv->mm.bound_list, |
1975 | typeof(*obj), global_list); | |
c8725f3d | 1976 | list_move_tail(&obj->global_list, &still_in_list); |
57094f82 | 1977 | |
80dcfdbd BW |
1978 | if (!i915_gem_object_is_purgeable(obj) && purgeable_only) |
1979 | continue; | |
1980 | ||
57094f82 CW |
1981 | drm_gem_object_reference(&obj->base); |
1982 | ||
07fe0b12 BW |
1983 | list_for_each_entry_safe(vma, v, &obj->vma_list, vma_link) |
1984 | if (i915_vma_unbind(vma)) | |
1985 | break; | |
80dcfdbd | 1986 | |
57094f82 | 1987 | if (i915_gem_object_put_pages(obj) == 0) |
6c085a72 | 1988 | count += obj->base.size >> PAGE_SHIFT; |
57094f82 CW |
1989 | |
1990 | drm_gem_object_unreference(&obj->base); | |
6c085a72 | 1991 | } |
c8725f3d | 1992 | list_splice(&still_in_list, &dev_priv->mm.bound_list); |
6c085a72 CW |
1993 | |
1994 | return count; | |
1995 | } | |
1996 | ||
d9973b43 | 1997 | static unsigned long |
93927ca5 DV |
1998 | i915_gem_purge(struct drm_i915_private *dev_priv, long target) |
1999 | { | |
2000 | return __i915_gem_shrink(dev_priv, target, true); | |
2001 | } | |
2002 | ||
d9973b43 | 2003 | static unsigned long |
6c085a72 CW |
2004 | i915_gem_shrink_all(struct drm_i915_private *dev_priv) |
2005 | { | |
6c085a72 | 2006 | i915_gem_evict_everything(dev_priv->dev); |
c8725f3d | 2007 | return __i915_gem_shrink(dev_priv, LONG_MAX, false); |
225067ee DV |
2008 | } |
2009 | ||
37e680a1 | 2010 | static int |
6c085a72 | 2011 | i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj) |
e5281ccd | 2012 | { |
6c085a72 | 2013 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
e5281ccd CW |
2014 | int page_count, i; |
2015 | struct address_space *mapping; | |
9da3da66 CW |
2016 | struct sg_table *st; |
2017 | struct scatterlist *sg; | |
90797e6d | 2018 | struct sg_page_iter sg_iter; |
e5281ccd | 2019 | struct page *page; |
90797e6d | 2020 | unsigned long last_pfn = 0; /* suppress gcc warning */ |
6c085a72 | 2021 | gfp_t gfp; |
e5281ccd | 2022 | |
6c085a72 CW |
2023 | /* Assert that the object is not currently in any GPU domain. As it |
2024 | * wasn't in the GTT, there shouldn't be any way it could have been in | |
2025 | * a GPU cache | |
2026 | */ | |
2027 | BUG_ON(obj->base.read_domains & I915_GEM_GPU_DOMAINS); | |
2028 | BUG_ON(obj->base.write_domain & I915_GEM_GPU_DOMAINS); | |
2029 | ||
9da3da66 CW |
2030 | st = kmalloc(sizeof(*st), GFP_KERNEL); |
2031 | if (st == NULL) | |
2032 | return -ENOMEM; | |
2033 | ||
05394f39 | 2034 | page_count = obj->base.size / PAGE_SIZE; |
9da3da66 | 2035 | if (sg_alloc_table(st, page_count, GFP_KERNEL)) { |
9da3da66 | 2036 | kfree(st); |
e5281ccd | 2037 | return -ENOMEM; |
9da3da66 | 2038 | } |
e5281ccd | 2039 | |
9da3da66 CW |
2040 | /* Get the list of pages out of our struct file. They'll be pinned |
2041 | * at this point until we release them. | |
2042 | * | |
2043 | * Fail silently without starting the shrinker | |
2044 | */ | |
496ad9aa | 2045 | mapping = file_inode(obj->base.filp)->i_mapping; |
6c085a72 | 2046 | gfp = mapping_gfp_mask(mapping); |
caf49191 | 2047 | gfp |= __GFP_NORETRY | __GFP_NOWARN | __GFP_NO_KSWAPD; |
6c085a72 | 2048 | gfp &= ~(__GFP_IO | __GFP_WAIT); |
90797e6d ID |
2049 | sg = st->sgl; |
2050 | st->nents = 0; | |
2051 | for (i = 0; i < page_count; i++) { | |
6c085a72 CW |
2052 | page = shmem_read_mapping_page_gfp(mapping, i, gfp); |
2053 | if (IS_ERR(page)) { | |
2054 | i915_gem_purge(dev_priv, page_count); | |
2055 | page = shmem_read_mapping_page_gfp(mapping, i, gfp); | |
2056 | } | |
2057 | if (IS_ERR(page)) { | |
2058 | /* We've tried hard to allocate the memory by reaping | |
2059 | * our own buffer, now let the real VM do its job and | |
2060 | * go down in flames if truly OOM. | |
2061 | */ | |
caf49191 | 2062 | gfp &= ~(__GFP_NORETRY | __GFP_NOWARN | __GFP_NO_KSWAPD); |
6c085a72 CW |
2063 | gfp |= __GFP_IO | __GFP_WAIT; |
2064 | ||
2065 | i915_gem_shrink_all(dev_priv); | |
2066 | page = shmem_read_mapping_page_gfp(mapping, i, gfp); | |
2067 | if (IS_ERR(page)) | |
2068 | goto err_pages; | |
2069 | ||
caf49191 | 2070 | gfp |= __GFP_NORETRY | __GFP_NOWARN | __GFP_NO_KSWAPD; |
6c085a72 CW |
2071 | gfp &= ~(__GFP_IO | __GFP_WAIT); |
2072 | } | |
426729dc KRW |
2073 | #ifdef CONFIG_SWIOTLB |
2074 | if (swiotlb_nr_tbl()) { | |
2075 | st->nents++; | |
2076 | sg_set_page(sg, page, PAGE_SIZE, 0); | |
2077 | sg = sg_next(sg); | |
2078 | continue; | |
2079 | } | |
2080 | #endif | |
90797e6d ID |
2081 | if (!i || page_to_pfn(page) != last_pfn + 1) { |
2082 | if (i) | |
2083 | sg = sg_next(sg); | |
2084 | st->nents++; | |
2085 | sg_set_page(sg, page, PAGE_SIZE, 0); | |
2086 | } else { | |
2087 | sg->length += PAGE_SIZE; | |
2088 | } | |
2089 | last_pfn = page_to_pfn(page); | |
3bbbe706 DV |
2090 | |
2091 | /* Check that the i965g/gm workaround works. */ | |
2092 | WARN_ON((gfp & __GFP_DMA32) && (last_pfn >= 0x00100000UL)); | |
e5281ccd | 2093 | } |
426729dc KRW |
2094 | #ifdef CONFIG_SWIOTLB |
2095 | if (!swiotlb_nr_tbl()) | |
2096 | #endif | |
2097 | sg_mark_end(sg); | |
74ce6b6c CW |
2098 | obj->pages = st; |
2099 | ||
6dacfd2f | 2100 | if (i915_gem_object_needs_bit17_swizzle(obj)) |
e5281ccd CW |
2101 | i915_gem_object_do_bit_17_swizzle(obj); |
2102 | ||
2103 | return 0; | |
2104 | ||
2105 | err_pages: | |
90797e6d ID |
2106 | sg_mark_end(sg); |
2107 | for_each_sg_page(st->sgl, &sg_iter, st->nents, 0) | |
2db76d7c | 2108 | page_cache_release(sg_page_iter_page(&sg_iter)); |
9da3da66 CW |
2109 | sg_free_table(st); |
2110 | kfree(st); | |
0820baf3 CW |
2111 | |
2112 | /* shmemfs first checks if there is enough memory to allocate the page | |
2113 | * and reports ENOSPC should there be insufficient, along with the usual | |
2114 | * ENOMEM for a genuine allocation failure. | |
2115 | * | |
2116 | * We use ENOSPC in our driver to mean that we have run out of aperture | |
2117 | * space and so want to translate the error from shmemfs back to our | |
2118 | * usual understanding of ENOMEM. | |
2119 | */ | |
2120 | if (PTR_ERR(page) == -ENOSPC) | |
2121 | return -ENOMEM; | |
2122 | else | |
2123 | return PTR_ERR(page); | |
673a394b EA |
2124 | } |
2125 | ||
37e680a1 CW |
2126 | /* Ensure that the associated pages are gathered from the backing storage |
2127 | * and pinned into our object. i915_gem_object_get_pages() may be called | |
2128 | * multiple times before they are released by a single call to | |
2129 | * i915_gem_object_put_pages() - once the pages are no longer referenced | |
2130 | * either as a result of memory pressure (reaping pages under the shrinker) | |
2131 | * or as the object is itself released. | |
2132 | */ | |
2133 | int | |
2134 | i915_gem_object_get_pages(struct drm_i915_gem_object *obj) | |
2135 | { | |
2136 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; | |
2137 | const struct drm_i915_gem_object_ops *ops = obj->ops; | |
2138 | int ret; | |
2139 | ||
2f745ad3 | 2140 | if (obj->pages) |
37e680a1 CW |
2141 | return 0; |
2142 | ||
43e28f09 | 2143 | if (obj->madv != I915_MADV_WILLNEED) { |
bd9b6a4e | 2144 | DRM_DEBUG("Attempting to obtain a purgeable object\n"); |
8c99e57d | 2145 | return -EFAULT; |
43e28f09 CW |
2146 | } |
2147 | ||
a5570178 CW |
2148 | BUG_ON(obj->pages_pin_count); |
2149 | ||
37e680a1 CW |
2150 | ret = ops->get_pages(obj); |
2151 | if (ret) | |
2152 | return ret; | |
2153 | ||
35c20a60 | 2154 | list_add_tail(&obj->global_list, &dev_priv->mm.unbound_list); |
37e680a1 | 2155 | return 0; |
673a394b EA |
2156 | } |
2157 | ||
e2d05a8b | 2158 | static void |
05394f39 | 2159 | i915_gem_object_move_to_active(struct drm_i915_gem_object *obj, |
a4872ba6 | 2160 | struct intel_engine_cs *ring) |
673a394b | 2161 | { |
05394f39 | 2162 | struct drm_device *dev = obj->base.dev; |
69dc4987 | 2163 | struct drm_i915_private *dev_priv = dev->dev_private; |
9d773091 | 2164 | u32 seqno = intel_ring_get_seqno(ring); |
617dbe27 | 2165 | |
852835f3 | 2166 | BUG_ON(ring == NULL); |
02978ff5 CW |
2167 | if (obj->ring != ring && obj->last_write_seqno) { |
2168 | /* Keep the seqno relative to the current ring */ | |
2169 | obj->last_write_seqno = seqno; | |
2170 | } | |
05394f39 | 2171 | obj->ring = ring; |
673a394b EA |
2172 | |
2173 | /* Add a reference if we're newly entering the active list. */ | |
05394f39 CW |
2174 | if (!obj->active) { |
2175 | drm_gem_object_reference(&obj->base); | |
2176 | obj->active = 1; | |
673a394b | 2177 | } |
e35a41de | 2178 | |
05394f39 | 2179 | list_move_tail(&obj->ring_list, &ring->active_list); |
caea7476 | 2180 | |
0201f1ec | 2181 | obj->last_read_seqno = seqno; |
caea7476 | 2182 | |
7dd49065 | 2183 | if (obj->fenced_gpu_access) { |
caea7476 | 2184 | obj->last_fenced_seqno = seqno; |
caea7476 | 2185 | |
7dd49065 CW |
2186 | /* Bump MRU to take account of the delayed flush */ |
2187 | if (obj->fence_reg != I915_FENCE_REG_NONE) { | |
2188 | struct drm_i915_fence_reg *reg; | |
2189 | ||
2190 | reg = &dev_priv->fence_regs[obj->fence_reg]; | |
2191 | list_move_tail(®->lru_list, | |
2192 | &dev_priv->mm.fence_list); | |
2193 | } | |
caea7476 CW |
2194 | } |
2195 | } | |
2196 | ||
e2d05a8b | 2197 | void i915_vma_move_to_active(struct i915_vma *vma, |
a4872ba6 | 2198 | struct intel_engine_cs *ring) |
e2d05a8b BW |
2199 | { |
2200 | list_move_tail(&vma->mm_list, &vma->vm->active_list); | |
2201 | return i915_gem_object_move_to_active(vma->obj, ring); | |
2202 | } | |
2203 | ||
caea7476 | 2204 | static void |
caea7476 | 2205 | i915_gem_object_move_to_inactive(struct drm_i915_gem_object *obj) |
ce44b0ea | 2206 | { |
ca191b13 | 2207 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
feb822cf BW |
2208 | struct i915_address_space *vm; |
2209 | struct i915_vma *vma; | |
ce44b0ea | 2210 | |
65ce3027 | 2211 | BUG_ON(obj->base.write_domain & ~I915_GEM_GPU_DOMAINS); |
05394f39 | 2212 | BUG_ON(!obj->active); |
caea7476 | 2213 | |
feb822cf BW |
2214 | list_for_each_entry(vm, &dev_priv->vm_list, global_link) { |
2215 | vma = i915_gem_obj_to_vma(obj, vm); | |
2216 | if (vma && !list_empty(&vma->mm_list)) | |
2217 | list_move_tail(&vma->mm_list, &vm->inactive_list); | |
2218 | } | |
caea7476 | 2219 | |
65ce3027 | 2220 | list_del_init(&obj->ring_list); |
caea7476 CW |
2221 | obj->ring = NULL; |
2222 | ||
65ce3027 CW |
2223 | obj->last_read_seqno = 0; |
2224 | obj->last_write_seqno = 0; | |
2225 | obj->base.write_domain = 0; | |
2226 | ||
2227 | obj->last_fenced_seqno = 0; | |
caea7476 | 2228 | obj->fenced_gpu_access = false; |
caea7476 CW |
2229 | |
2230 | obj->active = 0; | |
2231 | drm_gem_object_unreference(&obj->base); | |
2232 | ||
2233 | WARN_ON(i915_verify_lists(dev)); | |
ce44b0ea | 2234 | } |
673a394b | 2235 | |
c8725f3d CW |
2236 | static void |
2237 | i915_gem_object_retire(struct drm_i915_gem_object *obj) | |
2238 | { | |
a4872ba6 | 2239 | struct intel_engine_cs *ring = obj->ring; |
c8725f3d CW |
2240 | |
2241 | if (ring == NULL) | |
2242 | return; | |
2243 | ||
2244 | if (i915_seqno_passed(ring->get_seqno(ring, true), | |
2245 | obj->last_read_seqno)) | |
2246 | i915_gem_object_move_to_inactive(obj); | |
2247 | } | |
2248 | ||
9d773091 | 2249 | static int |
fca26bb4 | 2250 | i915_gem_init_seqno(struct drm_device *dev, u32 seqno) |
53d227f2 | 2251 | { |
9d773091 | 2252 | struct drm_i915_private *dev_priv = dev->dev_private; |
a4872ba6 | 2253 | struct intel_engine_cs *ring; |
9d773091 | 2254 | int ret, i, j; |
53d227f2 | 2255 | |
107f27a5 | 2256 | /* Carefully retire all requests without writing to the rings */ |
9d773091 | 2257 | for_each_ring(ring, dev_priv, i) { |
107f27a5 CW |
2258 | ret = intel_ring_idle(ring); |
2259 | if (ret) | |
2260 | return ret; | |
9d773091 | 2261 | } |
9d773091 | 2262 | i915_gem_retire_requests(dev); |
107f27a5 CW |
2263 | |
2264 | /* Finally reset hw state */ | |
9d773091 | 2265 | for_each_ring(ring, dev_priv, i) { |
fca26bb4 | 2266 | intel_ring_init_seqno(ring, seqno); |
498d2ac1 | 2267 | |
ebc348b2 BW |
2268 | for (j = 0; j < ARRAY_SIZE(ring->semaphore.sync_seqno); j++) |
2269 | ring->semaphore.sync_seqno[j] = 0; | |
9d773091 | 2270 | } |
53d227f2 | 2271 | |
9d773091 | 2272 | return 0; |
53d227f2 DV |
2273 | } |
2274 | ||
fca26bb4 MK |
2275 | int i915_gem_set_seqno(struct drm_device *dev, u32 seqno) |
2276 | { | |
2277 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2278 | int ret; | |
2279 | ||
2280 | if (seqno == 0) | |
2281 | return -EINVAL; | |
2282 | ||
2283 | /* HWS page needs to be set less than what we | |
2284 | * will inject to ring | |
2285 | */ | |
2286 | ret = i915_gem_init_seqno(dev, seqno - 1); | |
2287 | if (ret) | |
2288 | return ret; | |
2289 | ||
2290 | /* Carefully set the last_seqno value so that wrap | |
2291 | * detection still works | |
2292 | */ | |
2293 | dev_priv->next_seqno = seqno; | |
2294 | dev_priv->last_seqno = seqno - 1; | |
2295 | if (dev_priv->last_seqno == 0) | |
2296 | dev_priv->last_seqno--; | |
2297 | ||
2298 | return 0; | |
2299 | } | |
2300 | ||
9d773091 CW |
2301 | int |
2302 | i915_gem_get_seqno(struct drm_device *dev, u32 *seqno) | |
53d227f2 | 2303 | { |
9d773091 CW |
2304 | struct drm_i915_private *dev_priv = dev->dev_private; |
2305 | ||
2306 | /* reserve 0 for non-seqno */ | |
2307 | if (dev_priv->next_seqno == 0) { | |
fca26bb4 | 2308 | int ret = i915_gem_init_seqno(dev, 0); |
9d773091 CW |
2309 | if (ret) |
2310 | return ret; | |
53d227f2 | 2311 | |
9d773091 CW |
2312 | dev_priv->next_seqno = 1; |
2313 | } | |
53d227f2 | 2314 | |
f72b3435 | 2315 | *seqno = dev_priv->last_seqno = dev_priv->next_seqno++; |
9d773091 | 2316 | return 0; |
53d227f2 DV |
2317 | } |
2318 | ||
a4872ba6 | 2319 | int __i915_add_request(struct intel_engine_cs *ring, |
0025c077 | 2320 | struct drm_file *file, |
7d736f4f | 2321 | struct drm_i915_gem_object *obj, |
0025c077 | 2322 | u32 *out_seqno) |
673a394b | 2323 | { |
3e31c6c0 | 2324 | struct drm_i915_private *dev_priv = ring->dev->dev_private; |
acb868d3 | 2325 | struct drm_i915_gem_request *request; |
7d736f4f | 2326 | u32 request_ring_position, request_start; |
3cce469c CW |
2327 | int ret; |
2328 | ||
7d736f4f | 2329 | request_start = intel_ring_get_tail(ring); |
cc889e0f DV |
2330 | /* |
2331 | * Emit any outstanding flushes - execbuf can fail to emit the flush | |
2332 | * after having emitted the batchbuffer command. Hence we need to fix | |
2333 | * things up similar to emitting the lazy request. The difference here | |
2334 | * is that the flush _must_ happen before the next request, no matter | |
2335 | * what. | |
2336 | */ | |
a7b9761d CW |
2337 | ret = intel_ring_flush_all_caches(ring); |
2338 | if (ret) | |
2339 | return ret; | |
cc889e0f | 2340 | |
3c0e234c CW |
2341 | request = ring->preallocated_lazy_request; |
2342 | if (WARN_ON(request == NULL)) | |
acb868d3 | 2343 | return -ENOMEM; |
cc889e0f | 2344 | |
a71d8d94 CW |
2345 | /* Record the position of the start of the request so that |
2346 | * should we detect the updated seqno part-way through the | |
2347 | * GPU processing the request, we never over-estimate the | |
2348 | * position of the head. | |
2349 | */ | |
2350 | request_ring_position = intel_ring_get_tail(ring); | |
2351 | ||
9d773091 | 2352 | ret = ring->add_request(ring); |
3c0e234c | 2353 | if (ret) |
3bb73aba | 2354 | return ret; |
673a394b | 2355 | |
9d773091 | 2356 | request->seqno = intel_ring_get_seqno(ring); |
852835f3 | 2357 | request->ring = ring; |
7d736f4f | 2358 | request->head = request_start; |
a71d8d94 | 2359 | request->tail = request_ring_position; |
7d736f4f MK |
2360 | |
2361 | /* Whilst this request exists, batch_obj will be on the | |
2362 | * active_list, and so will hold the active reference. Only when this | |
2363 | * request is retired will the the batch_obj be moved onto the | |
2364 | * inactive_list and lose its active reference. Hence we do not need | |
2365 | * to explicitly hold another reference here. | |
2366 | */ | |
9a7e0c2a | 2367 | request->batch_obj = obj; |
0e50e96b | 2368 | |
9a7e0c2a CW |
2369 | /* Hold a reference to the current context so that we can inspect |
2370 | * it later in case a hangcheck error event fires. | |
2371 | */ | |
2372 | request->ctx = ring->last_context; | |
0e50e96b MK |
2373 | if (request->ctx) |
2374 | i915_gem_context_reference(request->ctx); | |
2375 | ||
673a394b | 2376 | request->emitted_jiffies = jiffies; |
852835f3 | 2377 | list_add_tail(&request->list, &ring->request_list); |
3bb73aba | 2378 | request->file_priv = NULL; |
852835f3 | 2379 | |
db53a302 CW |
2380 | if (file) { |
2381 | struct drm_i915_file_private *file_priv = file->driver_priv; | |
2382 | ||
1c25595f | 2383 | spin_lock(&file_priv->mm.lock); |
f787a5f5 | 2384 | request->file_priv = file_priv; |
b962442e | 2385 | list_add_tail(&request->client_list, |
f787a5f5 | 2386 | &file_priv->mm.request_list); |
1c25595f | 2387 | spin_unlock(&file_priv->mm.lock); |
b962442e | 2388 | } |
673a394b | 2389 | |
9d773091 | 2390 | trace_i915_gem_request_add(ring, request->seqno); |
1823521d | 2391 | ring->outstanding_lazy_seqno = 0; |
3c0e234c | 2392 | ring->preallocated_lazy_request = NULL; |
db53a302 | 2393 | |
db1b76ca | 2394 | if (!dev_priv->ums.mm_suspended) { |
10cd45b6 MK |
2395 | i915_queue_hangcheck(ring->dev); |
2396 | ||
f62a0076 CW |
2397 | cancel_delayed_work_sync(&dev_priv->mm.idle_work); |
2398 | queue_delayed_work(dev_priv->wq, | |
2399 | &dev_priv->mm.retire_work, | |
2400 | round_jiffies_up_relative(HZ)); | |
2401 | intel_mark_busy(dev_priv->dev); | |
f65d9421 | 2402 | } |
cc889e0f | 2403 | |
acb868d3 | 2404 | if (out_seqno) |
9d773091 | 2405 | *out_seqno = request->seqno; |
3cce469c | 2406 | return 0; |
673a394b EA |
2407 | } |
2408 | ||
f787a5f5 CW |
2409 | static inline void |
2410 | i915_gem_request_remove_from_client(struct drm_i915_gem_request *request) | |
673a394b | 2411 | { |
1c25595f | 2412 | struct drm_i915_file_private *file_priv = request->file_priv; |
673a394b | 2413 | |
1c25595f CW |
2414 | if (!file_priv) |
2415 | return; | |
1c5d22f7 | 2416 | |
1c25595f | 2417 | spin_lock(&file_priv->mm.lock); |
b29c19b6 CW |
2418 | list_del(&request->client_list); |
2419 | request->file_priv = NULL; | |
1c25595f | 2420 | spin_unlock(&file_priv->mm.lock); |
673a394b | 2421 | } |
673a394b | 2422 | |
939fd762 | 2423 | static bool i915_context_is_banned(struct drm_i915_private *dev_priv, |
273497e5 | 2424 | const struct intel_context *ctx) |
be62acb4 | 2425 | { |
44e2c070 | 2426 | unsigned long elapsed; |
be62acb4 | 2427 | |
44e2c070 MK |
2428 | elapsed = get_seconds() - ctx->hang_stats.guilty_ts; |
2429 | ||
2430 | if (ctx->hang_stats.banned) | |
be62acb4 MK |
2431 | return true; |
2432 | ||
2433 | if (elapsed <= DRM_I915_CTX_BAN_PERIOD) { | |
ccc7bed0 | 2434 | if (!i915_gem_context_is_default(ctx)) { |
3fac8978 | 2435 | DRM_DEBUG("context hanging too fast, banning!\n"); |
ccc7bed0 | 2436 | return true; |
88b4aa87 MK |
2437 | } else if (i915_stop_ring_allow_ban(dev_priv)) { |
2438 | if (i915_stop_ring_allow_warn(dev_priv)) | |
2439 | DRM_ERROR("gpu hanging too fast, banning!\n"); | |
ccc7bed0 | 2440 | return true; |
3fac8978 | 2441 | } |
be62acb4 MK |
2442 | } |
2443 | ||
2444 | return false; | |
2445 | } | |
2446 | ||
939fd762 | 2447 | static void i915_set_reset_status(struct drm_i915_private *dev_priv, |
273497e5 | 2448 | struct intel_context *ctx, |
b6b0fac0 | 2449 | const bool guilty) |
aa60c664 | 2450 | { |
44e2c070 MK |
2451 | struct i915_ctx_hang_stats *hs; |
2452 | ||
2453 | if (WARN_ON(!ctx)) | |
2454 | return; | |
aa60c664 | 2455 | |
44e2c070 MK |
2456 | hs = &ctx->hang_stats; |
2457 | ||
2458 | if (guilty) { | |
939fd762 | 2459 | hs->banned = i915_context_is_banned(dev_priv, ctx); |
44e2c070 MK |
2460 | hs->batch_active++; |
2461 | hs->guilty_ts = get_seconds(); | |
2462 | } else { | |
2463 | hs->batch_pending++; | |
aa60c664 MK |
2464 | } |
2465 | } | |
2466 | ||
0e50e96b MK |
2467 | static void i915_gem_free_request(struct drm_i915_gem_request *request) |
2468 | { | |
2469 | list_del(&request->list); | |
2470 | i915_gem_request_remove_from_client(request); | |
2471 | ||
2472 | if (request->ctx) | |
2473 | i915_gem_context_unreference(request->ctx); | |
2474 | ||
2475 | kfree(request); | |
2476 | } | |
2477 | ||
8d9fc7fd | 2478 | struct drm_i915_gem_request * |
a4872ba6 | 2479 | i915_gem_find_active_request(struct intel_engine_cs *ring) |
9375e446 | 2480 | { |
4db080f9 | 2481 | struct drm_i915_gem_request *request; |
8d9fc7fd CW |
2482 | u32 completed_seqno; |
2483 | ||
2484 | completed_seqno = ring->get_seqno(ring, false); | |
4db080f9 CW |
2485 | |
2486 | list_for_each_entry(request, &ring->request_list, list) { | |
2487 | if (i915_seqno_passed(completed_seqno, request->seqno)) | |
2488 | continue; | |
aa60c664 | 2489 | |
b6b0fac0 | 2490 | return request; |
4db080f9 | 2491 | } |
b6b0fac0 MK |
2492 | |
2493 | return NULL; | |
2494 | } | |
2495 | ||
2496 | static void i915_gem_reset_ring_status(struct drm_i915_private *dev_priv, | |
a4872ba6 | 2497 | struct intel_engine_cs *ring) |
b6b0fac0 MK |
2498 | { |
2499 | struct drm_i915_gem_request *request; | |
2500 | bool ring_hung; | |
2501 | ||
8d9fc7fd | 2502 | request = i915_gem_find_active_request(ring); |
b6b0fac0 MK |
2503 | |
2504 | if (request == NULL) | |
2505 | return; | |
2506 | ||
2507 | ring_hung = ring->hangcheck.score >= HANGCHECK_SCORE_RING_HUNG; | |
2508 | ||
939fd762 | 2509 | i915_set_reset_status(dev_priv, request->ctx, ring_hung); |
b6b0fac0 MK |
2510 | |
2511 | list_for_each_entry_continue(request, &ring->request_list, list) | |
939fd762 | 2512 | i915_set_reset_status(dev_priv, request->ctx, false); |
4db080f9 | 2513 | } |
aa60c664 | 2514 | |
4db080f9 | 2515 | static void i915_gem_reset_ring_cleanup(struct drm_i915_private *dev_priv, |
a4872ba6 | 2516 | struct intel_engine_cs *ring) |
4db080f9 | 2517 | { |
dfaae392 | 2518 | while (!list_empty(&ring->active_list)) { |
05394f39 | 2519 | struct drm_i915_gem_object *obj; |
9375e446 | 2520 | |
05394f39 CW |
2521 | obj = list_first_entry(&ring->active_list, |
2522 | struct drm_i915_gem_object, | |
2523 | ring_list); | |
9375e446 | 2524 | |
05394f39 | 2525 | i915_gem_object_move_to_inactive(obj); |
673a394b | 2526 | } |
1d62beea BW |
2527 | |
2528 | /* | |
2529 | * We must free the requests after all the corresponding objects have | |
2530 | * been moved off active lists. Which is the same order as the normal | |
2531 | * retire_requests function does. This is important if object hold | |
2532 | * implicit references on things like e.g. ppgtt address spaces through | |
2533 | * the request. | |
2534 | */ | |
2535 | while (!list_empty(&ring->request_list)) { | |
2536 | struct drm_i915_gem_request *request; | |
2537 | ||
2538 | request = list_first_entry(&ring->request_list, | |
2539 | struct drm_i915_gem_request, | |
2540 | list); | |
2541 | ||
2542 | i915_gem_free_request(request); | |
2543 | } | |
e3efda49 CW |
2544 | |
2545 | /* These may not have been flush before the reset, do so now */ | |
2546 | kfree(ring->preallocated_lazy_request); | |
2547 | ring->preallocated_lazy_request = NULL; | |
2548 | ring->outstanding_lazy_seqno = 0; | |
673a394b EA |
2549 | } |
2550 | ||
19b2dbde | 2551 | void i915_gem_restore_fences(struct drm_device *dev) |
312817a3 CW |
2552 | { |
2553 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2554 | int i; | |
2555 | ||
4b9de737 | 2556 | for (i = 0; i < dev_priv->num_fence_regs; i++) { |
312817a3 | 2557 | struct drm_i915_fence_reg *reg = &dev_priv->fence_regs[i]; |
7d2cb39c | 2558 | |
94a335db DV |
2559 | /* |
2560 | * Commit delayed tiling changes if we have an object still | |
2561 | * attached to the fence, otherwise just clear the fence. | |
2562 | */ | |
2563 | if (reg->obj) { | |
2564 | i915_gem_object_update_fence(reg->obj, reg, | |
2565 | reg->obj->tiling_mode); | |
2566 | } else { | |
2567 | i915_gem_write_fence(dev, i, NULL); | |
2568 | } | |
312817a3 CW |
2569 | } |
2570 | } | |
2571 | ||
069efc1d | 2572 | void i915_gem_reset(struct drm_device *dev) |
673a394b | 2573 | { |
77f01230 | 2574 | struct drm_i915_private *dev_priv = dev->dev_private; |
a4872ba6 | 2575 | struct intel_engine_cs *ring; |
1ec14ad3 | 2576 | int i; |
673a394b | 2577 | |
4db080f9 CW |
2578 | /* |
2579 | * Before we free the objects from the requests, we need to inspect | |
2580 | * them for finding the guilty party. As the requests only borrow | |
2581 | * their reference to the objects, the inspection must be done first. | |
2582 | */ | |
2583 | for_each_ring(ring, dev_priv, i) | |
2584 | i915_gem_reset_ring_status(dev_priv, ring); | |
2585 | ||
b4519513 | 2586 | for_each_ring(ring, dev_priv, i) |
4db080f9 | 2587 | i915_gem_reset_ring_cleanup(dev_priv, ring); |
dfaae392 | 2588 | |
acce9ffa BW |
2589 | i915_gem_context_reset(dev); |
2590 | ||
19b2dbde | 2591 | i915_gem_restore_fences(dev); |
673a394b EA |
2592 | } |
2593 | ||
2594 | /** | |
2595 | * This function clears the request list as sequence numbers are passed. | |
2596 | */ | |
1cf0ba14 | 2597 | void |
a4872ba6 | 2598 | i915_gem_retire_requests_ring(struct intel_engine_cs *ring) |
673a394b | 2599 | { |
673a394b EA |
2600 | uint32_t seqno; |
2601 | ||
db53a302 | 2602 | if (list_empty(&ring->request_list)) |
6c0594a3 KW |
2603 | return; |
2604 | ||
db53a302 | 2605 | WARN_ON(i915_verify_lists(ring->dev)); |
673a394b | 2606 | |
b2eadbc8 | 2607 | seqno = ring->get_seqno(ring, true); |
1ec14ad3 | 2608 | |
e9103038 CW |
2609 | /* Move any buffers on the active list that are no longer referenced |
2610 | * by the ringbuffer to the flushing/inactive lists as appropriate, | |
2611 | * before we free the context associated with the requests. | |
2612 | */ | |
2613 | while (!list_empty(&ring->active_list)) { | |
2614 | struct drm_i915_gem_object *obj; | |
2615 | ||
2616 | obj = list_first_entry(&ring->active_list, | |
2617 | struct drm_i915_gem_object, | |
2618 | ring_list); | |
2619 | ||
2620 | if (!i915_seqno_passed(seqno, obj->last_read_seqno)) | |
2621 | break; | |
2622 | ||
2623 | i915_gem_object_move_to_inactive(obj); | |
2624 | } | |
2625 | ||
2626 | ||
852835f3 | 2627 | while (!list_empty(&ring->request_list)) { |
673a394b | 2628 | struct drm_i915_gem_request *request; |
673a394b | 2629 | |
852835f3 | 2630 | request = list_first_entry(&ring->request_list, |
673a394b EA |
2631 | struct drm_i915_gem_request, |
2632 | list); | |
673a394b | 2633 | |
dfaae392 | 2634 | if (!i915_seqno_passed(seqno, request->seqno)) |
b84d5f0c CW |
2635 | break; |
2636 | ||
db53a302 | 2637 | trace_i915_gem_request_retire(ring, request->seqno); |
a71d8d94 CW |
2638 | /* We know the GPU must have read the request to have |
2639 | * sent us the seqno + interrupt, so use the position | |
2640 | * of tail of the request to update the last known position | |
2641 | * of the GPU head. | |
2642 | */ | |
ee1b1e5e | 2643 | ring->buffer->last_retired_head = request->tail; |
b84d5f0c | 2644 | |
0e50e96b | 2645 | i915_gem_free_request(request); |
b84d5f0c | 2646 | } |
673a394b | 2647 | |
db53a302 CW |
2648 | if (unlikely(ring->trace_irq_seqno && |
2649 | i915_seqno_passed(seqno, ring->trace_irq_seqno))) { | |
1ec14ad3 | 2650 | ring->irq_put(ring); |
db53a302 | 2651 | ring->trace_irq_seqno = 0; |
9d34e5db | 2652 | } |
23bc5982 | 2653 | |
db53a302 | 2654 | WARN_ON(i915_verify_lists(ring->dev)); |
673a394b EA |
2655 | } |
2656 | ||
b29c19b6 | 2657 | bool |
b09a1fec CW |
2658 | i915_gem_retire_requests(struct drm_device *dev) |
2659 | { | |
3e31c6c0 | 2660 | struct drm_i915_private *dev_priv = dev->dev_private; |
a4872ba6 | 2661 | struct intel_engine_cs *ring; |
b29c19b6 | 2662 | bool idle = true; |
1ec14ad3 | 2663 | int i; |
b09a1fec | 2664 | |
b29c19b6 | 2665 | for_each_ring(ring, dev_priv, i) { |
b4519513 | 2666 | i915_gem_retire_requests_ring(ring); |
b29c19b6 CW |
2667 | idle &= list_empty(&ring->request_list); |
2668 | } | |
2669 | ||
2670 | if (idle) | |
2671 | mod_delayed_work(dev_priv->wq, | |
2672 | &dev_priv->mm.idle_work, | |
2673 | msecs_to_jiffies(100)); | |
2674 | ||
2675 | return idle; | |
b09a1fec CW |
2676 | } |
2677 | ||
75ef9da2 | 2678 | static void |
673a394b EA |
2679 | i915_gem_retire_work_handler(struct work_struct *work) |
2680 | { | |
b29c19b6 CW |
2681 | struct drm_i915_private *dev_priv = |
2682 | container_of(work, typeof(*dev_priv), mm.retire_work.work); | |
2683 | struct drm_device *dev = dev_priv->dev; | |
0a58705b | 2684 | bool idle; |
673a394b | 2685 | |
891b48cf | 2686 | /* Come back later if the device is busy... */ |
b29c19b6 CW |
2687 | idle = false; |
2688 | if (mutex_trylock(&dev->struct_mutex)) { | |
2689 | idle = i915_gem_retire_requests(dev); | |
2690 | mutex_unlock(&dev->struct_mutex); | |
673a394b | 2691 | } |
b29c19b6 | 2692 | if (!idle) |
bcb45086 CW |
2693 | queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, |
2694 | round_jiffies_up_relative(HZ)); | |
b29c19b6 | 2695 | } |
0a58705b | 2696 | |
b29c19b6 CW |
2697 | static void |
2698 | i915_gem_idle_work_handler(struct work_struct *work) | |
2699 | { | |
2700 | struct drm_i915_private *dev_priv = | |
2701 | container_of(work, typeof(*dev_priv), mm.idle_work.work); | |
2702 | ||
2703 | intel_mark_idle(dev_priv->dev); | |
673a394b EA |
2704 | } |
2705 | ||
30dfebf3 DV |
2706 | /** |
2707 | * Ensures that an object will eventually get non-busy by flushing any required | |
2708 | * write domains, emitting any outstanding lazy request and retiring and | |
2709 | * completed requests. | |
2710 | */ | |
2711 | static int | |
2712 | i915_gem_object_flush_active(struct drm_i915_gem_object *obj) | |
2713 | { | |
2714 | int ret; | |
2715 | ||
2716 | if (obj->active) { | |
0201f1ec | 2717 | ret = i915_gem_check_olr(obj->ring, obj->last_read_seqno); |
30dfebf3 DV |
2718 | if (ret) |
2719 | return ret; | |
2720 | ||
30dfebf3 DV |
2721 | i915_gem_retire_requests_ring(obj->ring); |
2722 | } | |
2723 | ||
2724 | return 0; | |
2725 | } | |
2726 | ||
23ba4fd0 BW |
2727 | /** |
2728 | * i915_gem_wait_ioctl - implements DRM_IOCTL_I915_GEM_WAIT | |
2729 | * @DRM_IOCTL_ARGS: standard ioctl arguments | |
2730 | * | |
2731 | * Returns 0 if successful, else an error is returned with the remaining time in | |
2732 | * the timeout parameter. | |
2733 | * -ETIME: object is still busy after timeout | |
2734 | * -ERESTARTSYS: signal interrupted the wait | |
2735 | * -ENONENT: object doesn't exist | |
2736 | * Also possible, but rare: | |
2737 | * -EAGAIN: GPU wedged | |
2738 | * -ENOMEM: damn | |
2739 | * -ENODEV: Internal IRQ fail | |
2740 | * -E?: The add request failed | |
2741 | * | |
2742 | * The wait ioctl with a timeout of 0 reimplements the busy ioctl. With any | |
2743 | * non-zero timeout parameter the wait ioctl will wait for the given number of | |
2744 | * nanoseconds on an object becoming unbusy. Since the wait itself does so | |
2745 | * without holding struct_mutex the object may become re-busied before this | |
2746 | * function completes. A similar but shorter * race condition exists in the busy | |
2747 | * ioctl | |
2748 | */ | |
2749 | int | |
2750 | i915_gem_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *file) | |
2751 | { | |
3e31c6c0 | 2752 | struct drm_i915_private *dev_priv = dev->dev_private; |
23ba4fd0 BW |
2753 | struct drm_i915_gem_wait *args = data; |
2754 | struct drm_i915_gem_object *obj; | |
a4872ba6 | 2755 | struct intel_engine_cs *ring = NULL; |
eac1f14f | 2756 | struct timespec timeout_stack, *timeout = NULL; |
f69061be | 2757 | unsigned reset_counter; |
23ba4fd0 BW |
2758 | u32 seqno = 0; |
2759 | int ret = 0; | |
2760 | ||
eac1f14f BW |
2761 | if (args->timeout_ns >= 0) { |
2762 | timeout_stack = ns_to_timespec(args->timeout_ns); | |
2763 | timeout = &timeout_stack; | |
2764 | } | |
23ba4fd0 BW |
2765 | |
2766 | ret = i915_mutex_lock_interruptible(dev); | |
2767 | if (ret) | |
2768 | return ret; | |
2769 | ||
2770 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->bo_handle)); | |
2771 | if (&obj->base == NULL) { | |
2772 | mutex_unlock(&dev->struct_mutex); | |
2773 | return -ENOENT; | |
2774 | } | |
2775 | ||
30dfebf3 DV |
2776 | /* Need to make sure the object gets inactive eventually. */ |
2777 | ret = i915_gem_object_flush_active(obj); | |
23ba4fd0 BW |
2778 | if (ret) |
2779 | goto out; | |
2780 | ||
2781 | if (obj->active) { | |
0201f1ec | 2782 | seqno = obj->last_read_seqno; |
23ba4fd0 BW |
2783 | ring = obj->ring; |
2784 | } | |
2785 | ||
2786 | if (seqno == 0) | |
2787 | goto out; | |
2788 | ||
23ba4fd0 BW |
2789 | /* Do this after OLR check to make sure we make forward progress polling |
2790 | * on this IOCTL with a 0 timeout (like busy ioctl) | |
2791 | */ | |
2792 | if (!args->timeout_ns) { | |
2793 | ret = -ETIME; | |
2794 | goto out; | |
2795 | } | |
2796 | ||
2797 | drm_gem_object_unreference(&obj->base); | |
f69061be | 2798 | reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter); |
23ba4fd0 BW |
2799 | mutex_unlock(&dev->struct_mutex); |
2800 | ||
b29c19b6 | 2801 | ret = __wait_seqno(ring, seqno, reset_counter, true, timeout, file->driver_priv); |
4f42f4ef | 2802 | if (timeout) |
eac1f14f | 2803 | args->timeout_ns = timespec_to_ns(timeout); |
23ba4fd0 BW |
2804 | return ret; |
2805 | ||
2806 | out: | |
2807 | drm_gem_object_unreference(&obj->base); | |
2808 | mutex_unlock(&dev->struct_mutex); | |
2809 | return ret; | |
2810 | } | |
2811 | ||
5816d648 BW |
2812 | /** |
2813 | * i915_gem_object_sync - sync an object to a ring. | |
2814 | * | |
2815 | * @obj: object which may be in use on another ring. | |
2816 | * @to: ring we wish to use the object on. May be NULL. | |
2817 | * | |
2818 | * This code is meant to abstract object synchronization with the GPU. | |
2819 | * Calling with NULL implies synchronizing the object with the CPU | |
2820 | * rather than a particular GPU ring. | |
2821 | * | |
2822 | * Returns 0 if successful, else propagates up the lower layer error. | |
2823 | */ | |
2911a35b BW |
2824 | int |
2825 | i915_gem_object_sync(struct drm_i915_gem_object *obj, | |
a4872ba6 | 2826 | struct intel_engine_cs *to) |
2911a35b | 2827 | { |
a4872ba6 | 2828 | struct intel_engine_cs *from = obj->ring; |
2911a35b BW |
2829 | u32 seqno; |
2830 | int ret, idx; | |
2831 | ||
2832 | if (from == NULL || to == from) | |
2833 | return 0; | |
2834 | ||
5816d648 | 2835 | if (to == NULL || !i915_semaphore_is_enabled(obj->base.dev)) |
0201f1ec | 2836 | return i915_gem_object_wait_rendering(obj, false); |
2911a35b BW |
2837 | |
2838 | idx = intel_ring_sync_index(from, to); | |
2839 | ||
0201f1ec | 2840 | seqno = obj->last_read_seqno; |
ebc348b2 | 2841 | if (seqno <= from->semaphore.sync_seqno[idx]) |
2911a35b BW |
2842 | return 0; |
2843 | ||
b4aca010 BW |
2844 | ret = i915_gem_check_olr(obj->ring, seqno); |
2845 | if (ret) | |
2846 | return ret; | |
2911a35b | 2847 | |
b52b89da | 2848 | trace_i915_gem_ring_sync_to(from, to, seqno); |
ebc348b2 | 2849 | ret = to->semaphore.sync_to(to, from, seqno); |
e3a5a225 | 2850 | if (!ret) |
7b01e260 MK |
2851 | /* We use last_read_seqno because sync_to() |
2852 | * might have just caused seqno wrap under | |
2853 | * the radar. | |
2854 | */ | |
ebc348b2 | 2855 | from->semaphore.sync_seqno[idx] = obj->last_read_seqno; |
2911a35b | 2856 | |
e3a5a225 | 2857 | return ret; |
2911a35b BW |
2858 | } |
2859 | ||
b5ffc9bc CW |
2860 | static void i915_gem_object_finish_gtt(struct drm_i915_gem_object *obj) |
2861 | { | |
2862 | u32 old_write_domain, old_read_domains; | |
2863 | ||
b5ffc9bc CW |
2864 | /* Force a pagefault for domain tracking on next user access */ |
2865 | i915_gem_release_mmap(obj); | |
2866 | ||
b97c3d9c KP |
2867 | if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0) |
2868 | return; | |
2869 | ||
97c809fd CW |
2870 | /* Wait for any direct GTT access to complete */ |
2871 | mb(); | |
2872 | ||
b5ffc9bc CW |
2873 | old_read_domains = obj->base.read_domains; |
2874 | old_write_domain = obj->base.write_domain; | |
2875 | ||
2876 | obj->base.read_domains &= ~I915_GEM_DOMAIN_GTT; | |
2877 | obj->base.write_domain &= ~I915_GEM_DOMAIN_GTT; | |
2878 | ||
2879 | trace_i915_gem_object_change_domain(obj, | |
2880 | old_read_domains, | |
2881 | old_write_domain); | |
2882 | } | |
2883 | ||
07fe0b12 | 2884 | int i915_vma_unbind(struct i915_vma *vma) |
673a394b | 2885 | { |
07fe0b12 | 2886 | struct drm_i915_gem_object *obj = vma->obj; |
3e31c6c0 | 2887 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
43e28f09 | 2888 | int ret; |
673a394b | 2889 | |
07fe0b12 | 2890 | if (list_empty(&vma->vma_link)) |
673a394b EA |
2891 | return 0; |
2892 | ||
0ff501cb DV |
2893 | if (!drm_mm_node_allocated(&vma->node)) { |
2894 | i915_gem_vma_destroy(vma); | |
0ff501cb DV |
2895 | return 0; |
2896 | } | |
433544bd | 2897 | |
d7f46fc4 | 2898 | if (vma->pin_count) |
31d8d651 | 2899 | return -EBUSY; |
673a394b | 2900 | |
c4670ad0 CW |
2901 | BUG_ON(obj->pages == NULL); |
2902 | ||
a8198eea | 2903 | ret = i915_gem_object_finish_gpu(obj); |
1488fc08 | 2904 | if (ret) |
a8198eea CW |
2905 | return ret; |
2906 | /* Continue on if we fail due to EIO, the GPU is hung so we | |
2907 | * should be safe and we need to cleanup or else we might | |
2908 | * cause memory corruption through use-after-free. | |
2909 | */ | |
2910 | ||
8b1bc9b4 DV |
2911 | if (i915_is_ggtt(vma->vm)) { |
2912 | i915_gem_object_finish_gtt(obj); | |
5323fd04 | 2913 | |
8b1bc9b4 DV |
2914 | /* release the fence reg _after_ flushing */ |
2915 | ret = i915_gem_object_put_fence(obj); | |
2916 | if (ret) | |
2917 | return ret; | |
2918 | } | |
96b47b65 | 2919 | |
07fe0b12 | 2920 | trace_i915_vma_unbind(vma); |
db53a302 | 2921 | |
6f65e29a BW |
2922 | vma->unbind_vma(vma); |
2923 | ||
74163907 | 2924 | i915_gem_gtt_finish_object(obj); |
7bddb01f | 2925 | |
64bf9303 | 2926 | list_del_init(&vma->mm_list); |
75e9e915 | 2927 | /* Avoid an unnecessary call to unbind on rebind. */ |
5cacaac7 BW |
2928 | if (i915_is_ggtt(vma->vm)) |
2929 | obj->map_and_fenceable = true; | |
673a394b | 2930 | |
2f633156 BW |
2931 | drm_mm_remove_node(&vma->node); |
2932 | i915_gem_vma_destroy(vma); | |
2933 | ||
2934 | /* Since the unbound list is global, only move to that list if | |
b93dab6e | 2935 | * no more VMAs exist. */ |
2f633156 BW |
2936 | if (list_empty(&obj->vma_list)) |
2937 | list_move_tail(&obj->global_list, &dev_priv->mm.unbound_list); | |
673a394b | 2938 | |
70903c3b CW |
2939 | /* And finally now the object is completely decoupled from this vma, |
2940 | * we can drop its hold on the backing storage and allow it to be | |
2941 | * reaped by the shrinker. | |
2942 | */ | |
2943 | i915_gem_object_unpin_pages(obj); | |
2944 | ||
88241785 | 2945 | return 0; |
54cf91dc CW |
2946 | } |
2947 | ||
b2da9fe5 | 2948 | int i915_gpu_idle(struct drm_device *dev) |
4df2faf4 | 2949 | { |
3e31c6c0 | 2950 | struct drm_i915_private *dev_priv = dev->dev_private; |
a4872ba6 | 2951 | struct intel_engine_cs *ring; |
1ec14ad3 | 2952 | int ret, i; |
4df2faf4 | 2953 | |
4df2faf4 | 2954 | /* Flush everything onto the inactive list. */ |
b4519513 | 2955 | for_each_ring(ring, dev_priv, i) { |
691e6415 | 2956 | ret = i915_switch_context(ring, ring->default_context); |
b6c7488d BW |
2957 | if (ret) |
2958 | return ret; | |
2959 | ||
3e960501 | 2960 | ret = intel_ring_idle(ring); |
1ec14ad3 CW |
2961 | if (ret) |
2962 | return ret; | |
2963 | } | |
4df2faf4 | 2964 | |
8a1a49f9 | 2965 | return 0; |
4df2faf4 DV |
2966 | } |
2967 | ||
9ce079e4 CW |
2968 | static void i965_write_fence_reg(struct drm_device *dev, int reg, |
2969 | struct drm_i915_gem_object *obj) | |
de151cf6 | 2970 | { |
3e31c6c0 | 2971 | struct drm_i915_private *dev_priv = dev->dev_private; |
56c844e5 ID |
2972 | int fence_reg; |
2973 | int fence_pitch_shift; | |
de151cf6 | 2974 | |
56c844e5 ID |
2975 | if (INTEL_INFO(dev)->gen >= 6) { |
2976 | fence_reg = FENCE_REG_SANDYBRIDGE_0; | |
2977 | fence_pitch_shift = SANDYBRIDGE_FENCE_PITCH_SHIFT; | |
2978 | } else { | |
2979 | fence_reg = FENCE_REG_965_0; | |
2980 | fence_pitch_shift = I965_FENCE_PITCH_SHIFT; | |
2981 | } | |
2982 | ||
d18b9619 CW |
2983 | fence_reg += reg * 8; |
2984 | ||
2985 | /* To w/a incoherency with non-atomic 64-bit register updates, | |
2986 | * we split the 64-bit update into two 32-bit writes. In order | |
2987 | * for a partial fence not to be evaluated between writes, we | |
2988 | * precede the update with write to turn off the fence register, | |
2989 | * and only enable the fence as the last step. | |
2990 | * | |
2991 | * For extra levels of paranoia, we make sure each step lands | |
2992 | * before applying the next step. | |
2993 | */ | |
2994 | I915_WRITE(fence_reg, 0); | |
2995 | POSTING_READ(fence_reg); | |
2996 | ||
9ce079e4 | 2997 | if (obj) { |
f343c5f6 | 2998 | u32 size = i915_gem_obj_ggtt_size(obj); |
d18b9619 | 2999 | uint64_t val; |
de151cf6 | 3000 | |
f343c5f6 | 3001 | val = (uint64_t)((i915_gem_obj_ggtt_offset(obj) + size - 4096) & |
9ce079e4 | 3002 | 0xfffff000) << 32; |
f343c5f6 | 3003 | val |= i915_gem_obj_ggtt_offset(obj) & 0xfffff000; |
56c844e5 | 3004 | val |= (uint64_t)((obj->stride / 128) - 1) << fence_pitch_shift; |
9ce079e4 CW |
3005 | if (obj->tiling_mode == I915_TILING_Y) |
3006 | val |= 1 << I965_FENCE_TILING_Y_SHIFT; | |
3007 | val |= I965_FENCE_REG_VALID; | |
c6642782 | 3008 | |
d18b9619 CW |
3009 | I915_WRITE(fence_reg + 4, val >> 32); |
3010 | POSTING_READ(fence_reg + 4); | |
3011 | ||
3012 | I915_WRITE(fence_reg + 0, val); | |
3013 | POSTING_READ(fence_reg); | |
3014 | } else { | |
3015 | I915_WRITE(fence_reg + 4, 0); | |
3016 | POSTING_READ(fence_reg + 4); | |
3017 | } | |
de151cf6 JB |
3018 | } |
3019 | ||
9ce079e4 CW |
3020 | static void i915_write_fence_reg(struct drm_device *dev, int reg, |
3021 | struct drm_i915_gem_object *obj) | |
de151cf6 | 3022 | { |
3e31c6c0 | 3023 | struct drm_i915_private *dev_priv = dev->dev_private; |
9ce079e4 | 3024 | u32 val; |
de151cf6 | 3025 | |
9ce079e4 | 3026 | if (obj) { |
f343c5f6 | 3027 | u32 size = i915_gem_obj_ggtt_size(obj); |
9ce079e4 CW |
3028 | int pitch_val; |
3029 | int tile_width; | |
c6642782 | 3030 | |
f343c5f6 | 3031 | WARN((i915_gem_obj_ggtt_offset(obj) & ~I915_FENCE_START_MASK) || |
9ce079e4 | 3032 | (size & -size) != size || |
f343c5f6 BW |
3033 | (i915_gem_obj_ggtt_offset(obj) & (size - 1)), |
3034 | "object 0x%08lx [fenceable? %d] not 1M or pot-size (0x%08x) aligned\n", | |
3035 | i915_gem_obj_ggtt_offset(obj), obj->map_and_fenceable, size); | |
c6642782 | 3036 | |
9ce079e4 CW |
3037 | if (obj->tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev)) |
3038 | tile_width = 128; | |
3039 | else | |
3040 | tile_width = 512; | |
3041 | ||
3042 | /* Note: pitch better be a power of two tile widths */ | |
3043 | pitch_val = obj->stride / tile_width; | |
3044 | pitch_val = ffs(pitch_val) - 1; | |
3045 | ||
f343c5f6 | 3046 | val = i915_gem_obj_ggtt_offset(obj); |
9ce079e4 CW |
3047 | if (obj->tiling_mode == I915_TILING_Y) |
3048 | val |= 1 << I830_FENCE_TILING_Y_SHIFT; | |
3049 | val |= I915_FENCE_SIZE_BITS(size); | |
3050 | val |= pitch_val << I830_FENCE_PITCH_SHIFT; | |
3051 | val |= I830_FENCE_REG_VALID; | |
3052 | } else | |
3053 | val = 0; | |
3054 | ||
3055 | if (reg < 8) | |
3056 | reg = FENCE_REG_830_0 + reg * 4; | |
3057 | else | |
3058 | reg = FENCE_REG_945_8 + (reg - 8) * 4; | |
3059 | ||
3060 | I915_WRITE(reg, val); | |
3061 | POSTING_READ(reg); | |
de151cf6 JB |
3062 | } |
3063 | ||
9ce079e4 CW |
3064 | static void i830_write_fence_reg(struct drm_device *dev, int reg, |
3065 | struct drm_i915_gem_object *obj) | |
de151cf6 | 3066 | { |
3e31c6c0 | 3067 | struct drm_i915_private *dev_priv = dev->dev_private; |
de151cf6 | 3068 | uint32_t val; |
de151cf6 | 3069 | |
9ce079e4 | 3070 | if (obj) { |
f343c5f6 | 3071 | u32 size = i915_gem_obj_ggtt_size(obj); |
9ce079e4 | 3072 | uint32_t pitch_val; |
de151cf6 | 3073 | |
f343c5f6 | 3074 | WARN((i915_gem_obj_ggtt_offset(obj) & ~I830_FENCE_START_MASK) || |
9ce079e4 | 3075 | (size & -size) != size || |
f343c5f6 BW |
3076 | (i915_gem_obj_ggtt_offset(obj) & (size - 1)), |
3077 | "object 0x%08lx not 512K or pot-size 0x%08x aligned\n", | |
3078 | i915_gem_obj_ggtt_offset(obj), size); | |
e76a16de | 3079 | |
9ce079e4 CW |
3080 | pitch_val = obj->stride / 128; |
3081 | pitch_val = ffs(pitch_val) - 1; | |
de151cf6 | 3082 | |
f343c5f6 | 3083 | val = i915_gem_obj_ggtt_offset(obj); |
9ce079e4 CW |
3084 | if (obj->tiling_mode == I915_TILING_Y) |
3085 | val |= 1 << I830_FENCE_TILING_Y_SHIFT; | |
3086 | val |= I830_FENCE_SIZE_BITS(size); | |
3087 | val |= pitch_val << I830_FENCE_PITCH_SHIFT; | |
3088 | val |= I830_FENCE_REG_VALID; | |
3089 | } else | |
3090 | val = 0; | |
c6642782 | 3091 | |
9ce079e4 CW |
3092 | I915_WRITE(FENCE_REG_830_0 + reg * 4, val); |
3093 | POSTING_READ(FENCE_REG_830_0 + reg * 4); | |
3094 | } | |
3095 | ||
d0a57789 CW |
3096 | inline static bool i915_gem_object_needs_mb(struct drm_i915_gem_object *obj) |
3097 | { | |
3098 | return obj && obj->base.read_domains & I915_GEM_DOMAIN_GTT; | |
3099 | } | |
3100 | ||
9ce079e4 CW |
3101 | static void i915_gem_write_fence(struct drm_device *dev, int reg, |
3102 | struct drm_i915_gem_object *obj) | |
3103 | { | |
d0a57789 CW |
3104 | struct drm_i915_private *dev_priv = dev->dev_private; |
3105 | ||
3106 | /* Ensure that all CPU reads are completed before installing a fence | |
3107 | * and all writes before removing the fence. | |
3108 | */ | |
3109 | if (i915_gem_object_needs_mb(dev_priv->fence_regs[reg].obj)) | |
3110 | mb(); | |
3111 | ||
94a335db DV |
3112 | WARN(obj && (!obj->stride || !obj->tiling_mode), |
3113 | "bogus fence setup with stride: 0x%x, tiling mode: %i\n", | |
3114 | obj->stride, obj->tiling_mode); | |
3115 | ||
9ce079e4 | 3116 | switch (INTEL_INFO(dev)->gen) { |
5ab31333 | 3117 | case 8: |
9ce079e4 | 3118 | case 7: |
56c844e5 | 3119 | case 6: |
9ce079e4 CW |
3120 | case 5: |
3121 | case 4: i965_write_fence_reg(dev, reg, obj); break; | |
3122 | case 3: i915_write_fence_reg(dev, reg, obj); break; | |
3123 | case 2: i830_write_fence_reg(dev, reg, obj); break; | |
7dbf9d6e | 3124 | default: BUG(); |
9ce079e4 | 3125 | } |
d0a57789 CW |
3126 | |
3127 | /* And similarly be paranoid that no direct access to this region | |
3128 | * is reordered to before the fence is installed. | |
3129 | */ | |
3130 | if (i915_gem_object_needs_mb(obj)) | |
3131 | mb(); | |
de151cf6 JB |
3132 | } |
3133 | ||
61050808 CW |
3134 | static inline int fence_number(struct drm_i915_private *dev_priv, |
3135 | struct drm_i915_fence_reg *fence) | |
3136 | { | |
3137 | return fence - dev_priv->fence_regs; | |
3138 | } | |
3139 | ||
3140 | static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj, | |
3141 | struct drm_i915_fence_reg *fence, | |
3142 | bool enable) | |
3143 | { | |
2dc8aae0 | 3144 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
46a0b638 CW |
3145 | int reg = fence_number(dev_priv, fence); |
3146 | ||
3147 | i915_gem_write_fence(obj->base.dev, reg, enable ? obj : NULL); | |
61050808 CW |
3148 | |
3149 | if (enable) { | |
46a0b638 | 3150 | obj->fence_reg = reg; |
61050808 CW |
3151 | fence->obj = obj; |
3152 | list_move_tail(&fence->lru_list, &dev_priv->mm.fence_list); | |
3153 | } else { | |
3154 | obj->fence_reg = I915_FENCE_REG_NONE; | |
3155 | fence->obj = NULL; | |
3156 | list_del_init(&fence->lru_list); | |
3157 | } | |
94a335db | 3158 | obj->fence_dirty = false; |
61050808 CW |
3159 | } |
3160 | ||
d9e86c0e | 3161 | static int |
d0a57789 | 3162 | i915_gem_object_wait_fence(struct drm_i915_gem_object *obj) |
d9e86c0e | 3163 | { |
1c293ea3 | 3164 | if (obj->last_fenced_seqno) { |
86d5bc37 | 3165 | int ret = i915_wait_seqno(obj->ring, obj->last_fenced_seqno); |
18991845 CW |
3166 | if (ret) |
3167 | return ret; | |
d9e86c0e CW |
3168 | |
3169 | obj->last_fenced_seqno = 0; | |
d9e86c0e CW |
3170 | } |
3171 | ||
86d5bc37 | 3172 | obj->fenced_gpu_access = false; |
d9e86c0e CW |
3173 | return 0; |
3174 | } | |
3175 | ||
3176 | int | |
3177 | i915_gem_object_put_fence(struct drm_i915_gem_object *obj) | |
3178 | { | |
61050808 | 3179 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
f9c513e9 | 3180 | struct drm_i915_fence_reg *fence; |
d9e86c0e CW |
3181 | int ret; |
3182 | ||
d0a57789 | 3183 | ret = i915_gem_object_wait_fence(obj); |
d9e86c0e CW |
3184 | if (ret) |
3185 | return ret; | |
3186 | ||
61050808 CW |
3187 | if (obj->fence_reg == I915_FENCE_REG_NONE) |
3188 | return 0; | |
d9e86c0e | 3189 | |
f9c513e9 CW |
3190 | fence = &dev_priv->fence_regs[obj->fence_reg]; |
3191 | ||
aff10b30 DV |
3192 | if (WARN_ON(fence->pin_count)) |
3193 | return -EBUSY; | |
3194 | ||
61050808 | 3195 | i915_gem_object_fence_lost(obj); |
f9c513e9 | 3196 | i915_gem_object_update_fence(obj, fence, false); |
d9e86c0e CW |
3197 | |
3198 | return 0; | |
3199 | } | |
3200 | ||
3201 | static struct drm_i915_fence_reg * | |
a360bb1a | 3202 | i915_find_fence_reg(struct drm_device *dev) |
ae3db24a | 3203 | { |
ae3db24a | 3204 | struct drm_i915_private *dev_priv = dev->dev_private; |
8fe301ad | 3205 | struct drm_i915_fence_reg *reg, *avail; |
d9e86c0e | 3206 | int i; |
ae3db24a DV |
3207 | |
3208 | /* First try to find a free reg */ | |
d9e86c0e | 3209 | avail = NULL; |
ae3db24a DV |
3210 | for (i = dev_priv->fence_reg_start; i < dev_priv->num_fence_regs; i++) { |
3211 | reg = &dev_priv->fence_regs[i]; | |
3212 | if (!reg->obj) | |
d9e86c0e | 3213 | return reg; |
ae3db24a | 3214 | |
1690e1eb | 3215 | if (!reg->pin_count) |
d9e86c0e | 3216 | avail = reg; |
ae3db24a DV |
3217 | } |
3218 | ||
d9e86c0e | 3219 | if (avail == NULL) |
5dce5b93 | 3220 | goto deadlock; |
ae3db24a DV |
3221 | |
3222 | /* None available, try to steal one or wait for a user to finish */ | |
d9e86c0e | 3223 | list_for_each_entry(reg, &dev_priv->mm.fence_list, lru_list) { |
1690e1eb | 3224 | if (reg->pin_count) |
ae3db24a DV |
3225 | continue; |
3226 | ||
8fe301ad | 3227 | return reg; |
ae3db24a DV |
3228 | } |
3229 | ||
5dce5b93 CW |
3230 | deadlock: |
3231 | /* Wait for completion of pending flips which consume fences */ | |
3232 | if (intel_has_pending_fb_unpin(dev)) | |
3233 | return ERR_PTR(-EAGAIN); | |
3234 | ||
3235 | return ERR_PTR(-EDEADLK); | |
ae3db24a DV |
3236 | } |
3237 | ||
de151cf6 | 3238 | /** |
9a5a53b3 | 3239 | * i915_gem_object_get_fence - set up fencing for an object |
de151cf6 JB |
3240 | * @obj: object to map through a fence reg |
3241 | * | |
3242 | * When mapping objects through the GTT, userspace wants to be able to write | |
3243 | * to them without having to worry about swizzling if the object is tiled. | |
de151cf6 JB |
3244 | * This function walks the fence regs looking for a free one for @obj, |
3245 | * stealing one if it can't find any. | |
3246 | * | |
3247 | * It then sets up the reg based on the object's properties: address, pitch | |
3248 | * and tiling format. | |
9a5a53b3 CW |
3249 | * |
3250 | * For an untiled surface, this removes any existing fence. | |
de151cf6 | 3251 | */ |
8c4b8c3f | 3252 | int |
06d98131 | 3253 | i915_gem_object_get_fence(struct drm_i915_gem_object *obj) |
de151cf6 | 3254 | { |
05394f39 | 3255 | struct drm_device *dev = obj->base.dev; |
79e53945 | 3256 | struct drm_i915_private *dev_priv = dev->dev_private; |
14415745 | 3257 | bool enable = obj->tiling_mode != I915_TILING_NONE; |
d9e86c0e | 3258 | struct drm_i915_fence_reg *reg; |
ae3db24a | 3259 | int ret; |
de151cf6 | 3260 | |
14415745 CW |
3261 | /* Have we updated the tiling parameters upon the object and so |
3262 | * will need to serialise the write to the associated fence register? | |
3263 | */ | |
5d82e3e6 | 3264 | if (obj->fence_dirty) { |
d0a57789 | 3265 | ret = i915_gem_object_wait_fence(obj); |
14415745 CW |
3266 | if (ret) |
3267 | return ret; | |
3268 | } | |
9a5a53b3 | 3269 | |
d9e86c0e | 3270 | /* Just update our place in the LRU if our fence is getting reused. */ |
05394f39 CW |
3271 | if (obj->fence_reg != I915_FENCE_REG_NONE) { |
3272 | reg = &dev_priv->fence_regs[obj->fence_reg]; | |
5d82e3e6 | 3273 | if (!obj->fence_dirty) { |
14415745 CW |
3274 | list_move_tail(®->lru_list, |
3275 | &dev_priv->mm.fence_list); | |
3276 | return 0; | |
3277 | } | |
3278 | } else if (enable) { | |
3279 | reg = i915_find_fence_reg(dev); | |
5dce5b93 CW |
3280 | if (IS_ERR(reg)) |
3281 | return PTR_ERR(reg); | |
d9e86c0e | 3282 | |
14415745 CW |
3283 | if (reg->obj) { |
3284 | struct drm_i915_gem_object *old = reg->obj; | |
3285 | ||
d0a57789 | 3286 | ret = i915_gem_object_wait_fence(old); |
29c5a587 CW |
3287 | if (ret) |
3288 | return ret; | |
3289 | ||
14415745 | 3290 | i915_gem_object_fence_lost(old); |
29c5a587 | 3291 | } |
14415745 | 3292 | } else |
a09ba7fa | 3293 | return 0; |
a09ba7fa | 3294 | |
14415745 | 3295 | i915_gem_object_update_fence(obj, reg, enable); |
14415745 | 3296 | |
9ce079e4 | 3297 | return 0; |
de151cf6 JB |
3298 | } |
3299 | ||
42d6ab48 CW |
3300 | static bool i915_gem_valid_gtt_space(struct drm_device *dev, |
3301 | struct drm_mm_node *gtt_space, | |
3302 | unsigned long cache_level) | |
3303 | { | |
3304 | struct drm_mm_node *other; | |
3305 | ||
3306 | /* On non-LLC machines we have to be careful when putting differing | |
3307 | * types of snoopable memory together to avoid the prefetcher | |
4239ca77 | 3308 | * crossing memory domains and dying. |
42d6ab48 CW |
3309 | */ |
3310 | if (HAS_LLC(dev)) | |
3311 | return true; | |
3312 | ||
c6cfb325 | 3313 | if (!drm_mm_node_allocated(gtt_space)) |
42d6ab48 CW |
3314 | return true; |
3315 | ||
3316 | if (list_empty(>t_space->node_list)) | |
3317 | return true; | |
3318 | ||
3319 | other = list_entry(gtt_space->node_list.prev, struct drm_mm_node, node_list); | |
3320 | if (other->allocated && !other->hole_follows && other->color != cache_level) | |
3321 | return false; | |
3322 | ||
3323 | other = list_entry(gtt_space->node_list.next, struct drm_mm_node, node_list); | |
3324 | if (other->allocated && !gtt_space->hole_follows && other->color != cache_level) | |
3325 | return false; | |
3326 | ||
3327 | return true; | |
3328 | } | |
3329 | ||
3330 | static void i915_gem_verify_gtt(struct drm_device *dev) | |
3331 | { | |
3332 | #if WATCH_GTT | |
3333 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3334 | struct drm_i915_gem_object *obj; | |
3335 | int err = 0; | |
3336 | ||
35c20a60 | 3337 | list_for_each_entry(obj, &dev_priv->mm.gtt_list, global_list) { |
42d6ab48 CW |
3338 | if (obj->gtt_space == NULL) { |
3339 | printk(KERN_ERR "object found on GTT list with no space reserved\n"); | |
3340 | err++; | |
3341 | continue; | |
3342 | } | |
3343 | ||
3344 | if (obj->cache_level != obj->gtt_space->color) { | |
3345 | printk(KERN_ERR "object reserved space [%08lx, %08lx] with wrong color, cache_level=%x, color=%lx\n", | |
f343c5f6 BW |
3346 | i915_gem_obj_ggtt_offset(obj), |
3347 | i915_gem_obj_ggtt_offset(obj) + i915_gem_obj_ggtt_size(obj), | |
42d6ab48 CW |
3348 | obj->cache_level, |
3349 | obj->gtt_space->color); | |
3350 | err++; | |
3351 | continue; | |
3352 | } | |
3353 | ||
3354 | if (!i915_gem_valid_gtt_space(dev, | |
3355 | obj->gtt_space, | |
3356 | obj->cache_level)) { | |
3357 | printk(KERN_ERR "invalid GTT space found at [%08lx, %08lx] - color=%x\n", | |
f343c5f6 BW |
3358 | i915_gem_obj_ggtt_offset(obj), |
3359 | i915_gem_obj_ggtt_offset(obj) + i915_gem_obj_ggtt_size(obj), | |
42d6ab48 CW |
3360 | obj->cache_level); |
3361 | err++; | |
3362 | continue; | |
3363 | } | |
3364 | } | |
3365 | ||
3366 | WARN_ON(err); | |
3367 | #endif | |
3368 | } | |
3369 | ||
673a394b EA |
3370 | /** |
3371 | * Finds free space in the GTT aperture and binds the object there. | |
3372 | */ | |
262de145 | 3373 | static struct i915_vma * |
07fe0b12 BW |
3374 | i915_gem_object_bind_to_vm(struct drm_i915_gem_object *obj, |
3375 | struct i915_address_space *vm, | |
3376 | unsigned alignment, | |
d23db88c | 3377 | uint64_t flags) |
673a394b | 3378 | { |
05394f39 | 3379 | struct drm_device *dev = obj->base.dev; |
3e31c6c0 | 3380 | struct drm_i915_private *dev_priv = dev->dev_private; |
5e783301 | 3381 | u32 size, fence_size, fence_alignment, unfenced_alignment; |
d23db88c CW |
3382 | unsigned long start = |
3383 | flags & PIN_OFFSET_BIAS ? flags & PIN_OFFSET_MASK : 0; | |
3384 | unsigned long end = | |
1ec9e26d | 3385 | flags & PIN_MAPPABLE ? dev_priv->gtt.mappable_end : vm->total; |
2f633156 | 3386 | struct i915_vma *vma; |
07f73f69 | 3387 | int ret; |
673a394b | 3388 | |
e28f8711 CW |
3389 | fence_size = i915_gem_get_gtt_size(dev, |
3390 | obj->base.size, | |
3391 | obj->tiling_mode); | |
3392 | fence_alignment = i915_gem_get_gtt_alignment(dev, | |
3393 | obj->base.size, | |
d865110c | 3394 | obj->tiling_mode, true); |
e28f8711 | 3395 | unfenced_alignment = |
d865110c | 3396 | i915_gem_get_gtt_alignment(dev, |
1ec9e26d DV |
3397 | obj->base.size, |
3398 | obj->tiling_mode, false); | |
a00b10c3 | 3399 | |
673a394b | 3400 | if (alignment == 0) |
1ec9e26d | 3401 | alignment = flags & PIN_MAPPABLE ? fence_alignment : |
5e783301 | 3402 | unfenced_alignment; |
1ec9e26d | 3403 | if (flags & PIN_MAPPABLE && alignment & (fence_alignment - 1)) { |
bd9b6a4e | 3404 | DRM_DEBUG("Invalid object alignment requested %u\n", alignment); |
262de145 | 3405 | return ERR_PTR(-EINVAL); |
673a394b EA |
3406 | } |
3407 | ||
1ec9e26d | 3408 | size = flags & PIN_MAPPABLE ? fence_size : obj->base.size; |
a00b10c3 | 3409 | |
654fc607 CW |
3410 | /* If the object is bigger than the entire aperture, reject it early |
3411 | * before evicting everything in a vain attempt to find space. | |
3412 | */ | |
d23db88c CW |
3413 | if (obj->base.size > end) { |
3414 | DRM_DEBUG("Attempting to bind an object larger than the aperture: object=%zd > %s aperture=%lu\n", | |
a36689cb | 3415 | obj->base.size, |
1ec9e26d | 3416 | flags & PIN_MAPPABLE ? "mappable" : "total", |
d23db88c | 3417 | end); |
262de145 | 3418 | return ERR_PTR(-E2BIG); |
654fc607 CW |
3419 | } |
3420 | ||
37e680a1 | 3421 | ret = i915_gem_object_get_pages(obj); |
6c085a72 | 3422 | if (ret) |
262de145 | 3423 | return ERR_PTR(ret); |
6c085a72 | 3424 | |
fbdda6fb CW |
3425 | i915_gem_object_pin_pages(obj); |
3426 | ||
accfef2e | 3427 | vma = i915_gem_obj_lookup_or_create_vma(obj, vm); |
262de145 | 3428 | if (IS_ERR(vma)) |
bc6bc15b | 3429 | goto err_unpin; |
2f633156 | 3430 | |
0a9ae0d7 | 3431 | search_free: |
07fe0b12 | 3432 | ret = drm_mm_insert_node_in_range_generic(&vm->mm, &vma->node, |
0a9ae0d7 | 3433 | size, alignment, |
d23db88c CW |
3434 | obj->cache_level, |
3435 | start, end, | |
62347f9e LK |
3436 | DRM_MM_SEARCH_DEFAULT, |
3437 | DRM_MM_CREATE_DEFAULT); | |
dc9dd7a2 | 3438 | if (ret) { |
f6cd1f15 | 3439 | ret = i915_gem_evict_something(dev, vm, size, alignment, |
d23db88c CW |
3440 | obj->cache_level, |
3441 | start, end, | |
3442 | flags); | |
dc9dd7a2 CW |
3443 | if (ret == 0) |
3444 | goto search_free; | |
9731129c | 3445 | |
bc6bc15b | 3446 | goto err_free_vma; |
673a394b | 3447 | } |
2f633156 | 3448 | if (WARN_ON(!i915_gem_valid_gtt_space(dev, &vma->node, |
c6cfb325 | 3449 | obj->cache_level))) { |
2f633156 | 3450 | ret = -EINVAL; |
bc6bc15b | 3451 | goto err_remove_node; |
673a394b EA |
3452 | } |
3453 | ||
74163907 | 3454 | ret = i915_gem_gtt_prepare_object(obj); |
2f633156 | 3455 | if (ret) |
bc6bc15b | 3456 | goto err_remove_node; |
673a394b | 3457 | |
35c20a60 | 3458 | list_move_tail(&obj->global_list, &dev_priv->mm.bound_list); |
ca191b13 | 3459 | list_add_tail(&vma->mm_list, &vm->inactive_list); |
bf1a1092 | 3460 | |
4bd561b3 BW |
3461 | if (i915_is_ggtt(vm)) { |
3462 | bool mappable, fenceable; | |
a00b10c3 | 3463 | |
49987099 DV |
3464 | fenceable = (vma->node.size == fence_size && |
3465 | (vma->node.start & (fence_alignment - 1)) == 0); | |
4bd561b3 | 3466 | |
49987099 DV |
3467 | mappable = (vma->node.start + obj->base.size <= |
3468 | dev_priv->gtt.mappable_end); | |
a00b10c3 | 3469 | |
5cacaac7 | 3470 | obj->map_and_fenceable = mappable && fenceable; |
4bd561b3 | 3471 | } |
75e9e915 | 3472 | |
1ec9e26d | 3473 | WARN_ON(flags & PIN_MAPPABLE && !obj->map_and_fenceable); |
75e9e915 | 3474 | |
1ec9e26d | 3475 | trace_i915_vma_bind(vma, flags); |
8ea99c92 DV |
3476 | vma->bind_vma(vma, obj->cache_level, |
3477 | flags & (PIN_MAPPABLE | PIN_GLOBAL) ? GLOBAL_BIND : 0); | |
3478 | ||
42d6ab48 | 3479 | i915_gem_verify_gtt(dev); |
262de145 | 3480 | return vma; |
2f633156 | 3481 | |
bc6bc15b | 3482 | err_remove_node: |
6286ef9b | 3483 | drm_mm_remove_node(&vma->node); |
bc6bc15b | 3484 | err_free_vma: |
2f633156 | 3485 | i915_gem_vma_destroy(vma); |
262de145 | 3486 | vma = ERR_PTR(ret); |
bc6bc15b | 3487 | err_unpin: |
2f633156 | 3488 | i915_gem_object_unpin_pages(obj); |
262de145 | 3489 | return vma; |
673a394b EA |
3490 | } |
3491 | ||
000433b6 | 3492 | bool |
2c22569b CW |
3493 | i915_gem_clflush_object(struct drm_i915_gem_object *obj, |
3494 | bool force) | |
673a394b | 3495 | { |
673a394b EA |
3496 | /* If we don't have a page list set up, then we're not pinned |
3497 | * to GPU, and we can ignore the cache flush because it'll happen | |
3498 | * again at bind time. | |
3499 | */ | |
05394f39 | 3500 | if (obj->pages == NULL) |
000433b6 | 3501 | return false; |
673a394b | 3502 | |
769ce464 ID |
3503 | /* |
3504 | * Stolen memory is always coherent with the GPU as it is explicitly | |
3505 | * marked as wc by the system, or the system is cache-coherent. | |
3506 | */ | |
3507 | if (obj->stolen) | |
000433b6 | 3508 | return false; |
769ce464 | 3509 | |
9c23f7fc CW |
3510 | /* If the GPU is snooping the contents of the CPU cache, |
3511 | * we do not need to manually clear the CPU cache lines. However, | |
3512 | * the caches are only snooped when the render cache is | |
3513 | * flushed/invalidated. As we always have to emit invalidations | |
3514 | * and flushes when moving into and out of the RENDER domain, correct | |
3515 | * snooping behaviour occurs naturally as the result of our domain | |
3516 | * tracking. | |
3517 | */ | |
2c22569b | 3518 | if (!force && cpu_cache_is_coherent(obj->base.dev, obj->cache_level)) |
000433b6 | 3519 | return false; |
9c23f7fc | 3520 | |
1c5d22f7 | 3521 | trace_i915_gem_object_clflush(obj); |
9da3da66 | 3522 | drm_clflush_sg(obj->pages); |
000433b6 CW |
3523 | |
3524 | return true; | |
e47c68e9 EA |
3525 | } |
3526 | ||
3527 | /** Flushes the GTT write domain for the object if it's dirty. */ | |
3528 | static void | |
05394f39 | 3529 | i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj) |
e47c68e9 | 3530 | { |
1c5d22f7 CW |
3531 | uint32_t old_write_domain; |
3532 | ||
05394f39 | 3533 | if (obj->base.write_domain != I915_GEM_DOMAIN_GTT) |
e47c68e9 EA |
3534 | return; |
3535 | ||
63256ec5 | 3536 | /* No actual flushing is required for the GTT write domain. Writes |
e47c68e9 EA |
3537 | * to it immediately go to main memory as far as we know, so there's |
3538 | * no chipset flush. It also doesn't land in render cache. | |
63256ec5 CW |
3539 | * |
3540 | * However, we do have to enforce the order so that all writes through | |
3541 | * the GTT land before any writes to the device, such as updates to | |
3542 | * the GATT itself. | |
e47c68e9 | 3543 | */ |
63256ec5 CW |
3544 | wmb(); |
3545 | ||
05394f39 CW |
3546 | old_write_domain = obj->base.write_domain; |
3547 | obj->base.write_domain = 0; | |
1c5d22f7 CW |
3548 | |
3549 | trace_i915_gem_object_change_domain(obj, | |
05394f39 | 3550 | obj->base.read_domains, |
1c5d22f7 | 3551 | old_write_domain); |
e47c68e9 EA |
3552 | } |
3553 | ||
3554 | /** Flushes the CPU write domain for the object if it's dirty. */ | |
3555 | static void | |
2c22569b CW |
3556 | i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj, |
3557 | bool force) | |
e47c68e9 | 3558 | { |
1c5d22f7 | 3559 | uint32_t old_write_domain; |
e47c68e9 | 3560 | |
05394f39 | 3561 | if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) |
e47c68e9 EA |
3562 | return; |
3563 | ||
000433b6 CW |
3564 | if (i915_gem_clflush_object(obj, force)) |
3565 | i915_gem_chipset_flush(obj->base.dev); | |
3566 | ||
05394f39 CW |
3567 | old_write_domain = obj->base.write_domain; |
3568 | obj->base.write_domain = 0; | |
1c5d22f7 CW |
3569 | |
3570 | trace_i915_gem_object_change_domain(obj, | |
05394f39 | 3571 | obj->base.read_domains, |
1c5d22f7 | 3572 | old_write_domain); |
e47c68e9 EA |
3573 | } |
3574 | ||
2ef7eeaa EA |
3575 | /** |
3576 | * Moves a single object to the GTT read, and possibly write domain. | |
3577 | * | |
3578 | * This function returns when the move is complete, including waiting on | |
3579 | * flushes to occur. | |
3580 | */ | |
79e53945 | 3581 | int |
2021746e | 3582 | i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write) |
2ef7eeaa | 3583 | { |
3e31c6c0 | 3584 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
1c5d22f7 | 3585 | uint32_t old_write_domain, old_read_domains; |
e47c68e9 | 3586 | int ret; |
2ef7eeaa | 3587 | |
02354392 | 3588 | /* Not valid to be called on unbound objects. */ |
9843877d | 3589 | if (!i915_gem_obj_bound_any(obj)) |
02354392 EA |
3590 | return -EINVAL; |
3591 | ||
8d7e3de1 CW |
3592 | if (obj->base.write_domain == I915_GEM_DOMAIN_GTT) |
3593 | return 0; | |
3594 | ||
0201f1ec | 3595 | ret = i915_gem_object_wait_rendering(obj, !write); |
88241785 CW |
3596 | if (ret) |
3597 | return ret; | |
3598 | ||
c8725f3d | 3599 | i915_gem_object_retire(obj); |
2c22569b | 3600 | i915_gem_object_flush_cpu_write_domain(obj, false); |
1c5d22f7 | 3601 | |
d0a57789 CW |
3602 | /* Serialise direct access to this object with the barriers for |
3603 | * coherent writes from the GPU, by effectively invalidating the | |
3604 | * GTT domain upon first access. | |
3605 | */ | |
3606 | if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0) | |
3607 | mb(); | |
3608 | ||
05394f39 CW |
3609 | old_write_domain = obj->base.write_domain; |
3610 | old_read_domains = obj->base.read_domains; | |
1c5d22f7 | 3611 | |
e47c68e9 EA |
3612 | /* It should now be out of any other write domains, and we can update |
3613 | * the domain values for our changes. | |
3614 | */ | |
05394f39 CW |
3615 | BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_GTT) != 0); |
3616 | obj->base.read_domains |= I915_GEM_DOMAIN_GTT; | |
e47c68e9 | 3617 | if (write) { |
05394f39 CW |
3618 | obj->base.read_domains = I915_GEM_DOMAIN_GTT; |
3619 | obj->base.write_domain = I915_GEM_DOMAIN_GTT; | |
3620 | obj->dirty = 1; | |
2ef7eeaa EA |
3621 | } |
3622 | ||
1c5d22f7 CW |
3623 | trace_i915_gem_object_change_domain(obj, |
3624 | old_read_domains, | |
3625 | old_write_domain); | |
3626 | ||
8325a09d | 3627 | /* And bump the LRU for this access */ |
ca191b13 | 3628 | if (i915_gem_object_is_inactive(obj)) { |
5c2abbea | 3629 | struct i915_vma *vma = i915_gem_obj_to_ggtt(obj); |
ca191b13 BW |
3630 | if (vma) |
3631 | list_move_tail(&vma->mm_list, | |
3632 | &dev_priv->gtt.base.inactive_list); | |
3633 | ||
3634 | } | |
8325a09d | 3635 | |
e47c68e9 EA |
3636 | return 0; |
3637 | } | |
3638 | ||
e4ffd173 CW |
3639 | int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj, |
3640 | enum i915_cache_level cache_level) | |
3641 | { | |
7bddb01f | 3642 | struct drm_device *dev = obj->base.dev; |
df6f783a | 3643 | struct i915_vma *vma, *next; |
e4ffd173 CW |
3644 | int ret; |
3645 | ||
3646 | if (obj->cache_level == cache_level) | |
3647 | return 0; | |
3648 | ||
d7f46fc4 | 3649 | if (i915_gem_obj_is_pinned(obj)) { |
e4ffd173 CW |
3650 | DRM_DEBUG("can not change the cache level of pinned objects\n"); |
3651 | return -EBUSY; | |
3652 | } | |
3653 | ||
df6f783a | 3654 | list_for_each_entry_safe(vma, next, &obj->vma_list, vma_link) { |
3089c6f2 | 3655 | if (!i915_gem_valid_gtt_space(dev, &vma->node, cache_level)) { |
07fe0b12 | 3656 | ret = i915_vma_unbind(vma); |
3089c6f2 BW |
3657 | if (ret) |
3658 | return ret; | |
3089c6f2 | 3659 | } |
42d6ab48 CW |
3660 | } |
3661 | ||
3089c6f2 | 3662 | if (i915_gem_obj_bound_any(obj)) { |
e4ffd173 CW |
3663 | ret = i915_gem_object_finish_gpu(obj); |
3664 | if (ret) | |
3665 | return ret; | |
3666 | ||
3667 | i915_gem_object_finish_gtt(obj); | |
3668 | ||
3669 | /* Before SandyBridge, you could not use tiling or fence | |
3670 | * registers with snooped memory, so relinquish any fences | |
3671 | * currently pointing to our region in the aperture. | |
3672 | */ | |
42d6ab48 | 3673 | if (INTEL_INFO(dev)->gen < 6) { |
e4ffd173 CW |
3674 | ret = i915_gem_object_put_fence(obj); |
3675 | if (ret) | |
3676 | return ret; | |
3677 | } | |
3678 | ||
6f65e29a | 3679 | list_for_each_entry(vma, &obj->vma_list, vma_link) |
8ea99c92 DV |
3680 | if (drm_mm_node_allocated(&vma->node)) |
3681 | vma->bind_vma(vma, cache_level, | |
3682 | obj->has_global_gtt_mapping ? GLOBAL_BIND : 0); | |
e4ffd173 CW |
3683 | } |
3684 | ||
2c22569b CW |
3685 | list_for_each_entry(vma, &obj->vma_list, vma_link) |
3686 | vma->node.color = cache_level; | |
3687 | obj->cache_level = cache_level; | |
3688 | ||
3689 | if (cpu_write_needs_clflush(obj)) { | |
e4ffd173 CW |
3690 | u32 old_read_domains, old_write_domain; |
3691 | ||
3692 | /* If we're coming from LLC cached, then we haven't | |
3693 | * actually been tracking whether the data is in the | |
3694 | * CPU cache or not, since we only allow one bit set | |
3695 | * in obj->write_domain and have been skipping the clflushes. | |
3696 | * Just set it to the CPU cache for now. | |
3697 | */ | |
c8725f3d | 3698 | i915_gem_object_retire(obj); |
e4ffd173 | 3699 | WARN_ON(obj->base.write_domain & ~I915_GEM_DOMAIN_CPU); |
e4ffd173 CW |
3700 | |
3701 | old_read_domains = obj->base.read_domains; | |
3702 | old_write_domain = obj->base.write_domain; | |
3703 | ||
3704 | obj->base.read_domains = I915_GEM_DOMAIN_CPU; | |
3705 | obj->base.write_domain = I915_GEM_DOMAIN_CPU; | |
3706 | ||
3707 | trace_i915_gem_object_change_domain(obj, | |
3708 | old_read_domains, | |
3709 | old_write_domain); | |
3710 | } | |
3711 | ||
42d6ab48 | 3712 | i915_gem_verify_gtt(dev); |
e4ffd173 CW |
3713 | return 0; |
3714 | } | |
3715 | ||
199adf40 BW |
3716 | int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data, |
3717 | struct drm_file *file) | |
e6994aee | 3718 | { |
199adf40 | 3719 | struct drm_i915_gem_caching *args = data; |
e6994aee CW |
3720 | struct drm_i915_gem_object *obj; |
3721 | int ret; | |
3722 | ||
3723 | ret = i915_mutex_lock_interruptible(dev); | |
3724 | if (ret) | |
3725 | return ret; | |
3726 | ||
3727 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); | |
3728 | if (&obj->base == NULL) { | |
3729 | ret = -ENOENT; | |
3730 | goto unlock; | |
3731 | } | |
3732 | ||
651d794f CW |
3733 | switch (obj->cache_level) { |
3734 | case I915_CACHE_LLC: | |
3735 | case I915_CACHE_L3_LLC: | |
3736 | args->caching = I915_CACHING_CACHED; | |
3737 | break; | |
3738 | ||
4257d3ba CW |
3739 | case I915_CACHE_WT: |
3740 | args->caching = I915_CACHING_DISPLAY; | |
3741 | break; | |
3742 | ||
651d794f CW |
3743 | default: |
3744 | args->caching = I915_CACHING_NONE; | |
3745 | break; | |
3746 | } | |
e6994aee CW |
3747 | |
3748 | drm_gem_object_unreference(&obj->base); | |
3749 | unlock: | |
3750 | mutex_unlock(&dev->struct_mutex); | |
3751 | return ret; | |
3752 | } | |
3753 | ||
199adf40 BW |
3754 | int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data, |
3755 | struct drm_file *file) | |
e6994aee | 3756 | { |
199adf40 | 3757 | struct drm_i915_gem_caching *args = data; |
e6994aee CW |
3758 | struct drm_i915_gem_object *obj; |
3759 | enum i915_cache_level level; | |
3760 | int ret; | |
3761 | ||
199adf40 BW |
3762 | switch (args->caching) { |
3763 | case I915_CACHING_NONE: | |
e6994aee CW |
3764 | level = I915_CACHE_NONE; |
3765 | break; | |
199adf40 | 3766 | case I915_CACHING_CACHED: |
e6994aee CW |
3767 | level = I915_CACHE_LLC; |
3768 | break; | |
4257d3ba CW |
3769 | case I915_CACHING_DISPLAY: |
3770 | level = HAS_WT(dev) ? I915_CACHE_WT : I915_CACHE_NONE; | |
3771 | break; | |
e6994aee CW |
3772 | default: |
3773 | return -EINVAL; | |
3774 | } | |
3775 | ||
3bc2913e BW |
3776 | ret = i915_mutex_lock_interruptible(dev); |
3777 | if (ret) | |
3778 | return ret; | |
3779 | ||
e6994aee CW |
3780 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
3781 | if (&obj->base == NULL) { | |
3782 | ret = -ENOENT; | |
3783 | goto unlock; | |
3784 | } | |
3785 | ||
3786 | ret = i915_gem_object_set_cache_level(obj, level); | |
3787 | ||
3788 | drm_gem_object_unreference(&obj->base); | |
3789 | unlock: | |
3790 | mutex_unlock(&dev->struct_mutex); | |
3791 | return ret; | |
3792 | } | |
3793 | ||
cc98b413 CW |
3794 | static bool is_pin_display(struct drm_i915_gem_object *obj) |
3795 | { | |
19656430 OM |
3796 | struct i915_vma *vma; |
3797 | ||
3798 | if (list_empty(&obj->vma_list)) | |
3799 | return false; | |
3800 | ||
3801 | vma = i915_gem_obj_to_ggtt(obj); | |
3802 | if (!vma) | |
3803 | return false; | |
3804 | ||
cc98b413 CW |
3805 | /* There are 3 sources that pin objects: |
3806 | * 1. The display engine (scanouts, sprites, cursors); | |
3807 | * 2. Reservations for execbuffer; | |
3808 | * 3. The user. | |
3809 | * | |
3810 | * We can ignore reservations as we hold the struct_mutex and | |
3811 | * are only called outside of the reservation path. The user | |
3812 | * can only increment pin_count once, and so if after | |
3813 | * subtracting the potential reference by the user, any pin_count | |
3814 | * remains, it must be due to another use by the display engine. | |
3815 | */ | |
19656430 | 3816 | return vma->pin_count - !!obj->user_pin_count; |
cc98b413 CW |
3817 | } |
3818 | ||
b9241ea3 | 3819 | /* |
2da3b9b9 CW |
3820 | * Prepare buffer for display plane (scanout, cursors, etc). |
3821 | * Can be called from an uninterruptible phase (modesetting) and allows | |
3822 | * any flushes to be pipelined (for pageflips). | |
b9241ea3 ZW |
3823 | */ |
3824 | int | |
2da3b9b9 CW |
3825 | i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj, |
3826 | u32 alignment, | |
a4872ba6 | 3827 | struct intel_engine_cs *pipelined) |
b9241ea3 | 3828 | { |
2da3b9b9 | 3829 | u32 old_read_domains, old_write_domain; |
19656430 | 3830 | bool was_pin_display; |
b9241ea3 ZW |
3831 | int ret; |
3832 | ||
0be73284 | 3833 | if (pipelined != obj->ring) { |
2911a35b BW |
3834 | ret = i915_gem_object_sync(obj, pipelined); |
3835 | if (ret) | |
b9241ea3 ZW |
3836 | return ret; |
3837 | } | |
3838 | ||
cc98b413 CW |
3839 | /* Mark the pin_display early so that we account for the |
3840 | * display coherency whilst setting up the cache domains. | |
3841 | */ | |
19656430 | 3842 | was_pin_display = obj->pin_display; |
cc98b413 CW |
3843 | obj->pin_display = true; |
3844 | ||
a7ef0640 EA |
3845 | /* The display engine is not coherent with the LLC cache on gen6. As |
3846 | * a result, we make sure that the pinning that is about to occur is | |
3847 | * done with uncached PTEs. This is lowest common denominator for all | |
3848 | * chipsets. | |
3849 | * | |
3850 | * However for gen6+, we could do better by using the GFDT bit instead | |
3851 | * of uncaching, which would allow us to flush all the LLC-cached data | |
3852 | * with that bit in the PTE to main memory with just one PIPE_CONTROL. | |
3853 | */ | |
651d794f CW |
3854 | ret = i915_gem_object_set_cache_level(obj, |
3855 | HAS_WT(obj->base.dev) ? I915_CACHE_WT : I915_CACHE_NONE); | |
a7ef0640 | 3856 | if (ret) |
cc98b413 | 3857 | goto err_unpin_display; |
a7ef0640 | 3858 | |
2da3b9b9 CW |
3859 | /* As the user may map the buffer once pinned in the display plane |
3860 | * (e.g. libkms for the bootup splash), we have to ensure that we | |
3861 | * always use map_and_fenceable for all scanout buffers. | |
3862 | */ | |
1ec9e26d | 3863 | ret = i915_gem_obj_ggtt_pin(obj, alignment, PIN_MAPPABLE); |
2da3b9b9 | 3864 | if (ret) |
cc98b413 | 3865 | goto err_unpin_display; |
2da3b9b9 | 3866 | |
2c22569b | 3867 | i915_gem_object_flush_cpu_write_domain(obj, true); |
b118c1e3 | 3868 | |
2da3b9b9 | 3869 | old_write_domain = obj->base.write_domain; |
05394f39 | 3870 | old_read_domains = obj->base.read_domains; |
2da3b9b9 CW |
3871 | |
3872 | /* It should now be out of any other write domains, and we can update | |
3873 | * the domain values for our changes. | |
3874 | */ | |
e5f1d962 | 3875 | obj->base.write_domain = 0; |
05394f39 | 3876 | obj->base.read_domains |= I915_GEM_DOMAIN_GTT; |
b9241ea3 ZW |
3877 | |
3878 | trace_i915_gem_object_change_domain(obj, | |
3879 | old_read_domains, | |
2da3b9b9 | 3880 | old_write_domain); |
b9241ea3 ZW |
3881 | |
3882 | return 0; | |
cc98b413 CW |
3883 | |
3884 | err_unpin_display: | |
19656430 OM |
3885 | WARN_ON(was_pin_display != is_pin_display(obj)); |
3886 | obj->pin_display = was_pin_display; | |
cc98b413 CW |
3887 | return ret; |
3888 | } | |
3889 | ||
3890 | void | |
3891 | i915_gem_object_unpin_from_display_plane(struct drm_i915_gem_object *obj) | |
3892 | { | |
d7f46fc4 | 3893 | i915_gem_object_ggtt_unpin(obj); |
cc98b413 | 3894 | obj->pin_display = is_pin_display(obj); |
b9241ea3 ZW |
3895 | } |
3896 | ||
85345517 | 3897 | int |
a8198eea | 3898 | i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj) |
85345517 | 3899 | { |
88241785 CW |
3900 | int ret; |
3901 | ||
a8198eea | 3902 | if ((obj->base.read_domains & I915_GEM_GPU_DOMAINS) == 0) |
85345517 CW |
3903 | return 0; |
3904 | ||
0201f1ec | 3905 | ret = i915_gem_object_wait_rendering(obj, false); |
c501ae7f CW |
3906 | if (ret) |
3907 | return ret; | |
3908 | ||
a8198eea CW |
3909 | /* Ensure that we invalidate the GPU's caches and TLBs. */ |
3910 | obj->base.read_domains &= ~I915_GEM_GPU_DOMAINS; | |
c501ae7f | 3911 | return 0; |
85345517 CW |
3912 | } |
3913 | ||
e47c68e9 EA |
3914 | /** |
3915 | * Moves a single object to the CPU read, and possibly write domain. | |
3916 | * | |
3917 | * This function returns when the move is complete, including waiting on | |
3918 | * flushes to occur. | |
3919 | */ | |
dabdfe02 | 3920 | int |
919926ae | 3921 | i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write) |
e47c68e9 | 3922 | { |
1c5d22f7 | 3923 | uint32_t old_write_domain, old_read_domains; |
e47c68e9 EA |
3924 | int ret; |
3925 | ||
8d7e3de1 CW |
3926 | if (obj->base.write_domain == I915_GEM_DOMAIN_CPU) |
3927 | return 0; | |
3928 | ||
0201f1ec | 3929 | ret = i915_gem_object_wait_rendering(obj, !write); |
88241785 CW |
3930 | if (ret) |
3931 | return ret; | |
3932 | ||
c8725f3d | 3933 | i915_gem_object_retire(obj); |
e47c68e9 | 3934 | i915_gem_object_flush_gtt_write_domain(obj); |
2ef7eeaa | 3935 | |
05394f39 CW |
3936 | old_write_domain = obj->base.write_domain; |
3937 | old_read_domains = obj->base.read_domains; | |
1c5d22f7 | 3938 | |
e47c68e9 | 3939 | /* Flush the CPU cache if it's still invalid. */ |
05394f39 | 3940 | if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0) { |
2c22569b | 3941 | i915_gem_clflush_object(obj, false); |
2ef7eeaa | 3942 | |
05394f39 | 3943 | obj->base.read_domains |= I915_GEM_DOMAIN_CPU; |
2ef7eeaa EA |
3944 | } |
3945 | ||
3946 | /* It should now be out of any other write domains, and we can update | |
3947 | * the domain values for our changes. | |
3948 | */ | |
05394f39 | 3949 | BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_CPU) != 0); |
e47c68e9 EA |
3950 | |
3951 | /* If we're writing through the CPU, then the GPU read domains will | |
3952 | * need to be invalidated at next use. | |
3953 | */ | |
3954 | if (write) { | |
05394f39 CW |
3955 | obj->base.read_domains = I915_GEM_DOMAIN_CPU; |
3956 | obj->base.write_domain = I915_GEM_DOMAIN_CPU; | |
e47c68e9 | 3957 | } |
2ef7eeaa | 3958 | |
1c5d22f7 CW |
3959 | trace_i915_gem_object_change_domain(obj, |
3960 | old_read_domains, | |
3961 | old_write_domain); | |
3962 | ||
2ef7eeaa EA |
3963 | return 0; |
3964 | } | |
3965 | ||
673a394b EA |
3966 | /* Throttle our rendering by waiting until the ring has completed our requests |
3967 | * emitted over 20 msec ago. | |
3968 | * | |
b962442e EA |
3969 | * Note that if we were to use the current jiffies each time around the loop, |
3970 | * we wouldn't escape the function with any frames outstanding if the time to | |
3971 | * render a frame was over 20ms. | |
3972 | * | |
673a394b EA |
3973 | * This should get us reasonable parallelism between CPU and GPU but also |
3974 | * relatively low latency when blocking on a particular request to finish. | |
3975 | */ | |
40a5f0de | 3976 | static int |
f787a5f5 | 3977 | i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file) |
40a5f0de | 3978 | { |
f787a5f5 CW |
3979 | struct drm_i915_private *dev_priv = dev->dev_private; |
3980 | struct drm_i915_file_private *file_priv = file->driver_priv; | |
b962442e | 3981 | unsigned long recent_enough = jiffies - msecs_to_jiffies(20); |
f787a5f5 | 3982 | struct drm_i915_gem_request *request; |
a4872ba6 | 3983 | struct intel_engine_cs *ring = NULL; |
f69061be | 3984 | unsigned reset_counter; |
f787a5f5 CW |
3985 | u32 seqno = 0; |
3986 | int ret; | |
93533c29 | 3987 | |
308887aa DV |
3988 | ret = i915_gem_wait_for_error(&dev_priv->gpu_error); |
3989 | if (ret) | |
3990 | return ret; | |
3991 | ||
3992 | ret = i915_gem_check_wedge(&dev_priv->gpu_error, false); | |
3993 | if (ret) | |
3994 | return ret; | |
e110e8d6 | 3995 | |
1c25595f | 3996 | spin_lock(&file_priv->mm.lock); |
f787a5f5 | 3997 | list_for_each_entry(request, &file_priv->mm.request_list, client_list) { |
b962442e EA |
3998 | if (time_after_eq(request->emitted_jiffies, recent_enough)) |
3999 | break; | |
40a5f0de | 4000 | |
f787a5f5 CW |
4001 | ring = request->ring; |
4002 | seqno = request->seqno; | |
b962442e | 4003 | } |
f69061be | 4004 | reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter); |
1c25595f | 4005 | spin_unlock(&file_priv->mm.lock); |
40a5f0de | 4006 | |
f787a5f5 CW |
4007 | if (seqno == 0) |
4008 | return 0; | |
2bc43b5c | 4009 | |
b29c19b6 | 4010 | ret = __wait_seqno(ring, seqno, reset_counter, true, NULL, NULL); |
f787a5f5 CW |
4011 | if (ret == 0) |
4012 | queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, 0); | |
40a5f0de EA |
4013 | |
4014 | return ret; | |
4015 | } | |
4016 | ||
d23db88c CW |
4017 | static bool |
4018 | i915_vma_misplaced(struct i915_vma *vma, uint32_t alignment, uint64_t flags) | |
4019 | { | |
4020 | struct drm_i915_gem_object *obj = vma->obj; | |
4021 | ||
4022 | if (alignment && | |
4023 | vma->node.start & (alignment - 1)) | |
4024 | return true; | |
4025 | ||
4026 | if (flags & PIN_MAPPABLE && !obj->map_and_fenceable) | |
4027 | return true; | |
4028 | ||
4029 | if (flags & PIN_OFFSET_BIAS && | |
4030 | vma->node.start < (flags & PIN_OFFSET_MASK)) | |
4031 | return true; | |
4032 | ||
4033 | return false; | |
4034 | } | |
4035 | ||
673a394b | 4036 | int |
05394f39 | 4037 | i915_gem_object_pin(struct drm_i915_gem_object *obj, |
c37e2204 | 4038 | struct i915_address_space *vm, |
05394f39 | 4039 | uint32_t alignment, |
d23db88c | 4040 | uint64_t flags) |
673a394b | 4041 | { |
6e7186af | 4042 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
07fe0b12 | 4043 | struct i915_vma *vma; |
673a394b EA |
4044 | int ret; |
4045 | ||
6e7186af BW |
4046 | if (WARN_ON(vm == &dev_priv->mm.aliasing_ppgtt->base)) |
4047 | return -ENODEV; | |
4048 | ||
bf3d149b | 4049 | if (WARN_ON(flags & (PIN_GLOBAL | PIN_MAPPABLE) && !i915_is_ggtt(vm))) |
1ec9e26d | 4050 | return -EINVAL; |
07fe0b12 BW |
4051 | |
4052 | vma = i915_gem_obj_to_vma(obj, vm); | |
07fe0b12 | 4053 | if (vma) { |
d7f46fc4 BW |
4054 | if (WARN_ON(vma->pin_count == DRM_I915_GEM_OBJECT_MAX_PIN_COUNT)) |
4055 | return -EBUSY; | |
4056 | ||
d23db88c | 4057 | if (i915_vma_misplaced(vma, alignment, flags)) { |
d7f46fc4 | 4058 | WARN(vma->pin_count, |
ae7d49d8 | 4059 | "bo is already pinned with incorrect alignment:" |
f343c5f6 | 4060 | " offset=%lx, req.alignment=%x, req.map_and_fenceable=%d," |
75e9e915 | 4061 | " obj->map_and_fenceable=%d\n", |
07fe0b12 | 4062 | i915_gem_obj_offset(obj, vm), alignment, |
d23db88c | 4063 | !!(flags & PIN_MAPPABLE), |
05394f39 | 4064 | obj->map_and_fenceable); |
07fe0b12 | 4065 | ret = i915_vma_unbind(vma); |
ac0c6b5a CW |
4066 | if (ret) |
4067 | return ret; | |
8ea99c92 DV |
4068 | |
4069 | vma = NULL; | |
ac0c6b5a CW |
4070 | } |
4071 | } | |
4072 | ||
8ea99c92 | 4073 | if (vma == NULL || !drm_mm_node_allocated(&vma->node)) { |
262de145 DV |
4074 | vma = i915_gem_object_bind_to_vm(obj, vm, alignment, flags); |
4075 | if (IS_ERR(vma)) | |
4076 | return PTR_ERR(vma); | |
22c344e9 | 4077 | } |
76446cac | 4078 | |
8ea99c92 DV |
4079 | if (flags & PIN_GLOBAL && !obj->has_global_gtt_mapping) |
4080 | vma->bind_vma(vma, obj->cache_level, GLOBAL_BIND); | |
74898d7e | 4081 | |
8ea99c92 | 4082 | vma->pin_count++; |
1ec9e26d DV |
4083 | if (flags & PIN_MAPPABLE) |
4084 | obj->pin_mappable |= true; | |
673a394b EA |
4085 | |
4086 | return 0; | |
4087 | } | |
4088 | ||
4089 | void | |
d7f46fc4 | 4090 | i915_gem_object_ggtt_unpin(struct drm_i915_gem_object *obj) |
673a394b | 4091 | { |
d7f46fc4 | 4092 | struct i915_vma *vma = i915_gem_obj_to_ggtt(obj); |
673a394b | 4093 | |
d7f46fc4 BW |
4094 | BUG_ON(!vma); |
4095 | BUG_ON(vma->pin_count == 0); | |
4096 | BUG_ON(!i915_gem_obj_ggtt_bound(obj)); | |
4097 | ||
4098 | if (--vma->pin_count == 0) | |
6299f992 | 4099 | obj->pin_mappable = false; |
673a394b EA |
4100 | } |
4101 | ||
d8ffa60b DV |
4102 | bool |
4103 | i915_gem_object_pin_fence(struct drm_i915_gem_object *obj) | |
4104 | { | |
4105 | if (obj->fence_reg != I915_FENCE_REG_NONE) { | |
4106 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; | |
4107 | struct i915_vma *ggtt_vma = i915_gem_obj_to_ggtt(obj); | |
4108 | ||
4109 | WARN_ON(!ggtt_vma || | |
4110 | dev_priv->fence_regs[obj->fence_reg].pin_count > | |
4111 | ggtt_vma->pin_count); | |
4112 | dev_priv->fence_regs[obj->fence_reg].pin_count++; | |
4113 | return true; | |
4114 | } else | |
4115 | return false; | |
4116 | } | |
4117 | ||
4118 | void | |
4119 | i915_gem_object_unpin_fence(struct drm_i915_gem_object *obj) | |
4120 | { | |
4121 | if (obj->fence_reg != I915_FENCE_REG_NONE) { | |
4122 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; | |
4123 | WARN_ON(dev_priv->fence_regs[obj->fence_reg].pin_count <= 0); | |
4124 | dev_priv->fence_regs[obj->fence_reg].pin_count--; | |
4125 | } | |
4126 | } | |
4127 | ||
673a394b EA |
4128 | int |
4129 | i915_gem_pin_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 4130 | struct drm_file *file) |
673a394b EA |
4131 | { |
4132 | struct drm_i915_gem_pin *args = data; | |
05394f39 | 4133 | struct drm_i915_gem_object *obj; |
673a394b EA |
4134 | int ret; |
4135 | ||
02f6bccc DV |
4136 | if (INTEL_INFO(dev)->gen >= 6) |
4137 | return -ENODEV; | |
4138 | ||
1d7cfea1 CW |
4139 | ret = i915_mutex_lock_interruptible(dev); |
4140 | if (ret) | |
4141 | return ret; | |
673a394b | 4142 | |
05394f39 | 4143 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 4144 | if (&obj->base == NULL) { |
1d7cfea1 CW |
4145 | ret = -ENOENT; |
4146 | goto unlock; | |
673a394b | 4147 | } |
673a394b | 4148 | |
05394f39 | 4149 | if (obj->madv != I915_MADV_WILLNEED) { |
bd9b6a4e | 4150 | DRM_DEBUG("Attempting to pin a purgeable buffer\n"); |
8c99e57d | 4151 | ret = -EFAULT; |
1d7cfea1 | 4152 | goto out; |
3ef94daa CW |
4153 | } |
4154 | ||
05394f39 | 4155 | if (obj->pin_filp != NULL && obj->pin_filp != file) { |
bd9b6a4e | 4156 | DRM_DEBUG("Already pinned in i915_gem_pin_ioctl(): %d\n", |
79e53945 | 4157 | args->handle); |
1d7cfea1 CW |
4158 | ret = -EINVAL; |
4159 | goto out; | |
79e53945 JB |
4160 | } |
4161 | ||
aa5f8021 DV |
4162 | if (obj->user_pin_count == ULONG_MAX) { |
4163 | ret = -EBUSY; | |
4164 | goto out; | |
4165 | } | |
4166 | ||
93be8788 | 4167 | if (obj->user_pin_count == 0) { |
1ec9e26d | 4168 | ret = i915_gem_obj_ggtt_pin(obj, args->alignment, PIN_MAPPABLE); |
1d7cfea1 CW |
4169 | if (ret) |
4170 | goto out; | |
673a394b EA |
4171 | } |
4172 | ||
93be8788 CW |
4173 | obj->user_pin_count++; |
4174 | obj->pin_filp = file; | |
4175 | ||
f343c5f6 | 4176 | args->offset = i915_gem_obj_ggtt_offset(obj); |
1d7cfea1 | 4177 | out: |
05394f39 | 4178 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 4179 | unlock: |
673a394b | 4180 | mutex_unlock(&dev->struct_mutex); |
1d7cfea1 | 4181 | return ret; |
673a394b EA |
4182 | } |
4183 | ||
4184 | int | |
4185 | i915_gem_unpin_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 4186 | struct drm_file *file) |
673a394b EA |
4187 | { |
4188 | struct drm_i915_gem_pin *args = data; | |
05394f39 | 4189 | struct drm_i915_gem_object *obj; |
76c1dec1 | 4190 | int ret; |
673a394b | 4191 | |
1d7cfea1 CW |
4192 | ret = i915_mutex_lock_interruptible(dev); |
4193 | if (ret) | |
4194 | return ret; | |
673a394b | 4195 | |
05394f39 | 4196 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 4197 | if (&obj->base == NULL) { |
1d7cfea1 CW |
4198 | ret = -ENOENT; |
4199 | goto unlock; | |
673a394b | 4200 | } |
76c1dec1 | 4201 | |
05394f39 | 4202 | if (obj->pin_filp != file) { |
bd9b6a4e | 4203 | DRM_DEBUG("Not pinned by caller in i915_gem_pin_ioctl(): %d\n", |
79e53945 | 4204 | args->handle); |
1d7cfea1 CW |
4205 | ret = -EINVAL; |
4206 | goto out; | |
79e53945 | 4207 | } |
05394f39 CW |
4208 | obj->user_pin_count--; |
4209 | if (obj->user_pin_count == 0) { | |
4210 | obj->pin_filp = NULL; | |
d7f46fc4 | 4211 | i915_gem_object_ggtt_unpin(obj); |
79e53945 | 4212 | } |
673a394b | 4213 | |
1d7cfea1 | 4214 | out: |
05394f39 | 4215 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 4216 | unlock: |
673a394b | 4217 | mutex_unlock(&dev->struct_mutex); |
1d7cfea1 | 4218 | return ret; |
673a394b EA |
4219 | } |
4220 | ||
4221 | int | |
4222 | i915_gem_busy_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 4223 | struct drm_file *file) |
673a394b EA |
4224 | { |
4225 | struct drm_i915_gem_busy *args = data; | |
05394f39 | 4226 | struct drm_i915_gem_object *obj; |
30dbf0c0 CW |
4227 | int ret; |
4228 | ||
76c1dec1 | 4229 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 4230 | if (ret) |
76c1dec1 | 4231 | return ret; |
673a394b | 4232 | |
05394f39 | 4233 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 4234 | if (&obj->base == NULL) { |
1d7cfea1 CW |
4235 | ret = -ENOENT; |
4236 | goto unlock; | |
673a394b | 4237 | } |
d1b851fc | 4238 | |
0be555b6 CW |
4239 | /* Count all active objects as busy, even if they are currently not used |
4240 | * by the gpu. Users of this interface expect objects to eventually | |
4241 | * become non-busy without any further actions, therefore emit any | |
4242 | * necessary flushes here. | |
c4de0a5d | 4243 | */ |
30dfebf3 | 4244 | ret = i915_gem_object_flush_active(obj); |
0be555b6 | 4245 | |
30dfebf3 | 4246 | args->busy = obj->active; |
e9808edd CW |
4247 | if (obj->ring) { |
4248 | BUILD_BUG_ON(I915_NUM_RINGS > 16); | |
4249 | args->busy |= intel_ring_flag(obj->ring) << 16; | |
4250 | } | |
673a394b | 4251 | |
05394f39 | 4252 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 4253 | unlock: |
673a394b | 4254 | mutex_unlock(&dev->struct_mutex); |
1d7cfea1 | 4255 | return ret; |
673a394b EA |
4256 | } |
4257 | ||
4258 | int | |
4259 | i915_gem_throttle_ioctl(struct drm_device *dev, void *data, | |
4260 | struct drm_file *file_priv) | |
4261 | { | |
0206e353 | 4262 | return i915_gem_ring_throttle(dev, file_priv); |
673a394b EA |
4263 | } |
4264 | ||
3ef94daa CW |
4265 | int |
4266 | i915_gem_madvise_ioctl(struct drm_device *dev, void *data, | |
4267 | struct drm_file *file_priv) | |
4268 | { | |
4269 | struct drm_i915_gem_madvise *args = data; | |
05394f39 | 4270 | struct drm_i915_gem_object *obj; |
76c1dec1 | 4271 | int ret; |
3ef94daa CW |
4272 | |
4273 | switch (args->madv) { | |
4274 | case I915_MADV_DONTNEED: | |
4275 | case I915_MADV_WILLNEED: | |
4276 | break; | |
4277 | default: | |
4278 | return -EINVAL; | |
4279 | } | |
4280 | ||
1d7cfea1 CW |
4281 | ret = i915_mutex_lock_interruptible(dev); |
4282 | if (ret) | |
4283 | return ret; | |
4284 | ||
05394f39 | 4285 | obj = to_intel_bo(drm_gem_object_lookup(dev, file_priv, args->handle)); |
c8725226 | 4286 | if (&obj->base == NULL) { |
1d7cfea1 CW |
4287 | ret = -ENOENT; |
4288 | goto unlock; | |
3ef94daa | 4289 | } |
3ef94daa | 4290 | |
d7f46fc4 | 4291 | if (i915_gem_obj_is_pinned(obj)) { |
1d7cfea1 CW |
4292 | ret = -EINVAL; |
4293 | goto out; | |
3ef94daa CW |
4294 | } |
4295 | ||
05394f39 CW |
4296 | if (obj->madv != __I915_MADV_PURGED) |
4297 | obj->madv = args->madv; | |
3ef94daa | 4298 | |
6c085a72 CW |
4299 | /* if the object is no longer attached, discard its backing storage */ |
4300 | if (i915_gem_object_is_purgeable(obj) && obj->pages == NULL) | |
2d7ef395 CW |
4301 | i915_gem_object_truncate(obj); |
4302 | ||
05394f39 | 4303 | args->retained = obj->madv != __I915_MADV_PURGED; |
bb6baf76 | 4304 | |
1d7cfea1 | 4305 | out: |
05394f39 | 4306 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 4307 | unlock: |
3ef94daa | 4308 | mutex_unlock(&dev->struct_mutex); |
1d7cfea1 | 4309 | return ret; |
3ef94daa CW |
4310 | } |
4311 | ||
37e680a1 CW |
4312 | void i915_gem_object_init(struct drm_i915_gem_object *obj, |
4313 | const struct drm_i915_gem_object_ops *ops) | |
0327d6ba | 4314 | { |
35c20a60 | 4315 | INIT_LIST_HEAD(&obj->global_list); |
0327d6ba | 4316 | INIT_LIST_HEAD(&obj->ring_list); |
b25cb2f8 | 4317 | INIT_LIST_HEAD(&obj->obj_exec_link); |
2f633156 | 4318 | INIT_LIST_HEAD(&obj->vma_list); |
0327d6ba | 4319 | |
37e680a1 CW |
4320 | obj->ops = ops; |
4321 | ||
0327d6ba CW |
4322 | obj->fence_reg = I915_FENCE_REG_NONE; |
4323 | obj->madv = I915_MADV_WILLNEED; | |
4324 | /* Avoid an unnecessary call to unbind on the first bind. */ | |
4325 | obj->map_and_fenceable = true; | |
4326 | ||
4327 | i915_gem_info_add_obj(obj->base.dev->dev_private, obj->base.size); | |
4328 | } | |
4329 | ||
37e680a1 CW |
4330 | static const struct drm_i915_gem_object_ops i915_gem_object_ops = { |
4331 | .get_pages = i915_gem_object_get_pages_gtt, | |
4332 | .put_pages = i915_gem_object_put_pages_gtt, | |
4333 | }; | |
4334 | ||
05394f39 CW |
4335 | struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev, |
4336 | size_t size) | |
ac52bc56 | 4337 | { |
c397b908 | 4338 | struct drm_i915_gem_object *obj; |
5949eac4 | 4339 | struct address_space *mapping; |
1a240d4d | 4340 | gfp_t mask; |
ac52bc56 | 4341 | |
42dcedd4 | 4342 | obj = i915_gem_object_alloc(dev); |
c397b908 DV |
4343 | if (obj == NULL) |
4344 | return NULL; | |
673a394b | 4345 | |
c397b908 | 4346 | if (drm_gem_object_init(dev, &obj->base, size) != 0) { |
42dcedd4 | 4347 | i915_gem_object_free(obj); |
c397b908 DV |
4348 | return NULL; |
4349 | } | |
673a394b | 4350 | |
bed1ea95 CW |
4351 | mask = GFP_HIGHUSER | __GFP_RECLAIMABLE; |
4352 | if (IS_CRESTLINE(dev) || IS_BROADWATER(dev)) { | |
4353 | /* 965gm cannot relocate objects above 4GiB. */ | |
4354 | mask &= ~__GFP_HIGHMEM; | |
4355 | mask |= __GFP_DMA32; | |
4356 | } | |
4357 | ||
496ad9aa | 4358 | mapping = file_inode(obj->base.filp)->i_mapping; |
bed1ea95 | 4359 | mapping_set_gfp_mask(mapping, mask); |
5949eac4 | 4360 | |
37e680a1 | 4361 | i915_gem_object_init(obj, &i915_gem_object_ops); |
73aa808f | 4362 | |
c397b908 DV |
4363 | obj->base.write_domain = I915_GEM_DOMAIN_CPU; |
4364 | obj->base.read_domains = I915_GEM_DOMAIN_CPU; | |
673a394b | 4365 | |
3d29b842 ED |
4366 | if (HAS_LLC(dev)) { |
4367 | /* On some devices, we can have the GPU use the LLC (the CPU | |
a1871112 EA |
4368 | * cache) for about a 10% performance improvement |
4369 | * compared to uncached. Graphics requests other than | |
4370 | * display scanout are coherent with the CPU in | |
4371 | * accessing this cache. This means in this mode we | |
4372 | * don't need to clflush on the CPU side, and on the | |
4373 | * GPU side we only need to flush internal caches to | |
4374 | * get data visible to the CPU. | |
4375 | * | |
4376 | * However, we maintain the display planes as UC, and so | |
4377 | * need to rebind when first used as such. | |
4378 | */ | |
4379 | obj->cache_level = I915_CACHE_LLC; | |
4380 | } else | |
4381 | obj->cache_level = I915_CACHE_NONE; | |
4382 | ||
d861e338 DV |
4383 | trace_i915_gem_object_create(obj); |
4384 | ||
05394f39 | 4385 | return obj; |
c397b908 DV |
4386 | } |
4387 | ||
340fbd8c CW |
4388 | static bool discard_backing_storage(struct drm_i915_gem_object *obj) |
4389 | { | |
4390 | /* If we are the last user of the backing storage (be it shmemfs | |
4391 | * pages or stolen etc), we know that the pages are going to be | |
4392 | * immediately released. In this case, we can then skip copying | |
4393 | * back the contents from the GPU. | |
4394 | */ | |
4395 | ||
4396 | if (obj->madv != I915_MADV_WILLNEED) | |
4397 | return false; | |
4398 | ||
4399 | if (obj->base.filp == NULL) | |
4400 | return true; | |
4401 | ||
4402 | /* At first glance, this looks racy, but then again so would be | |
4403 | * userspace racing mmap against close. However, the first external | |
4404 | * reference to the filp can only be obtained through the | |
4405 | * i915_gem_mmap_ioctl() which safeguards us against the user | |
4406 | * acquiring such a reference whilst we are in the middle of | |
4407 | * freeing the object. | |
4408 | */ | |
4409 | return atomic_long_read(&obj->base.filp->f_count) == 1; | |
4410 | } | |
4411 | ||
1488fc08 | 4412 | void i915_gem_free_object(struct drm_gem_object *gem_obj) |
673a394b | 4413 | { |
1488fc08 | 4414 | struct drm_i915_gem_object *obj = to_intel_bo(gem_obj); |
05394f39 | 4415 | struct drm_device *dev = obj->base.dev; |
3e31c6c0 | 4416 | struct drm_i915_private *dev_priv = dev->dev_private; |
07fe0b12 | 4417 | struct i915_vma *vma, *next; |
673a394b | 4418 | |
f65c9168 PZ |
4419 | intel_runtime_pm_get(dev_priv); |
4420 | ||
26e12f89 CW |
4421 | trace_i915_gem_object_destroy(obj); |
4422 | ||
07fe0b12 | 4423 | list_for_each_entry_safe(vma, next, &obj->vma_list, vma_link) { |
d7f46fc4 BW |
4424 | int ret; |
4425 | ||
4426 | vma->pin_count = 0; | |
4427 | ret = i915_vma_unbind(vma); | |
07fe0b12 BW |
4428 | if (WARN_ON(ret == -ERESTARTSYS)) { |
4429 | bool was_interruptible; | |
1488fc08 | 4430 | |
07fe0b12 BW |
4431 | was_interruptible = dev_priv->mm.interruptible; |
4432 | dev_priv->mm.interruptible = false; | |
1488fc08 | 4433 | |
07fe0b12 | 4434 | WARN_ON(i915_vma_unbind(vma)); |
1488fc08 | 4435 | |
07fe0b12 BW |
4436 | dev_priv->mm.interruptible = was_interruptible; |
4437 | } | |
1488fc08 CW |
4438 | } |
4439 | ||
00731155 CW |
4440 | i915_gem_object_detach_phys(obj); |
4441 | ||
1d64ae71 BW |
4442 | /* Stolen objects don't hold a ref, but do hold pin count. Fix that up |
4443 | * before progressing. */ | |
4444 | if (obj->stolen) | |
4445 | i915_gem_object_unpin_pages(obj); | |
4446 | ||
401c29f6 BW |
4447 | if (WARN_ON(obj->pages_pin_count)) |
4448 | obj->pages_pin_count = 0; | |
340fbd8c | 4449 | if (discard_backing_storage(obj)) |
5537252b | 4450 | obj->madv = I915_MADV_DONTNEED; |
37e680a1 | 4451 | i915_gem_object_put_pages(obj); |
d8cb5086 | 4452 | i915_gem_object_free_mmap_offset(obj); |
0104fdbb | 4453 | i915_gem_object_release_stolen(obj); |
de151cf6 | 4454 | |
9da3da66 CW |
4455 | BUG_ON(obj->pages); |
4456 | ||
2f745ad3 CW |
4457 | if (obj->base.import_attach) |
4458 | drm_prime_gem_destroy(&obj->base, NULL); | |
de151cf6 | 4459 | |
5cc9ed4b CW |
4460 | if (obj->ops->release) |
4461 | obj->ops->release(obj); | |
4462 | ||
05394f39 CW |
4463 | drm_gem_object_release(&obj->base); |
4464 | i915_gem_info_remove_obj(dev_priv, obj->base.size); | |
c397b908 | 4465 | |
05394f39 | 4466 | kfree(obj->bit_17); |
42dcedd4 | 4467 | i915_gem_object_free(obj); |
f65c9168 PZ |
4468 | |
4469 | intel_runtime_pm_put(dev_priv); | |
673a394b EA |
4470 | } |
4471 | ||
e656a6cb | 4472 | struct i915_vma *i915_gem_obj_to_vma(struct drm_i915_gem_object *obj, |
2f633156 | 4473 | struct i915_address_space *vm) |
e656a6cb DV |
4474 | { |
4475 | struct i915_vma *vma; | |
4476 | list_for_each_entry(vma, &obj->vma_list, vma_link) | |
4477 | if (vma->vm == vm) | |
4478 | return vma; | |
4479 | ||
4480 | return NULL; | |
4481 | } | |
4482 | ||
2f633156 BW |
4483 | void i915_gem_vma_destroy(struct i915_vma *vma) |
4484 | { | |
4485 | WARN_ON(vma->node.allocated); | |
aaa05667 CW |
4486 | |
4487 | /* Keep the vma as a placeholder in the execbuffer reservation lists */ | |
4488 | if (!list_empty(&vma->exec_list)) | |
4489 | return; | |
4490 | ||
8b9c2b94 | 4491 | list_del(&vma->vma_link); |
b93dab6e | 4492 | |
2f633156 BW |
4493 | kfree(vma); |
4494 | } | |
4495 | ||
e3efda49 CW |
4496 | static void |
4497 | i915_gem_stop_ringbuffers(struct drm_device *dev) | |
4498 | { | |
4499 | struct drm_i915_private *dev_priv = dev->dev_private; | |
a4872ba6 | 4500 | struct intel_engine_cs *ring; |
e3efda49 CW |
4501 | int i; |
4502 | ||
4503 | for_each_ring(ring, dev_priv, i) | |
4504 | intel_stop_ring_buffer(ring); | |
4505 | } | |
4506 | ||
29105ccc | 4507 | int |
45c5f202 | 4508 | i915_gem_suspend(struct drm_device *dev) |
29105ccc | 4509 | { |
3e31c6c0 | 4510 | struct drm_i915_private *dev_priv = dev->dev_private; |
45c5f202 | 4511 | int ret = 0; |
28dfe52a | 4512 | |
45c5f202 | 4513 | mutex_lock(&dev->struct_mutex); |
f7403347 | 4514 | if (dev_priv->ums.mm_suspended) |
45c5f202 | 4515 | goto err; |
28dfe52a | 4516 | |
b2da9fe5 | 4517 | ret = i915_gpu_idle(dev); |
f7403347 | 4518 | if (ret) |
45c5f202 | 4519 | goto err; |
f7403347 | 4520 | |
b2da9fe5 | 4521 | i915_gem_retire_requests(dev); |
673a394b | 4522 | |
29105ccc | 4523 | /* Under UMS, be paranoid and evict. */ |
a39d7efc | 4524 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) |
6c085a72 | 4525 | i915_gem_evict_everything(dev); |
29105ccc | 4526 | |
29105ccc | 4527 | i915_kernel_lost_context(dev); |
e3efda49 | 4528 | i915_gem_stop_ringbuffers(dev); |
29105ccc | 4529 | |
45c5f202 CW |
4530 | /* Hack! Don't let anybody do execbuf while we don't control the chip. |
4531 | * We need to replace this with a semaphore, or something. | |
4532 | * And not confound ums.mm_suspended! | |
4533 | */ | |
4534 | dev_priv->ums.mm_suspended = !drm_core_check_feature(dev, | |
4535 | DRIVER_MODESET); | |
4536 | mutex_unlock(&dev->struct_mutex); | |
4537 | ||
4538 | del_timer_sync(&dev_priv->gpu_error.hangcheck_timer); | |
29105ccc | 4539 | cancel_delayed_work_sync(&dev_priv->mm.retire_work); |
b29c19b6 | 4540 | cancel_delayed_work_sync(&dev_priv->mm.idle_work); |
29105ccc | 4541 | |
673a394b | 4542 | return 0; |
45c5f202 CW |
4543 | |
4544 | err: | |
4545 | mutex_unlock(&dev->struct_mutex); | |
4546 | return ret; | |
673a394b EA |
4547 | } |
4548 | ||
a4872ba6 | 4549 | int i915_gem_l3_remap(struct intel_engine_cs *ring, int slice) |
b9524a1e | 4550 | { |
c3787e2e | 4551 | struct drm_device *dev = ring->dev; |
3e31c6c0 | 4552 | struct drm_i915_private *dev_priv = dev->dev_private; |
35a85ac6 BW |
4553 | u32 reg_base = GEN7_L3LOG_BASE + (slice * 0x200); |
4554 | u32 *remap_info = dev_priv->l3_parity.remap_info[slice]; | |
c3787e2e | 4555 | int i, ret; |
b9524a1e | 4556 | |
040d2baa | 4557 | if (!HAS_L3_DPF(dev) || !remap_info) |
c3787e2e | 4558 | return 0; |
b9524a1e | 4559 | |
c3787e2e BW |
4560 | ret = intel_ring_begin(ring, GEN7_L3LOG_SIZE / 4 * 3); |
4561 | if (ret) | |
4562 | return ret; | |
b9524a1e | 4563 | |
c3787e2e BW |
4564 | /* |
4565 | * Note: We do not worry about the concurrent register cacheline hang | |
4566 | * here because no other code should access these registers other than | |
4567 | * at initialization time. | |
4568 | */ | |
b9524a1e | 4569 | for (i = 0; i < GEN7_L3LOG_SIZE; i += 4) { |
c3787e2e BW |
4570 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); |
4571 | intel_ring_emit(ring, reg_base + i); | |
4572 | intel_ring_emit(ring, remap_info[i/4]); | |
b9524a1e BW |
4573 | } |
4574 | ||
c3787e2e | 4575 | intel_ring_advance(ring); |
b9524a1e | 4576 | |
c3787e2e | 4577 | return ret; |
b9524a1e BW |
4578 | } |
4579 | ||
f691e2f4 DV |
4580 | void i915_gem_init_swizzling(struct drm_device *dev) |
4581 | { | |
3e31c6c0 | 4582 | struct drm_i915_private *dev_priv = dev->dev_private; |
f691e2f4 | 4583 | |
11782b02 | 4584 | if (INTEL_INFO(dev)->gen < 5 || |
f691e2f4 DV |
4585 | dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_NONE) |
4586 | return; | |
4587 | ||
4588 | I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) | | |
4589 | DISP_TILE_SURFACE_SWIZZLING); | |
4590 | ||
11782b02 DV |
4591 | if (IS_GEN5(dev)) |
4592 | return; | |
4593 | ||
f691e2f4 DV |
4594 | I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_SWZCTL); |
4595 | if (IS_GEN6(dev)) | |
6b26c86d | 4596 | I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB)); |
8782e26c | 4597 | else if (IS_GEN7(dev)) |
6b26c86d | 4598 | I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB)); |
31a5336e BW |
4599 | else if (IS_GEN8(dev)) |
4600 | I915_WRITE(GAMTARBMODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_BDW)); | |
8782e26c BW |
4601 | else |
4602 | BUG(); | |
f691e2f4 | 4603 | } |
e21af88d | 4604 | |
67b1b571 CW |
4605 | static bool |
4606 | intel_enable_blt(struct drm_device *dev) | |
4607 | { | |
4608 | if (!HAS_BLT(dev)) | |
4609 | return false; | |
4610 | ||
4611 | /* The blitter was dysfunctional on early prototypes */ | |
4612 | if (IS_GEN6(dev) && dev->pdev->revision < 8) { | |
4613 | DRM_INFO("BLT not supported on this pre-production hardware;" | |
4614 | " graphics performance will be degraded.\n"); | |
4615 | return false; | |
4616 | } | |
4617 | ||
4618 | return true; | |
4619 | } | |
4620 | ||
4fc7c971 | 4621 | static int i915_gem_init_rings(struct drm_device *dev) |
8187a2b7 | 4622 | { |
4fc7c971 | 4623 | struct drm_i915_private *dev_priv = dev->dev_private; |
8187a2b7 | 4624 | int ret; |
68f95ba9 | 4625 | |
5c1143bb | 4626 | ret = intel_init_render_ring_buffer(dev); |
68f95ba9 | 4627 | if (ret) |
b6913e4b | 4628 | return ret; |
68f95ba9 CW |
4629 | |
4630 | if (HAS_BSD(dev)) { | |
5c1143bb | 4631 | ret = intel_init_bsd_ring_buffer(dev); |
68f95ba9 CW |
4632 | if (ret) |
4633 | goto cleanup_render_ring; | |
d1b851fc | 4634 | } |
68f95ba9 | 4635 | |
67b1b571 | 4636 | if (intel_enable_blt(dev)) { |
549f7365 CW |
4637 | ret = intel_init_blt_ring_buffer(dev); |
4638 | if (ret) | |
4639 | goto cleanup_bsd_ring; | |
4640 | } | |
4641 | ||
9a8a2213 BW |
4642 | if (HAS_VEBOX(dev)) { |
4643 | ret = intel_init_vebox_ring_buffer(dev); | |
4644 | if (ret) | |
4645 | goto cleanup_blt_ring; | |
4646 | } | |
4647 | ||
845f74a7 ZY |
4648 | if (HAS_BSD2(dev)) { |
4649 | ret = intel_init_bsd2_ring_buffer(dev); | |
4650 | if (ret) | |
4651 | goto cleanup_vebox_ring; | |
4652 | } | |
9a8a2213 | 4653 | |
99433931 | 4654 | ret = i915_gem_set_seqno(dev, ((u32)~0 - 0x1000)); |
4fc7c971 | 4655 | if (ret) |
845f74a7 | 4656 | goto cleanup_bsd2_ring; |
4fc7c971 BW |
4657 | |
4658 | return 0; | |
4659 | ||
845f74a7 ZY |
4660 | cleanup_bsd2_ring: |
4661 | intel_cleanup_ring_buffer(&dev_priv->ring[VCS2]); | |
9a8a2213 BW |
4662 | cleanup_vebox_ring: |
4663 | intel_cleanup_ring_buffer(&dev_priv->ring[VECS]); | |
4fc7c971 BW |
4664 | cleanup_blt_ring: |
4665 | intel_cleanup_ring_buffer(&dev_priv->ring[BCS]); | |
4666 | cleanup_bsd_ring: | |
4667 | intel_cleanup_ring_buffer(&dev_priv->ring[VCS]); | |
4668 | cleanup_render_ring: | |
4669 | intel_cleanup_ring_buffer(&dev_priv->ring[RCS]); | |
4670 | ||
4671 | return ret; | |
4672 | } | |
4673 | ||
4674 | int | |
4675 | i915_gem_init_hw(struct drm_device *dev) | |
4676 | { | |
3e31c6c0 | 4677 | struct drm_i915_private *dev_priv = dev->dev_private; |
35a85ac6 | 4678 | int ret, i; |
4fc7c971 BW |
4679 | |
4680 | if (INTEL_INFO(dev)->gen < 6 && !intel_enable_gtt()) | |
4681 | return -EIO; | |
4682 | ||
59124506 | 4683 | if (dev_priv->ellc_size) |
05e21cc4 | 4684 | I915_WRITE(HSW_IDICR, I915_READ(HSW_IDICR) | IDIHASHMSK(0xf)); |
4fc7c971 | 4685 | |
0bf21347 VS |
4686 | if (IS_HASWELL(dev)) |
4687 | I915_WRITE(MI_PREDICATE_RESULT_2, IS_HSW_GT3(dev) ? | |
4688 | LOWER_SLICE_ENABLED : LOWER_SLICE_DISABLED); | |
9435373e | 4689 | |
88a2b2a3 | 4690 | if (HAS_PCH_NOP(dev)) { |
6ba844b0 DV |
4691 | if (IS_IVYBRIDGE(dev)) { |
4692 | u32 temp = I915_READ(GEN7_MSG_CTL); | |
4693 | temp &= ~(WAIT_FOR_PCH_FLR_ACK | WAIT_FOR_PCH_RESET_ACK); | |
4694 | I915_WRITE(GEN7_MSG_CTL, temp); | |
4695 | } else if (INTEL_INFO(dev)->gen >= 7) { | |
4696 | u32 temp = I915_READ(HSW_NDE_RSTWRN_OPT); | |
4697 | temp &= ~RESET_PCH_HANDSHAKE_ENABLE; | |
4698 | I915_WRITE(HSW_NDE_RSTWRN_OPT, temp); | |
4699 | } | |
88a2b2a3 BW |
4700 | } |
4701 | ||
4fc7c971 BW |
4702 | i915_gem_init_swizzling(dev); |
4703 | ||
4704 | ret = i915_gem_init_rings(dev); | |
99433931 MK |
4705 | if (ret) |
4706 | return ret; | |
4707 | ||
c3787e2e BW |
4708 | for (i = 0; i < NUM_L3_SLICES(dev); i++) |
4709 | i915_gem_l3_remap(&dev_priv->ring[RCS], i); | |
4710 | ||
254f965c | 4711 | /* |
2fa48d8d BW |
4712 | * XXX: Contexts should only be initialized once. Doing a switch to the |
4713 | * default context switch however is something we'd like to do after | |
4714 | * reset or thaw (the latter may not actually be necessary for HW, but | |
4715 | * goes with our code better). Context switching requires rings (for | |
4716 | * the do_switch), but before enabling PPGTT. So don't move this. | |
254f965c | 4717 | */ |
2fa48d8d | 4718 | ret = i915_gem_context_enable(dev_priv); |
60990320 | 4719 | if (ret && ret != -EIO) { |
2fa48d8d | 4720 | DRM_ERROR("Context enable failed %d\n", ret); |
60990320 | 4721 | i915_gem_cleanup_ringbuffer(dev); |
b7c36d25 | 4722 | } |
e21af88d | 4723 | |
2fa48d8d | 4724 | return ret; |
8187a2b7 ZN |
4725 | } |
4726 | ||
1070a42b CW |
4727 | int i915_gem_init(struct drm_device *dev) |
4728 | { | |
4729 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1070a42b CW |
4730 | int ret; |
4731 | ||
1070a42b | 4732 | mutex_lock(&dev->struct_mutex); |
d62b4892 JB |
4733 | |
4734 | if (IS_VALLEYVIEW(dev)) { | |
4735 | /* VLVA0 (potential hack), BIOS isn't actually waking us */ | |
981a5aea ID |
4736 | I915_WRITE(VLV_GTLC_WAKE_CTRL, VLV_GTLC_ALLOWWAKEREQ); |
4737 | if (wait_for((I915_READ(VLV_GTLC_PW_STATUS) & | |
4738 | VLV_GTLC_ALLOWWAKEACK), 10)) | |
d62b4892 JB |
4739 | DRM_DEBUG_DRIVER("allow wake ack timed out\n"); |
4740 | } | |
4741 | ||
5cc9ed4b | 4742 | i915_gem_init_userptr(dev); |
d7e5008f | 4743 | i915_gem_init_global_gtt(dev); |
d62b4892 | 4744 | |
2fa48d8d | 4745 | ret = i915_gem_context_init(dev); |
e3848694 MK |
4746 | if (ret) { |
4747 | mutex_unlock(&dev->struct_mutex); | |
2fa48d8d | 4748 | return ret; |
e3848694 | 4749 | } |
2fa48d8d | 4750 | |
1070a42b | 4751 | ret = i915_gem_init_hw(dev); |
60990320 CW |
4752 | if (ret == -EIO) { |
4753 | /* Allow ring initialisation to fail by marking the GPU as | |
4754 | * wedged. But we only want to do this where the GPU is angry, | |
4755 | * for all other failure, such as an allocation failure, bail. | |
4756 | */ | |
4757 | DRM_ERROR("Failed to initialize GPU, declaring it wedged\n"); | |
4758 | atomic_set_mask(I915_WEDGED, &dev_priv->gpu_error.reset_counter); | |
4759 | ret = 0; | |
1070a42b | 4760 | } |
60990320 | 4761 | mutex_unlock(&dev->struct_mutex); |
1070a42b | 4762 | |
53ca26ca DV |
4763 | /* Allow hardware batchbuffers unless told otherwise, but not for KMS. */ |
4764 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) | |
4765 | dev_priv->dri1.allow_batchbuffer = 1; | |
60990320 | 4766 | return ret; |
1070a42b CW |
4767 | } |
4768 | ||
8187a2b7 ZN |
4769 | void |
4770 | i915_gem_cleanup_ringbuffer(struct drm_device *dev) | |
4771 | { | |
3e31c6c0 | 4772 | struct drm_i915_private *dev_priv = dev->dev_private; |
a4872ba6 | 4773 | struct intel_engine_cs *ring; |
1ec14ad3 | 4774 | int i; |
8187a2b7 | 4775 | |
b4519513 CW |
4776 | for_each_ring(ring, dev_priv, i) |
4777 | intel_cleanup_ring_buffer(ring); | |
8187a2b7 ZN |
4778 | } |
4779 | ||
673a394b EA |
4780 | int |
4781 | i915_gem_entervt_ioctl(struct drm_device *dev, void *data, | |
4782 | struct drm_file *file_priv) | |
4783 | { | |
db1b76ca | 4784 | struct drm_i915_private *dev_priv = dev->dev_private; |
b4519513 | 4785 | int ret; |
673a394b | 4786 | |
79e53945 JB |
4787 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
4788 | return 0; | |
4789 | ||
1f83fee0 | 4790 | if (i915_reset_in_progress(&dev_priv->gpu_error)) { |
673a394b | 4791 | DRM_ERROR("Reenabling wedged hardware, good luck\n"); |
1f83fee0 | 4792 | atomic_set(&dev_priv->gpu_error.reset_counter, 0); |
673a394b EA |
4793 | } |
4794 | ||
673a394b | 4795 | mutex_lock(&dev->struct_mutex); |
db1b76ca | 4796 | dev_priv->ums.mm_suspended = 0; |
9bb2d6f9 | 4797 | |
f691e2f4 | 4798 | ret = i915_gem_init_hw(dev); |
d816f6ac WF |
4799 | if (ret != 0) { |
4800 | mutex_unlock(&dev->struct_mutex); | |
9bb2d6f9 | 4801 | return ret; |
d816f6ac | 4802 | } |
9bb2d6f9 | 4803 | |
5cef07e1 | 4804 | BUG_ON(!list_empty(&dev_priv->gtt.base.active_list)); |
dbb19d30 | 4805 | |
bb0f1b5c | 4806 | ret = drm_irq_install(dev, dev->pdev->irq); |
5f35308b CW |
4807 | if (ret) |
4808 | goto cleanup_ringbuffer; | |
e090c53b | 4809 | mutex_unlock(&dev->struct_mutex); |
dbb19d30 | 4810 | |
673a394b | 4811 | return 0; |
5f35308b CW |
4812 | |
4813 | cleanup_ringbuffer: | |
5f35308b | 4814 | i915_gem_cleanup_ringbuffer(dev); |
db1b76ca | 4815 | dev_priv->ums.mm_suspended = 1; |
5f35308b CW |
4816 | mutex_unlock(&dev->struct_mutex); |
4817 | ||
4818 | return ret; | |
673a394b EA |
4819 | } |
4820 | ||
4821 | int | |
4822 | i915_gem_leavevt_ioctl(struct drm_device *dev, void *data, | |
4823 | struct drm_file *file_priv) | |
4824 | { | |
79e53945 JB |
4825 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
4826 | return 0; | |
4827 | ||
e090c53b | 4828 | mutex_lock(&dev->struct_mutex); |
dbb19d30 | 4829 | drm_irq_uninstall(dev); |
e090c53b | 4830 | mutex_unlock(&dev->struct_mutex); |
db1b76ca | 4831 | |
45c5f202 | 4832 | return i915_gem_suspend(dev); |
673a394b EA |
4833 | } |
4834 | ||
4835 | void | |
4836 | i915_gem_lastclose(struct drm_device *dev) | |
4837 | { | |
4838 | int ret; | |
673a394b | 4839 | |
e806b495 EA |
4840 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
4841 | return; | |
4842 | ||
45c5f202 | 4843 | ret = i915_gem_suspend(dev); |
6dbe2772 KP |
4844 | if (ret) |
4845 | DRM_ERROR("failed to idle hardware: %d\n", ret); | |
673a394b EA |
4846 | } |
4847 | ||
64193406 | 4848 | static void |
a4872ba6 | 4849 | init_ring_lists(struct intel_engine_cs *ring) |
64193406 CW |
4850 | { |
4851 | INIT_LIST_HEAD(&ring->active_list); | |
4852 | INIT_LIST_HEAD(&ring->request_list); | |
64193406 CW |
4853 | } |
4854 | ||
7e0d96bc BW |
4855 | void i915_init_vm(struct drm_i915_private *dev_priv, |
4856 | struct i915_address_space *vm) | |
fc8c067e | 4857 | { |
7e0d96bc BW |
4858 | if (!i915_is_ggtt(vm)) |
4859 | drm_mm_init(&vm->mm, vm->start, vm->total); | |
fc8c067e BW |
4860 | vm->dev = dev_priv->dev; |
4861 | INIT_LIST_HEAD(&vm->active_list); | |
4862 | INIT_LIST_HEAD(&vm->inactive_list); | |
4863 | INIT_LIST_HEAD(&vm->global_link); | |
f72d21ed | 4864 | list_add_tail(&vm->global_link, &dev_priv->vm_list); |
fc8c067e BW |
4865 | } |
4866 | ||
673a394b EA |
4867 | void |
4868 | i915_gem_load(struct drm_device *dev) | |
4869 | { | |
3e31c6c0 | 4870 | struct drm_i915_private *dev_priv = dev->dev_private; |
42dcedd4 CW |
4871 | int i; |
4872 | ||
4873 | dev_priv->slab = | |
4874 | kmem_cache_create("i915_gem_object", | |
4875 | sizeof(struct drm_i915_gem_object), 0, | |
4876 | SLAB_HWCACHE_ALIGN, | |
4877 | NULL); | |
673a394b | 4878 | |
fc8c067e BW |
4879 | INIT_LIST_HEAD(&dev_priv->vm_list); |
4880 | i915_init_vm(dev_priv, &dev_priv->gtt.base); | |
4881 | ||
a33afea5 | 4882 | INIT_LIST_HEAD(&dev_priv->context_list); |
6c085a72 CW |
4883 | INIT_LIST_HEAD(&dev_priv->mm.unbound_list); |
4884 | INIT_LIST_HEAD(&dev_priv->mm.bound_list); | |
a09ba7fa | 4885 | INIT_LIST_HEAD(&dev_priv->mm.fence_list); |
1ec14ad3 CW |
4886 | for (i = 0; i < I915_NUM_RINGS; i++) |
4887 | init_ring_lists(&dev_priv->ring[i]); | |
4b9de737 | 4888 | for (i = 0; i < I915_MAX_NUM_FENCES; i++) |
007cc8ac | 4889 | INIT_LIST_HEAD(&dev_priv->fence_regs[i].lru_list); |
673a394b EA |
4890 | INIT_DELAYED_WORK(&dev_priv->mm.retire_work, |
4891 | i915_gem_retire_work_handler); | |
b29c19b6 CW |
4892 | INIT_DELAYED_WORK(&dev_priv->mm.idle_work, |
4893 | i915_gem_idle_work_handler); | |
1f83fee0 | 4894 | init_waitqueue_head(&dev_priv->gpu_error.reset_queue); |
31169714 | 4895 | |
94400120 | 4896 | /* On GEN3 we really need to make sure the ARB C3 LP bit is set */ |
dbb42748 | 4897 | if (!drm_core_check_feature(dev, DRIVER_MODESET) && IS_GEN3(dev)) { |
50743298 DV |
4898 | I915_WRITE(MI_ARB_STATE, |
4899 | _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE)); | |
94400120 DA |
4900 | } |
4901 | ||
72bfa19c CW |
4902 | dev_priv->relative_constants_mode = I915_EXEC_CONSTANTS_REL_GENERAL; |
4903 | ||
de151cf6 | 4904 | /* Old X drivers will take 0-2 for front, back, depth buffers */ |
b397c836 EA |
4905 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) |
4906 | dev_priv->fence_reg_start = 3; | |
de151cf6 | 4907 | |
42b5aeab VS |
4908 | if (INTEL_INFO(dev)->gen >= 7 && !IS_VALLEYVIEW(dev)) |
4909 | dev_priv->num_fence_regs = 32; | |
4910 | else if (INTEL_INFO(dev)->gen >= 4 || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) | |
de151cf6 JB |
4911 | dev_priv->num_fence_regs = 16; |
4912 | else | |
4913 | dev_priv->num_fence_regs = 8; | |
4914 | ||
b5aa8a0f | 4915 | /* Initialize fence registers to zero */ |
19b2dbde CW |
4916 | INIT_LIST_HEAD(&dev_priv->mm.fence_list); |
4917 | i915_gem_restore_fences(dev); | |
10ed13e4 | 4918 | |
673a394b | 4919 | i915_gem_detect_bit_6_swizzle(dev); |
6b95a207 | 4920 | init_waitqueue_head(&dev_priv->pending_flip_queue); |
17250b71 | 4921 | |
ce453d81 CW |
4922 | dev_priv->mm.interruptible = true; |
4923 | ||
ceabbba5 CW |
4924 | dev_priv->mm.shrinker.scan_objects = i915_gem_shrinker_scan; |
4925 | dev_priv->mm.shrinker.count_objects = i915_gem_shrinker_count; | |
4926 | dev_priv->mm.shrinker.seeks = DEFAULT_SEEKS; | |
4927 | register_shrinker(&dev_priv->mm.shrinker); | |
2cfcd32a CW |
4928 | |
4929 | dev_priv->mm.oom_notifier.notifier_call = i915_gem_shrinker_oom; | |
4930 | register_oom_notifier(&dev_priv->mm.oom_notifier); | |
673a394b | 4931 | } |
71acb5eb | 4932 | |
f787a5f5 | 4933 | void i915_gem_release(struct drm_device *dev, struct drm_file *file) |
b962442e | 4934 | { |
f787a5f5 | 4935 | struct drm_i915_file_private *file_priv = file->driver_priv; |
b962442e | 4936 | |
b29c19b6 CW |
4937 | cancel_delayed_work_sync(&file_priv->mm.idle_work); |
4938 | ||
b962442e EA |
4939 | /* Clean up our request list when the client is going away, so that |
4940 | * later retire_requests won't dereference our soon-to-be-gone | |
4941 | * file_priv. | |
4942 | */ | |
1c25595f | 4943 | spin_lock(&file_priv->mm.lock); |
f787a5f5 CW |
4944 | while (!list_empty(&file_priv->mm.request_list)) { |
4945 | struct drm_i915_gem_request *request; | |
4946 | ||
4947 | request = list_first_entry(&file_priv->mm.request_list, | |
4948 | struct drm_i915_gem_request, | |
4949 | client_list); | |
4950 | list_del(&request->client_list); | |
4951 | request->file_priv = NULL; | |
4952 | } | |
1c25595f | 4953 | spin_unlock(&file_priv->mm.lock); |
b962442e | 4954 | } |
31169714 | 4955 | |
b29c19b6 CW |
4956 | static void |
4957 | i915_gem_file_idle_work_handler(struct work_struct *work) | |
4958 | { | |
4959 | struct drm_i915_file_private *file_priv = | |
4960 | container_of(work, typeof(*file_priv), mm.idle_work.work); | |
4961 | ||
4962 | atomic_set(&file_priv->rps_wait_boost, false); | |
4963 | } | |
4964 | ||
4965 | int i915_gem_open(struct drm_device *dev, struct drm_file *file) | |
4966 | { | |
4967 | struct drm_i915_file_private *file_priv; | |
e422b888 | 4968 | int ret; |
b29c19b6 CW |
4969 | |
4970 | DRM_DEBUG_DRIVER("\n"); | |
4971 | ||
4972 | file_priv = kzalloc(sizeof(*file_priv), GFP_KERNEL); | |
4973 | if (!file_priv) | |
4974 | return -ENOMEM; | |
4975 | ||
4976 | file->driver_priv = file_priv; | |
4977 | file_priv->dev_priv = dev->dev_private; | |
ab0e7ff9 | 4978 | file_priv->file = file; |
b29c19b6 CW |
4979 | |
4980 | spin_lock_init(&file_priv->mm.lock); | |
4981 | INIT_LIST_HEAD(&file_priv->mm.request_list); | |
4982 | INIT_DELAYED_WORK(&file_priv->mm.idle_work, | |
4983 | i915_gem_file_idle_work_handler); | |
4984 | ||
e422b888 BW |
4985 | ret = i915_gem_context_open(dev, file); |
4986 | if (ret) | |
4987 | kfree(file_priv); | |
b29c19b6 | 4988 | |
e422b888 | 4989 | return ret; |
b29c19b6 CW |
4990 | } |
4991 | ||
5774506f CW |
4992 | static bool mutex_is_locked_by(struct mutex *mutex, struct task_struct *task) |
4993 | { | |
4994 | if (!mutex_is_locked(mutex)) | |
4995 | return false; | |
4996 | ||
4997 | #if defined(CONFIG_SMP) || defined(CONFIG_DEBUG_MUTEXES) | |
4998 | return mutex->owner == task; | |
4999 | #else | |
5000 | /* Since UP may be pre-empted, we cannot assume that we own the lock */ | |
5001 | return false; | |
5002 | #endif | |
5003 | } | |
5004 | ||
b453c4db CW |
5005 | static bool i915_gem_shrinker_lock(struct drm_device *dev, bool *unlock) |
5006 | { | |
5007 | if (!mutex_trylock(&dev->struct_mutex)) { | |
5008 | if (!mutex_is_locked_by(&dev->struct_mutex, current)) | |
5009 | return false; | |
5010 | ||
5011 | if (to_i915(dev)->mm.shrinker_no_lock_stealing) | |
5012 | return false; | |
5013 | ||
5014 | *unlock = false; | |
5015 | } else | |
5016 | *unlock = true; | |
5017 | ||
5018 | return true; | |
5019 | } | |
5020 | ||
ceabbba5 CW |
5021 | static int num_vma_bound(struct drm_i915_gem_object *obj) |
5022 | { | |
5023 | struct i915_vma *vma; | |
5024 | int count = 0; | |
5025 | ||
5026 | list_for_each_entry(vma, &obj->vma_list, vma_link) | |
5027 | if (drm_mm_node_allocated(&vma->node)) | |
5028 | count++; | |
5029 | ||
5030 | return count; | |
5031 | } | |
5032 | ||
7dc19d5a | 5033 | static unsigned long |
ceabbba5 | 5034 | i915_gem_shrinker_count(struct shrinker *shrinker, struct shrink_control *sc) |
31169714 | 5035 | { |
17250b71 | 5036 | struct drm_i915_private *dev_priv = |
ceabbba5 | 5037 | container_of(shrinker, struct drm_i915_private, mm.shrinker); |
17250b71 | 5038 | struct drm_device *dev = dev_priv->dev; |
6c085a72 | 5039 | struct drm_i915_gem_object *obj; |
7dc19d5a | 5040 | unsigned long count; |
b453c4db | 5041 | bool unlock; |
17250b71 | 5042 | |
b453c4db CW |
5043 | if (!i915_gem_shrinker_lock(dev, &unlock)) |
5044 | return 0; | |
31169714 | 5045 | |
7dc19d5a | 5046 | count = 0; |
35c20a60 | 5047 | list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) |
a5570178 | 5048 | if (obj->pages_pin_count == 0) |
7dc19d5a | 5049 | count += obj->base.size >> PAGE_SHIFT; |
fcb4a578 BW |
5050 | |
5051 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) { | |
ceabbba5 CW |
5052 | if (!i915_gem_obj_is_pinned(obj) && |
5053 | obj->pages_pin_count == num_vma_bound(obj)) | |
7dc19d5a | 5054 | count += obj->base.size >> PAGE_SHIFT; |
fcb4a578 | 5055 | } |
17250b71 | 5056 | |
5774506f CW |
5057 | if (unlock) |
5058 | mutex_unlock(&dev->struct_mutex); | |
d9973b43 | 5059 | |
7dc19d5a | 5060 | return count; |
31169714 | 5061 | } |
a70a3148 BW |
5062 | |
5063 | /* All the new VM stuff */ | |
5064 | unsigned long i915_gem_obj_offset(struct drm_i915_gem_object *o, | |
5065 | struct i915_address_space *vm) | |
5066 | { | |
5067 | struct drm_i915_private *dev_priv = o->base.dev->dev_private; | |
5068 | struct i915_vma *vma; | |
5069 | ||
6f425321 BW |
5070 | if (!dev_priv->mm.aliasing_ppgtt || |
5071 | vm == &dev_priv->mm.aliasing_ppgtt->base) | |
a70a3148 BW |
5072 | vm = &dev_priv->gtt.base; |
5073 | ||
5074 | BUG_ON(list_empty(&o->vma_list)); | |
5075 | list_for_each_entry(vma, &o->vma_list, vma_link) { | |
5076 | if (vma->vm == vm) | |
5077 | return vma->node.start; | |
5078 | ||
5079 | } | |
5080 | return -1; | |
5081 | } | |
5082 | ||
5083 | bool i915_gem_obj_bound(struct drm_i915_gem_object *o, | |
5084 | struct i915_address_space *vm) | |
5085 | { | |
5086 | struct i915_vma *vma; | |
5087 | ||
5088 | list_for_each_entry(vma, &o->vma_list, vma_link) | |
8b9c2b94 | 5089 | if (vma->vm == vm && drm_mm_node_allocated(&vma->node)) |
a70a3148 BW |
5090 | return true; |
5091 | ||
5092 | return false; | |
5093 | } | |
5094 | ||
5095 | bool i915_gem_obj_bound_any(struct drm_i915_gem_object *o) | |
5096 | { | |
5a1d5eb0 | 5097 | struct i915_vma *vma; |
a70a3148 | 5098 | |
5a1d5eb0 CW |
5099 | list_for_each_entry(vma, &o->vma_list, vma_link) |
5100 | if (drm_mm_node_allocated(&vma->node)) | |
a70a3148 BW |
5101 | return true; |
5102 | ||
5103 | return false; | |
5104 | } | |
5105 | ||
5106 | unsigned long i915_gem_obj_size(struct drm_i915_gem_object *o, | |
5107 | struct i915_address_space *vm) | |
5108 | { | |
5109 | struct drm_i915_private *dev_priv = o->base.dev->dev_private; | |
5110 | struct i915_vma *vma; | |
5111 | ||
6f425321 BW |
5112 | if (!dev_priv->mm.aliasing_ppgtt || |
5113 | vm == &dev_priv->mm.aliasing_ppgtt->base) | |
a70a3148 BW |
5114 | vm = &dev_priv->gtt.base; |
5115 | ||
5116 | BUG_ON(list_empty(&o->vma_list)); | |
5117 | ||
5118 | list_for_each_entry(vma, &o->vma_list, vma_link) | |
5119 | if (vma->vm == vm) | |
5120 | return vma->node.size; | |
5121 | ||
5122 | return 0; | |
5123 | } | |
5124 | ||
7dc19d5a | 5125 | static unsigned long |
ceabbba5 | 5126 | i915_gem_shrinker_scan(struct shrinker *shrinker, struct shrink_control *sc) |
7dc19d5a DC |
5127 | { |
5128 | struct drm_i915_private *dev_priv = | |
ceabbba5 | 5129 | container_of(shrinker, struct drm_i915_private, mm.shrinker); |
7dc19d5a | 5130 | struct drm_device *dev = dev_priv->dev; |
7dc19d5a | 5131 | unsigned long freed; |
b453c4db | 5132 | bool unlock; |
7dc19d5a | 5133 | |
b453c4db CW |
5134 | if (!i915_gem_shrinker_lock(dev, &unlock)) |
5135 | return SHRINK_STOP; | |
7dc19d5a | 5136 | |
d9973b43 CW |
5137 | freed = i915_gem_purge(dev_priv, sc->nr_to_scan); |
5138 | if (freed < sc->nr_to_scan) | |
5139 | freed += __i915_gem_shrink(dev_priv, | |
5140 | sc->nr_to_scan - freed, | |
5141 | false); | |
7dc19d5a DC |
5142 | if (unlock) |
5143 | mutex_unlock(&dev->struct_mutex); | |
d9973b43 | 5144 | |
7dc19d5a DC |
5145 | return freed; |
5146 | } | |
5c2abbea | 5147 | |
2cfcd32a CW |
5148 | static int |
5149 | i915_gem_shrinker_oom(struct notifier_block *nb, unsigned long event, void *ptr) | |
5150 | { | |
5151 | struct drm_i915_private *dev_priv = | |
5152 | container_of(nb, struct drm_i915_private, mm.oom_notifier); | |
5153 | struct drm_device *dev = dev_priv->dev; | |
5154 | struct drm_i915_gem_object *obj; | |
5155 | unsigned long timeout = msecs_to_jiffies(5000) + 1; | |
5156 | unsigned long pinned, bound, unbound, freed; | |
5157 | bool was_interruptible; | |
5158 | bool unlock; | |
5159 | ||
5160 | while (!i915_gem_shrinker_lock(dev, &unlock) && --timeout) | |
5161 | schedule_timeout_killable(1); | |
5162 | if (timeout == 0) { | |
5163 | pr_err("Unable to purge GPU memory due lock contention.\n"); | |
5164 | return NOTIFY_DONE; | |
5165 | } | |
5166 | ||
5167 | was_interruptible = dev_priv->mm.interruptible; | |
5168 | dev_priv->mm.interruptible = false; | |
5169 | ||
5170 | freed = i915_gem_shrink_all(dev_priv); | |
5171 | ||
5172 | dev_priv->mm.interruptible = was_interruptible; | |
5173 | ||
5174 | /* Because we may be allocating inside our own driver, we cannot | |
5175 | * assert that there are no objects with pinned pages that are not | |
5176 | * being pointed to by hardware. | |
5177 | */ | |
5178 | unbound = bound = pinned = 0; | |
5179 | list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) { | |
5180 | if (!obj->base.filp) /* not backed by a freeable object */ | |
5181 | continue; | |
5182 | ||
5183 | if (obj->pages_pin_count) | |
5184 | pinned += obj->base.size; | |
5185 | else | |
5186 | unbound += obj->base.size; | |
5187 | } | |
5188 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) { | |
5189 | if (!obj->base.filp) | |
5190 | continue; | |
5191 | ||
5192 | if (obj->pages_pin_count) | |
5193 | pinned += obj->base.size; | |
5194 | else | |
5195 | bound += obj->base.size; | |
5196 | } | |
5197 | ||
5198 | if (unlock) | |
5199 | mutex_unlock(&dev->struct_mutex); | |
5200 | ||
5201 | pr_info("Purging GPU memory, %lu bytes freed, %lu bytes still pinned.\n", | |
5202 | freed, pinned); | |
5203 | if (unbound || bound) | |
5204 | pr_err("%lu and %lu bytes still available in the " | |
5205 | "bound and unbound GPU page lists.\n", | |
5206 | bound, unbound); | |
5207 | ||
5208 | *(unsigned long *)ptr += freed; | |
5209 | return NOTIFY_DONE; | |
5210 | } | |
5211 | ||
5c2abbea BW |
5212 | struct i915_vma *i915_gem_obj_to_ggtt(struct drm_i915_gem_object *obj) |
5213 | { | |
5214 | struct i915_vma *vma; | |
5215 | ||
19656430 OM |
5216 | /* This WARN has probably outlived its usefulness (callers already |
5217 | * WARN if they don't find the GGTT vma they expect). When removing, | |
5218 | * remember to remove the pre-check in is_pin_display() as well */ | |
5c2abbea BW |
5219 | if (WARN_ON(list_empty(&obj->vma_list))) |
5220 | return NULL; | |
5221 | ||
5222 | vma = list_first_entry(&obj->vma_list, typeof(*vma), vma_link); | |
6e164c33 | 5223 | if (vma->vm != obj_to_ggtt(obj)) |
5c2abbea BW |
5224 | return NULL; |
5225 | ||
5226 | return vma; | |
5227 | } |