Commit | Line | Data |
---|---|---|
673a394b EA |
1 | /* |
2 | * Copyright © 2008 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | * | |
26 | */ | |
27 | ||
28 | #include "drmP.h" | |
29 | #include "drm.h" | |
30 | #include "i915_drm.h" | |
31 | #include "i915_drv.h" | |
1c5d22f7 | 32 | #include "i915_trace.h" |
652c393a | 33 | #include "intel_drv.h" |
5949eac4 | 34 | #include <linux/shmem_fs.h> |
5a0e3ad6 | 35 | #include <linux/slab.h> |
673a394b | 36 | #include <linux/swap.h> |
79e53945 | 37 | #include <linux/pci.h> |
673a394b | 38 | |
88241785 | 39 | static __must_check int i915_gem_object_flush_gpu_write_domain(struct drm_i915_gem_object *obj); |
05394f39 CW |
40 | static void i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj); |
41 | static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj); | |
88241785 CW |
42 | static __must_check int i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, |
43 | bool write); | |
44 | static __must_check int i915_gem_object_set_cpu_read_domain_range(struct drm_i915_gem_object *obj, | |
45 | uint64_t offset, | |
46 | uint64_t size); | |
05394f39 | 47 | static void i915_gem_object_set_to_full_cpu_read_domain(struct drm_i915_gem_object *obj); |
88241785 CW |
48 | static __must_check int i915_gem_object_bind_to_gtt(struct drm_i915_gem_object *obj, |
49 | unsigned alignment, | |
50 | bool map_and_fenceable); | |
d9e86c0e CW |
51 | static void i915_gem_clear_fence_reg(struct drm_device *dev, |
52 | struct drm_i915_fence_reg *reg); | |
05394f39 CW |
53 | static int i915_gem_phys_pwrite(struct drm_device *dev, |
54 | struct drm_i915_gem_object *obj, | |
71acb5eb | 55 | struct drm_i915_gem_pwrite *args, |
05394f39 CW |
56 | struct drm_file *file); |
57 | static void i915_gem_free_object_tail(struct drm_i915_gem_object *obj); | |
673a394b | 58 | |
17250b71 | 59 | static int i915_gem_inactive_shrink(struct shrinker *shrinker, |
1495f230 | 60 | struct shrink_control *sc); |
8c59967c | 61 | static void i915_gem_object_truncate(struct drm_i915_gem_object *obj); |
31169714 | 62 | |
73aa808f CW |
63 | /* some bookkeeping */ |
64 | static void i915_gem_info_add_obj(struct drm_i915_private *dev_priv, | |
65 | size_t size) | |
66 | { | |
67 | dev_priv->mm.object_count++; | |
68 | dev_priv->mm.object_memory += size; | |
69 | } | |
70 | ||
71 | static void i915_gem_info_remove_obj(struct drm_i915_private *dev_priv, | |
72 | size_t size) | |
73 | { | |
74 | dev_priv->mm.object_count--; | |
75 | dev_priv->mm.object_memory -= size; | |
76 | } | |
77 | ||
21dd3734 CW |
78 | static int |
79 | i915_gem_wait_for_error(struct drm_device *dev) | |
30dbf0c0 CW |
80 | { |
81 | struct drm_i915_private *dev_priv = dev->dev_private; | |
82 | struct completion *x = &dev_priv->error_completion; | |
83 | unsigned long flags; | |
84 | int ret; | |
85 | ||
86 | if (!atomic_read(&dev_priv->mm.wedged)) | |
87 | return 0; | |
88 | ||
89 | ret = wait_for_completion_interruptible(x); | |
90 | if (ret) | |
91 | return ret; | |
92 | ||
21dd3734 CW |
93 | if (atomic_read(&dev_priv->mm.wedged)) { |
94 | /* GPU is hung, bump the completion count to account for | |
95 | * the token we just consumed so that we never hit zero and | |
96 | * end up waiting upon a subsequent completion event that | |
97 | * will never happen. | |
98 | */ | |
99 | spin_lock_irqsave(&x->wait.lock, flags); | |
100 | x->done++; | |
101 | spin_unlock_irqrestore(&x->wait.lock, flags); | |
102 | } | |
103 | return 0; | |
30dbf0c0 CW |
104 | } |
105 | ||
54cf91dc | 106 | int i915_mutex_lock_interruptible(struct drm_device *dev) |
76c1dec1 | 107 | { |
76c1dec1 CW |
108 | int ret; |
109 | ||
21dd3734 | 110 | ret = i915_gem_wait_for_error(dev); |
76c1dec1 CW |
111 | if (ret) |
112 | return ret; | |
113 | ||
114 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
115 | if (ret) | |
116 | return ret; | |
117 | ||
23bc5982 | 118 | WARN_ON(i915_verify_lists(dev)); |
76c1dec1 CW |
119 | return 0; |
120 | } | |
30dbf0c0 | 121 | |
7d1c4804 | 122 | static inline bool |
05394f39 | 123 | i915_gem_object_is_inactive(struct drm_i915_gem_object *obj) |
7d1c4804 | 124 | { |
05394f39 | 125 | return obj->gtt_space && !obj->active && obj->pin_count == 0; |
7d1c4804 CW |
126 | } |
127 | ||
2021746e CW |
128 | void i915_gem_do_init(struct drm_device *dev, |
129 | unsigned long start, | |
130 | unsigned long mappable_end, | |
131 | unsigned long end) | |
673a394b EA |
132 | { |
133 | drm_i915_private_t *dev_priv = dev->dev_private; | |
673a394b | 134 | |
bee4a186 | 135 | drm_mm_init(&dev_priv->mm.gtt_space, start, end - start); |
673a394b | 136 | |
bee4a186 CW |
137 | dev_priv->mm.gtt_start = start; |
138 | dev_priv->mm.gtt_mappable_end = mappable_end; | |
139 | dev_priv->mm.gtt_end = end; | |
73aa808f | 140 | dev_priv->mm.gtt_total = end - start; |
fb7d516a | 141 | dev_priv->mm.mappable_gtt_total = min(end, mappable_end) - start; |
bee4a186 CW |
142 | |
143 | /* Take over this portion of the GTT */ | |
144 | intel_gtt_clear_range(start / PAGE_SIZE, (end-start) / PAGE_SIZE); | |
79e53945 | 145 | } |
673a394b | 146 | |
79e53945 JB |
147 | int |
148 | i915_gem_init_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 149 | struct drm_file *file) |
79e53945 JB |
150 | { |
151 | struct drm_i915_gem_init *args = data; | |
2021746e CW |
152 | |
153 | if (args->gtt_start >= args->gtt_end || | |
154 | (args->gtt_end | args->gtt_start) & (PAGE_SIZE - 1)) | |
155 | return -EINVAL; | |
79e53945 JB |
156 | |
157 | mutex_lock(&dev->struct_mutex); | |
2021746e | 158 | i915_gem_do_init(dev, args->gtt_start, args->gtt_end, args->gtt_end); |
673a394b EA |
159 | mutex_unlock(&dev->struct_mutex); |
160 | ||
2021746e | 161 | return 0; |
673a394b EA |
162 | } |
163 | ||
5a125c3c EA |
164 | int |
165 | i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 166 | struct drm_file *file) |
5a125c3c | 167 | { |
73aa808f | 168 | struct drm_i915_private *dev_priv = dev->dev_private; |
5a125c3c | 169 | struct drm_i915_gem_get_aperture *args = data; |
6299f992 CW |
170 | struct drm_i915_gem_object *obj; |
171 | size_t pinned; | |
5a125c3c EA |
172 | |
173 | if (!(dev->driver->driver_features & DRIVER_GEM)) | |
174 | return -ENODEV; | |
175 | ||
6299f992 | 176 | pinned = 0; |
73aa808f | 177 | mutex_lock(&dev->struct_mutex); |
6299f992 CW |
178 | list_for_each_entry(obj, &dev_priv->mm.pinned_list, mm_list) |
179 | pinned += obj->gtt_space->size; | |
73aa808f | 180 | mutex_unlock(&dev->struct_mutex); |
5a125c3c | 181 | |
6299f992 | 182 | args->aper_size = dev_priv->mm.gtt_total; |
0206e353 | 183 | args->aper_available_size = args->aper_size - pinned; |
6299f992 | 184 | |
5a125c3c EA |
185 | return 0; |
186 | } | |
187 | ||
ff72145b DA |
188 | static int |
189 | i915_gem_create(struct drm_file *file, | |
190 | struct drm_device *dev, | |
191 | uint64_t size, | |
192 | uint32_t *handle_p) | |
673a394b | 193 | { |
05394f39 | 194 | struct drm_i915_gem_object *obj; |
a1a2d1d3 PP |
195 | int ret; |
196 | u32 handle; | |
673a394b | 197 | |
ff72145b | 198 | size = roundup(size, PAGE_SIZE); |
8ffc0246 CW |
199 | if (size == 0) |
200 | return -EINVAL; | |
673a394b EA |
201 | |
202 | /* Allocate the new object */ | |
ff72145b | 203 | obj = i915_gem_alloc_object(dev, size); |
673a394b EA |
204 | if (obj == NULL) |
205 | return -ENOMEM; | |
206 | ||
05394f39 | 207 | ret = drm_gem_handle_create(file, &obj->base, &handle); |
1dfd9754 | 208 | if (ret) { |
05394f39 CW |
209 | drm_gem_object_release(&obj->base); |
210 | i915_gem_info_remove_obj(dev->dev_private, obj->base.size); | |
202f2fef | 211 | kfree(obj); |
673a394b | 212 | return ret; |
1dfd9754 | 213 | } |
673a394b | 214 | |
202f2fef | 215 | /* drop reference from allocate - handle holds it now */ |
05394f39 | 216 | drm_gem_object_unreference(&obj->base); |
202f2fef CW |
217 | trace_i915_gem_object_create(obj); |
218 | ||
ff72145b | 219 | *handle_p = handle; |
673a394b EA |
220 | return 0; |
221 | } | |
222 | ||
ff72145b DA |
223 | int |
224 | i915_gem_dumb_create(struct drm_file *file, | |
225 | struct drm_device *dev, | |
226 | struct drm_mode_create_dumb *args) | |
227 | { | |
228 | /* have to work out size/pitch and return them */ | |
ed0291fd | 229 | args->pitch = ALIGN(args->width * ((args->bpp + 7) / 8), 64); |
ff72145b DA |
230 | args->size = args->pitch * args->height; |
231 | return i915_gem_create(file, dev, | |
232 | args->size, &args->handle); | |
233 | } | |
234 | ||
235 | int i915_gem_dumb_destroy(struct drm_file *file, | |
236 | struct drm_device *dev, | |
237 | uint32_t handle) | |
238 | { | |
239 | return drm_gem_handle_delete(file, handle); | |
240 | } | |
241 | ||
242 | /** | |
243 | * Creates a new mm object and returns a handle to it. | |
244 | */ | |
245 | int | |
246 | i915_gem_create_ioctl(struct drm_device *dev, void *data, | |
247 | struct drm_file *file) | |
248 | { | |
249 | struct drm_i915_gem_create *args = data; | |
250 | return i915_gem_create(file, dev, | |
251 | args->size, &args->handle); | |
252 | } | |
253 | ||
05394f39 | 254 | static int i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj) |
280b713b | 255 | { |
05394f39 | 256 | drm_i915_private_t *dev_priv = obj->base.dev->dev_private; |
280b713b EA |
257 | |
258 | return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 && | |
05394f39 | 259 | obj->tiling_mode != I915_TILING_NONE; |
280b713b EA |
260 | } |
261 | ||
eb01459f EA |
262 | /** |
263 | * This is the fast shmem pread path, which attempts to copy_from_user directly | |
264 | * from the backing pages of the object to the user's address space. On a | |
265 | * fault, it fails so we can fall back to i915_gem_shmem_pwrite_slow(). | |
266 | */ | |
267 | static int | |
05394f39 CW |
268 | i915_gem_shmem_pread_fast(struct drm_device *dev, |
269 | struct drm_i915_gem_object *obj, | |
eb01459f | 270 | struct drm_i915_gem_pread *args, |
05394f39 | 271 | struct drm_file *file) |
eb01459f | 272 | { |
05394f39 | 273 | struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping; |
eb01459f | 274 | ssize_t remain; |
e5281ccd | 275 | loff_t offset; |
eb01459f EA |
276 | char __user *user_data; |
277 | int page_offset, page_length; | |
eb01459f EA |
278 | |
279 | user_data = (char __user *) (uintptr_t) args->data_ptr; | |
280 | remain = args->size; | |
281 | ||
eb01459f EA |
282 | offset = args->offset; |
283 | ||
284 | while (remain > 0) { | |
e5281ccd CW |
285 | struct page *page; |
286 | char *vaddr; | |
287 | int ret; | |
288 | ||
eb01459f EA |
289 | /* Operation in this page |
290 | * | |
eb01459f EA |
291 | * page_offset = offset within page |
292 | * page_length = bytes to copy for this page | |
293 | */ | |
c8cbbb8b | 294 | page_offset = offset_in_page(offset); |
eb01459f EA |
295 | page_length = remain; |
296 | if ((page_offset + remain) > PAGE_SIZE) | |
297 | page_length = PAGE_SIZE - page_offset; | |
298 | ||
5949eac4 | 299 | page = shmem_read_mapping_page(mapping, offset >> PAGE_SHIFT); |
e5281ccd CW |
300 | if (IS_ERR(page)) |
301 | return PTR_ERR(page); | |
302 | ||
303 | vaddr = kmap_atomic(page); | |
304 | ret = __copy_to_user_inatomic(user_data, | |
305 | vaddr + page_offset, | |
306 | page_length); | |
307 | kunmap_atomic(vaddr); | |
308 | ||
309 | mark_page_accessed(page); | |
310 | page_cache_release(page); | |
311 | if (ret) | |
4f27b75d | 312 | return -EFAULT; |
eb01459f EA |
313 | |
314 | remain -= page_length; | |
315 | user_data += page_length; | |
316 | offset += page_length; | |
317 | } | |
318 | ||
4f27b75d | 319 | return 0; |
eb01459f EA |
320 | } |
321 | ||
8461d226 DV |
322 | static inline int |
323 | __copy_to_user_swizzled(char __user *cpu_vaddr, | |
324 | const char *gpu_vaddr, int gpu_offset, | |
325 | int length) | |
326 | { | |
327 | int ret, cpu_offset = 0; | |
328 | ||
329 | while (length > 0) { | |
330 | int cacheline_end = ALIGN(gpu_offset + 1, 64); | |
331 | int this_length = min(cacheline_end - gpu_offset, length); | |
332 | int swizzled_gpu_offset = gpu_offset ^ 64; | |
333 | ||
334 | ret = __copy_to_user(cpu_vaddr + cpu_offset, | |
335 | gpu_vaddr + swizzled_gpu_offset, | |
336 | this_length); | |
337 | if (ret) | |
338 | return ret + length; | |
339 | ||
340 | cpu_offset += this_length; | |
341 | gpu_offset += this_length; | |
342 | length -= this_length; | |
343 | } | |
344 | ||
345 | return 0; | |
346 | } | |
347 | ||
8c59967c DV |
348 | static inline int |
349 | __copy_from_user_swizzled(char __user *gpu_vaddr, int gpu_offset, | |
350 | const char *cpu_vaddr, | |
351 | int length) | |
352 | { | |
353 | int ret, cpu_offset = 0; | |
354 | ||
355 | while (length > 0) { | |
356 | int cacheline_end = ALIGN(gpu_offset + 1, 64); | |
357 | int this_length = min(cacheline_end - gpu_offset, length); | |
358 | int swizzled_gpu_offset = gpu_offset ^ 64; | |
359 | ||
360 | ret = __copy_from_user(gpu_vaddr + swizzled_gpu_offset, | |
361 | cpu_vaddr + cpu_offset, | |
362 | this_length); | |
363 | if (ret) | |
364 | return ret + length; | |
365 | ||
366 | cpu_offset += this_length; | |
367 | gpu_offset += this_length; | |
368 | length -= this_length; | |
369 | } | |
370 | ||
371 | return 0; | |
372 | } | |
373 | ||
eb01459f EA |
374 | /** |
375 | * This is the fallback shmem pread path, which allocates temporary storage | |
376 | * in kernel space to copy_to_user into outside of the struct_mutex, so we | |
377 | * can copy out of the object's backing pages while holding the struct mutex | |
378 | * and not take page faults. | |
379 | */ | |
380 | static int | |
05394f39 CW |
381 | i915_gem_shmem_pread_slow(struct drm_device *dev, |
382 | struct drm_i915_gem_object *obj, | |
eb01459f | 383 | struct drm_i915_gem_pread *args, |
05394f39 | 384 | struct drm_file *file) |
eb01459f | 385 | { |
05394f39 | 386 | struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping; |
8461d226 | 387 | char __user *user_data; |
eb01459f | 388 | ssize_t remain; |
8461d226 DV |
389 | loff_t offset; |
390 | int shmem_page_offset, page_length, ret; | |
391 | int obj_do_bit17_swizzling, page_do_bit17_swizzling; | |
eb01459f | 392 | |
8461d226 | 393 | user_data = (char __user *) (uintptr_t) args->data_ptr; |
eb01459f EA |
394 | remain = args->size; |
395 | ||
8461d226 | 396 | obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj); |
eb01459f | 397 | |
8461d226 | 398 | offset = args->offset; |
eb01459f | 399 | |
4f27b75d | 400 | mutex_unlock(&dev->struct_mutex); |
eb01459f EA |
401 | |
402 | while (remain > 0) { | |
e5281ccd | 403 | struct page *page; |
8461d226 | 404 | char *vaddr; |
e5281ccd | 405 | |
eb01459f EA |
406 | /* Operation in this page |
407 | * | |
eb01459f | 408 | * shmem_page_offset = offset within page in shmem file |
eb01459f EA |
409 | * page_length = bytes to copy for this page |
410 | */ | |
c8cbbb8b | 411 | shmem_page_offset = offset_in_page(offset); |
eb01459f EA |
412 | page_length = remain; |
413 | if ((shmem_page_offset + page_length) > PAGE_SIZE) | |
414 | page_length = PAGE_SIZE - shmem_page_offset; | |
eb01459f | 415 | |
5949eac4 | 416 | page = shmem_read_mapping_page(mapping, offset >> PAGE_SHIFT); |
b65552f0 JJ |
417 | if (IS_ERR(page)) { |
418 | ret = PTR_ERR(page); | |
419 | goto out; | |
420 | } | |
e5281ccd | 421 | |
8461d226 DV |
422 | page_do_bit17_swizzling = obj_do_bit17_swizzling && |
423 | (page_to_phys(page) & (1 << 17)) != 0; | |
424 | ||
425 | vaddr = kmap(page); | |
426 | if (page_do_bit17_swizzling) | |
427 | ret = __copy_to_user_swizzled(user_data, | |
428 | vaddr, shmem_page_offset, | |
429 | page_length); | |
430 | else | |
431 | ret = __copy_to_user(user_data, | |
432 | vaddr + shmem_page_offset, | |
433 | page_length); | |
434 | kunmap(page); | |
eb01459f | 435 | |
e5281ccd CW |
436 | mark_page_accessed(page); |
437 | page_cache_release(page); | |
438 | ||
8461d226 DV |
439 | if (ret) { |
440 | ret = -EFAULT; | |
441 | goto out; | |
442 | } | |
443 | ||
eb01459f | 444 | remain -= page_length; |
8461d226 | 445 | user_data += page_length; |
eb01459f EA |
446 | offset += page_length; |
447 | } | |
448 | ||
4f27b75d | 449 | out: |
8461d226 DV |
450 | mutex_lock(&dev->struct_mutex); |
451 | /* Fixup: Kill any reinstated backing storage pages */ | |
452 | if (obj->madv == __I915_MADV_PURGED) | |
453 | i915_gem_object_truncate(obj); | |
eb01459f EA |
454 | |
455 | return ret; | |
456 | } | |
457 | ||
673a394b EA |
458 | /** |
459 | * Reads data from the object referenced by handle. | |
460 | * | |
461 | * On error, the contents of *data are undefined. | |
462 | */ | |
463 | int | |
464 | i915_gem_pread_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 465 | struct drm_file *file) |
673a394b EA |
466 | { |
467 | struct drm_i915_gem_pread *args = data; | |
05394f39 | 468 | struct drm_i915_gem_object *obj; |
35b62a89 | 469 | int ret = 0; |
673a394b | 470 | |
51311d0a CW |
471 | if (args->size == 0) |
472 | return 0; | |
473 | ||
474 | if (!access_ok(VERIFY_WRITE, | |
475 | (char __user *)(uintptr_t)args->data_ptr, | |
476 | args->size)) | |
477 | return -EFAULT; | |
478 | ||
479 | ret = fault_in_pages_writeable((char __user *)(uintptr_t)args->data_ptr, | |
480 | args->size); | |
481 | if (ret) | |
482 | return -EFAULT; | |
483 | ||
4f27b75d | 484 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 485 | if (ret) |
4f27b75d | 486 | return ret; |
673a394b | 487 | |
05394f39 | 488 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 489 | if (&obj->base == NULL) { |
1d7cfea1 CW |
490 | ret = -ENOENT; |
491 | goto unlock; | |
4f27b75d | 492 | } |
673a394b | 493 | |
7dcd2499 | 494 | /* Bounds check source. */ |
05394f39 CW |
495 | if (args->offset > obj->base.size || |
496 | args->size > obj->base.size - args->offset) { | |
ce9d419d | 497 | ret = -EINVAL; |
35b62a89 | 498 | goto out; |
ce9d419d CW |
499 | } |
500 | ||
db53a302 CW |
501 | trace_i915_gem_object_pread(obj, args->offset, args->size); |
502 | ||
4f27b75d CW |
503 | ret = i915_gem_object_set_cpu_read_domain_range(obj, |
504 | args->offset, | |
505 | args->size); | |
506 | if (ret) | |
e5281ccd | 507 | goto out; |
4f27b75d CW |
508 | |
509 | ret = -EFAULT; | |
510 | if (!i915_gem_object_needs_bit17_swizzle(obj)) | |
05394f39 | 511 | ret = i915_gem_shmem_pread_fast(dev, obj, args, file); |
4f27b75d | 512 | if (ret == -EFAULT) |
05394f39 | 513 | ret = i915_gem_shmem_pread_slow(dev, obj, args, file); |
673a394b | 514 | |
35b62a89 | 515 | out: |
05394f39 | 516 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 517 | unlock: |
4f27b75d | 518 | mutex_unlock(&dev->struct_mutex); |
eb01459f | 519 | return ret; |
673a394b EA |
520 | } |
521 | ||
0839ccb8 KP |
522 | /* This is the fast write path which cannot handle |
523 | * page faults in the source data | |
9b7530cc | 524 | */ |
0839ccb8 KP |
525 | |
526 | static inline int | |
527 | fast_user_write(struct io_mapping *mapping, | |
528 | loff_t page_base, int page_offset, | |
529 | char __user *user_data, | |
530 | int length) | |
9b7530cc | 531 | { |
9b7530cc | 532 | char *vaddr_atomic; |
0839ccb8 | 533 | unsigned long unwritten; |
9b7530cc | 534 | |
3e4d3af5 | 535 | vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base); |
0839ccb8 KP |
536 | unwritten = __copy_from_user_inatomic_nocache(vaddr_atomic + page_offset, |
537 | user_data, length); | |
3e4d3af5 | 538 | io_mapping_unmap_atomic(vaddr_atomic); |
fbd5a26d | 539 | return unwritten; |
0839ccb8 KP |
540 | } |
541 | ||
542 | /* Here's the write path which can sleep for | |
543 | * page faults | |
544 | */ | |
545 | ||
ab34c226 | 546 | static inline void |
3de09aa3 EA |
547 | slow_kernel_write(struct io_mapping *mapping, |
548 | loff_t gtt_base, int gtt_offset, | |
549 | struct page *user_page, int user_offset, | |
550 | int length) | |
0839ccb8 | 551 | { |
ab34c226 CW |
552 | char __iomem *dst_vaddr; |
553 | char *src_vaddr; | |
0839ccb8 | 554 | |
ab34c226 CW |
555 | dst_vaddr = io_mapping_map_wc(mapping, gtt_base); |
556 | src_vaddr = kmap(user_page); | |
557 | ||
558 | memcpy_toio(dst_vaddr + gtt_offset, | |
559 | src_vaddr + user_offset, | |
560 | length); | |
561 | ||
562 | kunmap(user_page); | |
563 | io_mapping_unmap(dst_vaddr); | |
9b7530cc LT |
564 | } |
565 | ||
3de09aa3 EA |
566 | /** |
567 | * This is the fast pwrite path, where we copy the data directly from the | |
568 | * user into the GTT, uncached. | |
569 | */ | |
673a394b | 570 | static int |
05394f39 CW |
571 | i915_gem_gtt_pwrite_fast(struct drm_device *dev, |
572 | struct drm_i915_gem_object *obj, | |
3de09aa3 | 573 | struct drm_i915_gem_pwrite *args, |
05394f39 | 574 | struct drm_file *file) |
673a394b | 575 | { |
0839ccb8 | 576 | drm_i915_private_t *dev_priv = dev->dev_private; |
673a394b | 577 | ssize_t remain; |
0839ccb8 | 578 | loff_t offset, page_base; |
673a394b | 579 | char __user *user_data; |
0839ccb8 | 580 | int page_offset, page_length; |
673a394b EA |
581 | |
582 | user_data = (char __user *) (uintptr_t) args->data_ptr; | |
583 | remain = args->size; | |
673a394b | 584 | |
05394f39 | 585 | offset = obj->gtt_offset + args->offset; |
673a394b EA |
586 | |
587 | while (remain > 0) { | |
588 | /* Operation in this page | |
589 | * | |
0839ccb8 KP |
590 | * page_base = page offset within aperture |
591 | * page_offset = offset within page | |
592 | * page_length = bytes to copy for this page | |
673a394b | 593 | */ |
c8cbbb8b CW |
594 | page_base = offset & PAGE_MASK; |
595 | page_offset = offset_in_page(offset); | |
0839ccb8 KP |
596 | page_length = remain; |
597 | if ((page_offset + remain) > PAGE_SIZE) | |
598 | page_length = PAGE_SIZE - page_offset; | |
599 | ||
0839ccb8 | 600 | /* If we get a fault while copying data, then (presumably) our |
3de09aa3 EA |
601 | * source page isn't available. Return the error and we'll |
602 | * retry in the slow path. | |
0839ccb8 | 603 | */ |
fbd5a26d CW |
604 | if (fast_user_write(dev_priv->mm.gtt_mapping, page_base, |
605 | page_offset, user_data, page_length)) | |
fbd5a26d | 606 | return -EFAULT; |
673a394b | 607 | |
0839ccb8 KP |
608 | remain -= page_length; |
609 | user_data += page_length; | |
610 | offset += page_length; | |
673a394b | 611 | } |
673a394b | 612 | |
fbd5a26d | 613 | return 0; |
673a394b EA |
614 | } |
615 | ||
3de09aa3 EA |
616 | /** |
617 | * This is the fallback GTT pwrite path, which uses get_user_pages to pin | |
618 | * the memory and maps it using kmap_atomic for copying. | |
619 | * | |
620 | * This code resulted in x11perf -rgb10text consuming about 10% more CPU | |
621 | * than using i915_gem_gtt_pwrite_fast on a G45 (32-bit). | |
622 | */ | |
3043c60c | 623 | static int |
05394f39 CW |
624 | i915_gem_gtt_pwrite_slow(struct drm_device *dev, |
625 | struct drm_i915_gem_object *obj, | |
3de09aa3 | 626 | struct drm_i915_gem_pwrite *args, |
05394f39 | 627 | struct drm_file *file) |
673a394b | 628 | { |
3de09aa3 EA |
629 | drm_i915_private_t *dev_priv = dev->dev_private; |
630 | ssize_t remain; | |
631 | loff_t gtt_page_base, offset; | |
632 | loff_t first_data_page, last_data_page, num_pages; | |
633 | loff_t pinned_pages, i; | |
634 | struct page **user_pages; | |
635 | struct mm_struct *mm = current->mm; | |
636 | int gtt_page_offset, data_page_offset, data_page_index, page_length; | |
673a394b | 637 | int ret; |
3de09aa3 EA |
638 | uint64_t data_ptr = args->data_ptr; |
639 | ||
640 | remain = args->size; | |
641 | ||
642 | /* Pin the user pages containing the data. We can't fault while | |
643 | * holding the struct mutex, and all of the pwrite implementations | |
644 | * want to hold it while dereferencing the user data. | |
645 | */ | |
646 | first_data_page = data_ptr / PAGE_SIZE; | |
647 | last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE; | |
648 | num_pages = last_data_page - first_data_page + 1; | |
649 | ||
fbd5a26d | 650 | user_pages = drm_malloc_ab(num_pages, sizeof(struct page *)); |
3de09aa3 EA |
651 | if (user_pages == NULL) |
652 | return -ENOMEM; | |
653 | ||
fbd5a26d | 654 | mutex_unlock(&dev->struct_mutex); |
3de09aa3 EA |
655 | down_read(&mm->mmap_sem); |
656 | pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr, | |
657 | num_pages, 0, 0, user_pages, NULL); | |
658 | up_read(&mm->mmap_sem); | |
fbd5a26d | 659 | mutex_lock(&dev->struct_mutex); |
3de09aa3 EA |
660 | if (pinned_pages < num_pages) { |
661 | ret = -EFAULT; | |
662 | goto out_unpin_pages; | |
663 | } | |
673a394b | 664 | |
d9e86c0e CW |
665 | ret = i915_gem_object_set_to_gtt_domain(obj, true); |
666 | if (ret) | |
667 | goto out_unpin_pages; | |
668 | ||
669 | ret = i915_gem_object_put_fence(obj); | |
3de09aa3 | 670 | if (ret) |
fbd5a26d | 671 | goto out_unpin_pages; |
3de09aa3 | 672 | |
05394f39 | 673 | offset = obj->gtt_offset + args->offset; |
3de09aa3 EA |
674 | |
675 | while (remain > 0) { | |
676 | /* Operation in this page | |
677 | * | |
678 | * gtt_page_base = page offset within aperture | |
679 | * gtt_page_offset = offset within page in aperture | |
680 | * data_page_index = page number in get_user_pages return | |
681 | * data_page_offset = offset with data_page_index page. | |
682 | * page_length = bytes to copy for this page | |
683 | */ | |
684 | gtt_page_base = offset & PAGE_MASK; | |
c8cbbb8b | 685 | gtt_page_offset = offset_in_page(offset); |
3de09aa3 | 686 | data_page_index = data_ptr / PAGE_SIZE - first_data_page; |
c8cbbb8b | 687 | data_page_offset = offset_in_page(data_ptr); |
3de09aa3 EA |
688 | |
689 | page_length = remain; | |
690 | if ((gtt_page_offset + page_length) > PAGE_SIZE) | |
691 | page_length = PAGE_SIZE - gtt_page_offset; | |
692 | if ((data_page_offset + page_length) > PAGE_SIZE) | |
693 | page_length = PAGE_SIZE - data_page_offset; | |
694 | ||
ab34c226 CW |
695 | slow_kernel_write(dev_priv->mm.gtt_mapping, |
696 | gtt_page_base, gtt_page_offset, | |
697 | user_pages[data_page_index], | |
698 | data_page_offset, | |
699 | page_length); | |
3de09aa3 EA |
700 | |
701 | remain -= page_length; | |
702 | offset += page_length; | |
703 | data_ptr += page_length; | |
704 | } | |
705 | ||
3de09aa3 EA |
706 | out_unpin_pages: |
707 | for (i = 0; i < pinned_pages; i++) | |
708 | page_cache_release(user_pages[i]); | |
8e7d2b2c | 709 | drm_free_large(user_pages); |
3de09aa3 EA |
710 | |
711 | return ret; | |
712 | } | |
713 | ||
40123c1f EA |
714 | /** |
715 | * This is the fast shmem pwrite path, which attempts to directly | |
716 | * copy_from_user into the kmapped pages backing the object. | |
717 | */ | |
3043c60c | 718 | static int |
05394f39 CW |
719 | i915_gem_shmem_pwrite_fast(struct drm_device *dev, |
720 | struct drm_i915_gem_object *obj, | |
40123c1f | 721 | struct drm_i915_gem_pwrite *args, |
05394f39 | 722 | struct drm_file *file) |
673a394b | 723 | { |
05394f39 | 724 | struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping; |
40123c1f | 725 | ssize_t remain; |
e5281ccd | 726 | loff_t offset; |
40123c1f EA |
727 | char __user *user_data; |
728 | int page_offset, page_length; | |
40123c1f EA |
729 | |
730 | user_data = (char __user *) (uintptr_t) args->data_ptr; | |
731 | remain = args->size; | |
673a394b | 732 | |
40123c1f | 733 | offset = args->offset; |
05394f39 | 734 | obj->dirty = 1; |
40123c1f EA |
735 | |
736 | while (remain > 0) { | |
e5281ccd CW |
737 | struct page *page; |
738 | char *vaddr; | |
739 | int ret; | |
740 | ||
40123c1f EA |
741 | /* Operation in this page |
742 | * | |
40123c1f EA |
743 | * page_offset = offset within page |
744 | * page_length = bytes to copy for this page | |
745 | */ | |
c8cbbb8b | 746 | page_offset = offset_in_page(offset); |
40123c1f EA |
747 | page_length = remain; |
748 | if ((page_offset + remain) > PAGE_SIZE) | |
749 | page_length = PAGE_SIZE - page_offset; | |
750 | ||
5949eac4 | 751 | page = shmem_read_mapping_page(mapping, offset >> PAGE_SHIFT); |
e5281ccd CW |
752 | if (IS_ERR(page)) |
753 | return PTR_ERR(page); | |
754 | ||
130c2561 | 755 | vaddr = kmap_atomic(page); |
e5281ccd CW |
756 | ret = __copy_from_user_inatomic(vaddr + page_offset, |
757 | user_data, | |
758 | page_length); | |
130c2561 | 759 | kunmap_atomic(vaddr); |
e5281ccd CW |
760 | |
761 | set_page_dirty(page); | |
762 | mark_page_accessed(page); | |
763 | page_cache_release(page); | |
764 | ||
765 | /* If we get a fault while copying data, then (presumably) our | |
766 | * source page isn't available. Return the error and we'll | |
767 | * retry in the slow path. | |
768 | */ | |
769 | if (ret) | |
fbd5a26d | 770 | return -EFAULT; |
40123c1f EA |
771 | |
772 | remain -= page_length; | |
773 | user_data += page_length; | |
774 | offset += page_length; | |
775 | } | |
776 | ||
fbd5a26d | 777 | return 0; |
40123c1f EA |
778 | } |
779 | ||
780 | /** | |
781 | * This is the fallback shmem pwrite path, which uses get_user_pages to pin | |
782 | * the memory and maps it using kmap_atomic for copying. | |
783 | * | |
784 | * This avoids taking mmap_sem for faulting on the user's address while the | |
785 | * struct_mutex is held. | |
786 | */ | |
787 | static int | |
05394f39 CW |
788 | i915_gem_shmem_pwrite_slow(struct drm_device *dev, |
789 | struct drm_i915_gem_object *obj, | |
40123c1f | 790 | struct drm_i915_gem_pwrite *args, |
05394f39 | 791 | struct drm_file *file) |
40123c1f | 792 | { |
05394f39 | 793 | struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping; |
40123c1f | 794 | ssize_t remain; |
8c59967c DV |
795 | loff_t offset; |
796 | char __user *user_data; | |
797 | int shmem_page_offset, page_length, ret; | |
798 | int obj_do_bit17_swizzling, page_do_bit17_swizzling; | |
40123c1f | 799 | |
8c59967c | 800 | user_data = (char __user *) (uintptr_t) args->data_ptr; |
40123c1f EA |
801 | remain = args->size; |
802 | ||
8c59967c | 803 | obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj); |
40123c1f | 804 | |
673a394b | 805 | offset = args->offset; |
05394f39 | 806 | obj->dirty = 1; |
673a394b | 807 | |
8c59967c DV |
808 | mutex_unlock(&dev->struct_mutex); |
809 | ||
40123c1f | 810 | while (remain > 0) { |
e5281ccd | 811 | struct page *page; |
8c59967c | 812 | char *vaddr; |
e5281ccd | 813 | |
40123c1f EA |
814 | /* Operation in this page |
815 | * | |
40123c1f | 816 | * shmem_page_offset = offset within page in shmem file |
40123c1f EA |
817 | * page_length = bytes to copy for this page |
818 | */ | |
c8cbbb8b | 819 | shmem_page_offset = offset_in_page(offset); |
40123c1f EA |
820 | |
821 | page_length = remain; | |
822 | if ((shmem_page_offset + page_length) > PAGE_SIZE) | |
823 | page_length = PAGE_SIZE - shmem_page_offset; | |
40123c1f | 824 | |
5949eac4 | 825 | page = shmem_read_mapping_page(mapping, offset >> PAGE_SHIFT); |
e5281ccd CW |
826 | if (IS_ERR(page)) { |
827 | ret = PTR_ERR(page); | |
828 | goto out; | |
829 | } | |
830 | ||
8c59967c DV |
831 | page_do_bit17_swizzling = obj_do_bit17_swizzling && |
832 | (page_to_phys(page) & (1 << 17)) != 0; | |
833 | ||
834 | vaddr = kmap(page); | |
835 | if (page_do_bit17_swizzling) | |
836 | ret = __copy_from_user_swizzled(vaddr, shmem_page_offset, | |
837 | user_data, | |
838 | page_length); | |
839 | else | |
840 | ret = __copy_from_user(vaddr + shmem_page_offset, | |
841 | user_data, | |
842 | page_length); | |
843 | kunmap(page); | |
40123c1f | 844 | |
e5281ccd CW |
845 | set_page_dirty(page); |
846 | mark_page_accessed(page); | |
847 | page_cache_release(page); | |
848 | ||
8c59967c DV |
849 | if (ret) { |
850 | ret = -EFAULT; | |
851 | goto out; | |
852 | } | |
853 | ||
40123c1f | 854 | remain -= page_length; |
8c59967c | 855 | user_data += page_length; |
40123c1f | 856 | offset += page_length; |
673a394b EA |
857 | } |
858 | ||
fbd5a26d | 859 | out: |
8c59967c DV |
860 | mutex_lock(&dev->struct_mutex); |
861 | /* Fixup: Kill any reinstated backing storage pages */ | |
862 | if (obj->madv == __I915_MADV_PURGED) | |
863 | i915_gem_object_truncate(obj); | |
864 | /* and flush dirty cachelines in case the object isn't in the cpu write | |
865 | * domain anymore. */ | |
866 | if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) { | |
867 | i915_gem_clflush_object(obj); | |
868 | intel_gtt_chipset_flush(); | |
869 | } | |
673a394b | 870 | |
40123c1f | 871 | return ret; |
673a394b EA |
872 | } |
873 | ||
874 | /** | |
875 | * Writes data to the object referenced by handle. | |
876 | * | |
877 | * On error, the contents of the buffer that were to be modified are undefined. | |
878 | */ | |
879 | int | |
880 | i915_gem_pwrite_ioctl(struct drm_device *dev, void *data, | |
fbd5a26d | 881 | struct drm_file *file) |
673a394b EA |
882 | { |
883 | struct drm_i915_gem_pwrite *args = data; | |
05394f39 | 884 | struct drm_i915_gem_object *obj; |
51311d0a CW |
885 | int ret; |
886 | ||
887 | if (args->size == 0) | |
888 | return 0; | |
889 | ||
890 | if (!access_ok(VERIFY_READ, | |
891 | (char __user *)(uintptr_t)args->data_ptr, | |
892 | args->size)) | |
893 | return -EFAULT; | |
894 | ||
895 | ret = fault_in_pages_readable((char __user *)(uintptr_t)args->data_ptr, | |
896 | args->size); | |
897 | if (ret) | |
898 | return -EFAULT; | |
673a394b | 899 | |
fbd5a26d | 900 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 901 | if (ret) |
fbd5a26d | 902 | return ret; |
1d7cfea1 | 903 | |
05394f39 | 904 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 905 | if (&obj->base == NULL) { |
1d7cfea1 CW |
906 | ret = -ENOENT; |
907 | goto unlock; | |
fbd5a26d | 908 | } |
673a394b | 909 | |
7dcd2499 | 910 | /* Bounds check destination. */ |
05394f39 CW |
911 | if (args->offset > obj->base.size || |
912 | args->size > obj->base.size - args->offset) { | |
ce9d419d | 913 | ret = -EINVAL; |
35b62a89 | 914 | goto out; |
ce9d419d CW |
915 | } |
916 | ||
db53a302 CW |
917 | trace_i915_gem_object_pwrite(obj, args->offset, args->size); |
918 | ||
673a394b EA |
919 | /* We can only do the GTT pwrite on untiled buffers, as otherwise |
920 | * it would end up going through the fenced access, and we'll get | |
921 | * different detiling behavior between reading and writing. | |
922 | * pread/pwrite currently are reading and writing from the CPU | |
923 | * perspective, requiring manual detiling by the client. | |
924 | */ | |
5c0480f2 | 925 | if (obj->phys_obj) { |
fbd5a26d | 926 | ret = i915_gem_phys_pwrite(dev, obj, args, file); |
5c0480f2 DV |
927 | goto out; |
928 | } | |
929 | ||
930 | if (obj->gtt_space && | |
931 | obj->base.write_domain != I915_GEM_DOMAIN_CPU) { | |
75e9e915 | 932 | ret = i915_gem_object_pin(obj, 0, true); |
fbd5a26d CW |
933 | if (ret) |
934 | goto out; | |
935 | ||
d9e86c0e CW |
936 | ret = i915_gem_object_set_to_gtt_domain(obj, true); |
937 | if (ret) | |
938 | goto out_unpin; | |
939 | ||
940 | ret = i915_gem_object_put_fence(obj); | |
fbd5a26d CW |
941 | if (ret) |
942 | goto out_unpin; | |
943 | ||
944 | ret = i915_gem_gtt_pwrite_fast(dev, obj, args, file); | |
945 | if (ret == -EFAULT) | |
946 | ret = i915_gem_gtt_pwrite_slow(dev, obj, args, file); | |
947 | ||
948 | out_unpin: | |
949 | i915_gem_object_unpin(obj); | |
673a394b | 950 | |
5c0480f2 DV |
951 | if (ret != -EFAULT) |
952 | goto out; | |
953 | /* Fall through to the shmfs paths because the gtt paths might | |
954 | * fail with non-page-backed user pointers (e.g. gtt mappings | |
955 | * when moving data between textures). */ | |
fbd5a26d | 956 | } |
673a394b | 957 | |
5c0480f2 DV |
958 | ret = i915_gem_object_set_to_cpu_domain(obj, 1); |
959 | if (ret) | |
960 | goto out; | |
961 | ||
962 | ret = -EFAULT; | |
963 | if (!i915_gem_object_needs_bit17_swizzle(obj)) | |
964 | ret = i915_gem_shmem_pwrite_fast(dev, obj, args, file); | |
965 | if (ret == -EFAULT) | |
966 | ret = i915_gem_shmem_pwrite_slow(dev, obj, args, file); | |
967 | ||
35b62a89 | 968 | out: |
05394f39 | 969 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 970 | unlock: |
fbd5a26d | 971 | mutex_unlock(&dev->struct_mutex); |
673a394b EA |
972 | return ret; |
973 | } | |
974 | ||
975 | /** | |
2ef7eeaa EA |
976 | * Called when user space prepares to use an object with the CPU, either |
977 | * through the mmap ioctl's mapping or a GTT mapping. | |
673a394b EA |
978 | */ |
979 | int | |
980 | i915_gem_set_domain_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 981 | struct drm_file *file) |
673a394b EA |
982 | { |
983 | struct drm_i915_gem_set_domain *args = data; | |
05394f39 | 984 | struct drm_i915_gem_object *obj; |
2ef7eeaa EA |
985 | uint32_t read_domains = args->read_domains; |
986 | uint32_t write_domain = args->write_domain; | |
673a394b EA |
987 | int ret; |
988 | ||
989 | if (!(dev->driver->driver_features & DRIVER_GEM)) | |
990 | return -ENODEV; | |
991 | ||
2ef7eeaa | 992 | /* Only handle setting domains to types used by the CPU. */ |
21d509e3 | 993 | if (write_domain & I915_GEM_GPU_DOMAINS) |
2ef7eeaa EA |
994 | return -EINVAL; |
995 | ||
21d509e3 | 996 | if (read_domains & I915_GEM_GPU_DOMAINS) |
2ef7eeaa EA |
997 | return -EINVAL; |
998 | ||
999 | /* Having something in the write domain implies it's in the read | |
1000 | * domain, and only that read domain. Enforce that in the request. | |
1001 | */ | |
1002 | if (write_domain != 0 && read_domains != write_domain) | |
1003 | return -EINVAL; | |
1004 | ||
76c1dec1 | 1005 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 1006 | if (ret) |
76c1dec1 | 1007 | return ret; |
1d7cfea1 | 1008 | |
05394f39 | 1009 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 1010 | if (&obj->base == NULL) { |
1d7cfea1 CW |
1011 | ret = -ENOENT; |
1012 | goto unlock; | |
76c1dec1 | 1013 | } |
673a394b | 1014 | |
2ef7eeaa EA |
1015 | if (read_domains & I915_GEM_DOMAIN_GTT) { |
1016 | ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0); | |
02354392 EA |
1017 | |
1018 | /* Silently promote "you're not bound, there was nothing to do" | |
1019 | * to success, since the client was just asking us to | |
1020 | * make sure everything was done. | |
1021 | */ | |
1022 | if (ret == -EINVAL) | |
1023 | ret = 0; | |
2ef7eeaa | 1024 | } else { |
e47c68e9 | 1025 | ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0); |
2ef7eeaa EA |
1026 | } |
1027 | ||
05394f39 | 1028 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 1029 | unlock: |
673a394b EA |
1030 | mutex_unlock(&dev->struct_mutex); |
1031 | return ret; | |
1032 | } | |
1033 | ||
1034 | /** | |
1035 | * Called when user space has done writes to this buffer | |
1036 | */ | |
1037 | int | |
1038 | i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 1039 | struct drm_file *file) |
673a394b EA |
1040 | { |
1041 | struct drm_i915_gem_sw_finish *args = data; | |
05394f39 | 1042 | struct drm_i915_gem_object *obj; |
673a394b EA |
1043 | int ret = 0; |
1044 | ||
1045 | if (!(dev->driver->driver_features & DRIVER_GEM)) | |
1046 | return -ENODEV; | |
1047 | ||
76c1dec1 | 1048 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 1049 | if (ret) |
76c1dec1 | 1050 | return ret; |
1d7cfea1 | 1051 | |
05394f39 | 1052 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 1053 | if (&obj->base == NULL) { |
1d7cfea1 CW |
1054 | ret = -ENOENT; |
1055 | goto unlock; | |
673a394b EA |
1056 | } |
1057 | ||
673a394b | 1058 | /* Pinned buffers may be scanout, so flush the cache */ |
05394f39 | 1059 | if (obj->pin_count) |
e47c68e9 EA |
1060 | i915_gem_object_flush_cpu_write_domain(obj); |
1061 | ||
05394f39 | 1062 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 1063 | unlock: |
673a394b EA |
1064 | mutex_unlock(&dev->struct_mutex); |
1065 | return ret; | |
1066 | } | |
1067 | ||
1068 | /** | |
1069 | * Maps the contents of an object, returning the address it is mapped | |
1070 | * into. | |
1071 | * | |
1072 | * While the mapping holds a reference on the contents of the object, it doesn't | |
1073 | * imply a ref on the object itself. | |
1074 | */ | |
1075 | int | |
1076 | i915_gem_mmap_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 1077 | struct drm_file *file) |
673a394b EA |
1078 | { |
1079 | struct drm_i915_gem_mmap *args = data; | |
1080 | struct drm_gem_object *obj; | |
673a394b EA |
1081 | unsigned long addr; |
1082 | ||
1083 | if (!(dev->driver->driver_features & DRIVER_GEM)) | |
1084 | return -ENODEV; | |
1085 | ||
05394f39 | 1086 | obj = drm_gem_object_lookup(dev, file, args->handle); |
673a394b | 1087 | if (obj == NULL) |
bf79cb91 | 1088 | return -ENOENT; |
673a394b | 1089 | |
673a394b EA |
1090 | down_write(¤t->mm->mmap_sem); |
1091 | addr = do_mmap(obj->filp, 0, args->size, | |
1092 | PROT_READ | PROT_WRITE, MAP_SHARED, | |
1093 | args->offset); | |
1094 | up_write(¤t->mm->mmap_sem); | |
bc9025bd | 1095 | drm_gem_object_unreference_unlocked(obj); |
673a394b EA |
1096 | if (IS_ERR((void *)addr)) |
1097 | return addr; | |
1098 | ||
1099 | args->addr_ptr = (uint64_t) addr; | |
1100 | ||
1101 | return 0; | |
1102 | } | |
1103 | ||
de151cf6 JB |
1104 | /** |
1105 | * i915_gem_fault - fault a page into the GTT | |
1106 | * vma: VMA in question | |
1107 | * vmf: fault info | |
1108 | * | |
1109 | * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped | |
1110 | * from userspace. The fault handler takes care of binding the object to | |
1111 | * the GTT (if needed), allocating and programming a fence register (again, | |
1112 | * only if needed based on whether the old reg is still valid or the object | |
1113 | * is tiled) and inserting a new PTE into the faulting process. | |
1114 | * | |
1115 | * Note that the faulting process may involve evicting existing objects | |
1116 | * from the GTT and/or fence registers to make room. So performance may | |
1117 | * suffer if the GTT working set is large or there are few fence registers | |
1118 | * left. | |
1119 | */ | |
1120 | int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf) | |
1121 | { | |
05394f39 CW |
1122 | struct drm_i915_gem_object *obj = to_intel_bo(vma->vm_private_data); |
1123 | struct drm_device *dev = obj->base.dev; | |
7d1c4804 | 1124 | drm_i915_private_t *dev_priv = dev->dev_private; |
de151cf6 JB |
1125 | pgoff_t page_offset; |
1126 | unsigned long pfn; | |
1127 | int ret = 0; | |
0f973f27 | 1128 | bool write = !!(vmf->flags & FAULT_FLAG_WRITE); |
de151cf6 JB |
1129 | |
1130 | /* We don't use vmf->pgoff since that has the fake offset */ | |
1131 | page_offset = ((unsigned long)vmf->virtual_address - vma->vm_start) >> | |
1132 | PAGE_SHIFT; | |
1133 | ||
d9bc7e9f CW |
1134 | ret = i915_mutex_lock_interruptible(dev); |
1135 | if (ret) | |
1136 | goto out; | |
a00b10c3 | 1137 | |
db53a302 CW |
1138 | trace_i915_gem_object_fault(obj, page_offset, true, write); |
1139 | ||
d9bc7e9f | 1140 | /* Now bind it into the GTT if needed */ |
919926ae CW |
1141 | if (!obj->map_and_fenceable) { |
1142 | ret = i915_gem_object_unbind(obj); | |
1143 | if (ret) | |
1144 | goto unlock; | |
a00b10c3 | 1145 | } |
05394f39 | 1146 | if (!obj->gtt_space) { |
75e9e915 | 1147 | ret = i915_gem_object_bind_to_gtt(obj, 0, true); |
c715089f CW |
1148 | if (ret) |
1149 | goto unlock; | |
de151cf6 | 1150 | |
e92d03bf EA |
1151 | ret = i915_gem_object_set_to_gtt_domain(obj, write); |
1152 | if (ret) | |
1153 | goto unlock; | |
1154 | } | |
4a684a41 | 1155 | |
d9e86c0e CW |
1156 | if (obj->tiling_mode == I915_TILING_NONE) |
1157 | ret = i915_gem_object_put_fence(obj); | |
1158 | else | |
ce453d81 | 1159 | ret = i915_gem_object_get_fence(obj, NULL); |
d9e86c0e CW |
1160 | if (ret) |
1161 | goto unlock; | |
de151cf6 | 1162 | |
05394f39 CW |
1163 | if (i915_gem_object_is_inactive(obj)) |
1164 | list_move_tail(&obj->mm_list, &dev_priv->mm.inactive_list); | |
7d1c4804 | 1165 | |
6299f992 CW |
1166 | obj->fault_mappable = true; |
1167 | ||
05394f39 | 1168 | pfn = ((dev->agp->base + obj->gtt_offset) >> PAGE_SHIFT) + |
de151cf6 JB |
1169 | page_offset; |
1170 | ||
1171 | /* Finally, remap it using the new GTT offset */ | |
1172 | ret = vm_insert_pfn(vma, (unsigned long)vmf->virtual_address, pfn); | |
c715089f | 1173 | unlock: |
de151cf6 | 1174 | mutex_unlock(&dev->struct_mutex); |
d9bc7e9f | 1175 | out: |
de151cf6 | 1176 | switch (ret) { |
d9bc7e9f | 1177 | case -EIO: |
045e769a | 1178 | case -EAGAIN: |
d9bc7e9f CW |
1179 | /* Give the error handler a chance to run and move the |
1180 | * objects off the GPU active list. Next time we service the | |
1181 | * fault, we should be able to transition the page into the | |
1182 | * GTT without touching the GPU (and so avoid further | |
1183 | * EIO/EGAIN). If the GPU is wedged, then there is no issue | |
1184 | * with coherency, just lost writes. | |
1185 | */ | |
045e769a | 1186 | set_need_resched(); |
c715089f CW |
1187 | case 0: |
1188 | case -ERESTARTSYS: | |
bed636ab | 1189 | case -EINTR: |
c715089f | 1190 | return VM_FAULT_NOPAGE; |
de151cf6 | 1191 | case -ENOMEM: |
de151cf6 | 1192 | return VM_FAULT_OOM; |
de151cf6 | 1193 | default: |
c715089f | 1194 | return VM_FAULT_SIGBUS; |
de151cf6 JB |
1195 | } |
1196 | } | |
1197 | ||
901782b2 CW |
1198 | /** |
1199 | * i915_gem_release_mmap - remove physical page mappings | |
1200 | * @obj: obj in question | |
1201 | * | |
af901ca1 | 1202 | * Preserve the reservation of the mmapping with the DRM core code, but |
901782b2 CW |
1203 | * relinquish ownership of the pages back to the system. |
1204 | * | |
1205 | * It is vital that we remove the page mapping if we have mapped a tiled | |
1206 | * object through the GTT and then lose the fence register due to | |
1207 | * resource pressure. Similarly if the object has been moved out of the | |
1208 | * aperture, than pages mapped into userspace must be revoked. Removing the | |
1209 | * mapping will then trigger a page fault on the next user access, allowing | |
1210 | * fixup by i915_gem_fault(). | |
1211 | */ | |
d05ca301 | 1212 | void |
05394f39 | 1213 | i915_gem_release_mmap(struct drm_i915_gem_object *obj) |
901782b2 | 1214 | { |
6299f992 CW |
1215 | if (!obj->fault_mappable) |
1216 | return; | |
901782b2 | 1217 | |
f6e47884 CW |
1218 | if (obj->base.dev->dev_mapping) |
1219 | unmap_mapping_range(obj->base.dev->dev_mapping, | |
1220 | (loff_t)obj->base.map_list.hash.key<<PAGE_SHIFT, | |
1221 | obj->base.size, 1); | |
fb7d516a | 1222 | |
6299f992 | 1223 | obj->fault_mappable = false; |
901782b2 CW |
1224 | } |
1225 | ||
92b88aeb | 1226 | static uint32_t |
e28f8711 | 1227 | i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode) |
92b88aeb | 1228 | { |
e28f8711 | 1229 | uint32_t gtt_size; |
92b88aeb CW |
1230 | |
1231 | if (INTEL_INFO(dev)->gen >= 4 || | |
e28f8711 CW |
1232 | tiling_mode == I915_TILING_NONE) |
1233 | return size; | |
92b88aeb CW |
1234 | |
1235 | /* Previous chips need a power-of-two fence region when tiling */ | |
1236 | if (INTEL_INFO(dev)->gen == 3) | |
e28f8711 | 1237 | gtt_size = 1024*1024; |
92b88aeb | 1238 | else |
e28f8711 | 1239 | gtt_size = 512*1024; |
92b88aeb | 1240 | |
e28f8711 CW |
1241 | while (gtt_size < size) |
1242 | gtt_size <<= 1; | |
92b88aeb | 1243 | |
e28f8711 | 1244 | return gtt_size; |
92b88aeb CW |
1245 | } |
1246 | ||
de151cf6 JB |
1247 | /** |
1248 | * i915_gem_get_gtt_alignment - return required GTT alignment for an object | |
1249 | * @obj: object to check | |
1250 | * | |
1251 | * Return the required GTT alignment for an object, taking into account | |
5e783301 | 1252 | * potential fence register mapping. |
de151cf6 JB |
1253 | */ |
1254 | static uint32_t | |
e28f8711 CW |
1255 | i915_gem_get_gtt_alignment(struct drm_device *dev, |
1256 | uint32_t size, | |
1257 | int tiling_mode) | |
de151cf6 | 1258 | { |
de151cf6 JB |
1259 | /* |
1260 | * Minimum alignment is 4k (GTT page size), but might be greater | |
1261 | * if a fence register is needed for the object. | |
1262 | */ | |
a00b10c3 | 1263 | if (INTEL_INFO(dev)->gen >= 4 || |
e28f8711 | 1264 | tiling_mode == I915_TILING_NONE) |
de151cf6 JB |
1265 | return 4096; |
1266 | ||
a00b10c3 CW |
1267 | /* |
1268 | * Previous chips need to be aligned to the size of the smallest | |
1269 | * fence register that can contain the object. | |
1270 | */ | |
e28f8711 | 1271 | return i915_gem_get_gtt_size(dev, size, tiling_mode); |
a00b10c3 CW |
1272 | } |
1273 | ||
5e783301 DV |
1274 | /** |
1275 | * i915_gem_get_unfenced_gtt_alignment - return required GTT alignment for an | |
1276 | * unfenced object | |
e28f8711 CW |
1277 | * @dev: the device |
1278 | * @size: size of the object | |
1279 | * @tiling_mode: tiling mode of the object | |
5e783301 DV |
1280 | * |
1281 | * Return the required GTT alignment for an object, only taking into account | |
1282 | * unfenced tiled surface requirements. | |
1283 | */ | |
467cffba | 1284 | uint32_t |
e28f8711 CW |
1285 | i915_gem_get_unfenced_gtt_alignment(struct drm_device *dev, |
1286 | uint32_t size, | |
1287 | int tiling_mode) | |
5e783301 | 1288 | { |
5e783301 DV |
1289 | /* |
1290 | * Minimum alignment is 4k (GTT page size) for sane hw. | |
1291 | */ | |
1292 | if (INTEL_INFO(dev)->gen >= 4 || IS_G33(dev) || | |
e28f8711 | 1293 | tiling_mode == I915_TILING_NONE) |
5e783301 DV |
1294 | return 4096; |
1295 | ||
e28f8711 CW |
1296 | /* Previous hardware however needs to be aligned to a power-of-two |
1297 | * tile height. The simplest method for determining this is to reuse | |
1298 | * the power-of-tile object size. | |
5e783301 | 1299 | */ |
e28f8711 | 1300 | return i915_gem_get_gtt_size(dev, size, tiling_mode); |
5e783301 DV |
1301 | } |
1302 | ||
de151cf6 | 1303 | int |
ff72145b DA |
1304 | i915_gem_mmap_gtt(struct drm_file *file, |
1305 | struct drm_device *dev, | |
1306 | uint32_t handle, | |
1307 | uint64_t *offset) | |
de151cf6 | 1308 | { |
da761a6e | 1309 | struct drm_i915_private *dev_priv = dev->dev_private; |
05394f39 | 1310 | struct drm_i915_gem_object *obj; |
de151cf6 JB |
1311 | int ret; |
1312 | ||
1313 | if (!(dev->driver->driver_features & DRIVER_GEM)) | |
1314 | return -ENODEV; | |
1315 | ||
76c1dec1 | 1316 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 1317 | if (ret) |
76c1dec1 | 1318 | return ret; |
de151cf6 | 1319 | |
ff72145b | 1320 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle)); |
c8725226 | 1321 | if (&obj->base == NULL) { |
1d7cfea1 CW |
1322 | ret = -ENOENT; |
1323 | goto unlock; | |
1324 | } | |
de151cf6 | 1325 | |
05394f39 | 1326 | if (obj->base.size > dev_priv->mm.gtt_mappable_end) { |
da761a6e | 1327 | ret = -E2BIG; |
ff56b0bc | 1328 | goto out; |
da761a6e CW |
1329 | } |
1330 | ||
05394f39 | 1331 | if (obj->madv != I915_MADV_WILLNEED) { |
ab18282d | 1332 | DRM_ERROR("Attempting to mmap a purgeable buffer\n"); |
1d7cfea1 CW |
1333 | ret = -EINVAL; |
1334 | goto out; | |
ab18282d CW |
1335 | } |
1336 | ||
05394f39 | 1337 | if (!obj->base.map_list.map) { |
b464e9a2 | 1338 | ret = drm_gem_create_mmap_offset(&obj->base); |
1d7cfea1 CW |
1339 | if (ret) |
1340 | goto out; | |
de151cf6 JB |
1341 | } |
1342 | ||
ff72145b | 1343 | *offset = (u64)obj->base.map_list.hash.key << PAGE_SHIFT; |
de151cf6 | 1344 | |
1d7cfea1 | 1345 | out: |
05394f39 | 1346 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 1347 | unlock: |
de151cf6 | 1348 | mutex_unlock(&dev->struct_mutex); |
1d7cfea1 | 1349 | return ret; |
de151cf6 JB |
1350 | } |
1351 | ||
ff72145b DA |
1352 | /** |
1353 | * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing | |
1354 | * @dev: DRM device | |
1355 | * @data: GTT mapping ioctl data | |
1356 | * @file: GEM object info | |
1357 | * | |
1358 | * Simply returns the fake offset to userspace so it can mmap it. | |
1359 | * The mmap call will end up in drm_gem_mmap(), which will set things | |
1360 | * up so we can get faults in the handler above. | |
1361 | * | |
1362 | * The fault handler will take care of binding the object into the GTT | |
1363 | * (since it may have been evicted to make room for something), allocating | |
1364 | * a fence register, and mapping the appropriate aperture address into | |
1365 | * userspace. | |
1366 | */ | |
1367 | int | |
1368 | i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data, | |
1369 | struct drm_file *file) | |
1370 | { | |
1371 | struct drm_i915_gem_mmap_gtt *args = data; | |
1372 | ||
1373 | if (!(dev->driver->driver_features & DRIVER_GEM)) | |
1374 | return -ENODEV; | |
1375 | ||
1376 | return i915_gem_mmap_gtt(file, dev, args->handle, &args->offset); | |
1377 | } | |
1378 | ||
1379 | ||
e5281ccd | 1380 | static int |
05394f39 | 1381 | i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj, |
e5281ccd CW |
1382 | gfp_t gfpmask) |
1383 | { | |
e5281ccd CW |
1384 | int page_count, i; |
1385 | struct address_space *mapping; | |
1386 | struct inode *inode; | |
1387 | struct page *page; | |
1388 | ||
1389 | /* Get the list of pages out of our struct file. They'll be pinned | |
1390 | * at this point until we release them. | |
1391 | */ | |
05394f39 CW |
1392 | page_count = obj->base.size / PAGE_SIZE; |
1393 | BUG_ON(obj->pages != NULL); | |
1394 | obj->pages = drm_malloc_ab(page_count, sizeof(struct page *)); | |
1395 | if (obj->pages == NULL) | |
e5281ccd CW |
1396 | return -ENOMEM; |
1397 | ||
05394f39 | 1398 | inode = obj->base.filp->f_path.dentry->d_inode; |
e5281ccd | 1399 | mapping = inode->i_mapping; |
5949eac4 HD |
1400 | gfpmask |= mapping_gfp_mask(mapping); |
1401 | ||
e5281ccd | 1402 | for (i = 0; i < page_count; i++) { |
5949eac4 | 1403 | page = shmem_read_mapping_page_gfp(mapping, i, gfpmask); |
e5281ccd CW |
1404 | if (IS_ERR(page)) |
1405 | goto err_pages; | |
1406 | ||
05394f39 | 1407 | obj->pages[i] = page; |
e5281ccd CW |
1408 | } |
1409 | ||
6dacfd2f | 1410 | if (i915_gem_object_needs_bit17_swizzle(obj)) |
e5281ccd CW |
1411 | i915_gem_object_do_bit_17_swizzle(obj); |
1412 | ||
1413 | return 0; | |
1414 | ||
1415 | err_pages: | |
1416 | while (i--) | |
05394f39 | 1417 | page_cache_release(obj->pages[i]); |
e5281ccd | 1418 | |
05394f39 CW |
1419 | drm_free_large(obj->pages); |
1420 | obj->pages = NULL; | |
e5281ccd CW |
1421 | return PTR_ERR(page); |
1422 | } | |
1423 | ||
5cdf5881 | 1424 | static void |
05394f39 | 1425 | i915_gem_object_put_pages_gtt(struct drm_i915_gem_object *obj) |
673a394b | 1426 | { |
05394f39 | 1427 | int page_count = obj->base.size / PAGE_SIZE; |
673a394b EA |
1428 | int i; |
1429 | ||
05394f39 | 1430 | BUG_ON(obj->madv == __I915_MADV_PURGED); |
673a394b | 1431 | |
6dacfd2f | 1432 | if (i915_gem_object_needs_bit17_swizzle(obj)) |
280b713b EA |
1433 | i915_gem_object_save_bit_17_swizzle(obj); |
1434 | ||
05394f39 CW |
1435 | if (obj->madv == I915_MADV_DONTNEED) |
1436 | obj->dirty = 0; | |
3ef94daa CW |
1437 | |
1438 | for (i = 0; i < page_count; i++) { | |
05394f39 CW |
1439 | if (obj->dirty) |
1440 | set_page_dirty(obj->pages[i]); | |
3ef94daa | 1441 | |
05394f39 CW |
1442 | if (obj->madv == I915_MADV_WILLNEED) |
1443 | mark_page_accessed(obj->pages[i]); | |
3ef94daa | 1444 | |
05394f39 | 1445 | page_cache_release(obj->pages[i]); |
3ef94daa | 1446 | } |
05394f39 | 1447 | obj->dirty = 0; |
673a394b | 1448 | |
05394f39 CW |
1449 | drm_free_large(obj->pages); |
1450 | obj->pages = NULL; | |
673a394b EA |
1451 | } |
1452 | ||
54cf91dc | 1453 | void |
05394f39 | 1454 | i915_gem_object_move_to_active(struct drm_i915_gem_object *obj, |
1ec14ad3 CW |
1455 | struct intel_ring_buffer *ring, |
1456 | u32 seqno) | |
673a394b | 1457 | { |
05394f39 | 1458 | struct drm_device *dev = obj->base.dev; |
69dc4987 | 1459 | struct drm_i915_private *dev_priv = dev->dev_private; |
617dbe27 | 1460 | |
852835f3 | 1461 | BUG_ON(ring == NULL); |
05394f39 | 1462 | obj->ring = ring; |
673a394b EA |
1463 | |
1464 | /* Add a reference if we're newly entering the active list. */ | |
05394f39 CW |
1465 | if (!obj->active) { |
1466 | drm_gem_object_reference(&obj->base); | |
1467 | obj->active = 1; | |
673a394b | 1468 | } |
e35a41de | 1469 | |
673a394b | 1470 | /* Move from whatever list we were on to the tail of execution. */ |
05394f39 CW |
1471 | list_move_tail(&obj->mm_list, &dev_priv->mm.active_list); |
1472 | list_move_tail(&obj->ring_list, &ring->active_list); | |
caea7476 | 1473 | |
05394f39 | 1474 | obj->last_rendering_seqno = seqno; |
caea7476 | 1475 | |
7dd49065 | 1476 | if (obj->fenced_gpu_access) { |
caea7476 CW |
1477 | obj->last_fenced_seqno = seqno; |
1478 | obj->last_fenced_ring = ring; | |
1479 | ||
7dd49065 CW |
1480 | /* Bump MRU to take account of the delayed flush */ |
1481 | if (obj->fence_reg != I915_FENCE_REG_NONE) { | |
1482 | struct drm_i915_fence_reg *reg; | |
1483 | ||
1484 | reg = &dev_priv->fence_regs[obj->fence_reg]; | |
1485 | list_move_tail(®->lru_list, | |
1486 | &dev_priv->mm.fence_list); | |
1487 | } | |
caea7476 CW |
1488 | } |
1489 | } | |
1490 | ||
1491 | static void | |
1492 | i915_gem_object_move_off_active(struct drm_i915_gem_object *obj) | |
1493 | { | |
1494 | list_del_init(&obj->ring_list); | |
1495 | obj->last_rendering_seqno = 0; | |
673a394b EA |
1496 | } |
1497 | ||
ce44b0ea | 1498 | static void |
05394f39 | 1499 | i915_gem_object_move_to_flushing(struct drm_i915_gem_object *obj) |
ce44b0ea | 1500 | { |
05394f39 | 1501 | struct drm_device *dev = obj->base.dev; |
ce44b0ea | 1502 | drm_i915_private_t *dev_priv = dev->dev_private; |
ce44b0ea | 1503 | |
05394f39 CW |
1504 | BUG_ON(!obj->active); |
1505 | list_move_tail(&obj->mm_list, &dev_priv->mm.flushing_list); | |
caea7476 CW |
1506 | |
1507 | i915_gem_object_move_off_active(obj); | |
1508 | } | |
1509 | ||
1510 | static void | |
1511 | i915_gem_object_move_to_inactive(struct drm_i915_gem_object *obj) | |
1512 | { | |
1513 | struct drm_device *dev = obj->base.dev; | |
1514 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1515 | ||
1516 | if (obj->pin_count != 0) | |
1517 | list_move_tail(&obj->mm_list, &dev_priv->mm.pinned_list); | |
1518 | else | |
1519 | list_move_tail(&obj->mm_list, &dev_priv->mm.inactive_list); | |
1520 | ||
1521 | BUG_ON(!list_empty(&obj->gpu_write_list)); | |
1522 | BUG_ON(!obj->active); | |
1523 | obj->ring = NULL; | |
1524 | ||
1525 | i915_gem_object_move_off_active(obj); | |
1526 | obj->fenced_gpu_access = false; | |
caea7476 CW |
1527 | |
1528 | obj->active = 0; | |
87ca9c8a | 1529 | obj->pending_gpu_write = false; |
caea7476 CW |
1530 | drm_gem_object_unreference(&obj->base); |
1531 | ||
1532 | WARN_ON(i915_verify_lists(dev)); | |
ce44b0ea | 1533 | } |
673a394b | 1534 | |
963b4836 CW |
1535 | /* Immediately discard the backing storage */ |
1536 | static void | |
05394f39 | 1537 | i915_gem_object_truncate(struct drm_i915_gem_object *obj) |
963b4836 | 1538 | { |
bb6baf76 | 1539 | struct inode *inode; |
963b4836 | 1540 | |
ae9fed6b CW |
1541 | /* Our goal here is to return as much of the memory as |
1542 | * is possible back to the system as we are called from OOM. | |
1543 | * To do this we must instruct the shmfs to drop all of its | |
e2377fe0 | 1544 | * backing pages, *now*. |
ae9fed6b | 1545 | */ |
05394f39 | 1546 | inode = obj->base.filp->f_path.dentry->d_inode; |
e2377fe0 | 1547 | shmem_truncate_range(inode, 0, (loff_t)-1); |
bb6baf76 | 1548 | |
05394f39 | 1549 | obj->madv = __I915_MADV_PURGED; |
963b4836 CW |
1550 | } |
1551 | ||
1552 | static inline int | |
05394f39 | 1553 | i915_gem_object_is_purgeable(struct drm_i915_gem_object *obj) |
963b4836 | 1554 | { |
05394f39 | 1555 | return obj->madv == I915_MADV_DONTNEED; |
963b4836 CW |
1556 | } |
1557 | ||
63560396 | 1558 | static void |
db53a302 CW |
1559 | i915_gem_process_flushing_list(struct intel_ring_buffer *ring, |
1560 | uint32_t flush_domains) | |
63560396 | 1561 | { |
05394f39 | 1562 | struct drm_i915_gem_object *obj, *next; |
63560396 | 1563 | |
05394f39 | 1564 | list_for_each_entry_safe(obj, next, |
64193406 | 1565 | &ring->gpu_write_list, |
63560396 | 1566 | gpu_write_list) { |
05394f39 CW |
1567 | if (obj->base.write_domain & flush_domains) { |
1568 | uint32_t old_write_domain = obj->base.write_domain; | |
63560396 | 1569 | |
05394f39 CW |
1570 | obj->base.write_domain = 0; |
1571 | list_del_init(&obj->gpu_write_list); | |
1ec14ad3 | 1572 | i915_gem_object_move_to_active(obj, ring, |
db53a302 | 1573 | i915_gem_next_request_seqno(ring)); |
63560396 | 1574 | |
63560396 | 1575 | trace_i915_gem_object_change_domain(obj, |
05394f39 | 1576 | obj->base.read_domains, |
63560396 DV |
1577 | old_write_domain); |
1578 | } | |
1579 | } | |
1580 | } | |
8187a2b7 | 1581 | |
53d227f2 DV |
1582 | static u32 |
1583 | i915_gem_get_seqno(struct drm_device *dev) | |
1584 | { | |
1585 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1586 | u32 seqno = dev_priv->next_seqno; | |
1587 | ||
1588 | /* reserve 0 for non-seqno */ | |
1589 | if (++dev_priv->next_seqno == 0) | |
1590 | dev_priv->next_seqno = 1; | |
1591 | ||
1592 | return seqno; | |
1593 | } | |
1594 | ||
1595 | u32 | |
1596 | i915_gem_next_request_seqno(struct intel_ring_buffer *ring) | |
1597 | { | |
1598 | if (ring->outstanding_lazy_request == 0) | |
1599 | ring->outstanding_lazy_request = i915_gem_get_seqno(ring->dev); | |
1600 | ||
1601 | return ring->outstanding_lazy_request; | |
1602 | } | |
1603 | ||
3cce469c | 1604 | int |
db53a302 | 1605 | i915_add_request(struct intel_ring_buffer *ring, |
f787a5f5 | 1606 | struct drm_file *file, |
db53a302 | 1607 | struct drm_i915_gem_request *request) |
673a394b | 1608 | { |
db53a302 | 1609 | drm_i915_private_t *dev_priv = ring->dev->dev_private; |
673a394b | 1610 | uint32_t seqno; |
a71d8d94 | 1611 | u32 request_ring_position; |
673a394b | 1612 | int was_empty; |
3cce469c CW |
1613 | int ret; |
1614 | ||
1615 | BUG_ON(request == NULL); | |
53d227f2 | 1616 | seqno = i915_gem_next_request_seqno(ring); |
673a394b | 1617 | |
a71d8d94 CW |
1618 | /* Record the position of the start of the request so that |
1619 | * should we detect the updated seqno part-way through the | |
1620 | * GPU processing the request, we never over-estimate the | |
1621 | * position of the head. | |
1622 | */ | |
1623 | request_ring_position = intel_ring_get_tail(ring); | |
1624 | ||
3cce469c CW |
1625 | ret = ring->add_request(ring, &seqno); |
1626 | if (ret) | |
1627 | return ret; | |
673a394b | 1628 | |
db53a302 | 1629 | trace_i915_gem_request_add(ring, seqno); |
673a394b EA |
1630 | |
1631 | request->seqno = seqno; | |
852835f3 | 1632 | request->ring = ring; |
a71d8d94 | 1633 | request->tail = request_ring_position; |
673a394b | 1634 | request->emitted_jiffies = jiffies; |
852835f3 ZN |
1635 | was_empty = list_empty(&ring->request_list); |
1636 | list_add_tail(&request->list, &ring->request_list); | |
1637 | ||
db53a302 CW |
1638 | if (file) { |
1639 | struct drm_i915_file_private *file_priv = file->driver_priv; | |
1640 | ||
1c25595f | 1641 | spin_lock(&file_priv->mm.lock); |
f787a5f5 | 1642 | request->file_priv = file_priv; |
b962442e | 1643 | list_add_tail(&request->client_list, |
f787a5f5 | 1644 | &file_priv->mm.request_list); |
1c25595f | 1645 | spin_unlock(&file_priv->mm.lock); |
b962442e | 1646 | } |
673a394b | 1647 | |
5391d0cf | 1648 | ring->outstanding_lazy_request = 0; |
db53a302 | 1649 | |
f65d9421 | 1650 | if (!dev_priv->mm.suspended) { |
3e0dc6b0 BW |
1651 | if (i915_enable_hangcheck) { |
1652 | mod_timer(&dev_priv->hangcheck_timer, | |
1653 | jiffies + | |
1654 | msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD)); | |
1655 | } | |
f65d9421 | 1656 | if (was_empty) |
b3b079db CW |
1657 | queue_delayed_work(dev_priv->wq, |
1658 | &dev_priv->mm.retire_work, HZ); | |
f65d9421 | 1659 | } |
3cce469c | 1660 | return 0; |
673a394b EA |
1661 | } |
1662 | ||
f787a5f5 CW |
1663 | static inline void |
1664 | i915_gem_request_remove_from_client(struct drm_i915_gem_request *request) | |
673a394b | 1665 | { |
1c25595f | 1666 | struct drm_i915_file_private *file_priv = request->file_priv; |
673a394b | 1667 | |
1c25595f CW |
1668 | if (!file_priv) |
1669 | return; | |
1c5d22f7 | 1670 | |
1c25595f | 1671 | spin_lock(&file_priv->mm.lock); |
09bfa517 HRK |
1672 | if (request->file_priv) { |
1673 | list_del(&request->client_list); | |
1674 | request->file_priv = NULL; | |
1675 | } | |
1c25595f | 1676 | spin_unlock(&file_priv->mm.lock); |
673a394b | 1677 | } |
673a394b | 1678 | |
dfaae392 CW |
1679 | static void i915_gem_reset_ring_lists(struct drm_i915_private *dev_priv, |
1680 | struct intel_ring_buffer *ring) | |
9375e446 | 1681 | { |
dfaae392 CW |
1682 | while (!list_empty(&ring->request_list)) { |
1683 | struct drm_i915_gem_request *request; | |
673a394b | 1684 | |
dfaae392 CW |
1685 | request = list_first_entry(&ring->request_list, |
1686 | struct drm_i915_gem_request, | |
1687 | list); | |
de151cf6 | 1688 | |
dfaae392 | 1689 | list_del(&request->list); |
f787a5f5 | 1690 | i915_gem_request_remove_from_client(request); |
dfaae392 CW |
1691 | kfree(request); |
1692 | } | |
673a394b | 1693 | |
dfaae392 | 1694 | while (!list_empty(&ring->active_list)) { |
05394f39 | 1695 | struct drm_i915_gem_object *obj; |
9375e446 | 1696 | |
05394f39 CW |
1697 | obj = list_first_entry(&ring->active_list, |
1698 | struct drm_i915_gem_object, | |
1699 | ring_list); | |
9375e446 | 1700 | |
05394f39 CW |
1701 | obj->base.write_domain = 0; |
1702 | list_del_init(&obj->gpu_write_list); | |
1703 | i915_gem_object_move_to_inactive(obj); | |
673a394b EA |
1704 | } |
1705 | } | |
1706 | ||
312817a3 CW |
1707 | static void i915_gem_reset_fences(struct drm_device *dev) |
1708 | { | |
1709 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1710 | int i; | |
1711 | ||
4b9de737 | 1712 | for (i = 0; i < dev_priv->num_fence_regs; i++) { |
312817a3 | 1713 | struct drm_i915_fence_reg *reg = &dev_priv->fence_regs[i]; |
7d2cb39c CW |
1714 | struct drm_i915_gem_object *obj = reg->obj; |
1715 | ||
1716 | if (!obj) | |
1717 | continue; | |
1718 | ||
1719 | if (obj->tiling_mode) | |
1720 | i915_gem_release_mmap(obj); | |
1721 | ||
d9e86c0e CW |
1722 | reg->obj->fence_reg = I915_FENCE_REG_NONE; |
1723 | reg->obj->fenced_gpu_access = false; | |
1724 | reg->obj->last_fenced_seqno = 0; | |
1725 | reg->obj->last_fenced_ring = NULL; | |
1726 | i915_gem_clear_fence_reg(dev, reg); | |
312817a3 CW |
1727 | } |
1728 | } | |
1729 | ||
069efc1d | 1730 | void i915_gem_reset(struct drm_device *dev) |
673a394b | 1731 | { |
77f01230 | 1732 | struct drm_i915_private *dev_priv = dev->dev_private; |
05394f39 | 1733 | struct drm_i915_gem_object *obj; |
1ec14ad3 | 1734 | int i; |
673a394b | 1735 | |
1ec14ad3 CW |
1736 | for (i = 0; i < I915_NUM_RINGS; i++) |
1737 | i915_gem_reset_ring_lists(dev_priv, &dev_priv->ring[i]); | |
dfaae392 CW |
1738 | |
1739 | /* Remove anything from the flushing lists. The GPU cache is likely | |
1740 | * to be lost on reset along with the data, so simply move the | |
1741 | * lost bo to the inactive list. | |
1742 | */ | |
1743 | while (!list_empty(&dev_priv->mm.flushing_list)) { | |
0206e353 | 1744 | obj = list_first_entry(&dev_priv->mm.flushing_list, |
05394f39 CW |
1745 | struct drm_i915_gem_object, |
1746 | mm_list); | |
dfaae392 | 1747 | |
05394f39 CW |
1748 | obj->base.write_domain = 0; |
1749 | list_del_init(&obj->gpu_write_list); | |
1750 | i915_gem_object_move_to_inactive(obj); | |
dfaae392 CW |
1751 | } |
1752 | ||
1753 | /* Move everything out of the GPU domains to ensure we do any | |
1754 | * necessary invalidation upon reuse. | |
1755 | */ | |
05394f39 | 1756 | list_for_each_entry(obj, |
77f01230 | 1757 | &dev_priv->mm.inactive_list, |
69dc4987 | 1758 | mm_list) |
77f01230 | 1759 | { |
05394f39 | 1760 | obj->base.read_domains &= ~I915_GEM_GPU_DOMAINS; |
77f01230 | 1761 | } |
069efc1d CW |
1762 | |
1763 | /* The fence registers are invalidated so clear them out */ | |
312817a3 | 1764 | i915_gem_reset_fences(dev); |
673a394b EA |
1765 | } |
1766 | ||
1767 | /** | |
1768 | * This function clears the request list as sequence numbers are passed. | |
1769 | */ | |
a71d8d94 | 1770 | void |
db53a302 | 1771 | i915_gem_retire_requests_ring(struct intel_ring_buffer *ring) |
673a394b | 1772 | { |
673a394b | 1773 | uint32_t seqno; |
1ec14ad3 | 1774 | int i; |
673a394b | 1775 | |
db53a302 | 1776 | if (list_empty(&ring->request_list)) |
6c0594a3 KW |
1777 | return; |
1778 | ||
db53a302 | 1779 | WARN_ON(i915_verify_lists(ring->dev)); |
673a394b | 1780 | |
78501eac | 1781 | seqno = ring->get_seqno(ring); |
1ec14ad3 | 1782 | |
076e2c0e | 1783 | for (i = 0; i < ARRAY_SIZE(ring->sync_seqno); i++) |
1ec14ad3 CW |
1784 | if (seqno >= ring->sync_seqno[i]) |
1785 | ring->sync_seqno[i] = 0; | |
1786 | ||
852835f3 | 1787 | while (!list_empty(&ring->request_list)) { |
673a394b | 1788 | struct drm_i915_gem_request *request; |
673a394b | 1789 | |
852835f3 | 1790 | request = list_first_entry(&ring->request_list, |
673a394b EA |
1791 | struct drm_i915_gem_request, |
1792 | list); | |
673a394b | 1793 | |
dfaae392 | 1794 | if (!i915_seqno_passed(seqno, request->seqno)) |
b84d5f0c CW |
1795 | break; |
1796 | ||
db53a302 | 1797 | trace_i915_gem_request_retire(ring, request->seqno); |
a71d8d94 CW |
1798 | /* We know the GPU must have read the request to have |
1799 | * sent us the seqno + interrupt, so use the position | |
1800 | * of tail of the request to update the last known position | |
1801 | * of the GPU head. | |
1802 | */ | |
1803 | ring->last_retired_head = request->tail; | |
b84d5f0c CW |
1804 | |
1805 | list_del(&request->list); | |
f787a5f5 | 1806 | i915_gem_request_remove_from_client(request); |
b84d5f0c CW |
1807 | kfree(request); |
1808 | } | |
673a394b | 1809 | |
b84d5f0c CW |
1810 | /* Move any buffers on the active list that are no longer referenced |
1811 | * by the ringbuffer to the flushing/inactive lists as appropriate. | |
1812 | */ | |
1813 | while (!list_empty(&ring->active_list)) { | |
05394f39 | 1814 | struct drm_i915_gem_object *obj; |
b84d5f0c | 1815 | |
0206e353 | 1816 | obj = list_first_entry(&ring->active_list, |
05394f39 CW |
1817 | struct drm_i915_gem_object, |
1818 | ring_list); | |
673a394b | 1819 | |
05394f39 | 1820 | if (!i915_seqno_passed(seqno, obj->last_rendering_seqno)) |
673a394b | 1821 | break; |
b84d5f0c | 1822 | |
05394f39 | 1823 | if (obj->base.write_domain != 0) |
b84d5f0c CW |
1824 | i915_gem_object_move_to_flushing(obj); |
1825 | else | |
1826 | i915_gem_object_move_to_inactive(obj); | |
673a394b | 1827 | } |
9d34e5db | 1828 | |
db53a302 CW |
1829 | if (unlikely(ring->trace_irq_seqno && |
1830 | i915_seqno_passed(seqno, ring->trace_irq_seqno))) { | |
1ec14ad3 | 1831 | ring->irq_put(ring); |
db53a302 | 1832 | ring->trace_irq_seqno = 0; |
9d34e5db | 1833 | } |
23bc5982 | 1834 | |
db53a302 | 1835 | WARN_ON(i915_verify_lists(ring->dev)); |
673a394b EA |
1836 | } |
1837 | ||
b09a1fec CW |
1838 | void |
1839 | i915_gem_retire_requests(struct drm_device *dev) | |
1840 | { | |
1841 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1ec14ad3 | 1842 | int i; |
b09a1fec | 1843 | |
be72615b | 1844 | if (!list_empty(&dev_priv->mm.deferred_free_list)) { |
05394f39 | 1845 | struct drm_i915_gem_object *obj, *next; |
be72615b CW |
1846 | |
1847 | /* We must be careful that during unbind() we do not | |
1848 | * accidentally infinitely recurse into retire requests. | |
1849 | * Currently: | |
1850 | * retire -> free -> unbind -> wait -> retire_ring | |
1851 | */ | |
05394f39 | 1852 | list_for_each_entry_safe(obj, next, |
be72615b | 1853 | &dev_priv->mm.deferred_free_list, |
69dc4987 | 1854 | mm_list) |
05394f39 | 1855 | i915_gem_free_object_tail(obj); |
be72615b CW |
1856 | } |
1857 | ||
1ec14ad3 | 1858 | for (i = 0; i < I915_NUM_RINGS; i++) |
db53a302 | 1859 | i915_gem_retire_requests_ring(&dev_priv->ring[i]); |
b09a1fec CW |
1860 | } |
1861 | ||
75ef9da2 | 1862 | static void |
673a394b EA |
1863 | i915_gem_retire_work_handler(struct work_struct *work) |
1864 | { | |
1865 | drm_i915_private_t *dev_priv; | |
1866 | struct drm_device *dev; | |
0a58705b CW |
1867 | bool idle; |
1868 | int i; | |
673a394b EA |
1869 | |
1870 | dev_priv = container_of(work, drm_i915_private_t, | |
1871 | mm.retire_work.work); | |
1872 | dev = dev_priv->dev; | |
1873 | ||
891b48cf CW |
1874 | /* Come back later if the device is busy... */ |
1875 | if (!mutex_trylock(&dev->struct_mutex)) { | |
1876 | queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, HZ); | |
1877 | return; | |
1878 | } | |
1879 | ||
b09a1fec | 1880 | i915_gem_retire_requests(dev); |
d1b851fc | 1881 | |
0a58705b CW |
1882 | /* Send a periodic flush down the ring so we don't hold onto GEM |
1883 | * objects indefinitely. | |
1884 | */ | |
1885 | idle = true; | |
1886 | for (i = 0; i < I915_NUM_RINGS; i++) { | |
1887 | struct intel_ring_buffer *ring = &dev_priv->ring[i]; | |
1888 | ||
1889 | if (!list_empty(&ring->gpu_write_list)) { | |
1890 | struct drm_i915_gem_request *request; | |
1891 | int ret; | |
1892 | ||
db53a302 CW |
1893 | ret = i915_gem_flush_ring(ring, |
1894 | 0, I915_GEM_GPU_DOMAINS); | |
0a58705b CW |
1895 | request = kzalloc(sizeof(*request), GFP_KERNEL); |
1896 | if (ret || request == NULL || | |
db53a302 | 1897 | i915_add_request(ring, NULL, request)) |
0a58705b CW |
1898 | kfree(request); |
1899 | } | |
1900 | ||
1901 | idle &= list_empty(&ring->request_list); | |
1902 | } | |
1903 | ||
1904 | if (!dev_priv->mm.suspended && !idle) | |
9c9fe1f8 | 1905 | queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, HZ); |
0a58705b | 1906 | |
673a394b EA |
1907 | mutex_unlock(&dev->struct_mutex); |
1908 | } | |
1909 | ||
db53a302 CW |
1910 | /** |
1911 | * Waits for a sequence number to be signaled, and cleans up the | |
1912 | * request and object lists appropriately for that event. | |
1913 | */ | |
5a5a0c64 | 1914 | int |
db53a302 | 1915 | i915_wait_request(struct intel_ring_buffer *ring, |
b93f9cf1 BW |
1916 | uint32_t seqno, |
1917 | bool do_retire) | |
673a394b | 1918 | { |
db53a302 | 1919 | drm_i915_private_t *dev_priv = ring->dev->dev_private; |
802c7eb6 | 1920 | u32 ier; |
673a394b EA |
1921 | int ret = 0; |
1922 | ||
1923 | BUG_ON(seqno == 0); | |
1924 | ||
d9bc7e9f CW |
1925 | if (atomic_read(&dev_priv->mm.wedged)) { |
1926 | struct completion *x = &dev_priv->error_completion; | |
1927 | bool recovery_complete; | |
1928 | unsigned long flags; | |
1929 | ||
1930 | /* Give the error handler a chance to run. */ | |
1931 | spin_lock_irqsave(&x->wait.lock, flags); | |
1932 | recovery_complete = x->done > 0; | |
1933 | spin_unlock_irqrestore(&x->wait.lock, flags); | |
1934 | ||
1935 | return recovery_complete ? -EIO : -EAGAIN; | |
1936 | } | |
30dbf0c0 | 1937 | |
5d97eb69 | 1938 | if (seqno == ring->outstanding_lazy_request) { |
3cce469c CW |
1939 | struct drm_i915_gem_request *request; |
1940 | ||
1941 | request = kzalloc(sizeof(*request), GFP_KERNEL); | |
1942 | if (request == NULL) | |
e35a41de | 1943 | return -ENOMEM; |
3cce469c | 1944 | |
db53a302 | 1945 | ret = i915_add_request(ring, NULL, request); |
3cce469c CW |
1946 | if (ret) { |
1947 | kfree(request); | |
1948 | return ret; | |
1949 | } | |
1950 | ||
1951 | seqno = request->seqno; | |
e35a41de | 1952 | } |
ffed1d09 | 1953 | |
78501eac | 1954 | if (!i915_seqno_passed(ring->get_seqno(ring), seqno)) { |
db53a302 | 1955 | if (HAS_PCH_SPLIT(ring->dev)) |
036a4a7d ZW |
1956 | ier = I915_READ(DEIER) | I915_READ(GTIER); |
1957 | else | |
1958 | ier = I915_READ(IER); | |
802c7eb6 JB |
1959 | if (!ier) { |
1960 | DRM_ERROR("something (likely vbetool) disabled " | |
1961 | "interrupts, re-enabling\n"); | |
f01c22fd CW |
1962 | ring->dev->driver->irq_preinstall(ring->dev); |
1963 | ring->dev->driver->irq_postinstall(ring->dev); | |
802c7eb6 JB |
1964 | } |
1965 | ||
db53a302 | 1966 | trace_i915_gem_request_wait_begin(ring, seqno); |
1c5d22f7 | 1967 | |
b2223497 | 1968 | ring->waiting_seqno = seqno; |
b13c2b96 | 1969 | if (ring->irq_get(ring)) { |
ce453d81 | 1970 | if (dev_priv->mm.interruptible) |
b13c2b96 CW |
1971 | ret = wait_event_interruptible(ring->irq_queue, |
1972 | i915_seqno_passed(ring->get_seqno(ring), seqno) | |
1973 | || atomic_read(&dev_priv->mm.wedged)); | |
1974 | else | |
1975 | wait_event(ring->irq_queue, | |
1976 | i915_seqno_passed(ring->get_seqno(ring), seqno) | |
1977 | || atomic_read(&dev_priv->mm.wedged)); | |
1978 | ||
1979 | ring->irq_put(ring); | |
e959b5db EA |
1980 | } else if (wait_for_atomic(i915_seqno_passed(ring->get_seqno(ring), |
1981 | seqno) || | |
1982 | atomic_read(&dev_priv->mm.wedged), 3000)) | |
b5ba177d | 1983 | ret = -EBUSY; |
b2223497 | 1984 | ring->waiting_seqno = 0; |
1c5d22f7 | 1985 | |
db53a302 | 1986 | trace_i915_gem_request_wait_end(ring, seqno); |
673a394b | 1987 | } |
ba1234d1 | 1988 | if (atomic_read(&dev_priv->mm.wedged)) |
30dbf0c0 | 1989 | ret = -EAGAIN; |
673a394b | 1990 | |
673a394b EA |
1991 | /* Directly dispatch request retiring. While we have the work queue |
1992 | * to handle this, the waiter on a request often wants an associated | |
1993 | * buffer to have made it to the inactive list, and we would need | |
1994 | * a separate wait queue to handle that. | |
1995 | */ | |
b93f9cf1 | 1996 | if (ret == 0 && do_retire) |
db53a302 | 1997 | i915_gem_retire_requests_ring(ring); |
673a394b EA |
1998 | |
1999 | return ret; | |
2000 | } | |
2001 | ||
673a394b EA |
2002 | /** |
2003 | * Ensures that all rendering to the object has completed and the object is | |
2004 | * safe to unbind from the GTT or access from the CPU. | |
2005 | */ | |
54cf91dc | 2006 | int |
ce453d81 | 2007 | i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj) |
673a394b | 2008 | { |
673a394b EA |
2009 | int ret; |
2010 | ||
e47c68e9 EA |
2011 | /* This function only exists to support waiting for existing rendering, |
2012 | * not for emitting required flushes. | |
673a394b | 2013 | */ |
05394f39 | 2014 | BUG_ON((obj->base.write_domain & I915_GEM_GPU_DOMAINS) != 0); |
673a394b EA |
2015 | |
2016 | /* If there is rendering queued on the buffer being evicted, wait for | |
2017 | * it. | |
2018 | */ | |
05394f39 | 2019 | if (obj->active) { |
b93f9cf1 BW |
2020 | ret = i915_wait_request(obj->ring, obj->last_rendering_seqno, |
2021 | true); | |
2cf34d7b | 2022 | if (ret) |
673a394b EA |
2023 | return ret; |
2024 | } | |
2025 | ||
2026 | return 0; | |
2027 | } | |
2028 | ||
b5ffc9bc CW |
2029 | static void i915_gem_object_finish_gtt(struct drm_i915_gem_object *obj) |
2030 | { | |
2031 | u32 old_write_domain, old_read_domains; | |
2032 | ||
b5ffc9bc CW |
2033 | /* Act a barrier for all accesses through the GTT */ |
2034 | mb(); | |
2035 | ||
2036 | /* Force a pagefault for domain tracking on next user access */ | |
2037 | i915_gem_release_mmap(obj); | |
2038 | ||
b97c3d9c KP |
2039 | if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0) |
2040 | return; | |
2041 | ||
b5ffc9bc CW |
2042 | old_read_domains = obj->base.read_domains; |
2043 | old_write_domain = obj->base.write_domain; | |
2044 | ||
2045 | obj->base.read_domains &= ~I915_GEM_DOMAIN_GTT; | |
2046 | obj->base.write_domain &= ~I915_GEM_DOMAIN_GTT; | |
2047 | ||
2048 | trace_i915_gem_object_change_domain(obj, | |
2049 | old_read_domains, | |
2050 | old_write_domain); | |
2051 | } | |
2052 | ||
673a394b EA |
2053 | /** |
2054 | * Unbinds an object from the GTT aperture. | |
2055 | */ | |
0f973f27 | 2056 | int |
05394f39 | 2057 | i915_gem_object_unbind(struct drm_i915_gem_object *obj) |
673a394b | 2058 | { |
7bddb01f | 2059 | drm_i915_private_t *dev_priv = obj->base.dev->dev_private; |
673a394b EA |
2060 | int ret = 0; |
2061 | ||
05394f39 | 2062 | if (obj->gtt_space == NULL) |
673a394b EA |
2063 | return 0; |
2064 | ||
05394f39 | 2065 | if (obj->pin_count != 0) { |
673a394b EA |
2066 | DRM_ERROR("Attempting to unbind pinned buffer\n"); |
2067 | return -EINVAL; | |
2068 | } | |
2069 | ||
a8198eea CW |
2070 | ret = i915_gem_object_finish_gpu(obj); |
2071 | if (ret == -ERESTARTSYS) | |
2072 | return ret; | |
2073 | /* Continue on if we fail due to EIO, the GPU is hung so we | |
2074 | * should be safe and we need to cleanup or else we might | |
2075 | * cause memory corruption through use-after-free. | |
2076 | */ | |
2077 | ||
b5ffc9bc | 2078 | i915_gem_object_finish_gtt(obj); |
5323fd04 | 2079 | |
673a394b EA |
2080 | /* Move the object to the CPU domain to ensure that |
2081 | * any possible CPU writes while it's not in the GTT | |
a8198eea | 2082 | * are flushed when we go to remap it. |
673a394b | 2083 | */ |
a8198eea CW |
2084 | if (ret == 0) |
2085 | ret = i915_gem_object_set_to_cpu_domain(obj, 1); | |
8dc1775d | 2086 | if (ret == -ERESTARTSYS) |
673a394b | 2087 | return ret; |
812ed492 | 2088 | if (ret) { |
a8198eea CW |
2089 | /* In the event of a disaster, abandon all caches and |
2090 | * hope for the best. | |
2091 | */ | |
812ed492 | 2092 | i915_gem_clflush_object(obj); |
05394f39 | 2093 | obj->base.read_domains = obj->base.write_domain = I915_GEM_DOMAIN_CPU; |
812ed492 | 2094 | } |
673a394b | 2095 | |
96b47b65 | 2096 | /* release the fence reg _after_ flushing */ |
d9e86c0e CW |
2097 | ret = i915_gem_object_put_fence(obj); |
2098 | if (ret == -ERESTARTSYS) | |
2099 | return ret; | |
96b47b65 | 2100 | |
db53a302 CW |
2101 | trace_i915_gem_object_unbind(obj); |
2102 | ||
7c2e6fdf | 2103 | i915_gem_gtt_unbind_object(obj); |
7bddb01f DV |
2104 | if (obj->has_aliasing_ppgtt_mapping) { |
2105 | i915_ppgtt_unbind_object(dev_priv->mm.aliasing_ppgtt, obj); | |
2106 | obj->has_aliasing_ppgtt_mapping = 0; | |
2107 | } | |
2108 | ||
e5281ccd | 2109 | i915_gem_object_put_pages_gtt(obj); |
673a394b | 2110 | |
6299f992 | 2111 | list_del_init(&obj->gtt_list); |
05394f39 | 2112 | list_del_init(&obj->mm_list); |
75e9e915 | 2113 | /* Avoid an unnecessary call to unbind on rebind. */ |
05394f39 | 2114 | obj->map_and_fenceable = true; |
673a394b | 2115 | |
05394f39 CW |
2116 | drm_mm_put_block(obj->gtt_space); |
2117 | obj->gtt_space = NULL; | |
2118 | obj->gtt_offset = 0; | |
673a394b | 2119 | |
05394f39 | 2120 | if (i915_gem_object_is_purgeable(obj)) |
963b4836 CW |
2121 | i915_gem_object_truncate(obj); |
2122 | ||
8dc1775d | 2123 | return ret; |
673a394b EA |
2124 | } |
2125 | ||
88241785 | 2126 | int |
db53a302 | 2127 | i915_gem_flush_ring(struct intel_ring_buffer *ring, |
54cf91dc CW |
2128 | uint32_t invalidate_domains, |
2129 | uint32_t flush_domains) | |
2130 | { | |
88241785 CW |
2131 | int ret; |
2132 | ||
36d527de CW |
2133 | if (((invalidate_domains | flush_domains) & I915_GEM_GPU_DOMAINS) == 0) |
2134 | return 0; | |
2135 | ||
db53a302 CW |
2136 | trace_i915_gem_ring_flush(ring, invalidate_domains, flush_domains); |
2137 | ||
88241785 CW |
2138 | ret = ring->flush(ring, invalidate_domains, flush_domains); |
2139 | if (ret) | |
2140 | return ret; | |
2141 | ||
36d527de CW |
2142 | if (flush_domains & I915_GEM_GPU_DOMAINS) |
2143 | i915_gem_process_flushing_list(ring, flush_domains); | |
2144 | ||
88241785 | 2145 | return 0; |
54cf91dc CW |
2146 | } |
2147 | ||
b93f9cf1 | 2148 | static int i915_ring_idle(struct intel_ring_buffer *ring, bool do_retire) |
a56ba56c | 2149 | { |
88241785 CW |
2150 | int ret; |
2151 | ||
395b70be | 2152 | if (list_empty(&ring->gpu_write_list) && list_empty(&ring->active_list)) |
64193406 CW |
2153 | return 0; |
2154 | ||
88241785 | 2155 | if (!list_empty(&ring->gpu_write_list)) { |
db53a302 | 2156 | ret = i915_gem_flush_ring(ring, |
0ac74c6b | 2157 | I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS); |
88241785 CW |
2158 | if (ret) |
2159 | return ret; | |
2160 | } | |
2161 | ||
b93f9cf1 BW |
2162 | return i915_wait_request(ring, i915_gem_next_request_seqno(ring), |
2163 | do_retire); | |
a56ba56c CW |
2164 | } |
2165 | ||
b93f9cf1 | 2166 | int i915_gpu_idle(struct drm_device *dev, bool do_retire) |
4df2faf4 DV |
2167 | { |
2168 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1ec14ad3 | 2169 | int ret, i; |
4df2faf4 | 2170 | |
4df2faf4 | 2171 | /* Flush everything onto the inactive list. */ |
1ec14ad3 | 2172 | for (i = 0; i < I915_NUM_RINGS; i++) { |
b93f9cf1 | 2173 | ret = i915_ring_idle(&dev_priv->ring[i], do_retire); |
1ec14ad3 CW |
2174 | if (ret) |
2175 | return ret; | |
2176 | } | |
4df2faf4 | 2177 | |
8a1a49f9 | 2178 | return 0; |
4df2faf4 DV |
2179 | } |
2180 | ||
c6642782 DV |
2181 | static int sandybridge_write_fence_reg(struct drm_i915_gem_object *obj, |
2182 | struct intel_ring_buffer *pipelined) | |
4e901fdc | 2183 | { |
05394f39 | 2184 | struct drm_device *dev = obj->base.dev; |
4e901fdc | 2185 | drm_i915_private_t *dev_priv = dev->dev_private; |
05394f39 CW |
2186 | u32 size = obj->gtt_space->size; |
2187 | int regnum = obj->fence_reg; | |
4e901fdc EA |
2188 | uint64_t val; |
2189 | ||
05394f39 | 2190 | val = (uint64_t)((obj->gtt_offset + size - 4096) & |
c6642782 | 2191 | 0xfffff000) << 32; |
05394f39 CW |
2192 | val |= obj->gtt_offset & 0xfffff000; |
2193 | val |= (uint64_t)((obj->stride / 128) - 1) << | |
4e901fdc EA |
2194 | SANDYBRIDGE_FENCE_PITCH_SHIFT; |
2195 | ||
05394f39 | 2196 | if (obj->tiling_mode == I915_TILING_Y) |
4e901fdc EA |
2197 | val |= 1 << I965_FENCE_TILING_Y_SHIFT; |
2198 | val |= I965_FENCE_REG_VALID; | |
2199 | ||
c6642782 DV |
2200 | if (pipelined) { |
2201 | int ret = intel_ring_begin(pipelined, 6); | |
2202 | if (ret) | |
2203 | return ret; | |
2204 | ||
2205 | intel_ring_emit(pipelined, MI_NOOP); | |
2206 | intel_ring_emit(pipelined, MI_LOAD_REGISTER_IMM(2)); | |
2207 | intel_ring_emit(pipelined, FENCE_REG_SANDYBRIDGE_0 + regnum*8); | |
2208 | intel_ring_emit(pipelined, (u32)val); | |
2209 | intel_ring_emit(pipelined, FENCE_REG_SANDYBRIDGE_0 + regnum*8 + 4); | |
2210 | intel_ring_emit(pipelined, (u32)(val >> 32)); | |
2211 | intel_ring_advance(pipelined); | |
2212 | } else | |
2213 | I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + regnum * 8, val); | |
2214 | ||
2215 | return 0; | |
4e901fdc EA |
2216 | } |
2217 | ||
c6642782 DV |
2218 | static int i965_write_fence_reg(struct drm_i915_gem_object *obj, |
2219 | struct intel_ring_buffer *pipelined) | |
de151cf6 | 2220 | { |
05394f39 | 2221 | struct drm_device *dev = obj->base.dev; |
de151cf6 | 2222 | drm_i915_private_t *dev_priv = dev->dev_private; |
05394f39 CW |
2223 | u32 size = obj->gtt_space->size; |
2224 | int regnum = obj->fence_reg; | |
de151cf6 JB |
2225 | uint64_t val; |
2226 | ||
05394f39 | 2227 | val = (uint64_t)((obj->gtt_offset + size - 4096) & |
de151cf6 | 2228 | 0xfffff000) << 32; |
05394f39 CW |
2229 | val |= obj->gtt_offset & 0xfffff000; |
2230 | val |= ((obj->stride / 128) - 1) << I965_FENCE_PITCH_SHIFT; | |
2231 | if (obj->tiling_mode == I915_TILING_Y) | |
de151cf6 JB |
2232 | val |= 1 << I965_FENCE_TILING_Y_SHIFT; |
2233 | val |= I965_FENCE_REG_VALID; | |
2234 | ||
c6642782 DV |
2235 | if (pipelined) { |
2236 | int ret = intel_ring_begin(pipelined, 6); | |
2237 | if (ret) | |
2238 | return ret; | |
2239 | ||
2240 | intel_ring_emit(pipelined, MI_NOOP); | |
2241 | intel_ring_emit(pipelined, MI_LOAD_REGISTER_IMM(2)); | |
2242 | intel_ring_emit(pipelined, FENCE_REG_965_0 + regnum*8); | |
2243 | intel_ring_emit(pipelined, (u32)val); | |
2244 | intel_ring_emit(pipelined, FENCE_REG_965_0 + regnum*8 + 4); | |
2245 | intel_ring_emit(pipelined, (u32)(val >> 32)); | |
2246 | intel_ring_advance(pipelined); | |
2247 | } else | |
2248 | I915_WRITE64(FENCE_REG_965_0 + regnum * 8, val); | |
2249 | ||
2250 | return 0; | |
de151cf6 JB |
2251 | } |
2252 | ||
c6642782 DV |
2253 | static int i915_write_fence_reg(struct drm_i915_gem_object *obj, |
2254 | struct intel_ring_buffer *pipelined) | |
de151cf6 | 2255 | { |
05394f39 | 2256 | struct drm_device *dev = obj->base.dev; |
de151cf6 | 2257 | drm_i915_private_t *dev_priv = dev->dev_private; |
05394f39 | 2258 | u32 size = obj->gtt_space->size; |
c6642782 | 2259 | u32 fence_reg, val, pitch_val; |
0f973f27 | 2260 | int tile_width; |
de151cf6 | 2261 | |
c6642782 DV |
2262 | if (WARN((obj->gtt_offset & ~I915_FENCE_START_MASK) || |
2263 | (size & -size) != size || | |
2264 | (obj->gtt_offset & (size - 1)), | |
2265 | "object 0x%08x [fenceable? %d] not 1M or pot-size (0x%08x) aligned\n", | |
2266 | obj->gtt_offset, obj->map_and_fenceable, size)) | |
2267 | return -EINVAL; | |
de151cf6 | 2268 | |
c6642782 | 2269 | if (obj->tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev)) |
0f973f27 | 2270 | tile_width = 128; |
de151cf6 | 2271 | else |
0f973f27 JB |
2272 | tile_width = 512; |
2273 | ||
2274 | /* Note: pitch better be a power of two tile widths */ | |
05394f39 | 2275 | pitch_val = obj->stride / tile_width; |
0f973f27 | 2276 | pitch_val = ffs(pitch_val) - 1; |
de151cf6 | 2277 | |
05394f39 CW |
2278 | val = obj->gtt_offset; |
2279 | if (obj->tiling_mode == I915_TILING_Y) | |
de151cf6 | 2280 | val |= 1 << I830_FENCE_TILING_Y_SHIFT; |
a00b10c3 | 2281 | val |= I915_FENCE_SIZE_BITS(size); |
de151cf6 JB |
2282 | val |= pitch_val << I830_FENCE_PITCH_SHIFT; |
2283 | val |= I830_FENCE_REG_VALID; | |
2284 | ||
05394f39 | 2285 | fence_reg = obj->fence_reg; |
a00b10c3 CW |
2286 | if (fence_reg < 8) |
2287 | fence_reg = FENCE_REG_830_0 + fence_reg * 4; | |
dc529a4f | 2288 | else |
a00b10c3 | 2289 | fence_reg = FENCE_REG_945_8 + (fence_reg - 8) * 4; |
c6642782 DV |
2290 | |
2291 | if (pipelined) { | |
2292 | int ret = intel_ring_begin(pipelined, 4); | |
2293 | if (ret) | |
2294 | return ret; | |
2295 | ||
2296 | intel_ring_emit(pipelined, MI_NOOP); | |
2297 | intel_ring_emit(pipelined, MI_LOAD_REGISTER_IMM(1)); | |
2298 | intel_ring_emit(pipelined, fence_reg); | |
2299 | intel_ring_emit(pipelined, val); | |
2300 | intel_ring_advance(pipelined); | |
2301 | } else | |
2302 | I915_WRITE(fence_reg, val); | |
2303 | ||
2304 | return 0; | |
de151cf6 JB |
2305 | } |
2306 | ||
c6642782 DV |
2307 | static int i830_write_fence_reg(struct drm_i915_gem_object *obj, |
2308 | struct intel_ring_buffer *pipelined) | |
de151cf6 | 2309 | { |
05394f39 | 2310 | struct drm_device *dev = obj->base.dev; |
de151cf6 | 2311 | drm_i915_private_t *dev_priv = dev->dev_private; |
05394f39 CW |
2312 | u32 size = obj->gtt_space->size; |
2313 | int regnum = obj->fence_reg; | |
de151cf6 JB |
2314 | uint32_t val; |
2315 | uint32_t pitch_val; | |
2316 | ||
c6642782 DV |
2317 | if (WARN((obj->gtt_offset & ~I830_FENCE_START_MASK) || |
2318 | (size & -size) != size || | |
2319 | (obj->gtt_offset & (size - 1)), | |
2320 | "object 0x%08x not 512K or pot-size 0x%08x aligned\n", | |
2321 | obj->gtt_offset, size)) | |
2322 | return -EINVAL; | |
de151cf6 | 2323 | |
05394f39 | 2324 | pitch_val = obj->stride / 128; |
e76a16de | 2325 | pitch_val = ffs(pitch_val) - 1; |
e76a16de | 2326 | |
05394f39 CW |
2327 | val = obj->gtt_offset; |
2328 | if (obj->tiling_mode == I915_TILING_Y) | |
de151cf6 | 2329 | val |= 1 << I830_FENCE_TILING_Y_SHIFT; |
c6642782 | 2330 | val |= I830_FENCE_SIZE_BITS(size); |
de151cf6 JB |
2331 | val |= pitch_val << I830_FENCE_PITCH_SHIFT; |
2332 | val |= I830_FENCE_REG_VALID; | |
2333 | ||
c6642782 DV |
2334 | if (pipelined) { |
2335 | int ret = intel_ring_begin(pipelined, 4); | |
2336 | if (ret) | |
2337 | return ret; | |
2338 | ||
2339 | intel_ring_emit(pipelined, MI_NOOP); | |
2340 | intel_ring_emit(pipelined, MI_LOAD_REGISTER_IMM(1)); | |
2341 | intel_ring_emit(pipelined, FENCE_REG_830_0 + regnum*4); | |
2342 | intel_ring_emit(pipelined, val); | |
2343 | intel_ring_advance(pipelined); | |
2344 | } else | |
2345 | I915_WRITE(FENCE_REG_830_0 + regnum * 4, val); | |
2346 | ||
2347 | return 0; | |
de151cf6 JB |
2348 | } |
2349 | ||
d9e86c0e CW |
2350 | static bool ring_passed_seqno(struct intel_ring_buffer *ring, u32 seqno) |
2351 | { | |
2352 | return i915_seqno_passed(ring->get_seqno(ring), seqno); | |
2353 | } | |
2354 | ||
2355 | static int | |
2356 | i915_gem_object_flush_fence(struct drm_i915_gem_object *obj, | |
ce453d81 | 2357 | struct intel_ring_buffer *pipelined) |
d9e86c0e CW |
2358 | { |
2359 | int ret; | |
2360 | ||
2361 | if (obj->fenced_gpu_access) { | |
88241785 | 2362 | if (obj->base.write_domain & I915_GEM_GPU_DOMAINS) { |
db53a302 | 2363 | ret = i915_gem_flush_ring(obj->last_fenced_ring, |
88241785 CW |
2364 | 0, obj->base.write_domain); |
2365 | if (ret) | |
2366 | return ret; | |
2367 | } | |
d9e86c0e CW |
2368 | |
2369 | obj->fenced_gpu_access = false; | |
2370 | } | |
2371 | ||
2372 | if (obj->last_fenced_seqno && pipelined != obj->last_fenced_ring) { | |
2373 | if (!ring_passed_seqno(obj->last_fenced_ring, | |
2374 | obj->last_fenced_seqno)) { | |
db53a302 | 2375 | ret = i915_wait_request(obj->last_fenced_ring, |
b93f9cf1 BW |
2376 | obj->last_fenced_seqno, |
2377 | true); | |
d9e86c0e CW |
2378 | if (ret) |
2379 | return ret; | |
2380 | } | |
2381 | ||
2382 | obj->last_fenced_seqno = 0; | |
2383 | obj->last_fenced_ring = NULL; | |
2384 | } | |
2385 | ||
63256ec5 CW |
2386 | /* Ensure that all CPU reads are completed before installing a fence |
2387 | * and all writes before removing the fence. | |
2388 | */ | |
2389 | if (obj->base.read_domains & I915_GEM_DOMAIN_GTT) | |
2390 | mb(); | |
2391 | ||
d9e86c0e CW |
2392 | return 0; |
2393 | } | |
2394 | ||
2395 | int | |
2396 | i915_gem_object_put_fence(struct drm_i915_gem_object *obj) | |
2397 | { | |
2398 | int ret; | |
2399 | ||
2400 | if (obj->tiling_mode) | |
2401 | i915_gem_release_mmap(obj); | |
2402 | ||
ce453d81 | 2403 | ret = i915_gem_object_flush_fence(obj, NULL); |
d9e86c0e CW |
2404 | if (ret) |
2405 | return ret; | |
2406 | ||
2407 | if (obj->fence_reg != I915_FENCE_REG_NONE) { | |
2408 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; | |
1690e1eb CW |
2409 | |
2410 | WARN_ON(dev_priv->fence_regs[obj->fence_reg].pin_count); | |
d9e86c0e CW |
2411 | i915_gem_clear_fence_reg(obj->base.dev, |
2412 | &dev_priv->fence_regs[obj->fence_reg]); | |
2413 | ||
2414 | obj->fence_reg = I915_FENCE_REG_NONE; | |
2415 | } | |
2416 | ||
2417 | return 0; | |
2418 | } | |
2419 | ||
2420 | static struct drm_i915_fence_reg * | |
2421 | i915_find_fence_reg(struct drm_device *dev, | |
2422 | struct intel_ring_buffer *pipelined) | |
ae3db24a | 2423 | { |
ae3db24a | 2424 | struct drm_i915_private *dev_priv = dev->dev_private; |
d9e86c0e CW |
2425 | struct drm_i915_fence_reg *reg, *first, *avail; |
2426 | int i; | |
ae3db24a DV |
2427 | |
2428 | /* First try to find a free reg */ | |
d9e86c0e | 2429 | avail = NULL; |
ae3db24a DV |
2430 | for (i = dev_priv->fence_reg_start; i < dev_priv->num_fence_regs; i++) { |
2431 | reg = &dev_priv->fence_regs[i]; | |
2432 | if (!reg->obj) | |
d9e86c0e | 2433 | return reg; |
ae3db24a | 2434 | |
1690e1eb | 2435 | if (!reg->pin_count) |
d9e86c0e | 2436 | avail = reg; |
ae3db24a DV |
2437 | } |
2438 | ||
d9e86c0e CW |
2439 | if (avail == NULL) |
2440 | return NULL; | |
ae3db24a DV |
2441 | |
2442 | /* None available, try to steal one or wait for a user to finish */ | |
d9e86c0e CW |
2443 | avail = first = NULL; |
2444 | list_for_each_entry(reg, &dev_priv->mm.fence_list, lru_list) { | |
1690e1eb | 2445 | if (reg->pin_count) |
ae3db24a DV |
2446 | continue; |
2447 | ||
d9e86c0e CW |
2448 | if (first == NULL) |
2449 | first = reg; | |
2450 | ||
2451 | if (!pipelined || | |
2452 | !reg->obj->last_fenced_ring || | |
2453 | reg->obj->last_fenced_ring == pipelined) { | |
2454 | avail = reg; | |
2455 | break; | |
2456 | } | |
ae3db24a DV |
2457 | } |
2458 | ||
d9e86c0e CW |
2459 | if (avail == NULL) |
2460 | avail = first; | |
ae3db24a | 2461 | |
a00b10c3 | 2462 | return avail; |
ae3db24a DV |
2463 | } |
2464 | ||
de151cf6 | 2465 | /** |
d9e86c0e | 2466 | * i915_gem_object_get_fence - set up a fence reg for an object |
de151cf6 | 2467 | * @obj: object to map through a fence reg |
d9e86c0e CW |
2468 | * @pipelined: ring on which to queue the change, or NULL for CPU access |
2469 | * @interruptible: must we wait uninterruptibly for the register to retire? | |
de151cf6 JB |
2470 | * |
2471 | * When mapping objects through the GTT, userspace wants to be able to write | |
2472 | * to them without having to worry about swizzling if the object is tiled. | |
2473 | * | |
2474 | * This function walks the fence regs looking for a free one for @obj, | |
2475 | * stealing one if it can't find any. | |
2476 | * | |
2477 | * It then sets up the reg based on the object's properties: address, pitch | |
2478 | * and tiling format. | |
2479 | */ | |
8c4b8c3f | 2480 | int |
d9e86c0e | 2481 | i915_gem_object_get_fence(struct drm_i915_gem_object *obj, |
ce453d81 | 2482 | struct intel_ring_buffer *pipelined) |
de151cf6 | 2483 | { |
05394f39 | 2484 | struct drm_device *dev = obj->base.dev; |
79e53945 | 2485 | struct drm_i915_private *dev_priv = dev->dev_private; |
d9e86c0e | 2486 | struct drm_i915_fence_reg *reg; |
ae3db24a | 2487 | int ret; |
de151cf6 | 2488 | |
6bda10d1 CW |
2489 | /* XXX disable pipelining. There are bugs. Shocking. */ |
2490 | pipelined = NULL; | |
2491 | ||
d9e86c0e | 2492 | /* Just update our place in the LRU if our fence is getting reused. */ |
05394f39 CW |
2493 | if (obj->fence_reg != I915_FENCE_REG_NONE) { |
2494 | reg = &dev_priv->fence_regs[obj->fence_reg]; | |
007cc8ac | 2495 | list_move_tail(®->lru_list, &dev_priv->mm.fence_list); |
d9e86c0e | 2496 | |
29c5a587 CW |
2497 | if (obj->tiling_changed) { |
2498 | ret = i915_gem_object_flush_fence(obj, pipelined); | |
2499 | if (ret) | |
2500 | return ret; | |
2501 | ||
2502 | if (!obj->fenced_gpu_access && !obj->last_fenced_seqno) | |
2503 | pipelined = NULL; | |
2504 | ||
2505 | if (pipelined) { | |
2506 | reg->setup_seqno = | |
2507 | i915_gem_next_request_seqno(pipelined); | |
2508 | obj->last_fenced_seqno = reg->setup_seqno; | |
2509 | obj->last_fenced_ring = pipelined; | |
2510 | } | |
2511 | ||
2512 | goto update; | |
2513 | } | |
d9e86c0e CW |
2514 | |
2515 | if (!pipelined) { | |
2516 | if (reg->setup_seqno) { | |
2517 | if (!ring_passed_seqno(obj->last_fenced_ring, | |
2518 | reg->setup_seqno)) { | |
db53a302 | 2519 | ret = i915_wait_request(obj->last_fenced_ring, |
b93f9cf1 BW |
2520 | reg->setup_seqno, |
2521 | true); | |
d9e86c0e CW |
2522 | if (ret) |
2523 | return ret; | |
2524 | } | |
2525 | ||
2526 | reg->setup_seqno = 0; | |
2527 | } | |
2528 | } else if (obj->last_fenced_ring && | |
2529 | obj->last_fenced_ring != pipelined) { | |
ce453d81 | 2530 | ret = i915_gem_object_flush_fence(obj, pipelined); |
d9e86c0e CW |
2531 | if (ret) |
2532 | return ret; | |
d9e86c0e CW |
2533 | } |
2534 | ||
a09ba7fa EA |
2535 | return 0; |
2536 | } | |
2537 | ||
d9e86c0e CW |
2538 | reg = i915_find_fence_reg(dev, pipelined); |
2539 | if (reg == NULL) | |
39965b37 | 2540 | return -EDEADLK; |
de151cf6 | 2541 | |
ce453d81 | 2542 | ret = i915_gem_object_flush_fence(obj, pipelined); |
d9e86c0e | 2543 | if (ret) |
ae3db24a | 2544 | return ret; |
de151cf6 | 2545 | |
d9e86c0e CW |
2546 | if (reg->obj) { |
2547 | struct drm_i915_gem_object *old = reg->obj; | |
2548 | ||
2549 | drm_gem_object_reference(&old->base); | |
2550 | ||
2551 | if (old->tiling_mode) | |
2552 | i915_gem_release_mmap(old); | |
2553 | ||
ce453d81 | 2554 | ret = i915_gem_object_flush_fence(old, pipelined); |
d9e86c0e CW |
2555 | if (ret) { |
2556 | drm_gem_object_unreference(&old->base); | |
2557 | return ret; | |
2558 | } | |
2559 | ||
2560 | if (old->last_fenced_seqno == 0 && obj->last_fenced_seqno == 0) | |
2561 | pipelined = NULL; | |
2562 | ||
2563 | old->fence_reg = I915_FENCE_REG_NONE; | |
2564 | old->last_fenced_ring = pipelined; | |
2565 | old->last_fenced_seqno = | |
db53a302 | 2566 | pipelined ? i915_gem_next_request_seqno(pipelined) : 0; |
d9e86c0e CW |
2567 | |
2568 | drm_gem_object_unreference(&old->base); | |
2569 | } else if (obj->last_fenced_seqno == 0) | |
2570 | pipelined = NULL; | |
a09ba7fa | 2571 | |
de151cf6 | 2572 | reg->obj = obj; |
d9e86c0e CW |
2573 | list_move_tail(®->lru_list, &dev_priv->mm.fence_list); |
2574 | obj->fence_reg = reg - dev_priv->fence_regs; | |
2575 | obj->last_fenced_ring = pipelined; | |
de151cf6 | 2576 | |
d9e86c0e | 2577 | reg->setup_seqno = |
db53a302 | 2578 | pipelined ? i915_gem_next_request_seqno(pipelined) : 0; |
d9e86c0e CW |
2579 | obj->last_fenced_seqno = reg->setup_seqno; |
2580 | ||
2581 | update: | |
2582 | obj->tiling_changed = false; | |
e259befd | 2583 | switch (INTEL_INFO(dev)->gen) { |
25aebfc3 | 2584 | case 7: |
e259befd | 2585 | case 6: |
c6642782 | 2586 | ret = sandybridge_write_fence_reg(obj, pipelined); |
e259befd CW |
2587 | break; |
2588 | case 5: | |
2589 | case 4: | |
c6642782 | 2590 | ret = i965_write_fence_reg(obj, pipelined); |
e259befd CW |
2591 | break; |
2592 | case 3: | |
c6642782 | 2593 | ret = i915_write_fence_reg(obj, pipelined); |
e259befd CW |
2594 | break; |
2595 | case 2: | |
c6642782 | 2596 | ret = i830_write_fence_reg(obj, pipelined); |
e259befd CW |
2597 | break; |
2598 | } | |
d9ddcb96 | 2599 | |
c6642782 | 2600 | return ret; |
de151cf6 JB |
2601 | } |
2602 | ||
2603 | /** | |
2604 | * i915_gem_clear_fence_reg - clear out fence register info | |
2605 | * @obj: object to clear | |
2606 | * | |
2607 | * Zeroes out the fence register itself and clears out the associated | |
05394f39 | 2608 | * data structures in dev_priv and obj. |
de151cf6 JB |
2609 | */ |
2610 | static void | |
d9e86c0e CW |
2611 | i915_gem_clear_fence_reg(struct drm_device *dev, |
2612 | struct drm_i915_fence_reg *reg) | |
de151cf6 | 2613 | { |
79e53945 | 2614 | drm_i915_private_t *dev_priv = dev->dev_private; |
d9e86c0e | 2615 | uint32_t fence_reg = reg - dev_priv->fence_regs; |
de151cf6 | 2616 | |
e259befd | 2617 | switch (INTEL_INFO(dev)->gen) { |
25aebfc3 | 2618 | case 7: |
e259befd | 2619 | case 6: |
d9e86c0e | 2620 | I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + fence_reg*8, 0); |
e259befd CW |
2621 | break; |
2622 | case 5: | |
2623 | case 4: | |
d9e86c0e | 2624 | I915_WRITE64(FENCE_REG_965_0 + fence_reg*8, 0); |
e259befd CW |
2625 | break; |
2626 | case 3: | |
d9e86c0e CW |
2627 | if (fence_reg >= 8) |
2628 | fence_reg = FENCE_REG_945_8 + (fence_reg - 8) * 4; | |
dc529a4f | 2629 | else |
e259befd | 2630 | case 2: |
d9e86c0e | 2631 | fence_reg = FENCE_REG_830_0 + fence_reg * 4; |
dc529a4f EA |
2632 | |
2633 | I915_WRITE(fence_reg, 0); | |
e259befd | 2634 | break; |
dc529a4f | 2635 | } |
de151cf6 | 2636 | |
007cc8ac | 2637 | list_del_init(®->lru_list); |
d9e86c0e CW |
2638 | reg->obj = NULL; |
2639 | reg->setup_seqno = 0; | |
1690e1eb | 2640 | reg->pin_count = 0; |
52dc7d32 CW |
2641 | } |
2642 | ||
673a394b EA |
2643 | /** |
2644 | * Finds free space in the GTT aperture and binds the object there. | |
2645 | */ | |
2646 | static int | |
05394f39 | 2647 | i915_gem_object_bind_to_gtt(struct drm_i915_gem_object *obj, |
920afa77 | 2648 | unsigned alignment, |
75e9e915 | 2649 | bool map_and_fenceable) |
673a394b | 2650 | { |
05394f39 | 2651 | struct drm_device *dev = obj->base.dev; |
673a394b | 2652 | drm_i915_private_t *dev_priv = dev->dev_private; |
673a394b | 2653 | struct drm_mm_node *free_space; |
a00b10c3 | 2654 | gfp_t gfpmask = __GFP_NORETRY | __GFP_NOWARN; |
5e783301 | 2655 | u32 size, fence_size, fence_alignment, unfenced_alignment; |
75e9e915 | 2656 | bool mappable, fenceable; |
07f73f69 | 2657 | int ret; |
673a394b | 2658 | |
05394f39 | 2659 | if (obj->madv != I915_MADV_WILLNEED) { |
3ef94daa CW |
2660 | DRM_ERROR("Attempting to bind a purgeable object\n"); |
2661 | return -EINVAL; | |
2662 | } | |
2663 | ||
e28f8711 CW |
2664 | fence_size = i915_gem_get_gtt_size(dev, |
2665 | obj->base.size, | |
2666 | obj->tiling_mode); | |
2667 | fence_alignment = i915_gem_get_gtt_alignment(dev, | |
2668 | obj->base.size, | |
2669 | obj->tiling_mode); | |
2670 | unfenced_alignment = | |
2671 | i915_gem_get_unfenced_gtt_alignment(dev, | |
2672 | obj->base.size, | |
2673 | obj->tiling_mode); | |
a00b10c3 | 2674 | |
673a394b | 2675 | if (alignment == 0) |
5e783301 DV |
2676 | alignment = map_and_fenceable ? fence_alignment : |
2677 | unfenced_alignment; | |
75e9e915 | 2678 | if (map_and_fenceable && alignment & (fence_alignment - 1)) { |
673a394b EA |
2679 | DRM_ERROR("Invalid object alignment requested %u\n", alignment); |
2680 | return -EINVAL; | |
2681 | } | |
2682 | ||
05394f39 | 2683 | size = map_and_fenceable ? fence_size : obj->base.size; |
a00b10c3 | 2684 | |
654fc607 CW |
2685 | /* If the object is bigger than the entire aperture, reject it early |
2686 | * before evicting everything in a vain attempt to find space. | |
2687 | */ | |
05394f39 | 2688 | if (obj->base.size > |
75e9e915 | 2689 | (map_and_fenceable ? dev_priv->mm.gtt_mappable_end : dev_priv->mm.gtt_total)) { |
654fc607 CW |
2690 | DRM_ERROR("Attempting to bind an object larger than the aperture\n"); |
2691 | return -E2BIG; | |
2692 | } | |
2693 | ||
673a394b | 2694 | search_free: |
75e9e915 | 2695 | if (map_and_fenceable) |
920afa77 DV |
2696 | free_space = |
2697 | drm_mm_search_free_in_range(&dev_priv->mm.gtt_space, | |
a00b10c3 | 2698 | size, alignment, 0, |
920afa77 DV |
2699 | dev_priv->mm.gtt_mappable_end, |
2700 | 0); | |
2701 | else | |
2702 | free_space = drm_mm_search_free(&dev_priv->mm.gtt_space, | |
a00b10c3 | 2703 | size, alignment, 0); |
920afa77 DV |
2704 | |
2705 | if (free_space != NULL) { | |
75e9e915 | 2706 | if (map_and_fenceable) |
05394f39 | 2707 | obj->gtt_space = |
920afa77 | 2708 | drm_mm_get_block_range_generic(free_space, |
a00b10c3 | 2709 | size, alignment, 0, |
920afa77 DV |
2710 | dev_priv->mm.gtt_mappable_end, |
2711 | 0); | |
2712 | else | |
05394f39 | 2713 | obj->gtt_space = |
a00b10c3 | 2714 | drm_mm_get_block(free_space, size, alignment); |
920afa77 | 2715 | } |
05394f39 | 2716 | if (obj->gtt_space == NULL) { |
673a394b EA |
2717 | /* If the gtt is empty and we're still having trouble |
2718 | * fitting our object in, we're out of memory. | |
2719 | */ | |
75e9e915 DV |
2720 | ret = i915_gem_evict_something(dev, size, alignment, |
2721 | map_and_fenceable); | |
9731129c | 2722 | if (ret) |
673a394b | 2723 | return ret; |
9731129c | 2724 | |
673a394b EA |
2725 | goto search_free; |
2726 | } | |
2727 | ||
e5281ccd | 2728 | ret = i915_gem_object_get_pages_gtt(obj, gfpmask); |
673a394b | 2729 | if (ret) { |
05394f39 CW |
2730 | drm_mm_put_block(obj->gtt_space); |
2731 | obj->gtt_space = NULL; | |
07f73f69 CW |
2732 | |
2733 | if (ret == -ENOMEM) { | |
809b6334 CW |
2734 | /* first try to reclaim some memory by clearing the GTT */ |
2735 | ret = i915_gem_evict_everything(dev, false); | |
07f73f69 | 2736 | if (ret) { |
07f73f69 | 2737 | /* now try to shrink everyone else */ |
4bdadb97 CW |
2738 | if (gfpmask) { |
2739 | gfpmask = 0; | |
2740 | goto search_free; | |
07f73f69 CW |
2741 | } |
2742 | ||
809b6334 | 2743 | return -ENOMEM; |
07f73f69 CW |
2744 | } |
2745 | ||
2746 | goto search_free; | |
2747 | } | |
2748 | ||
673a394b EA |
2749 | return ret; |
2750 | } | |
2751 | ||
7c2e6fdf DV |
2752 | ret = i915_gem_gtt_bind_object(obj); |
2753 | if (ret) { | |
e5281ccd | 2754 | i915_gem_object_put_pages_gtt(obj); |
05394f39 CW |
2755 | drm_mm_put_block(obj->gtt_space); |
2756 | obj->gtt_space = NULL; | |
07f73f69 | 2757 | |
809b6334 | 2758 | if (i915_gem_evict_everything(dev, false)) |
07f73f69 | 2759 | return ret; |
07f73f69 CW |
2760 | |
2761 | goto search_free; | |
673a394b | 2762 | } |
673a394b | 2763 | |
6299f992 | 2764 | list_add_tail(&obj->gtt_list, &dev_priv->mm.gtt_list); |
05394f39 | 2765 | list_add_tail(&obj->mm_list, &dev_priv->mm.inactive_list); |
bf1a1092 | 2766 | |
673a394b EA |
2767 | /* Assert that the object is not currently in any GPU domain. As it |
2768 | * wasn't in the GTT, there shouldn't be any way it could have been in | |
2769 | * a GPU cache | |
2770 | */ | |
05394f39 CW |
2771 | BUG_ON(obj->base.read_domains & I915_GEM_GPU_DOMAINS); |
2772 | BUG_ON(obj->base.write_domain & I915_GEM_GPU_DOMAINS); | |
673a394b | 2773 | |
6299f992 | 2774 | obj->gtt_offset = obj->gtt_space->start; |
1c5d22f7 | 2775 | |
75e9e915 | 2776 | fenceable = |
05394f39 | 2777 | obj->gtt_space->size == fence_size && |
0206e353 | 2778 | (obj->gtt_space->start & (fence_alignment - 1)) == 0; |
a00b10c3 | 2779 | |
75e9e915 | 2780 | mappable = |
05394f39 | 2781 | obj->gtt_offset + obj->base.size <= dev_priv->mm.gtt_mappable_end; |
a00b10c3 | 2782 | |
05394f39 | 2783 | obj->map_and_fenceable = mappable && fenceable; |
75e9e915 | 2784 | |
db53a302 | 2785 | trace_i915_gem_object_bind(obj, map_and_fenceable); |
673a394b EA |
2786 | return 0; |
2787 | } | |
2788 | ||
2789 | void | |
05394f39 | 2790 | i915_gem_clflush_object(struct drm_i915_gem_object *obj) |
673a394b | 2791 | { |
673a394b EA |
2792 | /* If we don't have a page list set up, then we're not pinned |
2793 | * to GPU, and we can ignore the cache flush because it'll happen | |
2794 | * again at bind time. | |
2795 | */ | |
05394f39 | 2796 | if (obj->pages == NULL) |
673a394b EA |
2797 | return; |
2798 | ||
9c23f7fc CW |
2799 | /* If the GPU is snooping the contents of the CPU cache, |
2800 | * we do not need to manually clear the CPU cache lines. However, | |
2801 | * the caches are only snooped when the render cache is | |
2802 | * flushed/invalidated. As we always have to emit invalidations | |
2803 | * and flushes when moving into and out of the RENDER domain, correct | |
2804 | * snooping behaviour occurs naturally as the result of our domain | |
2805 | * tracking. | |
2806 | */ | |
2807 | if (obj->cache_level != I915_CACHE_NONE) | |
2808 | return; | |
2809 | ||
1c5d22f7 | 2810 | trace_i915_gem_object_clflush(obj); |
cfa16a0d | 2811 | |
05394f39 | 2812 | drm_clflush_pages(obj->pages, obj->base.size / PAGE_SIZE); |
673a394b EA |
2813 | } |
2814 | ||
e47c68e9 | 2815 | /** Flushes any GPU write domain for the object if it's dirty. */ |
88241785 | 2816 | static int |
3619df03 | 2817 | i915_gem_object_flush_gpu_write_domain(struct drm_i915_gem_object *obj) |
e47c68e9 | 2818 | { |
05394f39 | 2819 | if ((obj->base.write_domain & I915_GEM_GPU_DOMAINS) == 0) |
88241785 | 2820 | return 0; |
e47c68e9 EA |
2821 | |
2822 | /* Queue the GPU write cache flushing we need. */ | |
db53a302 | 2823 | return i915_gem_flush_ring(obj->ring, 0, obj->base.write_domain); |
e47c68e9 EA |
2824 | } |
2825 | ||
2826 | /** Flushes the GTT write domain for the object if it's dirty. */ | |
2827 | static void | |
05394f39 | 2828 | i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj) |
e47c68e9 | 2829 | { |
1c5d22f7 CW |
2830 | uint32_t old_write_domain; |
2831 | ||
05394f39 | 2832 | if (obj->base.write_domain != I915_GEM_DOMAIN_GTT) |
e47c68e9 EA |
2833 | return; |
2834 | ||
63256ec5 | 2835 | /* No actual flushing is required for the GTT write domain. Writes |
e47c68e9 EA |
2836 | * to it immediately go to main memory as far as we know, so there's |
2837 | * no chipset flush. It also doesn't land in render cache. | |
63256ec5 CW |
2838 | * |
2839 | * However, we do have to enforce the order so that all writes through | |
2840 | * the GTT land before any writes to the device, such as updates to | |
2841 | * the GATT itself. | |
e47c68e9 | 2842 | */ |
63256ec5 CW |
2843 | wmb(); |
2844 | ||
05394f39 CW |
2845 | old_write_domain = obj->base.write_domain; |
2846 | obj->base.write_domain = 0; | |
1c5d22f7 CW |
2847 | |
2848 | trace_i915_gem_object_change_domain(obj, | |
05394f39 | 2849 | obj->base.read_domains, |
1c5d22f7 | 2850 | old_write_domain); |
e47c68e9 EA |
2851 | } |
2852 | ||
2853 | /** Flushes the CPU write domain for the object if it's dirty. */ | |
2854 | static void | |
05394f39 | 2855 | i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj) |
e47c68e9 | 2856 | { |
1c5d22f7 | 2857 | uint32_t old_write_domain; |
e47c68e9 | 2858 | |
05394f39 | 2859 | if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) |
e47c68e9 EA |
2860 | return; |
2861 | ||
2862 | i915_gem_clflush_object(obj); | |
40ce6575 | 2863 | intel_gtt_chipset_flush(); |
05394f39 CW |
2864 | old_write_domain = obj->base.write_domain; |
2865 | obj->base.write_domain = 0; | |
1c5d22f7 CW |
2866 | |
2867 | trace_i915_gem_object_change_domain(obj, | |
05394f39 | 2868 | obj->base.read_domains, |
1c5d22f7 | 2869 | old_write_domain); |
e47c68e9 EA |
2870 | } |
2871 | ||
2ef7eeaa EA |
2872 | /** |
2873 | * Moves a single object to the GTT read, and possibly write domain. | |
2874 | * | |
2875 | * This function returns when the move is complete, including waiting on | |
2876 | * flushes to occur. | |
2877 | */ | |
79e53945 | 2878 | int |
2021746e | 2879 | i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write) |
2ef7eeaa | 2880 | { |
1c5d22f7 | 2881 | uint32_t old_write_domain, old_read_domains; |
e47c68e9 | 2882 | int ret; |
2ef7eeaa | 2883 | |
02354392 | 2884 | /* Not valid to be called on unbound objects. */ |
05394f39 | 2885 | if (obj->gtt_space == NULL) |
02354392 EA |
2886 | return -EINVAL; |
2887 | ||
8d7e3de1 CW |
2888 | if (obj->base.write_domain == I915_GEM_DOMAIN_GTT) |
2889 | return 0; | |
2890 | ||
88241785 CW |
2891 | ret = i915_gem_object_flush_gpu_write_domain(obj); |
2892 | if (ret) | |
2893 | return ret; | |
2894 | ||
87ca9c8a | 2895 | if (obj->pending_gpu_write || write) { |
ce453d81 | 2896 | ret = i915_gem_object_wait_rendering(obj); |
87ca9c8a CW |
2897 | if (ret) |
2898 | return ret; | |
2899 | } | |
2dafb1e0 | 2900 | |
7213342d | 2901 | i915_gem_object_flush_cpu_write_domain(obj); |
1c5d22f7 | 2902 | |
05394f39 CW |
2903 | old_write_domain = obj->base.write_domain; |
2904 | old_read_domains = obj->base.read_domains; | |
1c5d22f7 | 2905 | |
e47c68e9 EA |
2906 | /* It should now be out of any other write domains, and we can update |
2907 | * the domain values for our changes. | |
2908 | */ | |
05394f39 CW |
2909 | BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_GTT) != 0); |
2910 | obj->base.read_domains |= I915_GEM_DOMAIN_GTT; | |
e47c68e9 | 2911 | if (write) { |
05394f39 CW |
2912 | obj->base.read_domains = I915_GEM_DOMAIN_GTT; |
2913 | obj->base.write_domain = I915_GEM_DOMAIN_GTT; | |
2914 | obj->dirty = 1; | |
2ef7eeaa EA |
2915 | } |
2916 | ||
1c5d22f7 CW |
2917 | trace_i915_gem_object_change_domain(obj, |
2918 | old_read_domains, | |
2919 | old_write_domain); | |
2920 | ||
e47c68e9 EA |
2921 | return 0; |
2922 | } | |
2923 | ||
e4ffd173 CW |
2924 | int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj, |
2925 | enum i915_cache_level cache_level) | |
2926 | { | |
7bddb01f DV |
2927 | struct drm_device *dev = obj->base.dev; |
2928 | drm_i915_private_t *dev_priv = dev->dev_private; | |
e4ffd173 CW |
2929 | int ret; |
2930 | ||
2931 | if (obj->cache_level == cache_level) | |
2932 | return 0; | |
2933 | ||
2934 | if (obj->pin_count) { | |
2935 | DRM_DEBUG("can not change the cache level of pinned objects\n"); | |
2936 | return -EBUSY; | |
2937 | } | |
2938 | ||
2939 | if (obj->gtt_space) { | |
2940 | ret = i915_gem_object_finish_gpu(obj); | |
2941 | if (ret) | |
2942 | return ret; | |
2943 | ||
2944 | i915_gem_object_finish_gtt(obj); | |
2945 | ||
2946 | /* Before SandyBridge, you could not use tiling or fence | |
2947 | * registers with snooped memory, so relinquish any fences | |
2948 | * currently pointing to our region in the aperture. | |
2949 | */ | |
2950 | if (INTEL_INFO(obj->base.dev)->gen < 6) { | |
2951 | ret = i915_gem_object_put_fence(obj); | |
2952 | if (ret) | |
2953 | return ret; | |
2954 | } | |
2955 | ||
2956 | i915_gem_gtt_rebind_object(obj, cache_level); | |
7bddb01f DV |
2957 | if (obj->has_aliasing_ppgtt_mapping) |
2958 | i915_ppgtt_bind_object(dev_priv->mm.aliasing_ppgtt, | |
2959 | obj, cache_level); | |
e4ffd173 CW |
2960 | } |
2961 | ||
2962 | if (cache_level == I915_CACHE_NONE) { | |
2963 | u32 old_read_domains, old_write_domain; | |
2964 | ||
2965 | /* If we're coming from LLC cached, then we haven't | |
2966 | * actually been tracking whether the data is in the | |
2967 | * CPU cache or not, since we only allow one bit set | |
2968 | * in obj->write_domain and have been skipping the clflushes. | |
2969 | * Just set it to the CPU cache for now. | |
2970 | */ | |
2971 | WARN_ON(obj->base.write_domain & ~I915_GEM_DOMAIN_CPU); | |
2972 | WARN_ON(obj->base.read_domains & ~I915_GEM_DOMAIN_CPU); | |
2973 | ||
2974 | old_read_domains = obj->base.read_domains; | |
2975 | old_write_domain = obj->base.write_domain; | |
2976 | ||
2977 | obj->base.read_domains = I915_GEM_DOMAIN_CPU; | |
2978 | obj->base.write_domain = I915_GEM_DOMAIN_CPU; | |
2979 | ||
2980 | trace_i915_gem_object_change_domain(obj, | |
2981 | old_read_domains, | |
2982 | old_write_domain); | |
2983 | } | |
2984 | ||
2985 | obj->cache_level = cache_level; | |
2986 | return 0; | |
2987 | } | |
2988 | ||
b9241ea3 | 2989 | /* |
2da3b9b9 CW |
2990 | * Prepare buffer for display plane (scanout, cursors, etc). |
2991 | * Can be called from an uninterruptible phase (modesetting) and allows | |
2992 | * any flushes to be pipelined (for pageflips). | |
2993 | * | |
2994 | * For the display plane, we want to be in the GTT but out of any write | |
2995 | * domains. So in many ways this looks like set_to_gtt_domain() apart from the | |
2996 | * ability to pipeline the waits, pinning and any additional subtleties | |
2997 | * that may differentiate the display plane from ordinary buffers. | |
b9241ea3 ZW |
2998 | */ |
2999 | int | |
2da3b9b9 CW |
3000 | i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj, |
3001 | u32 alignment, | |
919926ae | 3002 | struct intel_ring_buffer *pipelined) |
b9241ea3 | 3003 | { |
2da3b9b9 | 3004 | u32 old_read_domains, old_write_domain; |
b9241ea3 ZW |
3005 | int ret; |
3006 | ||
88241785 CW |
3007 | ret = i915_gem_object_flush_gpu_write_domain(obj); |
3008 | if (ret) | |
3009 | return ret; | |
3010 | ||
0be73284 | 3011 | if (pipelined != obj->ring) { |
ce453d81 | 3012 | ret = i915_gem_object_wait_rendering(obj); |
f0b69efc | 3013 | if (ret == -ERESTARTSYS) |
b9241ea3 ZW |
3014 | return ret; |
3015 | } | |
3016 | ||
a7ef0640 EA |
3017 | /* The display engine is not coherent with the LLC cache on gen6. As |
3018 | * a result, we make sure that the pinning that is about to occur is | |
3019 | * done with uncached PTEs. This is lowest common denominator for all | |
3020 | * chipsets. | |
3021 | * | |
3022 | * However for gen6+, we could do better by using the GFDT bit instead | |
3023 | * of uncaching, which would allow us to flush all the LLC-cached data | |
3024 | * with that bit in the PTE to main memory with just one PIPE_CONTROL. | |
3025 | */ | |
3026 | ret = i915_gem_object_set_cache_level(obj, I915_CACHE_NONE); | |
3027 | if (ret) | |
3028 | return ret; | |
3029 | ||
2da3b9b9 CW |
3030 | /* As the user may map the buffer once pinned in the display plane |
3031 | * (e.g. libkms for the bootup splash), we have to ensure that we | |
3032 | * always use map_and_fenceable for all scanout buffers. | |
3033 | */ | |
3034 | ret = i915_gem_object_pin(obj, alignment, true); | |
3035 | if (ret) | |
3036 | return ret; | |
3037 | ||
b118c1e3 CW |
3038 | i915_gem_object_flush_cpu_write_domain(obj); |
3039 | ||
2da3b9b9 | 3040 | old_write_domain = obj->base.write_domain; |
05394f39 | 3041 | old_read_domains = obj->base.read_domains; |
2da3b9b9 CW |
3042 | |
3043 | /* It should now be out of any other write domains, and we can update | |
3044 | * the domain values for our changes. | |
3045 | */ | |
3046 | BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_GTT) != 0); | |
05394f39 | 3047 | obj->base.read_domains |= I915_GEM_DOMAIN_GTT; |
b9241ea3 ZW |
3048 | |
3049 | trace_i915_gem_object_change_domain(obj, | |
3050 | old_read_domains, | |
2da3b9b9 | 3051 | old_write_domain); |
b9241ea3 ZW |
3052 | |
3053 | return 0; | |
3054 | } | |
3055 | ||
85345517 | 3056 | int |
a8198eea | 3057 | i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj) |
85345517 | 3058 | { |
88241785 CW |
3059 | int ret; |
3060 | ||
a8198eea | 3061 | if ((obj->base.read_domains & I915_GEM_GPU_DOMAINS) == 0) |
85345517 CW |
3062 | return 0; |
3063 | ||
88241785 | 3064 | if (obj->base.write_domain & I915_GEM_GPU_DOMAINS) { |
db53a302 | 3065 | ret = i915_gem_flush_ring(obj->ring, 0, obj->base.write_domain); |
88241785 CW |
3066 | if (ret) |
3067 | return ret; | |
3068 | } | |
85345517 | 3069 | |
c501ae7f CW |
3070 | ret = i915_gem_object_wait_rendering(obj); |
3071 | if (ret) | |
3072 | return ret; | |
3073 | ||
a8198eea CW |
3074 | /* Ensure that we invalidate the GPU's caches and TLBs. */ |
3075 | obj->base.read_domains &= ~I915_GEM_GPU_DOMAINS; | |
c501ae7f | 3076 | return 0; |
85345517 CW |
3077 | } |
3078 | ||
e47c68e9 EA |
3079 | /** |
3080 | * Moves a single object to the CPU read, and possibly write domain. | |
3081 | * | |
3082 | * This function returns when the move is complete, including waiting on | |
3083 | * flushes to occur. | |
3084 | */ | |
3085 | static int | |
919926ae | 3086 | i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write) |
e47c68e9 | 3087 | { |
1c5d22f7 | 3088 | uint32_t old_write_domain, old_read_domains; |
e47c68e9 EA |
3089 | int ret; |
3090 | ||
8d7e3de1 CW |
3091 | if (obj->base.write_domain == I915_GEM_DOMAIN_CPU) |
3092 | return 0; | |
3093 | ||
88241785 CW |
3094 | ret = i915_gem_object_flush_gpu_write_domain(obj); |
3095 | if (ret) | |
3096 | return ret; | |
3097 | ||
ce453d81 | 3098 | ret = i915_gem_object_wait_rendering(obj); |
de18a29e | 3099 | if (ret) |
e47c68e9 | 3100 | return ret; |
2ef7eeaa | 3101 | |
e47c68e9 | 3102 | i915_gem_object_flush_gtt_write_domain(obj); |
2ef7eeaa | 3103 | |
e47c68e9 EA |
3104 | /* If we have a partially-valid cache of the object in the CPU, |
3105 | * finish invalidating it and free the per-page flags. | |
2ef7eeaa | 3106 | */ |
e47c68e9 | 3107 | i915_gem_object_set_to_full_cpu_read_domain(obj); |
2ef7eeaa | 3108 | |
05394f39 CW |
3109 | old_write_domain = obj->base.write_domain; |
3110 | old_read_domains = obj->base.read_domains; | |
1c5d22f7 | 3111 | |
e47c68e9 | 3112 | /* Flush the CPU cache if it's still invalid. */ |
05394f39 | 3113 | if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0) { |
2ef7eeaa | 3114 | i915_gem_clflush_object(obj); |
2ef7eeaa | 3115 | |
05394f39 | 3116 | obj->base.read_domains |= I915_GEM_DOMAIN_CPU; |
2ef7eeaa EA |
3117 | } |
3118 | ||
3119 | /* It should now be out of any other write domains, and we can update | |
3120 | * the domain values for our changes. | |
3121 | */ | |
05394f39 | 3122 | BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_CPU) != 0); |
e47c68e9 EA |
3123 | |
3124 | /* If we're writing through the CPU, then the GPU read domains will | |
3125 | * need to be invalidated at next use. | |
3126 | */ | |
3127 | if (write) { | |
05394f39 CW |
3128 | obj->base.read_domains = I915_GEM_DOMAIN_CPU; |
3129 | obj->base.write_domain = I915_GEM_DOMAIN_CPU; | |
e47c68e9 | 3130 | } |
2ef7eeaa | 3131 | |
1c5d22f7 CW |
3132 | trace_i915_gem_object_change_domain(obj, |
3133 | old_read_domains, | |
3134 | old_write_domain); | |
3135 | ||
2ef7eeaa EA |
3136 | return 0; |
3137 | } | |
3138 | ||
673a394b | 3139 | /** |
e47c68e9 | 3140 | * Moves the object from a partially CPU read to a full one. |
673a394b | 3141 | * |
e47c68e9 EA |
3142 | * Note that this only resolves i915_gem_object_set_cpu_read_domain_range(), |
3143 | * and doesn't handle transitioning from !(read_domains & I915_GEM_DOMAIN_CPU). | |
673a394b | 3144 | */ |
e47c68e9 | 3145 | static void |
05394f39 | 3146 | i915_gem_object_set_to_full_cpu_read_domain(struct drm_i915_gem_object *obj) |
673a394b | 3147 | { |
05394f39 | 3148 | if (!obj->page_cpu_valid) |
e47c68e9 EA |
3149 | return; |
3150 | ||
3151 | /* If we're partially in the CPU read domain, finish moving it in. | |
3152 | */ | |
05394f39 | 3153 | if (obj->base.read_domains & I915_GEM_DOMAIN_CPU) { |
e47c68e9 EA |
3154 | int i; |
3155 | ||
05394f39 CW |
3156 | for (i = 0; i <= (obj->base.size - 1) / PAGE_SIZE; i++) { |
3157 | if (obj->page_cpu_valid[i]) | |
e47c68e9 | 3158 | continue; |
05394f39 | 3159 | drm_clflush_pages(obj->pages + i, 1); |
e47c68e9 | 3160 | } |
e47c68e9 EA |
3161 | } |
3162 | ||
3163 | /* Free the page_cpu_valid mappings which are now stale, whether | |
3164 | * or not we've got I915_GEM_DOMAIN_CPU. | |
3165 | */ | |
05394f39 CW |
3166 | kfree(obj->page_cpu_valid); |
3167 | obj->page_cpu_valid = NULL; | |
e47c68e9 EA |
3168 | } |
3169 | ||
3170 | /** | |
3171 | * Set the CPU read domain on a range of the object. | |
3172 | * | |
3173 | * The object ends up with I915_GEM_DOMAIN_CPU in its read flags although it's | |
3174 | * not entirely valid. The page_cpu_valid member of the object flags which | |
3175 | * pages have been flushed, and will be respected by | |
3176 | * i915_gem_object_set_to_cpu_domain() if it's called on to get a valid mapping | |
3177 | * of the whole object. | |
3178 | * | |
3179 | * This function returns when the move is complete, including waiting on | |
3180 | * flushes to occur. | |
3181 | */ | |
3182 | static int | |
05394f39 | 3183 | i915_gem_object_set_cpu_read_domain_range(struct drm_i915_gem_object *obj, |
e47c68e9 EA |
3184 | uint64_t offset, uint64_t size) |
3185 | { | |
1c5d22f7 | 3186 | uint32_t old_read_domains; |
e47c68e9 | 3187 | int i, ret; |
673a394b | 3188 | |
05394f39 | 3189 | if (offset == 0 && size == obj->base.size) |
e47c68e9 | 3190 | return i915_gem_object_set_to_cpu_domain(obj, 0); |
673a394b | 3191 | |
88241785 CW |
3192 | ret = i915_gem_object_flush_gpu_write_domain(obj); |
3193 | if (ret) | |
3194 | return ret; | |
3195 | ||
ce453d81 | 3196 | ret = i915_gem_object_wait_rendering(obj); |
de18a29e | 3197 | if (ret) |
6a47baa6 | 3198 | return ret; |
de18a29e | 3199 | |
e47c68e9 EA |
3200 | i915_gem_object_flush_gtt_write_domain(obj); |
3201 | ||
3202 | /* If we're already fully in the CPU read domain, we're done. */ | |
05394f39 CW |
3203 | if (obj->page_cpu_valid == NULL && |
3204 | (obj->base.read_domains & I915_GEM_DOMAIN_CPU) != 0) | |
e47c68e9 | 3205 | return 0; |
673a394b | 3206 | |
e47c68e9 EA |
3207 | /* Otherwise, create/clear the per-page CPU read domain flag if we're |
3208 | * newly adding I915_GEM_DOMAIN_CPU | |
3209 | */ | |
05394f39 CW |
3210 | if (obj->page_cpu_valid == NULL) { |
3211 | obj->page_cpu_valid = kzalloc(obj->base.size / PAGE_SIZE, | |
3212 | GFP_KERNEL); | |
3213 | if (obj->page_cpu_valid == NULL) | |
e47c68e9 | 3214 | return -ENOMEM; |
05394f39 CW |
3215 | } else if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0) |
3216 | memset(obj->page_cpu_valid, 0, obj->base.size / PAGE_SIZE); | |
673a394b EA |
3217 | |
3218 | /* Flush the cache on any pages that are still invalid from the CPU's | |
3219 | * perspective. | |
3220 | */ | |
e47c68e9 EA |
3221 | for (i = offset / PAGE_SIZE; i <= (offset + size - 1) / PAGE_SIZE; |
3222 | i++) { | |
05394f39 | 3223 | if (obj->page_cpu_valid[i]) |
673a394b EA |
3224 | continue; |
3225 | ||
05394f39 | 3226 | drm_clflush_pages(obj->pages + i, 1); |
673a394b | 3227 | |
05394f39 | 3228 | obj->page_cpu_valid[i] = 1; |
673a394b EA |
3229 | } |
3230 | ||
e47c68e9 EA |
3231 | /* It should now be out of any other write domains, and we can update |
3232 | * the domain values for our changes. | |
3233 | */ | |
05394f39 | 3234 | BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_CPU) != 0); |
e47c68e9 | 3235 | |
05394f39 CW |
3236 | old_read_domains = obj->base.read_domains; |
3237 | obj->base.read_domains |= I915_GEM_DOMAIN_CPU; | |
e47c68e9 | 3238 | |
1c5d22f7 CW |
3239 | trace_i915_gem_object_change_domain(obj, |
3240 | old_read_domains, | |
05394f39 | 3241 | obj->base.write_domain); |
1c5d22f7 | 3242 | |
673a394b EA |
3243 | return 0; |
3244 | } | |
3245 | ||
673a394b EA |
3246 | /* Throttle our rendering by waiting until the ring has completed our requests |
3247 | * emitted over 20 msec ago. | |
3248 | * | |
b962442e EA |
3249 | * Note that if we were to use the current jiffies each time around the loop, |
3250 | * we wouldn't escape the function with any frames outstanding if the time to | |
3251 | * render a frame was over 20ms. | |
3252 | * | |
673a394b EA |
3253 | * This should get us reasonable parallelism between CPU and GPU but also |
3254 | * relatively low latency when blocking on a particular request to finish. | |
3255 | */ | |
40a5f0de | 3256 | static int |
f787a5f5 | 3257 | i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file) |
40a5f0de | 3258 | { |
f787a5f5 CW |
3259 | struct drm_i915_private *dev_priv = dev->dev_private; |
3260 | struct drm_i915_file_private *file_priv = file->driver_priv; | |
b962442e | 3261 | unsigned long recent_enough = jiffies - msecs_to_jiffies(20); |
f787a5f5 CW |
3262 | struct drm_i915_gem_request *request; |
3263 | struct intel_ring_buffer *ring = NULL; | |
3264 | u32 seqno = 0; | |
3265 | int ret; | |
93533c29 | 3266 | |
e110e8d6 CW |
3267 | if (atomic_read(&dev_priv->mm.wedged)) |
3268 | return -EIO; | |
3269 | ||
1c25595f | 3270 | spin_lock(&file_priv->mm.lock); |
f787a5f5 | 3271 | list_for_each_entry(request, &file_priv->mm.request_list, client_list) { |
b962442e EA |
3272 | if (time_after_eq(request->emitted_jiffies, recent_enough)) |
3273 | break; | |
40a5f0de | 3274 | |
f787a5f5 CW |
3275 | ring = request->ring; |
3276 | seqno = request->seqno; | |
b962442e | 3277 | } |
1c25595f | 3278 | spin_unlock(&file_priv->mm.lock); |
40a5f0de | 3279 | |
f787a5f5 CW |
3280 | if (seqno == 0) |
3281 | return 0; | |
2bc43b5c | 3282 | |
f787a5f5 | 3283 | ret = 0; |
78501eac | 3284 | if (!i915_seqno_passed(ring->get_seqno(ring), seqno)) { |
f787a5f5 CW |
3285 | /* And wait for the seqno passing without holding any locks and |
3286 | * causing extra latency for others. This is safe as the irq | |
3287 | * generation is designed to be run atomically and so is | |
3288 | * lockless. | |
3289 | */ | |
b13c2b96 CW |
3290 | if (ring->irq_get(ring)) { |
3291 | ret = wait_event_interruptible(ring->irq_queue, | |
3292 | i915_seqno_passed(ring->get_seqno(ring), seqno) | |
3293 | || atomic_read(&dev_priv->mm.wedged)); | |
3294 | ring->irq_put(ring); | |
40a5f0de | 3295 | |
b13c2b96 CW |
3296 | if (ret == 0 && atomic_read(&dev_priv->mm.wedged)) |
3297 | ret = -EIO; | |
e959b5db EA |
3298 | } else if (wait_for_atomic(i915_seqno_passed(ring->get_seqno(ring), |
3299 | seqno) || | |
7ea29b13 EA |
3300 | atomic_read(&dev_priv->mm.wedged), 3000)) { |
3301 | ret = -EBUSY; | |
b13c2b96 | 3302 | } |
40a5f0de EA |
3303 | } |
3304 | ||
f787a5f5 CW |
3305 | if (ret == 0) |
3306 | queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, 0); | |
40a5f0de EA |
3307 | |
3308 | return ret; | |
3309 | } | |
3310 | ||
673a394b | 3311 | int |
05394f39 CW |
3312 | i915_gem_object_pin(struct drm_i915_gem_object *obj, |
3313 | uint32_t alignment, | |
75e9e915 | 3314 | bool map_and_fenceable) |
673a394b | 3315 | { |
05394f39 | 3316 | struct drm_device *dev = obj->base.dev; |
f13d3f73 | 3317 | struct drm_i915_private *dev_priv = dev->dev_private; |
673a394b EA |
3318 | int ret; |
3319 | ||
05394f39 | 3320 | BUG_ON(obj->pin_count == DRM_I915_GEM_OBJECT_MAX_PIN_COUNT); |
23bc5982 | 3321 | WARN_ON(i915_verify_lists(dev)); |
ac0c6b5a | 3322 | |
05394f39 CW |
3323 | if (obj->gtt_space != NULL) { |
3324 | if ((alignment && obj->gtt_offset & (alignment - 1)) || | |
3325 | (map_and_fenceable && !obj->map_and_fenceable)) { | |
3326 | WARN(obj->pin_count, | |
ae7d49d8 | 3327 | "bo is already pinned with incorrect alignment:" |
75e9e915 DV |
3328 | " offset=%x, req.alignment=%x, req.map_and_fenceable=%d," |
3329 | " obj->map_and_fenceable=%d\n", | |
05394f39 | 3330 | obj->gtt_offset, alignment, |
75e9e915 | 3331 | map_and_fenceable, |
05394f39 | 3332 | obj->map_and_fenceable); |
ac0c6b5a CW |
3333 | ret = i915_gem_object_unbind(obj); |
3334 | if (ret) | |
3335 | return ret; | |
3336 | } | |
3337 | } | |
3338 | ||
05394f39 | 3339 | if (obj->gtt_space == NULL) { |
a00b10c3 | 3340 | ret = i915_gem_object_bind_to_gtt(obj, alignment, |
75e9e915 | 3341 | map_and_fenceable); |
9731129c | 3342 | if (ret) |
673a394b | 3343 | return ret; |
22c344e9 | 3344 | } |
76446cac | 3345 | |
05394f39 | 3346 | if (obj->pin_count++ == 0) { |
05394f39 CW |
3347 | if (!obj->active) |
3348 | list_move_tail(&obj->mm_list, | |
f13d3f73 | 3349 | &dev_priv->mm.pinned_list); |
673a394b | 3350 | } |
6299f992 | 3351 | obj->pin_mappable |= map_and_fenceable; |
673a394b | 3352 | |
23bc5982 | 3353 | WARN_ON(i915_verify_lists(dev)); |
673a394b EA |
3354 | return 0; |
3355 | } | |
3356 | ||
3357 | void | |
05394f39 | 3358 | i915_gem_object_unpin(struct drm_i915_gem_object *obj) |
673a394b | 3359 | { |
05394f39 | 3360 | struct drm_device *dev = obj->base.dev; |
673a394b | 3361 | drm_i915_private_t *dev_priv = dev->dev_private; |
673a394b | 3362 | |
23bc5982 | 3363 | WARN_ON(i915_verify_lists(dev)); |
05394f39 CW |
3364 | BUG_ON(obj->pin_count == 0); |
3365 | BUG_ON(obj->gtt_space == NULL); | |
673a394b | 3366 | |
05394f39 CW |
3367 | if (--obj->pin_count == 0) { |
3368 | if (!obj->active) | |
3369 | list_move_tail(&obj->mm_list, | |
673a394b | 3370 | &dev_priv->mm.inactive_list); |
6299f992 | 3371 | obj->pin_mappable = false; |
673a394b | 3372 | } |
23bc5982 | 3373 | WARN_ON(i915_verify_lists(dev)); |
673a394b EA |
3374 | } |
3375 | ||
3376 | int | |
3377 | i915_gem_pin_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 3378 | struct drm_file *file) |
673a394b EA |
3379 | { |
3380 | struct drm_i915_gem_pin *args = data; | |
05394f39 | 3381 | struct drm_i915_gem_object *obj; |
673a394b EA |
3382 | int ret; |
3383 | ||
1d7cfea1 CW |
3384 | ret = i915_mutex_lock_interruptible(dev); |
3385 | if (ret) | |
3386 | return ret; | |
673a394b | 3387 | |
05394f39 | 3388 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 3389 | if (&obj->base == NULL) { |
1d7cfea1 CW |
3390 | ret = -ENOENT; |
3391 | goto unlock; | |
673a394b | 3392 | } |
673a394b | 3393 | |
05394f39 | 3394 | if (obj->madv != I915_MADV_WILLNEED) { |
bb6baf76 | 3395 | DRM_ERROR("Attempting to pin a purgeable buffer\n"); |
1d7cfea1 CW |
3396 | ret = -EINVAL; |
3397 | goto out; | |
3ef94daa CW |
3398 | } |
3399 | ||
05394f39 | 3400 | if (obj->pin_filp != NULL && obj->pin_filp != file) { |
79e53945 JB |
3401 | DRM_ERROR("Already pinned in i915_gem_pin_ioctl(): %d\n", |
3402 | args->handle); | |
1d7cfea1 CW |
3403 | ret = -EINVAL; |
3404 | goto out; | |
79e53945 JB |
3405 | } |
3406 | ||
05394f39 CW |
3407 | obj->user_pin_count++; |
3408 | obj->pin_filp = file; | |
3409 | if (obj->user_pin_count == 1) { | |
75e9e915 | 3410 | ret = i915_gem_object_pin(obj, args->alignment, true); |
1d7cfea1 CW |
3411 | if (ret) |
3412 | goto out; | |
673a394b EA |
3413 | } |
3414 | ||
3415 | /* XXX - flush the CPU caches for pinned objects | |
3416 | * as the X server doesn't manage domains yet | |
3417 | */ | |
e47c68e9 | 3418 | i915_gem_object_flush_cpu_write_domain(obj); |
05394f39 | 3419 | args->offset = obj->gtt_offset; |
1d7cfea1 | 3420 | out: |
05394f39 | 3421 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 3422 | unlock: |
673a394b | 3423 | mutex_unlock(&dev->struct_mutex); |
1d7cfea1 | 3424 | return ret; |
673a394b EA |
3425 | } |
3426 | ||
3427 | int | |
3428 | i915_gem_unpin_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 3429 | struct drm_file *file) |
673a394b EA |
3430 | { |
3431 | struct drm_i915_gem_pin *args = data; | |
05394f39 | 3432 | struct drm_i915_gem_object *obj; |
76c1dec1 | 3433 | int ret; |
673a394b | 3434 | |
1d7cfea1 CW |
3435 | ret = i915_mutex_lock_interruptible(dev); |
3436 | if (ret) | |
3437 | return ret; | |
673a394b | 3438 | |
05394f39 | 3439 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 3440 | if (&obj->base == NULL) { |
1d7cfea1 CW |
3441 | ret = -ENOENT; |
3442 | goto unlock; | |
673a394b | 3443 | } |
76c1dec1 | 3444 | |
05394f39 | 3445 | if (obj->pin_filp != file) { |
79e53945 JB |
3446 | DRM_ERROR("Not pinned by caller in i915_gem_pin_ioctl(): %d\n", |
3447 | args->handle); | |
1d7cfea1 CW |
3448 | ret = -EINVAL; |
3449 | goto out; | |
79e53945 | 3450 | } |
05394f39 CW |
3451 | obj->user_pin_count--; |
3452 | if (obj->user_pin_count == 0) { | |
3453 | obj->pin_filp = NULL; | |
79e53945 JB |
3454 | i915_gem_object_unpin(obj); |
3455 | } | |
673a394b | 3456 | |
1d7cfea1 | 3457 | out: |
05394f39 | 3458 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 3459 | unlock: |
673a394b | 3460 | mutex_unlock(&dev->struct_mutex); |
1d7cfea1 | 3461 | return ret; |
673a394b EA |
3462 | } |
3463 | ||
3464 | int | |
3465 | i915_gem_busy_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 3466 | struct drm_file *file) |
673a394b EA |
3467 | { |
3468 | struct drm_i915_gem_busy *args = data; | |
05394f39 | 3469 | struct drm_i915_gem_object *obj; |
30dbf0c0 CW |
3470 | int ret; |
3471 | ||
76c1dec1 | 3472 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 3473 | if (ret) |
76c1dec1 | 3474 | return ret; |
673a394b | 3475 | |
05394f39 | 3476 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 3477 | if (&obj->base == NULL) { |
1d7cfea1 CW |
3478 | ret = -ENOENT; |
3479 | goto unlock; | |
673a394b | 3480 | } |
d1b851fc | 3481 | |
0be555b6 CW |
3482 | /* Count all active objects as busy, even if they are currently not used |
3483 | * by the gpu. Users of this interface expect objects to eventually | |
3484 | * become non-busy without any further actions, therefore emit any | |
3485 | * necessary flushes here. | |
c4de0a5d | 3486 | */ |
05394f39 | 3487 | args->busy = obj->active; |
0be555b6 CW |
3488 | if (args->busy) { |
3489 | /* Unconditionally flush objects, even when the gpu still uses this | |
3490 | * object. Userspace calling this function indicates that it wants to | |
3491 | * use this buffer rather sooner than later, so issuing the required | |
3492 | * flush earlier is beneficial. | |
3493 | */ | |
1a1c6976 | 3494 | if (obj->base.write_domain & I915_GEM_GPU_DOMAINS) { |
db53a302 | 3495 | ret = i915_gem_flush_ring(obj->ring, |
88241785 | 3496 | 0, obj->base.write_domain); |
1a1c6976 CW |
3497 | } else if (obj->ring->outstanding_lazy_request == |
3498 | obj->last_rendering_seqno) { | |
3499 | struct drm_i915_gem_request *request; | |
3500 | ||
7a194876 CW |
3501 | /* This ring is not being cleared by active usage, |
3502 | * so emit a request to do so. | |
3503 | */ | |
1a1c6976 | 3504 | request = kzalloc(sizeof(*request), GFP_KERNEL); |
457eafce | 3505 | if (request) { |
0206e353 | 3506 | ret = i915_add_request(obj->ring, NULL, request); |
457eafce RM |
3507 | if (ret) |
3508 | kfree(request); | |
3509 | } else | |
7a194876 CW |
3510 | ret = -ENOMEM; |
3511 | } | |
0be555b6 CW |
3512 | |
3513 | /* Update the active list for the hardware's current position. | |
3514 | * Otherwise this only updates on a delayed timer or when irqs | |
3515 | * are actually unmasked, and our working set ends up being | |
3516 | * larger than required. | |
3517 | */ | |
db53a302 | 3518 | i915_gem_retire_requests_ring(obj->ring); |
0be555b6 | 3519 | |
05394f39 | 3520 | args->busy = obj->active; |
0be555b6 | 3521 | } |
673a394b | 3522 | |
05394f39 | 3523 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 3524 | unlock: |
673a394b | 3525 | mutex_unlock(&dev->struct_mutex); |
1d7cfea1 | 3526 | return ret; |
673a394b EA |
3527 | } |
3528 | ||
3529 | int | |
3530 | i915_gem_throttle_ioctl(struct drm_device *dev, void *data, | |
3531 | struct drm_file *file_priv) | |
3532 | { | |
0206e353 | 3533 | return i915_gem_ring_throttle(dev, file_priv); |
673a394b EA |
3534 | } |
3535 | ||
3ef94daa CW |
3536 | int |
3537 | i915_gem_madvise_ioctl(struct drm_device *dev, void *data, | |
3538 | struct drm_file *file_priv) | |
3539 | { | |
3540 | struct drm_i915_gem_madvise *args = data; | |
05394f39 | 3541 | struct drm_i915_gem_object *obj; |
76c1dec1 | 3542 | int ret; |
3ef94daa CW |
3543 | |
3544 | switch (args->madv) { | |
3545 | case I915_MADV_DONTNEED: | |
3546 | case I915_MADV_WILLNEED: | |
3547 | break; | |
3548 | default: | |
3549 | return -EINVAL; | |
3550 | } | |
3551 | ||
1d7cfea1 CW |
3552 | ret = i915_mutex_lock_interruptible(dev); |
3553 | if (ret) | |
3554 | return ret; | |
3555 | ||
05394f39 | 3556 | obj = to_intel_bo(drm_gem_object_lookup(dev, file_priv, args->handle)); |
c8725226 | 3557 | if (&obj->base == NULL) { |
1d7cfea1 CW |
3558 | ret = -ENOENT; |
3559 | goto unlock; | |
3ef94daa | 3560 | } |
3ef94daa | 3561 | |
05394f39 | 3562 | if (obj->pin_count) { |
1d7cfea1 CW |
3563 | ret = -EINVAL; |
3564 | goto out; | |
3ef94daa CW |
3565 | } |
3566 | ||
05394f39 CW |
3567 | if (obj->madv != __I915_MADV_PURGED) |
3568 | obj->madv = args->madv; | |
3ef94daa | 3569 | |
2d7ef395 | 3570 | /* if the object is no longer bound, discard its backing storage */ |
05394f39 CW |
3571 | if (i915_gem_object_is_purgeable(obj) && |
3572 | obj->gtt_space == NULL) | |
2d7ef395 CW |
3573 | i915_gem_object_truncate(obj); |
3574 | ||
05394f39 | 3575 | args->retained = obj->madv != __I915_MADV_PURGED; |
bb6baf76 | 3576 | |
1d7cfea1 | 3577 | out: |
05394f39 | 3578 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 3579 | unlock: |
3ef94daa | 3580 | mutex_unlock(&dev->struct_mutex); |
1d7cfea1 | 3581 | return ret; |
3ef94daa CW |
3582 | } |
3583 | ||
05394f39 CW |
3584 | struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev, |
3585 | size_t size) | |
ac52bc56 | 3586 | { |
73aa808f | 3587 | struct drm_i915_private *dev_priv = dev->dev_private; |
c397b908 | 3588 | struct drm_i915_gem_object *obj; |
5949eac4 | 3589 | struct address_space *mapping; |
ac52bc56 | 3590 | |
c397b908 DV |
3591 | obj = kzalloc(sizeof(*obj), GFP_KERNEL); |
3592 | if (obj == NULL) | |
3593 | return NULL; | |
673a394b | 3594 | |
c397b908 DV |
3595 | if (drm_gem_object_init(dev, &obj->base, size) != 0) { |
3596 | kfree(obj); | |
3597 | return NULL; | |
3598 | } | |
673a394b | 3599 | |
5949eac4 HD |
3600 | mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping; |
3601 | mapping_set_gfp_mask(mapping, GFP_HIGHUSER | __GFP_RECLAIMABLE); | |
3602 | ||
73aa808f CW |
3603 | i915_gem_info_add_obj(dev_priv, size); |
3604 | ||
c397b908 DV |
3605 | obj->base.write_domain = I915_GEM_DOMAIN_CPU; |
3606 | obj->base.read_domains = I915_GEM_DOMAIN_CPU; | |
673a394b | 3607 | |
3d29b842 ED |
3608 | if (HAS_LLC(dev)) { |
3609 | /* On some devices, we can have the GPU use the LLC (the CPU | |
a1871112 EA |
3610 | * cache) for about a 10% performance improvement |
3611 | * compared to uncached. Graphics requests other than | |
3612 | * display scanout are coherent with the CPU in | |
3613 | * accessing this cache. This means in this mode we | |
3614 | * don't need to clflush on the CPU side, and on the | |
3615 | * GPU side we only need to flush internal caches to | |
3616 | * get data visible to the CPU. | |
3617 | * | |
3618 | * However, we maintain the display planes as UC, and so | |
3619 | * need to rebind when first used as such. | |
3620 | */ | |
3621 | obj->cache_level = I915_CACHE_LLC; | |
3622 | } else | |
3623 | obj->cache_level = I915_CACHE_NONE; | |
3624 | ||
62b8b215 | 3625 | obj->base.driver_private = NULL; |
c397b908 | 3626 | obj->fence_reg = I915_FENCE_REG_NONE; |
69dc4987 | 3627 | INIT_LIST_HEAD(&obj->mm_list); |
93a37f20 | 3628 | INIT_LIST_HEAD(&obj->gtt_list); |
69dc4987 | 3629 | INIT_LIST_HEAD(&obj->ring_list); |
432e58ed | 3630 | INIT_LIST_HEAD(&obj->exec_list); |
c397b908 | 3631 | INIT_LIST_HEAD(&obj->gpu_write_list); |
c397b908 | 3632 | obj->madv = I915_MADV_WILLNEED; |
75e9e915 DV |
3633 | /* Avoid an unnecessary call to unbind on the first bind. */ |
3634 | obj->map_and_fenceable = true; | |
de151cf6 | 3635 | |
05394f39 | 3636 | return obj; |
c397b908 DV |
3637 | } |
3638 | ||
3639 | int i915_gem_init_object(struct drm_gem_object *obj) | |
3640 | { | |
3641 | BUG(); | |
de151cf6 | 3642 | |
673a394b EA |
3643 | return 0; |
3644 | } | |
3645 | ||
05394f39 | 3646 | static void i915_gem_free_object_tail(struct drm_i915_gem_object *obj) |
673a394b | 3647 | { |
05394f39 | 3648 | struct drm_device *dev = obj->base.dev; |
be72615b | 3649 | drm_i915_private_t *dev_priv = dev->dev_private; |
be72615b | 3650 | int ret; |
673a394b | 3651 | |
be72615b CW |
3652 | ret = i915_gem_object_unbind(obj); |
3653 | if (ret == -ERESTARTSYS) { | |
05394f39 | 3654 | list_move(&obj->mm_list, |
be72615b CW |
3655 | &dev_priv->mm.deferred_free_list); |
3656 | return; | |
3657 | } | |
673a394b | 3658 | |
26e12f89 CW |
3659 | trace_i915_gem_object_destroy(obj); |
3660 | ||
05394f39 | 3661 | if (obj->base.map_list.map) |
b464e9a2 | 3662 | drm_gem_free_mmap_offset(&obj->base); |
de151cf6 | 3663 | |
05394f39 CW |
3664 | drm_gem_object_release(&obj->base); |
3665 | i915_gem_info_remove_obj(dev_priv, obj->base.size); | |
c397b908 | 3666 | |
05394f39 CW |
3667 | kfree(obj->page_cpu_valid); |
3668 | kfree(obj->bit_17); | |
3669 | kfree(obj); | |
673a394b EA |
3670 | } |
3671 | ||
05394f39 | 3672 | void i915_gem_free_object(struct drm_gem_object *gem_obj) |
be72615b | 3673 | { |
05394f39 CW |
3674 | struct drm_i915_gem_object *obj = to_intel_bo(gem_obj); |
3675 | struct drm_device *dev = obj->base.dev; | |
be72615b | 3676 | |
05394f39 | 3677 | while (obj->pin_count > 0) |
be72615b CW |
3678 | i915_gem_object_unpin(obj); |
3679 | ||
05394f39 | 3680 | if (obj->phys_obj) |
be72615b CW |
3681 | i915_gem_detach_phys_object(dev, obj); |
3682 | ||
3683 | i915_gem_free_object_tail(obj); | |
3684 | } | |
3685 | ||
29105ccc CW |
3686 | int |
3687 | i915_gem_idle(struct drm_device *dev) | |
3688 | { | |
3689 | drm_i915_private_t *dev_priv = dev->dev_private; | |
3690 | int ret; | |
28dfe52a | 3691 | |
29105ccc | 3692 | mutex_lock(&dev->struct_mutex); |
1c5d22f7 | 3693 | |
87acb0a5 | 3694 | if (dev_priv->mm.suspended) { |
29105ccc CW |
3695 | mutex_unlock(&dev->struct_mutex); |
3696 | return 0; | |
28dfe52a EA |
3697 | } |
3698 | ||
b93f9cf1 | 3699 | ret = i915_gpu_idle(dev, true); |
6dbe2772 KP |
3700 | if (ret) { |
3701 | mutex_unlock(&dev->struct_mutex); | |
673a394b | 3702 | return ret; |
6dbe2772 | 3703 | } |
673a394b | 3704 | |
29105ccc CW |
3705 | /* Under UMS, be paranoid and evict. */ |
3706 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) { | |
5eac3ab4 | 3707 | ret = i915_gem_evict_inactive(dev, false); |
29105ccc CW |
3708 | if (ret) { |
3709 | mutex_unlock(&dev->struct_mutex); | |
3710 | return ret; | |
3711 | } | |
3712 | } | |
3713 | ||
312817a3 CW |
3714 | i915_gem_reset_fences(dev); |
3715 | ||
29105ccc CW |
3716 | /* Hack! Don't let anybody do execbuf while we don't control the chip. |
3717 | * We need to replace this with a semaphore, or something. | |
3718 | * And not confound mm.suspended! | |
3719 | */ | |
3720 | dev_priv->mm.suspended = 1; | |
bc0c7f14 | 3721 | del_timer_sync(&dev_priv->hangcheck_timer); |
29105ccc CW |
3722 | |
3723 | i915_kernel_lost_context(dev); | |
6dbe2772 | 3724 | i915_gem_cleanup_ringbuffer(dev); |
29105ccc | 3725 | |
6dbe2772 KP |
3726 | mutex_unlock(&dev->struct_mutex); |
3727 | ||
29105ccc CW |
3728 | /* Cancel the retire work handler, which should be idle now. */ |
3729 | cancel_delayed_work_sync(&dev_priv->mm.retire_work); | |
3730 | ||
673a394b EA |
3731 | return 0; |
3732 | } | |
3733 | ||
f691e2f4 DV |
3734 | void i915_gem_init_swizzling(struct drm_device *dev) |
3735 | { | |
3736 | drm_i915_private_t *dev_priv = dev->dev_private; | |
3737 | ||
11782b02 | 3738 | if (INTEL_INFO(dev)->gen < 5 || |
f691e2f4 DV |
3739 | dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_NONE) |
3740 | return; | |
3741 | ||
3742 | I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) | | |
3743 | DISP_TILE_SURFACE_SWIZZLING); | |
3744 | ||
11782b02 DV |
3745 | if (IS_GEN5(dev)) |
3746 | return; | |
3747 | ||
f691e2f4 DV |
3748 | I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_SWZCTL); |
3749 | if (IS_GEN6(dev)) | |
3750 | I915_WRITE(ARB_MODE, ARB_MODE_ENABLE(ARB_MODE_SWIZZLE_SNB)); | |
3751 | else | |
3752 | I915_WRITE(ARB_MODE, ARB_MODE_ENABLE(ARB_MODE_SWIZZLE_IVB)); | |
3753 | } | |
e21af88d DV |
3754 | |
3755 | void i915_gem_init_ppgtt(struct drm_device *dev) | |
3756 | { | |
3757 | drm_i915_private_t *dev_priv = dev->dev_private; | |
3758 | uint32_t pd_offset; | |
3759 | struct intel_ring_buffer *ring; | |
55a254ac DV |
3760 | struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt; |
3761 | uint32_t __iomem *pd_addr; | |
3762 | uint32_t pd_entry; | |
e21af88d DV |
3763 | int i; |
3764 | ||
3765 | if (!dev_priv->mm.aliasing_ppgtt) | |
3766 | return; | |
3767 | ||
55a254ac DV |
3768 | |
3769 | pd_addr = dev_priv->mm.gtt->gtt + ppgtt->pd_offset/sizeof(uint32_t); | |
3770 | for (i = 0; i < ppgtt->num_pd_entries; i++) { | |
3771 | dma_addr_t pt_addr; | |
3772 | ||
3773 | if (dev_priv->mm.gtt->needs_dmar) | |
3774 | pt_addr = ppgtt->pt_dma_addr[i]; | |
3775 | else | |
3776 | pt_addr = page_to_phys(ppgtt->pt_pages[i]); | |
3777 | ||
3778 | pd_entry = GEN6_PDE_ADDR_ENCODE(pt_addr); | |
3779 | pd_entry |= GEN6_PDE_VALID; | |
3780 | ||
3781 | writel(pd_entry, pd_addr + i); | |
3782 | } | |
3783 | readl(pd_addr); | |
3784 | ||
3785 | pd_offset = ppgtt->pd_offset; | |
e21af88d DV |
3786 | pd_offset /= 64; /* in cachelines, */ |
3787 | pd_offset <<= 16; | |
3788 | ||
3789 | if (INTEL_INFO(dev)->gen == 6) { | |
3790 | uint32_t ecochk = I915_READ(GAM_ECOCHK); | |
3791 | I915_WRITE(GAM_ECOCHK, ecochk | ECOCHK_SNB_BIT | | |
3792 | ECOCHK_PPGTT_CACHE64B); | |
3793 | I915_WRITE(GFX_MODE, GFX_MODE_ENABLE(GFX_PPGTT_ENABLE)); | |
3794 | } else if (INTEL_INFO(dev)->gen >= 7) { | |
3795 | I915_WRITE(GAM_ECOCHK, ECOCHK_PPGTT_CACHE64B); | |
3796 | /* GFX_MODE is per-ring on gen7+ */ | |
3797 | } | |
3798 | ||
3799 | for (i = 0; i < I915_NUM_RINGS; i++) { | |
3800 | ring = &dev_priv->ring[i]; | |
3801 | ||
3802 | if (INTEL_INFO(dev)->gen >= 7) | |
3803 | I915_WRITE(RING_MODE_GEN7(ring), | |
3804 | GFX_MODE_ENABLE(GFX_PPGTT_ENABLE)); | |
3805 | ||
3806 | I915_WRITE(RING_PP_DIR_DCLV(ring), PP_DIR_DCLV_2G); | |
3807 | I915_WRITE(RING_PP_DIR_BASE(ring), pd_offset); | |
3808 | } | |
3809 | } | |
3810 | ||
8187a2b7 | 3811 | int |
f691e2f4 | 3812 | i915_gem_init_hw(struct drm_device *dev) |
8187a2b7 ZN |
3813 | { |
3814 | drm_i915_private_t *dev_priv = dev->dev_private; | |
3815 | int ret; | |
68f95ba9 | 3816 | |
f691e2f4 DV |
3817 | i915_gem_init_swizzling(dev); |
3818 | ||
5c1143bb | 3819 | ret = intel_init_render_ring_buffer(dev); |
68f95ba9 | 3820 | if (ret) |
b6913e4b | 3821 | return ret; |
68f95ba9 CW |
3822 | |
3823 | if (HAS_BSD(dev)) { | |
5c1143bb | 3824 | ret = intel_init_bsd_ring_buffer(dev); |
68f95ba9 CW |
3825 | if (ret) |
3826 | goto cleanup_render_ring; | |
d1b851fc | 3827 | } |
68f95ba9 | 3828 | |
549f7365 CW |
3829 | if (HAS_BLT(dev)) { |
3830 | ret = intel_init_blt_ring_buffer(dev); | |
3831 | if (ret) | |
3832 | goto cleanup_bsd_ring; | |
3833 | } | |
3834 | ||
6f392d54 CW |
3835 | dev_priv->next_seqno = 1; |
3836 | ||
e21af88d DV |
3837 | i915_gem_init_ppgtt(dev); |
3838 | ||
68f95ba9 CW |
3839 | return 0; |
3840 | ||
549f7365 | 3841 | cleanup_bsd_ring: |
1ec14ad3 | 3842 | intel_cleanup_ring_buffer(&dev_priv->ring[VCS]); |
68f95ba9 | 3843 | cleanup_render_ring: |
1ec14ad3 | 3844 | intel_cleanup_ring_buffer(&dev_priv->ring[RCS]); |
8187a2b7 ZN |
3845 | return ret; |
3846 | } | |
3847 | ||
3848 | void | |
3849 | i915_gem_cleanup_ringbuffer(struct drm_device *dev) | |
3850 | { | |
3851 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1ec14ad3 | 3852 | int i; |
8187a2b7 | 3853 | |
1ec14ad3 CW |
3854 | for (i = 0; i < I915_NUM_RINGS; i++) |
3855 | intel_cleanup_ring_buffer(&dev_priv->ring[i]); | |
8187a2b7 ZN |
3856 | } |
3857 | ||
673a394b EA |
3858 | int |
3859 | i915_gem_entervt_ioctl(struct drm_device *dev, void *data, | |
3860 | struct drm_file *file_priv) | |
3861 | { | |
3862 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1ec14ad3 | 3863 | int ret, i; |
673a394b | 3864 | |
79e53945 JB |
3865 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
3866 | return 0; | |
3867 | ||
ba1234d1 | 3868 | if (atomic_read(&dev_priv->mm.wedged)) { |
673a394b | 3869 | DRM_ERROR("Reenabling wedged hardware, good luck\n"); |
ba1234d1 | 3870 | atomic_set(&dev_priv->mm.wedged, 0); |
673a394b EA |
3871 | } |
3872 | ||
673a394b | 3873 | mutex_lock(&dev->struct_mutex); |
9bb2d6f9 EA |
3874 | dev_priv->mm.suspended = 0; |
3875 | ||
f691e2f4 | 3876 | ret = i915_gem_init_hw(dev); |
d816f6ac WF |
3877 | if (ret != 0) { |
3878 | mutex_unlock(&dev->struct_mutex); | |
9bb2d6f9 | 3879 | return ret; |
d816f6ac | 3880 | } |
9bb2d6f9 | 3881 | |
69dc4987 | 3882 | BUG_ON(!list_empty(&dev_priv->mm.active_list)); |
673a394b EA |
3883 | BUG_ON(!list_empty(&dev_priv->mm.flushing_list)); |
3884 | BUG_ON(!list_empty(&dev_priv->mm.inactive_list)); | |
1ec14ad3 CW |
3885 | for (i = 0; i < I915_NUM_RINGS; i++) { |
3886 | BUG_ON(!list_empty(&dev_priv->ring[i].active_list)); | |
3887 | BUG_ON(!list_empty(&dev_priv->ring[i].request_list)); | |
3888 | } | |
673a394b | 3889 | mutex_unlock(&dev->struct_mutex); |
dbb19d30 | 3890 | |
5f35308b CW |
3891 | ret = drm_irq_install(dev); |
3892 | if (ret) | |
3893 | goto cleanup_ringbuffer; | |
dbb19d30 | 3894 | |
673a394b | 3895 | return 0; |
5f35308b CW |
3896 | |
3897 | cleanup_ringbuffer: | |
3898 | mutex_lock(&dev->struct_mutex); | |
3899 | i915_gem_cleanup_ringbuffer(dev); | |
3900 | dev_priv->mm.suspended = 1; | |
3901 | mutex_unlock(&dev->struct_mutex); | |
3902 | ||
3903 | return ret; | |
673a394b EA |
3904 | } |
3905 | ||
3906 | int | |
3907 | i915_gem_leavevt_ioctl(struct drm_device *dev, void *data, | |
3908 | struct drm_file *file_priv) | |
3909 | { | |
79e53945 JB |
3910 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
3911 | return 0; | |
3912 | ||
dbb19d30 | 3913 | drm_irq_uninstall(dev); |
e6890f6f | 3914 | return i915_gem_idle(dev); |
673a394b EA |
3915 | } |
3916 | ||
3917 | void | |
3918 | i915_gem_lastclose(struct drm_device *dev) | |
3919 | { | |
3920 | int ret; | |
673a394b | 3921 | |
e806b495 EA |
3922 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
3923 | return; | |
3924 | ||
6dbe2772 KP |
3925 | ret = i915_gem_idle(dev); |
3926 | if (ret) | |
3927 | DRM_ERROR("failed to idle hardware: %d\n", ret); | |
673a394b EA |
3928 | } |
3929 | ||
64193406 CW |
3930 | static void |
3931 | init_ring_lists(struct intel_ring_buffer *ring) | |
3932 | { | |
3933 | INIT_LIST_HEAD(&ring->active_list); | |
3934 | INIT_LIST_HEAD(&ring->request_list); | |
3935 | INIT_LIST_HEAD(&ring->gpu_write_list); | |
3936 | } | |
3937 | ||
673a394b EA |
3938 | void |
3939 | i915_gem_load(struct drm_device *dev) | |
3940 | { | |
b5aa8a0f | 3941 | int i; |
673a394b EA |
3942 | drm_i915_private_t *dev_priv = dev->dev_private; |
3943 | ||
69dc4987 | 3944 | INIT_LIST_HEAD(&dev_priv->mm.active_list); |
673a394b EA |
3945 | INIT_LIST_HEAD(&dev_priv->mm.flushing_list); |
3946 | INIT_LIST_HEAD(&dev_priv->mm.inactive_list); | |
f13d3f73 | 3947 | INIT_LIST_HEAD(&dev_priv->mm.pinned_list); |
a09ba7fa | 3948 | INIT_LIST_HEAD(&dev_priv->mm.fence_list); |
be72615b | 3949 | INIT_LIST_HEAD(&dev_priv->mm.deferred_free_list); |
93a37f20 | 3950 | INIT_LIST_HEAD(&dev_priv->mm.gtt_list); |
1ec14ad3 CW |
3951 | for (i = 0; i < I915_NUM_RINGS; i++) |
3952 | init_ring_lists(&dev_priv->ring[i]); | |
4b9de737 | 3953 | for (i = 0; i < I915_MAX_NUM_FENCES; i++) |
007cc8ac | 3954 | INIT_LIST_HEAD(&dev_priv->fence_regs[i].lru_list); |
673a394b EA |
3955 | INIT_DELAYED_WORK(&dev_priv->mm.retire_work, |
3956 | i915_gem_retire_work_handler); | |
30dbf0c0 | 3957 | init_completion(&dev_priv->error_completion); |
31169714 | 3958 | |
94400120 DA |
3959 | /* On GEN3 we really need to make sure the ARB C3 LP bit is set */ |
3960 | if (IS_GEN3(dev)) { | |
3961 | u32 tmp = I915_READ(MI_ARB_STATE); | |
3962 | if (!(tmp & MI_ARB_C3_LP_WRITE_ENABLE)) { | |
3963 | /* arb state is a masked write, so set bit + bit in mask */ | |
3964 | tmp = MI_ARB_C3_LP_WRITE_ENABLE | (MI_ARB_C3_LP_WRITE_ENABLE << MI_ARB_MASK_SHIFT); | |
3965 | I915_WRITE(MI_ARB_STATE, tmp); | |
3966 | } | |
3967 | } | |
3968 | ||
72bfa19c CW |
3969 | dev_priv->relative_constants_mode = I915_EXEC_CONSTANTS_REL_GENERAL; |
3970 | ||
de151cf6 | 3971 | /* Old X drivers will take 0-2 for front, back, depth buffers */ |
b397c836 EA |
3972 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) |
3973 | dev_priv->fence_reg_start = 3; | |
de151cf6 | 3974 | |
a6c45cf0 | 3975 | if (INTEL_INFO(dev)->gen >= 4 || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) |
de151cf6 JB |
3976 | dev_priv->num_fence_regs = 16; |
3977 | else | |
3978 | dev_priv->num_fence_regs = 8; | |
3979 | ||
b5aa8a0f | 3980 | /* Initialize fence registers to zero */ |
10ed13e4 EA |
3981 | for (i = 0; i < dev_priv->num_fence_regs; i++) { |
3982 | i915_gem_clear_fence_reg(dev, &dev_priv->fence_regs[i]); | |
b5aa8a0f | 3983 | } |
10ed13e4 | 3984 | |
673a394b | 3985 | i915_gem_detect_bit_6_swizzle(dev); |
6b95a207 | 3986 | init_waitqueue_head(&dev_priv->pending_flip_queue); |
17250b71 | 3987 | |
ce453d81 CW |
3988 | dev_priv->mm.interruptible = true; |
3989 | ||
17250b71 CW |
3990 | dev_priv->mm.inactive_shrinker.shrink = i915_gem_inactive_shrink; |
3991 | dev_priv->mm.inactive_shrinker.seeks = DEFAULT_SEEKS; | |
3992 | register_shrinker(&dev_priv->mm.inactive_shrinker); | |
673a394b | 3993 | } |
71acb5eb DA |
3994 | |
3995 | /* | |
3996 | * Create a physically contiguous memory object for this object | |
3997 | * e.g. for cursor + overlay regs | |
3998 | */ | |
995b6762 CW |
3999 | static int i915_gem_init_phys_object(struct drm_device *dev, |
4000 | int id, int size, int align) | |
71acb5eb DA |
4001 | { |
4002 | drm_i915_private_t *dev_priv = dev->dev_private; | |
4003 | struct drm_i915_gem_phys_object *phys_obj; | |
4004 | int ret; | |
4005 | ||
4006 | if (dev_priv->mm.phys_objs[id - 1] || !size) | |
4007 | return 0; | |
4008 | ||
9a298b2a | 4009 | phys_obj = kzalloc(sizeof(struct drm_i915_gem_phys_object), GFP_KERNEL); |
71acb5eb DA |
4010 | if (!phys_obj) |
4011 | return -ENOMEM; | |
4012 | ||
4013 | phys_obj->id = id; | |
4014 | ||
6eeefaf3 | 4015 | phys_obj->handle = drm_pci_alloc(dev, size, align); |
71acb5eb DA |
4016 | if (!phys_obj->handle) { |
4017 | ret = -ENOMEM; | |
4018 | goto kfree_obj; | |
4019 | } | |
4020 | #ifdef CONFIG_X86 | |
4021 | set_memory_wc((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE); | |
4022 | #endif | |
4023 | ||
4024 | dev_priv->mm.phys_objs[id - 1] = phys_obj; | |
4025 | ||
4026 | return 0; | |
4027 | kfree_obj: | |
9a298b2a | 4028 | kfree(phys_obj); |
71acb5eb DA |
4029 | return ret; |
4030 | } | |
4031 | ||
995b6762 | 4032 | static void i915_gem_free_phys_object(struct drm_device *dev, int id) |
71acb5eb DA |
4033 | { |
4034 | drm_i915_private_t *dev_priv = dev->dev_private; | |
4035 | struct drm_i915_gem_phys_object *phys_obj; | |
4036 | ||
4037 | if (!dev_priv->mm.phys_objs[id - 1]) | |
4038 | return; | |
4039 | ||
4040 | phys_obj = dev_priv->mm.phys_objs[id - 1]; | |
4041 | if (phys_obj->cur_obj) { | |
4042 | i915_gem_detach_phys_object(dev, phys_obj->cur_obj); | |
4043 | } | |
4044 | ||
4045 | #ifdef CONFIG_X86 | |
4046 | set_memory_wb((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE); | |
4047 | #endif | |
4048 | drm_pci_free(dev, phys_obj->handle); | |
4049 | kfree(phys_obj); | |
4050 | dev_priv->mm.phys_objs[id - 1] = NULL; | |
4051 | } | |
4052 | ||
4053 | void i915_gem_free_all_phys_object(struct drm_device *dev) | |
4054 | { | |
4055 | int i; | |
4056 | ||
260883c8 | 4057 | for (i = I915_GEM_PHYS_CURSOR_0; i <= I915_MAX_PHYS_OBJECT; i++) |
71acb5eb DA |
4058 | i915_gem_free_phys_object(dev, i); |
4059 | } | |
4060 | ||
4061 | void i915_gem_detach_phys_object(struct drm_device *dev, | |
05394f39 | 4062 | struct drm_i915_gem_object *obj) |
71acb5eb | 4063 | { |
05394f39 | 4064 | struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping; |
e5281ccd | 4065 | char *vaddr; |
71acb5eb | 4066 | int i; |
71acb5eb DA |
4067 | int page_count; |
4068 | ||
05394f39 | 4069 | if (!obj->phys_obj) |
71acb5eb | 4070 | return; |
05394f39 | 4071 | vaddr = obj->phys_obj->handle->vaddr; |
71acb5eb | 4072 | |
05394f39 | 4073 | page_count = obj->base.size / PAGE_SIZE; |
71acb5eb | 4074 | for (i = 0; i < page_count; i++) { |
5949eac4 | 4075 | struct page *page = shmem_read_mapping_page(mapping, i); |
e5281ccd CW |
4076 | if (!IS_ERR(page)) { |
4077 | char *dst = kmap_atomic(page); | |
4078 | memcpy(dst, vaddr + i*PAGE_SIZE, PAGE_SIZE); | |
4079 | kunmap_atomic(dst); | |
4080 | ||
4081 | drm_clflush_pages(&page, 1); | |
4082 | ||
4083 | set_page_dirty(page); | |
4084 | mark_page_accessed(page); | |
4085 | page_cache_release(page); | |
4086 | } | |
71acb5eb | 4087 | } |
40ce6575 | 4088 | intel_gtt_chipset_flush(); |
d78b47b9 | 4089 | |
05394f39 CW |
4090 | obj->phys_obj->cur_obj = NULL; |
4091 | obj->phys_obj = NULL; | |
71acb5eb DA |
4092 | } |
4093 | ||
4094 | int | |
4095 | i915_gem_attach_phys_object(struct drm_device *dev, | |
05394f39 | 4096 | struct drm_i915_gem_object *obj, |
6eeefaf3 CW |
4097 | int id, |
4098 | int align) | |
71acb5eb | 4099 | { |
05394f39 | 4100 | struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping; |
71acb5eb | 4101 | drm_i915_private_t *dev_priv = dev->dev_private; |
71acb5eb DA |
4102 | int ret = 0; |
4103 | int page_count; | |
4104 | int i; | |
4105 | ||
4106 | if (id > I915_MAX_PHYS_OBJECT) | |
4107 | return -EINVAL; | |
4108 | ||
05394f39 CW |
4109 | if (obj->phys_obj) { |
4110 | if (obj->phys_obj->id == id) | |
71acb5eb DA |
4111 | return 0; |
4112 | i915_gem_detach_phys_object(dev, obj); | |
4113 | } | |
4114 | ||
71acb5eb DA |
4115 | /* create a new object */ |
4116 | if (!dev_priv->mm.phys_objs[id - 1]) { | |
4117 | ret = i915_gem_init_phys_object(dev, id, | |
05394f39 | 4118 | obj->base.size, align); |
71acb5eb | 4119 | if (ret) { |
05394f39 CW |
4120 | DRM_ERROR("failed to init phys object %d size: %zu\n", |
4121 | id, obj->base.size); | |
e5281ccd | 4122 | return ret; |
71acb5eb DA |
4123 | } |
4124 | } | |
4125 | ||
4126 | /* bind to the object */ | |
05394f39 CW |
4127 | obj->phys_obj = dev_priv->mm.phys_objs[id - 1]; |
4128 | obj->phys_obj->cur_obj = obj; | |
71acb5eb | 4129 | |
05394f39 | 4130 | page_count = obj->base.size / PAGE_SIZE; |
71acb5eb DA |
4131 | |
4132 | for (i = 0; i < page_count; i++) { | |
e5281ccd CW |
4133 | struct page *page; |
4134 | char *dst, *src; | |
4135 | ||
5949eac4 | 4136 | page = shmem_read_mapping_page(mapping, i); |
e5281ccd CW |
4137 | if (IS_ERR(page)) |
4138 | return PTR_ERR(page); | |
71acb5eb | 4139 | |
ff75b9bc | 4140 | src = kmap_atomic(page); |
05394f39 | 4141 | dst = obj->phys_obj->handle->vaddr + (i * PAGE_SIZE); |
71acb5eb | 4142 | memcpy(dst, src, PAGE_SIZE); |
3e4d3af5 | 4143 | kunmap_atomic(src); |
71acb5eb | 4144 | |
e5281ccd CW |
4145 | mark_page_accessed(page); |
4146 | page_cache_release(page); | |
4147 | } | |
d78b47b9 | 4148 | |
71acb5eb | 4149 | return 0; |
71acb5eb DA |
4150 | } |
4151 | ||
4152 | static int | |
05394f39 CW |
4153 | i915_gem_phys_pwrite(struct drm_device *dev, |
4154 | struct drm_i915_gem_object *obj, | |
71acb5eb DA |
4155 | struct drm_i915_gem_pwrite *args, |
4156 | struct drm_file *file_priv) | |
4157 | { | |
05394f39 | 4158 | void *vaddr = obj->phys_obj->handle->vaddr + args->offset; |
b47b30cc | 4159 | char __user *user_data = (char __user *) (uintptr_t) args->data_ptr; |
71acb5eb | 4160 | |
b47b30cc CW |
4161 | if (__copy_from_user_inatomic_nocache(vaddr, user_data, args->size)) { |
4162 | unsigned long unwritten; | |
4163 | ||
4164 | /* The physical object once assigned is fixed for the lifetime | |
4165 | * of the obj, so we can safely drop the lock and continue | |
4166 | * to access vaddr. | |
4167 | */ | |
4168 | mutex_unlock(&dev->struct_mutex); | |
4169 | unwritten = copy_from_user(vaddr, user_data, args->size); | |
4170 | mutex_lock(&dev->struct_mutex); | |
4171 | if (unwritten) | |
4172 | return -EFAULT; | |
4173 | } | |
71acb5eb | 4174 | |
40ce6575 | 4175 | intel_gtt_chipset_flush(); |
71acb5eb DA |
4176 | return 0; |
4177 | } | |
b962442e | 4178 | |
f787a5f5 | 4179 | void i915_gem_release(struct drm_device *dev, struct drm_file *file) |
b962442e | 4180 | { |
f787a5f5 | 4181 | struct drm_i915_file_private *file_priv = file->driver_priv; |
b962442e EA |
4182 | |
4183 | /* Clean up our request list when the client is going away, so that | |
4184 | * later retire_requests won't dereference our soon-to-be-gone | |
4185 | * file_priv. | |
4186 | */ | |
1c25595f | 4187 | spin_lock(&file_priv->mm.lock); |
f787a5f5 CW |
4188 | while (!list_empty(&file_priv->mm.request_list)) { |
4189 | struct drm_i915_gem_request *request; | |
4190 | ||
4191 | request = list_first_entry(&file_priv->mm.request_list, | |
4192 | struct drm_i915_gem_request, | |
4193 | client_list); | |
4194 | list_del(&request->client_list); | |
4195 | request->file_priv = NULL; | |
4196 | } | |
1c25595f | 4197 | spin_unlock(&file_priv->mm.lock); |
b962442e | 4198 | } |
31169714 | 4199 | |
1637ef41 CW |
4200 | static int |
4201 | i915_gpu_is_active(struct drm_device *dev) | |
4202 | { | |
4203 | drm_i915_private_t *dev_priv = dev->dev_private; | |
4204 | int lists_empty; | |
4205 | ||
1637ef41 | 4206 | lists_empty = list_empty(&dev_priv->mm.flushing_list) && |
17250b71 | 4207 | list_empty(&dev_priv->mm.active_list); |
1637ef41 CW |
4208 | |
4209 | return !lists_empty; | |
4210 | } | |
4211 | ||
31169714 | 4212 | static int |
1495f230 | 4213 | i915_gem_inactive_shrink(struct shrinker *shrinker, struct shrink_control *sc) |
31169714 | 4214 | { |
17250b71 CW |
4215 | struct drm_i915_private *dev_priv = |
4216 | container_of(shrinker, | |
4217 | struct drm_i915_private, | |
4218 | mm.inactive_shrinker); | |
4219 | struct drm_device *dev = dev_priv->dev; | |
4220 | struct drm_i915_gem_object *obj, *next; | |
1495f230 | 4221 | int nr_to_scan = sc->nr_to_scan; |
17250b71 CW |
4222 | int cnt; |
4223 | ||
4224 | if (!mutex_trylock(&dev->struct_mutex)) | |
bbe2e11a | 4225 | return 0; |
31169714 CW |
4226 | |
4227 | /* "fast-path" to count number of available objects */ | |
4228 | if (nr_to_scan == 0) { | |
17250b71 CW |
4229 | cnt = 0; |
4230 | list_for_each_entry(obj, | |
4231 | &dev_priv->mm.inactive_list, | |
4232 | mm_list) | |
4233 | cnt++; | |
4234 | mutex_unlock(&dev->struct_mutex); | |
4235 | return cnt / 100 * sysctl_vfs_cache_pressure; | |
31169714 CW |
4236 | } |
4237 | ||
1637ef41 | 4238 | rescan: |
31169714 | 4239 | /* first scan for clean buffers */ |
17250b71 | 4240 | i915_gem_retire_requests(dev); |
31169714 | 4241 | |
17250b71 CW |
4242 | list_for_each_entry_safe(obj, next, |
4243 | &dev_priv->mm.inactive_list, | |
4244 | mm_list) { | |
4245 | if (i915_gem_object_is_purgeable(obj)) { | |
2021746e CW |
4246 | if (i915_gem_object_unbind(obj) == 0 && |
4247 | --nr_to_scan == 0) | |
17250b71 | 4248 | break; |
31169714 | 4249 | } |
31169714 CW |
4250 | } |
4251 | ||
4252 | /* second pass, evict/count anything still on the inactive list */ | |
17250b71 CW |
4253 | cnt = 0; |
4254 | list_for_each_entry_safe(obj, next, | |
4255 | &dev_priv->mm.inactive_list, | |
4256 | mm_list) { | |
2021746e CW |
4257 | if (nr_to_scan && |
4258 | i915_gem_object_unbind(obj) == 0) | |
17250b71 | 4259 | nr_to_scan--; |
2021746e | 4260 | else |
17250b71 CW |
4261 | cnt++; |
4262 | } | |
4263 | ||
4264 | if (nr_to_scan && i915_gpu_is_active(dev)) { | |
1637ef41 CW |
4265 | /* |
4266 | * We are desperate for pages, so as a last resort, wait | |
4267 | * for the GPU to finish and discard whatever we can. | |
4268 | * This has a dramatic impact to reduce the number of | |
4269 | * OOM-killer events whilst running the GPU aggressively. | |
4270 | */ | |
b93f9cf1 | 4271 | if (i915_gpu_idle(dev, true) == 0) |
1637ef41 CW |
4272 | goto rescan; |
4273 | } | |
17250b71 CW |
4274 | mutex_unlock(&dev->struct_mutex); |
4275 | return cnt / 100 * sysctl_vfs_cache_pressure; | |
31169714 | 4276 | } |