Commit | Line | Data |
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673a394b | 1 | /* |
be6a0376 | 2 | * Copyright © 2008-2015 Intel Corporation |
673a394b EA |
3 | * |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | * | |
26 | */ | |
27 | ||
760285e7 | 28 | #include <drm/drmP.h> |
0de23977 | 29 | #include <drm/drm_vma_manager.h> |
760285e7 | 30 | #include <drm/i915_drm.h> |
673a394b | 31 | #include "i915_drv.h" |
eb82289a | 32 | #include "i915_vgpu.h" |
1c5d22f7 | 33 | #include "i915_trace.h" |
652c393a | 34 | #include "intel_drv.h" |
5949eac4 | 35 | #include <linux/shmem_fs.h> |
5a0e3ad6 | 36 | #include <linux/slab.h> |
673a394b | 37 | #include <linux/swap.h> |
79e53945 | 38 | #include <linux/pci.h> |
1286ff73 | 39 | #include <linux/dma-buf.h> |
673a394b | 40 | |
05394f39 | 41 | static void i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj); |
e62b59e4 | 42 | static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj); |
c8725f3d | 43 | static void |
b4716185 CW |
44 | i915_gem_object_retire__write(struct drm_i915_gem_object *obj); |
45 | static void | |
46 | i915_gem_object_retire__read(struct drm_i915_gem_object *obj, int ring); | |
61050808 | 47 | |
c76ce038 CW |
48 | static bool cpu_cache_is_coherent(struct drm_device *dev, |
49 | enum i915_cache_level level) | |
50 | { | |
51 | return HAS_LLC(dev) || level != I915_CACHE_NONE; | |
52 | } | |
53 | ||
2c22569b CW |
54 | static bool cpu_write_needs_clflush(struct drm_i915_gem_object *obj) |
55 | { | |
56 | if (!cpu_cache_is_coherent(obj->base.dev, obj->cache_level)) | |
57 | return true; | |
58 | ||
59 | return obj->pin_display; | |
60 | } | |
61 | ||
73aa808f CW |
62 | /* some bookkeeping */ |
63 | static void i915_gem_info_add_obj(struct drm_i915_private *dev_priv, | |
64 | size_t size) | |
65 | { | |
c20e8355 | 66 | spin_lock(&dev_priv->mm.object_stat_lock); |
73aa808f CW |
67 | dev_priv->mm.object_count++; |
68 | dev_priv->mm.object_memory += size; | |
c20e8355 | 69 | spin_unlock(&dev_priv->mm.object_stat_lock); |
73aa808f CW |
70 | } |
71 | ||
72 | static void i915_gem_info_remove_obj(struct drm_i915_private *dev_priv, | |
73 | size_t size) | |
74 | { | |
c20e8355 | 75 | spin_lock(&dev_priv->mm.object_stat_lock); |
73aa808f CW |
76 | dev_priv->mm.object_count--; |
77 | dev_priv->mm.object_memory -= size; | |
c20e8355 | 78 | spin_unlock(&dev_priv->mm.object_stat_lock); |
73aa808f CW |
79 | } |
80 | ||
21dd3734 | 81 | static int |
33196ded | 82 | i915_gem_wait_for_error(struct i915_gpu_error *error) |
30dbf0c0 | 83 | { |
30dbf0c0 CW |
84 | int ret; |
85 | ||
d98c52cf | 86 | if (!i915_reset_in_progress(error)) |
30dbf0c0 CW |
87 | return 0; |
88 | ||
0a6759c6 DV |
89 | /* |
90 | * Only wait 10 seconds for the gpu reset to complete to avoid hanging | |
91 | * userspace. If it takes that long something really bad is going on and | |
92 | * we should simply try to bail out and fail as gracefully as possible. | |
93 | */ | |
1f83fee0 | 94 | ret = wait_event_interruptible_timeout(error->reset_queue, |
d98c52cf | 95 | !i915_reset_in_progress(error), |
1f83fee0 | 96 | 10*HZ); |
0a6759c6 DV |
97 | if (ret == 0) { |
98 | DRM_ERROR("Timed out waiting for the gpu reset to complete\n"); | |
99 | return -EIO; | |
100 | } else if (ret < 0) { | |
30dbf0c0 | 101 | return ret; |
d98c52cf CW |
102 | } else { |
103 | return 0; | |
0a6759c6 | 104 | } |
30dbf0c0 CW |
105 | } |
106 | ||
54cf91dc | 107 | int i915_mutex_lock_interruptible(struct drm_device *dev) |
76c1dec1 | 108 | { |
33196ded | 109 | struct drm_i915_private *dev_priv = dev->dev_private; |
76c1dec1 CW |
110 | int ret; |
111 | ||
33196ded | 112 | ret = i915_gem_wait_for_error(&dev_priv->gpu_error); |
76c1dec1 CW |
113 | if (ret) |
114 | return ret; | |
115 | ||
116 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
117 | if (ret) | |
118 | return ret; | |
119 | ||
23bc5982 | 120 | WARN_ON(i915_verify_lists(dev)); |
76c1dec1 CW |
121 | return 0; |
122 | } | |
30dbf0c0 | 123 | |
5a125c3c EA |
124 | int |
125 | i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 126 | struct drm_file *file) |
5a125c3c | 127 | { |
72e96d64 | 128 | struct drm_i915_private *dev_priv = to_i915(dev); |
62106b4f | 129 | struct i915_ggtt *ggtt = &dev_priv->ggtt; |
72e96d64 | 130 | struct drm_i915_gem_get_aperture *args = data; |
ca1543be | 131 | struct i915_vma *vma; |
6299f992 | 132 | size_t pinned; |
5a125c3c | 133 | |
6299f992 | 134 | pinned = 0; |
73aa808f | 135 | mutex_lock(&dev->struct_mutex); |
1c7f4bca | 136 | list_for_each_entry(vma, &ggtt->base.active_list, vm_link) |
ca1543be TU |
137 | if (vma->pin_count) |
138 | pinned += vma->node.size; | |
1c7f4bca | 139 | list_for_each_entry(vma, &ggtt->base.inactive_list, vm_link) |
ca1543be TU |
140 | if (vma->pin_count) |
141 | pinned += vma->node.size; | |
73aa808f | 142 | mutex_unlock(&dev->struct_mutex); |
5a125c3c | 143 | |
72e96d64 | 144 | args->aper_size = ggtt->base.total; |
0206e353 | 145 | args->aper_available_size = args->aper_size - pinned; |
6299f992 | 146 | |
5a125c3c EA |
147 | return 0; |
148 | } | |
149 | ||
6a2c4232 CW |
150 | static int |
151 | i915_gem_object_get_pages_phys(struct drm_i915_gem_object *obj) | |
00731155 | 152 | { |
6a2c4232 CW |
153 | struct address_space *mapping = file_inode(obj->base.filp)->i_mapping; |
154 | char *vaddr = obj->phys_handle->vaddr; | |
155 | struct sg_table *st; | |
156 | struct scatterlist *sg; | |
157 | int i; | |
00731155 | 158 | |
6a2c4232 CW |
159 | if (WARN_ON(i915_gem_object_needs_bit17_swizzle(obj))) |
160 | return -EINVAL; | |
161 | ||
162 | for (i = 0; i < obj->base.size / PAGE_SIZE; i++) { | |
163 | struct page *page; | |
164 | char *src; | |
165 | ||
166 | page = shmem_read_mapping_page(mapping, i); | |
167 | if (IS_ERR(page)) | |
168 | return PTR_ERR(page); | |
169 | ||
170 | src = kmap_atomic(page); | |
171 | memcpy(vaddr, src, PAGE_SIZE); | |
172 | drm_clflush_virt_range(vaddr, PAGE_SIZE); | |
173 | kunmap_atomic(src); | |
174 | ||
09cbfeaf | 175 | put_page(page); |
6a2c4232 CW |
176 | vaddr += PAGE_SIZE; |
177 | } | |
178 | ||
179 | i915_gem_chipset_flush(obj->base.dev); | |
180 | ||
181 | st = kmalloc(sizeof(*st), GFP_KERNEL); | |
182 | if (st == NULL) | |
183 | return -ENOMEM; | |
184 | ||
185 | if (sg_alloc_table(st, 1, GFP_KERNEL)) { | |
186 | kfree(st); | |
187 | return -ENOMEM; | |
188 | } | |
189 | ||
190 | sg = st->sgl; | |
191 | sg->offset = 0; | |
192 | sg->length = obj->base.size; | |
00731155 | 193 | |
6a2c4232 CW |
194 | sg_dma_address(sg) = obj->phys_handle->busaddr; |
195 | sg_dma_len(sg) = obj->base.size; | |
196 | ||
197 | obj->pages = st; | |
6a2c4232 CW |
198 | return 0; |
199 | } | |
200 | ||
201 | static void | |
202 | i915_gem_object_put_pages_phys(struct drm_i915_gem_object *obj) | |
203 | { | |
204 | int ret; | |
205 | ||
206 | BUG_ON(obj->madv == __I915_MADV_PURGED); | |
00731155 | 207 | |
6a2c4232 | 208 | ret = i915_gem_object_set_to_cpu_domain(obj, true); |
f4457ae7 | 209 | if (WARN_ON(ret)) { |
6a2c4232 CW |
210 | /* In the event of a disaster, abandon all caches and |
211 | * hope for the best. | |
212 | */ | |
6a2c4232 CW |
213 | obj->base.read_domains = obj->base.write_domain = I915_GEM_DOMAIN_CPU; |
214 | } | |
215 | ||
216 | if (obj->madv == I915_MADV_DONTNEED) | |
217 | obj->dirty = 0; | |
218 | ||
219 | if (obj->dirty) { | |
00731155 | 220 | struct address_space *mapping = file_inode(obj->base.filp)->i_mapping; |
6a2c4232 | 221 | char *vaddr = obj->phys_handle->vaddr; |
00731155 CW |
222 | int i; |
223 | ||
224 | for (i = 0; i < obj->base.size / PAGE_SIZE; i++) { | |
6a2c4232 CW |
225 | struct page *page; |
226 | char *dst; | |
227 | ||
228 | page = shmem_read_mapping_page(mapping, i); | |
229 | if (IS_ERR(page)) | |
230 | continue; | |
231 | ||
232 | dst = kmap_atomic(page); | |
233 | drm_clflush_virt_range(vaddr, PAGE_SIZE); | |
234 | memcpy(dst, vaddr, PAGE_SIZE); | |
235 | kunmap_atomic(dst); | |
236 | ||
237 | set_page_dirty(page); | |
238 | if (obj->madv == I915_MADV_WILLNEED) | |
00731155 | 239 | mark_page_accessed(page); |
09cbfeaf | 240 | put_page(page); |
00731155 CW |
241 | vaddr += PAGE_SIZE; |
242 | } | |
6a2c4232 | 243 | obj->dirty = 0; |
00731155 CW |
244 | } |
245 | ||
6a2c4232 CW |
246 | sg_free_table(obj->pages); |
247 | kfree(obj->pages); | |
6a2c4232 CW |
248 | } |
249 | ||
250 | static void | |
251 | i915_gem_object_release_phys(struct drm_i915_gem_object *obj) | |
252 | { | |
253 | drm_pci_free(obj->base.dev, obj->phys_handle); | |
254 | } | |
255 | ||
256 | static const struct drm_i915_gem_object_ops i915_gem_phys_ops = { | |
257 | .get_pages = i915_gem_object_get_pages_phys, | |
258 | .put_pages = i915_gem_object_put_pages_phys, | |
259 | .release = i915_gem_object_release_phys, | |
260 | }; | |
261 | ||
262 | static int | |
263 | drop_pages(struct drm_i915_gem_object *obj) | |
264 | { | |
265 | struct i915_vma *vma, *next; | |
266 | int ret; | |
267 | ||
268 | drm_gem_object_reference(&obj->base); | |
1c7f4bca | 269 | list_for_each_entry_safe(vma, next, &obj->vma_list, obj_link) |
6a2c4232 CW |
270 | if (i915_vma_unbind(vma)) |
271 | break; | |
272 | ||
273 | ret = i915_gem_object_put_pages(obj); | |
274 | drm_gem_object_unreference(&obj->base); | |
275 | ||
276 | return ret; | |
00731155 CW |
277 | } |
278 | ||
279 | int | |
280 | i915_gem_object_attach_phys(struct drm_i915_gem_object *obj, | |
281 | int align) | |
282 | { | |
283 | drm_dma_handle_t *phys; | |
6a2c4232 | 284 | int ret; |
00731155 CW |
285 | |
286 | if (obj->phys_handle) { | |
287 | if ((unsigned long)obj->phys_handle->vaddr & (align -1)) | |
288 | return -EBUSY; | |
289 | ||
290 | return 0; | |
291 | } | |
292 | ||
293 | if (obj->madv != I915_MADV_WILLNEED) | |
294 | return -EFAULT; | |
295 | ||
296 | if (obj->base.filp == NULL) | |
297 | return -EINVAL; | |
298 | ||
6a2c4232 CW |
299 | ret = drop_pages(obj); |
300 | if (ret) | |
301 | return ret; | |
302 | ||
00731155 CW |
303 | /* create a new object */ |
304 | phys = drm_pci_alloc(obj->base.dev, obj->base.size, align); | |
305 | if (!phys) | |
306 | return -ENOMEM; | |
307 | ||
00731155 | 308 | obj->phys_handle = phys; |
6a2c4232 CW |
309 | obj->ops = &i915_gem_phys_ops; |
310 | ||
311 | return i915_gem_object_get_pages(obj); | |
00731155 CW |
312 | } |
313 | ||
314 | static int | |
315 | i915_gem_phys_pwrite(struct drm_i915_gem_object *obj, | |
316 | struct drm_i915_gem_pwrite *args, | |
317 | struct drm_file *file_priv) | |
318 | { | |
319 | struct drm_device *dev = obj->base.dev; | |
320 | void *vaddr = obj->phys_handle->vaddr + args->offset; | |
321 | char __user *user_data = to_user_ptr(args->data_ptr); | |
063e4e6b | 322 | int ret = 0; |
6a2c4232 CW |
323 | |
324 | /* We manually control the domain here and pretend that it | |
325 | * remains coherent i.e. in the GTT domain, like shmem_pwrite. | |
326 | */ | |
327 | ret = i915_gem_object_wait_rendering(obj, false); | |
328 | if (ret) | |
329 | return ret; | |
00731155 | 330 | |
77a0d1ca | 331 | intel_fb_obj_invalidate(obj, ORIGIN_CPU); |
00731155 CW |
332 | if (__copy_from_user_inatomic_nocache(vaddr, user_data, args->size)) { |
333 | unsigned long unwritten; | |
334 | ||
335 | /* The physical object once assigned is fixed for the lifetime | |
336 | * of the obj, so we can safely drop the lock and continue | |
337 | * to access vaddr. | |
338 | */ | |
339 | mutex_unlock(&dev->struct_mutex); | |
340 | unwritten = copy_from_user(vaddr, user_data, args->size); | |
341 | mutex_lock(&dev->struct_mutex); | |
063e4e6b PZ |
342 | if (unwritten) { |
343 | ret = -EFAULT; | |
344 | goto out; | |
345 | } | |
00731155 CW |
346 | } |
347 | ||
6a2c4232 | 348 | drm_clflush_virt_range(vaddr, args->size); |
00731155 | 349 | i915_gem_chipset_flush(dev); |
063e4e6b PZ |
350 | |
351 | out: | |
de152b62 | 352 | intel_fb_obj_flush(obj, false, ORIGIN_CPU); |
063e4e6b | 353 | return ret; |
00731155 CW |
354 | } |
355 | ||
42dcedd4 CW |
356 | void *i915_gem_object_alloc(struct drm_device *dev) |
357 | { | |
358 | struct drm_i915_private *dev_priv = dev->dev_private; | |
efab6d8d | 359 | return kmem_cache_zalloc(dev_priv->objects, GFP_KERNEL); |
42dcedd4 CW |
360 | } |
361 | ||
362 | void i915_gem_object_free(struct drm_i915_gem_object *obj) | |
363 | { | |
364 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; | |
efab6d8d | 365 | kmem_cache_free(dev_priv->objects, obj); |
42dcedd4 CW |
366 | } |
367 | ||
ff72145b DA |
368 | static int |
369 | i915_gem_create(struct drm_file *file, | |
370 | struct drm_device *dev, | |
371 | uint64_t size, | |
372 | uint32_t *handle_p) | |
673a394b | 373 | { |
05394f39 | 374 | struct drm_i915_gem_object *obj; |
a1a2d1d3 PP |
375 | int ret; |
376 | u32 handle; | |
673a394b | 377 | |
ff72145b | 378 | size = roundup(size, PAGE_SIZE); |
8ffc0246 CW |
379 | if (size == 0) |
380 | return -EINVAL; | |
673a394b EA |
381 | |
382 | /* Allocate the new object */ | |
ff72145b | 383 | obj = i915_gem_alloc_object(dev, size); |
673a394b EA |
384 | if (obj == NULL) |
385 | return -ENOMEM; | |
386 | ||
05394f39 | 387 | ret = drm_gem_handle_create(file, &obj->base, &handle); |
202f2fef | 388 | /* drop reference from allocate - handle holds it now */ |
d861e338 DV |
389 | drm_gem_object_unreference_unlocked(&obj->base); |
390 | if (ret) | |
391 | return ret; | |
202f2fef | 392 | |
ff72145b | 393 | *handle_p = handle; |
673a394b EA |
394 | return 0; |
395 | } | |
396 | ||
ff72145b DA |
397 | int |
398 | i915_gem_dumb_create(struct drm_file *file, | |
399 | struct drm_device *dev, | |
400 | struct drm_mode_create_dumb *args) | |
401 | { | |
402 | /* have to work out size/pitch and return them */ | |
de45eaf7 | 403 | args->pitch = ALIGN(args->width * DIV_ROUND_UP(args->bpp, 8), 64); |
ff72145b DA |
404 | args->size = args->pitch * args->height; |
405 | return i915_gem_create(file, dev, | |
da6b51d0 | 406 | args->size, &args->handle); |
ff72145b DA |
407 | } |
408 | ||
ff72145b DA |
409 | /** |
410 | * Creates a new mm object and returns a handle to it. | |
411 | */ | |
412 | int | |
413 | i915_gem_create_ioctl(struct drm_device *dev, void *data, | |
414 | struct drm_file *file) | |
415 | { | |
416 | struct drm_i915_gem_create *args = data; | |
63ed2cb2 | 417 | |
ff72145b | 418 | return i915_gem_create(file, dev, |
da6b51d0 | 419 | args->size, &args->handle); |
ff72145b DA |
420 | } |
421 | ||
8461d226 DV |
422 | static inline int |
423 | __copy_to_user_swizzled(char __user *cpu_vaddr, | |
424 | const char *gpu_vaddr, int gpu_offset, | |
425 | int length) | |
426 | { | |
427 | int ret, cpu_offset = 0; | |
428 | ||
429 | while (length > 0) { | |
430 | int cacheline_end = ALIGN(gpu_offset + 1, 64); | |
431 | int this_length = min(cacheline_end - gpu_offset, length); | |
432 | int swizzled_gpu_offset = gpu_offset ^ 64; | |
433 | ||
434 | ret = __copy_to_user(cpu_vaddr + cpu_offset, | |
435 | gpu_vaddr + swizzled_gpu_offset, | |
436 | this_length); | |
437 | if (ret) | |
438 | return ret + length; | |
439 | ||
440 | cpu_offset += this_length; | |
441 | gpu_offset += this_length; | |
442 | length -= this_length; | |
443 | } | |
444 | ||
445 | return 0; | |
446 | } | |
447 | ||
8c59967c | 448 | static inline int |
4f0c7cfb BW |
449 | __copy_from_user_swizzled(char *gpu_vaddr, int gpu_offset, |
450 | const char __user *cpu_vaddr, | |
8c59967c DV |
451 | int length) |
452 | { | |
453 | int ret, cpu_offset = 0; | |
454 | ||
455 | while (length > 0) { | |
456 | int cacheline_end = ALIGN(gpu_offset + 1, 64); | |
457 | int this_length = min(cacheline_end - gpu_offset, length); | |
458 | int swizzled_gpu_offset = gpu_offset ^ 64; | |
459 | ||
460 | ret = __copy_from_user(gpu_vaddr + swizzled_gpu_offset, | |
461 | cpu_vaddr + cpu_offset, | |
462 | this_length); | |
463 | if (ret) | |
464 | return ret + length; | |
465 | ||
466 | cpu_offset += this_length; | |
467 | gpu_offset += this_length; | |
468 | length -= this_length; | |
469 | } | |
470 | ||
471 | return 0; | |
472 | } | |
473 | ||
4c914c0c BV |
474 | /* |
475 | * Pins the specified object's pages and synchronizes the object with | |
476 | * GPU accesses. Sets needs_clflush to non-zero if the caller should | |
477 | * flush the object from the CPU cache. | |
478 | */ | |
479 | int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object *obj, | |
480 | int *needs_clflush) | |
481 | { | |
482 | int ret; | |
483 | ||
484 | *needs_clflush = 0; | |
485 | ||
1db6e2e7 | 486 | if (WARN_ON((obj->ops->flags & I915_GEM_OBJECT_HAS_STRUCT_PAGE) == 0)) |
4c914c0c BV |
487 | return -EINVAL; |
488 | ||
489 | if (!(obj->base.read_domains & I915_GEM_DOMAIN_CPU)) { | |
490 | /* If we're not in the cpu read domain, set ourself into the gtt | |
491 | * read domain and manually flush cachelines (if required). This | |
492 | * optimizes for the case when the gpu will dirty the data | |
493 | * anyway again before the next pread happens. */ | |
494 | *needs_clflush = !cpu_cache_is_coherent(obj->base.dev, | |
495 | obj->cache_level); | |
496 | ret = i915_gem_object_wait_rendering(obj, true); | |
497 | if (ret) | |
498 | return ret; | |
499 | } | |
500 | ||
501 | ret = i915_gem_object_get_pages(obj); | |
502 | if (ret) | |
503 | return ret; | |
504 | ||
505 | i915_gem_object_pin_pages(obj); | |
506 | ||
507 | return ret; | |
508 | } | |
509 | ||
d174bd64 DV |
510 | /* Per-page copy function for the shmem pread fastpath. |
511 | * Flushes invalid cachelines before reading the target if | |
512 | * needs_clflush is set. */ | |
eb01459f | 513 | static int |
d174bd64 DV |
514 | shmem_pread_fast(struct page *page, int shmem_page_offset, int page_length, |
515 | char __user *user_data, | |
516 | bool page_do_bit17_swizzling, bool needs_clflush) | |
517 | { | |
518 | char *vaddr; | |
519 | int ret; | |
520 | ||
e7e58eb5 | 521 | if (unlikely(page_do_bit17_swizzling)) |
d174bd64 DV |
522 | return -EINVAL; |
523 | ||
524 | vaddr = kmap_atomic(page); | |
525 | if (needs_clflush) | |
526 | drm_clflush_virt_range(vaddr + shmem_page_offset, | |
527 | page_length); | |
528 | ret = __copy_to_user_inatomic(user_data, | |
529 | vaddr + shmem_page_offset, | |
530 | page_length); | |
531 | kunmap_atomic(vaddr); | |
532 | ||
f60d7f0c | 533 | return ret ? -EFAULT : 0; |
d174bd64 DV |
534 | } |
535 | ||
23c18c71 DV |
536 | static void |
537 | shmem_clflush_swizzled_range(char *addr, unsigned long length, | |
538 | bool swizzled) | |
539 | { | |
e7e58eb5 | 540 | if (unlikely(swizzled)) { |
23c18c71 DV |
541 | unsigned long start = (unsigned long) addr; |
542 | unsigned long end = (unsigned long) addr + length; | |
543 | ||
544 | /* For swizzling simply ensure that we always flush both | |
545 | * channels. Lame, but simple and it works. Swizzled | |
546 | * pwrite/pread is far from a hotpath - current userspace | |
547 | * doesn't use it at all. */ | |
548 | start = round_down(start, 128); | |
549 | end = round_up(end, 128); | |
550 | ||
551 | drm_clflush_virt_range((void *)start, end - start); | |
552 | } else { | |
553 | drm_clflush_virt_range(addr, length); | |
554 | } | |
555 | ||
556 | } | |
557 | ||
d174bd64 DV |
558 | /* Only difference to the fast-path function is that this can handle bit17 |
559 | * and uses non-atomic copy and kmap functions. */ | |
560 | static int | |
561 | shmem_pread_slow(struct page *page, int shmem_page_offset, int page_length, | |
562 | char __user *user_data, | |
563 | bool page_do_bit17_swizzling, bool needs_clflush) | |
564 | { | |
565 | char *vaddr; | |
566 | int ret; | |
567 | ||
568 | vaddr = kmap(page); | |
569 | if (needs_clflush) | |
23c18c71 DV |
570 | shmem_clflush_swizzled_range(vaddr + shmem_page_offset, |
571 | page_length, | |
572 | page_do_bit17_swizzling); | |
d174bd64 DV |
573 | |
574 | if (page_do_bit17_swizzling) | |
575 | ret = __copy_to_user_swizzled(user_data, | |
576 | vaddr, shmem_page_offset, | |
577 | page_length); | |
578 | else | |
579 | ret = __copy_to_user(user_data, | |
580 | vaddr + shmem_page_offset, | |
581 | page_length); | |
582 | kunmap(page); | |
583 | ||
f60d7f0c | 584 | return ret ? - EFAULT : 0; |
d174bd64 DV |
585 | } |
586 | ||
eb01459f | 587 | static int |
dbf7bff0 DV |
588 | i915_gem_shmem_pread(struct drm_device *dev, |
589 | struct drm_i915_gem_object *obj, | |
590 | struct drm_i915_gem_pread *args, | |
591 | struct drm_file *file) | |
eb01459f | 592 | { |
8461d226 | 593 | char __user *user_data; |
eb01459f | 594 | ssize_t remain; |
8461d226 | 595 | loff_t offset; |
eb2c0c81 | 596 | int shmem_page_offset, page_length, ret = 0; |
8461d226 | 597 | int obj_do_bit17_swizzling, page_do_bit17_swizzling; |
96d79b52 | 598 | int prefaulted = 0; |
8489731c | 599 | int needs_clflush = 0; |
67d5a50c | 600 | struct sg_page_iter sg_iter; |
eb01459f | 601 | |
2bb4629a | 602 | user_data = to_user_ptr(args->data_ptr); |
eb01459f EA |
603 | remain = args->size; |
604 | ||
8461d226 | 605 | obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj); |
eb01459f | 606 | |
4c914c0c | 607 | ret = i915_gem_obj_prepare_shmem_read(obj, &needs_clflush); |
f60d7f0c CW |
608 | if (ret) |
609 | return ret; | |
610 | ||
8461d226 | 611 | offset = args->offset; |
eb01459f | 612 | |
67d5a50c ID |
613 | for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, |
614 | offset >> PAGE_SHIFT) { | |
2db76d7c | 615 | struct page *page = sg_page_iter_page(&sg_iter); |
9da3da66 CW |
616 | |
617 | if (remain <= 0) | |
618 | break; | |
619 | ||
eb01459f EA |
620 | /* Operation in this page |
621 | * | |
eb01459f | 622 | * shmem_page_offset = offset within page in shmem file |
eb01459f EA |
623 | * page_length = bytes to copy for this page |
624 | */ | |
c8cbbb8b | 625 | shmem_page_offset = offset_in_page(offset); |
eb01459f EA |
626 | page_length = remain; |
627 | if ((shmem_page_offset + page_length) > PAGE_SIZE) | |
628 | page_length = PAGE_SIZE - shmem_page_offset; | |
eb01459f | 629 | |
8461d226 DV |
630 | page_do_bit17_swizzling = obj_do_bit17_swizzling && |
631 | (page_to_phys(page) & (1 << 17)) != 0; | |
632 | ||
d174bd64 DV |
633 | ret = shmem_pread_fast(page, shmem_page_offset, page_length, |
634 | user_data, page_do_bit17_swizzling, | |
635 | needs_clflush); | |
636 | if (ret == 0) | |
637 | goto next_page; | |
dbf7bff0 | 638 | |
dbf7bff0 DV |
639 | mutex_unlock(&dev->struct_mutex); |
640 | ||
d330a953 | 641 | if (likely(!i915.prefault_disable) && !prefaulted) { |
f56f821f | 642 | ret = fault_in_multipages_writeable(user_data, remain); |
96d79b52 DV |
643 | /* Userspace is tricking us, but we've already clobbered |
644 | * its pages with the prefault and promised to write the | |
645 | * data up to the first fault. Hence ignore any errors | |
646 | * and just continue. */ | |
647 | (void)ret; | |
648 | prefaulted = 1; | |
649 | } | |
eb01459f | 650 | |
d174bd64 DV |
651 | ret = shmem_pread_slow(page, shmem_page_offset, page_length, |
652 | user_data, page_do_bit17_swizzling, | |
653 | needs_clflush); | |
eb01459f | 654 | |
dbf7bff0 | 655 | mutex_lock(&dev->struct_mutex); |
f60d7f0c | 656 | |
f60d7f0c | 657 | if (ret) |
8461d226 | 658 | goto out; |
8461d226 | 659 | |
17793c9a | 660 | next_page: |
eb01459f | 661 | remain -= page_length; |
8461d226 | 662 | user_data += page_length; |
eb01459f EA |
663 | offset += page_length; |
664 | } | |
665 | ||
4f27b75d | 666 | out: |
f60d7f0c CW |
667 | i915_gem_object_unpin_pages(obj); |
668 | ||
eb01459f EA |
669 | return ret; |
670 | } | |
671 | ||
673a394b EA |
672 | /** |
673 | * Reads data from the object referenced by handle. | |
674 | * | |
675 | * On error, the contents of *data are undefined. | |
676 | */ | |
677 | int | |
678 | i915_gem_pread_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 679 | struct drm_file *file) |
673a394b EA |
680 | { |
681 | struct drm_i915_gem_pread *args = data; | |
05394f39 | 682 | struct drm_i915_gem_object *obj; |
35b62a89 | 683 | int ret = 0; |
673a394b | 684 | |
51311d0a CW |
685 | if (args->size == 0) |
686 | return 0; | |
687 | ||
688 | if (!access_ok(VERIFY_WRITE, | |
2bb4629a | 689 | to_user_ptr(args->data_ptr), |
51311d0a CW |
690 | args->size)) |
691 | return -EFAULT; | |
692 | ||
4f27b75d | 693 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 694 | if (ret) |
4f27b75d | 695 | return ret; |
673a394b | 696 | |
05394f39 | 697 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 698 | if (&obj->base == NULL) { |
1d7cfea1 CW |
699 | ret = -ENOENT; |
700 | goto unlock; | |
4f27b75d | 701 | } |
673a394b | 702 | |
7dcd2499 | 703 | /* Bounds check source. */ |
05394f39 CW |
704 | if (args->offset > obj->base.size || |
705 | args->size > obj->base.size - args->offset) { | |
ce9d419d | 706 | ret = -EINVAL; |
35b62a89 | 707 | goto out; |
ce9d419d CW |
708 | } |
709 | ||
1286ff73 DV |
710 | /* prime objects have no backing filp to GEM pread/pwrite |
711 | * pages from. | |
712 | */ | |
713 | if (!obj->base.filp) { | |
714 | ret = -EINVAL; | |
715 | goto out; | |
716 | } | |
717 | ||
db53a302 CW |
718 | trace_i915_gem_object_pread(obj, args->offset, args->size); |
719 | ||
dbf7bff0 | 720 | ret = i915_gem_shmem_pread(dev, obj, args, file); |
673a394b | 721 | |
35b62a89 | 722 | out: |
05394f39 | 723 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 724 | unlock: |
4f27b75d | 725 | mutex_unlock(&dev->struct_mutex); |
eb01459f | 726 | return ret; |
673a394b EA |
727 | } |
728 | ||
0839ccb8 KP |
729 | /* This is the fast write path which cannot handle |
730 | * page faults in the source data | |
9b7530cc | 731 | */ |
0839ccb8 KP |
732 | |
733 | static inline int | |
734 | fast_user_write(struct io_mapping *mapping, | |
735 | loff_t page_base, int page_offset, | |
736 | char __user *user_data, | |
737 | int length) | |
9b7530cc | 738 | { |
4f0c7cfb BW |
739 | void __iomem *vaddr_atomic; |
740 | void *vaddr; | |
0839ccb8 | 741 | unsigned long unwritten; |
9b7530cc | 742 | |
3e4d3af5 | 743 | vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base); |
4f0c7cfb BW |
744 | /* We can use the cpu mem copy function because this is X86. */ |
745 | vaddr = (void __force*)vaddr_atomic + page_offset; | |
746 | unwritten = __copy_from_user_inatomic_nocache(vaddr, | |
0839ccb8 | 747 | user_data, length); |
3e4d3af5 | 748 | io_mapping_unmap_atomic(vaddr_atomic); |
fbd5a26d | 749 | return unwritten; |
0839ccb8 KP |
750 | } |
751 | ||
3de09aa3 EA |
752 | /** |
753 | * This is the fast pwrite path, where we copy the data directly from the | |
754 | * user into the GTT, uncached. | |
755 | */ | |
673a394b | 756 | static int |
05394f39 CW |
757 | i915_gem_gtt_pwrite_fast(struct drm_device *dev, |
758 | struct drm_i915_gem_object *obj, | |
3de09aa3 | 759 | struct drm_i915_gem_pwrite *args, |
05394f39 | 760 | struct drm_file *file) |
673a394b | 761 | { |
72e96d64 JL |
762 | struct drm_i915_private *dev_priv = to_i915(dev); |
763 | struct i915_ggtt *ggtt = &dev_priv->ggtt; | |
673a394b | 764 | ssize_t remain; |
0839ccb8 | 765 | loff_t offset, page_base; |
673a394b | 766 | char __user *user_data; |
935aaa69 DV |
767 | int page_offset, page_length, ret; |
768 | ||
1ec9e26d | 769 | ret = i915_gem_obj_ggtt_pin(obj, 0, PIN_MAPPABLE | PIN_NONBLOCK); |
935aaa69 DV |
770 | if (ret) |
771 | goto out; | |
772 | ||
773 | ret = i915_gem_object_set_to_gtt_domain(obj, true); | |
774 | if (ret) | |
775 | goto out_unpin; | |
776 | ||
777 | ret = i915_gem_object_put_fence(obj); | |
778 | if (ret) | |
779 | goto out_unpin; | |
673a394b | 780 | |
2bb4629a | 781 | user_data = to_user_ptr(args->data_ptr); |
673a394b | 782 | remain = args->size; |
673a394b | 783 | |
f343c5f6 | 784 | offset = i915_gem_obj_ggtt_offset(obj) + args->offset; |
673a394b | 785 | |
77a0d1ca | 786 | intel_fb_obj_invalidate(obj, ORIGIN_GTT); |
063e4e6b | 787 | |
673a394b EA |
788 | while (remain > 0) { |
789 | /* Operation in this page | |
790 | * | |
0839ccb8 KP |
791 | * page_base = page offset within aperture |
792 | * page_offset = offset within page | |
793 | * page_length = bytes to copy for this page | |
673a394b | 794 | */ |
c8cbbb8b CW |
795 | page_base = offset & PAGE_MASK; |
796 | page_offset = offset_in_page(offset); | |
0839ccb8 KP |
797 | page_length = remain; |
798 | if ((page_offset + remain) > PAGE_SIZE) | |
799 | page_length = PAGE_SIZE - page_offset; | |
800 | ||
0839ccb8 | 801 | /* If we get a fault while copying data, then (presumably) our |
3de09aa3 EA |
802 | * source page isn't available. Return the error and we'll |
803 | * retry in the slow path. | |
0839ccb8 | 804 | */ |
72e96d64 | 805 | if (fast_user_write(ggtt->mappable, page_base, |
935aaa69 DV |
806 | page_offset, user_data, page_length)) { |
807 | ret = -EFAULT; | |
063e4e6b | 808 | goto out_flush; |
935aaa69 | 809 | } |
673a394b | 810 | |
0839ccb8 KP |
811 | remain -= page_length; |
812 | user_data += page_length; | |
813 | offset += page_length; | |
673a394b | 814 | } |
673a394b | 815 | |
063e4e6b | 816 | out_flush: |
de152b62 | 817 | intel_fb_obj_flush(obj, false, ORIGIN_GTT); |
935aaa69 | 818 | out_unpin: |
d7f46fc4 | 819 | i915_gem_object_ggtt_unpin(obj); |
935aaa69 | 820 | out: |
3de09aa3 | 821 | return ret; |
673a394b EA |
822 | } |
823 | ||
d174bd64 DV |
824 | /* Per-page copy function for the shmem pwrite fastpath. |
825 | * Flushes invalid cachelines before writing to the target if | |
826 | * needs_clflush_before is set and flushes out any written cachelines after | |
827 | * writing if needs_clflush is set. */ | |
3043c60c | 828 | static int |
d174bd64 DV |
829 | shmem_pwrite_fast(struct page *page, int shmem_page_offset, int page_length, |
830 | char __user *user_data, | |
831 | bool page_do_bit17_swizzling, | |
832 | bool needs_clflush_before, | |
833 | bool needs_clflush_after) | |
673a394b | 834 | { |
d174bd64 | 835 | char *vaddr; |
673a394b | 836 | int ret; |
3de09aa3 | 837 | |
e7e58eb5 | 838 | if (unlikely(page_do_bit17_swizzling)) |
d174bd64 | 839 | return -EINVAL; |
3de09aa3 | 840 | |
d174bd64 DV |
841 | vaddr = kmap_atomic(page); |
842 | if (needs_clflush_before) | |
843 | drm_clflush_virt_range(vaddr + shmem_page_offset, | |
844 | page_length); | |
c2831a94 CW |
845 | ret = __copy_from_user_inatomic(vaddr + shmem_page_offset, |
846 | user_data, page_length); | |
d174bd64 DV |
847 | if (needs_clflush_after) |
848 | drm_clflush_virt_range(vaddr + shmem_page_offset, | |
849 | page_length); | |
850 | kunmap_atomic(vaddr); | |
3de09aa3 | 851 | |
755d2218 | 852 | return ret ? -EFAULT : 0; |
3de09aa3 EA |
853 | } |
854 | ||
d174bd64 DV |
855 | /* Only difference to the fast-path function is that this can handle bit17 |
856 | * and uses non-atomic copy and kmap functions. */ | |
3043c60c | 857 | static int |
d174bd64 DV |
858 | shmem_pwrite_slow(struct page *page, int shmem_page_offset, int page_length, |
859 | char __user *user_data, | |
860 | bool page_do_bit17_swizzling, | |
861 | bool needs_clflush_before, | |
862 | bool needs_clflush_after) | |
673a394b | 863 | { |
d174bd64 DV |
864 | char *vaddr; |
865 | int ret; | |
e5281ccd | 866 | |
d174bd64 | 867 | vaddr = kmap(page); |
e7e58eb5 | 868 | if (unlikely(needs_clflush_before || page_do_bit17_swizzling)) |
23c18c71 DV |
869 | shmem_clflush_swizzled_range(vaddr + shmem_page_offset, |
870 | page_length, | |
871 | page_do_bit17_swizzling); | |
d174bd64 DV |
872 | if (page_do_bit17_swizzling) |
873 | ret = __copy_from_user_swizzled(vaddr, shmem_page_offset, | |
e5281ccd CW |
874 | user_data, |
875 | page_length); | |
d174bd64 DV |
876 | else |
877 | ret = __copy_from_user(vaddr + shmem_page_offset, | |
878 | user_data, | |
879 | page_length); | |
880 | if (needs_clflush_after) | |
23c18c71 DV |
881 | shmem_clflush_swizzled_range(vaddr + shmem_page_offset, |
882 | page_length, | |
883 | page_do_bit17_swizzling); | |
d174bd64 | 884 | kunmap(page); |
40123c1f | 885 | |
755d2218 | 886 | return ret ? -EFAULT : 0; |
40123c1f EA |
887 | } |
888 | ||
40123c1f | 889 | static int |
e244a443 DV |
890 | i915_gem_shmem_pwrite(struct drm_device *dev, |
891 | struct drm_i915_gem_object *obj, | |
892 | struct drm_i915_gem_pwrite *args, | |
893 | struct drm_file *file) | |
40123c1f | 894 | { |
40123c1f | 895 | ssize_t remain; |
8c59967c DV |
896 | loff_t offset; |
897 | char __user *user_data; | |
eb2c0c81 | 898 | int shmem_page_offset, page_length, ret = 0; |
8c59967c | 899 | int obj_do_bit17_swizzling, page_do_bit17_swizzling; |
e244a443 | 900 | int hit_slowpath = 0; |
58642885 DV |
901 | int needs_clflush_after = 0; |
902 | int needs_clflush_before = 0; | |
67d5a50c | 903 | struct sg_page_iter sg_iter; |
40123c1f | 904 | |
2bb4629a | 905 | user_data = to_user_ptr(args->data_ptr); |
40123c1f EA |
906 | remain = args->size; |
907 | ||
8c59967c | 908 | obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj); |
40123c1f | 909 | |
58642885 DV |
910 | if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) { |
911 | /* If we're not in the cpu write domain, set ourself into the gtt | |
912 | * write domain and manually flush cachelines (if required). This | |
913 | * optimizes for the case when the gpu will use the data | |
914 | * right away and we therefore have to clflush anyway. */ | |
2c22569b | 915 | needs_clflush_after = cpu_write_needs_clflush(obj); |
23f54483 BW |
916 | ret = i915_gem_object_wait_rendering(obj, false); |
917 | if (ret) | |
918 | return ret; | |
58642885 | 919 | } |
c76ce038 CW |
920 | /* Same trick applies to invalidate partially written cachelines read |
921 | * before writing. */ | |
922 | if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0) | |
923 | needs_clflush_before = | |
924 | !cpu_cache_is_coherent(dev, obj->cache_level); | |
58642885 | 925 | |
755d2218 CW |
926 | ret = i915_gem_object_get_pages(obj); |
927 | if (ret) | |
928 | return ret; | |
929 | ||
77a0d1ca | 930 | intel_fb_obj_invalidate(obj, ORIGIN_CPU); |
063e4e6b | 931 | |
755d2218 CW |
932 | i915_gem_object_pin_pages(obj); |
933 | ||
673a394b | 934 | offset = args->offset; |
05394f39 | 935 | obj->dirty = 1; |
673a394b | 936 | |
67d5a50c ID |
937 | for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, |
938 | offset >> PAGE_SHIFT) { | |
2db76d7c | 939 | struct page *page = sg_page_iter_page(&sg_iter); |
58642885 | 940 | int partial_cacheline_write; |
e5281ccd | 941 | |
9da3da66 CW |
942 | if (remain <= 0) |
943 | break; | |
944 | ||
40123c1f EA |
945 | /* Operation in this page |
946 | * | |
40123c1f | 947 | * shmem_page_offset = offset within page in shmem file |
40123c1f EA |
948 | * page_length = bytes to copy for this page |
949 | */ | |
c8cbbb8b | 950 | shmem_page_offset = offset_in_page(offset); |
40123c1f EA |
951 | |
952 | page_length = remain; | |
953 | if ((shmem_page_offset + page_length) > PAGE_SIZE) | |
954 | page_length = PAGE_SIZE - shmem_page_offset; | |
40123c1f | 955 | |
58642885 DV |
956 | /* If we don't overwrite a cacheline completely we need to be |
957 | * careful to have up-to-date data by first clflushing. Don't | |
958 | * overcomplicate things and flush the entire patch. */ | |
959 | partial_cacheline_write = needs_clflush_before && | |
960 | ((shmem_page_offset | page_length) | |
961 | & (boot_cpu_data.x86_clflush_size - 1)); | |
962 | ||
8c59967c DV |
963 | page_do_bit17_swizzling = obj_do_bit17_swizzling && |
964 | (page_to_phys(page) & (1 << 17)) != 0; | |
965 | ||
d174bd64 DV |
966 | ret = shmem_pwrite_fast(page, shmem_page_offset, page_length, |
967 | user_data, page_do_bit17_swizzling, | |
968 | partial_cacheline_write, | |
969 | needs_clflush_after); | |
970 | if (ret == 0) | |
971 | goto next_page; | |
e244a443 DV |
972 | |
973 | hit_slowpath = 1; | |
e244a443 | 974 | mutex_unlock(&dev->struct_mutex); |
d174bd64 DV |
975 | ret = shmem_pwrite_slow(page, shmem_page_offset, page_length, |
976 | user_data, page_do_bit17_swizzling, | |
977 | partial_cacheline_write, | |
978 | needs_clflush_after); | |
40123c1f | 979 | |
e244a443 | 980 | mutex_lock(&dev->struct_mutex); |
755d2218 | 981 | |
755d2218 | 982 | if (ret) |
8c59967c | 983 | goto out; |
8c59967c | 984 | |
17793c9a | 985 | next_page: |
40123c1f | 986 | remain -= page_length; |
8c59967c | 987 | user_data += page_length; |
40123c1f | 988 | offset += page_length; |
673a394b EA |
989 | } |
990 | ||
fbd5a26d | 991 | out: |
755d2218 CW |
992 | i915_gem_object_unpin_pages(obj); |
993 | ||
e244a443 | 994 | if (hit_slowpath) { |
8dcf015e DV |
995 | /* |
996 | * Fixup: Flush cpu caches in case we didn't flush the dirty | |
997 | * cachelines in-line while writing and the object moved | |
998 | * out of the cpu write domain while we've dropped the lock. | |
999 | */ | |
1000 | if (!needs_clflush_after && | |
1001 | obj->base.write_domain != I915_GEM_DOMAIN_CPU) { | |
000433b6 | 1002 | if (i915_gem_clflush_object(obj, obj->pin_display)) |
ed75a55b | 1003 | needs_clflush_after = true; |
e244a443 | 1004 | } |
8c59967c | 1005 | } |
673a394b | 1006 | |
58642885 | 1007 | if (needs_clflush_after) |
e76e9aeb | 1008 | i915_gem_chipset_flush(dev); |
ed75a55b VS |
1009 | else |
1010 | obj->cache_dirty = true; | |
58642885 | 1011 | |
de152b62 | 1012 | intel_fb_obj_flush(obj, false, ORIGIN_CPU); |
40123c1f | 1013 | return ret; |
673a394b EA |
1014 | } |
1015 | ||
1016 | /** | |
1017 | * Writes data to the object referenced by handle. | |
1018 | * | |
1019 | * On error, the contents of the buffer that were to be modified are undefined. | |
1020 | */ | |
1021 | int | |
1022 | i915_gem_pwrite_ioctl(struct drm_device *dev, void *data, | |
fbd5a26d | 1023 | struct drm_file *file) |
673a394b | 1024 | { |
5d77d9c5 | 1025 | struct drm_i915_private *dev_priv = dev->dev_private; |
673a394b | 1026 | struct drm_i915_gem_pwrite *args = data; |
05394f39 | 1027 | struct drm_i915_gem_object *obj; |
51311d0a CW |
1028 | int ret; |
1029 | ||
1030 | if (args->size == 0) | |
1031 | return 0; | |
1032 | ||
1033 | if (!access_ok(VERIFY_READ, | |
2bb4629a | 1034 | to_user_ptr(args->data_ptr), |
51311d0a CW |
1035 | args->size)) |
1036 | return -EFAULT; | |
1037 | ||
d330a953 | 1038 | if (likely(!i915.prefault_disable)) { |
0b74b508 XZ |
1039 | ret = fault_in_multipages_readable(to_user_ptr(args->data_ptr), |
1040 | args->size); | |
1041 | if (ret) | |
1042 | return -EFAULT; | |
1043 | } | |
673a394b | 1044 | |
5d77d9c5 ID |
1045 | intel_runtime_pm_get(dev_priv); |
1046 | ||
fbd5a26d | 1047 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 1048 | if (ret) |
5d77d9c5 | 1049 | goto put_rpm; |
1d7cfea1 | 1050 | |
05394f39 | 1051 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 1052 | if (&obj->base == NULL) { |
1d7cfea1 CW |
1053 | ret = -ENOENT; |
1054 | goto unlock; | |
fbd5a26d | 1055 | } |
673a394b | 1056 | |
7dcd2499 | 1057 | /* Bounds check destination. */ |
05394f39 CW |
1058 | if (args->offset > obj->base.size || |
1059 | args->size > obj->base.size - args->offset) { | |
ce9d419d | 1060 | ret = -EINVAL; |
35b62a89 | 1061 | goto out; |
ce9d419d CW |
1062 | } |
1063 | ||
1286ff73 DV |
1064 | /* prime objects have no backing filp to GEM pread/pwrite |
1065 | * pages from. | |
1066 | */ | |
1067 | if (!obj->base.filp) { | |
1068 | ret = -EINVAL; | |
1069 | goto out; | |
1070 | } | |
1071 | ||
db53a302 CW |
1072 | trace_i915_gem_object_pwrite(obj, args->offset, args->size); |
1073 | ||
935aaa69 | 1074 | ret = -EFAULT; |
673a394b EA |
1075 | /* We can only do the GTT pwrite on untiled buffers, as otherwise |
1076 | * it would end up going through the fenced access, and we'll get | |
1077 | * different detiling behavior between reading and writing. | |
1078 | * pread/pwrite currently are reading and writing from the CPU | |
1079 | * perspective, requiring manual detiling by the client. | |
1080 | */ | |
2c22569b CW |
1081 | if (obj->tiling_mode == I915_TILING_NONE && |
1082 | obj->base.write_domain != I915_GEM_DOMAIN_CPU && | |
1083 | cpu_write_needs_clflush(obj)) { | |
fbd5a26d | 1084 | ret = i915_gem_gtt_pwrite_fast(dev, obj, args, file); |
935aaa69 DV |
1085 | /* Note that the gtt paths might fail with non-page-backed user |
1086 | * pointers (e.g. gtt mappings when moving data between | |
1087 | * textures). Fallback to the shmem path in that case. */ | |
fbd5a26d | 1088 | } |
673a394b | 1089 | |
6a2c4232 CW |
1090 | if (ret == -EFAULT || ret == -ENOSPC) { |
1091 | if (obj->phys_handle) | |
1092 | ret = i915_gem_phys_pwrite(obj, args, file); | |
1093 | else | |
1094 | ret = i915_gem_shmem_pwrite(dev, obj, args, file); | |
1095 | } | |
5c0480f2 | 1096 | |
35b62a89 | 1097 | out: |
05394f39 | 1098 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 1099 | unlock: |
fbd5a26d | 1100 | mutex_unlock(&dev->struct_mutex); |
5d77d9c5 ID |
1101 | put_rpm: |
1102 | intel_runtime_pm_put(dev_priv); | |
1103 | ||
673a394b EA |
1104 | return ret; |
1105 | } | |
1106 | ||
f4457ae7 CW |
1107 | static int |
1108 | i915_gem_check_wedge(unsigned reset_counter, bool interruptible) | |
b361237b | 1109 | { |
f4457ae7 CW |
1110 | if (__i915_terminally_wedged(reset_counter)) |
1111 | return -EIO; | |
d98c52cf | 1112 | |
f4457ae7 | 1113 | if (__i915_reset_in_progress(reset_counter)) { |
b361237b CW |
1114 | /* Non-interruptible callers can't handle -EAGAIN, hence return |
1115 | * -EIO unconditionally for these. */ | |
1116 | if (!interruptible) | |
1117 | return -EIO; | |
1118 | ||
d98c52cf | 1119 | return -EAGAIN; |
b361237b CW |
1120 | } |
1121 | ||
1122 | return 0; | |
1123 | } | |
1124 | ||
094f9a54 CW |
1125 | static void fake_irq(unsigned long data) |
1126 | { | |
1127 | wake_up_process((struct task_struct *)data); | |
1128 | } | |
1129 | ||
1130 | static bool missed_irq(struct drm_i915_private *dev_priv, | |
0bc40be8 | 1131 | struct intel_engine_cs *engine) |
094f9a54 | 1132 | { |
0bc40be8 | 1133 | return test_bit(engine->id, &dev_priv->gpu_error.missed_irq_rings); |
094f9a54 CW |
1134 | } |
1135 | ||
ca5b721e CW |
1136 | static unsigned long local_clock_us(unsigned *cpu) |
1137 | { | |
1138 | unsigned long t; | |
1139 | ||
1140 | /* Cheaply and approximately convert from nanoseconds to microseconds. | |
1141 | * The result and subsequent calculations are also defined in the same | |
1142 | * approximate microseconds units. The principal source of timing | |
1143 | * error here is from the simple truncation. | |
1144 | * | |
1145 | * Note that local_clock() is only defined wrt to the current CPU; | |
1146 | * the comparisons are no longer valid if we switch CPUs. Instead of | |
1147 | * blocking preemption for the entire busywait, we can detect the CPU | |
1148 | * switch and use that as indicator of system load and a reason to | |
1149 | * stop busywaiting, see busywait_stop(). | |
1150 | */ | |
1151 | *cpu = get_cpu(); | |
1152 | t = local_clock() >> 10; | |
1153 | put_cpu(); | |
1154 | ||
1155 | return t; | |
1156 | } | |
1157 | ||
1158 | static bool busywait_stop(unsigned long timeout, unsigned cpu) | |
1159 | { | |
1160 | unsigned this_cpu; | |
1161 | ||
1162 | if (time_after(local_clock_us(&this_cpu), timeout)) | |
1163 | return true; | |
1164 | ||
1165 | return this_cpu != cpu; | |
1166 | } | |
1167 | ||
91b0c352 | 1168 | static int __i915_spin_request(struct drm_i915_gem_request *req, int state) |
b29c19b6 | 1169 | { |
2def4ad9 | 1170 | unsigned long timeout; |
ca5b721e CW |
1171 | unsigned cpu; |
1172 | ||
1173 | /* When waiting for high frequency requests, e.g. during synchronous | |
1174 | * rendering split between the CPU and GPU, the finite amount of time | |
1175 | * required to set up the irq and wait upon it limits the response | |
1176 | * rate. By busywaiting on the request completion for a short while we | |
1177 | * can service the high frequency waits as quick as possible. However, | |
1178 | * if it is a slow request, we want to sleep as quickly as possible. | |
1179 | * The tradeoff between waiting and sleeping is roughly the time it | |
1180 | * takes to sleep on a request, on the order of a microsecond. | |
1181 | */ | |
2def4ad9 | 1182 | |
4a570db5 | 1183 | if (req->engine->irq_refcount) |
2def4ad9 CW |
1184 | return -EBUSY; |
1185 | ||
821485dc CW |
1186 | /* Only spin if we know the GPU is processing this request */ |
1187 | if (!i915_gem_request_started(req, true)) | |
1188 | return -EAGAIN; | |
1189 | ||
ca5b721e | 1190 | timeout = local_clock_us(&cpu) + 5; |
2def4ad9 | 1191 | while (!need_resched()) { |
eed29a5b | 1192 | if (i915_gem_request_completed(req, true)) |
2def4ad9 CW |
1193 | return 0; |
1194 | ||
91b0c352 CW |
1195 | if (signal_pending_state(state, current)) |
1196 | break; | |
1197 | ||
ca5b721e | 1198 | if (busywait_stop(timeout, cpu)) |
2def4ad9 | 1199 | break; |
b29c19b6 | 1200 | |
2def4ad9 CW |
1201 | cpu_relax_lowlatency(); |
1202 | } | |
821485dc | 1203 | |
eed29a5b | 1204 | if (i915_gem_request_completed(req, false)) |
2def4ad9 CW |
1205 | return 0; |
1206 | ||
1207 | return -EAGAIN; | |
b29c19b6 CW |
1208 | } |
1209 | ||
b361237b | 1210 | /** |
9c654818 JH |
1211 | * __i915_wait_request - wait until execution of request has finished |
1212 | * @req: duh! | |
b361237b CW |
1213 | * @interruptible: do an interruptible wait (normally yes) |
1214 | * @timeout: in - how long to wait (NULL forever); out - how much time remaining | |
1215 | * | |
f69061be DV |
1216 | * Note: It is of utmost importance that the passed in seqno and reset_counter |
1217 | * values have been read by the caller in an smp safe manner. Where read-side | |
1218 | * locks are involved, it is sufficient to read the reset_counter before | |
1219 | * unlocking the lock that protects the seqno. For lockless tricks, the | |
1220 | * reset_counter _must_ be read before, and an appropriate smp_rmb must be | |
1221 | * inserted. | |
1222 | * | |
9c654818 | 1223 | * Returns 0 if the request was found within the alloted time. Else returns the |
b361237b CW |
1224 | * errno with remaining time filled in timeout argument. |
1225 | */ | |
9c654818 | 1226 | int __i915_wait_request(struct drm_i915_gem_request *req, |
b29c19b6 | 1227 | bool interruptible, |
5ed0bdf2 | 1228 | s64 *timeout, |
2e1b8730 | 1229 | struct intel_rps_client *rps) |
b361237b | 1230 | { |
666796da | 1231 | struct intel_engine_cs *engine = i915_gem_request_get_engine(req); |
e2f80391 | 1232 | struct drm_device *dev = engine->dev; |
3e31c6c0 | 1233 | struct drm_i915_private *dev_priv = dev->dev_private; |
168c3f21 | 1234 | const bool irq_test_in_progress = |
666796da | 1235 | ACCESS_ONCE(dev_priv->gpu_error.test_irq_rings) & intel_engine_flag(engine); |
91b0c352 | 1236 | int state = interruptible ? TASK_INTERRUPTIBLE : TASK_UNINTERRUPTIBLE; |
094f9a54 | 1237 | DEFINE_WAIT(wait); |
47e9766d | 1238 | unsigned long timeout_expire; |
e0313db0 | 1239 | s64 before = 0; /* Only to silence a compiler warning. */ |
b361237b CW |
1240 | int ret; |
1241 | ||
9df7575f | 1242 | WARN(!intel_irqs_enabled(dev_priv), "IRQs disabled"); |
c67a470b | 1243 | |
b4716185 CW |
1244 | if (list_empty(&req->list)) |
1245 | return 0; | |
1246 | ||
1b5a433a | 1247 | if (i915_gem_request_completed(req, true)) |
b361237b CW |
1248 | return 0; |
1249 | ||
bb6d1984 CW |
1250 | timeout_expire = 0; |
1251 | if (timeout) { | |
1252 | if (WARN_ON(*timeout < 0)) | |
1253 | return -EINVAL; | |
1254 | ||
1255 | if (*timeout == 0) | |
1256 | return -ETIME; | |
1257 | ||
1258 | timeout_expire = jiffies + nsecs_to_jiffies_timeout(*timeout); | |
e0313db0 TU |
1259 | |
1260 | /* | |
1261 | * Record current time in case interrupted by signal, or wedged. | |
1262 | */ | |
1263 | before = ktime_get_raw_ns(); | |
bb6d1984 | 1264 | } |
b361237b | 1265 | |
2e1b8730 | 1266 | if (INTEL_INFO(dev_priv)->gen >= 6) |
e61b9958 | 1267 | gen6_rps_boost(dev_priv, rps, req->emitted_jiffies); |
b361237b | 1268 | |
74328ee5 | 1269 | trace_i915_gem_request_wait_begin(req); |
2def4ad9 CW |
1270 | |
1271 | /* Optimistic spin for the next jiffie before touching IRQs */ | |
91b0c352 | 1272 | ret = __i915_spin_request(req, state); |
2def4ad9 CW |
1273 | if (ret == 0) |
1274 | goto out; | |
1275 | ||
e2f80391 | 1276 | if (!irq_test_in_progress && WARN_ON(!engine->irq_get(engine))) { |
2def4ad9 CW |
1277 | ret = -ENODEV; |
1278 | goto out; | |
1279 | } | |
1280 | ||
094f9a54 CW |
1281 | for (;;) { |
1282 | struct timer_list timer; | |
b361237b | 1283 | |
e2f80391 | 1284 | prepare_to_wait(&engine->irq_queue, &wait, state); |
b361237b | 1285 | |
f69061be | 1286 | /* We need to check whether any gpu reset happened in between |
f4457ae7 CW |
1287 | * the request being submitted and now. If a reset has occurred, |
1288 | * the request is effectively complete (we either are in the | |
1289 | * process of or have discarded the rendering and completely | |
1290 | * reset the GPU. The results of the request are lost and we | |
1291 | * are free to continue on with the original operation. | |
1292 | */ | |
299259a3 | 1293 | if (req->reset_counter != i915_reset_counter(&dev_priv->gpu_error)) { |
f4457ae7 | 1294 | ret = 0; |
094f9a54 CW |
1295 | break; |
1296 | } | |
f69061be | 1297 | |
1b5a433a | 1298 | if (i915_gem_request_completed(req, false)) { |
094f9a54 CW |
1299 | ret = 0; |
1300 | break; | |
1301 | } | |
b361237b | 1302 | |
91b0c352 | 1303 | if (signal_pending_state(state, current)) { |
094f9a54 CW |
1304 | ret = -ERESTARTSYS; |
1305 | break; | |
1306 | } | |
1307 | ||
47e9766d | 1308 | if (timeout && time_after_eq(jiffies, timeout_expire)) { |
094f9a54 CW |
1309 | ret = -ETIME; |
1310 | break; | |
1311 | } | |
1312 | ||
1313 | timer.function = NULL; | |
e2f80391 | 1314 | if (timeout || missed_irq(dev_priv, engine)) { |
47e9766d MK |
1315 | unsigned long expire; |
1316 | ||
094f9a54 | 1317 | setup_timer_on_stack(&timer, fake_irq, (unsigned long)current); |
e2f80391 | 1318 | expire = missed_irq(dev_priv, engine) ? jiffies + 1 : timeout_expire; |
094f9a54 CW |
1319 | mod_timer(&timer, expire); |
1320 | } | |
1321 | ||
5035c275 | 1322 | io_schedule(); |
094f9a54 | 1323 | |
094f9a54 CW |
1324 | if (timer.function) { |
1325 | del_singleshot_timer_sync(&timer); | |
1326 | destroy_timer_on_stack(&timer); | |
1327 | } | |
1328 | } | |
168c3f21 | 1329 | if (!irq_test_in_progress) |
e2f80391 | 1330 | engine->irq_put(engine); |
094f9a54 | 1331 | |
e2f80391 | 1332 | finish_wait(&engine->irq_queue, &wait); |
b361237b | 1333 | |
2def4ad9 | 1334 | out: |
2def4ad9 CW |
1335 | trace_i915_gem_request_wait_end(req); |
1336 | ||
b361237b | 1337 | if (timeout) { |
e0313db0 | 1338 | s64 tres = *timeout - (ktime_get_raw_ns() - before); |
5ed0bdf2 TG |
1339 | |
1340 | *timeout = tres < 0 ? 0 : tres; | |
9cca3068 DV |
1341 | |
1342 | /* | |
1343 | * Apparently ktime isn't accurate enough and occasionally has a | |
1344 | * bit of mismatch in the jiffies<->nsecs<->ktime loop. So patch | |
1345 | * things up to make the test happy. We allow up to 1 jiffy. | |
1346 | * | |
1347 | * This is a regrssion from the timespec->ktime conversion. | |
1348 | */ | |
1349 | if (ret == -ETIME && *timeout < jiffies_to_usecs(1)*1000) | |
1350 | *timeout = 0; | |
b361237b CW |
1351 | } |
1352 | ||
094f9a54 | 1353 | return ret; |
b361237b CW |
1354 | } |
1355 | ||
fcfa423c JH |
1356 | int i915_gem_request_add_to_client(struct drm_i915_gem_request *req, |
1357 | struct drm_file *file) | |
1358 | { | |
fcfa423c JH |
1359 | struct drm_i915_file_private *file_priv; |
1360 | ||
1361 | WARN_ON(!req || !file || req->file_priv); | |
1362 | ||
1363 | if (!req || !file) | |
1364 | return -EINVAL; | |
1365 | ||
1366 | if (req->file_priv) | |
1367 | return -EINVAL; | |
1368 | ||
fcfa423c JH |
1369 | file_priv = file->driver_priv; |
1370 | ||
1371 | spin_lock(&file_priv->mm.lock); | |
1372 | req->file_priv = file_priv; | |
1373 | list_add_tail(&req->client_list, &file_priv->mm.request_list); | |
1374 | spin_unlock(&file_priv->mm.lock); | |
1375 | ||
1376 | req->pid = get_pid(task_pid(current)); | |
1377 | ||
1378 | return 0; | |
1379 | } | |
1380 | ||
b4716185 CW |
1381 | static inline void |
1382 | i915_gem_request_remove_from_client(struct drm_i915_gem_request *request) | |
1383 | { | |
1384 | struct drm_i915_file_private *file_priv = request->file_priv; | |
1385 | ||
1386 | if (!file_priv) | |
1387 | return; | |
1388 | ||
1389 | spin_lock(&file_priv->mm.lock); | |
1390 | list_del(&request->client_list); | |
1391 | request->file_priv = NULL; | |
1392 | spin_unlock(&file_priv->mm.lock); | |
fcfa423c JH |
1393 | |
1394 | put_pid(request->pid); | |
1395 | request->pid = NULL; | |
b4716185 CW |
1396 | } |
1397 | ||
1398 | static void i915_gem_request_retire(struct drm_i915_gem_request *request) | |
1399 | { | |
1400 | trace_i915_gem_request_retire(request); | |
1401 | ||
1402 | /* We know the GPU must have read the request to have | |
1403 | * sent us the seqno + interrupt, so use the position | |
1404 | * of tail of the request to update the last known position | |
1405 | * of the GPU head. | |
1406 | * | |
1407 | * Note this requires that we are always called in request | |
1408 | * completion order. | |
1409 | */ | |
1410 | request->ringbuf->last_retired_head = request->postfix; | |
1411 | ||
1412 | list_del_init(&request->list); | |
1413 | i915_gem_request_remove_from_client(request); | |
1414 | ||
b4716185 CW |
1415 | i915_gem_request_unreference(request); |
1416 | } | |
1417 | ||
1418 | static void | |
1419 | __i915_gem_request_retire__upto(struct drm_i915_gem_request *req) | |
1420 | { | |
4a570db5 | 1421 | struct intel_engine_cs *engine = req->engine; |
b4716185 CW |
1422 | struct drm_i915_gem_request *tmp; |
1423 | ||
1424 | lockdep_assert_held(&engine->dev->struct_mutex); | |
1425 | ||
1426 | if (list_empty(&req->list)) | |
1427 | return; | |
1428 | ||
1429 | do { | |
1430 | tmp = list_first_entry(&engine->request_list, | |
1431 | typeof(*tmp), list); | |
1432 | ||
1433 | i915_gem_request_retire(tmp); | |
1434 | } while (tmp != req); | |
1435 | ||
1436 | WARN_ON(i915_verify_lists(engine->dev)); | |
1437 | } | |
1438 | ||
b361237b | 1439 | /** |
a4b3a571 | 1440 | * Waits for a request to be signaled, and cleans up the |
b361237b CW |
1441 | * request and object lists appropriately for that event. |
1442 | */ | |
1443 | int | |
a4b3a571 | 1444 | i915_wait_request(struct drm_i915_gem_request *req) |
b361237b | 1445 | { |
a4b3a571 DV |
1446 | struct drm_device *dev; |
1447 | struct drm_i915_private *dev_priv; | |
1448 | bool interruptible; | |
b361237b CW |
1449 | int ret; |
1450 | ||
a4b3a571 DV |
1451 | BUG_ON(req == NULL); |
1452 | ||
4a570db5 | 1453 | dev = req->engine->dev; |
a4b3a571 DV |
1454 | dev_priv = dev->dev_private; |
1455 | interruptible = dev_priv->mm.interruptible; | |
1456 | ||
b361237b | 1457 | BUG_ON(!mutex_is_locked(&dev->struct_mutex)); |
b361237b | 1458 | |
299259a3 | 1459 | ret = __i915_wait_request(req, interruptible, NULL, NULL); |
b4716185 CW |
1460 | if (ret) |
1461 | return ret; | |
d26e3af8 | 1462 | |
b4716185 | 1463 | __i915_gem_request_retire__upto(req); |
d26e3af8 CW |
1464 | return 0; |
1465 | } | |
1466 | ||
b361237b CW |
1467 | /** |
1468 | * Ensures that all rendering to the object has completed and the object is | |
1469 | * safe to unbind from the GTT or access from the CPU. | |
1470 | */ | |
2e2f351d | 1471 | int |
b361237b CW |
1472 | i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj, |
1473 | bool readonly) | |
1474 | { | |
b4716185 | 1475 | int ret, i; |
b361237b | 1476 | |
b4716185 | 1477 | if (!obj->active) |
b361237b CW |
1478 | return 0; |
1479 | ||
b4716185 CW |
1480 | if (readonly) { |
1481 | if (obj->last_write_req != NULL) { | |
1482 | ret = i915_wait_request(obj->last_write_req); | |
1483 | if (ret) | |
1484 | return ret; | |
b361237b | 1485 | |
4a570db5 | 1486 | i = obj->last_write_req->engine->id; |
b4716185 CW |
1487 | if (obj->last_read_req[i] == obj->last_write_req) |
1488 | i915_gem_object_retire__read(obj, i); | |
1489 | else | |
1490 | i915_gem_object_retire__write(obj); | |
1491 | } | |
1492 | } else { | |
666796da | 1493 | for (i = 0; i < I915_NUM_ENGINES; i++) { |
b4716185 CW |
1494 | if (obj->last_read_req[i] == NULL) |
1495 | continue; | |
1496 | ||
1497 | ret = i915_wait_request(obj->last_read_req[i]); | |
1498 | if (ret) | |
1499 | return ret; | |
1500 | ||
1501 | i915_gem_object_retire__read(obj, i); | |
1502 | } | |
d501b1d2 | 1503 | GEM_BUG_ON(obj->active); |
b4716185 CW |
1504 | } |
1505 | ||
1506 | return 0; | |
1507 | } | |
1508 | ||
1509 | static void | |
1510 | i915_gem_object_retire_request(struct drm_i915_gem_object *obj, | |
1511 | struct drm_i915_gem_request *req) | |
1512 | { | |
4a570db5 | 1513 | int ring = req->engine->id; |
b4716185 CW |
1514 | |
1515 | if (obj->last_read_req[ring] == req) | |
1516 | i915_gem_object_retire__read(obj, ring); | |
1517 | else if (obj->last_write_req == req) | |
1518 | i915_gem_object_retire__write(obj); | |
1519 | ||
1520 | __i915_gem_request_retire__upto(req); | |
b361237b CW |
1521 | } |
1522 | ||
3236f57a CW |
1523 | /* A nonblocking variant of the above wait. This is a highly dangerous routine |
1524 | * as the object state may change during this call. | |
1525 | */ | |
1526 | static __must_check int | |
1527 | i915_gem_object_wait_rendering__nonblocking(struct drm_i915_gem_object *obj, | |
2e1b8730 | 1528 | struct intel_rps_client *rps, |
3236f57a CW |
1529 | bool readonly) |
1530 | { | |
1531 | struct drm_device *dev = obj->base.dev; | |
1532 | struct drm_i915_private *dev_priv = dev->dev_private; | |
666796da | 1533 | struct drm_i915_gem_request *requests[I915_NUM_ENGINES]; |
b4716185 | 1534 | int ret, i, n = 0; |
3236f57a CW |
1535 | |
1536 | BUG_ON(!mutex_is_locked(&dev->struct_mutex)); | |
1537 | BUG_ON(!dev_priv->mm.interruptible); | |
1538 | ||
b4716185 | 1539 | if (!obj->active) |
3236f57a CW |
1540 | return 0; |
1541 | ||
b4716185 CW |
1542 | if (readonly) { |
1543 | struct drm_i915_gem_request *req; | |
1544 | ||
1545 | req = obj->last_write_req; | |
1546 | if (req == NULL) | |
1547 | return 0; | |
1548 | ||
b4716185 CW |
1549 | requests[n++] = i915_gem_request_reference(req); |
1550 | } else { | |
666796da | 1551 | for (i = 0; i < I915_NUM_ENGINES; i++) { |
b4716185 CW |
1552 | struct drm_i915_gem_request *req; |
1553 | ||
1554 | req = obj->last_read_req[i]; | |
1555 | if (req == NULL) | |
1556 | continue; | |
1557 | ||
b4716185 CW |
1558 | requests[n++] = i915_gem_request_reference(req); |
1559 | } | |
1560 | } | |
1561 | ||
3236f57a | 1562 | mutex_unlock(&dev->struct_mutex); |
299259a3 | 1563 | ret = 0; |
b4716185 | 1564 | for (i = 0; ret == 0 && i < n; i++) |
299259a3 | 1565 | ret = __i915_wait_request(requests[i], true, NULL, rps); |
3236f57a CW |
1566 | mutex_lock(&dev->struct_mutex); |
1567 | ||
b4716185 CW |
1568 | for (i = 0; i < n; i++) { |
1569 | if (ret == 0) | |
1570 | i915_gem_object_retire_request(obj, requests[i]); | |
1571 | i915_gem_request_unreference(requests[i]); | |
1572 | } | |
1573 | ||
1574 | return ret; | |
3236f57a CW |
1575 | } |
1576 | ||
2e1b8730 CW |
1577 | static struct intel_rps_client *to_rps_client(struct drm_file *file) |
1578 | { | |
1579 | struct drm_i915_file_private *fpriv = file->driver_priv; | |
1580 | return &fpriv->rps; | |
1581 | } | |
1582 | ||
673a394b | 1583 | /** |
2ef7eeaa EA |
1584 | * Called when user space prepares to use an object with the CPU, either |
1585 | * through the mmap ioctl's mapping or a GTT mapping. | |
673a394b EA |
1586 | */ |
1587 | int | |
1588 | i915_gem_set_domain_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 1589 | struct drm_file *file) |
673a394b EA |
1590 | { |
1591 | struct drm_i915_gem_set_domain *args = data; | |
05394f39 | 1592 | struct drm_i915_gem_object *obj; |
2ef7eeaa EA |
1593 | uint32_t read_domains = args->read_domains; |
1594 | uint32_t write_domain = args->write_domain; | |
673a394b EA |
1595 | int ret; |
1596 | ||
2ef7eeaa | 1597 | /* Only handle setting domains to types used by the CPU. */ |
21d509e3 | 1598 | if (write_domain & I915_GEM_GPU_DOMAINS) |
2ef7eeaa EA |
1599 | return -EINVAL; |
1600 | ||
21d509e3 | 1601 | if (read_domains & I915_GEM_GPU_DOMAINS) |
2ef7eeaa EA |
1602 | return -EINVAL; |
1603 | ||
1604 | /* Having something in the write domain implies it's in the read | |
1605 | * domain, and only that read domain. Enforce that in the request. | |
1606 | */ | |
1607 | if (write_domain != 0 && read_domains != write_domain) | |
1608 | return -EINVAL; | |
1609 | ||
76c1dec1 | 1610 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 1611 | if (ret) |
76c1dec1 | 1612 | return ret; |
1d7cfea1 | 1613 | |
05394f39 | 1614 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 1615 | if (&obj->base == NULL) { |
1d7cfea1 CW |
1616 | ret = -ENOENT; |
1617 | goto unlock; | |
76c1dec1 | 1618 | } |
673a394b | 1619 | |
3236f57a CW |
1620 | /* Try to flush the object off the GPU without holding the lock. |
1621 | * We will repeat the flush holding the lock in the normal manner | |
1622 | * to catch cases where we are gazumped. | |
1623 | */ | |
6e4930f6 | 1624 | ret = i915_gem_object_wait_rendering__nonblocking(obj, |
2e1b8730 | 1625 | to_rps_client(file), |
6e4930f6 | 1626 | !write_domain); |
3236f57a CW |
1627 | if (ret) |
1628 | goto unref; | |
1629 | ||
43566ded | 1630 | if (read_domains & I915_GEM_DOMAIN_GTT) |
2ef7eeaa | 1631 | ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0); |
43566ded | 1632 | else |
e47c68e9 | 1633 | ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0); |
2ef7eeaa | 1634 | |
031b698a DV |
1635 | if (write_domain != 0) |
1636 | intel_fb_obj_invalidate(obj, | |
1637 | write_domain == I915_GEM_DOMAIN_GTT ? | |
1638 | ORIGIN_GTT : ORIGIN_CPU); | |
1639 | ||
3236f57a | 1640 | unref: |
05394f39 | 1641 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 1642 | unlock: |
673a394b EA |
1643 | mutex_unlock(&dev->struct_mutex); |
1644 | return ret; | |
1645 | } | |
1646 | ||
1647 | /** | |
1648 | * Called when user space has done writes to this buffer | |
1649 | */ | |
1650 | int | |
1651 | i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 1652 | struct drm_file *file) |
673a394b EA |
1653 | { |
1654 | struct drm_i915_gem_sw_finish *args = data; | |
05394f39 | 1655 | struct drm_i915_gem_object *obj; |
673a394b EA |
1656 | int ret = 0; |
1657 | ||
76c1dec1 | 1658 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 1659 | if (ret) |
76c1dec1 | 1660 | return ret; |
1d7cfea1 | 1661 | |
05394f39 | 1662 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 1663 | if (&obj->base == NULL) { |
1d7cfea1 CW |
1664 | ret = -ENOENT; |
1665 | goto unlock; | |
673a394b EA |
1666 | } |
1667 | ||
673a394b | 1668 | /* Pinned buffers may be scanout, so flush the cache */ |
2c22569b | 1669 | if (obj->pin_display) |
e62b59e4 | 1670 | i915_gem_object_flush_cpu_write_domain(obj); |
e47c68e9 | 1671 | |
05394f39 | 1672 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 1673 | unlock: |
673a394b EA |
1674 | mutex_unlock(&dev->struct_mutex); |
1675 | return ret; | |
1676 | } | |
1677 | ||
1678 | /** | |
1679 | * Maps the contents of an object, returning the address it is mapped | |
1680 | * into. | |
1681 | * | |
1682 | * While the mapping holds a reference on the contents of the object, it doesn't | |
1683 | * imply a ref on the object itself. | |
34367381 DV |
1684 | * |
1685 | * IMPORTANT: | |
1686 | * | |
1687 | * DRM driver writers who look a this function as an example for how to do GEM | |
1688 | * mmap support, please don't implement mmap support like here. The modern way | |
1689 | * to implement DRM mmap support is with an mmap offset ioctl (like | |
1690 | * i915_gem_mmap_gtt) and then using the mmap syscall on the DRM fd directly. | |
1691 | * That way debug tooling like valgrind will understand what's going on, hiding | |
1692 | * the mmap call in a driver private ioctl will break that. The i915 driver only | |
1693 | * does cpu mmaps this way because we didn't know better. | |
673a394b EA |
1694 | */ |
1695 | int | |
1696 | i915_gem_mmap_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 1697 | struct drm_file *file) |
673a394b EA |
1698 | { |
1699 | struct drm_i915_gem_mmap *args = data; | |
1700 | struct drm_gem_object *obj; | |
673a394b EA |
1701 | unsigned long addr; |
1702 | ||
1816f923 AG |
1703 | if (args->flags & ~(I915_MMAP_WC)) |
1704 | return -EINVAL; | |
1705 | ||
1706 | if (args->flags & I915_MMAP_WC && !cpu_has_pat) | |
1707 | return -ENODEV; | |
1708 | ||
05394f39 | 1709 | obj = drm_gem_object_lookup(dev, file, args->handle); |
673a394b | 1710 | if (obj == NULL) |
bf79cb91 | 1711 | return -ENOENT; |
673a394b | 1712 | |
1286ff73 DV |
1713 | /* prime objects have no backing filp to GEM mmap |
1714 | * pages from. | |
1715 | */ | |
1716 | if (!obj->filp) { | |
1717 | drm_gem_object_unreference_unlocked(obj); | |
1718 | return -EINVAL; | |
1719 | } | |
1720 | ||
6be5ceb0 | 1721 | addr = vm_mmap(obj->filp, 0, args->size, |
673a394b EA |
1722 | PROT_READ | PROT_WRITE, MAP_SHARED, |
1723 | args->offset); | |
1816f923 AG |
1724 | if (args->flags & I915_MMAP_WC) { |
1725 | struct mm_struct *mm = current->mm; | |
1726 | struct vm_area_struct *vma; | |
1727 | ||
1728 | down_write(&mm->mmap_sem); | |
1729 | vma = find_vma(mm, addr); | |
1730 | if (vma) | |
1731 | vma->vm_page_prot = | |
1732 | pgprot_writecombine(vm_get_page_prot(vma->vm_flags)); | |
1733 | else | |
1734 | addr = -ENOMEM; | |
1735 | up_write(&mm->mmap_sem); | |
1736 | } | |
bc9025bd | 1737 | drm_gem_object_unreference_unlocked(obj); |
673a394b EA |
1738 | if (IS_ERR((void *)addr)) |
1739 | return addr; | |
1740 | ||
1741 | args->addr_ptr = (uint64_t) addr; | |
1742 | ||
1743 | return 0; | |
1744 | } | |
1745 | ||
de151cf6 JB |
1746 | /** |
1747 | * i915_gem_fault - fault a page into the GTT | |
d9072a3e GT |
1748 | * @vma: VMA in question |
1749 | * @vmf: fault info | |
de151cf6 JB |
1750 | * |
1751 | * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped | |
1752 | * from userspace. The fault handler takes care of binding the object to | |
1753 | * the GTT (if needed), allocating and programming a fence register (again, | |
1754 | * only if needed based on whether the old reg is still valid or the object | |
1755 | * is tiled) and inserting a new PTE into the faulting process. | |
1756 | * | |
1757 | * Note that the faulting process may involve evicting existing objects | |
1758 | * from the GTT and/or fence registers to make room. So performance may | |
1759 | * suffer if the GTT working set is large or there are few fence registers | |
1760 | * left. | |
1761 | */ | |
1762 | int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf) | |
1763 | { | |
05394f39 CW |
1764 | struct drm_i915_gem_object *obj = to_intel_bo(vma->vm_private_data); |
1765 | struct drm_device *dev = obj->base.dev; | |
72e96d64 JL |
1766 | struct drm_i915_private *dev_priv = to_i915(dev); |
1767 | struct i915_ggtt *ggtt = &dev_priv->ggtt; | |
c5ad54cf | 1768 | struct i915_ggtt_view view = i915_ggtt_view_normal; |
de151cf6 JB |
1769 | pgoff_t page_offset; |
1770 | unsigned long pfn; | |
1771 | int ret = 0; | |
0f973f27 | 1772 | bool write = !!(vmf->flags & FAULT_FLAG_WRITE); |
de151cf6 | 1773 | |
f65c9168 PZ |
1774 | intel_runtime_pm_get(dev_priv); |
1775 | ||
de151cf6 JB |
1776 | /* We don't use vmf->pgoff since that has the fake offset */ |
1777 | page_offset = ((unsigned long)vmf->virtual_address - vma->vm_start) >> | |
1778 | PAGE_SHIFT; | |
1779 | ||
d9bc7e9f CW |
1780 | ret = i915_mutex_lock_interruptible(dev); |
1781 | if (ret) | |
1782 | goto out; | |
a00b10c3 | 1783 | |
db53a302 CW |
1784 | trace_i915_gem_object_fault(obj, page_offset, true, write); |
1785 | ||
6e4930f6 CW |
1786 | /* Try to flush the object off the GPU first without holding the lock. |
1787 | * Upon reacquiring the lock, we will perform our sanity checks and then | |
1788 | * repeat the flush holding the lock in the normal manner to catch cases | |
1789 | * where we are gazumped. | |
1790 | */ | |
1791 | ret = i915_gem_object_wait_rendering__nonblocking(obj, NULL, !write); | |
1792 | if (ret) | |
1793 | goto unlock; | |
1794 | ||
eb119bd6 CW |
1795 | /* Access to snoopable pages through the GTT is incoherent. */ |
1796 | if (obj->cache_level != I915_CACHE_NONE && !HAS_LLC(dev)) { | |
ddeff6ee | 1797 | ret = -EFAULT; |
eb119bd6 CW |
1798 | goto unlock; |
1799 | } | |
1800 | ||
c5ad54cf | 1801 | /* Use a partial view if the object is bigger than the aperture. */ |
72e96d64 | 1802 | if (obj->base.size >= ggtt->mappable_end && |
e7ded2d7 | 1803 | obj->tiling_mode == I915_TILING_NONE) { |
c5ad54cf | 1804 | static const unsigned int chunk_size = 256; // 1 MiB |
e7ded2d7 | 1805 | |
c5ad54cf JL |
1806 | memset(&view, 0, sizeof(view)); |
1807 | view.type = I915_GGTT_VIEW_PARTIAL; | |
1808 | view.params.partial.offset = rounddown(page_offset, chunk_size); | |
1809 | view.params.partial.size = | |
1810 | min_t(unsigned int, | |
1811 | chunk_size, | |
1812 | (vma->vm_end - vma->vm_start)/PAGE_SIZE - | |
1813 | view.params.partial.offset); | |
1814 | } | |
1815 | ||
1816 | /* Now pin it into the GTT if needed */ | |
1817 | ret = i915_gem_object_ggtt_pin(obj, &view, 0, PIN_MAPPABLE); | |
c9839303 CW |
1818 | if (ret) |
1819 | goto unlock; | |
4a684a41 | 1820 | |
c9839303 CW |
1821 | ret = i915_gem_object_set_to_gtt_domain(obj, write); |
1822 | if (ret) | |
1823 | goto unpin; | |
74898d7e | 1824 | |
06d98131 | 1825 | ret = i915_gem_object_get_fence(obj); |
d9e86c0e | 1826 | if (ret) |
c9839303 | 1827 | goto unpin; |
7d1c4804 | 1828 | |
b90b91d8 | 1829 | /* Finally, remap it using the new GTT offset */ |
72e96d64 | 1830 | pfn = ggtt->mappable_base + |
c5ad54cf | 1831 | i915_gem_obj_ggtt_offset_view(obj, &view); |
f343c5f6 | 1832 | pfn >>= PAGE_SHIFT; |
de151cf6 | 1833 | |
c5ad54cf JL |
1834 | if (unlikely(view.type == I915_GGTT_VIEW_PARTIAL)) { |
1835 | /* Overriding existing pages in partial view does not cause | |
1836 | * us any trouble as TLBs are still valid because the fault | |
1837 | * is due to userspace losing part of the mapping or never | |
1838 | * having accessed it before (at this partials' range). | |
1839 | */ | |
1840 | unsigned long base = vma->vm_start + | |
1841 | (view.params.partial.offset << PAGE_SHIFT); | |
1842 | unsigned int i; | |
b90b91d8 | 1843 | |
c5ad54cf JL |
1844 | for (i = 0; i < view.params.partial.size; i++) { |
1845 | ret = vm_insert_pfn(vma, base + i * PAGE_SIZE, pfn + i); | |
b90b91d8 CW |
1846 | if (ret) |
1847 | break; | |
1848 | } | |
1849 | ||
1850 | obj->fault_mappable = true; | |
c5ad54cf JL |
1851 | } else { |
1852 | if (!obj->fault_mappable) { | |
1853 | unsigned long size = min_t(unsigned long, | |
1854 | vma->vm_end - vma->vm_start, | |
1855 | obj->base.size); | |
1856 | int i; | |
1857 | ||
1858 | for (i = 0; i < size >> PAGE_SHIFT; i++) { | |
1859 | ret = vm_insert_pfn(vma, | |
1860 | (unsigned long)vma->vm_start + i * PAGE_SIZE, | |
1861 | pfn + i); | |
1862 | if (ret) | |
1863 | break; | |
1864 | } | |
1865 | ||
1866 | obj->fault_mappable = true; | |
1867 | } else | |
1868 | ret = vm_insert_pfn(vma, | |
1869 | (unsigned long)vmf->virtual_address, | |
1870 | pfn + page_offset); | |
1871 | } | |
c9839303 | 1872 | unpin: |
c5ad54cf | 1873 | i915_gem_object_ggtt_unpin_view(obj, &view); |
c715089f | 1874 | unlock: |
de151cf6 | 1875 | mutex_unlock(&dev->struct_mutex); |
d9bc7e9f | 1876 | out: |
de151cf6 | 1877 | switch (ret) { |
d9bc7e9f | 1878 | case -EIO: |
2232f031 DV |
1879 | /* |
1880 | * We eat errors when the gpu is terminally wedged to avoid | |
1881 | * userspace unduly crashing (gl has no provisions for mmaps to | |
1882 | * fail). But any other -EIO isn't ours (e.g. swap in failure) | |
1883 | * and so needs to be reported. | |
1884 | */ | |
1885 | if (!i915_terminally_wedged(&dev_priv->gpu_error)) { | |
f65c9168 PZ |
1886 | ret = VM_FAULT_SIGBUS; |
1887 | break; | |
1888 | } | |
045e769a | 1889 | case -EAGAIN: |
571c608d DV |
1890 | /* |
1891 | * EAGAIN means the gpu is hung and we'll wait for the error | |
1892 | * handler to reset everything when re-faulting in | |
1893 | * i915_mutex_lock_interruptible. | |
d9bc7e9f | 1894 | */ |
c715089f CW |
1895 | case 0: |
1896 | case -ERESTARTSYS: | |
bed636ab | 1897 | case -EINTR: |
e79e0fe3 DR |
1898 | case -EBUSY: |
1899 | /* | |
1900 | * EBUSY is ok: this just means that another thread | |
1901 | * already did the job. | |
1902 | */ | |
f65c9168 PZ |
1903 | ret = VM_FAULT_NOPAGE; |
1904 | break; | |
de151cf6 | 1905 | case -ENOMEM: |
f65c9168 PZ |
1906 | ret = VM_FAULT_OOM; |
1907 | break; | |
a7c2e1aa | 1908 | case -ENOSPC: |
45d67817 | 1909 | case -EFAULT: |
f65c9168 PZ |
1910 | ret = VM_FAULT_SIGBUS; |
1911 | break; | |
de151cf6 | 1912 | default: |
a7c2e1aa | 1913 | WARN_ONCE(ret, "unhandled error in i915_gem_fault: %i\n", ret); |
f65c9168 PZ |
1914 | ret = VM_FAULT_SIGBUS; |
1915 | break; | |
de151cf6 | 1916 | } |
f65c9168 PZ |
1917 | |
1918 | intel_runtime_pm_put(dev_priv); | |
1919 | return ret; | |
de151cf6 JB |
1920 | } |
1921 | ||
901782b2 CW |
1922 | /** |
1923 | * i915_gem_release_mmap - remove physical page mappings | |
1924 | * @obj: obj in question | |
1925 | * | |
af901ca1 | 1926 | * Preserve the reservation of the mmapping with the DRM core code, but |
901782b2 CW |
1927 | * relinquish ownership of the pages back to the system. |
1928 | * | |
1929 | * It is vital that we remove the page mapping if we have mapped a tiled | |
1930 | * object through the GTT and then lose the fence register due to | |
1931 | * resource pressure. Similarly if the object has been moved out of the | |
1932 | * aperture, than pages mapped into userspace must be revoked. Removing the | |
1933 | * mapping will then trigger a page fault on the next user access, allowing | |
1934 | * fixup by i915_gem_fault(). | |
1935 | */ | |
d05ca301 | 1936 | void |
05394f39 | 1937 | i915_gem_release_mmap(struct drm_i915_gem_object *obj) |
901782b2 | 1938 | { |
349f2ccf CW |
1939 | /* Serialisation between user GTT access and our code depends upon |
1940 | * revoking the CPU's PTE whilst the mutex is held. The next user | |
1941 | * pagefault then has to wait until we release the mutex. | |
1942 | */ | |
1943 | lockdep_assert_held(&obj->base.dev->struct_mutex); | |
1944 | ||
6299f992 CW |
1945 | if (!obj->fault_mappable) |
1946 | return; | |
901782b2 | 1947 | |
6796cb16 DH |
1948 | drm_vma_node_unmap(&obj->base.vma_node, |
1949 | obj->base.dev->anon_inode->i_mapping); | |
349f2ccf CW |
1950 | |
1951 | /* Ensure that the CPU's PTE are revoked and there are not outstanding | |
1952 | * memory transactions from userspace before we return. The TLB | |
1953 | * flushing implied above by changing the PTE above *should* be | |
1954 | * sufficient, an extra barrier here just provides us with a bit | |
1955 | * of paranoid documentation about our requirement to serialise | |
1956 | * memory writes before touching registers / GSM. | |
1957 | */ | |
1958 | wmb(); | |
1959 | ||
6299f992 | 1960 | obj->fault_mappable = false; |
901782b2 CW |
1961 | } |
1962 | ||
eedd10f4 CW |
1963 | void |
1964 | i915_gem_release_all_mmaps(struct drm_i915_private *dev_priv) | |
1965 | { | |
1966 | struct drm_i915_gem_object *obj; | |
1967 | ||
1968 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) | |
1969 | i915_gem_release_mmap(obj); | |
1970 | } | |
1971 | ||
0fa87796 | 1972 | uint32_t |
e28f8711 | 1973 | i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode) |
92b88aeb | 1974 | { |
e28f8711 | 1975 | uint32_t gtt_size; |
92b88aeb CW |
1976 | |
1977 | if (INTEL_INFO(dev)->gen >= 4 || | |
e28f8711 CW |
1978 | tiling_mode == I915_TILING_NONE) |
1979 | return size; | |
92b88aeb CW |
1980 | |
1981 | /* Previous chips need a power-of-two fence region when tiling */ | |
1982 | if (INTEL_INFO(dev)->gen == 3) | |
e28f8711 | 1983 | gtt_size = 1024*1024; |
92b88aeb | 1984 | else |
e28f8711 | 1985 | gtt_size = 512*1024; |
92b88aeb | 1986 | |
e28f8711 CW |
1987 | while (gtt_size < size) |
1988 | gtt_size <<= 1; | |
92b88aeb | 1989 | |
e28f8711 | 1990 | return gtt_size; |
92b88aeb CW |
1991 | } |
1992 | ||
de151cf6 JB |
1993 | /** |
1994 | * i915_gem_get_gtt_alignment - return required GTT alignment for an object | |
1995 | * @obj: object to check | |
1996 | * | |
1997 | * Return the required GTT alignment for an object, taking into account | |
5e783301 | 1998 | * potential fence register mapping. |
de151cf6 | 1999 | */ |
d865110c ID |
2000 | uint32_t |
2001 | i915_gem_get_gtt_alignment(struct drm_device *dev, uint32_t size, | |
2002 | int tiling_mode, bool fenced) | |
de151cf6 | 2003 | { |
de151cf6 JB |
2004 | /* |
2005 | * Minimum alignment is 4k (GTT page size), but might be greater | |
2006 | * if a fence register is needed for the object. | |
2007 | */ | |
d865110c | 2008 | if (INTEL_INFO(dev)->gen >= 4 || (!fenced && IS_G33(dev)) || |
e28f8711 | 2009 | tiling_mode == I915_TILING_NONE) |
de151cf6 JB |
2010 | return 4096; |
2011 | ||
a00b10c3 CW |
2012 | /* |
2013 | * Previous chips need to be aligned to the size of the smallest | |
2014 | * fence register that can contain the object. | |
2015 | */ | |
e28f8711 | 2016 | return i915_gem_get_gtt_size(dev, size, tiling_mode); |
a00b10c3 CW |
2017 | } |
2018 | ||
d8cb5086 CW |
2019 | static int i915_gem_object_create_mmap_offset(struct drm_i915_gem_object *obj) |
2020 | { | |
2021 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; | |
2022 | int ret; | |
2023 | ||
0de23977 | 2024 | if (drm_vma_node_has_offset(&obj->base.vma_node)) |
d8cb5086 CW |
2025 | return 0; |
2026 | ||
da494d7c DV |
2027 | dev_priv->mm.shrinker_no_lock_stealing = true; |
2028 | ||
d8cb5086 CW |
2029 | ret = drm_gem_create_mmap_offset(&obj->base); |
2030 | if (ret != -ENOSPC) | |
da494d7c | 2031 | goto out; |
d8cb5086 CW |
2032 | |
2033 | /* Badly fragmented mmap space? The only way we can recover | |
2034 | * space is by destroying unwanted objects. We can't randomly release | |
2035 | * mmap_offsets as userspace expects them to be persistent for the | |
2036 | * lifetime of the objects. The closest we can is to release the | |
2037 | * offsets on purgeable objects by truncating it and marking it purged, | |
2038 | * which prevents userspace from ever using that object again. | |
2039 | */ | |
21ab4e74 CW |
2040 | i915_gem_shrink(dev_priv, |
2041 | obj->base.size >> PAGE_SHIFT, | |
2042 | I915_SHRINK_BOUND | | |
2043 | I915_SHRINK_UNBOUND | | |
2044 | I915_SHRINK_PURGEABLE); | |
d8cb5086 CW |
2045 | ret = drm_gem_create_mmap_offset(&obj->base); |
2046 | if (ret != -ENOSPC) | |
da494d7c | 2047 | goto out; |
d8cb5086 CW |
2048 | |
2049 | i915_gem_shrink_all(dev_priv); | |
da494d7c DV |
2050 | ret = drm_gem_create_mmap_offset(&obj->base); |
2051 | out: | |
2052 | dev_priv->mm.shrinker_no_lock_stealing = false; | |
2053 | ||
2054 | return ret; | |
d8cb5086 CW |
2055 | } |
2056 | ||
2057 | static void i915_gem_object_free_mmap_offset(struct drm_i915_gem_object *obj) | |
2058 | { | |
d8cb5086 CW |
2059 | drm_gem_free_mmap_offset(&obj->base); |
2060 | } | |
2061 | ||
da6b51d0 | 2062 | int |
ff72145b DA |
2063 | i915_gem_mmap_gtt(struct drm_file *file, |
2064 | struct drm_device *dev, | |
da6b51d0 | 2065 | uint32_t handle, |
ff72145b | 2066 | uint64_t *offset) |
de151cf6 | 2067 | { |
05394f39 | 2068 | struct drm_i915_gem_object *obj; |
de151cf6 JB |
2069 | int ret; |
2070 | ||
76c1dec1 | 2071 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 2072 | if (ret) |
76c1dec1 | 2073 | return ret; |
de151cf6 | 2074 | |
ff72145b | 2075 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle)); |
c8725226 | 2076 | if (&obj->base == NULL) { |
1d7cfea1 CW |
2077 | ret = -ENOENT; |
2078 | goto unlock; | |
2079 | } | |
de151cf6 | 2080 | |
05394f39 | 2081 | if (obj->madv != I915_MADV_WILLNEED) { |
bd9b6a4e | 2082 | DRM_DEBUG("Attempting to mmap a purgeable buffer\n"); |
8c99e57d | 2083 | ret = -EFAULT; |
1d7cfea1 | 2084 | goto out; |
ab18282d CW |
2085 | } |
2086 | ||
d8cb5086 CW |
2087 | ret = i915_gem_object_create_mmap_offset(obj); |
2088 | if (ret) | |
2089 | goto out; | |
de151cf6 | 2090 | |
0de23977 | 2091 | *offset = drm_vma_node_offset_addr(&obj->base.vma_node); |
de151cf6 | 2092 | |
1d7cfea1 | 2093 | out: |
05394f39 | 2094 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 2095 | unlock: |
de151cf6 | 2096 | mutex_unlock(&dev->struct_mutex); |
1d7cfea1 | 2097 | return ret; |
de151cf6 JB |
2098 | } |
2099 | ||
ff72145b DA |
2100 | /** |
2101 | * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing | |
2102 | * @dev: DRM device | |
2103 | * @data: GTT mapping ioctl data | |
2104 | * @file: GEM object info | |
2105 | * | |
2106 | * Simply returns the fake offset to userspace so it can mmap it. | |
2107 | * The mmap call will end up in drm_gem_mmap(), which will set things | |
2108 | * up so we can get faults in the handler above. | |
2109 | * | |
2110 | * The fault handler will take care of binding the object into the GTT | |
2111 | * (since it may have been evicted to make room for something), allocating | |
2112 | * a fence register, and mapping the appropriate aperture address into | |
2113 | * userspace. | |
2114 | */ | |
2115 | int | |
2116 | i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data, | |
2117 | struct drm_file *file) | |
2118 | { | |
2119 | struct drm_i915_gem_mmap_gtt *args = data; | |
2120 | ||
da6b51d0 | 2121 | return i915_gem_mmap_gtt(file, dev, args->handle, &args->offset); |
ff72145b DA |
2122 | } |
2123 | ||
225067ee DV |
2124 | /* Immediately discard the backing storage */ |
2125 | static void | |
2126 | i915_gem_object_truncate(struct drm_i915_gem_object *obj) | |
e5281ccd | 2127 | { |
4d6294bf | 2128 | i915_gem_object_free_mmap_offset(obj); |
1286ff73 | 2129 | |
4d6294bf CW |
2130 | if (obj->base.filp == NULL) |
2131 | return; | |
e5281ccd | 2132 | |
225067ee DV |
2133 | /* Our goal here is to return as much of the memory as |
2134 | * is possible back to the system as we are called from OOM. | |
2135 | * To do this we must instruct the shmfs to drop all of its | |
2136 | * backing pages, *now*. | |
2137 | */ | |
5537252b | 2138 | shmem_truncate_range(file_inode(obj->base.filp), 0, (loff_t)-1); |
225067ee DV |
2139 | obj->madv = __I915_MADV_PURGED; |
2140 | } | |
e5281ccd | 2141 | |
5537252b CW |
2142 | /* Try to discard unwanted pages */ |
2143 | static void | |
2144 | i915_gem_object_invalidate(struct drm_i915_gem_object *obj) | |
225067ee | 2145 | { |
5537252b CW |
2146 | struct address_space *mapping; |
2147 | ||
2148 | switch (obj->madv) { | |
2149 | case I915_MADV_DONTNEED: | |
2150 | i915_gem_object_truncate(obj); | |
2151 | case __I915_MADV_PURGED: | |
2152 | return; | |
2153 | } | |
2154 | ||
2155 | if (obj->base.filp == NULL) | |
2156 | return; | |
2157 | ||
2158 | mapping = file_inode(obj->base.filp)->i_mapping, | |
2159 | invalidate_mapping_pages(mapping, 0, (loff_t)-1); | |
e5281ccd CW |
2160 | } |
2161 | ||
5cdf5881 | 2162 | static void |
05394f39 | 2163 | i915_gem_object_put_pages_gtt(struct drm_i915_gem_object *obj) |
673a394b | 2164 | { |
90797e6d ID |
2165 | struct sg_page_iter sg_iter; |
2166 | int ret; | |
1286ff73 | 2167 | |
05394f39 | 2168 | BUG_ON(obj->madv == __I915_MADV_PURGED); |
673a394b | 2169 | |
6c085a72 | 2170 | ret = i915_gem_object_set_to_cpu_domain(obj, true); |
f4457ae7 | 2171 | if (WARN_ON(ret)) { |
6c085a72 CW |
2172 | /* In the event of a disaster, abandon all caches and |
2173 | * hope for the best. | |
2174 | */ | |
2c22569b | 2175 | i915_gem_clflush_object(obj, true); |
6c085a72 CW |
2176 | obj->base.read_domains = obj->base.write_domain = I915_GEM_DOMAIN_CPU; |
2177 | } | |
2178 | ||
e2273302 ID |
2179 | i915_gem_gtt_finish_object(obj); |
2180 | ||
6dacfd2f | 2181 | if (i915_gem_object_needs_bit17_swizzle(obj)) |
280b713b EA |
2182 | i915_gem_object_save_bit_17_swizzle(obj); |
2183 | ||
05394f39 CW |
2184 | if (obj->madv == I915_MADV_DONTNEED) |
2185 | obj->dirty = 0; | |
3ef94daa | 2186 | |
90797e6d | 2187 | for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, 0) { |
2db76d7c | 2188 | struct page *page = sg_page_iter_page(&sg_iter); |
9da3da66 | 2189 | |
05394f39 | 2190 | if (obj->dirty) |
9da3da66 | 2191 | set_page_dirty(page); |
3ef94daa | 2192 | |
05394f39 | 2193 | if (obj->madv == I915_MADV_WILLNEED) |
9da3da66 | 2194 | mark_page_accessed(page); |
3ef94daa | 2195 | |
09cbfeaf | 2196 | put_page(page); |
3ef94daa | 2197 | } |
05394f39 | 2198 | obj->dirty = 0; |
673a394b | 2199 | |
9da3da66 CW |
2200 | sg_free_table(obj->pages); |
2201 | kfree(obj->pages); | |
37e680a1 | 2202 | } |
6c085a72 | 2203 | |
dd624afd | 2204 | int |
37e680a1 CW |
2205 | i915_gem_object_put_pages(struct drm_i915_gem_object *obj) |
2206 | { | |
2207 | const struct drm_i915_gem_object_ops *ops = obj->ops; | |
2208 | ||
2f745ad3 | 2209 | if (obj->pages == NULL) |
37e680a1 CW |
2210 | return 0; |
2211 | ||
a5570178 CW |
2212 | if (obj->pages_pin_count) |
2213 | return -EBUSY; | |
2214 | ||
9843877d | 2215 | BUG_ON(i915_gem_obj_bound_any(obj)); |
3e123027 | 2216 | |
a2165e31 CW |
2217 | /* ->put_pages might need to allocate memory for the bit17 swizzle |
2218 | * array, hence protect them from being reaped by removing them from gtt | |
2219 | * lists early. */ | |
35c20a60 | 2220 | list_del(&obj->global_list); |
a2165e31 | 2221 | |
0a798eb9 | 2222 | if (obj->mapping) { |
fb8621d3 CW |
2223 | if (is_vmalloc_addr(obj->mapping)) |
2224 | vunmap(obj->mapping); | |
2225 | else | |
2226 | kunmap(kmap_to_page(obj->mapping)); | |
0a798eb9 CW |
2227 | obj->mapping = NULL; |
2228 | } | |
2229 | ||
37e680a1 | 2230 | ops->put_pages(obj); |
05394f39 | 2231 | obj->pages = NULL; |
37e680a1 | 2232 | |
5537252b | 2233 | i915_gem_object_invalidate(obj); |
6c085a72 CW |
2234 | |
2235 | return 0; | |
2236 | } | |
2237 | ||
37e680a1 | 2238 | static int |
6c085a72 | 2239 | i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj) |
e5281ccd | 2240 | { |
6c085a72 | 2241 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
e5281ccd CW |
2242 | int page_count, i; |
2243 | struct address_space *mapping; | |
9da3da66 CW |
2244 | struct sg_table *st; |
2245 | struct scatterlist *sg; | |
90797e6d | 2246 | struct sg_page_iter sg_iter; |
e5281ccd | 2247 | struct page *page; |
90797e6d | 2248 | unsigned long last_pfn = 0; /* suppress gcc warning */ |
e2273302 | 2249 | int ret; |
6c085a72 | 2250 | gfp_t gfp; |
e5281ccd | 2251 | |
6c085a72 CW |
2252 | /* Assert that the object is not currently in any GPU domain. As it |
2253 | * wasn't in the GTT, there shouldn't be any way it could have been in | |
2254 | * a GPU cache | |
2255 | */ | |
2256 | BUG_ON(obj->base.read_domains & I915_GEM_GPU_DOMAINS); | |
2257 | BUG_ON(obj->base.write_domain & I915_GEM_GPU_DOMAINS); | |
2258 | ||
9da3da66 CW |
2259 | st = kmalloc(sizeof(*st), GFP_KERNEL); |
2260 | if (st == NULL) | |
2261 | return -ENOMEM; | |
2262 | ||
05394f39 | 2263 | page_count = obj->base.size / PAGE_SIZE; |
9da3da66 | 2264 | if (sg_alloc_table(st, page_count, GFP_KERNEL)) { |
9da3da66 | 2265 | kfree(st); |
e5281ccd | 2266 | return -ENOMEM; |
9da3da66 | 2267 | } |
e5281ccd | 2268 | |
9da3da66 CW |
2269 | /* Get the list of pages out of our struct file. They'll be pinned |
2270 | * at this point until we release them. | |
2271 | * | |
2272 | * Fail silently without starting the shrinker | |
2273 | */ | |
496ad9aa | 2274 | mapping = file_inode(obj->base.filp)->i_mapping; |
c62d2555 | 2275 | gfp = mapping_gfp_constraint(mapping, ~(__GFP_IO | __GFP_RECLAIM)); |
d0164adc | 2276 | gfp |= __GFP_NORETRY | __GFP_NOWARN; |
90797e6d ID |
2277 | sg = st->sgl; |
2278 | st->nents = 0; | |
2279 | for (i = 0; i < page_count; i++) { | |
6c085a72 CW |
2280 | page = shmem_read_mapping_page_gfp(mapping, i, gfp); |
2281 | if (IS_ERR(page)) { | |
21ab4e74 CW |
2282 | i915_gem_shrink(dev_priv, |
2283 | page_count, | |
2284 | I915_SHRINK_BOUND | | |
2285 | I915_SHRINK_UNBOUND | | |
2286 | I915_SHRINK_PURGEABLE); | |
6c085a72 CW |
2287 | page = shmem_read_mapping_page_gfp(mapping, i, gfp); |
2288 | } | |
2289 | if (IS_ERR(page)) { | |
2290 | /* We've tried hard to allocate the memory by reaping | |
2291 | * our own buffer, now let the real VM do its job and | |
2292 | * go down in flames if truly OOM. | |
2293 | */ | |
6c085a72 | 2294 | i915_gem_shrink_all(dev_priv); |
f461d1be | 2295 | page = shmem_read_mapping_page(mapping, i); |
e2273302 ID |
2296 | if (IS_ERR(page)) { |
2297 | ret = PTR_ERR(page); | |
6c085a72 | 2298 | goto err_pages; |
e2273302 | 2299 | } |
6c085a72 | 2300 | } |
426729dc KRW |
2301 | #ifdef CONFIG_SWIOTLB |
2302 | if (swiotlb_nr_tbl()) { | |
2303 | st->nents++; | |
2304 | sg_set_page(sg, page, PAGE_SIZE, 0); | |
2305 | sg = sg_next(sg); | |
2306 | continue; | |
2307 | } | |
2308 | #endif | |
90797e6d ID |
2309 | if (!i || page_to_pfn(page) != last_pfn + 1) { |
2310 | if (i) | |
2311 | sg = sg_next(sg); | |
2312 | st->nents++; | |
2313 | sg_set_page(sg, page, PAGE_SIZE, 0); | |
2314 | } else { | |
2315 | sg->length += PAGE_SIZE; | |
2316 | } | |
2317 | last_pfn = page_to_pfn(page); | |
3bbbe706 DV |
2318 | |
2319 | /* Check that the i965g/gm workaround works. */ | |
2320 | WARN_ON((gfp & __GFP_DMA32) && (last_pfn >= 0x00100000UL)); | |
e5281ccd | 2321 | } |
426729dc KRW |
2322 | #ifdef CONFIG_SWIOTLB |
2323 | if (!swiotlb_nr_tbl()) | |
2324 | #endif | |
2325 | sg_mark_end(sg); | |
74ce6b6c CW |
2326 | obj->pages = st; |
2327 | ||
e2273302 ID |
2328 | ret = i915_gem_gtt_prepare_object(obj); |
2329 | if (ret) | |
2330 | goto err_pages; | |
2331 | ||
6dacfd2f | 2332 | if (i915_gem_object_needs_bit17_swizzle(obj)) |
e5281ccd CW |
2333 | i915_gem_object_do_bit_17_swizzle(obj); |
2334 | ||
656bfa3a DV |
2335 | if (obj->tiling_mode != I915_TILING_NONE && |
2336 | dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES) | |
2337 | i915_gem_object_pin_pages(obj); | |
2338 | ||
e5281ccd CW |
2339 | return 0; |
2340 | ||
2341 | err_pages: | |
90797e6d ID |
2342 | sg_mark_end(sg); |
2343 | for_each_sg_page(st->sgl, &sg_iter, st->nents, 0) | |
09cbfeaf | 2344 | put_page(sg_page_iter_page(&sg_iter)); |
9da3da66 CW |
2345 | sg_free_table(st); |
2346 | kfree(st); | |
0820baf3 CW |
2347 | |
2348 | /* shmemfs first checks if there is enough memory to allocate the page | |
2349 | * and reports ENOSPC should there be insufficient, along with the usual | |
2350 | * ENOMEM for a genuine allocation failure. | |
2351 | * | |
2352 | * We use ENOSPC in our driver to mean that we have run out of aperture | |
2353 | * space and so want to translate the error from shmemfs back to our | |
2354 | * usual understanding of ENOMEM. | |
2355 | */ | |
e2273302 ID |
2356 | if (ret == -ENOSPC) |
2357 | ret = -ENOMEM; | |
2358 | ||
2359 | return ret; | |
673a394b EA |
2360 | } |
2361 | ||
37e680a1 CW |
2362 | /* Ensure that the associated pages are gathered from the backing storage |
2363 | * and pinned into our object. i915_gem_object_get_pages() may be called | |
2364 | * multiple times before they are released by a single call to | |
2365 | * i915_gem_object_put_pages() - once the pages are no longer referenced | |
2366 | * either as a result of memory pressure (reaping pages under the shrinker) | |
2367 | * or as the object is itself released. | |
2368 | */ | |
2369 | int | |
2370 | i915_gem_object_get_pages(struct drm_i915_gem_object *obj) | |
2371 | { | |
2372 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; | |
2373 | const struct drm_i915_gem_object_ops *ops = obj->ops; | |
2374 | int ret; | |
2375 | ||
2f745ad3 | 2376 | if (obj->pages) |
37e680a1 CW |
2377 | return 0; |
2378 | ||
43e28f09 | 2379 | if (obj->madv != I915_MADV_WILLNEED) { |
bd9b6a4e | 2380 | DRM_DEBUG("Attempting to obtain a purgeable object\n"); |
8c99e57d | 2381 | return -EFAULT; |
43e28f09 CW |
2382 | } |
2383 | ||
a5570178 CW |
2384 | BUG_ON(obj->pages_pin_count); |
2385 | ||
37e680a1 CW |
2386 | ret = ops->get_pages(obj); |
2387 | if (ret) | |
2388 | return ret; | |
2389 | ||
35c20a60 | 2390 | list_add_tail(&obj->global_list, &dev_priv->mm.unbound_list); |
ee286370 CW |
2391 | |
2392 | obj->get_page.sg = obj->pages->sgl; | |
2393 | obj->get_page.last = 0; | |
2394 | ||
37e680a1 | 2395 | return 0; |
673a394b EA |
2396 | } |
2397 | ||
0a798eb9 CW |
2398 | void *i915_gem_object_pin_map(struct drm_i915_gem_object *obj) |
2399 | { | |
2400 | int ret; | |
2401 | ||
2402 | lockdep_assert_held(&obj->base.dev->struct_mutex); | |
2403 | ||
2404 | ret = i915_gem_object_get_pages(obj); | |
2405 | if (ret) | |
2406 | return ERR_PTR(ret); | |
2407 | ||
2408 | i915_gem_object_pin_pages(obj); | |
2409 | ||
2410 | if (obj->mapping == NULL) { | |
0a798eb9 | 2411 | struct page **pages; |
0a798eb9 | 2412 | |
fb8621d3 CW |
2413 | pages = NULL; |
2414 | if (obj->base.size == PAGE_SIZE) | |
2415 | obj->mapping = kmap(sg_page(obj->pages->sgl)); | |
2416 | else | |
2417 | pages = drm_malloc_gfp(obj->base.size >> PAGE_SHIFT, | |
2418 | sizeof(*pages), | |
2419 | GFP_TEMPORARY); | |
0a798eb9 | 2420 | if (pages != NULL) { |
fb8621d3 CW |
2421 | struct sg_page_iter sg_iter; |
2422 | int n; | |
2423 | ||
0a798eb9 CW |
2424 | n = 0; |
2425 | for_each_sg_page(obj->pages->sgl, &sg_iter, | |
2426 | obj->pages->nents, 0) | |
2427 | pages[n++] = sg_page_iter_page(&sg_iter); | |
2428 | ||
2429 | obj->mapping = vmap(pages, n, 0, PAGE_KERNEL); | |
2430 | drm_free_large(pages); | |
2431 | } | |
2432 | if (obj->mapping == NULL) { | |
2433 | i915_gem_object_unpin_pages(obj); | |
2434 | return ERR_PTR(-ENOMEM); | |
2435 | } | |
2436 | } | |
2437 | ||
2438 | return obj->mapping; | |
2439 | } | |
2440 | ||
b4716185 | 2441 | void i915_vma_move_to_active(struct i915_vma *vma, |
b2af0376 | 2442 | struct drm_i915_gem_request *req) |
673a394b | 2443 | { |
b4716185 | 2444 | struct drm_i915_gem_object *obj = vma->obj; |
e2f80391 | 2445 | struct intel_engine_cs *engine; |
b2af0376 | 2446 | |
666796da | 2447 | engine = i915_gem_request_get_engine(req); |
673a394b EA |
2448 | |
2449 | /* Add a reference if we're newly entering the active list. */ | |
b4716185 | 2450 | if (obj->active == 0) |
05394f39 | 2451 | drm_gem_object_reference(&obj->base); |
666796da | 2452 | obj->active |= intel_engine_flag(engine); |
e35a41de | 2453 | |
117897f4 | 2454 | list_move_tail(&obj->engine_list[engine->id], &engine->active_list); |
e2f80391 | 2455 | i915_gem_request_assign(&obj->last_read_req[engine->id], req); |
caea7476 | 2456 | |
1c7f4bca | 2457 | list_move_tail(&vma->vm_link, &vma->vm->active_list); |
caea7476 CW |
2458 | } |
2459 | ||
b4716185 CW |
2460 | static void |
2461 | i915_gem_object_retire__write(struct drm_i915_gem_object *obj) | |
e2d05a8b | 2462 | { |
d501b1d2 CW |
2463 | GEM_BUG_ON(obj->last_write_req == NULL); |
2464 | GEM_BUG_ON(!(obj->active & intel_engine_flag(obj->last_write_req->engine))); | |
b4716185 CW |
2465 | |
2466 | i915_gem_request_assign(&obj->last_write_req, NULL); | |
de152b62 | 2467 | intel_fb_obj_flush(obj, true, ORIGIN_CS); |
e2d05a8b BW |
2468 | } |
2469 | ||
caea7476 | 2470 | static void |
b4716185 | 2471 | i915_gem_object_retire__read(struct drm_i915_gem_object *obj, int ring) |
ce44b0ea | 2472 | { |
feb822cf | 2473 | struct i915_vma *vma; |
ce44b0ea | 2474 | |
d501b1d2 CW |
2475 | GEM_BUG_ON(obj->last_read_req[ring] == NULL); |
2476 | GEM_BUG_ON(!(obj->active & (1 << ring))); | |
b4716185 | 2477 | |
117897f4 | 2478 | list_del_init(&obj->engine_list[ring]); |
b4716185 CW |
2479 | i915_gem_request_assign(&obj->last_read_req[ring], NULL); |
2480 | ||
4a570db5 | 2481 | if (obj->last_write_req && obj->last_write_req->engine->id == ring) |
b4716185 CW |
2482 | i915_gem_object_retire__write(obj); |
2483 | ||
2484 | obj->active &= ~(1 << ring); | |
2485 | if (obj->active) | |
2486 | return; | |
caea7476 | 2487 | |
6c246959 CW |
2488 | /* Bump our place on the bound list to keep it roughly in LRU order |
2489 | * so that we don't steal from recently used but inactive objects | |
2490 | * (unless we are forced to ofc!) | |
2491 | */ | |
2492 | list_move_tail(&obj->global_list, | |
2493 | &to_i915(obj->base.dev)->mm.bound_list); | |
2494 | ||
1c7f4bca CW |
2495 | list_for_each_entry(vma, &obj->vma_list, obj_link) { |
2496 | if (!list_empty(&vma->vm_link)) | |
2497 | list_move_tail(&vma->vm_link, &vma->vm->inactive_list); | |
feb822cf | 2498 | } |
caea7476 | 2499 | |
97b2a6a1 | 2500 | i915_gem_request_assign(&obj->last_fenced_req, NULL); |
caea7476 | 2501 | drm_gem_object_unreference(&obj->base); |
c8725f3d CW |
2502 | } |
2503 | ||
9d773091 | 2504 | static int |
fca26bb4 | 2505 | i915_gem_init_seqno(struct drm_device *dev, u32 seqno) |
53d227f2 | 2506 | { |
9d773091 | 2507 | struct drm_i915_private *dev_priv = dev->dev_private; |
e2f80391 | 2508 | struct intel_engine_cs *engine; |
29dcb570 | 2509 | int ret; |
53d227f2 | 2510 | |
107f27a5 | 2511 | /* Carefully retire all requests without writing to the rings */ |
b4ac5afc | 2512 | for_each_engine(engine, dev_priv) { |
666796da | 2513 | ret = intel_engine_idle(engine); |
107f27a5 CW |
2514 | if (ret) |
2515 | return ret; | |
9d773091 | 2516 | } |
9d773091 | 2517 | i915_gem_retire_requests(dev); |
107f27a5 CW |
2518 | |
2519 | /* Finally reset hw state */ | |
29dcb570 | 2520 | for_each_engine(engine, dev_priv) |
e2f80391 | 2521 | intel_ring_init_seqno(engine, seqno); |
498d2ac1 | 2522 | |
9d773091 | 2523 | return 0; |
53d227f2 DV |
2524 | } |
2525 | ||
fca26bb4 MK |
2526 | int i915_gem_set_seqno(struct drm_device *dev, u32 seqno) |
2527 | { | |
2528 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2529 | int ret; | |
2530 | ||
2531 | if (seqno == 0) | |
2532 | return -EINVAL; | |
2533 | ||
2534 | /* HWS page needs to be set less than what we | |
2535 | * will inject to ring | |
2536 | */ | |
2537 | ret = i915_gem_init_seqno(dev, seqno - 1); | |
2538 | if (ret) | |
2539 | return ret; | |
2540 | ||
2541 | /* Carefully set the last_seqno value so that wrap | |
2542 | * detection still works | |
2543 | */ | |
2544 | dev_priv->next_seqno = seqno; | |
2545 | dev_priv->last_seqno = seqno - 1; | |
2546 | if (dev_priv->last_seqno == 0) | |
2547 | dev_priv->last_seqno--; | |
2548 | ||
2549 | return 0; | |
2550 | } | |
2551 | ||
9d773091 CW |
2552 | int |
2553 | i915_gem_get_seqno(struct drm_device *dev, u32 *seqno) | |
53d227f2 | 2554 | { |
9d773091 CW |
2555 | struct drm_i915_private *dev_priv = dev->dev_private; |
2556 | ||
2557 | /* reserve 0 for non-seqno */ | |
2558 | if (dev_priv->next_seqno == 0) { | |
fca26bb4 | 2559 | int ret = i915_gem_init_seqno(dev, 0); |
9d773091 CW |
2560 | if (ret) |
2561 | return ret; | |
53d227f2 | 2562 | |
9d773091 CW |
2563 | dev_priv->next_seqno = 1; |
2564 | } | |
53d227f2 | 2565 | |
f72b3435 | 2566 | *seqno = dev_priv->last_seqno = dev_priv->next_seqno++; |
9d773091 | 2567 | return 0; |
53d227f2 DV |
2568 | } |
2569 | ||
bf7dc5b7 JH |
2570 | /* |
2571 | * NB: This function is not allowed to fail. Doing so would mean the the | |
2572 | * request is not being tracked for completion but the work itself is | |
2573 | * going to happen on the hardware. This would be a Bad Thing(tm). | |
2574 | */ | |
75289874 | 2575 | void __i915_add_request(struct drm_i915_gem_request *request, |
5b4a60c2 JH |
2576 | struct drm_i915_gem_object *obj, |
2577 | bool flush_caches) | |
673a394b | 2578 | { |
e2f80391 | 2579 | struct intel_engine_cs *engine; |
75289874 | 2580 | struct drm_i915_private *dev_priv; |
48e29f55 | 2581 | struct intel_ringbuffer *ringbuf; |
6d3d8274 | 2582 | u32 request_start; |
3cce469c CW |
2583 | int ret; |
2584 | ||
48e29f55 | 2585 | if (WARN_ON(request == NULL)) |
bf7dc5b7 | 2586 | return; |
48e29f55 | 2587 | |
4a570db5 | 2588 | engine = request->engine; |
39dabecd | 2589 | dev_priv = request->i915; |
75289874 JH |
2590 | ringbuf = request->ringbuf; |
2591 | ||
29b1b415 JH |
2592 | /* |
2593 | * To ensure that this call will not fail, space for its emissions | |
2594 | * should already have been reserved in the ring buffer. Let the ring | |
2595 | * know that it is time to use that space up. | |
2596 | */ | |
2597 | intel_ring_reserved_space_use(ringbuf); | |
2598 | ||
48e29f55 | 2599 | request_start = intel_ring_get_tail(ringbuf); |
cc889e0f DV |
2600 | /* |
2601 | * Emit any outstanding flushes - execbuf can fail to emit the flush | |
2602 | * after having emitted the batchbuffer command. Hence we need to fix | |
2603 | * things up similar to emitting the lazy request. The difference here | |
2604 | * is that the flush _must_ happen before the next request, no matter | |
2605 | * what. | |
2606 | */ | |
5b4a60c2 JH |
2607 | if (flush_caches) { |
2608 | if (i915.enable_execlists) | |
4866d729 | 2609 | ret = logical_ring_flush_all_caches(request); |
5b4a60c2 | 2610 | else |
4866d729 | 2611 | ret = intel_ring_flush_all_caches(request); |
5b4a60c2 JH |
2612 | /* Not allowed to fail! */ |
2613 | WARN(ret, "*_ring_flush_all_caches failed: %d!\n", ret); | |
2614 | } | |
cc889e0f | 2615 | |
7c90b7de CW |
2616 | trace_i915_gem_request_add(request); |
2617 | ||
2618 | request->head = request_start; | |
2619 | ||
2620 | /* Whilst this request exists, batch_obj will be on the | |
2621 | * active_list, and so will hold the active reference. Only when this | |
2622 | * request is retired will the the batch_obj be moved onto the | |
2623 | * inactive_list and lose its active reference. Hence we do not need | |
2624 | * to explicitly hold another reference here. | |
2625 | */ | |
2626 | request->batch_obj = obj; | |
2627 | ||
2628 | /* Seal the request and mark it as pending execution. Note that | |
2629 | * we may inspect this state, without holding any locks, during | |
2630 | * hangcheck. Hence we apply the barrier to ensure that we do not | |
2631 | * see a more recent value in the hws than we are tracking. | |
2632 | */ | |
2633 | request->emitted_jiffies = jiffies; | |
2634 | request->previous_seqno = engine->last_submitted_seqno; | |
2635 | smp_store_mb(engine->last_submitted_seqno, request->seqno); | |
2636 | list_add_tail(&request->list, &engine->request_list); | |
2637 | ||
a71d8d94 CW |
2638 | /* Record the position of the start of the request so that |
2639 | * should we detect the updated seqno part-way through the | |
2640 | * GPU processing the request, we never over-estimate the | |
2641 | * position of the head. | |
2642 | */ | |
6d3d8274 | 2643 | request->postfix = intel_ring_get_tail(ringbuf); |
a71d8d94 | 2644 | |
bf7dc5b7 | 2645 | if (i915.enable_execlists) |
e2f80391 | 2646 | ret = engine->emit_request(request); |
bf7dc5b7 | 2647 | else { |
e2f80391 | 2648 | ret = engine->add_request(request); |
53292cdb MT |
2649 | |
2650 | request->tail = intel_ring_get_tail(ringbuf); | |
48e29f55 | 2651 | } |
bf7dc5b7 JH |
2652 | /* Not allowed to fail! */ |
2653 | WARN(ret, "emit|add_request failed: %d!\n", ret); | |
673a394b | 2654 | |
e2f80391 | 2655 | i915_queue_hangcheck(engine->dev); |
10cd45b6 | 2656 | |
87255483 DV |
2657 | queue_delayed_work(dev_priv->wq, |
2658 | &dev_priv->mm.retire_work, | |
2659 | round_jiffies_up_relative(HZ)); | |
2660 | intel_mark_busy(dev_priv->dev); | |
cc889e0f | 2661 | |
29b1b415 JH |
2662 | /* Sanity check that the reserved size was large enough. */ |
2663 | intel_ring_reserved_space_end(ringbuf); | |
673a394b EA |
2664 | } |
2665 | ||
939fd762 | 2666 | static bool i915_context_is_banned(struct drm_i915_private *dev_priv, |
273497e5 | 2667 | const struct intel_context *ctx) |
be62acb4 | 2668 | { |
44e2c070 | 2669 | unsigned long elapsed; |
be62acb4 | 2670 | |
44e2c070 MK |
2671 | elapsed = get_seconds() - ctx->hang_stats.guilty_ts; |
2672 | ||
2673 | if (ctx->hang_stats.banned) | |
be62acb4 MK |
2674 | return true; |
2675 | ||
676fa572 CW |
2676 | if (ctx->hang_stats.ban_period_seconds && |
2677 | elapsed <= ctx->hang_stats.ban_period_seconds) { | |
ccc7bed0 | 2678 | if (!i915_gem_context_is_default(ctx)) { |
3fac8978 | 2679 | DRM_DEBUG("context hanging too fast, banning!\n"); |
ccc7bed0 | 2680 | return true; |
88b4aa87 MK |
2681 | } else if (i915_stop_ring_allow_ban(dev_priv)) { |
2682 | if (i915_stop_ring_allow_warn(dev_priv)) | |
2683 | DRM_ERROR("gpu hanging too fast, banning!\n"); | |
ccc7bed0 | 2684 | return true; |
3fac8978 | 2685 | } |
be62acb4 MK |
2686 | } |
2687 | ||
2688 | return false; | |
2689 | } | |
2690 | ||
939fd762 | 2691 | static void i915_set_reset_status(struct drm_i915_private *dev_priv, |
273497e5 | 2692 | struct intel_context *ctx, |
b6b0fac0 | 2693 | const bool guilty) |
aa60c664 | 2694 | { |
44e2c070 MK |
2695 | struct i915_ctx_hang_stats *hs; |
2696 | ||
2697 | if (WARN_ON(!ctx)) | |
2698 | return; | |
aa60c664 | 2699 | |
44e2c070 MK |
2700 | hs = &ctx->hang_stats; |
2701 | ||
2702 | if (guilty) { | |
939fd762 | 2703 | hs->banned = i915_context_is_banned(dev_priv, ctx); |
44e2c070 MK |
2704 | hs->batch_active++; |
2705 | hs->guilty_ts = get_seconds(); | |
2706 | } else { | |
2707 | hs->batch_pending++; | |
aa60c664 MK |
2708 | } |
2709 | } | |
2710 | ||
abfe262a JH |
2711 | void i915_gem_request_free(struct kref *req_ref) |
2712 | { | |
2713 | struct drm_i915_gem_request *req = container_of(req_ref, | |
2714 | typeof(*req), ref); | |
2715 | struct intel_context *ctx = req->ctx; | |
2716 | ||
fcfa423c JH |
2717 | if (req->file_priv) |
2718 | i915_gem_request_remove_from_client(req); | |
2719 | ||
0794aed3 | 2720 | if (ctx) { |
e28e404c | 2721 | if (i915.enable_execlists && ctx != req->i915->kernel_context) |
4a570db5 | 2722 | intel_lr_context_unpin(ctx, req->engine); |
abfe262a | 2723 | |
dcb4c12a OM |
2724 | i915_gem_context_unreference(ctx); |
2725 | } | |
abfe262a | 2726 | |
efab6d8d | 2727 | kmem_cache_free(req->i915->requests, req); |
0e50e96b MK |
2728 | } |
2729 | ||
26827088 | 2730 | static inline int |
0bc40be8 | 2731 | __i915_gem_request_alloc(struct intel_engine_cs *engine, |
26827088 DG |
2732 | struct intel_context *ctx, |
2733 | struct drm_i915_gem_request **req_out) | |
6689cb2b | 2734 | { |
0bc40be8 | 2735 | struct drm_i915_private *dev_priv = to_i915(engine->dev); |
299259a3 | 2736 | unsigned reset_counter = i915_reset_counter(&dev_priv->gpu_error); |
eed29a5b | 2737 | struct drm_i915_gem_request *req; |
6689cb2b | 2738 | int ret; |
6689cb2b | 2739 | |
217e46b5 JH |
2740 | if (!req_out) |
2741 | return -EINVAL; | |
2742 | ||
bccca494 | 2743 | *req_out = NULL; |
6689cb2b | 2744 | |
f4457ae7 CW |
2745 | /* ABI: Before userspace accesses the GPU (e.g. execbuffer), report |
2746 | * EIO if the GPU is already wedged, or EAGAIN to drop the struct_mutex | |
2747 | * and restart. | |
2748 | */ | |
2749 | ret = i915_gem_check_wedge(reset_counter, dev_priv->mm.interruptible); | |
299259a3 CW |
2750 | if (ret) |
2751 | return ret; | |
2752 | ||
eed29a5b DV |
2753 | req = kmem_cache_zalloc(dev_priv->requests, GFP_KERNEL); |
2754 | if (req == NULL) | |
6689cb2b JH |
2755 | return -ENOMEM; |
2756 | ||
0bc40be8 | 2757 | ret = i915_gem_get_seqno(engine->dev, &req->seqno); |
9a0c1e27 CW |
2758 | if (ret) |
2759 | goto err; | |
6689cb2b | 2760 | |
40e895ce JH |
2761 | kref_init(&req->ref); |
2762 | req->i915 = dev_priv; | |
4a570db5 | 2763 | req->engine = engine; |
299259a3 | 2764 | req->reset_counter = reset_counter; |
40e895ce JH |
2765 | req->ctx = ctx; |
2766 | i915_gem_context_reference(req->ctx); | |
6689cb2b JH |
2767 | |
2768 | if (i915.enable_execlists) | |
40e895ce | 2769 | ret = intel_logical_ring_alloc_request_extras(req); |
6689cb2b | 2770 | else |
eed29a5b | 2771 | ret = intel_ring_alloc_request_extras(req); |
40e895ce JH |
2772 | if (ret) { |
2773 | i915_gem_context_unreference(req->ctx); | |
9a0c1e27 | 2774 | goto err; |
40e895ce | 2775 | } |
6689cb2b | 2776 | |
29b1b415 JH |
2777 | /* |
2778 | * Reserve space in the ring buffer for all the commands required to | |
2779 | * eventually emit this request. This is to guarantee that the | |
2780 | * i915_add_request() call can't fail. Note that the reserve may need | |
2781 | * to be redone if the request is not actually submitted straight | |
2782 | * away, e.g. because a GPU scheduler has deferred it. | |
29b1b415 | 2783 | */ |
ccd98fe4 JH |
2784 | if (i915.enable_execlists) |
2785 | ret = intel_logical_ring_reserve_space(req); | |
2786 | else | |
2787 | ret = intel_ring_reserve_space(req); | |
2788 | if (ret) { | |
2789 | /* | |
2790 | * At this point, the request is fully allocated even if not | |
2791 | * fully prepared. Thus it can be cleaned up using the proper | |
2792 | * free code. | |
2793 | */ | |
2794 | i915_gem_request_cancel(req); | |
2795 | return ret; | |
2796 | } | |
29b1b415 | 2797 | |
bccca494 | 2798 | *req_out = req; |
6689cb2b | 2799 | return 0; |
9a0c1e27 CW |
2800 | |
2801 | err: | |
2802 | kmem_cache_free(dev_priv->requests, req); | |
2803 | return ret; | |
0e50e96b MK |
2804 | } |
2805 | ||
26827088 DG |
2806 | /** |
2807 | * i915_gem_request_alloc - allocate a request structure | |
2808 | * | |
2809 | * @engine: engine that we wish to issue the request on. | |
2810 | * @ctx: context that the request will be associated with. | |
2811 | * This can be NULL if the request is not directly related to | |
2812 | * any specific user context, in which case this function will | |
2813 | * choose an appropriate context to use. | |
2814 | * | |
2815 | * Returns a pointer to the allocated request if successful, | |
2816 | * or an error code if not. | |
2817 | */ | |
2818 | struct drm_i915_gem_request * | |
2819 | i915_gem_request_alloc(struct intel_engine_cs *engine, | |
2820 | struct intel_context *ctx) | |
2821 | { | |
2822 | struct drm_i915_gem_request *req; | |
2823 | int err; | |
2824 | ||
2825 | if (ctx == NULL) | |
ed54c1a1 | 2826 | ctx = to_i915(engine->dev)->kernel_context; |
26827088 DG |
2827 | err = __i915_gem_request_alloc(engine, ctx, &req); |
2828 | return err ? ERR_PTR(err) : req; | |
2829 | } | |
2830 | ||
29b1b415 JH |
2831 | void i915_gem_request_cancel(struct drm_i915_gem_request *req) |
2832 | { | |
2833 | intel_ring_reserved_space_cancel(req->ringbuf); | |
2834 | ||
2835 | i915_gem_request_unreference(req); | |
2836 | } | |
2837 | ||
8d9fc7fd | 2838 | struct drm_i915_gem_request * |
0bc40be8 | 2839 | i915_gem_find_active_request(struct intel_engine_cs *engine) |
9375e446 | 2840 | { |
4db080f9 CW |
2841 | struct drm_i915_gem_request *request; |
2842 | ||
0bc40be8 | 2843 | list_for_each_entry(request, &engine->request_list, list) { |
1b5a433a | 2844 | if (i915_gem_request_completed(request, false)) |
4db080f9 | 2845 | continue; |
aa60c664 | 2846 | |
b6b0fac0 | 2847 | return request; |
4db080f9 | 2848 | } |
b6b0fac0 MK |
2849 | |
2850 | return NULL; | |
2851 | } | |
2852 | ||
666796da | 2853 | static void i915_gem_reset_engine_status(struct drm_i915_private *dev_priv, |
0bc40be8 | 2854 | struct intel_engine_cs *engine) |
b6b0fac0 MK |
2855 | { |
2856 | struct drm_i915_gem_request *request; | |
2857 | bool ring_hung; | |
2858 | ||
0bc40be8 | 2859 | request = i915_gem_find_active_request(engine); |
b6b0fac0 MK |
2860 | |
2861 | if (request == NULL) | |
2862 | return; | |
2863 | ||
0bc40be8 | 2864 | ring_hung = engine->hangcheck.score >= HANGCHECK_SCORE_RING_HUNG; |
b6b0fac0 | 2865 | |
939fd762 | 2866 | i915_set_reset_status(dev_priv, request->ctx, ring_hung); |
b6b0fac0 | 2867 | |
0bc40be8 | 2868 | list_for_each_entry_continue(request, &engine->request_list, list) |
939fd762 | 2869 | i915_set_reset_status(dev_priv, request->ctx, false); |
4db080f9 | 2870 | } |
aa60c664 | 2871 | |
666796da | 2872 | static void i915_gem_reset_engine_cleanup(struct drm_i915_private *dev_priv, |
0bc40be8 | 2873 | struct intel_engine_cs *engine) |
4db080f9 | 2874 | { |
608c1a52 CW |
2875 | struct intel_ringbuffer *buffer; |
2876 | ||
0bc40be8 | 2877 | while (!list_empty(&engine->active_list)) { |
05394f39 | 2878 | struct drm_i915_gem_object *obj; |
9375e446 | 2879 | |
0bc40be8 | 2880 | obj = list_first_entry(&engine->active_list, |
05394f39 | 2881 | struct drm_i915_gem_object, |
117897f4 | 2882 | engine_list[engine->id]); |
9375e446 | 2883 | |
0bc40be8 | 2884 | i915_gem_object_retire__read(obj, engine->id); |
673a394b | 2885 | } |
1d62beea | 2886 | |
dcb4c12a OM |
2887 | /* |
2888 | * Clear the execlists queue up before freeing the requests, as those | |
2889 | * are the ones that keep the context and ringbuffer backing objects | |
2890 | * pinned in place. | |
2891 | */ | |
dcb4c12a | 2892 | |
7de1691a | 2893 | if (i915.enable_execlists) { |
27af5eea TU |
2894 | /* Ensure irq handler finishes or is cancelled. */ |
2895 | tasklet_kill(&engine->irq_tasklet); | |
1197b4f2 | 2896 | |
27af5eea | 2897 | spin_lock_bh(&engine->execlist_lock); |
c5baa566 | 2898 | /* list_splice_tail_init checks for empty lists */ |
0bc40be8 TU |
2899 | list_splice_tail_init(&engine->execlist_queue, |
2900 | &engine->execlist_retired_req_list); | |
27af5eea | 2901 | spin_unlock_bh(&engine->execlist_lock); |
1197b4f2 | 2902 | |
0bc40be8 | 2903 | intel_execlists_retire_requests(engine); |
dcb4c12a OM |
2904 | } |
2905 | ||
1d62beea BW |
2906 | /* |
2907 | * We must free the requests after all the corresponding objects have | |
2908 | * been moved off active lists. Which is the same order as the normal | |
2909 | * retire_requests function does. This is important if object hold | |
2910 | * implicit references on things like e.g. ppgtt address spaces through | |
2911 | * the request. | |
2912 | */ | |
0bc40be8 | 2913 | while (!list_empty(&engine->request_list)) { |
1d62beea BW |
2914 | struct drm_i915_gem_request *request; |
2915 | ||
0bc40be8 | 2916 | request = list_first_entry(&engine->request_list, |
1d62beea BW |
2917 | struct drm_i915_gem_request, |
2918 | list); | |
2919 | ||
b4716185 | 2920 | i915_gem_request_retire(request); |
1d62beea | 2921 | } |
608c1a52 CW |
2922 | |
2923 | /* Having flushed all requests from all queues, we know that all | |
2924 | * ringbuffers must now be empty. However, since we do not reclaim | |
2925 | * all space when retiring the request (to prevent HEADs colliding | |
2926 | * with rapid ringbuffer wraparound) the amount of available space | |
2927 | * upon reset is less than when we start. Do one more pass over | |
2928 | * all the ringbuffers to reset last_retired_head. | |
2929 | */ | |
0bc40be8 | 2930 | list_for_each_entry(buffer, &engine->buffers, link) { |
608c1a52 CW |
2931 | buffer->last_retired_head = buffer->tail; |
2932 | intel_ring_update_space(buffer); | |
2933 | } | |
2ed53a94 CW |
2934 | |
2935 | intel_ring_init_seqno(engine, engine->last_submitted_seqno); | |
673a394b EA |
2936 | } |
2937 | ||
069efc1d | 2938 | void i915_gem_reset(struct drm_device *dev) |
673a394b | 2939 | { |
77f01230 | 2940 | struct drm_i915_private *dev_priv = dev->dev_private; |
e2f80391 | 2941 | struct intel_engine_cs *engine; |
673a394b | 2942 | |
4db080f9 CW |
2943 | /* |
2944 | * Before we free the objects from the requests, we need to inspect | |
2945 | * them for finding the guilty party. As the requests only borrow | |
2946 | * their reference to the objects, the inspection must be done first. | |
2947 | */ | |
b4ac5afc | 2948 | for_each_engine(engine, dev_priv) |
666796da | 2949 | i915_gem_reset_engine_status(dev_priv, engine); |
4db080f9 | 2950 | |
b4ac5afc | 2951 | for_each_engine(engine, dev_priv) |
666796da | 2952 | i915_gem_reset_engine_cleanup(dev_priv, engine); |
dfaae392 | 2953 | |
acce9ffa BW |
2954 | i915_gem_context_reset(dev); |
2955 | ||
19b2dbde | 2956 | i915_gem_restore_fences(dev); |
b4716185 CW |
2957 | |
2958 | WARN_ON(i915_verify_lists(dev)); | |
673a394b EA |
2959 | } |
2960 | ||
2961 | /** | |
2962 | * This function clears the request list as sequence numbers are passed. | |
2963 | */ | |
1cf0ba14 | 2964 | void |
0bc40be8 | 2965 | i915_gem_retire_requests_ring(struct intel_engine_cs *engine) |
673a394b | 2966 | { |
0bc40be8 | 2967 | WARN_ON(i915_verify_lists(engine->dev)); |
673a394b | 2968 | |
832a3aad CW |
2969 | /* Retire requests first as we use it above for the early return. |
2970 | * If we retire requests last, we may use a later seqno and so clear | |
2971 | * the requests lists without clearing the active list, leading to | |
2972 | * confusion. | |
e9103038 | 2973 | */ |
0bc40be8 | 2974 | while (!list_empty(&engine->request_list)) { |
673a394b | 2975 | struct drm_i915_gem_request *request; |
673a394b | 2976 | |
0bc40be8 | 2977 | request = list_first_entry(&engine->request_list, |
673a394b EA |
2978 | struct drm_i915_gem_request, |
2979 | list); | |
673a394b | 2980 | |
1b5a433a | 2981 | if (!i915_gem_request_completed(request, true)) |
b84d5f0c CW |
2982 | break; |
2983 | ||
b4716185 | 2984 | i915_gem_request_retire(request); |
b84d5f0c | 2985 | } |
673a394b | 2986 | |
832a3aad CW |
2987 | /* Move any buffers on the active list that are no longer referenced |
2988 | * by the ringbuffer to the flushing/inactive lists as appropriate, | |
2989 | * before we free the context associated with the requests. | |
2990 | */ | |
0bc40be8 | 2991 | while (!list_empty(&engine->active_list)) { |
832a3aad CW |
2992 | struct drm_i915_gem_object *obj; |
2993 | ||
0bc40be8 TU |
2994 | obj = list_first_entry(&engine->active_list, |
2995 | struct drm_i915_gem_object, | |
117897f4 | 2996 | engine_list[engine->id]); |
832a3aad | 2997 | |
0bc40be8 | 2998 | if (!list_empty(&obj->last_read_req[engine->id]->list)) |
832a3aad CW |
2999 | break; |
3000 | ||
0bc40be8 | 3001 | i915_gem_object_retire__read(obj, engine->id); |
832a3aad CW |
3002 | } |
3003 | ||
0bc40be8 TU |
3004 | if (unlikely(engine->trace_irq_req && |
3005 | i915_gem_request_completed(engine->trace_irq_req, true))) { | |
3006 | engine->irq_put(engine); | |
3007 | i915_gem_request_assign(&engine->trace_irq_req, NULL); | |
9d34e5db | 3008 | } |
23bc5982 | 3009 | |
0bc40be8 | 3010 | WARN_ON(i915_verify_lists(engine->dev)); |
673a394b EA |
3011 | } |
3012 | ||
b29c19b6 | 3013 | bool |
b09a1fec CW |
3014 | i915_gem_retire_requests(struct drm_device *dev) |
3015 | { | |
3e31c6c0 | 3016 | struct drm_i915_private *dev_priv = dev->dev_private; |
e2f80391 | 3017 | struct intel_engine_cs *engine; |
b29c19b6 | 3018 | bool idle = true; |
b09a1fec | 3019 | |
b4ac5afc | 3020 | for_each_engine(engine, dev_priv) { |
e2f80391 TU |
3021 | i915_gem_retire_requests_ring(engine); |
3022 | idle &= list_empty(&engine->request_list); | |
c86ee3a9 | 3023 | if (i915.enable_execlists) { |
27af5eea | 3024 | spin_lock_bh(&engine->execlist_lock); |
e2f80391 | 3025 | idle &= list_empty(&engine->execlist_queue); |
27af5eea | 3026 | spin_unlock_bh(&engine->execlist_lock); |
c86ee3a9 | 3027 | |
e2f80391 | 3028 | intel_execlists_retire_requests(engine); |
c86ee3a9 | 3029 | } |
b29c19b6 CW |
3030 | } |
3031 | ||
3032 | if (idle) | |
3033 | mod_delayed_work(dev_priv->wq, | |
3034 | &dev_priv->mm.idle_work, | |
3035 | msecs_to_jiffies(100)); | |
3036 | ||
3037 | return idle; | |
b09a1fec CW |
3038 | } |
3039 | ||
75ef9da2 | 3040 | static void |
673a394b EA |
3041 | i915_gem_retire_work_handler(struct work_struct *work) |
3042 | { | |
b29c19b6 CW |
3043 | struct drm_i915_private *dev_priv = |
3044 | container_of(work, typeof(*dev_priv), mm.retire_work.work); | |
3045 | struct drm_device *dev = dev_priv->dev; | |
0a58705b | 3046 | bool idle; |
673a394b | 3047 | |
891b48cf | 3048 | /* Come back later if the device is busy... */ |
b29c19b6 CW |
3049 | idle = false; |
3050 | if (mutex_trylock(&dev->struct_mutex)) { | |
3051 | idle = i915_gem_retire_requests(dev); | |
3052 | mutex_unlock(&dev->struct_mutex); | |
673a394b | 3053 | } |
b29c19b6 | 3054 | if (!idle) |
bcb45086 CW |
3055 | queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, |
3056 | round_jiffies_up_relative(HZ)); | |
b29c19b6 | 3057 | } |
0a58705b | 3058 | |
b29c19b6 CW |
3059 | static void |
3060 | i915_gem_idle_work_handler(struct work_struct *work) | |
3061 | { | |
3062 | struct drm_i915_private *dev_priv = | |
3063 | container_of(work, typeof(*dev_priv), mm.idle_work.work); | |
35c94185 | 3064 | struct drm_device *dev = dev_priv->dev; |
b4ac5afc | 3065 | struct intel_engine_cs *engine; |
b29c19b6 | 3066 | |
b4ac5afc DG |
3067 | for_each_engine(engine, dev_priv) |
3068 | if (!list_empty(&engine->request_list)) | |
423795cb | 3069 | return; |
35c94185 | 3070 | |
30ecad77 | 3071 | /* we probably should sync with hangcheck here, using cancel_work_sync. |
b4ac5afc | 3072 | * Also locking seems to be fubar here, engine->request_list is protected |
30ecad77 DV |
3073 | * by dev->struct_mutex. */ |
3074 | ||
35c94185 CW |
3075 | intel_mark_idle(dev); |
3076 | ||
3077 | if (mutex_trylock(&dev->struct_mutex)) { | |
b4ac5afc | 3078 | for_each_engine(engine, dev_priv) |
e2f80391 | 3079 | i915_gem_batch_pool_fini(&engine->batch_pool); |
b29c19b6 | 3080 | |
35c94185 CW |
3081 | mutex_unlock(&dev->struct_mutex); |
3082 | } | |
673a394b EA |
3083 | } |
3084 | ||
30dfebf3 DV |
3085 | /** |
3086 | * Ensures that an object will eventually get non-busy by flushing any required | |
3087 | * write domains, emitting any outstanding lazy request and retiring and | |
3088 | * completed requests. | |
3089 | */ | |
3090 | static int | |
3091 | i915_gem_object_flush_active(struct drm_i915_gem_object *obj) | |
3092 | { | |
a5ac0f90 | 3093 | int i; |
b4716185 CW |
3094 | |
3095 | if (!obj->active) | |
3096 | return 0; | |
30dfebf3 | 3097 | |
666796da | 3098 | for (i = 0; i < I915_NUM_ENGINES; i++) { |
b4716185 | 3099 | struct drm_i915_gem_request *req; |
41c52415 | 3100 | |
b4716185 CW |
3101 | req = obj->last_read_req[i]; |
3102 | if (req == NULL) | |
3103 | continue; | |
3104 | ||
3105 | if (list_empty(&req->list)) | |
3106 | goto retire; | |
3107 | ||
b4716185 CW |
3108 | if (i915_gem_request_completed(req, true)) { |
3109 | __i915_gem_request_retire__upto(req); | |
3110 | retire: | |
3111 | i915_gem_object_retire__read(obj, i); | |
3112 | } | |
30dfebf3 DV |
3113 | } |
3114 | ||
3115 | return 0; | |
3116 | } | |
3117 | ||
23ba4fd0 BW |
3118 | /** |
3119 | * i915_gem_wait_ioctl - implements DRM_IOCTL_I915_GEM_WAIT | |
3120 | * @DRM_IOCTL_ARGS: standard ioctl arguments | |
3121 | * | |
3122 | * Returns 0 if successful, else an error is returned with the remaining time in | |
3123 | * the timeout parameter. | |
3124 | * -ETIME: object is still busy after timeout | |
3125 | * -ERESTARTSYS: signal interrupted the wait | |
3126 | * -ENONENT: object doesn't exist | |
3127 | * Also possible, but rare: | |
3128 | * -EAGAIN: GPU wedged | |
3129 | * -ENOMEM: damn | |
3130 | * -ENODEV: Internal IRQ fail | |
3131 | * -E?: The add request failed | |
3132 | * | |
3133 | * The wait ioctl with a timeout of 0 reimplements the busy ioctl. With any | |
3134 | * non-zero timeout parameter the wait ioctl will wait for the given number of | |
3135 | * nanoseconds on an object becoming unbusy. Since the wait itself does so | |
3136 | * without holding struct_mutex the object may become re-busied before this | |
3137 | * function completes. A similar but shorter * race condition exists in the busy | |
3138 | * ioctl | |
3139 | */ | |
3140 | int | |
3141 | i915_gem_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *file) | |
3142 | { | |
3143 | struct drm_i915_gem_wait *args = data; | |
3144 | struct drm_i915_gem_object *obj; | |
666796da | 3145 | struct drm_i915_gem_request *req[I915_NUM_ENGINES]; |
b4716185 CW |
3146 | int i, n = 0; |
3147 | int ret; | |
23ba4fd0 | 3148 | |
11b5d511 DV |
3149 | if (args->flags != 0) |
3150 | return -EINVAL; | |
3151 | ||
23ba4fd0 BW |
3152 | ret = i915_mutex_lock_interruptible(dev); |
3153 | if (ret) | |
3154 | return ret; | |
3155 | ||
3156 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->bo_handle)); | |
3157 | if (&obj->base == NULL) { | |
3158 | mutex_unlock(&dev->struct_mutex); | |
3159 | return -ENOENT; | |
3160 | } | |
3161 | ||
30dfebf3 DV |
3162 | /* Need to make sure the object gets inactive eventually. */ |
3163 | ret = i915_gem_object_flush_active(obj); | |
23ba4fd0 BW |
3164 | if (ret) |
3165 | goto out; | |
3166 | ||
b4716185 | 3167 | if (!obj->active) |
97b2a6a1 | 3168 | goto out; |
23ba4fd0 | 3169 | |
23ba4fd0 | 3170 | /* Do this after OLR check to make sure we make forward progress polling |
762e4583 | 3171 | * on this IOCTL with a timeout == 0 (like busy ioctl) |
23ba4fd0 | 3172 | */ |
762e4583 | 3173 | if (args->timeout_ns == 0) { |
23ba4fd0 BW |
3174 | ret = -ETIME; |
3175 | goto out; | |
3176 | } | |
3177 | ||
3178 | drm_gem_object_unreference(&obj->base); | |
b4716185 | 3179 | |
666796da | 3180 | for (i = 0; i < I915_NUM_ENGINES; i++) { |
b4716185 CW |
3181 | if (obj->last_read_req[i] == NULL) |
3182 | continue; | |
3183 | ||
3184 | req[n++] = i915_gem_request_reference(obj->last_read_req[i]); | |
3185 | } | |
3186 | ||
23ba4fd0 BW |
3187 | mutex_unlock(&dev->struct_mutex); |
3188 | ||
b4716185 CW |
3189 | for (i = 0; i < n; i++) { |
3190 | if (ret == 0) | |
299259a3 | 3191 | ret = __i915_wait_request(req[i], true, |
b4716185 | 3192 | args->timeout_ns > 0 ? &args->timeout_ns : NULL, |
b6aa0873 | 3193 | to_rps_client(file)); |
b4716185 CW |
3194 | i915_gem_request_unreference__unlocked(req[i]); |
3195 | } | |
ff865885 | 3196 | return ret; |
23ba4fd0 BW |
3197 | |
3198 | out: | |
3199 | drm_gem_object_unreference(&obj->base); | |
3200 | mutex_unlock(&dev->struct_mutex); | |
3201 | return ret; | |
3202 | } | |
3203 | ||
b4716185 CW |
3204 | static int |
3205 | __i915_gem_object_sync(struct drm_i915_gem_object *obj, | |
3206 | struct intel_engine_cs *to, | |
91af127f JH |
3207 | struct drm_i915_gem_request *from_req, |
3208 | struct drm_i915_gem_request **to_req) | |
b4716185 CW |
3209 | { |
3210 | struct intel_engine_cs *from; | |
3211 | int ret; | |
3212 | ||
666796da | 3213 | from = i915_gem_request_get_engine(from_req); |
b4716185 CW |
3214 | if (to == from) |
3215 | return 0; | |
3216 | ||
91af127f | 3217 | if (i915_gem_request_completed(from_req, true)) |
b4716185 CW |
3218 | return 0; |
3219 | ||
b4716185 | 3220 | if (!i915_semaphore_is_enabled(obj->base.dev)) { |
a6f766f3 | 3221 | struct drm_i915_private *i915 = to_i915(obj->base.dev); |
91af127f | 3222 | ret = __i915_wait_request(from_req, |
a6f766f3 CW |
3223 | i915->mm.interruptible, |
3224 | NULL, | |
3225 | &i915->rps.semaphores); | |
b4716185 CW |
3226 | if (ret) |
3227 | return ret; | |
3228 | ||
91af127f | 3229 | i915_gem_object_retire_request(obj, from_req); |
b4716185 CW |
3230 | } else { |
3231 | int idx = intel_ring_sync_index(from, to); | |
91af127f JH |
3232 | u32 seqno = i915_gem_request_get_seqno(from_req); |
3233 | ||
3234 | WARN_ON(!to_req); | |
b4716185 CW |
3235 | |
3236 | if (seqno <= from->semaphore.sync_seqno[idx]) | |
3237 | return 0; | |
3238 | ||
91af127f | 3239 | if (*to_req == NULL) { |
26827088 DG |
3240 | struct drm_i915_gem_request *req; |
3241 | ||
3242 | req = i915_gem_request_alloc(to, NULL); | |
3243 | if (IS_ERR(req)) | |
3244 | return PTR_ERR(req); | |
3245 | ||
3246 | *to_req = req; | |
91af127f JH |
3247 | } |
3248 | ||
599d924c JH |
3249 | trace_i915_gem_ring_sync_to(*to_req, from, from_req); |
3250 | ret = to->semaphore.sync_to(*to_req, from, seqno); | |
b4716185 CW |
3251 | if (ret) |
3252 | return ret; | |
3253 | ||
3254 | /* We use last_read_req because sync_to() | |
3255 | * might have just caused seqno wrap under | |
3256 | * the radar. | |
3257 | */ | |
3258 | from->semaphore.sync_seqno[idx] = | |
3259 | i915_gem_request_get_seqno(obj->last_read_req[from->id]); | |
3260 | } | |
3261 | ||
3262 | return 0; | |
3263 | } | |
3264 | ||
5816d648 BW |
3265 | /** |
3266 | * i915_gem_object_sync - sync an object to a ring. | |
3267 | * | |
3268 | * @obj: object which may be in use on another ring. | |
3269 | * @to: ring we wish to use the object on. May be NULL. | |
91af127f JH |
3270 | * @to_req: request we wish to use the object for. See below. |
3271 | * This will be allocated and returned if a request is | |
3272 | * required but not passed in. | |
5816d648 BW |
3273 | * |
3274 | * This code is meant to abstract object synchronization with the GPU. | |
3275 | * Calling with NULL implies synchronizing the object with the CPU | |
b4716185 | 3276 | * rather than a particular GPU ring. Conceptually we serialise writes |
91af127f | 3277 | * between engines inside the GPU. We only allow one engine to write |
b4716185 CW |
3278 | * into a buffer at any time, but multiple readers. To ensure each has |
3279 | * a coherent view of memory, we must: | |
3280 | * | |
3281 | * - If there is an outstanding write request to the object, the new | |
3282 | * request must wait for it to complete (either CPU or in hw, requests | |
3283 | * on the same ring will be naturally ordered). | |
3284 | * | |
3285 | * - If we are a write request (pending_write_domain is set), the new | |
3286 | * request must wait for outstanding read requests to complete. | |
5816d648 | 3287 | * |
91af127f JH |
3288 | * For CPU synchronisation (NULL to) no request is required. For syncing with |
3289 | * rings to_req must be non-NULL. However, a request does not have to be | |
3290 | * pre-allocated. If *to_req is NULL and sync commands will be emitted then a | |
3291 | * request will be allocated automatically and returned through *to_req. Note | |
3292 | * that it is not guaranteed that commands will be emitted (because the system | |
3293 | * might already be idle). Hence there is no need to create a request that | |
3294 | * might never have any work submitted. Note further that if a request is | |
3295 | * returned in *to_req, it is the responsibility of the caller to submit | |
3296 | * that request (after potentially adding more work to it). | |
3297 | * | |
5816d648 BW |
3298 | * Returns 0 if successful, else propagates up the lower layer error. |
3299 | */ | |
2911a35b BW |
3300 | int |
3301 | i915_gem_object_sync(struct drm_i915_gem_object *obj, | |
91af127f JH |
3302 | struct intel_engine_cs *to, |
3303 | struct drm_i915_gem_request **to_req) | |
2911a35b | 3304 | { |
b4716185 | 3305 | const bool readonly = obj->base.pending_write_domain == 0; |
666796da | 3306 | struct drm_i915_gem_request *req[I915_NUM_ENGINES]; |
b4716185 | 3307 | int ret, i, n; |
41c52415 | 3308 | |
b4716185 | 3309 | if (!obj->active) |
2911a35b BW |
3310 | return 0; |
3311 | ||
b4716185 CW |
3312 | if (to == NULL) |
3313 | return i915_gem_object_wait_rendering(obj, readonly); | |
2911a35b | 3314 | |
b4716185 CW |
3315 | n = 0; |
3316 | if (readonly) { | |
3317 | if (obj->last_write_req) | |
3318 | req[n++] = obj->last_write_req; | |
3319 | } else { | |
666796da | 3320 | for (i = 0; i < I915_NUM_ENGINES; i++) |
b4716185 CW |
3321 | if (obj->last_read_req[i]) |
3322 | req[n++] = obj->last_read_req[i]; | |
3323 | } | |
3324 | for (i = 0; i < n; i++) { | |
91af127f | 3325 | ret = __i915_gem_object_sync(obj, to, req[i], to_req); |
b4716185 CW |
3326 | if (ret) |
3327 | return ret; | |
3328 | } | |
2911a35b | 3329 | |
b4716185 | 3330 | return 0; |
2911a35b BW |
3331 | } |
3332 | ||
b5ffc9bc CW |
3333 | static void i915_gem_object_finish_gtt(struct drm_i915_gem_object *obj) |
3334 | { | |
3335 | u32 old_write_domain, old_read_domains; | |
3336 | ||
b5ffc9bc CW |
3337 | /* Force a pagefault for domain tracking on next user access */ |
3338 | i915_gem_release_mmap(obj); | |
3339 | ||
b97c3d9c KP |
3340 | if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0) |
3341 | return; | |
3342 | ||
b5ffc9bc CW |
3343 | old_read_domains = obj->base.read_domains; |
3344 | old_write_domain = obj->base.write_domain; | |
3345 | ||
3346 | obj->base.read_domains &= ~I915_GEM_DOMAIN_GTT; | |
3347 | obj->base.write_domain &= ~I915_GEM_DOMAIN_GTT; | |
3348 | ||
3349 | trace_i915_gem_object_change_domain(obj, | |
3350 | old_read_domains, | |
3351 | old_write_domain); | |
3352 | } | |
3353 | ||
e9f24d5f | 3354 | static int __i915_vma_unbind(struct i915_vma *vma, bool wait) |
673a394b | 3355 | { |
07fe0b12 | 3356 | struct drm_i915_gem_object *obj = vma->obj; |
3e31c6c0 | 3357 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
43e28f09 | 3358 | int ret; |
673a394b | 3359 | |
1c7f4bca | 3360 | if (list_empty(&vma->obj_link)) |
673a394b EA |
3361 | return 0; |
3362 | ||
0ff501cb DV |
3363 | if (!drm_mm_node_allocated(&vma->node)) { |
3364 | i915_gem_vma_destroy(vma); | |
0ff501cb DV |
3365 | return 0; |
3366 | } | |
433544bd | 3367 | |
d7f46fc4 | 3368 | if (vma->pin_count) |
31d8d651 | 3369 | return -EBUSY; |
673a394b | 3370 | |
c4670ad0 CW |
3371 | BUG_ON(obj->pages == NULL); |
3372 | ||
e9f24d5f TU |
3373 | if (wait) { |
3374 | ret = i915_gem_object_wait_rendering(obj, false); | |
3375 | if (ret) | |
3376 | return ret; | |
3377 | } | |
a8198eea | 3378 | |
596c5923 | 3379 | if (vma->is_ggtt && vma->ggtt_view.type == I915_GGTT_VIEW_NORMAL) { |
8b1bc9b4 | 3380 | i915_gem_object_finish_gtt(obj); |
5323fd04 | 3381 | |
8b1bc9b4 DV |
3382 | /* release the fence reg _after_ flushing */ |
3383 | ret = i915_gem_object_put_fence(obj); | |
3384 | if (ret) | |
3385 | return ret; | |
3386 | } | |
96b47b65 | 3387 | |
07fe0b12 | 3388 | trace_i915_vma_unbind(vma); |
db53a302 | 3389 | |
777dc5bb | 3390 | vma->vm->unbind_vma(vma); |
5e562f1d | 3391 | vma->bound = 0; |
6f65e29a | 3392 | |
1c7f4bca | 3393 | list_del_init(&vma->vm_link); |
596c5923 | 3394 | if (vma->is_ggtt) { |
fe14d5f4 TU |
3395 | if (vma->ggtt_view.type == I915_GGTT_VIEW_NORMAL) { |
3396 | obj->map_and_fenceable = false; | |
3397 | } else if (vma->ggtt_view.pages) { | |
3398 | sg_free_table(vma->ggtt_view.pages); | |
3399 | kfree(vma->ggtt_view.pages); | |
fe14d5f4 | 3400 | } |
016a65a3 | 3401 | vma->ggtt_view.pages = NULL; |
fe14d5f4 | 3402 | } |
673a394b | 3403 | |
2f633156 BW |
3404 | drm_mm_remove_node(&vma->node); |
3405 | i915_gem_vma_destroy(vma); | |
3406 | ||
3407 | /* Since the unbound list is global, only move to that list if | |
b93dab6e | 3408 | * no more VMAs exist. */ |
e2273302 | 3409 | if (list_empty(&obj->vma_list)) |
2f633156 | 3410 | list_move_tail(&obj->global_list, &dev_priv->mm.unbound_list); |
673a394b | 3411 | |
70903c3b CW |
3412 | /* And finally now the object is completely decoupled from this vma, |
3413 | * we can drop its hold on the backing storage and allow it to be | |
3414 | * reaped by the shrinker. | |
3415 | */ | |
3416 | i915_gem_object_unpin_pages(obj); | |
3417 | ||
88241785 | 3418 | return 0; |
54cf91dc CW |
3419 | } |
3420 | ||
e9f24d5f TU |
3421 | int i915_vma_unbind(struct i915_vma *vma) |
3422 | { | |
3423 | return __i915_vma_unbind(vma, true); | |
3424 | } | |
3425 | ||
3426 | int __i915_vma_unbind_no_wait(struct i915_vma *vma) | |
3427 | { | |
3428 | return __i915_vma_unbind(vma, false); | |
3429 | } | |
3430 | ||
b2da9fe5 | 3431 | int i915_gpu_idle(struct drm_device *dev) |
4df2faf4 | 3432 | { |
3e31c6c0 | 3433 | struct drm_i915_private *dev_priv = dev->dev_private; |
e2f80391 | 3434 | struct intel_engine_cs *engine; |
b4ac5afc | 3435 | int ret; |
4df2faf4 | 3436 | |
4df2faf4 | 3437 | /* Flush everything onto the inactive list. */ |
b4ac5afc | 3438 | for_each_engine(engine, dev_priv) { |
ecdb5fd8 | 3439 | if (!i915.enable_execlists) { |
73cfa865 JH |
3440 | struct drm_i915_gem_request *req; |
3441 | ||
e2f80391 | 3442 | req = i915_gem_request_alloc(engine, NULL); |
26827088 DG |
3443 | if (IS_ERR(req)) |
3444 | return PTR_ERR(req); | |
73cfa865 | 3445 | |
ba01cc93 | 3446 | ret = i915_switch_context(req); |
73cfa865 JH |
3447 | if (ret) { |
3448 | i915_gem_request_cancel(req); | |
3449 | return ret; | |
3450 | } | |
3451 | ||
75289874 | 3452 | i915_add_request_no_flush(req); |
ecdb5fd8 | 3453 | } |
b6c7488d | 3454 | |
666796da | 3455 | ret = intel_engine_idle(engine); |
1ec14ad3 CW |
3456 | if (ret) |
3457 | return ret; | |
3458 | } | |
4df2faf4 | 3459 | |
b4716185 | 3460 | WARN_ON(i915_verify_lists(dev)); |
8a1a49f9 | 3461 | return 0; |
4df2faf4 DV |
3462 | } |
3463 | ||
4144f9b5 | 3464 | static bool i915_gem_valid_gtt_space(struct i915_vma *vma, |
42d6ab48 CW |
3465 | unsigned long cache_level) |
3466 | { | |
4144f9b5 | 3467 | struct drm_mm_node *gtt_space = &vma->node; |
42d6ab48 CW |
3468 | struct drm_mm_node *other; |
3469 | ||
4144f9b5 CW |
3470 | /* |
3471 | * On some machines we have to be careful when putting differing types | |
3472 | * of snoopable memory together to avoid the prefetcher crossing memory | |
3473 | * domains and dying. During vm initialisation, we decide whether or not | |
3474 | * these constraints apply and set the drm_mm.color_adjust | |
3475 | * appropriately. | |
42d6ab48 | 3476 | */ |
4144f9b5 | 3477 | if (vma->vm->mm.color_adjust == NULL) |
42d6ab48 CW |
3478 | return true; |
3479 | ||
c6cfb325 | 3480 | if (!drm_mm_node_allocated(gtt_space)) |
42d6ab48 CW |
3481 | return true; |
3482 | ||
3483 | if (list_empty(>t_space->node_list)) | |
3484 | return true; | |
3485 | ||
3486 | other = list_entry(gtt_space->node_list.prev, struct drm_mm_node, node_list); | |
3487 | if (other->allocated && !other->hole_follows && other->color != cache_level) | |
3488 | return false; | |
3489 | ||
3490 | other = list_entry(gtt_space->node_list.next, struct drm_mm_node, node_list); | |
3491 | if (other->allocated && !gtt_space->hole_follows && other->color != cache_level) | |
3492 | return false; | |
3493 | ||
3494 | return true; | |
3495 | } | |
3496 | ||
673a394b | 3497 | /** |
91e6711e JL |
3498 | * Finds free space in the GTT aperture and binds the object or a view of it |
3499 | * there. | |
673a394b | 3500 | */ |
262de145 | 3501 | static struct i915_vma * |
07fe0b12 BW |
3502 | i915_gem_object_bind_to_vm(struct drm_i915_gem_object *obj, |
3503 | struct i915_address_space *vm, | |
ec7adb6e | 3504 | const struct i915_ggtt_view *ggtt_view, |
07fe0b12 | 3505 | unsigned alignment, |
ec7adb6e | 3506 | uint64_t flags) |
673a394b | 3507 | { |
05394f39 | 3508 | struct drm_device *dev = obj->base.dev; |
72e96d64 JL |
3509 | struct drm_i915_private *dev_priv = to_i915(dev); |
3510 | struct i915_ggtt *ggtt = &dev_priv->ggtt; | |
65bd342f | 3511 | u32 fence_alignment, unfenced_alignment; |
101b506a MT |
3512 | u32 search_flag, alloc_flag; |
3513 | u64 start, end; | |
65bd342f | 3514 | u64 size, fence_size; |
2f633156 | 3515 | struct i915_vma *vma; |
07f73f69 | 3516 | int ret; |
673a394b | 3517 | |
91e6711e JL |
3518 | if (i915_is_ggtt(vm)) { |
3519 | u32 view_size; | |
3520 | ||
3521 | if (WARN_ON(!ggtt_view)) | |
3522 | return ERR_PTR(-EINVAL); | |
ec7adb6e | 3523 | |
91e6711e JL |
3524 | view_size = i915_ggtt_view_size(obj, ggtt_view); |
3525 | ||
3526 | fence_size = i915_gem_get_gtt_size(dev, | |
3527 | view_size, | |
3528 | obj->tiling_mode); | |
3529 | fence_alignment = i915_gem_get_gtt_alignment(dev, | |
3530 | view_size, | |
3531 | obj->tiling_mode, | |
3532 | true); | |
3533 | unfenced_alignment = i915_gem_get_gtt_alignment(dev, | |
3534 | view_size, | |
3535 | obj->tiling_mode, | |
3536 | false); | |
3537 | size = flags & PIN_MAPPABLE ? fence_size : view_size; | |
3538 | } else { | |
3539 | fence_size = i915_gem_get_gtt_size(dev, | |
3540 | obj->base.size, | |
3541 | obj->tiling_mode); | |
3542 | fence_alignment = i915_gem_get_gtt_alignment(dev, | |
3543 | obj->base.size, | |
3544 | obj->tiling_mode, | |
3545 | true); | |
3546 | unfenced_alignment = | |
3547 | i915_gem_get_gtt_alignment(dev, | |
3548 | obj->base.size, | |
3549 | obj->tiling_mode, | |
3550 | false); | |
3551 | size = flags & PIN_MAPPABLE ? fence_size : obj->base.size; | |
3552 | } | |
a00b10c3 | 3553 | |
101b506a MT |
3554 | start = flags & PIN_OFFSET_BIAS ? flags & PIN_OFFSET_MASK : 0; |
3555 | end = vm->total; | |
3556 | if (flags & PIN_MAPPABLE) | |
72e96d64 | 3557 | end = min_t(u64, end, ggtt->mappable_end); |
101b506a | 3558 | if (flags & PIN_ZONE_4G) |
48ea1e32 | 3559 | end = min_t(u64, end, (1ULL << 32) - PAGE_SIZE); |
101b506a | 3560 | |
673a394b | 3561 | if (alignment == 0) |
1ec9e26d | 3562 | alignment = flags & PIN_MAPPABLE ? fence_alignment : |
5e783301 | 3563 | unfenced_alignment; |
1ec9e26d | 3564 | if (flags & PIN_MAPPABLE && alignment & (fence_alignment - 1)) { |
91e6711e JL |
3565 | DRM_DEBUG("Invalid object (view type=%u) alignment requested %u\n", |
3566 | ggtt_view ? ggtt_view->type : 0, | |
3567 | alignment); | |
262de145 | 3568 | return ERR_PTR(-EINVAL); |
673a394b EA |
3569 | } |
3570 | ||
91e6711e JL |
3571 | /* If binding the object/GGTT view requires more space than the entire |
3572 | * aperture has, reject it early before evicting everything in a vain | |
3573 | * attempt to find space. | |
654fc607 | 3574 | */ |
91e6711e | 3575 | if (size > end) { |
65bd342f | 3576 | DRM_DEBUG("Attempting to bind an object (view type=%u) larger than the aperture: size=%llu > %s aperture=%llu\n", |
91e6711e JL |
3577 | ggtt_view ? ggtt_view->type : 0, |
3578 | size, | |
1ec9e26d | 3579 | flags & PIN_MAPPABLE ? "mappable" : "total", |
d23db88c | 3580 | end); |
262de145 | 3581 | return ERR_PTR(-E2BIG); |
654fc607 CW |
3582 | } |
3583 | ||
37e680a1 | 3584 | ret = i915_gem_object_get_pages(obj); |
6c085a72 | 3585 | if (ret) |
262de145 | 3586 | return ERR_PTR(ret); |
6c085a72 | 3587 | |
fbdda6fb CW |
3588 | i915_gem_object_pin_pages(obj); |
3589 | ||
ec7adb6e JL |
3590 | vma = ggtt_view ? i915_gem_obj_lookup_or_create_ggtt_vma(obj, ggtt_view) : |
3591 | i915_gem_obj_lookup_or_create_vma(obj, vm); | |
3592 | ||
262de145 | 3593 | if (IS_ERR(vma)) |
bc6bc15b | 3594 | goto err_unpin; |
2f633156 | 3595 | |
506a8e87 CW |
3596 | if (flags & PIN_OFFSET_FIXED) { |
3597 | uint64_t offset = flags & PIN_OFFSET_MASK; | |
3598 | ||
3599 | if (offset & (alignment - 1) || offset + size > end) { | |
3600 | ret = -EINVAL; | |
3601 | goto err_free_vma; | |
3602 | } | |
3603 | vma->node.start = offset; | |
3604 | vma->node.size = size; | |
3605 | vma->node.color = obj->cache_level; | |
3606 | ret = drm_mm_reserve_node(&vm->mm, &vma->node); | |
3607 | if (ret) { | |
3608 | ret = i915_gem_evict_for_vma(vma); | |
3609 | if (ret == 0) | |
3610 | ret = drm_mm_reserve_node(&vm->mm, &vma->node); | |
3611 | } | |
3612 | if (ret) | |
3613 | goto err_free_vma; | |
101b506a | 3614 | } else { |
506a8e87 CW |
3615 | if (flags & PIN_HIGH) { |
3616 | search_flag = DRM_MM_SEARCH_BELOW; | |
3617 | alloc_flag = DRM_MM_CREATE_TOP; | |
3618 | } else { | |
3619 | search_flag = DRM_MM_SEARCH_DEFAULT; | |
3620 | alloc_flag = DRM_MM_CREATE_DEFAULT; | |
3621 | } | |
101b506a | 3622 | |
0a9ae0d7 | 3623 | search_free: |
506a8e87 CW |
3624 | ret = drm_mm_insert_node_in_range_generic(&vm->mm, &vma->node, |
3625 | size, alignment, | |
3626 | obj->cache_level, | |
3627 | start, end, | |
3628 | search_flag, | |
3629 | alloc_flag); | |
3630 | if (ret) { | |
3631 | ret = i915_gem_evict_something(dev, vm, size, alignment, | |
3632 | obj->cache_level, | |
3633 | start, end, | |
3634 | flags); | |
3635 | if (ret == 0) | |
3636 | goto search_free; | |
9731129c | 3637 | |
506a8e87 CW |
3638 | goto err_free_vma; |
3639 | } | |
673a394b | 3640 | } |
4144f9b5 | 3641 | if (WARN_ON(!i915_gem_valid_gtt_space(vma, obj->cache_level))) { |
2f633156 | 3642 | ret = -EINVAL; |
bc6bc15b | 3643 | goto err_remove_node; |
673a394b EA |
3644 | } |
3645 | ||
fe14d5f4 | 3646 | trace_i915_vma_bind(vma, flags); |
0875546c | 3647 | ret = i915_vma_bind(vma, obj->cache_level, flags); |
fe14d5f4 | 3648 | if (ret) |
e2273302 | 3649 | goto err_remove_node; |
fe14d5f4 | 3650 | |
35c20a60 | 3651 | list_move_tail(&obj->global_list, &dev_priv->mm.bound_list); |
1c7f4bca | 3652 | list_add_tail(&vma->vm_link, &vm->inactive_list); |
bf1a1092 | 3653 | |
262de145 | 3654 | return vma; |
2f633156 | 3655 | |
bc6bc15b | 3656 | err_remove_node: |
6286ef9b | 3657 | drm_mm_remove_node(&vma->node); |
bc6bc15b | 3658 | err_free_vma: |
2f633156 | 3659 | i915_gem_vma_destroy(vma); |
262de145 | 3660 | vma = ERR_PTR(ret); |
bc6bc15b | 3661 | err_unpin: |
2f633156 | 3662 | i915_gem_object_unpin_pages(obj); |
262de145 | 3663 | return vma; |
673a394b EA |
3664 | } |
3665 | ||
000433b6 | 3666 | bool |
2c22569b CW |
3667 | i915_gem_clflush_object(struct drm_i915_gem_object *obj, |
3668 | bool force) | |
673a394b | 3669 | { |
673a394b EA |
3670 | /* If we don't have a page list set up, then we're not pinned |
3671 | * to GPU, and we can ignore the cache flush because it'll happen | |
3672 | * again at bind time. | |
3673 | */ | |
05394f39 | 3674 | if (obj->pages == NULL) |
000433b6 | 3675 | return false; |
673a394b | 3676 | |
769ce464 ID |
3677 | /* |
3678 | * Stolen memory is always coherent with the GPU as it is explicitly | |
3679 | * marked as wc by the system, or the system is cache-coherent. | |
3680 | */ | |
6a2c4232 | 3681 | if (obj->stolen || obj->phys_handle) |
000433b6 | 3682 | return false; |
769ce464 | 3683 | |
9c23f7fc CW |
3684 | /* If the GPU is snooping the contents of the CPU cache, |
3685 | * we do not need to manually clear the CPU cache lines. However, | |
3686 | * the caches are only snooped when the render cache is | |
3687 | * flushed/invalidated. As we always have to emit invalidations | |
3688 | * and flushes when moving into and out of the RENDER domain, correct | |
3689 | * snooping behaviour occurs naturally as the result of our domain | |
3690 | * tracking. | |
3691 | */ | |
0f71979a CW |
3692 | if (!force && cpu_cache_is_coherent(obj->base.dev, obj->cache_level)) { |
3693 | obj->cache_dirty = true; | |
000433b6 | 3694 | return false; |
0f71979a | 3695 | } |
9c23f7fc | 3696 | |
1c5d22f7 | 3697 | trace_i915_gem_object_clflush(obj); |
9da3da66 | 3698 | drm_clflush_sg(obj->pages); |
0f71979a | 3699 | obj->cache_dirty = false; |
000433b6 CW |
3700 | |
3701 | return true; | |
e47c68e9 EA |
3702 | } |
3703 | ||
3704 | /** Flushes the GTT write domain for the object if it's dirty. */ | |
3705 | static void | |
05394f39 | 3706 | i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj) |
e47c68e9 | 3707 | { |
1c5d22f7 CW |
3708 | uint32_t old_write_domain; |
3709 | ||
05394f39 | 3710 | if (obj->base.write_domain != I915_GEM_DOMAIN_GTT) |
e47c68e9 EA |
3711 | return; |
3712 | ||
63256ec5 | 3713 | /* No actual flushing is required for the GTT write domain. Writes |
e47c68e9 EA |
3714 | * to it immediately go to main memory as far as we know, so there's |
3715 | * no chipset flush. It also doesn't land in render cache. | |
63256ec5 CW |
3716 | * |
3717 | * However, we do have to enforce the order so that all writes through | |
3718 | * the GTT land before any writes to the device, such as updates to | |
3719 | * the GATT itself. | |
e47c68e9 | 3720 | */ |
63256ec5 CW |
3721 | wmb(); |
3722 | ||
05394f39 CW |
3723 | old_write_domain = obj->base.write_domain; |
3724 | obj->base.write_domain = 0; | |
1c5d22f7 | 3725 | |
de152b62 | 3726 | intel_fb_obj_flush(obj, false, ORIGIN_GTT); |
f99d7069 | 3727 | |
1c5d22f7 | 3728 | trace_i915_gem_object_change_domain(obj, |
05394f39 | 3729 | obj->base.read_domains, |
1c5d22f7 | 3730 | old_write_domain); |
e47c68e9 EA |
3731 | } |
3732 | ||
3733 | /** Flushes the CPU write domain for the object if it's dirty. */ | |
3734 | static void | |
e62b59e4 | 3735 | i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj) |
e47c68e9 | 3736 | { |
1c5d22f7 | 3737 | uint32_t old_write_domain; |
e47c68e9 | 3738 | |
05394f39 | 3739 | if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) |
e47c68e9 EA |
3740 | return; |
3741 | ||
e62b59e4 | 3742 | if (i915_gem_clflush_object(obj, obj->pin_display)) |
000433b6 CW |
3743 | i915_gem_chipset_flush(obj->base.dev); |
3744 | ||
05394f39 CW |
3745 | old_write_domain = obj->base.write_domain; |
3746 | obj->base.write_domain = 0; | |
1c5d22f7 | 3747 | |
de152b62 | 3748 | intel_fb_obj_flush(obj, false, ORIGIN_CPU); |
f99d7069 | 3749 | |
1c5d22f7 | 3750 | trace_i915_gem_object_change_domain(obj, |
05394f39 | 3751 | obj->base.read_domains, |
1c5d22f7 | 3752 | old_write_domain); |
e47c68e9 EA |
3753 | } |
3754 | ||
2ef7eeaa EA |
3755 | /** |
3756 | * Moves a single object to the GTT read, and possibly write domain. | |
3757 | * | |
3758 | * This function returns when the move is complete, including waiting on | |
3759 | * flushes to occur. | |
3760 | */ | |
79e53945 | 3761 | int |
2021746e | 3762 | i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write) |
2ef7eeaa | 3763 | { |
72e96d64 JL |
3764 | struct drm_device *dev = obj->base.dev; |
3765 | struct drm_i915_private *dev_priv = to_i915(dev); | |
3766 | struct i915_ggtt *ggtt = &dev_priv->ggtt; | |
1c5d22f7 | 3767 | uint32_t old_write_domain, old_read_domains; |
43566ded | 3768 | struct i915_vma *vma; |
e47c68e9 | 3769 | int ret; |
2ef7eeaa | 3770 | |
8d7e3de1 CW |
3771 | if (obj->base.write_domain == I915_GEM_DOMAIN_GTT) |
3772 | return 0; | |
3773 | ||
0201f1ec | 3774 | ret = i915_gem_object_wait_rendering(obj, !write); |
88241785 CW |
3775 | if (ret) |
3776 | return ret; | |
3777 | ||
43566ded CW |
3778 | /* Flush and acquire obj->pages so that we are coherent through |
3779 | * direct access in memory with previous cached writes through | |
3780 | * shmemfs and that our cache domain tracking remains valid. | |
3781 | * For example, if the obj->filp was moved to swap without us | |
3782 | * being notified and releasing the pages, we would mistakenly | |
3783 | * continue to assume that the obj remained out of the CPU cached | |
3784 | * domain. | |
3785 | */ | |
3786 | ret = i915_gem_object_get_pages(obj); | |
3787 | if (ret) | |
3788 | return ret; | |
3789 | ||
e62b59e4 | 3790 | i915_gem_object_flush_cpu_write_domain(obj); |
1c5d22f7 | 3791 | |
d0a57789 CW |
3792 | /* Serialise direct access to this object with the barriers for |
3793 | * coherent writes from the GPU, by effectively invalidating the | |
3794 | * GTT domain upon first access. | |
3795 | */ | |
3796 | if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0) | |
3797 | mb(); | |
3798 | ||
05394f39 CW |
3799 | old_write_domain = obj->base.write_domain; |
3800 | old_read_domains = obj->base.read_domains; | |
1c5d22f7 | 3801 | |
e47c68e9 EA |
3802 | /* It should now be out of any other write domains, and we can update |
3803 | * the domain values for our changes. | |
3804 | */ | |
05394f39 CW |
3805 | BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_GTT) != 0); |
3806 | obj->base.read_domains |= I915_GEM_DOMAIN_GTT; | |
e47c68e9 | 3807 | if (write) { |
05394f39 CW |
3808 | obj->base.read_domains = I915_GEM_DOMAIN_GTT; |
3809 | obj->base.write_domain = I915_GEM_DOMAIN_GTT; | |
3810 | obj->dirty = 1; | |
2ef7eeaa EA |
3811 | } |
3812 | ||
1c5d22f7 CW |
3813 | trace_i915_gem_object_change_domain(obj, |
3814 | old_read_domains, | |
3815 | old_write_domain); | |
3816 | ||
8325a09d | 3817 | /* And bump the LRU for this access */ |
43566ded CW |
3818 | vma = i915_gem_obj_to_ggtt(obj); |
3819 | if (vma && drm_mm_node_allocated(&vma->node) && !obj->active) | |
1c7f4bca | 3820 | list_move_tail(&vma->vm_link, |
72e96d64 | 3821 | &ggtt->base.inactive_list); |
8325a09d | 3822 | |
e47c68e9 EA |
3823 | return 0; |
3824 | } | |
3825 | ||
ef55f92a CW |
3826 | /** |
3827 | * Changes the cache-level of an object across all VMA. | |
3828 | * | |
3829 | * After this function returns, the object will be in the new cache-level | |
3830 | * across all GTT and the contents of the backing storage will be coherent, | |
3831 | * with respect to the new cache-level. In order to keep the backing storage | |
3832 | * coherent for all users, we only allow a single cache level to be set | |
3833 | * globally on the object and prevent it from being changed whilst the | |
3834 | * hardware is reading from the object. That is if the object is currently | |
3835 | * on the scanout it will be set to uncached (or equivalent display | |
3836 | * cache coherency) and all non-MOCS GPU access will also be uncached so | |
3837 | * that all direct access to the scanout remains coherent. | |
3838 | */ | |
e4ffd173 CW |
3839 | int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj, |
3840 | enum i915_cache_level cache_level) | |
3841 | { | |
7bddb01f | 3842 | struct drm_device *dev = obj->base.dev; |
df6f783a | 3843 | struct i915_vma *vma, *next; |
ef55f92a | 3844 | bool bound = false; |
ed75a55b | 3845 | int ret = 0; |
e4ffd173 CW |
3846 | |
3847 | if (obj->cache_level == cache_level) | |
ed75a55b | 3848 | goto out; |
e4ffd173 | 3849 | |
ef55f92a CW |
3850 | /* Inspect the list of currently bound VMA and unbind any that would |
3851 | * be invalid given the new cache-level. This is principally to | |
3852 | * catch the issue of the CS prefetch crossing page boundaries and | |
3853 | * reading an invalid PTE on older architectures. | |
3854 | */ | |
1c7f4bca | 3855 | list_for_each_entry_safe(vma, next, &obj->vma_list, obj_link) { |
ef55f92a CW |
3856 | if (!drm_mm_node_allocated(&vma->node)) |
3857 | continue; | |
3858 | ||
3859 | if (vma->pin_count) { | |
3860 | DRM_DEBUG("can not change the cache level of pinned objects\n"); | |
3861 | return -EBUSY; | |
3862 | } | |
3863 | ||
4144f9b5 | 3864 | if (!i915_gem_valid_gtt_space(vma, cache_level)) { |
07fe0b12 | 3865 | ret = i915_vma_unbind(vma); |
3089c6f2 BW |
3866 | if (ret) |
3867 | return ret; | |
ef55f92a CW |
3868 | } else |
3869 | bound = true; | |
42d6ab48 CW |
3870 | } |
3871 | ||
ef55f92a CW |
3872 | /* We can reuse the existing drm_mm nodes but need to change the |
3873 | * cache-level on the PTE. We could simply unbind them all and | |
3874 | * rebind with the correct cache-level on next use. However since | |
3875 | * we already have a valid slot, dma mapping, pages etc, we may as | |
3876 | * rewrite the PTE in the belief that doing so tramples upon less | |
3877 | * state and so involves less work. | |
3878 | */ | |
3879 | if (bound) { | |
3880 | /* Before we change the PTE, the GPU must not be accessing it. | |
3881 | * If we wait upon the object, we know that all the bound | |
3882 | * VMA are no longer active. | |
3883 | */ | |
2e2f351d | 3884 | ret = i915_gem_object_wait_rendering(obj, false); |
e4ffd173 CW |
3885 | if (ret) |
3886 | return ret; | |
3887 | ||
ef55f92a CW |
3888 | if (!HAS_LLC(dev) && cache_level != I915_CACHE_NONE) { |
3889 | /* Access to snoopable pages through the GTT is | |
3890 | * incoherent and on some machines causes a hard | |
3891 | * lockup. Relinquish the CPU mmaping to force | |
3892 | * userspace to refault in the pages and we can | |
3893 | * then double check if the GTT mapping is still | |
3894 | * valid for that pointer access. | |
3895 | */ | |
3896 | i915_gem_release_mmap(obj); | |
3897 | ||
3898 | /* As we no longer need a fence for GTT access, | |
3899 | * we can relinquish it now (and so prevent having | |
3900 | * to steal a fence from someone else on the next | |
3901 | * fence request). Note GPU activity would have | |
3902 | * dropped the fence as all snoopable access is | |
3903 | * supposed to be linear. | |
3904 | */ | |
e4ffd173 CW |
3905 | ret = i915_gem_object_put_fence(obj); |
3906 | if (ret) | |
3907 | return ret; | |
ef55f92a CW |
3908 | } else { |
3909 | /* We either have incoherent backing store and | |
3910 | * so no GTT access or the architecture is fully | |
3911 | * coherent. In such cases, existing GTT mmaps | |
3912 | * ignore the cache bit in the PTE and we can | |
3913 | * rewrite it without confusing the GPU or having | |
3914 | * to force userspace to fault back in its mmaps. | |
3915 | */ | |
e4ffd173 CW |
3916 | } |
3917 | ||
1c7f4bca | 3918 | list_for_each_entry(vma, &obj->vma_list, obj_link) { |
ef55f92a CW |
3919 | if (!drm_mm_node_allocated(&vma->node)) |
3920 | continue; | |
3921 | ||
3922 | ret = i915_vma_bind(vma, cache_level, PIN_UPDATE); | |
3923 | if (ret) | |
3924 | return ret; | |
3925 | } | |
e4ffd173 CW |
3926 | } |
3927 | ||
1c7f4bca | 3928 | list_for_each_entry(vma, &obj->vma_list, obj_link) |
2c22569b CW |
3929 | vma->node.color = cache_level; |
3930 | obj->cache_level = cache_level; | |
3931 | ||
ed75a55b | 3932 | out: |
ef55f92a CW |
3933 | /* Flush the dirty CPU caches to the backing storage so that the |
3934 | * object is now coherent at its new cache level (with respect | |
3935 | * to the access domain). | |
3936 | */ | |
0f71979a CW |
3937 | if (obj->cache_dirty && |
3938 | obj->base.write_domain != I915_GEM_DOMAIN_CPU && | |
3939 | cpu_write_needs_clflush(obj)) { | |
3940 | if (i915_gem_clflush_object(obj, true)) | |
3941 | i915_gem_chipset_flush(obj->base.dev); | |
e4ffd173 CW |
3942 | } |
3943 | ||
e4ffd173 CW |
3944 | return 0; |
3945 | } | |
3946 | ||
199adf40 BW |
3947 | int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data, |
3948 | struct drm_file *file) | |
e6994aee | 3949 | { |
199adf40 | 3950 | struct drm_i915_gem_caching *args = data; |
e6994aee | 3951 | struct drm_i915_gem_object *obj; |
e6994aee CW |
3952 | |
3953 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); | |
432be69d CW |
3954 | if (&obj->base == NULL) |
3955 | return -ENOENT; | |
e6994aee | 3956 | |
651d794f CW |
3957 | switch (obj->cache_level) { |
3958 | case I915_CACHE_LLC: | |
3959 | case I915_CACHE_L3_LLC: | |
3960 | args->caching = I915_CACHING_CACHED; | |
3961 | break; | |
3962 | ||
4257d3ba CW |
3963 | case I915_CACHE_WT: |
3964 | args->caching = I915_CACHING_DISPLAY; | |
3965 | break; | |
3966 | ||
651d794f CW |
3967 | default: |
3968 | args->caching = I915_CACHING_NONE; | |
3969 | break; | |
3970 | } | |
e6994aee | 3971 | |
432be69d CW |
3972 | drm_gem_object_unreference_unlocked(&obj->base); |
3973 | return 0; | |
e6994aee CW |
3974 | } |
3975 | ||
199adf40 BW |
3976 | int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data, |
3977 | struct drm_file *file) | |
e6994aee | 3978 | { |
fd0fe6ac | 3979 | struct drm_i915_private *dev_priv = dev->dev_private; |
199adf40 | 3980 | struct drm_i915_gem_caching *args = data; |
e6994aee CW |
3981 | struct drm_i915_gem_object *obj; |
3982 | enum i915_cache_level level; | |
3983 | int ret; | |
3984 | ||
199adf40 BW |
3985 | switch (args->caching) { |
3986 | case I915_CACHING_NONE: | |
e6994aee CW |
3987 | level = I915_CACHE_NONE; |
3988 | break; | |
199adf40 | 3989 | case I915_CACHING_CACHED: |
e5756c10 ID |
3990 | /* |
3991 | * Due to a HW issue on BXT A stepping, GPU stores via a | |
3992 | * snooped mapping may leave stale data in a corresponding CPU | |
3993 | * cacheline, whereas normally such cachelines would get | |
3994 | * invalidated. | |
3995 | */ | |
ca377809 | 3996 | if (!HAS_LLC(dev) && !HAS_SNOOP(dev)) |
e5756c10 ID |
3997 | return -ENODEV; |
3998 | ||
e6994aee CW |
3999 | level = I915_CACHE_LLC; |
4000 | break; | |
4257d3ba CW |
4001 | case I915_CACHING_DISPLAY: |
4002 | level = HAS_WT(dev) ? I915_CACHE_WT : I915_CACHE_NONE; | |
4003 | break; | |
e6994aee CW |
4004 | default: |
4005 | return -EINVAL; | |
4006 | } | |
4007 | ||
fd0fe6ac ID |
4008 | intel_runtime_pm_get(dev_priv); |
4009 | ||
3bc2913e BW |
4010 | ret = i915_mutex_lock_interruptible(dev); |
4011 | if (ret) | |
fd0fe6ac | 4012 | goto rpm_put; |
3bc2913e | 4013 | |
e6994aee CW |
4014 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
4015 | if (&obj->base == NULL) { | |
4016 | ret = -ENOENT; | |
4017 | goto unlock; | |
4018 | } | |
4019 | ||
4020 | ret = i915_gem_object_set_cache_level(obj, level); | |
4021 | ||
4022 | drm_gem_object_unreference(&obj->base); | |
4023 | unlock: | |
4024 | mutex_unlock(&dev->struct_mutex); | |
fd0fe6ac ID |
4025 | rpm_put: |
4026 | intel_runtime_pm_put(dev_priv); | |
4027 | ||
e6994aee CW |
4028 | return ret; |
4029 | } | |
4030 | ||
b9241ea3 | 4031 | /* |
2da3b9b9 CW |
4032 | * Prepare buffer for display plane (scanout, cursors, etc). |
4033 | * Can be called from an uninterruptible phase (modesetting) and allows | |
4034 | * any flushes to be pipelined (for pageflips). | |
b9241ea3 ZW |
4035 | */ |
4036 | int | |
2da3b9b9 CW |
4037 | i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj, |
4038 | u32 alignment, | |
e6617330 | 4039 | const struct i915_ggtt_view *view) |
b9241ea3 | 4040 | { |
2da3b9b9 | 4041 | u32 old_read_domains, old_write_domain; |
b9241ea3 ZW |
4042 | int ret; |
4043 | ||
cc98b413 CW |
4044 | /* Mark the pin_display early so that we account for the |
4045 | * display coherency whilst setting up the cache domains. | |
4046 | */ | |
8a0c39b1 | 4047 | obj->pin_display++; |
cc98b413 | 4048 | |
a7ef0640 EA |
4049 | /* The display engine is not coherent with the LLC cache on gen6. As |
4050 | * a result, we make sure that the pinning that is about to occur is | |
4051 | * done with uncached PTEs. This is lowest common denominator for all | |
4052 | * chipsets. | |
4053 | * | |
4054 | * However for gen6+, we could do better by using the GFDT bit instead | |
4055 | * of uncaching, which would allow us to flush all the LLC-cached data | |
4056 | * with that bit in the PTE to main memory with just one PIPE_CONTROL. | |
4057 | */ | |
651d794f CW |
4058 | ret = i915_gem_object_set_cache_level(obj, |
4059 | HAS_WT(obj->base.dev) ? I915_CACHE_WT : I915_CACHE_NONE); | |
a7ef0640 | 4060 | if (ret) |
cc98b413 | 4061 | goto err_unpin_display; |
a7ef0640 | 4062 | |
2da3b9b9 CW |
4063 | /* As the user may map the buffer once pinned in the display plane |
4064 | * (e.g. libkms for the bootup splash), we have to ensure that we | |
4065 | * always use map_and_fenceable for all scanout buffers. | |
4066 | */ | |
50470bb0 TU |
4067 | ret = i915_gem_object_ggtt_pin(obj, view, alignment, |
4068 | view->type == I915_GGTT_VIEW_NORMAL ? | |
4069 | PIN_MAPPABLE : 0); | |
2da3b9b9 | 4070 | if (ret) |
cc98b413 | 4071 | goto err_unpin_display; |
2da3b9b9 | 4072 | |
e62b59e4 | 4073 | i915_gem_object_flush_cpu_write_domain(obj); |
b118c1e3 | 4074 | |
2da3b9b9 | 4075 | old_write_domain = obj->base.write_domain; |
05394f39 | 4076 | old_read_domains = obj->base.read_domains; |
2da3b9b9 CW |
4077 | |
4078 | /* It should now be out of any other write domains, and we can update | |
4079 | * the domain values for our changes. | |
4080 | */ | |
e5f1d962 | 4081 | obj->base.write_domain = 0; |
05394f39 | 4082 | obj->base.read_domains |= I915_GEM_DOMAIN_GTT; |
b9241ea3 ZW |
4083 | |
4084 | trace_i915_gem_object_change_domain(obj, | |
4085 | old_read_domains, | |
2da3b9b9 | 4086 | old_write_domain); |
b9241ea3 ZW |
4087 | |
4088 | return 0; | |
cc98b413 CW |
4089 | |
4090 | err_unpin_display: | |
8a0c39b1 | 4091 | obj->pin_display--; |
cc98b413 CW |
4092 | return ret; |
4093 | } | |
4094 | ||
4095 | void | |
e6617330 TU |
4096 | i915_gem_object_unpin_from_display_plane(struct drm_i915_gem_object *obj, |
4097 | const struct i915_ggtt_view *view) | |
cc98b413 | 4098 | { |
8a0c39b1 TU |
4099 | if (WARN_ON(obj->pin_display == 0)) |
4100 | return; | |
4101 | ||
e6617330 TU |
4102 | i915_gem_object_ggtt_unpin_view(obj, view); |
4103 | ||
8a0c39b1 | 4104 | obj->pin_display--; |
b9241ea3 ZW |
4105 | } |
4106 | ||
e47c68e9 EA |
4107 | /** |
4108 | * Moves a single object to the CPU read, and possibly write domain. | |
4109 | * | |
4110 | * This function returns when the move is complete, including waiting on | |
4111 | * flushes to occur. | |
4112 | */ | |
dabdfe02 | 4113 | int |
919926ae | 4114 | i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write) |
e47c68e9 | 4115 | { |
1c5d22f7 | 4116 | uint32_t old_write_domain, old_read_domains; |
e47c68e9 EA |
4117 | int ret; |
4118 | ||
8d7e3de1 CW |
4119 | if (obj->base.write_domain == I915_GEM_DOMAIN_CPU) |
4120 | return 0; | |
4121 | ||
0201f1ec | 4122 | ret = i915_gem_object_wait_rendering(obj, !write); |
88241785 CW |
4123 | if (ret) |
4124 | return ret; | |
4125 | ||
e47c68e9 | 4126 | i915_gem_object_flush_gtt_write_domain(obj); |
2ef7eeaa | 4127 | |
05394f39 CW |
4128 | old_write_domain = obj->base.write_domain; |
4129 | old_read_domains = obj->base.read_domains; | |
1c5d22f7 | 4130 | |
e47c68e9 | 4131 | /* Flush the CPU cache if it's still invalid. */ |
05394f39 | 4132 | if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0) { |
2c22569b | 4133 | i915_gem_clflush_object(obj, false); |
2ef7eeaa | 4134 | |
05394f39 | 4135 | obj->base.read_domains |= I915_GEM_DOMAIN_CPU; |
2ef7eeaa EA |
4136 | } |
4137 | ||
4138 | /* It should now be out of any other write domains, and we can update | |
4139 | * the domain values for our changes. | |
4140 | */ | |
05394f39 | 4141 | BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_CPU) != 0); |
e47c68e9 EA |
4142 | |
4143 | /* If we're writing through the CPU, then the GPU read domains will | |
4144 | * need to be invalidated at next use. | |
4145 | */ | |
4146 | if (write) { | |
05394f39 CW |
4147 | obj->base.read_domains = I915_GEM_DOMAIN_CPU; |
4148 | obj->base.write_domain = I915_GEM_DOMAIN_CPU; | |
e47c68e9 | 4149 | } |
2ef7eeaa | 4150 | |
1c5d22f7 CW |
4151 | trace_i915_gem_object_change_domain(obj, |
4152 | old_read_domains, | |
4153 | old_write_domain); | |
4154 | ||
2ef7eeaa EA |
4155 | return 0; |
4156 | } | |
4157 | ||
673a394b EA |
4158 | /* Throttle our rendering by waiting until the ring has completed our requests |
4159 | * emitted over 20 msec ago. | |
4160 | * | |
b962442e EA |
4161 | * Note that if we were to use the current jiffies each time around the loop, |
4162 | * we wouldn't escape the function with any frames outstanding if the time to | |
4163 | * render a frame was over 20ms. | |
4164 | * | |
673a394b EA |
4165 | * This should get us reasonable parallelism between CPU and GPU but also |
4166 | * relatively low latency when blocking on a particular request to finish. | |
4167 | */ | |
40a5f0de | 4168 | static int |
f787a5f5 | 4169 | i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file) |
40a5f0de | 4170 | { |
f787a5f5 CW |
4171 | struct drm_i915_private *dev_priv = dev->dev_private; |
4172 | struct drm_i915_file_private *file_priv = file->driver_priv; | |
d0bc54f2 | 4173 | unsigned long recent_enough = jiffies - DRM_I915_THROTTLE_JIFFIES; |
54fb2411 | 4174 | struct drm_i915_gem_request *request, *target = NULL; |
f787a5f5 | 4175 | int ret; |
93533c29 | 4176 | |
308887aa DV |
4177 | ret = i915_gem_wait_for_error(&dev_priv->gpu_error); |
4178 | if (ret) | |
4179 | return ret; | |
4180 | ||
f4457ae7 CW |
4181 | /* ABI: return -EIO if already wedged */ |
4182 | if (i915_terminally_wedged(&dev_priv->gpu_error)) | |
4183 | return -EIO; | |
e110e8d6 | 4184 | |
1c25595f | 4185 | spin_lock(&file_priv->mm.lock); |
f787a5f5 | 4186 | list_for_each_entry(request, &file_priv->mm.request_list, client_list) { |
b962442e EA |
4187 | if (time_after_eq(request->emitted_jiffies, recent_enough)) |
4188 | break; | |
40a5f0de | 4189 | |
fcfa423c JH |
4190 | /* |
4191 | * Note that the request might not have been submitted yet. | |
4192 | * In which case emitted_jiffies will be zero. | |
4193 | */ | |
4194 | if (!request->emitted_jiffies) | |
4195 | continue; | |
4196 | ||
54fb2411 | 4197 | target = request; |
b962442e | 4198 | } |
ff865885 JH |
4199 | if (target) |
4200 | i915_gem_request_reference(target); | |
1c25595f | 4201 | spin_unlock(&file_priv->mm.lock); |
40a5f0de | 4202 | |
54fb2411 | 4203 | if (target == NULL) |
f787a5f5 | 4204 | return 0; |
2bc43b5c | 4205 | |
299259a3 | 4206 | ret = __i915_wait_request(target, true, NULL, NULL); |
f787a5f5 CW |
4207 | if (ret == 0) |
4208 | queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, 0); | |
40a5f0de | 4209 | |
41037f9f | 4210 | i915_gem_request_unreference__unlocked(target); |
ff865885 | 4211 | |
40a5f0de EA |
4212 | return ret; |
4213 | } | |
4214 | ||
d23db88c CW |
4215 | static bool |
4216 | i915_vma_misplaced(struct i915_vma *vma, uint32_t alignment, uint64_t flags) | |
4217 | { | |
4218 | struct drm_i915_gem_object *obj = vma->obj; | |
4219 | ||
4220 | if (alignment && | |
4221 | vma->node.start & (alignment - 1)) | |
4222 | return true; | |
4223 | ||
4224 | if (flags & PIN_MAPPABLE && !obj->map_and_fenceable) | |
4225 | return true; | |
4226 | ||
4227 | if (flags & PIN_OFFSET_BIAS && | |
4228 | vma->node.start < (flags & PIN_OFFSET_MASK)) | |
4229 | return true; | |
4230 | ||
506a8e87 CW |
4231 | if (flags & PIN_OFFSET_FIXED && |
4232 | vma->node.start != (flags & PIN_OFFSET_MASK)) | |
4233 | return true; | |
4234 | ||
d23db88c CW |
4235 | return false; |
4236 | } | |
4237 | ||
d0710abb CW |
4238 | void __i915_vma_set_map_and_fenceable(struct i915_vma *vma) |
4239 | { | |
4240 | struct drm_i915_gem_object *obj = vma->obj; | |
4241 | bool mappable, fenceable; | |
4242 | u32 fence_size, fence_alignment; | |
4243 | ||
4244 | fence_size = i915_gem_get_gtt_size(obj->base.dev, | |
4245 | obj->base.size, | |
4246 | obj->tiling_mode); | |
4247 | fence_alignment = i915_gem_get_gtt_alignment(obj->base.dev, | |
4248 | obj->base.size, | |
4249 | obj->tiling_mode, | |
4250 | true); | |
4251 | ||
4252 | fenceable = (vma->node.size == fence_size && | |
4253 | (vma->node.start & (fence_alignment - 1)) == 0); | |
4254 | ||
4255 | mappable = (vma->node.start + fence_size <= | |
62106b4f | 4256 | to_i915(obj->base.dev)->ggtt.mappable_end); |
d0710abb CW |
4257 | |
4258 | obj->map_and_fenceable = mappable && fenceable; | |
4259 | } | |
4260 | ||
ec7adb6e JL |
4261 | static int |
4262 | i915_gem_object_do_pin(struct drm_i915_gem_object *obj, | |
4263 | struct i915_address_space *vm, | |
4264 | const struct i915_ggtt_view *ggtt_view, | |
4265 | uint32_t alignment, | |
4266 | uint64_t flags) | |
673a394b | 4267 | { |
6e7186af | 4268 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
07fe0b12 | 4269 | struct i915_vma *vma; |
ef79e17c | 4270 | unsigned bound; |
673a394b EA |
4271 | int ret; |
4272 | ||
6e7186af BW |
4273 | if (WARN_ON(vm == &dev_priv->mm.aliasing_ppgtt->base)) |
4274 | return -ENODEV; | |
4275 | ||
bf3d149b | 4276 | if (WARN_ON(flags & (PIN_GLOBAL | PIN_MAPPABLE) && !i915_is_ggtt(vm))) |
1ec9e26d | 4277 | return -EINVAL; |
07fe0b12 | 4278 | |
c826c449 CW |
4279 | if (WARN_ON((flags & (PIN_MAPPABLE | PIN_GLOBAL)) == PIN_MAPPABLE)) |
4280 | return -EINVAL; | |
4281 | ||
ec7adb6e JL |
4282 | if (WARN_ON(i915_is_ggtt(vm) != !!ggtt_view)) |
4283 | return -EINVAL; | |
4284 | ||
4285 | vma = ggtt_view ? i915_gem_obj_to_ggtt_view(obj, ggtt_view) : | |
4286 | i915_gem_obj_to_vma(obj, vm); | |
4287 | ||
07fe0b12 | 4288 | if (vma) { |
d7f46fc4 BW |
4289 | if (WARN_ON(vma->pin_count == DRM_I915_GEM_OBJECT_MAX_PIN_COUNT)) |
4290 | return -EBUSY; | |
4291 | ||
d23db88c | 4292 | if (i915_vma_misplaced(vma, alignment, flags)) { |
d7f46fc4 | 4293 | WARN(vma->pin_count, |
ec7adb6e | 4294 | "bo is already pinned in %s with incorrect alignment:" |
088e0df4 | 4295 | " offset=%08x %08x, req.alignment=%x, req.map_and_fenceable=%d," |
75e9e915 | 4296 | " obj->map_and_fenceable=%d\n", |
ec7adb6e | 4297 | ggtt_view ? "ggtt" : "ppgtt", |
088e0df4 MT |
4298 | upper_32_bits(vma->node.start), |
4299 | lower_32_bits(vma->node.start), | |
fe14d5f4 | 4300 | alignment, |
d23db88c | 4301 | !!(flags & PIN_MAPPABLE), |
05394f39 | 4302 | obj->map_and_fenceable); |
07fe0b12 | 4303 | ret = i915_vma_unbind(vma); |
ac0c6b5a CW |
4304 | if (ret) |
4305 | return ret; | |
8ea99c92 DV |
4306 | |
4307 | vma = NULL; | |
ac0c6b5a CW |
4308 | } |
4309 | } | |
4310 | ||
ef79e17c | 4311 | bound = vma ? vma->bound : 0; |
8ea99c92 | 4312 | if (vma == NULL || !drm_mm_node_allocated(&vma->node)) { |
ec7adb6e JL |
4313 | vma = i915_gem_object_bind_to_vm(obj, vm, ggtt_view, alignment, |
4314 | flags); | |
262de145 DV |
4315 | if (IS_ERR(vma)) |
4316 | return PTR_ERR(vma); | |
0875546c DV |
4317 | } else { |
4318 | ret = i915_vma_bind(vma, obj->cache_level, flags); | |
fe14d5f4 TU |
4319 | if (ret) |
4320 | return ret; | |
4321 | } | |
74898d7e | 4322 | |
91e6711e JL |
4323 | if (ggtt_view && ggtt_view->type == I915_GGTT_VIEW_NORMAL && |
4324 | (bound ^ vma->bound) & GLOBAL_BIND) { | |
d0710abb | 4325 | __i915_vma_set_map_and_fenceable(vma); |
91e6711e JL |
4326 | WARN_ON(flags & PIN_MAPPABLE && !obj->map_and_fenceable); |
4327 | } | |
ef79e17c | 4328 | |
8ea99c92 | 4329 | vma->pin_count++; |
673a394b EA |
4330 | return 0; |
4331 | } | |
4332 | ||
ec7adb6e JL |
4333 | int |
4334 | i915_gem_object_pin(struct drm_i915_gem_object *obj, | |
4335 | struct i915_address_space *vm, | |
4336 | uint32_t alignment, | |
4337 | uint64_t flags) | |
4338 | { | |
4339 | return i915_gem_object_do_pin(obj, vm, | |
4340 | i915_is_ggtt(vm) ? &i915_ggtt_view_normal : NULL, | |
4341 | alignment, flags); | |
4342 | } | |
4343 | ||
4344 | int | |
4345 | i915_gem_object_ggtt_pin(struct drm_i915_gem_object *obj, | |
4346 | const struct i915_ggtt_view *view, | |
4347 | uint32_t alignment, | |
4348 | uint64_t flags) | |
4349 | { | |
72e96d64 JL |
4350 | struct drm_device *dev = obj->base.dev; |
4351 | struct drm_i915_private *dev_priv = to_i915(dev); | |
4352 | struct i915_ggtt *ggtt = &dev_priv->ggtt; | |
4353 | ||
ade7daa1 | 4354 | BUG_ON(!view); |
ec7adb6e | 4355 | |
72e96d64 | 4356 | return i915_gem_object_do_pin(obj, &ggtt->base, view, |
6fafab76 | 4357 | alignment, flags | PIN_GLOBAL); |
ec7adb6e JL |
4358 | } |
4359 | ||
673a394b | 4360 | void |
e6617330 TU |
4361 | i915_gem_object_ggtt_unpin_view(struct drm_i915_gem_object *obj, |
4362 | const struct i915_ggtt_view *view) | |
673a394b | 4363 | { |
e6617330 | 4364 | struct i915_vma *vma = i915_gem_obj_to_ggtt_view(obj, view); |
673a394b | 4365 | |
d7f46fc4 | 4366 | BUG_ON(!vma); |
e6617330 | 4367 | WARN_ON(vma->pin_count == 0); |
9abc4648 | 4368 | WARN_ON(!i915_gem_obj_ggtt_bound_view(obj, view)); |
d7f46fc4 | 4369 | |
30154650 | 4370 | --vma->pin_count; |
673a394b EA |
4371 | } |
4372 | ||
673a394b EA |
4373 | int |
4374 | i915_gem_busy_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 4375 | struct drm_file *file) |
673a394b EA |
4376 | { |
4377 | struct drm_i915_gem_busy *args = data; | |
05394f39 | 4378 | struct drm_i915_gem_object *obj; |
30dbf0c0 CW |
4379 | int ret; |
4380 | ||
76c1dec1 | 4381 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 4382 | if (ret) |
76c1dec1 | 4383 | return ret; |
673a394b | 4384 | |
05394f39 | 4385 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 4386 | if (&obj->base == NULL) { |
1d7cfea1 CW |
4387 | ret = -ENOENT; |
4388 | goto unlock; | |
673a394b | 4389 | } |
d1b851fc | 4390 | |
0be555b6 CW |
4391 | /* Count all active objects as busy, even if they are currently not used |
4392 | * by the gpu. Users of this interface expect objects to eventually | |
4393 | * become non-busy without any further actions, therefore emit any | |
4394 | * necessary flushes here. | |
c4de0a5d | 4395 | */ |
30dfebf3 | 4396 | ret = i915_gem_object_flush_active(obj); |
b4716185 CW |
4397 | if (ret) |
4398 | goto unref; | |
0be555b6 | 4399 | |
426960be CW |
4400 | args->busy = 0; |
4401 | if (obj->active) { | |
4402 | int i; | |
4403 | ||
666796da | 4404 | for (i = 0; i < I915_NUM_ENGINES; i++) { |
426960be CW |
4405 | struct drm_i915_gem_request *req; |
4406 | ||
4407 | req = obj->last_read_req[i]; | |
4408 | if (req) | |
4a570db5 | 4409 | args->busy |= 1 << (16 + req->engine->exec_id); |
426960be CW |
4410 | } |
4411 | if (obj->last_write_req) | |
4a570db5 | 4412 | args->busy |= obj->last_write_req->engine->exec_id; |
426960be | 4413 | } |
673a394b | 4414 | |
b4716185 | 4415 | unref: |
05394f39 | 4416 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 4417 | unlock: |
673a394b | 4418 | mutex_unlock(&dev->struct_mutex); |
1d7cfea1 | 4419 | return ret; |
673a394b EA |
4420 | } |
4421 | ||
4422 | int | |
4423 | i915_gem_throttle_ioctl(struct drm_device *dev, void *data, | |
4424 | struct drm_file *file_priv) | |
4425 | { | |
0206e353 | 4426 | return i915_gem_ring_throttle(dev, file_priv); |
673a394b EA |
4427 | } |
4428 | ||
3ef94daa CW |
4429 | int |
4430 | i915_gem_madvise_ioctl(struct drm_device *dev, void *data, | |
4431 | struct drm_file *file_priv) | |
4432 | { | |
656bfa3a | 4433 | struct drm_i915_private *dev_priv = dev->dev_private; |
3ef94daa | 4434 | struct drm_i915_gem_madvise *args = data; |
05394f39 | 4435 | struct drm_i915_gem_object *obj; |
76c1dec1 | 4436 | int ret; |
3ef94daa CW |
4437 | |
4438 | switch (args->madv) { | |
4439 | case I915_MADV_DONTNEED: | |
4440 | case I915_MADV_WILLNEED: | |
4441 | break; | |
4442 | default: | |
4443 | return -EINVAL; | |
4444 | } | |
4445 | ||
1d7cfea1 CW |
4446 | ret = i915_mutex_lock_interruptible(dev); |
4447 | if (ret) | |
4448 | return ret; | |
4449 | ||
05394f39 | 4450 | obj = to_intel_bo(drm_gem_object_lookup(dev, file_priv, args->handle)); |
c8725226 | 4451 | if (&obj->base == NULL) { |
1d7cfea1 CW |
4452 | ret = -ENOENT; |
4453 | goto unlock; | |
3ef94daa | 4454 | } |
3ef94daa | 4455 | |
d7f46fc4 | 4456 | if (i915_gem_obj_is_pinned(obj)) { |
1d7cfea1 CW |
4457 | ret = -EINVAL; |
4458 | goto out; | |
3ef94daa CW |
4459 | } |
4460 | ||
656bfa3a DV |
4461 | if (obj->pages && |
4462 | obj->tiling_mode != I915_TILING_NONE && | |
4463 | dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES) { | |
4464 | if (obj->madv == I915_MADV_WILLNEED) | |
4465 | i915_gem_object_unpin_pages(obj); | |
4466 | if (args->madv == I915_MADV_WILLNEED) | |
4467 | i915_gem_object_pin_pages(obj); | |
4468 | } | |
4469 | ||
05394f39 CW |
4470 | if (obj->madv != __I915_MADV_PURGED) |
4471 | obj->madv = args->madv; | |
3ef94daa | 4472 | |
6c085a72 | 4473 | /* if the object is no longer attached, discard its backing storage */ |
be6a0376 | 4474 | if (obj->madv == I915_MADV_DONTNEED && obj->pages == NULL) |
2d7ef395 CW |
4475 | i915_gem_object_truncate(obj); |
4476 | ||
05394f39 | 4477 | args->retained = obj->madv != __I915_MADV_PURGED; |
bb6baf76 | 4478 | |
1d7cfea1 | 4479 | out: |
05394f39 | 4480 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 4481 | unlock: |
3ef94daa | 4482 | mutex_unlock(&dev->struct_mutex); |
1d7cfea1 | 4483 | return ret; |
3ef94daa CW |
4484 | } |
4485 | ||
37e680a1 CW |
4486 | void i915_gem_object_init(struct drm_i915_gem_object *obj, |
4487 | const struct drm_i915_gem_object_ops *ops) | |
0327d6ba | 4488 | { |
b4716185 CW |
4489 | int i; |
4490 | ||
35c20a60 | 4491 | INIT_LIST_HEAD(&obj->global_list); |
666796da | 4492 | for (i = 0; i < I915_NUM_ENGINES; i++) |
117897f4 | 4493 | INIT_LIST_HEAD(&obj->engine_list[i]); |
b25cb2f8 | 4494 | INIT_LIST_HEAD(&obj->obj_exec_link); |
2f633156 | 4495 | INIT_LIST_HEAD(&obj->vma_list); |
8d9d5744 | 4496 | INIT_LIST_HEAD(&obj->batch_pool_link); |
0327d6ba | 4497 | |
37e680a1 CW |
4498 | obj->ops = ops; |
4499 | ||
0327d6ba CW |
4500 | obj->fence_reg = I915_FENCE_REG_NONE; |
4501 | obj->madv = I915_MADV_WILLNEED; | |
0327d6ba CW |
4502 | |
4503 | i915_gem_info_add_obj(obj->base.dev->dev_private, obj->base.size); | |
4504 | } | |
4505 | ||
37e680a1 | 4506 | static const struct drm_i915_gem_object_ops i915_gem_object_ops = { |
de472664 | 4507 | .flags = I915_GEM_OBJECT_HAS_STRUCT_PAGE, |
37e680a1 CW |
4508 | .get_pages = i915_gem_object_get_pages_gtt, |
4509 | .put_pages = i915_gem_object_put_pages_gtt, | |
4510 | }; | |
4511 | ||
05394f39 CW |
4512 | struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev, |
4513 | size_t size) | |
ac52bc56 | 4514 | { |
c397b908 | 4515 | struct drm_i915_gem_object *obj; |
5949eac4 | 4516 | struct address_space *mapping; |
1a240d4d | 4517 | gfp_t mask; |
ac52bc56 | 4518 | |
42dcedd4 | 4519 | obj = i915_gem_object_alloc(dev); |
c397b908 DV |
4520 | if (obj == NULL) |
4521 | return NULL; | |
673a394b | 4522 | |
c397b908 | 4523 | if (drm_gem_object_init(dev, &obj->base, size) != 0) { |
42dcedd4 | 4524 | i915_gem_object_free(obj); |
c397b908 DV |
4525 | return NULL; |
4526 | } | |
673a394b | 4527 | |
bed1ea95 CW |
4528 | mask = GFP_HIGHUSER | __GFP_RECLAIMABLE; |
4529 | if (IS_CRESTLINE(dev) || IS_BROADWATER(dev)) { | |
4530 | /* 965gm cannot relocate objects above 4GiB. */ | |
4531 | mask &= ~__GFP_HIGHMEM; | |
4532 | mask |= __GFP_DMA32; | |
4533 | } | |
4534 | ||
496ad9aa | 4535 | mapping = file_inode(obj->base.filp)->i_mapping; |
bed1ea95 | 4536 | mapping_set_gfp_mask(mapping, mask); |
5949eac4 | 4537 | |
37e680a1 | 4538 | i915_gem_object_init(obj, &i915_gem_object_ops); |
73aa808f | 4539 | |
c397b908 DV |
4540 | obj->base.write_domain = I915_GEM_DOMAIN_CPU; |
4541 | obj->base.read_domains = I915_GEM_DOMAIN_CPU; | |
673a394b | 4542 | |
3d29b842 ED |
4543 | if (HAS_LLC(dev)) { |
4544 | /* On some devices, we can have the GPU use the LLC (the CPU | |
a1871112 EA |
4545 | * cache) for about a 10% performance improvement |
4546 | * compared to uncached. Graphics requests other than | |
4547 | * display scanout are coherent with the CPU in | |
4548 | * accessing this cache. This means in this mode we | |
4549 | * don't need to clflush on the CPU side, and on the | |
4550 | * GPU side we only need to flush internal caches to | |
4551 | * get data visible to the CPU. | |
4552 | * | |
4553 | * However, we maintain the display planes as UC, and so | |
4554 | * need to rebind when first used as such. | |
4555 | */ | |
4556 | obj->cache_level = I915_CACHE_LLC; | |
4557 | } else | |
4558 | obj->cache_level = I915_CACHE_NONE; | |
4559 | ||
d861e338 DV |
4560 | trace_i915_gem_object_create(obj); |
4561 | ||
05394f39 | 4562 | return obj; |
c397b908 DV |
4563 | } |
4564 | ||
340fbd8c CW |
4565 | static bool discard_backing_storage(struct drm_i915_gem_object *obj) |
4566 | { | |
4567 | /* If we are the last user of the backing storage (be it shmemfs | |
4568 | * pages or stolen etc), we know that the pages are going to be | |
4569 | * immediately released. In this case, we can then skip copying | |
4570 | * back the contents from the GPU. | |
4571 | */ | |
4572 | ||
4573 | if (obj->madv != I915_MADV_WILLNEED) | |
4574 | return false; | |
4575 | ||
4576 | if (obj->base.filp == NULL) | |
4577 | return true; | |
4578 | ||
4579 | /* At first glance, this looks racy, but then again so would be | |
4580 | * userspace racing mmap against close. However, the first external | |
4581 | * reference to the filp can only be obtained through the | |
4582 | * i915_gem_mmap_ioctl() which safeguards us against the user | |
4583 | * acquiring such a reference whilst we are in the middle of | |
4584 | * freeing the object. | |
4585 | */ | |
4586 | return atomic_long_read(&obj->base.filp->f_count) == 1; | |
4587 | } | |
4588 | ||
1488fc08 | 4589 | void i915_gem_free_object(struct drm_gem_object *gem_obj) |
673a394b | 4590 | { |
1488fc08 | 4591 | struct drm_i915_gem_object *obj = to_intel_bo(gem_obj); |
05394f39 | 4592 | struct drm_device *dev = obj->base.dev; |
3e31c6c0 | 4593 | struct drm_i915_private *dev_priv = dev->dev_private; |
07fe0b12 | 4594 | struct i915_vma *vma, *next; |
673a394b | 4595 | |
f65c9168 PZ |
4596 | intel_runtime_pm_get(dev_priv); |
4597 | ||
26e12f89 CW |
4598 | trace_i915_gem_object_destroy(obj); |
4599 | ||
1c7f4bca | 4600 | list_for_each_entry_safe(vma, next, &obj->vma_list, obj_link) { |
d7f46fc4 BW |
4601 | int ret; |
4602 | ||
4603 | vma->pin_count = 0; | |
4604 | ret = i915_vma_unbind(vma); | |
07fe0b12 BW |
4605 | if (WARN_ON(ret == -ERESTARTSYS)) { |
4606 | bool was_interruptible; | |
1488fc08 | 4607 | |
07fe0b12 BW |
4608 | was_interruptible = dev_priv->mm.interruptible; |
4609 | dev_priv->mm.interruptible = false; | |
1488fc08 | 4610 | |
07fe0b12 | 4611 | WARN_ON(i915_vma_unbind(vma)); |
1488fc08 | 4612 | |
07fe0b12 BW |
4613 | dev_priv->mm.interruptible = was_interruptible; |
4614 | } | |
1488fc08 CW |
4615 | } |
4616 | ||
1d64ae71 BW |
4617 | /* Stolen objects don't hold a ref, but do hold pin count. Fix that up |
4618 | * before progressing. */ | |
4619 | if (obj->stolen) | |
4620 | i915_gem_object_unpin_pages(obj); | |
4621 | ||
a071fa00 DV |
4622 | WARN_ON(obj->frontbuffer_bits); |
4623 | ||
656bfa3a DV |
4624 | if (obj->pages && obj->madv == I915_MADV_WILLNEED && |
4625 | dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES && | |
4626 | obj->tiling_mode != I915_TILING_NONE) | |
4627 | i915_gem_object_unpin_pages(obj); | |
4628 | ||
401c29f6 BW |
4629 | if (WARN_ON(obj->pages_pin_count)) |
4630 | obj->pages_pin_count = 0; | |
340fbd8c | 4631 | if (discard_backing_storage(obj)) |
5537252b | 4632 | obj->madv = I915_MADV_DONTNEED; |
37e680a1 | 4633 | i915_gem_object_put_pages(obj); |
d8cb5086 | 4634 | i915_gem_object_free_mmap_offset(obj); |
de151cf6 | 4635 | |
9da3da66 CW |
4636 | BUG_ON(obj->pages); |
4637 | ||
2f745ad3 CW |
4638 | if (obj->base.import_attach) |
4639 | drm_prime_gem_destroy(&obj->base, NULL); | |
de151cf6 | 4640 | |
5cc9ed4b CW |
4641 | if (obj->ops->release) |
4642 | obj->ops->release(obj); | |
4643 | ||
05394f39 CW |
4644 | drm_gem_object_release(&obj->base); |
4645 | i915_gem_info_remove_obj(dev_priv, obj->base.size); | |
c397b908 | 4646 | |
05394f39 | 4647 | kfree(obj->bit_17); |
42dcedd4 | 4648 | i915_gem_object_free(obj); |
f65c9168 PZ |
4649 | |
4650 | intel_runtime_pm_put(dev_priv); | |
673a394b EA |
4651 | } |
4652 | ||
ec7adb6e JL |
4653 | struct i915_vma *i915_gem_obj_to_vma(struct drm_i915_gem_object *obj, |
4654 | struct i915_address_space *vm) | |
e656a6cb DV |
4655 | { |
4656 | struct i915_vma *vma; | |
1c7f4bca | 4657 | list_for_each_entry(vma, &obj->vma_list, obj_link) { |
1b683729 TU |
4658 | if (vma->ggtt_view.type == I915_GGTT_VIEW_NORMAL && |
4659 | vma->vm == vm) | |
e656a6cb | 4660 | return vma; |
ec7adb6e JL |
4661 | } |
4662 | return NULL; | |
4663 | } | |
4664 | ||
4665 | struct i915_vma *i915_gem_obj_to_ggtt_view(struct drm_i915_gem_object *obj, | |
4666 | const struct i915_ggtt_view *view) | |
4667 | { | |
72e96d64 JL |
4668 | struct drm_device *dev = obj->base.dev; |
4669 | struct drm_i915_private *dev_priv = to_i915(dev); | |
4670 | struct i915_ggtt *ggtt = &dev_priv->ggtt; | |
ec7adb6e | 4671 | struct i915_vma *vma; |
e656a6cb | 4672 | |
ade7daa1 | 4673 | BUG_ON(!view); |
ec7adb6e | 4674 | |
1c7f4bca | 4675 | list_for_each_entry(vma, &obj->vma_list, obj_link) |
72e96d64 | 4676 | if (vma->vm == &ggtt->base && |
9abc4648 | 4677 | i915_ggtt_view_equal(&vma->ggtt_view, view)) |
ec7adb6e | 4678 | return vma; |
e656a6cb DV |
4679 | return NULL; |
4680 | } | |
4681 | ||
2f633156 BW |
4682 | void i915_gem_vma_destroy(struct i915_vma *vma) |
4683 | { | |
4684 | WARN_ON(vma->node.allocated); | |
aaa05667 CW |
4685 | |
4686 | /* Keep the vma as a placeholder in the execbuffer reservation lists */ | |
4687 | if (!list_empty(&vma->exec_list)) | |
4688 | return; | |
4689 | ||
596c5923 CW |
4690 | if (!vma->is_ggtt) |
4691 | i915_ppgtt_put(i915_vm_to_ppgtt(vma->vm)); | |
b9d06dd9 | 4692 | |
1c7f4bca | 4693 | list_del(&vma->obj_link); |
b93dab6e | 4694 | |
e20d2ab7 | 4695 | kmem_cache_free(to_i915(vma->obj->base.dev)->vmas, vma); |
2f633156 BW |
4696 | } |
4697 | ||
e3efda49 | 4698 | static void |
117897f4 | 4699 | i915_gem_stop_engines(struct drm_device *dev) |
e3efda49 CW |
4700 | { |
4701 | struct drm_i915_private *dev_priv = dev->dev_private; | |
e2f80391 | 4702 | struct intel_engine_cs *engine; |
e3efda49 | 4703 | |
b4ac5afc | 4704 | for_each_engine(engine, dev_priv) |
117897f4 | 4705 | dev_priv->gt.stop_engine(engine); |
e3efda49 CW |
4706 | } |
4707 | ||
29105ccc | 4708 | int |
45c5f202 | 4709 | i915_gem_suspend(struct drm_device *dev) |
29105ccc | 4710 | { |
3e31c6c0 | 4711 | struct drm_i915_private *dev_priv = dev->dev_private; |
45c5f202 | 4712 | int ret = 0; |
28dfe52a | 4713 | |
45c5f202 | 4714 | mutex_lock(&dev->struct_mutex); |
b2da9fe5 | 4715 | ret = i915_gpu_idle(dev); |
f7403347 | 4716 | if (ret) |
45c5f202 | 4717 | goto err; |
f7403347 | 4718 | |
b2da9fe5 | 4719 | i915_gem_retire_requests(dev); |
673a394b | 4720 | |
117897f4 | 4721 | i915_gem_stop_engines(dev); |
45c5f202 CW |
4722 | mutex_unlock(&dev->struct_mutex); |
4723 | ||
737b1506 | 4724 | cancel_delayed_work_sync(&dev_priv->gpu_error.hangcheck_work); |
29105ccc | 4725 | cancel_delayed_work_sync(&dev_priv->mm.retire_work); |
274fa1c1 | 4726 | flush_delayed_work(&dev_priv->mm.idle_work); |
29105ccc | 4727 | |
bdcf120b CW |
4728 | /* Assert that we sucessfully flushed all the work and |
4729 | * reset the GPU back to its idle, low power state. | |
4730 | */ | |
4731 | WARN_ON(dev_priv->mm.busy); | |
4732 | ||
673a394b | 4733 | return 0; |
45c5f202 CW |
4734 | |
4735 | err: | |
4736 | mutex_unlock(&dev->struct_mutex); | |
4737 | return ret; | |
673a394b EA |
4738 | } |
4739 | ||
6909a666 | 4740 | int i915_gem_l3_remap(struct drm_i915_gem_request *req, int slice) |
b9524a1e | 4741 | { |
4a570db5 | 4742 | struct intel_engine_cs *engine = req->engine; |
e2f80391 | 4743 | struct drm_device *dev = engine->dev; |
3e31c6c0 | 4744 | struct drm_i915_private *dev_priv = dev->dev_private; |
35a85ac6 | 4745 | u32 *remap_info = dev_priv->l3_parity.remap_info[slice]; |
c3787e2e | 4746 | int i, ret; |
b9524a1e | 4747 | |
040d2baa | 4748 | if (!HAS_L3_DPF(dev) || !remap_info) |
c3787e2e | 4749 | return 0; |
b9524a1e | 4750 | |
5fb9de1a | 4751 | ret = intel_ring_begin(req, GEN7_L3LOG_SIZE / 4 * 3); |
c3787e2e BW |
4752 | if (ret) |
4753 | return ret; | |
b9524a1e | 4754 | |
c3787e2e BW |
4755 | /* |
4756 | * Note: We do not worry about the concurrent register cacheline hang | |
4757 | * here because no other code should access these registers other than | |
4758 | * at initialization time. | |
4759 | */ | |
6fa1c5f1 | 4760 | for (i = 0; i < GEN7_L3LOG_SIZE / 4; i++) { |
e2f80391 TU |
4761 | intel_ring_emit(engine, MI_LOAD_REGISTER_IMM(1)); |
4762 | intel_ring_emit_reg(engine, GEN7_L3LOG(slice, i)); | |
4763 | intel_ring_emit(engine, remap_info[i]); | |
b9524a1e BW |
4764 | } |
4765 | ||
e2f80391 | 4766 | intel_ring_advance(engine); |
b9524a1e | 4767 | |
c3787e2e | 4768 | return ret; |
b9524a1e BW |
4769 | } |
4770 | ||
f691e2f4 DV |
4771 | void i915_gem_init_swizzling(struct drm_device *dev) |
4772 | { | |
3e31c6c0 | 4773 | struct drm_i915_private *dev_priv = dev->dev_private; |
f691e2f4 | 4774 | |
11782b02 | 4775 | if (INTEL_INFO(dev)->gen < 5 || |
f691e2f4 DV |
4776 | dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_NONE) |
4777 | return; | |
4778 | ||
4779 | I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) | | |
4780 | DISP_TILE_SURFACE_SWIZZLING); | |
4781 | ||
11782b02 DV |
4782 | if (IS_GEN5(dev)) |
4783 | return; | |
4784 | ||
f691e2f4 DV |
4785 | I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_SWZCTL); |
4786 | if (IS_GEN6(dev)) | |
6b26c86d | 4787 | I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB)); |
8782e26c | 4788 | else if (IS_GEN7(dev)) |
6b26c86d | 4789 | I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB)); |
31a5336e BW |
4790 | else if (IS_GEN8(dev)) |
4791 | I915_WRITE(GAMTARBMODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_BDW)); | |
8782e26c BW |
4792 | else |
4793 | BUG(); | |
f691e2f4 | 4794 | } |
e21af88d | 4795 | |
81e7f200 VS |
4796 | static void init_unused_ring(struct drm_device *dev, u32 base) |
4797 | { | |
4798 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4799 | ||
4800 | I915_WRITE(RING_CTL(base), 0); | |
4801 | I915_WRITE(RING_HEAD(base), 0); | |
4802 | I915_WRITE(RING_TAIL(base), 0); | |
4803 | I915_WRITE(RING_START(base), 0); | |
4804 | } | |
4805 | ||
4806 | static void init_unused_rings(struct drm_device *dev) | |
4807 | { | |
4808 | if (IS_I830(dev)) { | |
4809 | init_unused_ring(dev, PRB1_BASE); | |
4810 | init_unused_ring(dev, SRB0_BASE); | |
4811 | init_unused_ring(dev, SRB1_BASE); | |
4812 | init_unused_ring(dev, SRB2_BASE); | |
4813 | init_unused_ring(dev, SRB3_BASE); | |
4814 | } else if (IS_GEN2(dev)) { | |
4815 | init_unused_ring(dev, SRB0_BASE); | |
4816 | init_unused_ring(dev, SRB1_BASE); | |
4817 | } else if (IS_GEN3(dev)) { | |
4818 | init_unused_ring(dev, PRB1_BASE); | |
4819 | init_unused_ring(dev, PRB2_BASE); | |
4820 | } | |
4821 | } | |
4822 | ||
117897f4 | 4823 | int i915_gem_init_engines(struct drm_device *dev) |
8187a2b7 | 4824 | { |
4fc7c971 | 4825 | struct drm_i915_private *dev_priv = dev->dev_private; |
8187a2b7 | 4826 | int ret; |
68f95ba9 | 4827 | |
5c1143bb | 4828 | ret = intel_init_render_ring_buffer(dev); |
68f95ba9 | 4829 | if (ret) |
b6913e4b | 4830 | return ret; |
68f95ba9 CW |
4831 | |
4832 | if (HAS_BSD(dev)) { | |
5c1143bb | 4833 | ret = intel_init_bsd_ring_buffer(dev); |
68f95ba9 CW |
4834 | if (ret) |
4835 | goto cleanup_render_ring; | |
d1b851fc | 4836 | } |
68f95ba9 | 4837 | |
d39398f5 | 4838 | if (HAS_BLT(dev)) { |
549f7365 CW |
4839 | ret = intel_init_blt_ring_buffer(dev); |
4840 | if (ret) | |
4841 | goto cleanup_bsd_ring; | |
4842 | } | |
4843 | ||
9a8a2213 BW |
4844 | if (HAS_VEBOX(dev)) { |
4845 | ret = intel_init_vebox_ring_buffer(dev); | |
4846 | if (ret) | |
4847 | goto cleanup_blt_ring; | |
4848 | } | |
4849 | ||
845f74a7 ZY |
4850 | if (HAS_BSD2(dev)) { |
4851 | ret = intel_init_bsd2_ring_buffer(dev); | |
4852 | if (ret) | |
4853 | goto cleanup_vebox_ring; | |
4854 | } | |
9a8a2213 | 4855 | |
4fc7c971 BW |
4856 | return 0; |
4857 | ||
9a8a2213 | 4858 | cleanup_vebox_ring: |
117897f4 | 4859 | intel_cleanup_engine(&dev_priv->engine[VECS]); |
4fc7c971 | 4860 | cleanup_blt_ring: |
117897f4 | 4861 | intel_cleanup_engine(&dev_priv->engine[BCS]); |
4fc7c971 | 4862 | cleanup_bsd_ring: |
117897f4 | 4863 | intel_cleanup_engine(&dev_priv->engine[VCS]); |
4fc7c971 | 4864 | cleanup_render_ring: |
117897f4 | 4865 | intel_cleanup_engine(&dev_priv->engine[RCS]); |
4fc7c971 BW |
4866 | |
4867 | return ret; | |
4868 | } | |
4869 | ||
4870 | int | |
4871 | i915_gem_init_hw(struct drm_device *dev) | |
4872 | { | |
3e31c6c0 | 4873 | struct drm_i915_private *dev_priv = dev->dev_private; |
e2f80391 | 4874 | struct intel_engine_cs *engine; |
b4ac5afc | 4875 | int ret, j; |
4fc7c971 BW |
4876 | |
4877 | if (INTEL_INFO(dev)->gen < 6 && !intel_enable_gtt()) | |
4878 | return -EIO; | |
4879 | ||
5e4f5189 CW |
4880 | /* Double layer security blanket, see i915_gem_init() */ |
4881 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); | |
4882 | ||
3accaf7e | 4883 | if (HAS_EDRAM(dev) && INTEL_GEN(dev_priv) < 9) |
05e21cc4 | 4884 | I915_WRITE(HSW_IDICR, I915_READ(HSW_IDICR) | IDIHASHMSK(0xf)); |
4fc7c971 | 4885 | |
0bf21347 VS |
4886 | if (IS_HASWELL(dev)) |
4887 | I915_WRITE(MI_PREDICATE_RESULT_2, IS_HSW_GT3(dev) ? | |
4888 | LOWER_SLICE_ENABLED : LOWER_SLICE_DISABLED); | |
9435373e | 4889 | |
88a2b2a3 | 4890 | if (HAS_PCH_NOP(dev)) { |
6ba844b0 DV |
4891 | if (IS_IVYBRIDGE(dev)) { |
4892 | u32 temp = I915_READ(GEN7_MSG_CTL); | |
4893 | temp &= ~(WAIT_FOR_PCH_FLR_ACK | WAIT_FOR_PCH_RESET_ACK); | |
4894 | I915_WRITE(GEN7_MSG_CTL, temp); | |
4895 | } else if (INTEL_INFO(dev)->gen >= 7) { | |
4896 | u32 temp = I915_READ(HSW_NDE_RSTWRN_OPT); | |
4897 | temp &= ~RESET_PCH_HANDSHAKE_ENABLE; | |
4898 | I915_WRITE(HSW_NDE_RSTWRN_OPT, temp); | |
4899 | } | |
88a2b2a3 BW |
4900 | } |
4901 | ||
4fc7c971 BW |
4902 | i915_gem_init_swizzling(dev); |
4903 | ||
d5abdfda DV |
4904 | /* |
4905 | * At least 830 can leave some of the unused rings | |
4906 | * "active" (ie. head != tail) after resume which | |
4907 | * will prevent c3 entry. Makes sure all unused rings | |
4908 | * are totally idle. | |
4909 | */ | |
4910 | init_unused_rings(dev); | |
4911 | ||
ed54c1a1 | 4912 | BUG_ON(!dev_priv->kernel_context); |
90638cc1 | 4913 | |
4ad2fd88 JH |
4914 | ret = i915_ppgtt_init_hw(dev); |
4915 | if (ret) { | |
4916 | DRM_ERROR("PPGTT enable HW failed %d\n", ret); | |
4917 | goto out; | |
4918 | } | |
4919 | ||
4920 | /* Need to do basic initialisation of all rings first: */ | |
b4ac5afc | 4921 | for_each_engine(engine, dev_priv) { |
e2f80391 | 4922 | ret = engine->init_hw(engine); |
35a57ffb | 4923 | if (ret) |
5e4f5189 | 4924 | goto out; |
35a57ffb | 4925 | } |
99433931 | 4926 | |
33a732f4 | 4927 | /* We can't enable contexts until all firmware is loaded */ |
87bcdd2e JB |
4928 | if (HAS_GUC_UCODE(dev)) { |
4929 | ret = intel_guc_ucode_load(dev); | |
4930 | if (ret) { | |
9f9e539f DV |
4931 | DRM_ERROR("Failed to initialize GuC, error %d\n", ret); |
4932 | ret = -EIO; | |
4933 | goto out; | |
87bcdd2e | 4934 | } |
33a732f4 AD |
4935 | } |
4936 | ||
e84fe803 NH |
4937 | /* |
4938 | * Increment the next seqno by 0x100 so we have a visible break | |
4939 | * on re-initialisation | |
4940 | */ | |
4941 | ret = i915_gem_set_seqno(dev, dev_priv->next_seqno+0x100); | |
4942 | if (ret) | |
4943 | goto out; | |
4944 | ||
4ad2fd88 | 4945 | /* Now it is safe to go back round and do everything else: */ |
b4ac5afc | 4946 | for_each_engine(engine, dev_priv) { |
dc4be607 JH |
4947 | struct drm_i915_gem_request *req; |
4948 | ||
e2f80391 | 4949 | req = i915_gem_request_alloc(engine, NULL); |
26827088 DG |
4950 | if (IS_ERR(req)) { |
4951 | ret = PTR_ERR(req); | |
117897f4 | 4952 | i915_gem_cleanup_engines(dev); |
dc4be607 JH |
4953 | goto out; |
4954 | } | |
4955 | ||
e2f80391 | 4956 | if (engine->id == RCS) { |
4ad2fd88 | 4957 | for (j = 0; j < NUM_L3_SLICES(dev); j++) |
6909a666 | 4958 | i915_gem_l3_remap(req, j); |
4ad2fd88 | 4959 | } |
c3787e2e | 4960 | |
b3dd6b96 | 4961 | ret = i915_ppgtt_init_ring(req); |
4ad2fd88 | 4962 | if (ret && ret != -EIO) { |
b4ac5afc DG |
4963 | DRM_ERROR("PPGTT enable %s failed %d\n", |
4964 | engine->name, ret); | |
dc4be607 | 4965 | i915_gem_request_cancel(req); |
117897f4 | 4966 | i915_gem_cleanup_engines(dev); |
4ad2fd88 JH |
4967 | goto out; |
4968 | } | |
82460d97 | 4969 | |
b3dd6b96 | 4970 | ret = i915_gem_context_enable(req); |
90638cc1 | 4971 | if (ret && ret != -EIO) { |
b4ac5afc DG |
4972 | DRM_ERROR("Context enable %s failed %d\n", |
4973 | engine->name, ret); | |
dc4be607 | 4974 | i915_gem_request_cancel(req); |
117897f4 | 4975 | i915_gem_cleanup_engines(dev); |
90638cc1 JH |
4976 | goto out; |
4977 | } | |
dc4be607 | 4978 | |
75289874 | 4979 | i915_add_request_no_flush(req); |
b7c36d25 | 4980 | } |
e21af88d | 4981 | |
5e4f5189 CW |
4982 | out: |
4983 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); | |
2fa48d8d | 4984 | return ret; |
8187a2b7 ZN |
4985 | } |
4986 | ||
1070a42b CW |
4987 | int i915_gem_init(struct drm_device *dev) |
4988 | { | |
4989 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1070a42b CW |
4990 | int ret; |
4991 | ||
127f1003 OM |
4992 | i915.enable_execlists = intel_sanitize_enable_execlists(dev, |
4993 | i915.enable_execlists); | |
4994 | ||
1070a42b | 4995 | mutex_lock(&dev->struct_mutex); |
d62b4892 | 4996 | |
a83014d3 | 4997 | if (!i915.enable_execlists) { |
f3dc74c0 | 4998 | dev_priv->gt.execbuf_submit = i915_gem_ringbuffer_submission; |
117897f4 TU |
4999 | dev_priv->gt.init_engines = i915_gem_init_engines; |
5000 | dev_priv->gt.cleanup_engine = intel_cleanup_engine; | |
5001 | dev_priv->gt.stop_engine = intel_stop_engine; | |
454afebd | 5002 | } else { |
f3dc74c0 | 5003 | dev_priv->gt.execbuf_submit = intel_execlists_submission; |
117897f4 TU |
5004 | dev_priv->gt.init_engines = intel_logical_rings_init; |
5005 | dev_priv->gt.cleanup_engine = intel_logical_ring_cleanup; | |
5006 | dev_priv->gt.stop_engine = intel_logical_ring_stop; | |
a83014d3 OM |
5007 | } |
5008 | ||
5e4f5189 CW |
5009 | /* This is just a security blanket to placate dragons. |
5010 | * On some systems, we very sporadically observe that the first TLBs | |
5011 | * used by the CS may be stale, despite us poking the TLB reset. If | |
5012 | * we hold the forcewake during initialisation these problems | |
5013 | * just magically go away. | |
5014 | */ | |
5015 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); | |
5016 | ||
6c5566a8 | 5017 | ret = i915_gem_init_userptr(dev); |
7bcc3777 JN |
5018 | if (ret) |
5019 | goto out_unlock; | |
6c5566a8 | 5020 | |
d85489d3 | 5021 | i915_gem_init_ggtt(dev); |
d62b4892 | 5022 | |
2fa48d8d | 5023 | ret = i915_gem_context_init(dev); |
7bcc3777 JN |
5024 | if (ret) |
5025 | goto out_unlock; | |
2fa48d8d | 5026 | |
117897f4 | 5027 | ret = dev_priv->gt.init_engines(dev); |
35a57ffb | 5028 | if (ret) |
7bcc3777 | 5029 | goto out_unlock; |
2fa48d8d | 5030 | |
1070a42b | 5031 | ret = i915_gem_init_hw(dev); |
60990320 CW |
5032 | if (ret == -EIO) { |
5033 | /* Allow ring initialisation to fail by marking the GPU as | |
5034 | * wedged. But we only want to do this where the GPU is angry, | |
5035 | * for all other failure, such as an allocation failure, bail. | |
5036 | */ | |
5037 | DRM_ERROR("Failed to initialize GPU, declaring it wedged\n"); | |
805de8f4 | 5038 | atomic_or(I915_WEDGED, &dev_priv->gpu_error.reset_counter); |
60990320 | 5039 | ret = 0; |
1070a42b | 5040 | } |
7bcc3777 JN |
5041 | |
5042 | out_unlock: | |
5e4f5189 | 5043 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); |
60990320 | 5044 | mutex_unlock(&dev->struct_mutex); |
1070a42b | 5045 | |
60990320 | 5046 | return ret; |
1070a42b CW |
5047 | } |
5048 | ||
8187a2b7 | 5049 | void |
117897f4 | 5050 | i915_gem_cleanup_engines(struct drm_device *dev) |
8187a2b7 | 5051 | { |
3e31c6c0 | 5052 | struct drm_i915_private *dev_priv = dev->dev_private; |
e2f80391 | 5053 | struct intel_engine_cs *engine; |
8187a2b7 | 5054 | |
b4ac5afc | 5055 | for_each_engine(engine, dev_priv) |
117897f4 | 5056 | dev_priv->gt.cleanup_engine(engine); |
a647828a | 5057 | |
ee4b6faf MK |
5058 | if (i915.enable_execlists) |
5059 | /* | |
5060 | * Neither the BIOS, ourselves or any other kernel | |
5061 | * expects the system to be in execlists mode on startup, | |
5062 | * so we need to reset the GPU back to legacy mode. | |
5063 | */ | |
5064 | intel_gpu_reset(dev, ALL_ENGINES); | |
8187a2b7 ZN |
5065 | } |
5066 | ||
64193406 | 5067 | static void |
666796da | 5068 | init_engine_lists(struct intel_engine_cs *engine) |
64193406 | 5069 | { |
0bc40be8 TU |
5070 | INIT_LIST_HEAD(&engine->active_list); |
5071 | INIT_LIST_HEAD(&engine->request_list); | |
64193406 CW |
5072 | } |
5073 | ||
40ae4e16 ID |
5074 | void |
5075 | i915_gem_load_init_fences(struct drm_i915_private *dev_priv) | |
5076 | { | |
5077 | struct drm_device *dev = dev_priv->dev; | |
5078 | ||
5079 | if (INTEL_INFO(dev_priv)->gen >= 7 && !IS_VALLEYVIEW(dev_priv) && | |
5080 | !IS_CHERRYVIEW(dev_priv)) | |
5081 | dev_priv->num_fence_regs = 32; | |
5082 | else if (INTEL_INFO(dev_priv)->gen >= 4 || IS_I945G(dev_priv) || | |
5083 | IS_I945GM(dev_priv) || IS_G33(dev_priv)) | |
5084 | dev_priv->num_fence_regs = 16; | |
5085 | else | |
5086 | dev_priv->num_fence_regs = 8; | |
5087 | ||
5088 | if (intel_vgpu_active(dev)) | |
5089 | dev_priv->num_fence_regs = | |
5090 | I915_READ(vgtif_reg(avail_rs.fence_num)); | |
5091 | ||
5092 | /* Initialize fence registers to zero */ | |
5093 | i915_gem_restore_fences(dev); | |
5094 | ||
5095 | i915_gem_detect_bit_6_swizzle(dev); | |
5096 | } | |
5097 | ||
673a394b | 5098 | void |
d64aa096 | 5099 | i915_gem_load_init(struct drm_device *dev) |
673a394b | 5100 | { |
3e31c6c0 | 5101 | struct drm_i915_private *dev_priv = dev->dev_private; |
42dcedd4 CW |
5102 | int i; |
5103 | ||
efab6d8d | 5104 | dev_priv->objects = |
42dcedd4 CW |
5105 | kmem_cache_create("i915_gem_object", |
5106 | sizeof(struct drm_i915_gem_object), 0, | |
5107 | SLAB_HWCACHE_ALIGN, | |
5108 | NULL); | |
e20d2ab7 CW |
5109 | dev_priv->vmas = |
5110 | kmem_cache_create("i915_gem_vma", | |
5111 | sizeof(struct i915_vma), 0, | |
5112 | SLAB_HWCACHE_ALIGN, | |
5113 | NULL); | |
efab6d8d CW |
5114 | dev_priv->requests = |
5115 | kmem_cache_create("i915_gem_request", | |
5116 | sizeof(struct drm_i915_gem_request), 0, | |
5117 | SLAB_HWCACHE_ALIGN, | |
5118 | NULL); | |
673a394b | 5119 | |
fc8c067e | 5120 | INIT_LIST_HEAD(&dev_priv->vm_list); |
a33afea5 | 5121 | INIT_LIST_HEAD(&dev_priv->context_list); |
6c085a72 CW |
5122 | INIT_LIST_HEAD(&dev_priv->mm.unbound_list); |
5123 | INIT_LIST_HEAD(&dev_priv->mm.bound_list); | |
a09ba7fa | 5124 | INIT_LIST_HEAD(&dev_priv->mm.fence_list); |
666796da TU |
5125 | for (i = 0; i < I915_NUM_ENGINES; i++) |
5126 | init_engine_lists(&dev_priv->engine[i]); | |
4b9de737 | 5127 | for (i = 0; i < I915_MAX_NUM_FENCES; i++) |
007cc8ac | 5128 | INIT_LIST_HEAD(&dev_priv->fence_regs[i].lru_list); |
673a394b EA |
5129 | INIT_DELAYED_WORK(&dev_priv->mm.retire_work, |
5130 | i915_gem_retire_work_handler); | |
b29c19b6 CW |
5131 | INIT_DELAYED_WORK(&dev_priv->mm.idle_work, |
5132 | i915_gem_idle_work_handler); | |
1f83fee0 | 5133 | init_waitqueue_head(&dev_priv->gpu_error.reset_queue); |
31169714 | 5134 | |
72bfa19c CW |
5135 | dev_priv->relative_constants_mode = I915_EXEC_CONSTANTS_REL_GENERAL; |
5136 | ||
e84fe803 NH |
5137 | /* |
5138 | * Set initial sequence number for requests. | |
5139 | * Using this number allows the wraparound to happen early, | |
5140 | * catching any obvious problems. | |
5141 | */ | |
5142 | dev_priv->next_seqno = ((u32)~0 - 0x1100); | |
5143 | dev_priv->last_seqno = ((u32)~0 - 0x1101); | |
5144 | ||
19b2dbde | 5145 | INIT_LIST_HEAD(&dev_priv->mm.fence_list); |
10ed13e4 | 5146 | |
6b95a207 | 5147 | init_waitqueue_head(&dev_priv->pending_flip_queue); |
17250b71 | 5148 | |
ce453d81 CW |
5149 | dev_priv->mm.interruptible = true; |
5150 | ||
f99d7069 | 5151 | mutex_init(&dev_priv->fb_tracking.lock); |
673a394b | 5152 | } |
71acb5eb | 5153 | |
d64aa096 ID |
5154 | void i915_gem_load_cleanup(struct drm_device *dev) |
5155 | { | |
5156 | struct drm_i915_private *dev_priv = to_i915(dev); | |
5157 | ||
5158 | kmem_cache_destroy(dev_priv->requests); | |
5159 | kmem_cache_destroy(dev_priv->vmas); | |
5160 | kmem_cache_destroy(dev_priv->objects); | |
5161 | } | |
5162 | ||
f787a5f5 | 5163 | void i915_gem_release(struct drm_device *dev, struct drm_file *file) |
b962442e | 5164 | { |
f787a5f5 | 5165 | struct drm_i915_file_private *file_priv = file->driver_priv; |
b962442e EA |
5166 | |
5167 | /* Clean up our request list when the client is going away, so that | |
5168 | * later retire_requests won't dereference our soon-to-be-gone | |
5169 | * file_priv. | |
5170 | */ | |
1c25595f | 5171 | spin_lock(&file_priv->mm.lock); |
f787a5f5 CW |
5172 | while (!list_empty(&file_priv->mm.request_list)) { |
5173 | struct drm_i915_gem_request *request; | |
5174 | ||
5175 | request = list_first_entry(&file_priv->mm.request_list, | |
5176 | struct drm_i915_gem_request, | |
5177 | client_list); | |
5178 | list_del(&request->client_list); | |
5179 | request->file_priv = NULL; | |
5180 | } | |
1c25595f | 5181 | spin_unlock(&file_priv->mm.lock); |
b29c19b6 | 5182 | |
2e1b8730 | 5183 | if (!list_empty(&file_priv->rps.link)) { |
8d3afd7d | 5184 | spin_lock(&to_i915(dev)->rps.client_lock); |
2e1b8730 | 5185 | list_del(&file_priv->rps.link); |
8d3afd7d | 5186 | spin_unlock(&to_i915(dev)->rps.client_lock); |
1854d5ca | 5187 | } |
b29c19b6 CW |
5188 | } |
5189 | ||
5190 | int i915_gem_open(struct drm_device *dev, struct drm_file *file) | |
5191 | { | |
5192 | struct drm_i915_file_private *file_priv; | |
e422b888 | 5193 | int ret; |
b29c19b6 CW |
5194 | |
5195 | DRM_DEBUG_DRIVER("\n"); | |
5196 | ||
5197 | file_priv = kzalloc(sizeof(*file_priv), GFP_KERNEL); | |
5198 | if (!file_priv) | |
5199 | return -ENOMEM; | |
5200 | ||
5201 | file->driver_priv = file_priv; | |
5202 | file_priv->dev_priv = dev->dev_private; | |
ab0e7ff9 | 5203 | file_priv->file = file; |
2e1b8730 | 5204 | INIT_LIST_HEAD(&file_priv->rps.link); |
b29c19b6 CW |
5205 | |
5206 | spin_lock_init(&file_priv->mm.lock); | |
5207 | INIT_LIST_HEAD(&file_priv->mm.request_list); | |
b29c19b6 | 5208 | |
de1add36 TU |
5209 | file_priv->bsd_ring = -1; |
5210 | ||
e422b888 BW |
5211 | ret = i915_gem_context_open(dev, file); |
5212 | if (ret) | |
5213 | kfree(file_priv); | |
b29c19b6 | 5214 | |
e422b888 | 5215 | return ret; |
b29c19b6 CW |
5216 | } |
5217 | ||
b680c37a DV |
5218 | /** |
5219 | * i915_gem_track_fb - update frontbuffer tracking | |
d9072a3e GT |
5220 | * @old: current GEM buffer for the frontbuffer slots |
5221 | * @new: new GEM buffer for the frontbuffer slots | |
5222 | * @frontbuffer_bits: bitmask of frontbuffer slots | |
b680c37a DV |
5223 | * |
5224 | * This updates the frontbuffer tracking bits @frontbuffer_bits by clearing them | |
5225 | * from @old and setting them in @new. Both @old and @new can be NULL. | |
5226 | */ | |
a071fa00 DV |
5227 | void i915_gem_track_fb(struct drm_i915_gem_object *old, |
5228 | struct drm_i915_gem_object *new, | |
5229 | unsigned frontbuffer_bits) | |
5230 | { | |
5231 | if (old) { | |
5232 | WARN_ON(!mutex_is_locked(&old->base.dev->struct_mutex)); | |
5233 | WARN_ON(!(old->frontbuffer_bits & frontbuffer_bits)); | |
5234 | old->frontbuffer_bits &= ~frontbuffer_bits; | |
5235 | } | |
5236 | ||
5237 | if (new) { | |
5238 | WARN_ON(!mutex_is_locked(&new->base.dev->struct_mutex)); | |
5239 | WARN_ON(new->frontbuffer_bits & frontbuffer_bits); | |
5240 | new->frontbuffer_bits |= frontbuffer_bits; | |
5241 | } | |
5242 | } | |
5243 | ||
a70a3148 | 5244 | /* All the new VM stuff */ |
088e0df4 MT |
5245 | u64 i915_gem_obj_offset(struct drm_i915_gem_object *o, |
5246 | struct i915_address_space *vm) | |
a70a3148 BW |
5247 | { |
5248 | struct drm_i915_private *dev_priv = o->base.dev->dev_private; | |
5249 | struct i915_vma *vma; | |
5250 | ||
896ab1a5 | 5251 | WARN_ON(vm == &dev_priv->mm.aliasing_ppgtt->base); |
a70a3148 | 5252 | |
1c7f4bca | 5253 | list_for_each_entry(vma, &o->vma_list, obj_link) { |
596c5923 | 5254 | if (vma->is_ggtt && |
ec7adb6e JL |
5255 | vma->ggtt_view.type != I915_GGTT_VIEW_NORMAL) |
5256 | continue; | |
5257 | if (vma->vm == vm) | |
a70a3148 | 5258 | return vma->node.start; |
a70a3148 | 5259 | } |
ec7adb6e | 5260 | |
f25748ea DV |
5261 | WARN(1, "%s vma for this object not found.\n", |
5262 | i915_is_ggtt(vm) ? "global" : "ppgtt"); | |
a70a3148 BW |
5263 | return -1; |
5264 | } | |
5265 | ||
088e0df4 MT |
5266 | u64 i915_gem_obj_ggtt_offset_view(struct drm_i915_gem_object *o, |
5267 | const struct i915_ggtt_view *view) | |
a70a3148 | 5268 | { |
72e96d64 JL |
5269 | struct drm_i915_private *dev_priv = to_i915(o->base.dev); |
5270 | struct i915_ggtt *ggtt = &dev_priv->ggtt; | |
a70a3148 BW |
5271 | struct i915_vma *vma; |
5272 | ||
1c7f4bca | 5273 | list_for_each_entry(vma, &o->vma_list, obj_link) |
72e96d64 | 5274 | if (vma->vm == &ggtt->base && |
9abc4648 | 5275 | i915_ggtt_view_equal(&vma->ggtt_view, view)) |
ec7adb6e JL |
5276 | return vma->node.start; |
5277 | ||
5678ad73 | 5278 | WARN(1, "global vma for this object not found. (view=%u)\n", view->type); |
ec7adb6e JL |
5279 | return -1; |
5280 | } | |
5281 | ||
5282 | bool i915_gem_obj_bound(struct drm_i915_gem_object *o, | |
5283 | struct i915_address_space *vm) | |
5284 | { | |
5285 | struct i915_vma *vma; | |
5286 | ||
1c7f4bca | 5287 | list_for_each_entry(vma, &o->vma_list, obj_link) { |
596c5923 | 5288 | if (vma->is_ggtt && |
ec7adb6e JL |
5289 | vma->ggtt_view.type != I915_GGTT_VIEW_NORMAL) |
5290 | continue; | |
5291 | if (vma->vm == vm && drm_mm_node_allocated(&vma->node)) | |
5292 | return true; | |
5293 | } | |
5294 | ||
5295 | return false; | |
5296 | } | |
5297 | ||
5298 | bool i915_gem_obj_ggtt_bound_view(struct drm_i915_gem_object *o, | |
9abc4648 | 5299 | const struct i915_ggtt_view *view) |
ec7adb6e | 5300 | { |
72e96d64 JL |
5301 | struct drm_i915_private *dev_priv = to_i915(o->base.dev); |
5302 | struct i915_ggtt *ggtt = &dev_priv->ggtt; | |
ec7adb6e JL |
5303 | struct i915_vma *vma; |
5304 | ||
1c7f4bca | 5305 | list_for_each_entry(vma, &o->vma_list, obj_link) |
72e96d64 | 5306 | if (vma->vm == &ggtt->base && |
9abc4648 | 5307 | i915_ggtt_view_equal(&vma->ggtt_view, view) && |
fe14d5f4 | 5308 | drm_mm_node_allocated(&vma->node)) |
a70a3148 BW |
5309 | return true; |
5310 | ||
5311 | return false; | |
5312 | } | |
5313 | ||
5314 | bool i915_gem_obj_bound_any(struct drm_i915_gem_object *o) | |
5315 | { | |
5a1d5eb0 | 5316 | struct i915_vma *vma; |
a70a3148 | 5317 | |
1c7f4bca | 5318 | list_for_each_entry(vma, &o->vma_list, obj_link) |
5a1d5eb0 | 5319 | if (drm_mm_node_allocated(&vma->node)) |
a70a3148 BW |
5320 | return true; |
5321 | ||
5322 | return false; | |
5323 | } | |
5324 | ||
5325 | unsigned long i915_gem_obj_size(struct drm_i915_gem_object *o, | |
5326 | struct i915_address_space *vm) | |
5327 | { | |
5328 | struct drm_i915_private *dev_priv = o->base.dev->dev_private; | |
5329 | struct i915_vma *vma; | |
5330 | ||
896ab1a5 | 5331 | WARN_ON(vm == &dev_priv->mm.aliasing_ppgtt->base); |
a70a3148 BW |
5332 | |
5333 | BUG_ON(list_empty(&o->vma_list)); | |
5334 | ||
1c7f4bca | 5335 | list_for_each_entry(vma, &o->vma_list, obj_link) { |
596c5923 | 5336 | if (vma->is_ggtt && |
ec7adb6e JL |
5337 | vma->ggtt_view.type != I915_GGTT_VIEW_NORMAL) |
5338 | continue; | |
a70a3148 BW |
5339 | if (vma->vm == vm) |
5340 | return vma->node.size; | |
ec7adb6e | 5341 | } |
a70a3148 BW |
5342 | return 0; |
5343 | } | |
5344 | ||
ec7adb6e | 5345 | bool i915_gem_obj_is_pinned(struct drm_i915_gem_object *obj) |
5c2abbea BW |
5346 | { |
5347 | struct i915_vma *vma; | |
1c7f4bca | 5348 | list_for_each_entry(vma, &obj->vma_list, obj_link) |
ec7adb6e JL |
5349 | if (vma->pin_count > 0) |
5350 | return true; | |
a6631ae1 | 5351 | |
ec7adb6e | 5352 | return false; |
5c2abbea | 5353 | } |
ea70299d | 5354 | |
033908ae DG |
5355 | /* Like i915_gem_object_get_page(), but mark the returned page dirty */ |
5356 | struct page * | |
5357 | i915_gem_object_get_dirty_page(struct drm_i915_gem_object *obj, int n) | |
5358 | { | |
5359 | struct page *page; | |
5360 | ||
5361 | /* Only default objects have per-page dirty tracking */ | |
de472664 | 5362 | if (WARN_ON((obj->ops->flags & I915_GEM_OBJECT_HAS_STRUCT_PAGE) == 0)) |
033908ae DG |
5363 | return NULL; |
5364 | ||
5365 | page = i915_gem_object_get_page(obj, n); | |
5366 | set_page_dirty(page); | |
5367 | return page; | |
5368 | } | |
5369 | ||
ea70299d DG |
5370 | /* Allocate a new GEM object and fill it with the supplied data */ |
5371 | struct drm_i915_gem_object * | |
5372 | i915_gem_object_create_from_data(struct drm_device *dev, | |
5373 | const void *data, size_t size) | |
5374 | { | |
5375 | struct drm_i915_gem_object *obj; | |
5376 | struct sg_table *sg; | |
5377 | size_t bytes; | |
5378 | int ret; | |
5379 | ||
5380 | obj = i915_gem_alloc_object(dev, round_up(size, PAGE_SIZE)); | |
5381 | if (IS_ERR_OR_NULL(obj)) | |
5382 | return obj; | |
5383 | ||
5384 | ret = i915_gem_object_set_to_cpu_domain(obj, true); | |
5385 | if (ret) | |
5386 | goto fail; | |
5387 | ||
5388 | ret = i915_gem_object_get_pages(obj); | |
5389 | if (ret) | |
5390 | goto fail; | |
5391 | ||
5392 | i915_gem_object_pin_pages(obj); | |
5393 | sg = obj->pages; | |
5394 | bytes = sg_copy_from_buffer(sg->sgl, sg->nents, (void *)data, size); | |
9e7d18c0 | 5395 | obj->dirty = 1; /* Backing store is now out of date */ |
ea70299d DG |
5396 | i915_gem_object_unpin_pages(obj); |
5397 | ||
5398 | if (WARN_ON(bytes != size)) { | |
5399 | DRM_ERROR("Incomplete copy, wrote %zu of %zu", bytes, size); | |
5400 | ret = -EFAULT; | |
5401 | goto fail; | |
5402 | } | |
5403 | ||
5404 | return obj; | |
5405 | ||
5406 | fail: | |
5407 | drm_gem_object_unreference(&obj->base); | |
5408 | return ERR_PTR(ret); | |
5409 | } |