Commit | Line | Data |
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54cf91dc CW |
1 | /* |
2 | * Copyright © 2008,2010 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | * Chris Wilson <chris@chris-wilson.co.uk> | |
26 | * | |
27 | */ | |
28 | ||
760285e7 DH |
29 | #include <drm/drmP.h> |
30 | #include <drm/i915_drm.h> | |
54cf91dc CW |
31 | #include "i915_drv.h" |
32 | #include "i915_trace.h" | |
33 | #include "intel_drv.h" | |
f45b5557 | 34 | #include <linux/dma_remapping.h> |
54cf91dc | 35 | |
67731b87 | 36 | struct eb_objects { |
bcffc3fa | 37 | struct list_head objects; |
67731b87 | 38 | int and; |
eef90ccb CW |
39 | union { |
40 | struct drm_i915_gem_object *lut[0]; | |
41 | struct hlist_head buckets[0]; | |
42 | }; | |
67731b87 CW |
43 | }; |
44 | ||
45 | static struct eb_objects * | |
eef90ccb | 46 | eb_create(struct drm_i915_gem_execbuffer2 *args) |
67731b87 | 47 | { |
eef90ccb CW |
48 | struct eb_objects *eb = NULL; |
49 | ||
50 | if (args->flags & I915_EXEC_HANDLE_LUT) { | |
51 | int size = args->buffer_count; | |
52 | size *= sizeof(struct drm_i915_gem_object *); | |
53 | size += sizeof(struct eb_objects); | |
54 | eb = kmalloc(size, GFP_TEMPORARY | __GFP_NOWARN | __GFP_NORETRY); | |
55 | } | |
56 | ||
57 | if (eb == NULL) { | |
58 | int size = args->buffer_count; | |
59 | int count = PAGE_SIZE / sizeof(struct hlist_head) / 2; | |
27b7c63a | 60 | BUILD_BUG_ON_NOT_POWER_OF_2(PAGE_SIZE / sizeof(struct hlist_head)); |
eef90ccb CW |
61 | while (count > 2*size) |
62 | count >>= 1; | |
63 | eb = kzalloc(count*sizeof(struct hlist_head) + | |
64 | sizeof(struct eb_objects), | |
65 | GFP_TEMPORARY); | |
66 | if (eb == NULL) | |
67 | return eb; | |
68 | ||
69 | eb->and = count - 1; | |
70 | } else | |
71 | eb->and = -args->buffer_count; | |
72 | ||
bcffc3fa | 73 | INIT_LIST_HEAD(&eb->objects); |
67731b87 CW |
74 | return eb; |
75 | } | |
76 | ||
77 | static void | |
78 | eb_reset(struct eb_objects *eb) | |
79 | { | |
eef90ccb CW |
80 | if (eb->and >= 0) |
81 | memset(eb->buckets, 0, (eb->and+1)*sizeof(struct hlist_head)); | |
67731b87 CW |
82 | } |
83 | ||
3b96eff4 CW |
84 | static int |
85 | eb_lookup_objects(struct eb_objects *eb, | |
86 | struct drm_i915_gem_exec_object2 *exec, | |
eef90ccb | 87 | const struct drm_i915_gem_execbuffer2 *args, |
bcffc3fa | 88 | struct drm_file *file) |
3b96eff4 CW |
89 | { |
90 | int i; | |
91 | ||
92 | spin_lock(&file->table_lock); | |
eef90ccb | 93 | for (i = 0; i < args->buffer_count; i++) { |
3b96eff4 CW |
94 | struct drm_i915_gem_object *obj; |
95 | ||
96 | obj = to_intel_bo(idr_find(&file->object_idr, exec[i].handle)); | |
97 | if (obj == NULL) { | |
98 | spin_unlock(&file->table_lock); | |
99 | DRM_DEBUG("Invalid object handle %d at index %d\n", | |
100 | exec[i].handle, i); | |
101 | return -ENOENT; | |
102 | } | |
103 | ||
104 | if (!list_empty(&obj->exec_list)) { | |
105 | spin_unlock(&file->table_lock); | |
106 | DRM_DEBUG("Object %p [handle %d, index %d] appears more than once in object list\n", | |
107 | obj, exec[i].handle, i); | |
108 | return -EINVAL; | |
109 | } | |
110 | ||
111 | drm_gem_object_reference(&obj->base); | |
bcffc3fa | 112 | list_add_tail(&obj->exec_list, &eb->objects); |
3b96eff4 | 113 | |
3b96eff4 | 114 | obj->exec_entry = &exec[i]; |
eef90ccb CW |
115 | if (eb->and < 0) { |
116 | eb->lut[i] = obj; | |
117 | } else { | |
118 | uint32_t handle = args->flags & I915_EXEC_HANDLE_LUT ? i : exec[i].handle; | |
119 | obj->exec_handle = handle; | |
120 | hlist_add_head(&obj->exec_node, | |
121 | &eb->buckets[handle & eb->and]); | |
122 | } | |
3b96eff4 CW |
123 | } |
124 | spin_unlock(&file->table_lock); | |
125 | ||
126 | return 0; | |
127 | } | |
128 | ||
67731b87 CW |
129 | static struct drm_i915_gem_object * |
130 | eb_get_object(struct eb_objects *eb, unsigned long handle) | |
131 | { | |
eef90ccb CW |
132 | if (eb->and < 0) { |
133 | if (handle >= -eb->and) | |
134 | return NULL; | |
135 | return eb->lut[handle]; | |
136 | } else { | |
137 | struct hlist_head *head; | |
138 | struct hlist_node *node; | |
67731b87 | 139 | |
eef90ccb CW |
140 | head = &eb->buckets[handle & eb->and]; |
141 | hlist_for_each(node, head) { | |
142 | struct drm_i915_gem_object *obj; | |
67731b87 | 143 | |
eef90ccb CW |
144 | obj = hlist_entry(node, struct drm_i915_gem_object, exec_node); |
145 | if (obj->exec_handle == handle) | |
146 | return obj; | |
147 | } | |
148 | return NULL; | |
149 | } | |
67731b87 CW |
150 | } |
151 | ||
152 | static void | |
153 | eb_destroy(struct eb_objects *eb) | |
154 | { | |
bcffc3fa CW |
155 | while (!list_empty(&eb->objects)) { |
156 | struct drm_i915_gem_object *obj; | |
157 | ||
158 | obj = list_first_entry(&eb->objects, | |
159 | struct drm_i915_gem_object, | |
160 | exec_list); | |
161 | list_del_init(&obj->exec_list); | |
162 | drm_gem_object_unreference(&obj->base); | |
163 | } | |
67731b87 CW |
164 | kfree(eb); |
165 | } | |
166 | ||
dabdfe02 CW |
167 | static inline int use_cpu_reloc(struct drm_i915_gem_object *obj) |
168 | { | |
169 | return (obj->base.write_domain == I915_GEM_DOMAIN_CPU || | |
504c7267 | 170 | !obj->map_and_fenceable || |
dabdfe02 CW |
171 | obj->cache_level != I915_CACHE_NONE); |
172 | } | |
173 | ||
54cf91dc CW |
174 | static int |
175 | i915_gem_execbuffer_relocate_entry(struct drm_i915_gem_object *obj, | |
67731b87 | 176 | struct eb_objects *eb, |
28d6a7bf BW |
177 | struct drm_i915_gem_relocation_entry *reloc, |
178 | struct i915_address_space *vm) | |
54cf91dc CW |
179 | { |
180 | struct drm_device *dev = obj->base.dev; | |
181 | struct drm_gem_object *target_obj; | |
149c8407 | 182 | struct drm_i915_gem_object *target_i915_obj; |
54cf91dc CW |
183 | uint32_t target_offset; |
184 | int ret = -EINVAL; | |
185 | ||
67731b87 CW |
186 | /* we've already hold a reference to all valid objects */ |
187 | target_obj = &eb_get_object(eb, reloc->target_handle)->base; | |
188 | if (unlikely(target_obj == NULL)) | |
54cf91dc CW |
189 | return -ENOENT; |
190 | ||
149c8407 | 191 | target_i915_obj = to_intel_bo(target_obj); |
f343c5f6 | 192 | target_offset = i915_gem_obj_ggtt_offset(target_i915_obj); |
54cf91dc | 193 | |
e844b990 EA |
194 | /* Sandybridge PPGTT errata: We need a global gtt mapping for MI and |
195 | * pipe_control writes because the gpu doesn't properly redirect them | |
196 | * through the ppgtt for non_secure batchbuffers. */ | |
197 | if (unlikely(IS_GEN6(dev) && | |
198 | reloc->write_domain == I915_GEM_DOMAIN_INSTRUCTION && | |
199 | !target_i915_obj->has_global_gtt_mapping)) { | |
200 | i915_gem_gtt_bind_object(target_i915_obj, | |
201 | target_i915_obj->cache_level); | |
202 | } | |
203 | ||
54cf91dc | 204 | /* Validate that the target is in a valid r/w GPU domain */ |
b8f7ab17 | 205 | if (unlikely(reloc->write_domain & (reloc->write_domain - 1))) { |
ff240199 | 206 | DRM_DEBUG("reloc with multiple write domains: " |
54cf91dc CW |
207 | "obj %p target %d offset %d " |
208 | "read %08x write %08x", | |
209 | obj, reloc->target_handle, | |
210 | (int) reloc->offset, | |
211 | reloc->read_domains, | |
212 | reloc->write_domain); | |
67731b87 | 213 | return ret; |
54cf91dc | 214 | } |
4ca4a250 DV |
215 | if (unlikely((reloc->write_domain | reloc->read_domains) |
216 | & ~I915_GEM_GPU_DOMAINS)) { | |
ff240199 | 217 | DRM_DEBUG("reloc with read/write non-GPU domains: " |
54cf91dc CW |
218 | "obj %p target %d offset %d " |
219 | "read %08x write %08x", | |
220 | obj, reloc->target_handle, | |
221 | (int) reloc->offset, | |
222 | reloc->read_domains, | |
223 | reloc->write_domain); | |
67731b87 | 224 | return ret; |
54cf91dc | 225 | } |
54cf91dc CW |
226 | |
227 | target_obj->pending_read_domains |= reloc->read_domains; | |
228 | target_obj->pending_write_domain |= reloc->write_domain; | |
229 | ||
230 | /* If the relocation already has the right value in it, no | |
231 | * more work needs to be done. | |
232 | */ | |
233 | if (target_offset == reloc->presumed_offset) | |
67731b87 | 234 | return 0; |
54cf91dc CW |
235 | |
236 | /* Check that the relocation address is valid... */ | |
b8f7ab17 | 237 | if (unlikely(reloc->offset > obj->base.size - 4)) { |
ff240199 | 238 | DRM_DEBUG("Relocation beyond object bounds: " |
54cf91dc CW |
239 | "obj %p target %d offset %d size %d.\n", |
240 | obj, reloc->target_handle, | |
241 | (int) reloc->offset, | |
242 | (int) obj->base.size); | |
67731b87 | 243 | return ret; |
54cf91dc | 244 | } |
b8f7ab17 | 245 | if (unlikely(reloc->offset & 3)) { |
ff240199 | 246 | DRM_DEBUG("Relocation not 4-byte aligned: " |
54cf91dc CW |
247 | "obj %p target %d offset %d.\n", |
248 | obj, reloc->target_handle, | |
249 | (int) reloc->offset); | |
67731b87 | 250 | return ret; |
54cf91dc CW |
251 | } |
252 | ||
dabdfe02 CW |
253 | /* We can't wait for rendering with pagefaults disabled */ |
254 | if (obj->active && in_atomic()) | |
255 | return -EFAULT; | |
256 | ||
54cf91dc | 257 | reloc->delta += target_offset; |
dabdfe02 | 258 | if (use_cpu_reloc(obj)) { |
de51f04f | 259 | uint32_t page_offset = offset_in_page(reloc->offset); |
54cf91dc CW |
260 | char *vaddr; |
261 | ||
dabdfe02 CW |
262 | ret = i915_gem_object_set_to_cpu_domain(obj, 1); |
263 | if (ret) | |
264 | return ret; | |
265 | ||
9da3da66 CW |
266 | vaddr = kmap_atomic(i915_gem_object_get_page(obj, |
267 | reloc->offset >> PAGE_SHIFT)); | |
54cf91dc CW |
268 | *(uint32_t *)(vaddr + page_offset) = reloc->delta; |
269 | kunmap_atomic(vaddr); | |
270 | } else { | |
271 | struct drm_i915_private *dev_priv = dev->dev_private; | |
272 | uint32_t __iomem *reloc_entry; | |
273 | void __iomem *reloc_page; | |
274 | ||
7b09638f CW |
275 | ret = i915_gem_object_set_to_gtt_domain(obj, true); |
276 | if (ret) | |
277 | return ret; | |
278 | ||
279 | ret = i915_gem_object_put_fence(obj); | |
54cf91dc | 280 | if (ret) |
67731b87 | 281 | return ret; |
54cf91dc CW |
282 | |
283 | /* Map the page containing the relocation we're going to perform. */ | |
f343c5f6 | 284 | reloc->offset += i915_gem_obj_ggtt_offset(obj); |
5d4545ae | 285 | reloc_page = io_mapping_map_atomic_wc(dev_priv->gtt.mappable, |
54cf91dc CW |
286 | reloc->offset & PAGE_MASK); |
287 | reloc_entry = (uint32_t __iomem *) | |
de51f04f | 288 | (reloc_page + offset_in_page(reloc->offset)); |
54cf91dc CW |
289 | iowrite32(reloc->delta, reloc_entry); |
290 | io_mapping_unmap_atomic(reloc_page); | |
291 | } | |
292 | ||
293 | /* and update the user's relocation entry */ | |
294 | reloc->presumed_offset = target_offset; | |
295 | ||
67731b87 | 296 | return 0; |
54cf91dc CW |
297 | } |
298 | ||
299 | static int | |
300 | i915_gem_execbuffer_relocate_object(struct drm_i915_gem_object *obj, | |
28d6a7bf BW |
301 | struct eb_objects *eb, |
302 | struct i915_address_space *vm) | |
54cf91dc | 303 | { |
1d83f442 CW |
304 | #define N_RELOC(x) ((x) / sizeof(struct drm_i915_gem_relocation_entry)) |
305 | struct drm_i915_gem_relocation_entry stack_reloc[N_RELOC(512)]; | |
54cf91dc | 306 | struct drm_i915_gem_relocation_entry __user *user_relocs; |
6fe4f140 | 307 | struct drm_i915_gem_exec_object2 *entry = obj->exec_entry; |
1d83f442 | 308 | int remain, ret; |
54cf91dc | 309 | |
2bb4629a | 310 | user_relocs = to_user_ptr(entry->relocs_ptr); |
54cf91dc | 311 | |
1d83f442 CW |
312 | remain = entry->relocation_count; |
313 | while (remain) { | |
314 | struct drm_i915_gem_relocation_entry *r = stack_reloc; | |
315 | int count = remain; | |
316 | if (count > ARRAY_SIZE(stack_reloc)) | |
317 | count = ARRAY_SIZE(stack_reloc); | |
318 | remain -= count; | |
319 | ||
320 | if (__copy_from_user_inatomic(r, user_relocs, count*sizeof(r[0]))) | |
54cf91dc CW |
321 | return -EFAULT; |
322 | ||
1d83f442 CW |
323 | do { |
324 | u64 offset = r->presumed_offset; | |
54cf91dc | 325 | |
28d6a7bf BW |
326 | ret = i915_gem_execbuffer_relocate_entry(obj, eb, r, |
327 | vm); | |
1d83f442 CW |
328 | if (ret) |
329 | return ret; | |
330 | ||
331 | if (r->presumed_offset != offset && | |
332 | __copy_to_user_inatomic(&user_relocs->presumed_offset, | |
333 | &r->presumed_offset, | |
334 | sizeof(r->presumed_offset))) { | |
335 | return -EFAULT; | |
336 | } | |
337 | ||
338 | user_relocs++; | |
339 | r++; | |
340 | } while (--count); | |
54cf91dc CW |
341 | } |
342 | ||
343 | return 0; | |
1d83f442 | 344 | #undef N_RELOC |
54cf91dc CW |
345 | } |
346 | ||
347 | static int | |
348 | i915_gem_execbuffer_relocate_object_slow(struct drm_i915_gem_object *obj, | |
67731b87 | 349 | struct eb_objects *eb, |
28d6a7bf BW |
350 | struct drm_i915_gem_relocation_entry *relocs, |
351 | struct i915_address_space *vm) | |
54cf91dc | 352 | { |
6fe4f140 | 353 | const struct drm_i915_gem_exec_object2 *entry = obj->exec_entry; |
54cf91dc CW |
354 | int i, ret; |
355 | ||
356 | for (i = 0; i < entry->relocation_count; i++) { | |
28d6a7bf BW |
357 | ret = i915_gem_execbuffer_relocate_entry(obj, eb, &relocs[i], |
358 | vm); | |
54cf91dc CW |
359 | if (ret) |
360 | return ret; | |
361 | } | |
362 | ||
363 | return 0; | |
364 | } | |
365 | ||
366 | static int | |
28d6a7bf BW |
367 | i915_gem_execbuffer_relocate(struct eb_objects *eb, |
368 | struct i915_address_space *vm) | |
54cf91dc | 369 | { |
432e58ed | 370 | struct drm_i915_gem_object *obj; |
d4aeee77 CW |
371 | int ret = 0; |
372 | ||
373 | /* This is the fast path and we cannot handle a pagefault whilst | |
374 | * holding the struct mutex lest the user pass in the relocations | |
375 | * contained within a mmaped bo. For in such a case we, the page | |
376 | * fault handler would call i915_gem_fault() and we would try to | |
377 | * acquire the struct mutex again. Obviously this is bad and so | |
378 | * lockdep complains vehemently. | |
379 | */ | |
380 | pagefault_disable(); | |
bcffc3fa | 381 | list_for_each_entry(obj, &eb->objects, exec_list) { |
28d6a7bf | 382 | ret = i915_gem_execbuffer_relocate_object(obj, eb, vm); |
54cf91dc | 383 | if (ret) |
d4aeee77 | 384 | break; |
54cf91dc | 385 | } |
d4aeee77 | 386 | pagefault_enable(); |
54cf91dc | 387 | |
d4aeee77 | 388 | return ret; |
54cf91dc CW |
389 | } |
390 | ||
7788a765 CW |
391 | #define __EXEC_OBJECT_HAS_PIN (1<<31) |
392 | #define __EXEC_OBJECT_HAS_FENCE (1<<30) | |
1690e1eb | 393 | |
dabdfe02 CW |
394 | static int |
395 | need_reloc_mappable(struct drm_i915_gem_object *obj) | |
396 | { | |
397 | struct drm_i915_gem_exec_object2 *entry = obj->exec_entry; | |
398 | return entry->relocation_count && !use_cpu_reloc(obj); | |
399 | } | |
400 | ||
1690e1eb | 401 | static int |
7788a765 | 402 | i915_gem_execbuffer_reserve_object(struct drm_i915_gem_object *obj, |
ed5982e6 | 403 | struct intel_ring_buffer *ring, |
28d6a7bf | 404 | struct i915_address_space *vm, |
ed5982e6 | 405 | bool *need_reloc) |
1690e1eb | 406 | { |
7788a765 | 407 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
1690e1eb CW |
408 | struct drm_i915_gem_exec_object2 *entry = obj->exec_entry; |
409 | bool has_fenced_gpu_access = INTEL_INFO(ring->dev)->gen < 4; | |
410 | bool need_fence, need_mappable; | |
411 | int ret; | |
412 | ||
413 | need_fence = | |
414 | has_fenced_gpu_access && | |
415 | entry->flags & EXEC_OBJECT_NEEDS_FENCE && | |
416 | obj->tiling_mode != I915_TILING_NONE; | |
dabdfe02 | 417 | need_mappable = need_fence || need_reloc_mappable(obj); |
1690e1eb | 418 | |
28d6a7bf BW |
419 | ret = i915_gem_object_pin(obj, vm, entry->alignment, need_mappable, |
420 | false); | |
1690e1eb CW |
421 | if (ret) |
422 | return ret; | |
423 | ||
7788a765 CW |
424 | entry->flags |= __EXEC_OBJECT_HAS_PIN; |
425 | ||
1690e1eb CW |
426 | if (has_fenced_gpu_access) { |
427 | if (entry->flags & EXEC_OBJECT_NEEDS_FENCE) { | |
06d98131 | 428 | ret = i915_gem_object_get_fence(obj); |
9a5a53b3 | 429 | if (ret) |
7788a765 | 430 | return ret; |
1690e1eb | 431 | |
9a5a53b3 | 432 | if (i915_gem_object_pin_fence(obj)) |
1690e1eb | 433 | entry->flags |= __EXEC_OBJECT_HAS_FENCE; |
9a5a53b3 | 434 | |
7dd49065 | 435 | obj->pending_fenced_gpu_access = true; |
1690e1eb | 436 | } |
1690e1eb CW |
437 | } |
438 | ||
7788a765 CW |
439 | /* Ensure ppgtt mapping exists if needed */ |
440 | if (dev_priv->mm.aliasing_ppgtt && !obj->has_aliasing_ppgtt_mapping) { | |
441 | i915_ppgtt_bind_object(dev_priv->mm.aliasing_ppgtt, | |
442 | obj, obj->cache_level); | |
443 | ||
444 | obj->has_aliasing_ppgtt_mapping = 1; | |
445 | } | |
446 | ||
28d6a7bf BW |
447 | if (entry->offset != i915_gem_obj_offset(obj, vm)) { |
448 | entry->offset = i915_gem_obj_offset(obj, vm); | |
ed5982e6 DV |
449 | *need_reloc = true; |
450 | } | |
451 | ||
452 | if (entry->flags & EXEC_OBJECT_WRITE) { | |
453 | obj->base.pending_read_domains = I915_GEM_DOMAIN_RENDER; | |
454 | obj->base.pending_write_domain = I915_GEM_DOMAIN_RENDER; | |
455 | } | |
456 | ||
457 | if (entry->flags & EXEC_OBJECT_NEEDS_GTT && | |
458 | !obj->has_global_gtt_mapping) | |
459 | i915_gem_gtt_bind_object(obj, obj->cache_level); | |
460 | ||
1690e1eb | 461 | return 0; |
7788a765 | 462 | } |
1690e1eb | 463 | |
7788a765 CW |
464 | static void |
465 | i915_gem_execbuffer_unreserve_object(struct drm_i915_gem_object *obj) | |
466 | { | |
467 | struct drm_i915_gem_exec_object2 *entry; | |
468 | ||
9843877d | 469 | if (!i915_gem_obj_bound_any(obj)) |
7788a765 CW |
470 | return; |
471 | ||
472 | entry = obj->exec_entry; | |
473 | ||
474 | if (entry->flags & __EXEC_OBJECT_HAS_FENCE) | |
475 | i915_gem_object_unpin_fence(obj); | |
476 | ||
477 | if (entry->flags & __EXEC_OBJECT_HAS_PIN) | |
478 | i915_gem_object_unpin(obj); | |
479 | ||
480 | entry->flags &= ~(__EXEC_OBJECT_HAS_FENCE | __EXEC_OBJECT_HAS_PIN); | |
1690e1eb CW |
481 | } |
482 | ||
54cf91dc | 483 | static int |
d9e86c0e | 484 | i915_gem_execbuffer_reserve(struct intel_ring_buffer *ring, |
ed5982e6 | 485 | struct list_head *objects, |
28d6a7bf | 486 | struct i915_address_space *vm, |
ed5982e6 | 487 | bool *need_relocs) |
54cf91dc | 488 | { |
432e58ed | 489 | struct drm_i915_gem_object *obj; |
6fe4f140 | 490 | struct list_head ordered_objects; |
7788a765 CW |
491 | bool has_fenced_gpu_access = INTEL_INFO(ring->dev)->gen < 4; |
492 | int retry; | |
6fe4f140 CW |
493 | |
494 | INIT_LIST_HEAD(&ordered_objects); | |
495 | while (!list_empty(objects)) { | |
496 | struct drm_i915_gem_exec_object2 *entry; | |
497 | bool need_fence, need_mappable; | |
498 | ||
499 | obj = list_first_entry(objects, | |
500 | struct drm_i915_gem_object, | |
501 | exec_list); | |
502 | entry = obj->exec_entry; | |
503 | ||
504 | need_fence = | |
505 | has_fenced_gpu_access && | |
506 | entry->flags & EXEC_OBJECT_NEEDS_FENCE && | |
507 | obj->tiling_mode != I915_TILING_NONE; | |
dabdfe02 | 508 | need_mappable = need_fence || need_reloc_mappable(obj); |
6fe4f140 CW |
509 | |
510 | if (need_mappable) | |
511 | list_move(&obj->exec_list, &ordered_objects); | |
512 | else | |
513 | list_move_tail(&obj->exec_list, &ordered_objects); | |
595dad76 | 514 | |
ed5982e6 | 515 | obj->base.pending_read_domains = I915_GEM_GPU_DOMAINS & ~I915_GEM_DOMAIN_COMMAND; |
595dad76 | 516 | obj->base.pending_write_domain = 0; |
016fd0c1 | 517 | obj->pending_fenced_gpu_access = false; |
6fe4f140 CW |
518 | } |
519 | list_splice(&ordered_objects, objects); | |
54cf91dc CW |
520 | |
521 | /* Attempt to pin all of the buffers into the GTT. | |
522 | * This is done in 3 phases: | |
523 | * | |
524 | * 1a. Unbind all objects that do not match the GTT constraints for | |
525 | * the execbuffer (fenceable, mappable, alignment etc). | |
526 | * 1b. Increment pin count for already bound objects. | |
527 | * 2. Bind new objects. | |
528 | * 3. Decrement pin count. | |
529 | * | |
7788a765 | 530 | * This avoid unnecessary unbinding of later objects in order to make |
54cf91dc CW |
531 | * room for the earlier objects *unless* we need to defragment. |
532 | */ | |
533 | retry = 0; | |
534 | do { | |
7788a765 | 535 | int ret = 0; |
54cf91dc CW |
536 | |
537 | /* Unbind any ill-fitting objects or pin. */ | |
432e58ed | 538 | list_for_each_entry(obj, objects, exec_list) { |
6fe4f140 | 539 | struct drm_i915_gem_exec_object2 *entry = obj->exec_entry; |
54cf91dc | 540 | bool need_fence, need_mappable; |
28d6a7bf | 541 | u32 obj_offset; |
1690e1eb | 542 | |
28d6a7bf | 543 | if (!i915_gem_obj_bound(obj, vm)) |
54cf91dc CW |
544 | continue; |
545 | ||
28d6a7bf | 546 | obj_offset = i915_gem_obj_offset(obj, vm); |
54cf91dc | 547 | need_fence = |
9b3826bf | 548 | has_fenced_gpu_access && |
54cf91dc CW |
549 | entry->flags & EXEC_OBJECT_NEEDS_FENCE && |
550 | obj->tiling_mode != I915_TILING_NONE; | |
dabdfe02 | 551 | need_mappable = need_fence || need_reloc_mappable(obj); |
54cf91dc | 552 | |
28d6a7bf BW |
553 | WARN_ON((need_mappable || need_fence) && |
554 | !i915_is_ggtt(vm)); | |
555 | ||
f343c5f6 | 556 | if ((entry->alignment && |
28d6a7bf | 557 | obj_offset & (entry->alignment - 1)) || |
54cf91dc | 558 | (need_mappable && !obj->map_and_fenceable)) |
07fe0b12 | 559 | ret = i915_vma_unbind(i915_gem_obj_to_vma(obj, vm)); |
54cf91dc | 560 | else |
28d6a7bf | 561 | ret = i915_gem_execbuffer_reserve_object(obj, ring, vm, need_relocs); |
432e58ed | 562 | if (ret) |
54cf91dc | 563 | goto err; |
54cf91dc CW |
564 | } |
565 | ||
566 | /* Bind fresh objects */ | |
432e58ed | 567 | list_for_each_entry(obj, objects, exec_list) { |
28d6a7bf | 568 | if (i915_gem_obj_bound(obj, vm)) |
1690e1eb | 569 | continue; |
54cf91dc | 570 | |
28d6a7bf | 571 | ret = i915_gem_execbuffer_reserve_object(obj, ring, vm, need_relocs); |
7788a765 CW |
572 | if (ret) |
573 | goto err; | |
54cf91dc CW |
574 | } |
575 | ||
7788a765 CW |
576 | err: /* Decrement pin count for bound objects */ |
577 | list_for_each_entry(obj, objects, exec_list) | |
578 | i915_gem_execbuffer_unreserve_object(obj); | |
54cf91dc | 579 | |
6c085a72 | 580 | if (ret != -ENOSPC || retry++) |
54cf91dc CW |
581 | return ret; |
582 | ||
6c085a72 | 583 | ret = i915_gem_evict_everything(ring->dev); |
54cf91dc CW |
584 | if (ret) |
585 | return ret; | |
54cf91dc CW |
586 | } while (1); |
587 | } | |
588 | ||
589 | static int | |
590 | i915_gem_execbuffer_relocate_slow(struct drm_device *dev, | |
ed5982e6 | 591 | struct drm_i915_gem_execbuffer2 *args, |
54cf91dc | 592 | struct drm_file *file, |
d9e86c0e | 593 | struct intel_ring_buffer *ring, |
67731b87 | 594 | struct eb_objects *eb, |
28d6a7bf BW |
595 | struct drm_i915_gem_exec_object2 *exec, |
596 | struct i915_address_space *vm) | |
54cf91dc CW |
597 | { |
598 | struct drm_i915_gem_relocation_entry *reloc; | |
432e58ed | 599 | struct drm_i915_gem_object *obj; |
ed5982e6 | 600 | bool need_relocs; |
dd6864a4 | 601 | int *reloc_offset; |
54cf91dc | 602 | int i, total, ret; |
ed5982e6 | 603 | int count = args->buffer_count; |
54cf91dc | 604 | |
67731b87 | 605 | /* We may process another execbuffer during the unlock... */ |
bcffc3fa CW |
606 | while (!list_empty(&eb->objects)) { |
607 | obj = list_first_entry(&eb->objects, | |
67731b87 CW |
608 | struct drm_i915_gem_object, |
609 | exec_list); | |
610 | list_del_init(&obj->exec_list); | |
611 | drm_gem_object_unreference(&obj->base); | |
612 | } | |
613 | ||
54cf91dc CW |
614 | mutex_unlock(&dev->struct_mutex); |
615 | ||
616 | total = 0; | |
617 | for (i = 0; i < count; i++) | |
432e58ed | 618 | total += exec[i].relocation_count; |
54cf91dc | 619 | |
dd6864a4 | 620 | reloc_offset = drm_malloc_ab(count, sizeof(*reloc_offset)); |
54cf91dc | 621 | reloc = drm_malloc_ab(total, sizeof(*reloc)); |
dd6864a4 CW |
622 | if (reloc == NULL || reloc_offset == NULL) { |
623 | drm_free_large(reloc); | |
624 | drm_free_large(reloc_offset); | |
54cf91dc CW |
625 | mutex_lock(&dev->struct_mutex); |
626 | return -ENOMEM; | |
627 | } | |
628 | ||
629 | total = 0; | |
630 | for (i = 0; i < count; i++) { | |
631 | struct drm_i915_gem_relocation_entry __user *user_relocs; | |
262b6d36 CW |
632 | u64 invalid_offset = (u64)-1; |
633 | int j; | |
54cf91dc | 634 | |
2bb4629a | 635 | user_relocs = to_user_ptr(exec[i].relocs_ptr); |
54cf91dc CW |
636 | |
637 | if (copy_from_user(reloc+total, user_relocs, | |
432e58ed | 638 | exec[i].relocation_count * sizeof(*reloc))) { |
54cf91dc CW |
639 | ret = -EFAULT; |
640 | mutex_lock(&dev->struct_mutex); | |
641 | goto err; | |
642 | } | |
643 | ||
262b6d36 CW |
644 | /* As we do not update the known relocation offsets after |
645 | * relocating (due to the complexities in lock handling), | |
646 | * we need to mark them as invalid now so that we force the | |
647 | * relocation processing next time. Just in case the target | |
648 | * object is evicted and then rebound into its old | |
649 | * presumed_offset before the next execbuffer - if that | |
650 | * happened we would make the mistake of assuming that the | |
651 | * relocations were valid. | |
652 | */ | |
653 | for (j = 0; j < exec[i].relocation_count; j++) { | |
654 | if (copy_to_user(&user_relocs[j].presumed_offset, | |
655 | &invalid_offset, | |
656 | sizeof(invalid_offset))) { | |
657 | ret = -EFAULT; | |
658 | mutex_lock(&dev->struct_mutex); | |
659 | goto err; | |
660 | } | |
661 | } | |
662 | ||
dd6864a4 | 663 | reloc_offset[i] = total; |
432e58ed | 664 | total += exec[i].relocation_count; |
54cf91dc CW |
665 | } |
666 | ||
667 | ret = i915_mutex_lock_interruptible(dev); | |
668 | if (ret) { | |
669 | mutex_lock(&dev->struct_mutex); | |
670 | goto err; | |
671 | } | |
672 | ||
67731b87 | 673 | /* reacquire the objects */ |
67731b87 | 674 | eb_reset(eb); |
eef90ccb | 675 | ret = eb_lookup_objects(eb, exec, args, file); |
3b96eff4 CW |
676 | if (ret) |
677 | goto err; | |
67731b87 | 678 | |
ed5982e6 | 679 | need_relocs = (args->flags & I915_EXEC_NO_RELOC) == 0; |
28d6a7bf | 680 | ret = i915_gem_execbuffer_reserve(ring, &eb->objects, vm, &need_relocs); |
54cf91dc CW |
681 | if (ret) |
682 | goto err; | |
683 | ||
bcffc3fa | 684 | list_for_each_entry(obj, &eb->objects, exec_list) { |
dd6864a4 | 685 | int offset = obj->exec_entry - exec; |
67731b87 | 686 | ret = i915_gem_execbuffer_relocate_object_slow(obj, eb, |
28d6a7bf BW |
687 | reloc + reloc_offset[offset], |
688 | vm); | |
54cf91dc CW |
689 | if (ret) |
690 | goto err; | |
54cf91dc CW |
691 | } |
692 | ||
693 | /* Leave the user relocations as are, this is the painfully slow path, | |
694 | * and we want to avoid the complication of dropping the lock whilst | |
695 | * having buffers reserved in the aperture and so causing spurious | |
696 | * ENOSPC for random operations. | |
697 | */ | |
698 | ||
699 | err: | |
700 | drm_free_large(reloc); | |
dd6864a4 | 701 | drm_free_large(reloc_offset); |
54cf91dc CW |
702 | return ret; |
703 | } | |
704 | ||
54cf91dc | 705 | static int |
432e58ed CW |
706 | i915_gem_execbuffer_move_to_gpu(struct intel_ring_buffer *ring, |
707 | struct list_head *objects) | |
54cf91dc | 708 | { |
432e58ed | 709 | struct drm_i915_gem_object *obj; |
6ac42f41 | 710 | uint32_t flush_domains = 0; |
000433b6 | 711 | bool flush_chipset = false; |
432e58ed | 712 | int ret; |
54cf91dc | 713 | |
6ac42f41 DV |
714 | list_for_each_entry(obj, objects, exec_list) { |
715 | ret = i915_gem_object_sync(obj, ring); | |
c59a333f CW |
716 | if (ret) |
717 | return ret; | |
6ac42f41 DV |
718 | |
719 | if (obj->base.write_domain & I915_GEM_DOMAIN_CPU) | |
000433b6 | 720 | flush_chipset |= i915_gem_clflush_object(obj, false); |
6ac42f41 | 721 | |
6ac42f41 | 722 | flush_domains |= obj->base.write_domain; |
c59a333f CW |
723 | } |
724 | ||
000433b6 | 725 | if (flush_chipset) |
e76e9aeb | 726 | i915_gem_chipset_flush(ring->dev); |
6ac42f41 DV |
727 | |
728 | if (flush_domains & I915_GEM_DOMAIN_GTT) | |
729 | wmb(); | |
730 | ||
09cf7c9a CW |
731 | /* Unconditionally invalidate gpu caches and ensure that we do flush |
732 | * any residual writes from the previous batch. | |
733 | */ | |
a7b9761d | 734 | return intel_ring_invalidate_all_caches(ring); |
54cf91dc CW |
735 | } |
736 | ||
432e58ed CW |
737 | static bool |
738 | i915_gem_check_execbuffer(struct drm_i915_gem_execbuffer2 *exec) | |
54cf91dc | 739 | { |
ed5982e6 DV |
740 | if (exec->flags & __I915_EXEC_UNKNOWN_FLAGS) |
741 | return false; | |
742 | ||
432e58ed | 743 | return ((exec->batch_start_offset | exec->batch_len) & 0x7) == 0; |
54cf91dc CW |
744 | } |
745 | ||
746 | static int | |
747 | validate_exec_list(struct drm_i915_gem_exec_object2 *exec, | |
748 | int count) | |
749 | { | |
750 | int i; | |
3118a4f6 KC |
751 | int relocs_total = 0; |
752 | int relocs_max = INT_MAX / sizeof(struct drm_i915_gem_relocation_entry); | |
54cf91dc CW |
753 | |
754 | for (i = 0; i < count; i++) { | |
2bb4629a | 755 | char __user *ptr = to_user_ptr(exec[i].relocs_ptr); |
54cf91dc CW |
756 | int length; /* limited by fault_in_pages_readable() */ |
757 | ||
ed5982e6 DV |
758 | if (exec[i].flags & __EXEC_OBJECT_UNKNOWN_FLAGS) |
759 | return -EINVAL; | |
760 | ||
3118a4f6 KC |
761 | /* First check for malicious input causing overflow in |
762 | * the worst case where we need to allocate the entire | |
763 | * relocation tree as a single array. | |
764 | */ | |
765 | if (exec[i].relocation_count > relocs_max - relocs_total) | |
54cf91dc | 766 | return -EINVAL; |
3118a4f6 | 767 | relocs_total += exec[i].relocation_count; |
54cf91dc CW |
768 | |
769 | length = exec[i].relocation_count * | |
770 | sizeof(struct drm_i915_gem_relocation_entry); | |
30587535 KC |
771 | /* |
772 | * We must check that the entire relocation array is safe | |
773 | * to read, but since we may need to update the presumed | |
774 | * offsets during execution, check for full write access. | |
775 | */ | |
54cf91dc CW |
776 | if (!access_ok(VERIFY_WRITE, ptr, length)) |
777 | return -EFAULT; | |
778 | ||
0b74b508 XZ |
779 | if (likely(!i915_prefault_disable)) { |
780 | if (fault_in_multipages_readable(ptr, length)) | |
781 | return -EFAULT; | |
782 | } | |
54cf91dc CW |
783 | } |
784 | ||
785 | return 0; | |
786 | } | |
787 | ||
432e58ed CW |
788 | static void |
789 | i915_gem_execbuffer_move_to_active(struct list_head *objects, | |
28d6a7bf | 790 | struct i915_address_space *vm, |
9d773091 | 791 | struct intel_ring_buffer *ring) |
432e58ed CW |
792 | { |
793 | struct drm_i915_gem_object *obj; | |
794 | ||
795 | list_for_each_entry(obj, objects, exec_list) { | |
69c2fc89 CW |
796 | u32 old_read = obj->base.read_domains; |
797 | u32 old_write = obj->base.write_domain; | |
db53a302 | 798 | |
432e58ed | 799 | obj->base.write_domain = obj->base.pending_write_domain; |
ed5982e6 DV |
800 | if (obj->base.write_domain == 0) |
801 | obj->base.pending_read_domains |= obj->base.read_domains; | |
802 | obj->base.read_domains = obj->base.pending_read_domains; | |
432e58ed CW |
803 | obj->fenced_gpu_access = obj->pending_fenced_gpu_access; |
804 | ||
ca191b13 BW |
805 | /* FIXME: This lookup gets fixed later <-- danvet */ |
806 | list_move_tail(&i915_gem_obj_to_vma(obj, vm)->mm_list, &vm->active_list); | |
9d773091 | 807 | i915_gem_object_move_to_active(obj, ring); |
432e58ed CW |
808 | if (obj->base.write_domain) { |
809 | obj->dirty = 1; | |
9d773091 | 810 | obj->last_write_seqno = intel_ring_get_seqno(ring); |
acb87dfb | 811 | if (obj->pin_count) /* check for potential scanout */ |
c65355bb | 812 | intel_mark_fb_busy(obj, ring); |
432e58ed CW |
813 | } |
814 | ||
db53a302 | 815 | trace_i915_gem_object_change_domain(obj, old_read, old_write); |
432e58ed CW |
816 | } |
817 | } | |
818 | ||
54cf91dc CW |
819 | static void |
820 | i915_gem_execbuffer_retire_commands(struct drm_device *dev, | |
432e58ed | 821 | struct drm_file *file, |
7d736f4f MK |
822 | struct intel_ring_buffer *ring, |
823 | struct drm_i915_gem_object *obj) | |
54cf91dc | 824 | { |
cc889e0f DV |
825 | /* Unconditionally force add_request to emit a full flush. */ |
826 | ring->gpu_caches_dirty = true; | |
54cf91dc | 827 | |
432e58ed | 828 | /* Add a breadcrumb for the completion of the batch buffer */ |
7d736f4f | 829 | (void)__i915_add_request(ring, file, obj, NULL); |
432e58ed | 830 | } |
54cf91dc | 831 | |
ae662d31 EA |
832 | static int |
833 | i915_reset_gen7_sol_offsets(struct drm_device *dev, | |
834 | struct intel_ring_buffer *ring) | |
835 | { | |
836 | drm_i915_private_t *dev_priv = dev->dev_private; | |
837 | int ret, i; | |
838 | ||
839 | if (!IS_GEN7(dev) || ring != &dev_priv->ring[RCS]) | |
840 | return 0; | |
841 | ||
842 | ret = intel_ring_begin(ring, 4 * 3); | |
843 | if (ret) | |
844 | return ret; | |
845 | ||
846 | for (i = 0; i < 4; i++) { | |
847 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); | |
848 | intel_ring_emit(ring, GEN7_SO_WRITE_OFFSET(i)); | |
849 | intel_ring_emit(ring, 0); | |
850 | } | |
851 | ||
852 | intel_ring_advance(ring); | |
853 | ||
854 | return 0; | |
855 | } | |
856 | ||
54cf91dc CW |
857 | static int |
858 | i915_gem_do_execbuffer(struct drm_device *dev, void *data, | |
859 | struct drm_file *file, | |
860 | struct drm_i915_gem_execbuffer2 *args, | |
28d6a7bf BW |
861 | struct drm_i915_gem_exec_object2 *exec, |
862 | struct i915_address_space *vm) | |
54cf91dc CW |
863 | { |
864 | drm_i915_private_t *dev_priv = dev->dev_private; | |
67731b87 | 865 | struct eb_objects *eb; |
54cf91dc CW |
866 | struct drm_i915_gem_object *batch_obj; |
867 | struct drm_clip_rect *cliprects = NULL; | |
54cf91dc | 868 | struct intel_ring_buffer *ring; |
6e0a69db | 869 | u32 ctx_id = i915_execbuffer2_get_context_id(*args); |
c4e7a414 | 870 | u32 exec_start, exec_len; |
ed5982e6 | 871 | u32 mask, flags; |
72bfa19c | 872 | int ret, mode, i; |
ed5982e6 | 873 | bool need_relocs; |
54cf91dc | 874 | |
ed5982e6 | 875 | if (!i915_gem_check_execbuffer(args)) |
432e58ed | 876 | return -EINVAL; |
432e58ed CW |
877 | |
878 | ret = validate_exec_list(exec, args->buffer_count); | |
54cf91dc CW |
879 | if (ret) |
880 | return ret; | |
881 | ||
d7d4eedd CW |
882 | flags = 0; |
883 | if (args->flags & I915_EXEC_SECURE) { | |
884 | if (!file->is_master || !capable(CAP_SYS_ADMIN)) | |
885 | return -EPERM; | |
886 | ||
887 | flags |= I915_DISPATCH_SECURE; | |
888 | } | |
b45305fc DV |
889 | if (args->flags & I915_EXEC_IS_PINNED) |
890 | flags |= I915_DISPATCH_PINNED; | |
d7d4eedd | 891 | |
54cf91dc CW |
892 | switch (args->flags & I915_EXEC_RING_MASK) { |
893 | case I915_EXEC_DEFAULT: | |
894 | case I915_EXEC_RENDER: | |
1ec14ad3 | 895 | ring = &dev_priv->ring[RCS]; |
54cf91dc CW |
896 | break; |
897 | case I915_EXEC_BSD: | |
1ec14ad3 | 898 | ring = &dev_priv->ring[VCS]; |
e8520969 | 899 | if (ctx_id != DEFAULT_CONTEXT_ID) { |
6e0a69db BW |
900 | DRM_DEBUG("Ring %s doesn't support contexts\n", |
901 | ring->name); | |
902 | return -EPERM; | |
903 | } | |
54cf91dc CW |
904 | break; |
905 | case I915_EXEC_BLT: | |
1ec14ad3 | 906 | ring = &dev_priv->ring[BCS]; |
e8520969 | 907 | if (ctx_id != DEFAULT_CONTEXT_ID) { |
6e0a69db BW |
908 | DRM_DEBUG("Ring %s doesn't support contexts\n", |
909 | ring->name); | |
910 | return -EPERM; | |
911 | } | |
54cf91dc | 912 | break; |
82f91b6e XH |
913 | case I915_EXEC_VEBOX: |
914 | ring = &dev_priv->ring[VECS]; | |
e8520969 | 915 | if (ctx_id != DEFAULT_CONTEXT_ID) { |
82f91b6e XH |
916 | DRM_DEBUG("Ring %s doesn't support contexts\n", |
917 | ring->name); | |
918 | return -EPERM; | |
919 | } | |
920 | break; | |
921 | ||
54cf91dc | 922 | default: |
ff240199 | 923 | DRM_DEBUG("execbuf with unknown ring: %d\n", |
54cf91dc CW |
924 | (int)(args->flags & I915_EXEC_RING_MASK)); |
925 | return -EINVAL; | |
926 | } | |
a15817cf CW |
927 | if (!intel_ring_initialized(ring)) { |
928 | DRM_DEBUG("execbuf with invalid ring: %d\n", | |
929 | (int)(args->flags & I915_EXEC_RING_MASK)); | |
930 | return -EINVAL; | |
931 | } | |
54cf91dc | 932 | |
72bfa19c | 933 | mode = args->flags & I915_EXEC_CONSTANTS_MASK; |
84f9f938 | 934 | mask = I915_EXEC_CONSTANTS_MASK; |
72bfa19c CW |
935 | switch (mode) { |
936 | case I915_EXEC_CONSTANTS_REL_GENERAL: | |
937 | case I915_EXEC_CONSTANTS_ABSOLUTE: | |
938 | case I915_EXEC_CONSTANTS_REL_SURFACE: | |
939 | if (ring == &dev_priv->ring[RCS] && | |
940 | mode != dev_priv->relative_constants_mode) { | |
941 | if (INTEL_INFO(dev)->gen < 4) | |
942 | return -EINVAL; | |
943 | ||
944 | if (INTEL_INFO(dev)->gen > 5 && | |
945 | mode == I915_EXEC_CONSTANTS_REL_SURFACE) | |
946 | return -EINVAL; | |
84f9f938 BW |
947 | |
948 | /* The HW changed the meaning on this bit on gen6 */ | |
949 | if (INTEL_INFO(dev)->gen >= 6) | |
950 | mask &= ~I915_EXEC_CONSTANTS_REL_SURFACE; | |
72bfa19c CW |
951 | } |
952 | break; | |
953 | default: | |
ff240199 | 954 | DRM_DEBUG("execbuf with unknown constants: %d\n", mode); |
72bfa19c CW |
955 | return -EINVAL; |
956 | } | |
957 | ||
54cf91dc | 958 | if (args->buffer_count < 1) { |
ff240199 | 959 | DRM_DEBUG("execbuf with %d buffers\n", args->buffer_count); |
54cf91dc CW |
960 | return -EINVAL; |
961 | } | |
54cf91dc CW |
962 | |
963 | if (args->num_cliprects != 0) { | |
1ec14ad3 | 964 | if (ring != &dev_priv->ring[RCS]) { |
ff240199 | 965 | DRM_DEBUG("clip rectangles are only valid with the render ring\n"); |
c4e7a414 CW |
966 | return -EINVAL; |
967 | } | |
968 | ||
6ebebc92 DV |
969 | if (INTEL_INFO(dev)->gen >= 5) { |
970 | DRM_DEBUG("clip rectangles are only valid on pre-gen5\n"); | |
971 | return -EINVAL; | |
972 | } | |
973 | ||
44afb3a0 XW |
974 | if (args->num_cliprects > UINT_MAX / sizeof(*cliprects)) { |
975 | DRM_DEBUG("execbuf with %u cliprects\n", | |
976 | args->num_cliprects); | |
977 | return -EINVAL; | |
978 | } | |
5e13a0c5 | 979 | |
432e58ed | 980 | cliprects = kmalloc(args->num_cliprects * sizeof(*cliprects), |
54cf91dc CW |
981 | GFP_KERNEL); |
982 | if (cliprects == NULL) { | |
983 | ret = -ENOMEM; | |
984 | goto pre_mutex_err; | |
985 | } | |
986 | ||
432e58ed | 987 | if (copy_from_user(cliprects, |
2bb4629a VS |
988 | to_user_ptr(args->cliprects_ptr), |
989 | sizeof(*cliprects)*args->num_cliprects)) { | |
54cf91dc CW |
990 | ret = -EFAULT; |
991 | goto pre_mutex_err; | |
992 | } | |
993 | } | |
994 | ||
54cf91dc CW |
995 | ret = i915_mutex_lock_interruptible(dev); |
996 | if (ret) | |
997 | goto pre_mutex_err; | |
998 | ||
db1b76ca | 999 | if (dev_priv->ums.mm_suspended) { |
54cf91dc CW |
1000 | mutex_unlock(&dev->struct_mutex); |
1001 | ret = -EBUSY; | |
1002 | goto pre_mutex_err; | |
1003 | } | |
1004 | ||
eef90ccb | 1005 | eb = eb_create(args); |
67731b87 CW |
1006 | if (eb == NULL) { |
1007 | mutex_unlock(&dev->struct_mutex); | |
1008 | ret = -ENOMEM; | |
1009 | goto pre_mutex_err; | |
1010 | } | |
1011 | ||
54cf91dc | 1012 | /* Look up object handles */ |
eef90ccb | 1013 | ret = eb_lookup_objects(eb, exec, args, file); |
3b96eff4 CW |
1014 | if (ret) |
1015 | goto err; | |
54cf91dc | 1016 | |
6fe4f140 | 1017 | /* take note of the batch buffer before we might reorder the lists */ |
bcffc3fa | 1018 | batch_obj = list_entry(eb->objects.prev, |
6fe4f140 CW |
1019 | struct drm_i915_gem_object, |
1020 | exec_list); | |
1021 | ||
54cf91dc | 1022 | /* Move the objects en-masse into the GTT, evicting if necessary. */ |
ed5982e6 | 1023 | need_relocs = (args->flags & I915_EXEC_NO_RELOC) == 0; |
28d6a7bf | 1024 | ret = i915_gem_execbuffer_reserve(ring, &eb->objects, vm, &need_relocs); |
54cf91dc CW |
1025 | if (ret) |
1026 | goto err; | |
1027 | ||
1028 | /* The objects are in their final locations, apply the relocations. */ | |
ed5982e6 | 1029 | if (need_relocs) |
28d6a7bf | 1030 | ret = i915_gem_execbuffer_relocate(eb, vm); |
54cf91dc CW |
1031 | if (ret) { |
1032 | if (ret == -EFAULT) { | |
ed5982e6 | 1033 | ret = i915_gem_execbuffer_relocate_slow(dev, args, file, ring, |
28d6a7bf | 1034 | eb, exec, vm); |
54cf91dc CW |
1035 | BUG_ON(!mutex_is_locked(&dev->struct_mutex)); |
1036 | } | |
1037 | if (ret) | |
1038 | goto err; | |
1039 | } | |
1040 | ||
1041 | /* Set the pending read domains for the batch buffer to COMMAND */ | |
54cf91dc | 1042 | if (batch_obj->base.pending_write_domain) { |
ff240199 | 1043 | DRM_DEBUG("Attempting to use self-modifying batch buffer\n"); |
54cf91dc CW |
1044 | ret = -EINVAL; |
1045 | goto err; | |
1046 | } | |
1047 | batch_obj->base.pending_read_domains |= I915_GEM_DOMAIN_COMMAND; | |
1048 | ||
d7d4eedd CW |
1049 | /* snb/ivb/vlv conflate the "batch in ppgtt" bit with the "non-secure |
1050 | * batch" bit. Hence we need to pin secure batches into the global gtt. | |
1051 | * hsw should have this fixed, but let's be paranoid and do it | |
1052 | * unconditionally for now. */ | |
1053 | if (flags & I915_DISPATCH_SECURE && !batch_obj->has_global_gtt_mapping) | |
1054 | i915_gem_gtt_bind_object(batch_obj, batch_obj->cache_level); | |
1055 | ||
bcffc3fa | 1056 | ret = i915_gem_execbuffer_move_to_gpu(ring, &eb->objects); |
432e58ed | 1057 | if (ret) |
54cf91dc | 1058 | goto err; |
54cf91dc | 1059 | |
0da5cec1 EA |
1060 | ret = i915_switch_context(ring, file, ctx_id); |
1061 | if (ret) | |
1062 | goto err; | |
1063 | ||
e2971bda BW |
1064 | if (ring == &dev_priv->ring[RCS] && |
1065 | mode != dev_priv->relative_constants_mode) { | |
1066 | ret = intel_ring_begin(ring, 4); | |
1067 | if (ret) | |
1068 | goto err; | |
1069 | ||
1070 | intel_ring_emit(ring, MI_NOOP); | |
1071 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); | |
1072 | intel_ring_emit(ring, INSTPM); | |
84f9f938 | 1073 | intel_ring_emit(ring, mask << 16 | mode); |
e2971bda BW |
1074 | intel_ring_advance(ring); |
1075 | ||
1076 | dev_priv->relative_constants_mode = mode; | |
1077 | } | |
1078 | ||
ae662d31 EA |
1079 | if (args->flags & I915_EXEC_GEN7_SOL_RESET) { |
1080 | ret = i915_reset_gen7_sol_offsets(dev, ring); | |
1081 | if (ret) | |
1082 | goto err; | |
1083 | } | |
1084 | ||
28d6a7bf BW |
1085 | exec_start = i915_gem_obj_offset(batch_obj, vm) + |
1086 | args->batch_start_offset; | |
c4e7a414 CW |
1087 | exec_len = args->batch_len; |
1088 | if (cliprects) { | |
1089 | for (i = 0; i < args->num_cliprects; i++) { | |
1090 | ret = i915_emit_box(dev, &cliprects[i], | |
1091 | args->DR1, args->DR4); | |
1092 | if (ret) | |
1093 | goto err; | |
1094 | ||
1095 | ret = ring->dispatch_execbuffer(ring, | |
d7d4eedd CW |
1096 | exec_start, exec_len, |
1097 | flags); | |
c4e7a414 CW |
1098 | if (ret) |
1099 | goto err; | |
1100 | } | |
1101 | } else { | |
d7d4eedd CW |
1102 | ret = ring->dispatch_execbuffer(ring, |
1103 | exec_start, exec_len, | |
1104 | flags); | |
c4e7a414 CW |
1105 | if (ret) |
1106 | goto err; | |
1107 | } | |
54cf91dc | 1108 | |
9d773091 CW |
1109 | trace_i915_gem_ring_dispatch(ring, intel_ring_get_seqno(ring), flags); |
1110 | ||
28d6a7bf | 1111 | i915_gem_execbuffer_move_to_active(&eb->objects, vm, ring); |
7d736f4f | 1112 | i915_gem_execbuffer_retire_commands(dev, file, ring, batch_obj); |
54cf91dc CW |
1113 | |
1114 | err: | |
67731b87 | 1115 | eb_destroy(eb); |
54cf91dc CW |
1116 | |
1117 | mutex_unlock(&dev->struct_mutex); | |
1118 | ||
1119 | pre_mutex_err: | |
54cf91dc | 1120 | kfree(cliprects); |
54cf91dc CW |
1121 | return ret; |
1122 | } | |
1123 | ||
1124 | /* | |
1125 | * Legacy execbuffer just creates an exec2 list from the original exec object | |
1126 | * list array and passes it to the real function. | |
1127 | */ | |
1128 | int | |
1129 | i915_gem_execbuffer(struct drm_device *dev, void *data, | |
1130 | struct drm_file *file) | |
1131 | { | |
28d6a7bf | 1132 | struct drm_i915_private *dev_priv = dev->dev_private; |
54cf91dc CW |
1133 | struct drm_i915_gem_execbuffer *args = data; |
1134 | struct drm_i915_gem_execbuffer2 exec2; | |
1135 | struct drm_i915_gem_exec_object *exec_list = NULL; | |
1136 | struct drm_i915_gem_exec_object2 *exec2_list = NULL; | |
1137 | int ret, i; | |
1138 | ||
54cf91dc | 1139 | if (args->buffer_count < 1) { |
ff240199 | 1140 | DRM_DEBUG("execbuf with %d buffers\n", args->buffer_count); |
54cf91dc CW |
1141 | return -EINVAL; |
1142 | } | |
1143 | ||
1144 | /* Copy in the exec list from userland */ | |
1145 | exec_list = drm_malloc_ab(sizeof(*exec_list), args->buffer_count); | |
1146 | exec2_list = drm_malloc_ab(sizeof(*exec2_list), args->buffer_count); | |
1147 | if (exec_list == NULL || exec2_list == NULL) { | |
ff240199 | 1148 | DRM_DEBUG("Failed to allocate exec list for %d buffers\n", |
54cf91dc CW |
1149 | args->buffer_count); |
1150 | drm_free_large(exec_list); | |
1151 | drm_free_large(exec2_list); | |
1152 | return -ENOMEM; | |
1153 | } | |
1154 | ret = copy_from_user(exec_list, | |
2bb4629a | 1155 | to_user_ptr(args->buffers_ptr), |
54cf91dc CW |
1156 | sizeof(*exec_list) * args->buffer_count); |
1157 | if (ret != 0) { | |
ff240199 | 1158 | DRM_DEBUG("copy %d exec entries failed %d\n", |
54cf91dc CW |
1159 | args->buffer_count, ret); |
1160 | drm_free_large(exec_list); | |
1161 | drm_free_large(exec2_list); | |
1162 | return -EFAULT; | |
1163 | } | |
1164 | ||
1165 | for (i = 0; i < args->buffer_count; i++) { | |
1166 | exec2_list[i].handle = exec_list[i].handle; | |
1167 | exec2_list[i].relocation_count = exec_list[i].relocation_count; | |
1168 | exec2_list[i].relocs_ptr = exec_list[i].relocs_ptr; | |
1169 | exec2_list[i].alignment = exec_list[i].alignment; | |
1170 | exec2_list[i].offset = exec_list[i].offset; | |
1171 | if (INTEL_INFO(dev)->gen < 4) | |
1172 | exec2_list[i].flags = EXEC_OBJECT_NEEDS_FENCE; | |
1173 | else | |
1174 | exec2_list[i].flags = 0; | |
1175 | } | |
1176 | ||
1177 | exec2.buffers_ptr = args->buffers_ptr; | |
1178 | exec2.buffer_count = args->buffer_count; | |
1179 | exec2.batch_start_offset = args->batch_start_offset; | |
1180 | exec2.batch_len = args->batch_len; | |
1181 | exec2.DR1 = args->DR1; | |
1182 | exec2.DR4 = args->DR4; | |
1183 | exec2.num_cliprects = args->num_cliprects; | |
1184 | exec2.cliprects_ptr = args->cliprects_ptr; | |
1185 | exec2.flags = I915_EXEC_RENDER; | |
6e0a69db | 1186 | i915_execbuffer2_set_context_id(exec2, 0); |
54cf91dc | 1187 | |
28d6a7bf BW |
1188 | ret = i915_gem_do_execbuffer(dev, data, file, &exec2, exec2_list, |
1189 | &dev_priv->gtt.base); | |
54cf91dc CW |
1190 | if (!ret) { |
1191 | /* Copy the new buffer offsets back to the user's exec list. */ | |
1192 | for (i = 0; i < args->buffer_count; i++) | |
1193 | exec_list[i].offset = exec2_list[i].offset; | |
1194 | /* ... and back out to userspace */ | |
2bb4629a | 1195 | ret = copy_to_user(to_user_ptr(args->buffers_ptr), |
54cf91dc CW |
1196 | exec_list, |
1197 | sizeof(*exec_list) * args->buffer_count); | |
1198 | if (ret) { | |
1199 | ret = -EFAULT; | |
ff240199 | 1200 | DRM_DEBUG("failed to copy %d exec entries " |
54cf91dc CW |
1201 | "back to user (%d)\n", |
1202 | args->buffer_count, ret); | |
1203 | } | |
1204 | } | |
1205 | ||
1206 | drm_free_large(exec_list); | |
1207 | drm_free_large(exec2_list); | |
1208 | return ret; | |
1209 | } | |
1210 | ||
1211 | int | |
1212 | i915_gem_execbuffer2(struct drm_device *dev, void *data, | |
1213 | struct drm_file *file) | |
1214 | { | |
28d6a7bf | 1215 | struct drm_i915_private *dev_priv = dev->dev_private; |
54cf91dc CW |
1216 | struct drm_i915_gem_execbuffer2 *args = data; |
1217 | struct drm_i915_gem_exec_object2 *exec2_list = NULL; | |
1218 | int ret; | |
1219 | ||
ed8cd3b2 XW |
1220 | if (args->buffer_count < 1 || |
1221 | args->buffer_count > UINT_MAX / sizeof(*exec2_list)) { | |
ff240199 | 1222 | DRM_DEBUG("execbuf2 with %d buffers\n", args->buffer_count); |
54cf91dc CW |
1223 | return -EINVAL; |
1224 | } | |
1225 | ||
8408c282 | 1226 | exec2_list = kmalloc(sizeof(*exec2_list)*args->buffer_count, |
419fa72a | 1227 | GFP_TEMPORARY | __GFP_NOWARN | __GFP_NORETRY); |
8408c282 CW |
1228 | if (exec2_list == NULL) |
1229 | exec2_list = drm_malloc_ab(sizeof(*exec2_list), | |
1230 | args->buffer_count); | |
54cf91dc | 1231 | if (exec2_list == NULL) { |
ff240199 | 1232 | DRM_DEBUG("Failed to allocate exec list for %d buffers\n", |
54cf91dc CW |
1233 | args->buffer_count); |
1234 | return -ENOMEM; | |
1235 | } | |
1236 | ret = copy_from_user(exec2_list, | |
2bb4629a | 1237 | to_user_ptr(args->buffers_ptr), |
54cf91dc CW |
1238 | sizeof(*exec2_list) * args->buffer_count); |
1239 | if (ret != 0) { | |
ff240199 | 1240 | DRM_DEBUG("copy %d exec entries failed %d\n", |
54cf91dc CW |
1241 | args->buffer_count, ret); |
1242 | drm_free_large(exec2_list); | |
1243 | return -EFAULT; | |
1244 | } | |
1245 | ||
28d6a7bf BW |
1246 | ret = i915_gem_do_execbuffer(dev, data, file, args, exec2_list, |
1247 | &dev_priv->gtt.base); | |
54cf91dc CW |
1248 | if (!ret) { |
1249 | /* Copy the new buffer offsets back to the user's exec list. */ | |
2bb4629a | 1250 | ret = copy_to_user(to_user_ptr(args->buffers_ptr), |
54cf91dc CW |
1251 | exec2_list, |
1252 | sizeof(*exec2_list) * args->buffer_count); | |
1253 | if (ret) { | |
1254 | ret = -EFAULT; | |
ff240199 | 1255 | DRM_DEBUG("failed to copy %d exec entries " |
54cf91dc CW |
1256 | "back to user (%d)\n", |
1257 | args->buffer_count, ret); | |
1258 | } | |
1259 | } | |
1260 | ||
1261 | drm_free_large(exec2_list); | |
1262 | return ret; | |
1263 | } |