Commit | Line | Data |
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54cf91dc CW |
1 | /* |
2 | * Copyright © 2008,2010 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | * Chris Wilson <chris@chris-wilson.co.uk> | |
26 | * | |
27 | */ | |
28 | ||
760285e7 DH |
29 | #include <drm/drmP.h> |
30 | #include <drm/i915_drm.h> | |
54cf91dc CW |
31 | #include "i915_drv.h" |
32 | #include "i915_trace.h" | |
33 | #include "intel_drv.h" | |
f45b5557 | 34 | #include <linux/dma_remapping.h> |
54cf91dc | 35 | |
67731b87 CW |
36 | struct eb_objects { |
37 | int and; | |
38 | struct hlist_head buckets[0]; | |
39 | }; | |
40 | ||
41 | static struct eb_objects * | |
42 | eb_create(int size) | |
43 | { | |
44 | struct eb_objects *eb; | |
45 | int count = PAGE_SIZE / sizeof(struct hlist_head) / 2; | |
41783eea | 46 | BUILD_BUG_ON(!is_power_of_2(PAGE_SIZE / sizeof(struct hlist_head))); |
67731b87 CW |
47 | while (count > size) |
48 | count >>= 1; | |
49 | eb = kzalloc(count*sizeof(struct hlist_head) + | |
50 | sizeof(struct eb_objects), | |
51 | GFP_KERNEL); | |
52 | if (eb == NULL) | |
53 | return eb; | |
54 | ||
55 | eb->and = count - 1; | |
56 | return eb; | |
57 | } | |
58 | ||
59 | static void | |
60 | eb_reset(struct eb_objects *eb) | |
61 | { | |
62 | memset(eb->buckets, 0, (eb->and+1)*sizeof(struct hlist_head)); | |
63 | } | |
64 | ||
65 | static void | |
66 | eb_add_object(struct eb_objects *eb, struct drm_i915_gem_object *obj) | |
67 | { | |
68 | hlist_add_head(&obj->exec_node, | |
69 | &eb->buckets[obj->exec_handle & eb->and]); | |
70 | } | |
71 | ||
72 | static struct drm_i915_gem_object * | |
73 | eb_get_object(struct eb_objects *eb, unsigned long handle) | |
74 | { | |
75 | struct hlist_head *head; | |
76 | struct hlist_node *node; | |
77 | struct drm_i915_gem_object *obj; | |
78 | ||
79 | head = &eb->buckets[handle & eb->and]; | |
80 | hlist_for_each(node, head) { | |
81 | obj = hlist_entry(node, struct drm_i915_gem_object, exec_node); | |
82 | if (obj->exec_handle == handle) | |
83 | return obj; | |
84 | } | |
85 | ||
86 | return NULL; | |
87 | } | |
88 | ||
89 | static void | |
90 | eb_destroy(struct eb_objects *eb) | |
91 | { | |
92 | kfree(eb); | |
93 | } | |
94 | ||
dabdfe02 CW |
95 | static inline int use_cpu_reloc(struct drm_i915_gem_object *obj) |
96 | { | |
97 | return (obj->base.write_domain == I915_GEM_DOMAIN_CPU || | |
504c7267 | 98 | !obj->map_and_fenceable || |
dabdfe02 CW |
99 | obj->cache_level != I915_CACHE_NONE); |
100 | } | |
101 | ||
54cf91dc CW |
102 | static int |
103 | i915_gem_execbuffer_relocate_entry(struct drm_i915_gem_object *obj, | |
67731b87 | 104 | struct eb_objects *eb, |
54cf91dc CW |
105 | struct drm_i915_gem_relocation_entry *reloc) |
106 | { | |
107 | struct drm_device *dev = obj->base.dev; | |
108 | struct drm_gem_object *target_obj; | |
149c8407 | 109 | struct drm_i915_gem_object *target_i915_obj; |
54cf91dc CW |
110 | uint32_t target_offset; |
111 | int ret = -EINVAL; | |
112 | ||
67731b87 CW |
113 | /* we've already hold a reference to all valid objects */ |
114 | target_obj = &eb_get_object(eb, reloc->target_handle)->base; | |
115 | if (unlikely(target_obj == NULL)) | |
54cf91dc CW |
116 | return -ENOENT; |
117 | ||
149c8407 DV |
118 | target_i915_obj = to_intel_bo(target_obj); |
119 | target_offset = target_i915_obj->gtt_offset; | |
54cf91dc | 120 | |
e844b990 EA |
121 | /* Sandybridge PPGTT errata: We need a global gtt mapping for MI and |
122 | * pipe_control writes because the gpu doesn't properly redirect them | |
123 | * through the ppgtt for non_secure batchbuffers. */ | |
124 | if (unlikely(IS_GEN6(dev) && | |
125 | reloc->write_domain == I915_GEM_DOMAIN_INSTRUCTION && | |
126 | !target_i915_obj->has_global_gtt_mapping)) { | |
127 | i915_gem_gtt_bind_object(target_i915_obj, | |
128 | target_i915_obj->cache_level); | |
129 | } | |
130 | ||
54cf91dc | 131 | /* Validate that the target is in a valid r/w GPU domain */ |
b8f7ab17 | 132 | if (unlikely(reloc->write_domain & (reloc->write_domain - 1))) { |
ff240199 | 133 | DRM_DEBUG("reloc with multiple write domains: " |
54cf91dc CW |
134 | "obj %p target %d offset %d " |
135 | "read %08x write %08x", | |
136 | obj, reloc->target_handle, | |
137 | (int) reloc->offset, | |
138 | reloc->read_domains, | |
139 | reloc->write_domain); | |
67731b87 | 140 | return ret; |
54cf91dc | 141 | } |
4ca4a250 DV |
142 | if (unlikely((reloc->write_domain | reloc->read_domains) |
143 | & ~I915_GEM_GPU_DOMAINS)) { | |
ff240199 | 144 | DRM_DEBUG("reloc with read/write non-GPU domains: " |
54cf91dc CW |
145 | "obj %p target %d offset %d " |
146 | "read %08x write %08x", | |
147 | obj, reloc->target_handle, | |
148 | (int) reloc->offset, | |
149 | reloc->read_domains, | |
150 | reloc->write_domain); | |
67731b87 | 151 | return ret; |
54cf91dc | 152 | } |
b8f7ab17 CW |
153 | if (unlikely(reloc->write_domain && target_obj->pending_write_domain && |
154 | reloc->write_domain != target_obj->pending_write_domain)) { | |
ff240199 | 155 | DRM_DEBUG("Write domain conflict: " |
54cf91dc CW |
156 | "obj %p target %d offset %d " |
157 | "new %08x old %08x\n", | |
158 | obj, reloc->target_handle, | |
159 | (int) reloc->offset, | |
160 | reloc->write_domain, | |
161 | target_obj->pending_write_domain); | |
67731b87 | 162 | return ret; |
54cf91dc CW |
163 | } |
164 | ||
165 | target_obj->pending_read_domains |= reloc->read_domains; | |
166 | target_obj->pending_write_domain |= reloc->write_domain; | |
167 | ||
168 | /* If the relocation already has the right value in it, no | |
169 | * more work needs to be done. | |
170 | */ | |
171 | if (target_offset == reloc->presumed_offset) | |
67731b87 | 172 | return 0; |
54cf91dc CW |
173 | |
174 | /* Check that the relocation address is valid... */ | |
b8f7ab17 | 175 | if (unlikely(reloc->offset > obj->base.size - 4)) { |
ff240199 | 176 | DRM_DEBUG("Relocation beyond object bounds: " |
54cf91dc CW |
177 | "obj %p target %d offset %d size %d.\n", |
178 | obj, reloc->target_handle, | |
179 | (int) reloc->offset, | |
180 | (int) obj->base.size); | |
67731b87 | 181 | return ret; |
54cf91dc | 182 | } |
b8f7ab17 | 183 | if (unlikely(reloc->offset & 3)) { |
ff240199 | 184 | DRM_DEBUG("Relocation not 4-byte aligned: " |
54cf91dc CW |
185 | "obj %p target %d offset %d.\n", |
186 | obj, reloc->target_handle, | |
187 | (int) reloc->offset); | |
67731b87 | 188 | return ret; |
54cf91dc CW |
189 | } |
190 | ||
dabdfe02 CW |
191 | /* We can't wait for rendering with pagefaults disabled */ |
192 | if (obj->active && in_atomic()) | |
193 | return -EFAULT; | |
194 | ||
54cf91dc | 195 | reloc->delta += target_offset; |
dabdfe02 | 196 | if (use_cpu_reloc(obj)) { |
54cf91dc CW |
197 | uint32_t page_offset = reloc->offset & ~PAGE_MASK; |
198 | char *vaddr; | |
199 | ||
dabdfe02 CW |
200 | ret = i915_gem_object_set_to_cpu_domain(obj, 1); |
201 | if (ret) | |
202 | return ret; | |
203 | ||
9da3da66 CW |
204 | vaddr = kmap_atomic(i915_gem_object_get_page(obj, |
205 | reloc->offset >> PAGE_SHIFT)); | |
54cf91dc CW |
206 | *(uint32_t *)(vaddr + page_offset) = reloc->delta; |
207 | kunmap_atomic(vaddr); | |
208 | } else { | |
209 | struct drm_i915_private *dev_priv = dev->dev_private; | |
210 | uint32_t __iomem *reloc_entry; | |
211 | void __iomem *reloc_page; | |
212 | ||
7b09638f CW |
213 | ret = i915_gem_object_set_to_gtt_domain(obj, true); |
214 | if (ret) | |
215 | return ret; | |
216 | ||
217 | ret = i915_gem_object_put_fence(obj); | |
54cf91dc | 218 | if (ret) |
67731b87 | 219 | return ret; |
54cf91dc CW |
220 | |
221 | /* Map the page containing the relocation we're going to perform. */ | |
222 | reloc->offset += obj->gtt_offset; | |
223 | reloc_page = io_mapping_map_atomic_wc(dev_priv->mm.gtt_mapping, | |
224 | reloc->offset & PAGE_MASK); | |
225 | reloc_entry = (uint32_t __iomem *) | |
226 | (reloc_page + (reloc->offset & ~PAGE_MASK)); | |
227 | iowrite32(reloc->delta, reloc_entry); | |
228 | io_mapping_unmap_atomic(reloc_page); | |
229 | } | |
230 | ||
231 | /* and update the user's relocation entry */ | |
232 | reloc->presumed_offset = target_offset; | |
233 | ||
67731b87 | 234 | return 0; |
54cf91dc CW |
235 | } |
236 | ||
237 | static int | |
238 | i915_gem_execbuffer_relocate_object(struct drm_i915_gem_object *obj, | |
6fe4f140 | 239 | struct eb_objects *eb) |
54cf91dc | 240 | { |
1d83f442 CW |
241 | #define N_RELOC(x) ((x) / sizeof(struct drm_i915_gem_relocation_entry)) |
242 | struct drm_i915_gem_relocation_entry stack_reloc[N_RELOC(512)]; | |
54cf91dc | 243 | struct drm_i915_gem_relocation_entry __user *user_relocs; |
6fe4f140 | 244 | struct drm_i915_gem_exec_object2 *entry = obj->exec_entry; |
1d83f442 | 245 | int remain, ret; |
54cf91dc CW |
246 | |
247 | user_relocs = (void __user *)(uintptr_t)entry->relocs_ptr; | |
54cf91dc | 248 | |
1d83f442 CW |
249 | remain = entry->relocation_count; |
250 | while (remain) { | |
251 | struct drm_i915_gem_relocation_entry *r = stack_reloc; | |
252 | int count = remain; | |
253 | if (count > ARRAY_SIZE(stack_reloc)) | |
254 | count = ARRAY_SIZE(stack_reloc); | |
255 | remain -= count; | |
256 | ||
257 | if (__copy_from_user_inatomic(r, user_relocs, count*sizeof(r[0]))) | |
54cf91dc CW |
258 | return -EFAULT; |
259 | ||
1d83f442 CW |
260 | do { |
261 | u64 offset = r->presumed_offset; | |
54cf91dc | 262 | |
1d83f442 CW |
263 | ret = i915_gem_execbuffer_relocate_entry(obj, eb, r); |
264 | if (ret) | |
265 | return ret; | |
266 | ||
267 | if (r->presumed_offset != offset && | |
268 | __copy_to_user_inatomic(&user_relocs->presumed_offset, | |
269 | &r->presumed_offset, | |
270 | sizeof(r->presumed_offset))) { | |
271 | return -EFAULT; | |
272 | } | |
273 | ||
274 | user_relocs++; | |
275 | r++; | |
276 | } while (--count); | |
54cf91dc CW |
277 | } |
278 | ||
279 | return 0; | |
1d83f442 | 280 | #undef N_RELOC |
54cf91dc CW |
281 | } |
282 | ||
283 | static int | |
284 | i915_gem_execbuffer_relocate_object_slow(struct drm_i915_gem_object *obj, | |
67731b87 | 285 | struct eb_objects *eb, |
54cf91dc CW |
286 | struct drm_i915_gem_relocation_entry *relocs) |
287 | { | |
6fe4f140 | 288 | const struct drm_i915_gem_exec_object2 *entry = obj->exec_entry; |
54cf91dc CW |
289 | int i, ret; |
290 | ||
291 | for (i = 0; i < entry->relocation_count; i++) { | |
6fe4f140 | 292 | ret = i915_gem_execbuffer_relocate_entry(obj, eb, &relocs[i]); |
54cf91dc CW |
293 | if (ret) |
294 | return ret; | |
295 | } | |
296 | ||
297 | return 0; | |
298 | } | |
299 | ||
300 | static int | |
301 | i915_gem_execbuffer_relocate(struct drm_device *dev, | |
67731b87 | 302 | struct eb_objects *eb, |
6fe4f140 | 303 | struct list_head *objects) |
54cf91dc | 304 | { |
432e58ed | 305 | struct drm_i915_gem_object *obj; |
d4aeee77 CW |
306 | int ret = 0; |
307 | ||
308 | /* This is the fast path and we cannot handle a pagefault whilst | |
309 | * holding the struct mutex lest the user pass in the relocations | |
310 | * contained within a mmaped bo. For in such a case we, the page | |
311 | * fault handler would call i915_gem_fault() and we would try to | |
312 | * acquire the struct mutex again. Obviously this is bad and so | |
313 | * lockdep complains vehemently. | |
314 | */ | |
315 | pagefault_disable(); | |
432e58ed | 316 | list_for_each_entry(obj, objects, exec_list) { |
6fe4f140 | 317 | ret = i915_gem_execbuffer_relocate_object(obj, eb); |
54cf91dc | 318 | if (ret) |
d4aeee77 | 319 | break; |
54cf91dc | 320 | } |
d4aeee77 | 321 | pagefault_enable(); |
54cf91dc | 322 | |
d4aeee77 | 323 | return ret; |
54cf91dc CW |
324 | } |
325 | ||
7788a765 CW |
326 | #define __EXEC_OBJECT_HAS_PIN (1<<31) |
327 | #define __EXEC_OBJECT_HAS_FENCE (1<<30) | |
1690e1eb | 328 | |
dabdfe02 CW |
329 | static int |
330 | need_reloc_mappable(struct drm_i915_gem_object *obj) | |
331 | { | |
332 | struct drm_i915_gem_exec_object2 *entry = obj->exec_entry; | |
333 | return entry->relocation_count && !use_cpu_reloc(obj); | |
334 | } | |
335 | ||
1690e1eb | 336 | static int |
7788a765 CW |
337 | i915_gem_execbuffer_reserve_object(struct drm_i915_gem_object *obj, |
338 | struct intel_ring_buffer *ring) | |
1690e1eb | 339 | { |
7788a765 | 340 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
1690e1eb CW |
341 | struct drm_i915_gem_exec_object2 *entry = obj->exec_entry; |
342 | bool has_fenced_gpu_access = INTEL_INFO(ring->dev)->gen < 4; | |
343 | bool need_fence, need_mappable; | |
344 | int ret; | |
345 | ||
346 | need_fence = | |
347 | has_fenced_gpu_access && | |
348 | entry->flags & EXEC_OBJECT_NEEDS_FENCE && | |
349 | obj->tiling_mode != I915_TILING_NONE; | |
dabdfe02 | 350 | need_mappable = need_fence || need_reloc_mappable(obj); |
1690e1eb | 351 | |
86a1ee26 | 352 | ret = i915_gem_object_pin(obj, entry->alignment, need_mappable, false); |
1690e1eb CW |
353 | if (ret) |
354 | return ret; | |
355 | ||
7788a765 CW |
356 | entry->flags |= __EXEC_OBJECT_HAS_PIN; |
357 | ||
1690e1eb CW |
358 | if (has_fenced_gpu_access) { |
359 | if (entry->flags & EXEC_OBJECT_NEEDS_FENCE) { | |
06d98131 | 360 | ret = i915_gem_object_get_fence(obj); |
9a5a53b3 | 361 | if (ret) |
7788a765 | 362 | return ret; |
1690e1eb | 363 | |
9a5a53b3 | 364 | if (i915_gem_object_pin_fence(obj)) |
1690e1eb | 365 | entry->flags |= __EXEC_OBJECT_HAS_FENCE; |
9a5a53b3 | 366 | |
7dd49065 | 367 | obj->pending_fenced_gpu_access = true; |
1690e1eb | 368 | } |
1690e1eb CW |
369 | } |
370 | ||
7788a765 CW |
371 | /* Ensure ppgtt mapping exists if needed */ |
372 | if (dev_priv->mm.aliasing_ppgtt && !obj->has_aliasing_ppgtt_mapping) { | |
373 | i915_ppgtt_bind_object(dev_priv->mm.aliasing_ppgtt, | |
374 | obj, obj->cache_level); | |
375 | ||
376 | obj->has_aliasing_ppgtt_mapping = 1; | |
377 | } | |
378 | ||
1690e1eb CW |
379 | entry->offset = obj->gtt_offset; |
380 | return 0; | |
7788a765 | 381 | } |
1690e1eb | 382 | |
7788a765 CW |
383 | static void |
384 | i915_gem_execbuffer_unreserve_object(struct drm_i915_gem_object *obj) | |
385 | { | |
386 | struct drm_i915_gem_exec_object2 *entry; | |
387 | ||
388 | if (!obj->gtt_space) | |
389 | return; | |
390 | ||
391 | entry = obj->exec_entry; | |
392 | ||
393 | if (entry->flags & __EXEC_OBJECT_HAS_FENCE) | |
394 | i915_gem_object_unpin_fence(obj); | |
395 | ||
396 | if (entry->flags & __EXEC_OBJECT_HAS_PIN) | |
397 | i915_gem_object_unpin(obj); | |
398 | ||
399 | entry->flags &= ~(__EXEC_OBJECT_HAS_FENCE | __EXEC_OBJECT_HAS_PIN); | |
1690e1eb CW |
400 | } |
401 | ||
54cf91dc | 402 | static int |
d9e86c0e | 403 | i915_gem_execbuffer_reserve(struct intel_ring_buffer *ring, |
54cf91dc | 404 | struct drm_file *file, |
6fe4f140 | 405 | struct list_head *objects) |
54cf91dc | 406 | { |
432e58ed | 407 | struct drm_i915_gem_object *obj; |
6fe4f140 | 408 | struct list_head ordered_objects; |
7788a765 CW |
409 | bool has_fenced_gpu_access = INTEL_INFO(ring->dev)->gen < 4; |
410 | int retry; | |
6fe4f140 CW |
411 | |
412 | INIT_LIST_HEAD(&ordered_objects); | |
413 | while (!list_empty(objects)) { | |
414 | struct drm_i915_gem_exec_object2 *entry; | |
415 | bool need_fence, need_mappable; | |
416 | ||
417 | obj = list_first_entry(objects, | |
418 | struct drm_i915_gem_object, | |
419 | exec_list); | |
420 | entry = obj->exec_entry; | |
421 | ||
422 | need_fence = | |
423 | has_fenced_gpu_access && | |
424 | entry->flags & EXEC_OBJECT_NEEDS_FENCE && | |
425 | obj->tiling_mode != I915_TILING_NONE; | |
dabdfe02 | 426 | need_mappable = need_fence || need_reloc_mappable(obj); |
6fe4f140 CW |
427 | |
428 | if (need_mappable) | |
429 | list_move(&obj->exec_list, &ordered_objects); | |
430 | else | |
431 | list_move_tail(&obj->exec_list, &ordered_objects); | |
595dad76 CW |
432 | |
433 | obj->base.pending_read_domains = 0; | |
434 | obj->base.pending_write_domain = 0; | |
016fd0c1 | 435 | obj->pending_fenced_gpu_access = false; |
6fe4f140 CW |
436 | } |
437 | list_splice(&ordered_objects, objects); | |
54cf91dc CW |
438 | |
439 | /* Attempt to pin all of the buffers into the GTT. | |
440 | * This is done in 3 phases: | |
441 | * | |
442 | * 1a. Unbind all objects that do not match the GTT constraints for | |
443 | * the execbuffer (fenceable, mappable, alignment etc). | |
444 | * 1b. Increment pin count for already bound objects. | |
445 | * 2. Bind new objects. | |
446 | * 3. Decrement pin count. | |
447 | * | |
7788a765 | 448 | * This avoid unnecessary unbinding of later objects in order to make |
54cf91dc CW |
449 | * room for the earlier objects *unless* we need to defragment. |
450 | */ | |
451 | retry = 0; | |
452 | do { | |
7788a765 | 453 | int ret = 0; |
54cf91dc CW |
454 | |
455 | /* Unbind any ill-fitting objects or pin. */ | |
432e58ed | 456 | list_for_each_entry(obj, objects, exec_list) { |
6fe4f140 | 457 | struct drm_i915_gem_exec_object2 *entry = obj->exec_entry; |
54cf91dc | 458 | bool need_fence, need_mappable; |
1690e1eb | 459 | |
6fe4f140 | 460 | if (!obj->gtt_space) |
54cf91dc CW |
461 | continue; |
462 | ||
463 | need_fence = | |
9b3826bf | 464 | has_fenced_gpu_access && |
54cf91dc CW |
465 | entry->flags & EXEC_OBJECT_NEEDS_FENCE && |
466 | obj->tiling_mode != I915_TILING_NONE; | |
dabdfe02 | 467 | need_mappable = need_fence || need_reloc_mappable(obj); |
54cf91dc CW |
468 | |
469 | if ((entry->alignment && obj->gtt_offset & (entry->alignment - 1)) || | |
470 | (need_mappable && !obj->map_and_fenceable)) | |
471 | ret = i915_gem_object_unbind(obj); | |
472 | else | |
7788a765 | 473 | ret = i915_gem_execbuffer_reserve_object(obj, ring); |
432e58ed | 474 | if (ret) |
54cf91dc | 475 | goto err; |
54cf91dc CW |
476 | } |
477 | ||
478 | /* Bind fresh objects */ | |
432e58ed | 479 | list_for_each_entry(obj, objects, exec_list) { |
1690e1eb CW |
480 | if (obj->gtt_space) |
481 | continue; | |
54cf91dc | 482 | |
7788a765 CW |
483 | ret = i915_gem_execbuffer_reserve_object(obj, ring); |
484 | if (ret) | |
485 | goto err; | |
54cf91dc CW |
486 | } |
487 | ||
7788a765 CW |
488 | err: /* Decrement pin count for bound objects */ |
489 | list_for_each_entry(obj, objects, exec_list) | |
490 | i915_gem_execbuffer_unreserve_object(obj); | |
54cf91dc | 491 | |
6c085a72 | 492 | if (ret != -ENOSPC || retry++) |
54cf91dc CW |
493 | return ret; |
494 | ||
6c085a72 | 495 | ret = i915_gem_evict_everything(ring->dev); |
54cf91dc CW |
496 | if (ret) |
497 | return ret; | |
54cf91dc CW |
498 | } while (1); |
499 | } | |
500 | ||
501 | static int | |
502 | i915_gem_execbuffer_relocate_slow(struct drm_device *dev, | |
503 | struct drm_file *file, | |
d9e86c0e | 504 | struct intel_ring_buffer *ring, |
432e58ed | 505 | struct list_head *objects, |
67731b87 | 506 | struct eb_objects *eb, |
432e58ed | 507 | struct drm_i915_gem_exec_object2 *exec, |
54cf91dc CW |
508 | int count) |
509 | { | |
510 | struct drm_i915_gem_relocation_entry *reloc; | |
432e58ed | 511 | struct drm_i915_gem_object *obj; |
dd6864a4 | 512 | int *reloc_offset; |
54cf91dc CW |
513 | int i, total, ret; |
514 | ||
67731b87 | 515 | /* We may process another execbuffer during the unlock... */ |
36cf1742 | 516 | while (!list_empty(objects)) { |
67731b87 CW |
517 | obj = list_first_entry(objects, |
518 | struct drm_i915_gem_object, | |
519 | exec_list); | |
520 | list_del_init(&obj->exec_list); | |
521 | drm_gem_object_unreference(&obj->base); | |
522 | } | |
523 | ||
54cf91dc CW |
524 | mutex_unlock(&dev->struct_mutex); |
525 | ||
526 | total = 0; | |
527 | for (i = 0; i < count; i++) | |
432e58ed | 528 | total += exec[i].relocation_count; |
54cf91dc | 529 | |
dd6864a4 | 530 | reloc_offset = drm_malloc_ab(count, sizeof(*reloc_offset)); |
54cf91dc | 531 | reloc = drm_malloc_ab(total, sizeof(*reloc)); |
dd6864a4 CW |
532 | if (reloc == NULL || reloc_offset == NULL) { |
533 | drm_free_large(reloc); | |
534 | drm_free_large(reloc_offset); | |
54cf91dc CW |
535 | mutex_lock(&dev->struct_mutex); |
536 | return -ENOMEM; | |
537 | } | |
538 | ||
539 | total = 0; | |
540 | for (i = 0; i < count; i++) { | |
541 | struct drm_i915_gem_relocation_entry __user *user_relocs; | |
542 | ||
432e58ed | 543 | user_relocs = (void __user *)(uintptr_t)exec[i].relocs_ptr; |
54cf91dc CW |
544 | |
545 | if (copy_from_user(reloc+total, user_relocs, | |
432e58ed | 546 | exec[i].relocation_count * sizeof(*reloc))) { |
54cf91dc CW |
547 | ret = -EFAULT; |
548 | mutex_lock(&dev->struct_mutex); | |
549 | goto err; | |
550 | } | |
551 | ||
dd6864a4 | 552 | reloc_offset[i] = total; |
432e58ed | 553 | total += exec[i].relocation_count; |
54cf91dc CW |
554 | } |
555 | ||
556 | ret = i915_mutex_lock_interruptible(dev); | |
557 | if (ret) { | |
558 | mutex_lock(&dev->struct_mutex); | |
559 | goto err; | |
560 | } | |
561 | ||
67731b87 | 562 | /* reacquire the objects */ |
67731b87 CW |
563 | eb_reset(eb); |
564 | for (i = 0; i < count; i++) { | |
67731b87 CW |
565 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, |
566 | exec[i].handle)); | |
c8725226 | 567 | if (&obj->base == NULL) { |
ff240199 | 568 | DRM_DEBUG("Invalid object handle %d at index %d\n", |
67731b87 CW |
569 | exec[i].handle, i); |
570 | ret = -ENOENT; | |
571 | goto err; | |
572 | } | |
573 | ||
574 | list_add_tail(&obj->exec_list, objects); | |
575 | obj->exec_handle = exec[i].handle; | |
6fe4f140 | 576 | obj->exec_entry = &exec[i]; |
67731b87 CW |
577 | eb_add_object(eb, obj); |
578 | } | |
579 | ||
6fe4f140 | 580 | ret = i915_gem_execbuffer_reserve(ring, file, objects); |
54cf91dc CW |
581 | if (ret) |
582 | goto err; | |
583 | ||
432e58ed | 584 | list_for_each_entry(obj, objects, exec_list) { |
dd6864a4 | 585 | int offset = obj->exec_entry - exec; |
67731b87 | 586 | ret = i915_gem_execbuffer_relocate_object_slow(obj, eb, |
dd6864a4 | 587 | reloc + reloc_offset[offset]); |
54cf91dc CW |
588 | if (ret) |
589 | goto err; | |
54cf91dc CW |
590 | } |
591 | ||
592 | /* Leave the user relocations as are, this is the painfully slow path, | |
593 | * and we want to avoid the complication of dropping the lock whilst | |
594 | * having buffers reserved in the aperture and so causing spurious | |
595 | * ENOSPC for random operations. | |
596 | */ | |
597 | ||
598 | err: | |
599 | drm_free_large(reloc); | |
dd6864a4 | 600 | drm_free_large(reloc_offset); |
54cf91dc CW |
601 | return ret; |
602 | } | |
603 | ||
c59a333f CW |
604 | static int |
605 | i915_gem_execbuffer_wait_for_flips(struct intel_ring_buffer *ring, u32 flips) | |
606 | { | |
607 | u32 plane, flip_mask; | |
608 | int ret; | |
609 | ||
610 | /* Check for any pending flips. As we only maintain a flip queue depth | |
611 | * of 1, we can simply insert a WAIT for the next display flip prior | |
612 | * to executing the batch and avoid stalling the CPU. | |
613 | */ | |
614 | ||
615 | for (plane = 0; flips >> plane; plane++) { | |
616 | if (((flips >> plane) & 1) == 0) | |
617 | continue; | |
618 | ||
619 | if (plane) | |
620 | flip_mask = MI_WAIT_FOR_PLANE_B_FLIP; | |
621 | else | |
622 | flip_mask = MI_WAIT_FOR_PLANE_A_FLIP; | |
623 | ||
624 | ret = intel_ring_begin(ring, 2); | |
625 | if (ret) | |
626 | return ret; | |
627 | ||
628 | intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask); | |
629 | intel_ring_emit(ring, MI_NOOP); | |
630 | intel_ring_advance(ring); | |
631 | } | |
632 | ||
633 | return 0; | |
634 | } | |
635 | ||
54cf91dc | 636 | static int |
432e58ed CW |
637 | i915_gem_execbuffer_move_to_gpu(struct intel_ring_buffer *ring, |
638 | struct list_head *objects) | |
54cf91dc | 639 | { |
432e58ed | 640 | struct drm_i915_gem_object *obj; |
6ac42f41 DV |
641 | uint32_t flush_domains = 0; |
642 | uint32_t flips = 0; | |
432e58ed | 643 | int ret; |
54cf91dc | 644 | |
6ac42f41 DV |
645 | list_for_each_entry(obj, objects, exec_list) { |
646 | ret = i915_gem_object_sync(obj, ring); | |
c59a333f CW |
647 | if (ret) |
648 | return ret; | |
6ac42f41 DV |
649 | |
650 | if (obj->base.write_domain & I915_GEM_DOMAIN_CPU) | |
651 | i915_gem_clflush_object(obj); | |
652 | ||
653 | if (obj->base.pending_write_domain) | |
654 | flips |= atomic_read(&obj->pending_flip); | |
655 | ||
656 | flush_domains |= obj->base.write_domain; | |
c59a333f CW |
657 | } |
658 | ||
6ac42f41 DV |
659 | if (flips) { |
660 | ret = i915_gem_execbuffer_wait_for_flips(ring, flips); | |
1ec14ad3 CW |
661 | if (ret) |
662 | return ret; | |
54cf91dc CW |
663 | } |
664 | ||
6ac42f41 | 665 | if (flush_domains & I915_GEM_DOMAIN_CPU) |
e76e9aeb | 666 | i915_gem_chipset_flush(ring->dev); |
6ac42f41 DV |
667 | |
668 | if (flush_domains & I915_GEM_DOMAIN_GTT) | |
669 | wmb(); | |
670 | ||
09cf7c9a CW |
671 | /* Unconditionally invalidate gpu caches and ensure that we do flush |
672 | * any residual writes from the previous batch. | |
673 | */ | |
a7b9761d | 674 | return intel_ring_invalidate_all_caches(ring); |
54cf91dc CW |
675 | } |
676 | ||
432e58ed CW |
677 | static bool |
678 | i915_gem_check_execbuffer(struct drm_i915_gem_execbuffer2 *exec) | |
54cf91dc | 679 | { |
432e58ed | 680 | return ((exec->batch_start_offset | exec->batch_len) & 0x7) == 0; |
54cf91dc CW |
681 | } |
682 | ||
683 | static int | |
684 | validate_exec_list(struct drm_i915_gem_exec_object2 *exec, | |
685 | int count) | |
686 | { | |
687 | int i; | |
688 | ||
689 | for (i = 0; i < count; i++) { | |
690 | char __user *ptr = (char __user *)(uintptr_t)exec[i].relocs_ptr; | |
691 | int length; /* limited by fault_in_pages_readable() */ | |
692 | ||
693 | /* First check for malicious input causing overflow */ | |
694 | if (exec[i].relocation_count > | |
695 | INT_MAX / sizeof(struct drm_i915_gem_relocation_entry)) | |
696 | return -EINVAL; | |
697 | ||
698 | length = exec[i].relocation_count * | |
699 | sizeof(struct drm_i915_gem_relocation_entry); | |
700 | if (!access_ok(VERIFY_READ, ptr, length)) | |
701 | return -EFAULT; | |
702 | ||
703 | /* we may also need to update the presumed offsets */ | |
704 | if (!access_ok(VERIFY_WRITE, ptr, length)) | |
705 | return -EFAULT; | |
706 | ||
f56f821f | 707 | if (fault_in_multipages_readable(ptr, length)) |
54cf91dc CW |
708 | return -EFAULT; |
709 | } | |
710 | ||
711 | return 0; | |
712 | } | |
713 | ||
432e58ed CW |
714 | static void |
715 | i915_gem_execbuffer_move_to_active(struct list_head *objects, | |
1ec14ad3 CW |
716 | struct intel_ring_buffer *ring, |
717 | u32 seqno) | |
432e58ed CW |
718 | { |
719 | struct drm_i915_gem_object *obj; | |
720 | ||
721 | list_for_each_entry(obj, objects, exec_list) { | |
69c2fc89 CW |
722 | u32 old_read = obj->base.read_domains; |
723 | u32 old_write = obj->base.write_domain; | |
db53a302 | 724 | |
432e58ed CW |
725 | obj->base.read_domains = obj->base.pending_read_domains; |
726 | obj->base.write_domain = obj->base.pending_write_domain; | |
727 | obj->fenced_gpu_access = obj->pending_fenced_gpu_access; | |
728 | ||
1ec14ad3 | 729 | i915_gem_object_move_to_active(obj, ring, seqno); |
432e58ed CW |
730 | if (obj->base.write_domain) { |
731 | obj->dirty = 1; | |
0201f1ec | 732 | obj->last_write_seqno = seqno; |
acb87dfb | 733 | if (obj->pin_count) /* check for potential scanout */ |
f047e395 | 734 | intel_mark_fb_busy(obj); |
432e58ed CW |
735 | } |
736 | ||
db53a302 | 737 | trace_i915_gem_object_change_domain(obj, old_read, old_write); |
432e58ed CW |
738 | } |
739 | } | |
740 | ||
54cf91dc CW |
741 | static void |
742 | i915_gem_execbuffer_retire_commands(struct drm_device *dev, | |
432e58ed | 743 | struct drm_file *file, |
54cf91dc CW |
744 | struct intel_ring_buffer *ring) |
745 | { | |
cc889e0f DV |
746 | /* Unconditionally force add_request to emit a full flush. */ |
747 | ring->gpu_caches_dirty = true; | |
54cf91dc | 748 | |
432e58ed | 749 | /* Add a breadcrumb for the completion of the batch buffer */ |
3bb73aba | 750 | (void)i915_add_request(ring, file, NULL); |
432e58ed | 751 | } |
54cf91dc | 752 | |
ae662d31 EA |
753 | static int |
754 | i915_reset_gen7_sol_offsets(struct drm_device *dev, | |
755 | struct intel_ring_buffer *ring) | |
756 | { | |
757 | drm_i915_private_t *dev_priv = dev->dev_private; | |
758 | int ret, i; | |
759 | ||
760 | if (!IS_GEN7(dev) || ring != &dev_priv->ring[RCS]) | |
761 | return 0; | |
762 | ||
763 | ret = intel_ring_begin(ring, 4 * 3); | |
764 | if (ret) | |
765 | return ret; | |
766 | ||
767 | for (i = 0; i < 4; i++) { | |
768 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); | |
769 | intel_ring_emit(ring, GEN7_SO_WRITE_OFFSET(i)); | |
770 | intel_ring_emit(ring, 0); | |
771 | } | |
772 | ||
773 | intel_ring_advance(ring); | |
774 | ||
775 | return 0; | |
776 | } | |
777 | ||
54cf91dc CW |
778 | static int |
779 | i915_gem_do_execbuffer(struct drm_device *dev, void *data, | |
780 | struct drm_file *file, | |
781 | struct drm_i915_gem_execbuffer2 *args, | |
432e58ed | 782 | struct drm_i915_gem_exec_object2 *exec) |
54cf91dc CW |
783 | { |
784 | drm_i915_private_t *dev_priv = dev->dev_private; | |
432e58ed | 785 | struct list_head objects; |
67731b87 | 786 | struct eb_objects *eb; |
54cf91dc CW |
787 | struct drm_i915_gem_object *batch_obj; |
788 | struct drm_clip_rect *cliprects = NULL; | |
54cf91dc | 789 | struct intel_ring_buffer *ring; |
6e0a69db | 790 | u32 ctx_id = i915_execbuffer2_get_context_id(*args); |
c4e7a414 | 791 | u32 exec_start, exec_len; |
1ec14ad3 | 792 | u32 seqno; |
84f9f938 | 793 | u32 mask; |
d7d4eedd | 794 | u32 flags; |
72bfa19c | 795 | int ret, mode, i; |
54cf91dc | 796 | |
432e58ed | 797 | if (!i915_gem_check_execbuffer(args)) { |
ff240199 | 798 | DRM_DEBUG("execbuf with invalid offset/length\n"); |
432e58ed CW |
799 | return -EINVAL; |
800 | } | |
801 | ||
802 | ret = validate_exec_list(exec, args->buffer_count); | |
54cf91dc CW |
803 | if (ret) |
804 | return ret; | |
805 | ||
d7d4eedd CW |
806 | flags = 0; |
807 | if (args->flags & I915_EXEC_SECURE) { | |
808 | if (!file->is_master || !capable(CAP_SYS_ADMIN)) | |
809 | return -EPERM; | |
810 | ||
811 | flags |= I915_DISPATCH_SECURE; | |
812 | } | |
813 | ||
54cf91dc CW |
814 | switch (args->flags & I915_EXEC_RING_MASK) { |
815 | case I915_EXEC_DEFAULT: | |
816 | case I915_EXEC_RENDER: | |
1ec14ad3 | 817 | ring = &dev_priv->ring[RCS]; |
54cf91dc CW |
818 | break; |
819 | case I915_EXEC_BSD: | |
1ec14ad3 | 820 | ring = &dev_priv->ring[VCS]; |
6e0a69db BW |
821 | if (ctx_id != 0) { |
822 | DRM_DEBUG("Ring %s doesn't support contexts\n", | |
823 | ring->name); | |
824 | return -EPERM; | |
825 | } | |
54cf91dc CW |
826 | break; |
827 | case I915_EXEC_BLT: | |
1ec14ad3 | 828 | ring = &dev_priv->ring[BCS]; |
6e0a69db BW |
829 | if (ctx_id != 0) { |
830 | DRM_DEBUG("Ring %s doesn't support contexts\n", | |
831 | ring->name); | |
832 | return -EPERM; | |
833 | } | |
54cf91dc CW |
834 | break; |
835 | default: | |
ff240199 | 836 | DRM_DEBUG("execbuf with unknown ring: %d\n", |
54cf91dc CW |
837 | (int)(args->flags & I915_EXEC_RING_MASK)); |
838 | return -EINVAL; | |
839 | } | |
a15817cf CW |
840 | if (!intel_ring_initialized(ring)) { |
841 | DRM_DEBUG("execbuf with invalid ring: %d\n", | |
842 | (int)(args->flags & I915_EXEC_RING_MASK)); | |
843 | return -EINVAL; | |
844 | } | |
54cf91dc | 845 | |
72bfa19c | 846 | mode = args->flags & I915_EXEC_CONSTANTS_MASK; |
84f9f938 | 847 | mask = I915_EXEC_CONSTANTS_MASK; |
72bfa19c CW |
848 | switch (mode) { |
849 | case I915_EXEC_CONSTANTS_REL_GENERAL: | |
850 | case I915_EXEC_CONSTANTS_ABSOLUTE: | |
851 | case I915_EXEC_CONSTANTS_REL_SURFACE: | |
852 | if (ring == &dev_priv->ring[RCS] && | |
853 | mode != dev_priv->relative_constants_mode) { | |
854 | if (INTEL_INFO(dev)->gen < 4) | |
855 | return -EINVAL; | |
856 | ||
857 | if (INTEL_INFO(dev)->gen > 5 && | |
858 | mode == I915_EXEC_CONSTANTS_REL_SURFACE) | |
859 | return -EINVAL; | |
84f9f938 BW |
860 | |
861 | /* The HW changed the meaning on this bit on gen6 */ | |
862 | if (INTEL_INFO(dev)->gen >= 6) | |
863 | mask &= ~I915_EXEC_CONSTANTS_REL_SURFACE; | |
72bfa19c CW |
864 | } |
865 | break; | |
866 | default: | |
ff240199 | 867 | DRM_DEBUG("execbuf with unknown constants: %d\n", mode); |
72bfa19c CW |
868 | return -EINVAL; |
869 | } | |
870 | ||
54cf91dc | 871 | if (args->buffer_count < 1) { |
ff240199 | 872 | DRM_DEBUG("execbuf with %d buffers\n", args->buffer_count); |
54cf91dc CW |
873 | return -EINVAL; |
874 | } | |
54cf91dc CW |
875 | |
876 | if (args->num_cliprects != 0) { | |
1ec14ad3 | 877 | if (ring != &dev_priv->ring[RCS]) { |
ff240199 | 878 | DRM_DEBUG("clip rectangles are only valid with the render ring\n"); |
c4e7a414 CW |
879 | return -EINVAL; |
880 | } | |
881 | ||
6ebebc92 DV |
882 | if (INTEL_INFO(dev)->gen >= 5) { |
883 | DRM_DEBUG("clip rectangles are only valid on pre-gen5\n"); | |
884 | return -EINVAL; | |
885 | } | |
886 | ||
44afb3a0 XW |
887 | if (args->num_cliprects > UINT_MAX / sizeof(*cliprects)) { |
888 | DRM_DEBUG("execbuf with %u cliprects\n", | |
889 | args->num_cliprects); | |
890 | return -EINVAL; | |
891 | } | |
5e13a0c5 | 892 | |
432e58ed | 893 | cliprects = kmalloc(args->num_cliprects * sizeof(*cliprects), |
54cf91dc CW |
894 | GFP_KERNEL); |
895 | if (cliprects == NULL) { | |
896 | ret = -ENOMEM; | |
897 | goto pre_mutex_err; | |
898 | } | |
899 | ||
432e58ed CW |
900 | if (copy_from_user(cliprects, |
901 | (struct drm_clip_rect __user *)(uintptr_t) | |
902 | args->cliprects_ptr, | |
903 | sizeof(*cliprects)*args->num_cliprects)) { | |
54cf91dc CW |
904 | ret = -EFAULT; |
905 | goto pre_mutex_err; | |
906 | } | |
907 | } | |
908 | ||
54cf91dc CW |
909 | ret = i915_mutex_lock_interruptible(dev); |
910 | if (ret) | |
911 | goto pre_mutex_err; | |
912 | ||
913 | if (dev_priv->mm.suspended) { | |
914 | mutex_unlock(&dev->struct_mutex); | |
915 | ret = -EBUSY; | |
916 | goto pre_mutex_err; | |
917 | } | |
918 | ||
67731b87 CW |
919 | eb = eb_create(args->buffer_count); |
920 | if (eb == NULL) { | |
921 | mutex_unlock(&dev->struct_mutex); | |
922 | ret = -ENOMEM; | |
923 | goto pre_mutex_err; | |
924 | } | |
925 | ||
54cf91dc | 926 | /* Look up object handles */ |
432e58ed | 927 | INIT_LIST_HEAD(&objects); |
54cf91dc CW |
928 | for (i = 0; i < args->buffer_count; i++) { |
929 | struct drm_i915_gem_object *obj; | |
930 | ||
432e58ed CW |
931 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, |
932 | exec[i].handle)); | |
c8725226 | 933 | if (&obj->base == NULL) { |
ff240199 | 934 | DRM_DEBUG("Invalid object handle %d at index %d\n", |
432e58ed | 935 | exec[i].handle, i); |
54cf91dc | 936 | /* prevent error path from reading uninitialized data */ |
54cf91dc CW |
937 | ret = -ENOENT; |
938 | goto err; | |
939 | } | |
54cf91dc | 940 | |
432e58ed | 941 | if (!list_empty(&obj->exec_list)) { |
ff240199 | 942 | DRM_DEBUG("Object %p [handle %d, index %d] appears more than once in object list\n", |
432e58ed | 943 | obj, exec[i].handle, i); |
54cf91dc CW |
944 | ret = -EINVAL; |
945 | goto err; | |
946 | } | |
432e58ed CW |
947 | |
948 | list_add_tail(&obj->exec_list, &objects); | |
67731b87 | 949 | obj->exec_handle = exec[i].handle; |
6fe4f140 | 950 | obj->exec_entry = &exec[i]; |
67731b87 | 951 | eb_add_object(eb, obj); |
54cf91dc CW |
952 | } |
953 | ||
6fe4f140 CW |
954 | /* take note of the batch buffer before we might reorder the lists */ |
955 | batch_obj = list_entry(objects.prev, | |
956 | struct drm_i915_gem_object, | |
957 | exec_list); | |
958 | ||
54cf91dc | 959 | /* Move the objects en-masse into the GTT, evicting if necessary. */ |
6fe4f140 | 960 | ret = i915_gem_execbuffer_reserve(ring, file, &objects); |
54cf91dc CW |
961 | if (ret) |
962 | goto err; | |
963 | ||
964 | /* The objects are in their final locations, apply the relocations. */ | |
6fe4f140 | 965 | ret = i915_gem_execbuffer_relocate(dev, eb, &objects); |
54cf91dc CW |
966 | if (ret) { |
967 | if (ret == -EFAULT) { | |
d9e86c0e | 968 | ret = i915_gem_execbuffer_relocate_slow(dev, file, ring, |
67731b87 CW |
969 | &objects, eb, |
970 | exec, | |
54cf91dc CW |
971 | args->buffer_count); |
972 | BUG_ON(!mutex_is_locked(&dev->struct_mutex)); | |
973 | } | |
974 | if (ret) | |
975 | goto err; | |
976 | } | |
977 | ||
978 | /* Set the pending read domains for the batch buffer to COMMAND */ | |
54cf91dc | 979 | if (batch_obj->base.pending_write_domain) { |
ff240199 | 980 | DRM_DEBUG("Attempting to use self-modifying batch buffer\n"); |
54cf91dc CW |
981 | ret = -EINVAL; |
982 | goto err; | |
983 | } | |
984 | batch_obj->base.pending_read_domains |= I915_GEM_DOMAIN_COMMAND; | |
985 | ||
d7d4eedd CW |
986 | /* snb/ivb/vlv conflate the "batch in ppgtt" bit with the "non-secure |
987 | * batch" bit. Hence we need to pin secure batches into the global gtt. | |
988 | * hsw should have this fixed, but let's be paranoid and do it | |
989 | * unconditionally for now. */ | |
990 | if (flags & I915_DISPATCH_SECURE && !batch_obj->has_global_gtt_mapping) | |
991 | i915_gem_gtt_bind_object(batch_obj, batch_obj->cache_level); | |
992 | ||
432e58ed CW |
993 | ret = i915_gem_execbuffer_move_to_gpu(ring, &objects); |
994 | if (ret) | |
54cf91dc | 995 | goto err; |
54cf91dc | 996 | |
db53a302 | 997 | seqno = i915_gem_next_request_seqno(ring); |
076e2c0e | 998 | for (i = 0; i < ARRAY_SIZE(ring->sync_seqno); i++) { |
1ec14ad3 CW |
999 | if (seqno < ring->sync_seqno[i]) { |
1000 | /* The GPU can not handle its semaphore value wrapping, | |
1001 | * so every billion or so execbuffers, we need to stall | |
1002 | * the GPU in order to reset the counters. | |
1003 | */ | |
b2da9fe5 | 1004 | ret = i915_gpu_idle(dev); |
1ec14ad3 CW |
1005 | if (ret) |
1006 | goto err; | |
b2da9fe5 | 1007 | i915_gem_retire_requests(dev); |
1ec14ad3 CW |
1008 | |
1009 | BUG_ON(ring->sync_seqno[i]); | |
1010 | } | |
1011 | } | |
1012 | ||
0da5cec1 EA |
1013 | ret = i915_switch_context(ring, file, ctx_id); |
1014 | if (ret) | |
1015 | goto err; | |
1016 | ||
e2971bda BW |
1017 | if (ring == &dev_priv->ring[RCS] && |
1018 | mode != dev_priv->relative_constants_mode) { | |
1019 | ret = intel_ring_begin(ring, 4); | |
1020 | if (ret) | |
1021 | goto err; | |
1022 | ||
1023 | intel_ring_emit(ring, MI_NOOP); | |
1024 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); | |
1025 | intel_ring_emit(ring, INSTPM); | |
84f9f938 | 1026 | intel_ring_emit(ring, mask << 16 | mode); |
e2971bda BW |
1027 | intel_ring_advance(ring); |
1028 | ||
1029 | dev_priv->relative_constants_mode = mode; | |
1030 | } | |
1031 | ||
ae662d31 EA |
1032 | if (args->flags & I915_EXEC_GEN7_SOL_RESET) { |
1033 | ret = i915_reset_gen7_sol_offsets(dev, ring); | |
1034 | if (ret) | |
1035 | goto err; | |
1036 | } | |
1037 | ||
d7d4eedd | 1038 | trace_i915_gem_ring_dispatch(ring, seqno, flags); |
db53a302 | 1039 | |
c4e7a414 CW |
1040 | exec_start = batch_obj->gtt_offset + args->batch_start_offset; |
1041 | exec_len = args->batch_len; | |
1042 | if (cliprects) { | |
1043 | for (i = 0; i < args->num_cliprects; i++) { | |
1044 | ret = i915_emit_box(dev, &cliprects[i], | |
1045 | args->DR1, args->DR4); | |
1046 | if (ret) | |
1047 | goto err; | |
1048 | ||
1049 | ret = ring->dispatch_execbuffer(ring, | |
d7d4eedd CW |
1050 | exec_start, exec_len, |
1051 | flags); | |
c4e7a414 CW |
1052 | if (ret) |
1053 | goto err; | |
1054 | } | |
1055 | } else { | |
d7d4eedd CW |
1056 | ret = ring->dispatch_execbuffer(ring, |
1057 | exec_start, exec_len, | |
1058 | flags); | |
c4e7a414 CW |
1059 | if (ret) |
1060 | goto err; | |
1061 | } | |
54cf91dc | 1062 | |
1ec14ad3 | 1063 | i915_gem_execbuffer_move_to_active(&objects, ring, seqno); |
432e58ed | 1064 | i915_gem_execbuffer_retire_commands(dev, file, ring); |
54cf91dc CW |
1065 | |
1066 | err: | |
67731b87 | 1067 | eb_destroy(eb); |
432e58ed CW |
1068 | while (!list_empty(&objects)) { |
1069 | struct drm_i915_gem_object *obj; | |
1070 | ||
1071 | obj = list_first_entry(&objects, | |
1072 | struct drm_i915_gem_object, | |
1073 | exec_list); | |
1074 | list_del_init(&obj->exec_list); | |
1075 | drm_gem_object_unreference(&obj->base); | |
54cf91dc CW |
1076 | } |
1077 | ||
1078 | mutex_unlock(&dev->struct_mutex); | |
1079 | ||
1080 | pre_mutex_err: | |
54cf91dc | 1081 | kfree(cliprects); |
54cf91dc CW |
1082 | return ret; |
1083 | } | |
1084 | ||
1085 | /* | |
1086 | * Legacy execbuffer just creates an exec2 list from the original exec object | |
1087 | * list array and passes it to the real function. | |
1088 | */ | |
1089 | int | |
1090 | i915_gem_execbuffer(struct drm_device *dev, void *data, | |
1091 | struct drm_file *file) | |
1092 | { | |
1093 | struct drm_i915_gem_execbuffer *args = data; | |
1094 | struct drm_i915_gem_execbuffer2 exec2; | |
1095 | struct drm_i915_gem_exec_object *exec_list = NULL; | |
1096 | struct drm_i915_gem_exec_object2 *exec2_list = NULL; | |
1097 | int ret, i; | |
1098 | ||
54cf91dc | 1099 | if (args->buffer_count < 1) { |
ff240199 | 1100 | DRM_DEBUG("execbuf with %d buffers\n", args->buffer_count); |
54cf91dc CW |
1101 | return -EINVAL; |
1102 | } | |
1103 | ||
1104 | /* Copy in the exec list from userland */ | |
1105 | exec_list = drm_malloc_ab(sizeof(*exec_list), args->buffer_count); | |
1106 | exec2_list = drm_malloc_ab(sizeof(*exec2_list), args->buffer_count); | |
1107 | if (exec_list == NULL || exec2_list == NULL) { | |
ff240199 | 1108 | DRM_DEBUG("Failed to allocate exec list for %d buffers\n", |
54cf91dc CW |
1109 | args->buffer_count); |
1110 | drm_free_large(exec_list); | |
1111 | drm_free_large(exec2_list); | |
1112 | return -ENOMEM; | |
1113 | } | |
1114 | ret = copy_from_user(exec_list, | |
ba7a6458 | 1115 | (void __user *)(uintptr_t)args->buffers_ptr, |
54cf91dc CW |
1116 | sizeof(*exec_list) * args->buffer_count); |
1117 | if (ret != 0) { | |
ff240199 | 1118 | DRM_DEBUG("copy %d exec entries failed %d\n", |
54cf91dc CW |
1119 | args->buffer_count, ret); |
1120 | drm_free_large(exec_list); | |
1121 | drm_free_large(exec2_list); | |
1122 | return -EFAULT; | |
1123 | } | |
1124 | ||
1125 | for (i = 0; i < args->buffer_count; i++) { | |
1126 | exec2_list[i].handle = exec_list[i].handle; | |
1127 | exec2_list[i].relocation_count = exec_list[i].relocation_count; | |
1128 | exec2_list[i].relocs_ptr = exec_list[i].relocs_ptr; | |
1129 | exec2_list[i].alignment = exec_list[i].alignment; | |
1130 | exec2_list[i].offset = exec_list[i].offset; | |
1131 | if (INTEL_INFO(dev)->gen < 4) | |
1132 | exec2_list[i].flags = EXEC_OBJECT_NEEDS_FENCE; | |
1133 | else | |
1134 | exec2_list[i].flags = 0; | |
1135 | } | |
1136 | ||
1137 | exec2.buffers_ptr = args->buffers_ptr; | |
1138 | exec2.buffer_count = args->buffer_count; | |
1139 | exec2.batch_start_offset = args->batch_start_offset; | |
1140 | exec2.batch_len = args->batch_len; | |
1141 | exec2.DR1 = args->DR1; | |
1142 | exec2.DR4 = args->DR4; | |
1143 | exec2.num_cliprects = args->num_cliprects; | |
1144 | exec2.cliprects_ptr = args->cliprects_ptr; | |
1145 | exec2.flags = I915_EXEC_RENDER; | |
6e0a69db | 1146 | i915_execbuffer2_set_context_id(exec2, 0); |
54cf91dc CW |
1147 | |
1148 | ret = i915_gem_do_execbuffer(dev, data, file, &exec2, exec2_list); | |
1149 | if (!ret) { | |
1150 | /* Copy the new buffer offsets back to the user's exec list. */ | |
1151 | for (i = 0; i < args->buffer_count; i++) | |
1152 | exec_list[i].offset = exec2_list[i].offset; | |
1153 | /* ... and back out to userspace */ | |
ba7a6458 | 1154 | ret = copy_to_user((void __user *)(uintptr_t)args->buffers_ptr, |
54cf91dc CW |
1155 | exec_list, |
1156 | sizeof(*exec_list) * args->buffer_count); | |
1157 | if (ret) { | |
1158 | ret = -EFAULT; | |
ff240199 | 1159 | DRM_DEBUG("failed to copy %d exec entries " |
54cf91dc CW |
1160 | "back to user (%d)\n", |
1161 | args->buffer_count, ret); | |
1162 | } | |
1163 | } | |
1164 | ||
1165 | drm_free_large(exec_list); | |
1166 | drm_free_large(exec2_list); | |
1167 | return ret; | |
1168 | } | |
1169 | ||
1170 | int | |
1171 | i915_gem_execbuffer2(struct drm_device *dev, void *data, | |
1172 | struct drm_file *file) | |
1173 | { | |
1174 | struct drm_i915_gem_execbuffer2 *args = data; | |
1175 | struct drm_i915_gem_exec_object2 *exec2_list = NULL; | |
1176 | int ret; | |
1177 | ||
ed8cd3b2 XW |
1178 | if (args->buffer_count < 1 || |
1179 | args->buffer_count > UINT_MAX / sizeof(*exec2_list)) { | |
ff240199 | 1180 | DRM_DEBUG("execbuf2 with %d buffers\n", args->buffer_count); |
54cf91dc CW |
1181 | return -EINVAL; |
1182 | } | |
1183 | ||
8408c282 CW |
1184 | exec2_list = kmalloc(sizeof(*exec2_list)*args->buffer_count, |
1185 | GFP_KERNEL | __GFP_NOWARN | __GFP_NORETRY); | |
1186 | if (exec2_list == NULL) | |
1187 | exec2_list = drm_malloc_ab(sizeof(*exec2_list), | |
1188 | args->buffer_count); | |
54cf91dc | 1189 | if (exec2_list == NULL) { |
ff240199 | 1190 | DRM_DEBUG("Failed to allocate exec list for %d buffers\n", |
54cf91dc CW |
1191 | args->buffer_count); |
1192 | return -ENOMEM; | |
1193 | } | |
1194 | ret = copy_from_user(exec2_list, | |
1195 | (struct drm_i915_relocation_entry __user *) | |
1196 | (uintptr_t) args->buffers_ptr, | |
1197 | sizeof(*exec2_list) * args->buffer_count); | |
1198 | if (ret != 0) { | |
ff240199 | 1199 | DRM_DEBUG("copy %d exec entries failed %d\n", |
54cf91dc CW |
1200 | args->buffer_count, ret); |
1201 | drm_free_large(exec2_list); | |
1202 | return -EFAULT; | |
1203 | } | |
1204 | ||
1205 | ret = i915_gem_do_execbuffer(dev, data, file, args, exec2_list); | |
1206 | if (!ret) { | |
1207 | /* Copy the new buffer offsets back to the user's exec list. */ | |
ba7a6458 | 1208 | ret = copy_to_user((void __user *)(uintptr_t)args->buffers_ptr, |
54cf91dc CW |
1209 | exec2_list, |
1210 | sizeof(*exec2_list) * args->buffer_count); | |
1211 | if (ret) { | |
1212 | ret = -EFAULT; | |
ff240199 | 1213 | DRM_DEBUG("failed to copy %d exec entries " |
54cf91dc CW |
1214 | "back to user (%d)\n", |
1215 | args->buffer_count, ret); | |
1216 | } | |
1217 | } | |
1218 | ||
1219 | drm_free_large(exec2_list); | |
1220 | return ret; | |
1221 | } |