Commit | Line | Data |
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54cf91dc CW |
1 | /* |
2 | * Copyright © 2008,2010 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | * Chris Wilson <chris@chris-wilson.co.uk> | |
26 | * | |
27 | */ | |
28 | ||
29 | #include "drmP.h" | |
30 | #include "drm.h" | |
31 | #include "i915_drm.h" | |
32 | #include "i915_drv.h" | |
33 | #include "i915_trace.h" | |
34 | #include "intel_drv.h" | |
f45b5557 | 35 | #include <linux/dma_remapping.h> |
54cf91dc | 36 | |
67731b87 CW |
37 | struct eb_objects { |
38 | int and; | |
39 | struct hlist_head buckets[0]; | |
40 | }; | |
41 | ||
42 | static struct eb_objects * | |
43 | eb_create(int size) | |
44 | { | |
45 | struct eb_objects *eb; | |
46 | int count = PAGE_SIZE / sizeof(struct hlist_head) / 2; | |
47 | while (count > size) | |
48 | count >>= 1; | |
49 | eb = kzalloc(count*sizeof(struct hlist_head) + | |
50 | sizeof(struct eb_objects), | |
51 | GFP_KERNEL); | |
52 | if (eb == NULL) | |
53 | return eb; | |
54 | ||
55 | eb->and = count - 1; | |
56 | return eb; | |
57 | } | |
58 | ||
59 | static void | |
60 | eb_reset(struct eb_objects *eb) | |
61 | { | |
62 | memset(eb->buckets, 0, (eb->and+1)*sizeof(struct hlist_head)); | |
63 | } | |
64 | ||
65 | static void | |
66 | eb_add_object(struct eb_objects *eb, struct drm_i915_gem_object *obj) | |
67 | { | |
68 | hlist_add_head(&obj->exec_node, | |
69 | &eb->buckets[obj->exec_handle & eb->and]); | |
70 | } | |
71 | ||
72 | static struct drm_i915_gem_object * | |
73 | eb_get_object(struct eb_objects *eb, unsigned long handle) | |
74 | { | |
75 | struct hlist_head *head; | |
76 | struct hlist_node *node; | |
77 | struct drm_i915_gem_object *obj; | |
78 | ||
79 | head = &eb->buckets[handle & eb->and]; | |
80 | hlist_for_each(node, head) { | |
81 | obj = hlist_entry(node, struct drm_i915_gem_object, exec_node); | |
82 | if (obj->exec_handle == handle) | |
83 | return obj; | |
84 | } | |
85 | ||
86 | return NULL; | |
87 | } | |
88 | ||
89 | static void | |
90 | eb_destroy(struct eb_objects *eb) | |
91 | { | |
92 | kfree(eb); | |
93 | } | |
94 | ||
dabdfe02 CW |
95 | static inline int use_cpu_reloc(struct drm_i915_gem_object *obj) |
96 | { | |
97 | return (obj->base.write_domain == I915_GEM_DOMAIN_CPU || | |
98 | obj->cache_level != I915_CACHE_NONE); | |
99 | } | |
100 | ||
54cf91dc CW |
101 | static int |
102 | i915_gem_execbuffer_relocate_entry(struct drm_i915_gem_object *obj, | |
67731b87 | 103 | struct eb_objects *eb, |
54cf91dc CW |
104 | struct drm_i915_gem_relocation_entry *reloc) |
105 | { | |
106 | struct drm_device *dev = obj->base.dev; | |
107 | struct drm_gem_object *target_obj; | |
149c8407 | 108 | struct drm_i915_gem_object *target_i915_obj; |
54cf91dc CW |
109 | uint32_t target_offset; |
110 | int ret = -EINVAL; | |
111 | ||
67731b87 CW |
112 | /* we've already hold a reference to all valid objects */ |
113 | target_obj = &eb_get_object(eb, reloc->target_handle)->base; | |
114 | if (unlikely(target_obj == NULL)) | |
54cf91dc CW |
115 | return -ENOENT; |
116 | ||
149c8407 DV |
117 | target_i915_obj = to_intel_bo(target_obj); |
118 | target_offset = target_i915_obj->gtt_offset; | |
54cf91dc | 119 | |
e844b990 EA |
120 | /* Sandybridge PPGTT errata: We need a global gtt mapping for MI and |
121 | * pipe_control writes because the gpu doesn't properly redirect them | |
122 | * through the ppgtt for non_secure batchbuffers. */ | |
123 | if (unlikely(IS_GEN6(dev) && | |
124 | reloc->write_domain == I915_GEM_DOMAIN_INSTRUCTION && | |
125 | !target_i915_obj->has_global_gtt_mapping)) { | |
126 | i915_gem_gtt_bind_object(target_i915_obj, | |
127 | target_i915_obj->cache_level); | |
128 | } | |
129 | ||
54cf91dc CW |
130 | /* The target buffer should have appeared before us in the |
131 | * exec_object list, so it should have a GTT space bound by now. | |
132 | */ | |
b8f7ab17 | 133 | if (unlikely(target_offset == 0)) { |
ff240199 | 134 | DRM_DEBUG("No GTT space found for object %d\n", |
54cf91dc | 135 | reloc->target_handle); |
67731b87 | 136 | return ret; |
54cf91dc CW |
137 | } |
138 | ||
139 | /* Validate that the target is in a valid r/w GPU domain */ | |
b8f7ab17 | 140 | if (unlikely(reloc->write_domain & (reloc->write_domain - 1))) { |
ff240199 | 141 | DRM_DEBUG("reloc with multiple write domains: " |
54cf91dc CW |
142 | "obj %p target %d offset %d " |
143 | "read %08x write %08x", | |
144 | obj, reloc->target_handle, | |
145 | (int) reloc->offset, | |
146 | reloc->read_domains, | |
147 | reloc->write_domain); | |
67731b87 | 148 | return ret; |
54cf91dc | 149 | } |
4ca4a250 DV |
150 | if (unlikely((reloc->write_domain | reloc->read_domains) |
151 | & ~I915_GEM_GPU_DOMAINS)) { | |
ff240199 | 152 | DRM_DEBUG("reloc with read/write non-GPU domains: " |
54cf91dc CW |
153 | "obj %p target %d offset %d " |
154 | "read %08x write %08x", | |
155 | obj, reloc->target_handle, | |
156 | (int) reloc->offset, | |
157 | reloc->read_domains, | |
158 | reloc->write_domain); | |
67731b87 | 159 | return ret; |
54cf91dc | 160 | } |
b8f7ab17 CW |
161 | if (unlikely(reloc->write_domain && target_obj->pending_write_domain && |
162 | reloc->write_domain != target_obj->pending_write_domain)) { | |
ff240199 | 163 | DRM_DEBUG("Write domain conflict: " |
54cf91dc CW |
164 | "obj %p target %d offset %d " |
165 | "new %08x old %08x\n", | |
166 | obj, reloc->target_handle, | |
167 | (int) reloc->offset, | |
168 | reloc->write_domain, | |
169 | target_obj->pending_write_domain); | |
67731b87 | 170 | return ret; |
54cf91dc CW |
171 | } |
172 | ||
173 | target_obj->pending_read_domains |= reloc->read_domains; | |
174 | target_obj->pending_write_domain |= reloc->write_domain; | |
175 | ||
176 | /* If the relocation already has the right value in it, no | |
177 | * more work needs to be done. | |
178 | */ | |
179 | if (target_offset == reloc->presumed_offset) | |
67731b87 | 180 | return 0; |
54cf91dc CW |
181 | |
182 | /* Check that the relocation address is valid... */ | |
b8f7ab17 | 183 | if (unlikely(reloc->offset > obj->base.size - 4)) { |
ff240199 | 184 | DRM_DEBUG("Relocation beyond object bounds: " |
54cf91dc CW |
185 | "obj %p target %d offset %d size %d.\n", |
186 | obj, reloc->target_handle, | |
187 | (int) reloc->offset, | |
188 | (int) obj->base.size); | |
67731b87 | 189 | return ret; |
54cf91dc | 190 | } |
b8f7ab17 | 191 | if (unlikely(reloc->offset & 3)) { |
ff240199 | 192 | DRM_DEBUG("Relocation not 4-byte aligned: " |
54cf91dc CW |
193 | "obj %p target %d offset %d.\n", |
194 | obj, reloc->target_handle, | |
195 | (int) reloc->offset); | |
67731b87 | 196 | return ret; |
54cf91dc CW |
197 | } |
198 | ||
dabdfe02 CW |
199 | /* We can't wait for rendering with pagefaults disabled */ |
200 | if (obj->active && in_atomic()) | |
201 | return -EFAULT; | |
202 | ||
54cf91dc | 203 | reloc->delta += target_offset; |
dabdfe02 | 204 | if (use_cpu_reloc(obj)) { |
54cf91dc CW |
205 | uint32_t page_offset = reloc->offset & ~PAGE_MASK; |
206 | char *vaddr; | |
207 | ||
dabdfe02 CW |
208 | ret = i915_gem_object_set_to_cpu_domain(obj, 1); |
209 | if (ret) | |
210 | return ret; | |
211 | ||
54cf91dc CW |
212 | vaddr = kmap_atomic(obj->pages[reloc->offset >> PAGE_SHIFT]); |
213 | *(uint32_t *)(vaddr + page_offset) = reloc->delta; | |
214 | kunmap_atomic(vaddr); | |
215 | } else { | |
216 | struct drm_i915_private *dev_priv = dev->dev_private; | |
217 | uint32_t __iomem *reloc_entry; | |
218 | void __iomem *reloc_page; | |
219 | ||
7b09638f CW |
220 | ret = i915_gem_object_set_to_gtt_domain(obj, true); |
221 | if (ret) | |
222 | return ret; | |
223 | ||
224 | ret = i915_gem_object_put_fence(obj); | |
54cf91dc | 225 | if (ret) |
67731b87 | 226 | return ret; |
54cf91dc CW |
227 | |
228 | /* Map the page containing the relocation we're going to perform. */ | |
229 | reloc->offset += obj->gtt_offset; | |
230 | reloc_page = io_mapping_map_atomic_wc(dev_priv->mm.gtt_mapping, | |
231 | reloc->offset & PAGE_MASK); | |
232 | reloc_entry = (uint32_t __iomem *) | |
233 | (reloc_page + (reloc->offset & ~PAGE_MASK)); | |
234 | iowrite32(reloc->delta, reloc_entry); | |
235 | io_mapping_unmap_atomic(reloc_page); | |
236 | } | |
237 | ||
238 | /* and update the user's relocation entry */ | |
239 | reloc->presumed_offset = target_offset; | |
240 | ||
67731b87 | 241 | return 0; |
54cf91dc CW |
242 | } |
243 | ||
244 | static int | |
245 | i915_gem_execbuffer_relocate_object(struct drm_i915_gem_object *obj, | |
6fe4f140 | 246 | struct eb_objects *eb) |
54cf91dc | 247 | { |
1d83f442 CW |
248 | #define N_RELOC(x) ((x) / sizeof(struct drm_i915_gem_relocation_entry)) |
249 | struct drm_i915_gem_relocation_entry stack_reloc[N_RELOC(512)]; | |
54cf91dc | 250 | struct drm_i915_gem_relocation_entry __user *user_relocs; |
6fe4f140 | 251 | struct drm_i915_gem_exec_object2 *entry = obj->exec_entry; |
1d83f442 | 252 | int remain, ret; |
54cf91dc CW |
253 | |
254 | user_relocs = (void __user *)(uintptr_t)entry->relocs_ptr; | |
54cf91dc | 255 | |
1d83f442 CW |
256 | remain = entry->relocation_count; |
257 | while (remain) { | |
258 | struct drm_i915_gem_relocation_entry *r = stack_reloc; | |
259 | int count = remain; | |
260 | if (count > ARRAY_SIZE(stack_reloc)) | |
261 | count = ARRAY_SIZE(stack_reloc); | |
262 | remain -= count; | |
263 | ||
264 | if (__copy_from_user_inatomic(r, user_relocs, count*sizeof(r[0]))) | |
54cf91dc CW |
265 | return -EFAULT; |
266 | ||
1d83f442 CW |
267 | do { |
268 | u64 offset = r->presumed_offset; | |
54cf91dc | 269 | |
1d83f442 CW |
270 | ret = i915_gem_execbuffer_relocate_entry(obj, eb, r); |
271 | if (ret) | |
272 | return ret; | |
273 | ||
274 | if (r->presumed_offset != offset && | |
275 | __copy_to_user_inatomic(&user_relocs->presumed_offset, | |
276 | &r->presumed_offset, | |
277 | sizeof(r->presumed_offset))) { | |
278 | return -EFAULT; | |
279 | } | |
280 | ||
281 | user_relocs++; | |
282 | r++; | |
283 | } while (--count); | |
54cf91dc CW |
284 | } |
285 | ||
286 | return 0; | |
1d83f442 | 287 | #undef N_RELOC |
54cf91dc CW |
288 | } |
289 | ||
290 | static int | |
291 | i915_gem_execbuffer_relocate_object_slow(struct drm_i915_gem_object *obj, | |
67731b87 | 292 | struct eb_objects *eb, |
54cf91dc CW |
293 | struct drm_i915_gem_relocation_entry *relocs) |
294 | { | |
6fe4f140 | 295 | const struct drm_i915_gem_exec_object2 *entry = obj->exec_entry; |
54cf91dc CW |
296 | int i, ret; |
297 | ||
298 | for (i = 0; i < entry->relocation_count; i++) { | |
6fe4f140 | 299 | ret = i915_gem_execbuffer_relocate_entry(obj, eb, &relocs[i]); |
54cf91dc CW |
300 | if (ret) |
301 | return ret; | |
302 | } | |
303 | ||
304 | return 0; | |
305 | } | |
306 | ||
307 | static int | |
308 | i915_gem_execbuffer_relocate(struct drm_device *dev, | |
67731b87 | 309 | struct eb_objects *eb, |
6fe4f140 | 310 | struct list_head *objects) |
54cf91dc | 311 | { |
432e58ed | 312 | struct drm_i915_gem_object *obj; |
d4aeee77 CW |
313 | int ret = 0; |
314 | ||
315 | /* This is the fast path and we cannot handle a pagefault whilst | |
316 | * holding the struct mutex lest the user pass in the relocations | |
317 | * contained within a mmaped bo. For in such a case we, the page | |
318 | * fault handler would call i915_gem_fault() and we would try to | |
319 | * acquire the struct mutex again. Obviously this is bad and so | |
320 | * lockdep complains vehemently. | |
321 | */ | |
322 | pagefault_disable(); | |
432e58ed | 323 | list_for_each_entry(obj, objects, exec_list) { |
6fe4f140 | 324 | ret = i915_gem_execbuffer_relocate_object(obj, eb); |
54cf91dc | 325 | if (ret) |
d4aeee77 | 326 | break; |
54cf91dc | 327 | } |
d4aeee77 | 328 | pagefault_enable(); |
54cf91dc | 329 | |
d4aeee77 | 330 | return ret; |
54cf91dc CW |
331 | } |
332 | ||
1690e1eb CW |
333 | #define __EXEC_OBJECT_HAS_FENCE (1<<31) |
334 | ||
dabdfe02 CW |
335 | static int |
336 | need_reloc_mappable(struct drm_i915_gem_object *obj) | |
337 | { | |
338 | struct drm_i915_gem_exec_object2 *entry = obj->exec_entry; | |
339 | return entry->relocation_count && !use_cpu_reloc(obj); | |
340 | } | |
341 | ||
1690e1eb CW |
342 | static int |
343 | pin_and_fence_object(struct drm_i915_gem_object *obj, | |
344 | struct intel_ring_buffer *ring) | |
345 | { | |
346 | struct drm_i915_gem_exec_object2 *entry = obj->exec_entry; | |
347 | bool has_fenced_gpu_access = INTEL_INFO(ring->dev)->gen < 4; | |
348 | bool need_fence, need_mappable; | |
349 | int ret; | |
350 | ||
351 | need_fence = | |
352 | has_fenced_gpu_access && | |
353 | entry->flags & EXEC_OBJECT_NEEDS_FENCE && | |
354 | obj->tiling_mode != I915_TILING_NONE; | |
dabdfe02 | 355 | need_mappable = need_fence || need_reloc_mappable(obj); |
1690e1eb CW |
356 | |
357 | ret = i915_gem_object_pin(obj, entry->alignment, need_mappable); | |
358 | if (ret) | |
359 | return ret; | |
360 | ||
361 | if (has_fenced_gpu_access) { | |
362 | if (entry->flags & EXEC_OBJECT_NEEDS_FENCE) { | |
06d98131 | 363 | ret = i915_gem_object_get_fence(obj); |
9a5a53b3 CW |
364 | if (ret) |
365 | goto err_unpin; | |
1690e1eb | 366 | |
9a5a53b3 | 367 | if (i915_gem_object_pin_fence(obj)) |
1690e1eb | 368 | entry->flags |= __EXEC_OBJECT_HAS_FENCE; |
9a5a53b3 | 369 | |
7dd49065 | 370 | obj->pending_fenced_gpu_access = true; |
1690e1eb | 371 | } |
1690e1eb CW |
372 | } |
373 | ||
374 | entry->offset = obj->gtt_offset; | |
375 | return 0; | |
376 | ||
377 | err_unpin: | |
378 | i915_gem_object_unpin(obj); | |
379 | return ret; | |
380 | } | |
381 | ||
54cf91dc | 382 | static int |
d9e86c0e | 383 | i915_gem_execbuffer_reserve(struct intel_ring_buffer *ring, |
54cf91dc | 384 | struct drm_file *file, |
6fe4f140 | 385 | struct list_head *objects) |
54cf91dc | 386 | { |
7bddb01f | 387 | drm_i915_private_t *dev_priv = ring->dev->dev_private; |
432e58ed | 388 | struct drm_i915_gem_object *obj; |
432e58ed | 389 | int ret, retry; |
9b3826bf | 390 | bool has_fenced_gpu_access = INTEL_INFO(ring->dev)->gen < 4; |
6fe4f140 CW |
391 | struct list_head ordered_objects; |
392 | ||
393 | INIT_LIST_HEAD(&ordered_objects); | |
394 | while (!list_empty(objects)) { | |
395 | struct drm_i915_gem_exec_object2 *entry; | |
396 | bool need_fence, need_mappable; | |
397 | ||
398 | obj = list_first_entry(objects, | |
399 | struct drm_i915_gem_object, | |
400 | exec_list); | |
401 | entry = obj->exec_entry; | |
402 | ||
403 | need_fence = | |
404 | has_fenced_gpu_access && | |
405 | entry->flags & EXEC_OBJECT_NEEDS_FENCE && | |
406 | obj->tiling_mode != I915_TILING_NONE; | |
dabdfe02 | 407 | need_mappable = need_fence || need_reloc_mappable(obj); |
6fe4f140 CW |
408 | |
409 | if (need_mappable) | |
410 | list_move(&obj->exec_list, &ordered_objects); | |
411 | else | |
412 | list_move_tail(&obj->exec_list, &ordered_objects); | |
595dad76 CW |
413 | |
414 | obj->base.pending_read_domains = 0; | |
415 | obj->base.pending_write_domain = 0; | |
016fd0c1 | 416 | obj->pending_fenced_gpu_access = false; |
6fe4f140 CW |
417 | } |
418 | list_splice(&ordered_objects, objects); | |
54cf91dc CW |
419 | |
420 | /* Attempt to pin all of the buffers into the GTT. | |
421 | * This is done in 3 phases: | |
422 | * | |
423 | * 1a. Unbind all objects that do not match the GTT constraints for | |
424 | * the execbuffer (fenceable, mappable, alignment etc). | |
425 | * 1b. Increment pin count for already bound objects. | |
426 | * 2. Bind new objects. | |
427 | * 3. Decrement pin count. | |
428 | * | |
429 | * This avoid unnecessary unbinding of later objects in order to makr | |
430 | * room for the earlier objects *unless* we need to defragment. | |
431 | */ | |
432 | retry = 0; | |
433 | do { | |
434 | ret = 0; | |
435 | ||
436 | /* Unbind any ill-fitting objects or pin. */ | |
432e58ed | 437 | list_for_each_entry(obj, objects, exec_list) { |
6fe4f140 | 438 | struct drm_i915_gem_exec_object2 *entry = obj->exec_entry; |
54cf91dc | 439 | bool need_fence, need_mappable; |
1690e1eb | 440 | |
6fe4f140 | 441 | if (!obj->gtt_space) |
54cf91dc CW |
442 | continue; |
443 | ||
444 | need_fence = | |
9b3826bf | 445 | has_fenced_gpu_access && |
54cf91dc CW |
446 | entry->flags & EXEC_OBJECT_NEEDS_FENCE && |
447 | obj->tiling_mode != I915_TILING_NONE; | |
dabdfe02 | 448 | need_mappable = need_fence || need_reloc_mappable(obj); |
54cf91dc CW |
449 | |
450 | if ((entry->alignment && obj->gtt_offset & (entry->alignment - 1)) || | |
451 | (need_mappable && !obj->map_and_fenceable)) | |
452 | ret = i915_gem_object_unbind(obj); | |
453 | else | |
1690e1eb | 454 | ret = pin_and_fence_object(obj, ring); |
432e58ed | 455 | if (ret) |
54cf91dc | 456 | goto err; |
54cf91dc CW |
457 | } |
458 | ||
459 | /* Bind fresh objects */ | |
432e58ed | 460 | list_for_each_entry(obj, objects, exec_list) { |
1690e1eb CW |
461 | if (obj->gtt_space) |
462 | continue; | |
54cf91dc | 463 | |
1690e1eb CW |
464 | ret = pin_and_fence_object(obj, ring); |
465 | if (ret) { | |
466 | int ret_ignore; | |
467 | ||
468 | /* This can potentially raise a harmless | |
469 | * -EINVAL if we failed to bind in the above | |
470 | * call. It cannot raise -EINTR since we know | |
471 | * that the bo is freshly bound and so will | |
472 | * not need to be flushed or waited upon. | |
473 | */ | |
474 | ret_ignore = i915_gem_object_unbind(obj); | |
475 | (void)ret_ignore; | |
476 | WARN_ON(obj->gtt_space); | |
477 | break; | |
54cf91dc | 478 | } |
54cf91dc CW |
479 | } |
480 | ||
432e58ed CW |
481 | /* Decrement pin count for bound objects */ |
482 | list_for_each_entry(obj, objects, exec_list) { | |
1690e1eb CW |
483 | struct drm_i915_gem_exec_object2 *entry; |
484 | ||
485 | if (!obj->gtt_space) | |
486 | continue; | |
487 | ||
488 | entry = obj->exec_entry; | |
489 | if (entry->flags & __EXEC_OBJECT_HAS_FENCE) { | |
490 | i915_gem_object_unpin_fence(obj); | |
491 | entry->flags &= ~__EXEC_OBJECT_HAS_FENCE; | |
492 | } | |
493 | ||
494 | i915_gem_object_unpin(obj); | |
7bddb01f DV |
495 | |
496 | /* ... and ensure ppgtt mapping exist if needed. */ | |
497 | if (dev_priv->mm.aliasing_ppgtt && !obj->has_aliasing_ppgtt_mapping) { | |
498 | i915_ppgtt_bind_object(dev_priv->mm.aliasing_ppgtt, | |
499 | obj, obj->cache_level); | |
500 | ||
501 | obj->has_aliasing_ppgtt_mapping = 1; | |
502 | } | |
54cf91dc CW |
503 | } |
504 | ||
6c085a72 | 505 | if (ret != -ENOSPC || retry++) |
54cf91dc CW |
506 | return ret; |
507 | ||
6c085a72 | 508 | ret = i915_gem_evict_everything(ring->dev); |
54cf91dc CW |
509 | if (ret) |
510 | return ret; | |
54cf91dc | 511 | } while (1); |
432e58ed CW |
512 | |
513 | err: | |
1690e1eb CW |
514 | list_for_each_entry_continue_reverse(obj, objects, exec_list) { |
515 | struct drm_i915_gem_exec_object2 *entry; | |
516 | ||
517 | if (!obj->gtt_space) | |
518 | continue; | |
519 | ||
520 | entry = obj->exec_entry; | |
521 | if (entry->flags & __EXEC_OBJECT_HAS_FENCE) { | |
522 | i915_gem_object_unpin_fence(obj); | |
523 | entry->flags &= ~__EXEC_OBJECT_HAS_FENCE; | |
524 | } | |
432e58ed | 525 | |
1690e1eb | 526 | i915_gem_object_unpin(obj); |
432e58ed CW |
527 | } |
528 | ||
529 | return ret; | |
54cf91dc CW |
530 | } |
531 | ||
532 | static int | |
533 | i915_gem_execbuffer_relocate_slow(struct drm_device *dev, | |
534 | struct drm_file *file, | |
d9e86c0e | 535 | struct intel_ring_buffer *ring, |
432e58ed | 536 | struct list_head *objects, |
67731b87 | 537 | struct eb_objects *eb, |
432e58ed | 538 | struct drm_i915_gem_exec_object2 *exec, |
54cf91dc CW |
539 | int count) |
540 | { | |
541 | struct drm_i915_gem_relocation_entry *reloc; | |
432e58ed | 542 | struct drm_i915_gem_object *obj; |
dd6864a4 | 543 | int *reloc_offset; |
54cf91dc CW |
544 | int i, total, ret; |
545 | ||
67731b87 | 546 | /* We may process another execbuffer during the unlock... */ |
36cf1742 | 547 | while (!list_empty(objects)) { |
67731b87 CW |
548 | obj = list_first_entry(objects, |
549 | struct drm_i915_gem_object, | |
550 | exec_list); | |
551 | list_del_init(&obj->exec_list); | |
552 | drm_gem_object_unreference(&obj->base); | |
553 | } | |
554 | ||
54cf91dc CW |
555 | mutex_unlock(&dev->struct_mutex); |
556 | ||
557 | total = 0; | |
558 | for (i = 0; i < count; i++) | |
432e58ed | 559 | total += exec[i].relocation_count; |
54cf91dc | 560 | |
dd6864a4 | 561 | reloc_offset = drm_malloc_ab(count, sizeof(*reloc_offset)); |
54cf91dc | 562 | reloc = drm_malloc_ab(total, sizeof(*reloc)); |
dd6864a4 CW |
563 | if (reloc == NULL || reloc_offset == NULL) { |
564 | drm_free_large(reloc); | |
565 | drm_free_large(reloc_offset); | |
54cf91dc CW |
566 | mutex_lock(&dev->struct_mutex); |
567 | return -ENOMEM; | |
568 | } | |
569 | ||
570 | total = 0; | |
571 | for (i = 0; i < count; i++) { | |
572 | struct drm_i915_gem_relocation_entry __user *user_relocs; | |
573 | ||
432e58ed | 574 | user_relocs = (void __user *)(uintptr_t)exec[i].relocs_ptr; |
54cf91dc CW |
575 | |
576 | if (copy_from_user(reloc+total, user_relocs, | |
432e58ed | 577 | exec[i].relocation_count * sizeof(*reloc))) { |
54cf91dc CW |
578 | ret = -EFAULT; |
579 | mutex_lock(&dev->struct_mutex); | |
580 | goto err; | |
581 | } | |
582 | ||
dd6864a4 | 583 | reloc_offset[i] = total; |
432e58ed | 584 | total += exec[i].relocation_count; |
54cf91dc CW |
585 | } |
586 | ||
587 | ret = i915_mutex_lock_interruptible(dev); | |
588 | if (ret) { | |
589 | mutex_lock(&dev->struct_mutex); | |
590 | goto err; | |
591 | } | |
592 | ||
67731b87 | 593 | /* reacquire the objects */ |
67731b87 CW |
594 | eb_reset(eb); |
595 | for (i = 0; i < count; i++) { | |
67731b87 CW |
596 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, |
597 | exec[i].handle)); | |
c8725226 | 598 | if (&obj->base == NULL) { |
ff240199 | 599 | DRM_DEBUG("Invalid object handle %d at index %d\n", |
67731b87 CW |
600 | exec[i].handle, i); |
601 | ret = -ENOENT; | |
602 | goto err; | |
603 | } | |
604 | ||
605 | list_add_tail(&obj->exec_list, objects); | |
606 | obj->exec_handle = exec[i].handle; | |
6fe4f140 | 607 | obj->exec_entry = &exec[i]; |
67731b87 CW |
608 | eb_add_object(eb, obj); |
609 | } | |
610 | ||
6fe4f140 | 611 | ret = i915_gem_execbuffer_reserve(ring, file, objects); |
54cf91dc CW |
612 | if (ret) |
613 | goto err; | |
614 | ||
432e58ed | 615 | list_for_each_entry(obj, objects, exec_list) { |
dd6864a4 | 616 | int offset = obj->exec_entry - exec; |
67731b87 | 617 | ret = i915_gem_execbuffer_relocate_object_slow(obj, eb, |
dd6864a4 | 618 | reloc + reloc_offset[offset]); |
54cf91dc CW |
619 | if (ret) |
620 | goto err; | |
54cf91dc CW |
621 | } |
622 | ||
623 | /* Leave the user relocations as are, this is the painfully slow path, | |
624 | * and we want to avoid the complication of dropping the lock whilst | |
625 | * having buffers reserved in the aperture and so causing spurious | |
626 | * ENOSPC for random operations. | |
627 | */ | |
628 | ||
629 | err: | |
630 | drm_free_large(reloc); | |
dd6864a4 | 631 | drm_free_large(reloc_offset); |
54cf91dc CW |
632 | return ret; |
633 | } | |
634 | ||
c59a333f CW |
635 | static int |
636 | i915_gem_execbuffer_wait_for_flips(struct intel_ring_buffer *ring, u32 flips) | |
637 | { | |
638 | u32 plane, flip_mask; | |
639 | int ret; | |
640 | ||
641 | /* Check for any pending flips. As we only maintain a flip queue depth | |
642 | * of 1, we can simply insert a WAIT for the next display flip prior | |
643 | * to executing the batch and avoid stalling the CPU. | |
644 | */ | |
645 | ||
646 | for (plane = 0; flips >> plane; plane++) { | |
647 | if (((flips >> plane) & 1) == 0) | |
648 | continue; | |
649 | ||
650 | if (plane) | |
651 | flip_mask = MI_WAIT_FOR_PLANE_B_FLIP; | |
652 | else | |
653 | flip_mask = MI_WAIT_FOR_PLANE_A_FLIP; | |
654 | ||
655 | ret = intel_ring_begin(ring, 2); | |
656 | if (ret) | |
657 | return ret; | |
658 | ||
659 | intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask); | |
660 | intel_ring_emit(ring, MI_NOOP); | |
661 | intel_ring_advance(ring); | |
662 | } | |
663 | ||
664 | return 0; | |
665 | } | |
666 | ||
54cf91dc | 667 | static int |
432e58ed CW |
668 | i915_gem_execbuffer_move_to_gpu(struct intel_ring_buffer *ring, |
669 | struct list_head *objects) | |
54cf91dc | 670 | { |
432e58ed | 671 | struct drm_i915_gem_object *obj; |
6ac42f41 DV |
672 | uint32_t flush_domains = 0; |
673 | uint32_t flips = 0; | |
432e58ed | 674 | int ret; |
54cf91dc | 675 | |
6ac42f41 DV |
676 | list_for_each_entry(obj, objects, exec_list) { |
677 | ret = i915_gem_object_sync(obj, ring); | |
c59a333f CW |
678 | if (ret) |
679 | return ret; | |
6ac42f41 DV |
680 | |
681 | if (obj->base.write_domain & I915_GEM_DOMAIN_CPU) | |
682 | i915_gem_clflush_object(obj); | |
683 | ||
684 | if (obj->base.pending_write_domain) | |
685 | flips |= atomic_read(&obj->pending_flip); | |
686 | ||
687 | flush_domains |= obj->base.write_domain; | |
c59a333f CW |
688 | } |
689 | ||
6ac42f41 DV |
690 | if (flips) { |
691 | ret = i915_gem_execbuffer_wait_for_flips(ring, flips); | |
1ec14ad3 CW |
692 | if (ret) |
693 | return ret; | |
54cf91dc CW |
694 | } |
695 | ||
6ac42f41 DV |
696 | if (flush_domains & I915_GEM_DOMAIN_CPU) |
697 | intel_gtt_chipset_flush(); | |
698 | ||
699 | if (flush_domains & I915_GEM_DOMAIN_GTT) | |
700 | wmb(); | |
701 | ||
09cf7c9a CW |
702 | /* Unconditionally invalidate gpu caches and ensure that we do flush |
703 | * any residual writes from the previous batch. | |
704 | */ | |
a7b9761d | 705 | return intel_ring_invalidate_all_caches(ring); |
54cf91dc CW |
706 | } |
707 | ||
432e58ed CW |
708 | static bool |
709 | i915_gem_check_execbuffer(struct drm_i915_gem_execbuffer2 *exec) | |
54cf91dc | 710 | { |
432e58ed | 711 | return ((exec->batch_start_offset | exec->batch_len) & 0x7) == 0; |
54cf91dc CW |
712 | } |
713 | ||
714 | static int | |
715 | validate_exec_list(struct drm_i915_gem_exec_object2 *exec, | |
716 | int count) | |
717 | { | |
718 | int i; | |
719 | ||
720 | for (i = 0; i < count; i++) { | |
721 | char __user *ptr = (char __user *)(uintptr_t)exec[i].relocs_ptr; | |
722 | int length; /* limited by fault_in_pages_readable() */ | |
723 | ||
724 | /* First check for malicious input causing overflow */ | |
725 | if (exec[i].relocation_count > | |
726 | INT_MAX / sizeof(struct drm_i915_gem_relocation_entry)) | |
727 | return -EINVAL; | |
728 | ||
729 | length = exec[i].relocation_count * | |
730 | sizeof(struct drm_i915_gem_relocation_entry); | |
731 | if (!access_ok(VERIFY_READ, ptr, length)) | |
732 | return -EFAULT; | |
733 | ||
734 | /* we may also need to update the presumed offsets */ | |
735 | if (!access_ok(VERIFY_WRITE, ptr, length)) | |
736 | return -EFAULT; | |
737 | ||
f56f821f | 738 | if (fault_in_multipages_readable(ptr, length)) |
54cf91dc CW |
739 | return -EFAULT; |
740 | } | |
741 | ||
742 | return 0; | |
743 | } | |
744 | ||
432e58ed CW |
745 | static void |
746 | i915_gem_execbuffer_move_to_active(struct list_head *objects, | |
1ec14ad3 CW |
747 | struct intel_ring_buffer *ring, |
748 | u32 seqno) | |
432e58ed CW |
749 | { |
750 | struct drm_i915_gem_object *obj; | |
751 | ||
752 | list_for_each_entry(obj, objects, exec_list) { | |
69c2fc89 CW |
753 | u32 old_read = obj->base.read_domains; |
754 | u32 old_write = obj->base.write_domain; | |
db53a302 | 755 | |
432e58ed CW |
756 | obj->base.read_domains = obj->base.pending_read_domains; |
757 | obj->base.write_domain = obj->base.pending_write_domain; | |
758 | obj->fenced_gpu_access = obj->pending_fenced_gpu_access; | |
759 | ||
1ec14ad3 | 760 | i915_gem_object_move_to_active(obj, ring, seqno); |
432e58ed CW |
761 | if (obj->base.write_domain) { |
762 | obj->dirty = 1; | |
0201f1ec | 763 | obj->last_write_seqno = seqno; |
acb87dfb | 764 | if (obj->pin_count) /* check for potential scanout */ |
f047e395 | 765 | intel_mark_fb_busy(obj); |
432e58ed CW |
766 | } |
767 | ||
db53a302 | 768 | trace_i915_gem_object_change_domain(obj, old_read, old_write); |
432e58ed CW |
769 | } |
770 | } | |
771 | ||
54cf91dc CW |
772 | static void |
773 | i915_gem_execbuffer_retire_commands(struct drm_device *dev, | |
432e58ed | 774 | struct drm_file *file, |
54cf91dc CW |
775 | struct intel_ring_buffer *ring) |
776 | { | |
cc889e0f DV |
777 | /* Unconditionally force add_request to emit a full flush. */ |
778 | ring->gpu_caches_dirty = true; | |
54cf91dc | 779 | |
432e58ed | 780 | /* Add a breadcrumb for the completion of the batch buffer */ |
3bb73aba | 781 | (void)i915_add_request(ring, file, NULL); |
432e58ed | 782 | } |
54cf91dc | 783 | |
ae662d31 EA |
784 | static int |
785 | i915_reset_gen7_sol_offsets(struct drm_device *dev, | |
786 | struct intel_ring_buffer *ring) | |
787 | { | |
788 | drm_i915_private_t *dev_priv = dev->dev_private; | |
789 | int ret, i; | |
790 | ||
791 | if (!IS_GEN7(dev) || ring != &dev_priv->ring[RCS]) | |
792 | return 0; | |
793 | ||
794 | ret = intel_ring_begin(ring, 4 * 3); | |
795 | if (ret) | |
796 | return ret; | |
797 | ||
798 | for (i = 0; i < 4; i++) { | |
799 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); | |
800 | intel_ring_emit(ring, GEN7_SO_WRITE_OFFSET(i)); | |
801 | intel_ring_emit(ring, 0); | |
802 | } | |
803 | ||
804 | intel_ring_advance(ring); | |
805 | ||
806 | return 0; | |
807 | } | |
808 | ||
54cf91dc CW |
809 | static int |
810 | i915_gem_do_execbuffer(struct drm_device *dev, void *data, | |
811 | struct drm_file *file, | |
812 | struct drm_i915_gem_execbuffer2 *args, | |
432e58ed | 813 | struct drm_i915_gem_exec_object2 *exec) |
54cf91dc CW |
814 | { |
815 | drm_i915_private_t *dev_priv = dev->dev_private; | |
432e58ed | 816 | struct list_head objects; |
67731b87 | 817 | struct eb_objects *eb; |
54cf91dc CW |
818 | struct drm_i915_gem_object *batch_obj; |
819 | struct drm_clip_rect *cliprects = NULL; | |
54cf91dc | 820 | struct intel_ring_buffer *ring; |
6e0a69db | 821 | u32 ctx_id = i915_execbuffer2_get_context_id(*args); |
c4e7a414 | 822 | u32 exec_start, exec_len; |
1ec14ad3 | 823 | u32 seqno; |
84f9f938 | 824 | u32 mask; |
72bfa19c | 825 | int ret, mode, i; |
54cf91dc | 826 | |
432e58ed | 827 | if (!i915_gem_check_execbuffer(args)) { |
ff240199 | 828 | DRM_DEBUG("execbuf with invalid offset/length\n"); |
432e58ed CW |
829 | return -EINVAL; |
830 | } | |
831 | ||
832 | ret = validate_exec_list(exec, args->buffer_count); | |
54cf91dc CW |
833 | if (ret) |
834 | return ret; | |
835 | ||
54cf91dc CW |
836 | switch (args->flags & I915_EXEC_RING_MASK) { |
837 | case I915_EXEC_DEFAULT: | |
838 | case I915_EXEC_RENDER: | |
1ec14ad3 | 839 | ring = &dev_priv->ring[RCS]; |
54cf91dc CW |
840 | break; |
841 | case I915_EXEC_BSD: | |
1ec14ad3 | 842 | ring = &dev_priv->ring[VCS]; |
6e0a69db BW |
843 | if (ctx_id != 0) { |
844 | DRM_DEBUG("Ring %s doesn't support contexts\n", | |
845 | ring->name); | |
846 | return -EPERM; | |
847 | } | |
54cf91dc CW |
848 | break; |
849 | case I915_EXEC_BLT: | |
1ec14ad3 | 850 | ring = &dev_priv->ring[BCS]; |
6e0a69db BW |
851 | if (ctx_id != 0) { |
852 | DRM_DEBUG("Ring %s doesn't support contexts\n", | |
853 | ring->name); | |
854 | return -EPERM; | |
855 | } | |
54cf91dc CW |
856 | break; |
857 | default: | |
ff240199 | 858 | DRM_DEBUG("execbuf with unknown ring: %d\n", |
54cf91dc CW |
859 | (int)(args->flags & I915_EXEC_RING_MASK)); |
860 | return -EINVAL; | |
861 | } | |
a15817cf CW |
862 | if (!intel_ring_initialized(ring)) { |
863 | DRM_DEBUG("execbuf with invalid ring: %d\n", | |
864 | (int)(args->flags & I915_EXEC_RING_MASK)); | |
865 | return -EINVAL; | |
866 | } | |
54cf91dc | 867 | |
72bfa19c | 868 | mode = args->flags & I915_EXEC_CONSTANTS_MASK; |
84f9f938 | 869 | mask = I915_EXEC_CONSTANTS_MASK; |
72bfa19c CW |
870 | switch (mode) { |
871 | case I915_EXEC_CONSTANTS_REL_GENERAL: | |
872 | case I915_EXEC_CONSTANTS_ABSOLUTE: | |
873 | case I915_EXEC_CONSTANTS_REL_SURFACE: | |
874 | if (ring == &dev_priv->ring[RCS] && | |
875 | mode != dev_priv->relative_constants_mode) { | |
876 | if (INTEL_INFO(dev)->gen < 4) | |
877 | return -EINVAL; | |
878 | ||
879 | if (INTEL_INFO(dev)->gen > 5 && | |
880 | mode == I915_EXEC_CONSTANTS_REL_SURFACE) | |
881 | return -EINVAL; | |
84f9f938 BW |
882 | |
883 | /* The HW changed the meaning on this bit on gen6 */ | |
884 | if (INTEL_INFO(dev)->gen >= 6) | |
885 | mask &= ~I915_EXEC_CONSTANTS_REL_SURFACE; | |
72bfa19c CW |
886 | } |
887 | break; | |
888 | default: | |
ff240199 | 889 | DRM_DEBUG("execbuf with unknown constants: %d\n", mode); |
72bfa19c CW |
890 | return -EINVAL; |
891 | } | |
892 | ||
54cf91dc | 893 | if (args->buffer_count < 1) { |
ff240199 | 894 | DRM_DEBUG("execbuf with %d buffers\n", args->buffer_count); |
54cf91dc CW |
895 | return -EINVAL; |
896 | } | |
54cf91dc CW |
897 | |
898 | if (args->num_cliprects != 0) { | |
1ec14ad3 | 899 | if (ring != &dev_priv->ring[RCS]) { |
ff240199 | 900 | DRM_DEBUG("clip rectangles are only valid with the render ring\n"); |
c4e7a414 CW |
901 | return -EINVAL; |
902 | } | |
903 | ||
6ebebc92 DV |
904 | if (INTEL_INFO(dev)->gen >= 5) { |
905 | DRM_DEBUG("clip rectangles are only valid on pre-gen5\n"); | |
906 | return -EINVAL; | |
907 | } | |
908 | ||
44afb3a0 XW |
909 | if (args->num_cliprects > UINT_MAX / sizeof(*cliprects)) { |
910 | DRM_DEBUG("execbuf with %u cliprects\n", | |
911 | args->num_cliprects); | |
912 | return -EINVAL; | |
913 | } | |
5e13a0c5 | 914 | |
432e58ed | 915 | cliprects = kmalloc(args->num_cliprects * sizeof(*cliprects), |
54cf91dc CW |
916 | GFP_KERNEL); |
917 | if (cliprects == NULL) { | |
918 | ret = -ENOMEM; | |
919 | goto pre_mutex_err; | |
920 | } | |
921 | ||
432e58ed CW |
922 | if (copy_from_user(cliprects, |
923 | (struct drm_clip_rect __user *)(uintptr_t) | |
924 | args->cliprects_ptr, | |
925 | sizeof(*cliprects)*args->num_cliprects)) { | |
54cf91dc CW |
926 | ret = -EFAULT; |
927 | goto pre_mutex_err; | |
928 | } | |
929 | } | |
930 | ||
54cf91dc CW |
931 | ret = i915_mutex_lock_interruptible(dev); |
932 | if (ret) | |
933 | goto pre_mutex_err; | |
934 | ||
935 | if (dev_priv->mm.suspended) { | |
936 | mutex_unlock(&dev->struct_mutex); | |
937 | ret = -EBUSY; | |
938 | goto pre_mutex_err; | |
939 | } | |
940 | ||
67731b87 CW |
941 | eb = eb_create(args->buffer_count); |
942 | if (eb == NULL) { | |
943 | mutex_unlock(&dev->struct_mutex); | |
944 | ret = -ENOMEM; | |
945 | goto pre_mutex_err; | |
946 | } | |
947 | ||
54cf91dc | 948 | /* Look up object handles */ |
432e58ed | 949 | INIT_LIST_HEAD(&objects); |
54cf91dc CW |
950 | for (i = 0; i < args->buffer_count; i++) { |
951 | struct drm_i915_gem_object *obj; | |
952 | ||
432e58ed CW |
953 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, |
954 | exec[i].handle)); | |
c8725226 | 955 | if (&obj->base == NULL) { |
ff240199 | 956 | DRM_DEBUG("Invalid object handle %d at index %d\n", |
432e58ed | 957 | exec[i].handle, i); |
54cf91dc | 958 | /* prevent error path from reading uninitialized data */ |
54cf91dc CW |
959 | ret = -ENOENT; |
960 | goto err; | |
961 | } | |
54cf91dc | 962 | |
432e58ed | 963 | if (!list_empty(&obj->exec_list)) { |
ff240199 | 964 | DRM_DEBUG("Object %p [handle %d, index %d] appears more than once in object list\n", |
432e58ed | 965 | obj, exec[i].handle, i); |
54cf91dc CW |
966 | ret = -EINVAL; |
967 | goto err; | |
968 | } | |
432e58ed CW |
969 | |
970 | list_add_tail(&obj->exec_list, &objects); | |
67731b87 | 971 | obj->exec_handle = exec[i].handle; |
6fe4f140 | 972 | obj->exec_entry = &exec[i]; |
67731b87 | 973 | eb_add_object(eb, obj); |
54cf91dc CW |
974 | } |
975 | ||
6fe4f140 CW |
976 | /* take note of the batch buffer before we might reorder the lists */ |
977 | batch_obj = list_entry(objects.prev, | |
978 | struct drm_i915_gem_object, | |
979 | exec_list); | |
980 | ||
54cf91dc | 981 | /* Move the objects en-masse into the GTT, evicting if necessary. */ |
6fe4f140 | 982 | ret = i915_gem_execbuffer_reserve(ring, file, &objects); |
54cf91dc CW |
983 | if (ret) |
984 | goto err; | |
985 | ||
986 | /* The objects are in their final locations, apply the relocations. */ | |
6fe4f140 | 987 | ret = i915_gem_execbuffer_relocate(dev, eb, &objects); |
54cf91dc CW |
988 | if (ret) { |
989 | if (ret == -EFAULT) { | |
d9e86c0e | 990 | ret = i915_gem_execbuffer_relocate_slow(dev, file, ring, |
67731b87 CW |
991 | &objects, eb, |
992 | exec, | |
54cf91dc CW |
993 | args->buffer_count); |
994 | BUG_ON(!mutex_is_locked(&dev->struct_mutex)); | |
995 | } | |
996 | if (ret) | |
997 | goto err; | |
998 | } | |
999 | ||
1000 | /* Set the pending read domains for the batch buffer to COMMAND */ | |
54cf91dc | 1001 | if (batch_obj->base.pending_write_domain) { |
ff240199 | 1002 | DRM_DEBUG("Attempting to use self-modifying batch buffer\n"); |
54cf91dc CW |
1003 | ret = -EINVAL; |
1004 | goto err; | |
1005 | } | |
1006 | batch_obj->base.pending_read_domains |= I915_GEM_DOMAIN_COMMAND; | |
1007 | ||
432e58ed CW |
1008 | ret = i915_gem_execbuffer_move_to_gpu(ring, &objects); |
1009 | if (ret) | |
54cf91dc | 1010 | goto err; |
54cf91dc | 1011 | |
db53a302 | 1012 | seqno = i915_gem_next_request_seqno(ring); |
076e2c0e | 1013 | for (i = 0; i < ARRAY_SIZE(ring->sync_seqno); i++) { |
1ec14ad3 CW |
1014 | if (seqno < ring->sync_seqno[i]) { |
1015 | /* The GPU can not handle its semaphore value wrapping, | |
1016 | * so every billion or so execbuffers, we need to stall | |
1017 | * the GPU in order to reset the counters. | |
1018 | */ | |
b2da9fe5 | 1019 | ret = i915_gpu_idle(dev); |
1ec14ad3 CW |
1020 | if (ret) |
1021 | goto err; | |
b2da9fe5 | 1022 | i915_gem_retire_requests(dev); |
1ec14ad3 CW |
1023 | |
1024 | BUG_ON(ring->sync_seqno[i]); | |
1025 | } | |
1026 | } | |
1027 | ||
0da5cec1 EA |
1028 | ret = i915_switch_context(ring, file, ctx_id); |
1029 | if (ret) | |
1030 | goto err; | |
1031 | ||
e2971bda BW |
1032 | if (ring == &dev_priv->ring[RCS] && |
1033 | mode != dev_priv->relative_constants_mode) { | |
1034 | ret = intel_ring_begin(ring, 4); | |
1035 | if (ret) | |
1036 | goto err; | |
1037 | ||
1038 | intel_ring_emit(ring, MI_NOOP); | |
1039 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); | |
1040 | intel_ring_emit(ring, INSTPM); | |
84f9f938 | 1041 | intel_ring_emit(ring, mask << 16 | mode); |
e2971bda BW |
1042 | intel_ring_advance(ring); |
1043 | ||
1044 | dev_priv->relative_constants_mode = mode; | |
1045 | } | |
1046 | ||
ae662d31 EA |
1047 | if (args->flags & I915_EXEC_GEN7_SOL_RESET) { |
1048 | ret = i915_reset_gen7_sol_offsets(dev, ring); | |
1049 | if (ret) | |
1050 | goto err; | |
1051 | } | |
1052 | ||
db53a302 CW |
1053 | trace_i915_gem_ring_dispatch(ring, seqno); |
1054 | ||
c4e7a414 CW |
1055 | exec_start = batch_obj->gtt_offset + args->batch_start_offset; |
1056 | exec_len = args->batch_len; | |
1057 | if (cliprects) { | |
1058 | for (i = 0; i < args->num_cliprects; i++) { | |
1059 | ret = i915_emit_box(dev, &cliprects[i], | |
1060 | args->DR1, args->DR4); | |
1061 | if (ret) | |
1062 | goto err; | |
1063 | ||
1064 | ret = ring->dispatch_execbuffer(ring, | |
1065 | exec_start, exec_len); | |
1066 | if (ret) | |
1067 | goto err; | |
1068 | } | |
1069 | } else { | |
1070 | ret = ring->dispatch_execbuffer(ring, exec_start, exec_len); | |
1071 | if (ret) | |
1072 | goto err; | |
1073 | } | |
54cf91dc | 1074 | |
1ec14ad3 | 1075 | i915_gem_execbuffer_move_to_active(&objects, ring, seqno); |
432e58ed | 1076 | i915_gem_execbuffer_retire_commands(dev, file, ring); |
54cf91dc CW |
1077 | |
1078 | err: | |
67731b87 | 1079 | eb_destroy(eb); |
432e58ed CW |
1080 | while (!list_empty(&objects)) { |
1081 | struct drm_i915_gem_object *obj; | |
1082 | ||
1083 | obj = list_first_entry(&objects, | |
1084 | struct drm_i915_gem_object, | |
1085 | exec_list); | |
1086 | list_del_init(&obj->exec_list); | |
1087 | drm_gem_object_unreference(&obj->base); | |
54cf91dc CW |
1088 | } |
1089 | ||
1090 | mutex_unlock(&dev->struct_mutex); | |
1091 | ||
1092 | pre_mutex_err: | |
54cf91dc | 1093 | kfree(cliprects); |
54cf91dc CW |
1094 | return ret; |
1095 | } | |
1096 | ||
1097 | /* | |
1098 | * Legacy execbuffer just creates an exec2 list from the original exec object | |
1099 | * list array and passes it to the real function. | |
1100 | */ | |
1101 | int | |
1102 | i915_gem_execbuffer(struct drm_device *dev, void *data, | |
1103 | struct drm_file *file) | |
1104 | { | |
1105 | struct drm_i915_gem_execbuffer *args = data; | |
1106 | struct drm_i915_gem_execbuffer2 exec2; | |
1107 | struct drm_i915_gem_exec_object *exec_list = NULL; | |
1108 | struct drm_i915_gem_exec_object2 *exec2_list = NULL; | |
1109 | int ret, i; | |
1110 | ||
54cf91dc | 1111 | if (args->buffer_count < 1) { |
ff240199 | 1112 | DRM_DEBUG("execbuf with %d buffers\n", args->buffer_count); |
54cf91dc CW |
1113 | return -EINVAL; |
1114 | } | |
1115 | ||
1116 | /* Copy in the exec list from userland */ | |
1117 | exec_list = drm_malloc_ab(sizeof(*exec_list), args->buffer_count); | |
1118 | exec2_list = drm_malloc_ab(sizeof(*exec2_list), args->buffer_count); | |
1119 | if (exec_list == NULL || exec2_list == NULL) { | |
ff240199 | 1120 | DRM_DEBUG("Failed to allocate exec list for %d buffers\n", |
54cf91dc CW |
1121 | args->buffer_count); |
1122 | drm_free_large(exec_list); | |
1123 | drm_free_large(exec2_list); | |
1124 | return -ENOMEM; | |
1125 | } | |
1126 | ret = copy_from_user(exec_list, | |
1127 | (struct drm_i915_relocation_entry __user *) | |
1128 | (uintptr_t) args->buffers_ptr, | |
1129 | sizeof(*exec_list) * args->buffer_count); | |
1130 | if (ret != 0) { | |
ff240199 | 1131 | DRM_DEBUG("copy %d exec entries failed %d\n", |
54cf91dc CW |
1132 | args->buffer_count, ret); |
1133 | drm_free_large(exec_list); | |
1134 | drm_free_large(exec2_list); | |
1135 | return -EFAULT; | |
1136 | } | |
1137 | ||
1138 | for (i = 0; i < args->buffer_count; i++) { | |
1139 | exec2_list[i].handle = exec_list[i].handle; | |
1140 | exec2_list[i].relocation_count = exec_list[i].relocation_count; | |
1141 | exec2_list[i].relocs_ptr = exec_list[i].relocs_ptr; | |
1142 | exec2_list[i].alignment = exec_list[i].alignment; | |
1143 | exec2_list[i].offset = exec_list[i].offset; | |
1144 | if (INTEL_INFO(dev)->gen < 4) | |
1145 | exec2_list[i].flags = EXEC_OBJECT_NEEDS_FENCE; | |
1146 | else | |
1147 | exec2_list[i].flags = 0; | |
1148 | } | |
1149 | ||
1150 | exec2.buffers_ptr = args->buffers_ptr; | |
1151 | exec2.buffer_count = args->buffer_count; | |
1152 | exec2.batch_start_offset = args->batch_start_offset; | |
1153 | exec2.batch_len = args->batch_len; | |
1154 | exec2.DR1 = args->DR1; | |
1155 | exec2.DR4 = args->DR4; | |
1156 | exec2.num_cliprects = args->num_cliprects; | |
1157 | exec2.cliprects_ptr = args->cliprects_ptr; | |
1158 | exec2.flags = I915_EXEC_RENDER; | |
6e0a69db | 1159 | i915_execbuffer2_set_context_id(exec2, 0); |
54cf91dc CW |
1160 | |
1161 | ret = i915_gem_do_execbuffer(dev, data, file, &exec2, exec2_list); | |
1162 | if (!ret) { | |
1163 | /* Copy the new buffer offsets back to the user's exec list. */ | |
1164 | for (i = 0; i < args->buffer_count; i++) | |
1165 | exec_list[i].offset = exec2_list[i].offset; | |
1166 | /* ... and back out to userspace */ | |
1167 | ret = copy_to_user((struct drm_i915_relocation_entry __user *) | |
1168 | (uintptr_t) args->buffers_ptr, | |
1169 | exec_list, | |
1170 | sizeof(*exec_list) * args->buffer_count); | |
1171 | if (ret) { | |
1172 | ret = -EFAULT; | |
ff240199 | 1173 | DRM_DEBUG("failed to copy %d exec entries " |
54cf91dc CW |
1174 | "back to user (%d)\n", |
1175 | args->buffer_count, ret); | |
1176 | } | |
1177 | } | |
1178 | ||
1179 | drm_free_large(exec_list); | |
1180 | drm_free_large(exec2_list); | |
1181 | return ret; | |
1182 | } | |
1183 | ||
1184 | int | |
1185 | i915_gem_execbuffer2(struct drm_device *dev, void *data, | |
1186 | struct drm_file *file) | |
1187 | { | |
1188 | struct drm_i915_gem_execbuffer2 *args = data; | |
1189 | struct drm_i915_gem_exec_object2 *exec2_list = NULL; | |
1190 | int ret; | |
1191 | ||
ed8cd3b2 XW |
1192 | if (args->buffer_count < 1 || |
1193 | args->buffer_count > UINT_MAX / sizeof(*exec2_list)) { | |
ff240199 | 1194 | DRM_DEBUG("execbuf2 with %d buffers\n", args->buffer_count); |
54cf91dc CW |
1195 | return -EINVAL; |
1196 | } | |
1197 | ||
8408c282 CW |
1198 | exec2_list = kmalloc(sizeof(*exec2_list)*args->buffer_count, |
1199 | GFP_KERNEL | __GFP_NOWARN | __GFP_NORETRY); | |
1200 | if (exec2_list == NULL) | |
1201 | exec2_list = drm_malloc_ab(sizeof(*exec2_list), | |
1202 | args->buffer_count); | |
54cf91dc | 1203 | if (exec2_list == NULL) { |
ff240199 | 1204 | DRM_DEBUG("Failed to allocate exec list for %d buffers\n", |
54cf91dc CW |
1205 | args->buffer_count); |
1206 | return -ENOMEM; | |
1207 | } | |
1208 | ret = copy_from_user(exec2_list, | |
1209 | (struct drm_i915_relocation_entry __user *) | |
1210 | (uintptr_t) args->buffers_ptr, | |
1211 | sizeof(*exec2_list) * args->buffer_count); | |
1212 | if (ret != 0) { | |
ff240199 | 1213 | DRM_DEBUG("copy %d exec entries failed %d\n", |
54cf91dc CW |
1214 | args->buffer_count, ret); |
1215 | drm_free_large(exec2_list); | |
1216 | return -EFAULT; | |
1217 | } | |
1218 | ||
1219 | ret = i915_gem_do_execbuffer(dev, data, file, args, exec2_list); | |
1220 | if (!ret) { | |
1221 | /* Copy the new buffer offsets back to the user's exec list. */ | |
1222 | ret = copy_to_user((struct drm_i915_relocation_entry __user *) | |
1223 | (uintptr_t) args->buffers_ptr, | |
1224 | exec2_list, | |
1225 | sizeof(*exec2_list) * args->buffer_count); | |
1226 | if (ret) { | |
1227 | ret = -EFAULT; | |
ff240199 | 1228 | DRM_DEBUG("failed to copy %d exec entries " |
54cf91dc CW |
1229 | "back to user (%d)\n", |
1230 | args->buffer_count, ret); | |
1231 | } | |
1232 | } | |
1233 | ||
1234 | drm_free_large(exec2_list); | |
1235 | return ret; | |
1236 | } |