drm/i915/gen8: Add dynamic page trace events
[deliverable/linux.git] / drivers / gpu / drm / i915 / i915_gem_gtt.c
CommitLineData
76aaf220
DV
1/*
2 * Copyright © 2010 Daniel Vetter
c4ac524c 3 * Copyright © 2011-2014 Intel Corporation
76aaf220
DV
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
22 * IN THE SOFTWARE.
23 *
24 */
25
0e46ce2e 26#include <linux/seq_file.h>
760285e7
DH
27#include <drm/drmP.h>
28#include <drm/i915_drm.h>
76aaf220 29#include "i915_drv.h"
5dda8fa3 30#include "i915_vgpu.h"
76aaf220
DV
31#include "i915_trace.h"
32#include "intel_drv.h"
33
45f8f69a
TU
34/**
35 * DOC: Global GTT views
36 *
37 * Background and previous state
38 *
39 * Historically objects could exists (be bound) in global GTT space only as
40 * singular instances with a view representing all of the object's backing pages
41 * in a linear fashion. This view will be called a normal view.
42 *
43 * To support multiple views of the same object, where the number of mapped
44 * pages is not equal to the backing store, or where the layout of the pages
45 * is not linear, concept of a GGTT view was added.
46 *
47 * One example of an alternative view is a stereo display driven by a single
48 * image. In this case we would have a framebuffer looking like this
49 * (2x2 pages):
50 *
51 * 12
52 * 34
53 *
54 * Above would represent a normal GGTT view as normally mapped for GPU or CPU
55 * rendering. In contrast, fed to the display engine would be an alternative
56 * view which could look something like this:
57 *
58 * 1212
59 * 3434
60 *
61 * In this example both the size and layout of pages in the alternative view is
62 * different from the normal view.
63 *
64 * Implementation and usage
65 *
66 * GGTT views are implemented using VMAs and are distinguished via enum
67 * i915_ggtt_view_type and struct i915_ggtt_view.
68 *
69 * A new flavour of core GEM functions which work with GGTT bound objects were
ec7adb6e
JL
70 * added with the _ggtt_ infix, and sometimes with _view postfix to avoid
71 * renaming in large amounts of code. They take the struct i915_ggtt_view
72 * parameter encapsulating all metadata required to implement a view.
45f8f69a
TU
73 *
74 * As a helper for callers which are only interested in the normal view,
75 * globally const i915_ggtt_view_normal singleton instance exists. All old core
76 * GEM API functions, the ones not taking the view parameter, are operating on,
77 * or with the normal GGTT view.
78 *
79 * Code wanting to add or use a new GGTT view needs to:
80 *
81 * 1. Add a new enum with a suitable name.
82 * 2. Extend the metadata in the i915_ggtt_view structure if required.
83 * 3. Add support to i915_get_vma_pages().
84 *
85 * New views are required to build a scatter-gather table from within the
86 * i915_get_vma_pages function. This table is stored in the vma.ggtt_view and
87 * exists for the lifetime of an VMA.
88 *
89 * Core API is designed to have copy semantics which means that passed in
90 * struct i915_ggtt_view does not need to be persistent (left around after
91 * calling the core API functions).
92 *
93 */
94
70b9f6f8
DV
95static int
96i915_get_ggtt_vma_pages(struct i915_vma *vma);
97
fe14d5f4 98const struct i915_ggtt_view i915_ggtt_view_normal;
9abc4648
JL
99const struct i915_ggtt_view i915_ggtt_view_rotated = {
100 .type = I915_GGTT_VIEW_ROTATED
101};
fe14d5f4 102
cfa7c862
DV
103static int sanitize_enable_ppgtt(struct drm_device *dev, int enable_ppgtt)
104{
1893a71b
CW
105 bool has_aliasing_ppgtt;
106 bool has_full_ppgtt;
107
108 has_aliasing_ppgtt = INTEL_INFO(dev)->gen >= 6;
109 has_full_ppgtt = INTEL_INFO(dev)->gen >= 7;
1893a71b 110
71ba2d64
YZ
111 if (intel_vgpu_active(dev))
112 has_full_ppgtt = false; /* emulation is too hard */
113
70ee45e1
DL
114 /*
115 * We don't allow disabling PPGTT for gen9+ as it's a requirement for
116 * execlists, the sole mechanism available to submit work.
117 */
118 if (INTEL_INFO(dev)->gen < 9 &&
119 (enable_ppgtt == 0 || !has_aliasing_ppgtt))
cfa7c862
DV
120 return 0;
121
122 if (enable_ppgtt == 1)
123 return 1;
124
1893a71b 125 if (enable_ppgtt == 2 && has_full_ppgtt)
cfa7c862
DV
126 return 2;
127
93a25a9e
DV
128#ifdef CONFIG_INTEL_IOMMU
129 /* Disable ppgtt on SNB if VT-d is on. */
130 if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped) {
131 DRM_INFO("Disabling PPGTT because VT-d is on\n");
cfa7c862 132 return 0;
93a25a9e
DV
133 }
134#endif
135
62942ed7 136 /* Early VLV doesn't have this */
ca2aed6c
VS
137 if (IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) &&
138 dev->pdev->revision < 0xb) {
62942ed7
JB
139 DRM_DEBUG_DRIVER("disabling PPGTT on pre-B3 step VLV\n");
140 return 0;
141 }
142
2f82bbdf
MT
143 if (INTEL_INFO(dev)->gen >= 8 && i915.enable_execlists)
144 return 2;
145 else
146 return has_aliasing_ppgtt ? 1 : 0;
93a25a9e
DV
147}
148
70b9f6f8
DV
149static int ppgtt_bind_vma(struct i915_vma *vma,
150 enum i915_cache_level cache_level,
151 u32 unused)
47552659
DV
152{
153 u32 pte_flags = 0;
154
155 /* Currently applicable only to VLV */
156 if (vma->obj->gt_ro)
157 pte_flags |= PTE_READ_ONLY;
158
159 vma->vm->insert_entries(vma->vm, vma->obj->pages, vma->node.start,
160 cache_level, pte_flags);
70b9f6f8
DV
161
162 return 0;
47552659
DV
163}
164
165static void ppgtt_unbind_vma(struct i915_vma *vma)
166{
167 vma->vm->clear_range(vma->vm,
168 vma->node.start,
169 vma->obj->base.size,
170 true);
171}
6f65e29a 172
2c642b07
DV
173static gen8_pte_t gen8_pte_encode(dma_addr_t addr,
174 enum i915_cache_level level,
175 bool valid)
94ec8f61 176{
07749ef3 177 gen8_pte_t pte = valid ? _PAGE_PRESENT | _PAGE_RW : 0;
94ec8f61 178 pte |= addr;
63c42e56
BW
179
180 switch (level) {
181 case I915_CACHE_NONE:
fbe5d36e 182 pte |= PPAT_UNCACHED_INDEX;
63c42e56
BW
183 break;
184 case I915_CACHE_WT:
185 pte |= PPAT_DISPLAY_ELLC_INDEX;
186 break;
187 default:
188 pte |= PPAT_CACHED_INDEX;
189 break;
190 }
191
94ec8f61
BW
192 return pte;
193}
194
fe36f55d
MK
195static gen8_pde_t gen8_pde_encode(const dma_addr_t addr,
196 const enum i915_cache_level level)
b1fe6673 197{
07749ef3 198 gen8_pde_t pde = _PAGE_PRESENT | _PAGE_RW;
b1fe6673
BW
199 pde |= addr;
200 if (level != I915_CACHE_NONE)
201 pde |= PPAT_CACHED_PDE_INDEX;
202 else
203 pde |= PPAT_UNCACHED_INDEX;
204 return pde;
205}
206
07749ef3
MT
207static gen6_pte_t snb_pte_encode(dma_addr_t addr,
208 enum i915_cache_level level,
209 bool valid, u32 unused)
54d12527 210{
07749ef3 211 gen6_pte_t pte = valid ? GEN6_PTE_VALID : 0;
54d12527 212 pte |= GEN6_PTE_ADDR_ENCODE(addr);
e7210c3c
BW
213
214 switch (level) {
350ec881
CW
215 case I915_CACHE_L3_LLC:
216 case I915_CACHE_LLC:
217 pte |= GEN6_PTE_CACHE_LLC;
218 break;
219 case I915_CACHE_NONE:
220 pte |= GEN6_PTE_UNCACHED;
221 break;
222 default:
5f77eeb0 223 MISSING_CASE(level);
350ec881
CW
224 }
225
226 return pte;
227}
228
07749ef3
MT
229static gen6_pte_t ivb_pte_encode(dma_addr_t addr,
230 enum i915_cache_level level,
231 bool valid, u32 unused)
350ec881 232{
07749ef3 233 gen6_pte_t pte = valid ? GEN6_PTE_VALID : 0;
350ec881
CW
234 pte |= GEN6_PTE_ADDR_ENCODE(addr);
235
236 switch (level) {
237 case I915_CACHE_L3_LLC:
238 pte |= GEN7_PTE_CACHE_L3_LLC;
e7210c3c
BW
239 break;
240 case I915_CACHE_LLC:
241 pte |= GEN6_PTE_CACHE_LLC;
242 break;
243 case I915_CACHE_NONE:
9119708c 244 pte |= GEN6_PTE_UNCACHED;
e7210c3c
BW
245 break;
246 default:
5f77eeb0 247 MISSING_CASE(level);
e7210c3c
BW
248 }
249
54d12527
BW
250 return pte;
251}
252
07749ef3
MT
253static gen6_pte_t byt_pte_encode(dma_addr_t addr,
254 enum i915_cache_level level,
255 bool valid, u32 flags)
93c34e70 256{
07749ef3 257 gen6_pte_t pte = valid ? GEN6_PTE_VALID : 0;
93c34e70
KG
258 pte |= GEN6_PTE_ADDR_ENCODE(addr);
259
24f3a8cf
AG
260 if (!(flags & PTE_READ_ONLY))
261 pte |= BYT_PTE_WRITEABLE;
93c34e70
KG
262
263 if (level != I915_CACHE_NONE)
264 pte |= BYT_PTE_SNOOPED_BY_CPU_CACHES;
265
266 return pte;
267}
268
07749ef3
MT
269static gen6_pte_t hsw_pte_encode(dma_addr_t addr,
270 enum i915_cache_level level,
271 bool valid, u32 unused)
9119708c 272{
07749ef3 273 gen6_pte_t pte = valid ? GEN6_PTE_VALID : 0;
0d8ff15e 274 pte |= HSW_PTE_ADDR_ENCODE(addr);
9119708c
KG
275
276 if (level != I915_CACHE_NONE)
87a6b688 277 pte |= HSW_WB_LLC_AGE3;
9119708c
KG
278
279 return pte;
280}
281
07749ef3
MT
282static gen6_pte_t iris_pte_encode(dma_addr_t addr,
283 enum i915_cache_level level,
284 bool valid, u32 unused)
4d15c145 285{
07749ef3 286 gen6_pte_t pte = valid ? GEN6_PTE_VALID : 0;
4d15c145
BW
287 pte |= HSW_PTE_ADDR_ENCODE(addr);
288
651d794f
CW
289 switch (level) {
290 case I915_CACHE_NONE:
291 break;
292 case I915_CACHE_WT:
c51e9701 293 pte |= HSW_WT_ELLC_LLC_AGE3;
651d794f
CW
294 break;
295 default:
c51e9701 296 pte |= HSW_WB_ELLC_LLC_AGE3;
651d794f
CW
297 break;
298 }
4d15c145
BW
299
300 return pte;
301}
302
c114f76a
MK
303static int __setup_page_dma(struct drm_device *dev,
304 struct i915_page_dma *p, gfp_t flags)
678d96fb
BW
305{
306 struct device *device = &dev->pdev->dev;
307
c114f76a 308 p->page = alloc_page(flags);
44159ddb
MK
309 if (!p->page)
310 return -ENOMEM;
678d96fb 311
44159ddb
MK
312 p->daddr = dma_map_page(device,
313 p->page, 0, 4096, PCI_DMA_BIDIRECTIONAL);
678d96fb 314
44159ddb
MK
315 if (dma_mapping_error(device, p->daddr)) {
316 __free_page(p->page);
317 return -EINVAL;
318 }
1266cdb1
MT
319
320 return 0;
678d96fb
BW
321}
322
c114f76a
MK
323static int setup_page_dma(struct drm_device *dev, struct i915_page_dma *p)
324{
325 return __setup_page_dma(dev, p, GFP_KERNEL);
326}
327
44159ddb 328static void cleanup_page_dma(struct drm_device *dev, struct i915_page_dma *p)
06fda602 329{
44159ddb 330 if (WARN_ON(!p->page))
06fda602 331 return;
678d96fb 332
44159ddb
MK
333 dma_unmap_page(&dev->pdev->dev, p->daddr, 4096, PCI_DMA_BIDIRECTIONAL);
334 __free_page(p->page);
335 memset(p, 0, sizeof(*p));
336}
337
d1c54acd 338static void *kmap_page_dma(struct i915_page_dma *p)
73eeea53 339{
d1c54acd
MK
340 return kmap_atomic(p->page);
341}
73eeea53 342
d1c54acd
MK
343/* We use the flushing unmap only with ppgtt structures:
344 * page directories, page tables and scratch pages.
345 */
346static void kunmap_page_dma(struct drm_device *dev, void *vaddr)
347{
73eeea53
MK
348 /* There are only few exceptions for gen >=6. chv and bxt.
349 * And we are not sure about the latter so play safe for now.
350 */
351 if (IS_CHERRYVIEW(dev) || IS_BROXTON(dev))
352 drm_clflush_virt_range(vaddr, PAGE_SIZE);
353
354 kunmap_atomic(vaddr);
355}
356
567047be 357#define kmap_px(px) kmap_page_dma(px_base(px))
d1c54acd
MK
358#define kunmap_px(ppgtt, vaddr) kunmap_page_dma((ppgtt)->base.dev, (vaddr))
359
567047be
MK
360#define setup_px(dev, px) setup_page_dma((dev), px_base(px))
361#define cleanup_px(dev, px) cleanup_page_dma((dev), px_base(px))
362#define fill_px(dev, px, v) fill_page_dma((dev), px_base(px), (v))
363#define fill32_px(dev, px, v) fill_page_dma_32((dev), px_base(px), (v))
364
d1c54acd
MK
365static void fill_page_dma(struct drm_device *dev, struct i915_page_dma *p,
366 const uint64_t val)
367{
368 int i;
369 uint64_t * const vaddr = kmap_page_dma(p);
370
371 for (i = 0; i < 512; i++)
372 vaddr[i] = val;
373
374 kunmap_page_dma(dev, vaddr);
375}
376
73eeea53
MK
377static void fill_page_dma_32(struct drm_device *dev, struct i915_page_dma *p,
378 const uint32_t val32)
379{
380 uint64_t v = val32;
381
382 v = v << 32 | val32;
383
384 fill_page_dma(dev, p, v);
385}
386
4ad2af1e
MK
387static struct i915_page_scratch *alloc_scratch_page(struct drm_device *dev)
388{
389 struct i915_page_scratch *sp;
390 int ret;
391
392 sp = kzalloc(sizeof(*sp), GFP_KERNEL);
393 if (sp == NULL)
394 return ERR_PTR(-ENOMEM);
395
396 ret = __setup_page_dma(dev, px_base(sp), GFP_DMA32 | __GFP_ZERO);
397 if (ret) {
398 kfree(sp);
399 return ERR_PTR(ret);
400 }
401
402 set_pages_uc(px_page(sp), 1);
403
404 return sp;
405}
406
407static void free_scratch_page(struct drm_device *dev,
408 struct i915_page_scratch *sp)
409{
410 set_pages_wb(px_page(sp), 1);
411
412 cleanup_px(dev, sp);
413 kfree(sp);
414}
415
8a1ebd74 416static struct i915_page_table *alloc_pt(struct drm_device *dev)
06fda602 417{
ec565b3c 418 struct i915_page_table *pt;
678d96fb
BW
419 const size_t count = INTEL_INFO(dev)->gen >= 8 ?
420 GEN8_PTES : GEN6_PTES;
421 int ret = -ENOMEM;
06fda602
BW
422
423 pt = kzalloc(sizeof(*pt), GFP_KERNEL);
424 if (!pt)
425 return ERR_PTR(-ENOMEM);
426
678d96fb
BW
427 pt->used_ptes = kcalloc(BITS_TO_LONGS(count), sizeof(*pt->used_ptes),
428 GFP_KERNEL);
429
430 if (!pt->used_ptes)
431 goto fail_bitmap;
432
567047be 433 ret = setup_px(dev, pt);
678d96fb 434 if (ret)
44159ddb 435 goto fail_page_m;
06fda602
BW
436
437 return pt;
678d96fb 438
44159ddb 439fail_page_m:
678d96fb
BW
440 kfree(pt->used_ptes);
441fail_bitmap:
442 kfree(pt);
443
444 return ERR_PTR(ret);
06fda602
BW
445}
446
2e906bea 447static void free_pt(struct drm_device *dev, struct i915_page_table *pt)
06fda602 448{
2e906bea
MK
449 cleanup_px(dev, pt);
450 kfree(pt->used_ptes);
451 kfree(pt);
452}
453
454static void gen8_initialize_pt(struct i915_address_space *vm,
455 struct i915_page_table *pt)
456{
457 gen8_pte_t scratch_pte;
458
459 scratch_pte = gen8_pte_encode(px_dma(vm->scratch_page),
460 I915_CACHE_LLC, true);
461
462 fill_px(vm->dev, pt, scratch_pte);
463}
464
465static void gen6_initialize_pt(struct i915_address_space *vm,
466 struct i915_page_table *pt)
467{
468 gen6_pte_t scratch_pte;
469
470 WARN_ON(px_dma(vm->scratch_page) == 0);
471
472 scratch_pte = vm->pte_encode(px_dma(vm->scratch_page),
473 I915_CACHE_LLC, true, 0);
474
475 fill32_px(vm->dev, pt, scratch_pte);
06fda602
BW
476}
477
8a1ebd74 478static struct i915_page_directory *alloc_pd(struct drm_device *dev)
06fda602 479{
ec565b3c 480 struct i915_page_directory *pd;
33c8819f 481 int ret = -ENOMEM;
06fda602
BW
482
483 pd = kzalloc(sizeof(*pd), GFP_KERNEL);
484 if (!pd)
485 return ERR_PTR(-ENOMEM);
486
33c8819f
MT
487 pd->used_pdes = kcalloc(BITS_TO_LONGS(I915_PDES),
488 sizeof(*pd->used_pdes), GFP_KERNEL);
489 if (!pd->used_pdes)
a08e111a 490 goto fail_bitmap;
33c8819f 491
567047be 492 ret = setup_px(dev, pd);
33c8819f 493 if (ret)
a08e111a 494 goto fail_page_m;
e5815a2e 495
06fda602 496 return pd;
33c8819f 497
a08e111a 498fail_page_m:
33c8819f 499 kfree(pd->used_pdes);
a08e111a 500fail_bitmap:
33c8819f
MT
501 kfree(pd);
502
503 return ERR_PTR(ret);
06fda602
BW
504}
505
2e906bea
MK
506static void free_pd(struct drm_device *dev, struct i915_page_directory *pd)
507{
508 if (px_page(pd)) {
509 cleanup_px(dev, pd);
510 kfree(pd->used_pdes);
511 kfree(pd);
512 }
513}
514
515static void gen8_initialize_pd(struct i915_address_space *vm,
516 struct i915_page_directory *pd)
517{
518 gen8_pde_t scratch_pde;
519
520 scratch_pde = gen8_pde_encode(px_dma(vm->scratch_pt), I915_CACHE_LLC);
521
522 fill_px(vm->dev, pd, scratch_pde);
523}
524
6ac18502
MT
525static int __pdp_init(struct drm_device *dev,
526 struct i915_page_directory_pointer *pdp)
527{
528 size_t pdpes = I915_PDPES_PER_PDP(dev);
529
530 pdp->used_pdpes = kcalloc(BITS_TO_LONGS(pdpes),
531 sizeof(unsigned long),
532 GFP_KERNEL);
533 if (!pdp->used_pdpes)
534 return -ENOMEM;
535
536 pdp->page_directory = kcalloc(pdpes, sizeof(*pdp->page_directory),
537 GFP_KERNEL);
538 if (!pdp->page_directory) {
539 kfree(pdp->used_pdpes);
540 /* the PDP might be the statically allocated top level. Keep it
541 * as clean as possible */
542 pdp->used_pdpes = NULL;
543 return -ENOMEM;
544 }
545
546 return 0;
547}
548
549static void __pdp_fini(struct i915_page_directory_pointer *pdp)
550{
551 kfree(pdp->used_pdpes);
552 kfree(pdp->page_directory);
553 pdp->page_directory = NULL;
554}
555
556static void free_pdp(struct drm_device *dev,
557 struct i915_page_directory_pointer *pdp)
558{
559 __pdp_fini(pdp);
560}
561
94e409c1 562/* Broadwell Page Directory Pointer Descriptors */
e85b26dc 563static int gen8_write_pdp(struct drm_i915_gem_request *req,
7cb6d7ac
MT
564 unsigned entry,
565 dma_addr_t addr)
94e409c1 566{
e85b26dc 567 struct intel_engine_cs *ring = req->ring;
94e409c1
BW
568 int ret;
569
570 BUG_ON(entry >= 4);
571
5fb9de1a 572 ret = intel_ring_begin(req, 6);
94e409c1
BW
573 if (ret)
574 return ret;
575
576 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
577 intel_ring_emit(ring, GEN8_RING_PDP_UDW(ring, entry));
7cb6d7ac 578 intel_ring_emit(ring, upper_32_bits(addr));
94e409c1
BW
579 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
580 intel_ring_emit(ring, GEN8_RING_PDP_LDW(ring, entry));
7cb6d7ac 581 intel_ring_emit(ring, lower_32_bits(addr));
94e409c1
BW
582 intel_ring_advance(ring);
583
584 return 0;
585}
586
eeb9488e 587static int gen8_mm_switch(struct i915_hw_ppgtt *ppgtt,
e85b26dc 588 struct drm_i915_gem_request *req)
94e409c1 589{
eeb9488e 590 int i, ret;
94e409c1 591
7cb6d7ac 592 for (i = GEN8_LEGACY_PDPES - 1; i >= 0; i--) {
d852c7bf
MK
593 const dma_addr_t pd_daddr = i915_page_dir_dma_addr(ppgtt, i);
594
e85b26dc 595 ret = gen8_write_pdp(req, i, pd_daddr);
eeb9488e
BW
596 if (ret)
597 return ret;
94e409c1 598 }
d595bd4b 599
eeb9488e 600 return 0;
94e409c1
BW
601}
602
f9b5b782
MT
603static void gen8_ppgtt_clear_pte_range(struct i915_address_space *vm,
604 struct i915_page_directory_pointer *pdp,
605 uint64_t start,
606 uint64_t length,
607 gen8_pte_t scratch_pte)
459108b8
BW
608{
609 struct i915_hw_ppgtt *ppgtt =
610 container_of(vm, struct i915_hw_ppgtt, base);
f9b5b782 611 gen8_pte_t *pt_vaddr;
7ad47cf2
BW
612 unsigned pdpe = start >> GEN8_PDPE_SHIFT & GEN8_PDPE_MASK;
613 unsigned pde = start >> GEN8_PDE_SHIFT & GEN8_PDE_MASK;
614 unsigned pte = start >> GEN8_PTE_SHIFT & GEN8_PTE_MASK;
782f1495 615 unsigned num_entries = length >> PAGE_SHIFT;
459108b8
BW
616 unsigned last_pte, i;
617
f9b5b782
MT
618 if (WARN_ON(!pdp))
619 return;
459108b8
BW
620
621 while (num_entries) {
ec565b3c
MT
622 struct i915_page_directory *pd;
623 struct i915_page_table *pt;
06fda602 624
d4ec9da0 625 if (WARN_ON(!pdp->page_directory[pdpe]))
00245266 626 break;
06fda602 627
d4ec9da0 628 pd = pdp->page_directory[pdpe];
06fda602
BW
629
630 if (WARN_ON(!pd->page_table[pde]))
00245266 631 break;
06fda602
BW
632
633 pt = pd->page_table[pde];
634
567047be 635 if (WARN_ON(!px_page(pt)))
00245266 636 break;
06fda602 637
7ad47cf2 638 last_pte = pte + num_entries;
07749ef3
MT
639 if (last_pte > GEN8_PTES)
640 last_pte = GEN8_PTES;
459108b8 641
d1c54acd 642 pt_vaddr = kmap_px(pt);
459108b8 643
7ad47cf2 644 for (i = pte; i < last_pte; i++) {
459108b8 645 pt_vaddr[i] = scratch_pte;
7ad47cf2
BW
646 num_entries--;
647 }
459108b8 648
d1c54acd 649 kunmap_px(ppgtt, pt);
459108b8 650
7ad47cf2 651 pte = 0;
07749ef3 652 if (++pde == I915_PDES) {
7ad47cf2
BW
653 pdpe++;
654 pde = 0;
655 }
459108b8
BW
656 }
657}
658
f9b5b782
MT
659static void gen8_ppgtt_clear_range(struct i915_address_space *vm,
660 uint64_t start,
661 uint64_t length,
662 bool use_scratch)
9df15b49
BW
663{
664 struct i915_hw_ppgtt *ppgtt =
665 container_of(vm, struct i915_hw_ppgtt, base);
d4ec9da0 666 struct i915_page_directory_pointer *pdp = &ppgtt->pdp; /* FIXME: 48b */
f9b5b782
MT
667
668 gen8_pte_t scratch_pte = gen8_pte_encode(px_dma(vm->scratch_page),
669 I915_CACHE_LLC, use_scratch);
670
671 gen8_ppgtt_clear_pte_range(vm, pdp, start, length, scratch_pte);
672}
673
674static void
675gen8_ppgtt_insert_pte_entries(struct i915_address_space *vm,
676 struct i915_page_directory_pointer *pdp,
677 struct sg_table *pages,
678 uint64_t start,
679 enum i915_cache_level cache_level)
680{
681 struct i915_hw_ppgtt *ppgtt =
682 container_of(vm, struct i915_hw_ppgtt, base);
07749ef3 683 gen8_pte_t *pt_vaddr;
7ad47cf2
BW
684 unsigned pdpe = start >> GEN8_PDPE_SHIFT & GEN8_PDPE_MASK;
685 unsigned pde = start >> GEN8_PDE_SHIFT & GEN8_PDE_MASK;
686 unsigned pte = start >> GEN8_PTE_SHIFT & GEN8_PTE_MASK;
9df15b49
BW
687 struct sg_page_iter sg_iter;
688
6f1cc993 689 pt_vaddr = NULL;
7ad47cf2 690
9df15b49 691 for_each_sg_page(pages->sgl, &sg_iter, pages->nents, 0) {
76643600 692 if (WARN_ON(pdpe >= GEN8_LEGACY_PDPES))
7ad47cf2
BW
693 break;
694
d7b3de91 695 if (pt_vaddr == NULL) {
d4ec9da0 696 struct i915_page_directory *pd = pdp->page_directory[pdpe];
ec565b3c 697 struct i915_page_table *pt = pd->page_table[pde];
d1c54acd 698 pt_vaddr = kmap_px(pt);
d7b3de91 699 }
9df15b49 700
7ad47cf2 701 pt_vaddr[pte] =
6f1cc993
CW
702 gen8_pte_encode(sg_page_iter_dma_address(&sg_iter),
703 cache_level, true);
07749ef3 704 if (++pte == GEN8_PTES) {
d1c54acd 705 kunmap_px(ppgtt, pt_vaddr);
6f1cc993 706 pt_vaddr = NULL;
07749ef3 707 if (++pde == I915_PDES) {
7ad47cf2
BW
708 pdpe++;
709 pde = 0;
710 }
711 pte = 0;
9df15b49
BW
712 }
713 }
d1c54acd
MK
714
715 if (pt_vaddr)
716 kunmap_px(ppgtt, pt_vaddr);
9df15b49
BW
717}
718
f9b5b782
MT
719static void gen8_ppgtt_insert_entries(struct i915_address_space *vm,
720 struct sg_table *pages,
721 uint64_t start,
722 enum i915_cache_level cache_level,
723 u32 unused)
724{
725 struct i915_hw_ppgtt *ppgtt =
726 container_of(vm, struct i915_hw_ppgtt, base);
727 struct i915_page_directory_pointer *pdp = &ppgtt->pdp; /* FIXME: 48b */
728
729 gen8_ppgtt_insert_pte_entries(vm, pdp, pages, start, cache_level);
730}
731
f37c0505
MT
732static void gen8_free_page_tables(struct drm_device *dev,
733 struct i915_page_directory *pd)
7ad47cf2
BW
734{
735 int i;
736
567047be 737 if (!px_page(pd))
7ad47cf2
BW
738 return;
739
33c8819f 740 for_each_set_bit(i, pd->used_pdes, I915_PDES) {
06fda602
BW
741 if (WARN_ON(!pd->page_table[i]))
742 continue;
7ad47cf2 743
a08e111a 744 free_pt(dev, pd->page_table[i]);
06fda602
BW
745 pd->page_table[i] = NULL;
746 }
d7b3de91
BW
747}
748
8776f02b
MK
749static int gen8_init_scratch(struct i915_address_space *vm)
750{
751 struct drm_device *dev = vm->dev;
752
753 vm->scratch_page = alloc_scratch_page(dev);
754 if (IS_ERR(vm->scratch_page))
755 return PTR_ERR(vm->scratch_page);
756
757 vm->scratch_pt = alloc_pt(dev);
758 if (IS_ERR(vm->scratch_pt)) {
759 free_scratch_page(dev, vm->scratch_page);
760 return PTR_ERR(vm->scratch_pt);
761 }
762
763 vm->scratch_pd = alloc_pd(dev);
764 if (IS_ERR(vm->scratch_pd)) {
765 free_pt(dev, vm->scratch_pt);
766 free_scratch_page(dev, vm->scratch_page);
767 return PTR_ERR(vm->scratch_pd);
768 }
769
770 gen8_initialize_pt(vm, vm->scratch_pt);
771 gen8_initialize_pd(vm, vm->scratch_pd);
772
773 return 0;
774}
775
776static void gen8_free_scratch(struct i915_address_space *vm)
777{
778 struct drm_device *dev = vm->dev;
779
780 free_pd(dev, vm->scratch_pd);
781 free_pt(dev, vm->scratch_pt);
782 free_scratch_page(dev, vm->scratch_page);
783}
784
061dd493 785static void gen8_ppgtt_cleanup(struct i915_address_space *vm)
b45a6715 786{
061dd493
DV
787 struct i915_hw_ppgtt *ppgtt =
788 container_of(vm, struct i915_hw_ppgtt, base);
d4ec9da0
MT
789 struct i915_page_directory_pointer *pdp = &ppgtt->pdp; /* FIXME: 48b */
790 struct drm_device *dev = ppgtt->base.dev;
b45a6715
BW
791 int i;
792
d4ec9da0
MT
793 for_each_set_bit(i, pdp->used_pdpes, I915_PDPES_PER_PDP(dev)) {
794 if (WARN_ON(!pdp->page_directory[i]))
06fda602
BW
795 continue;
796
d4ec9da0
MT
797 gen8_free_page_tables(dev, pdp->page_directory[i]);
798 free_pd(dev, pdp->page_directory[i]);
7ad47cf2 799 }
69876bed 800
d4ec9da0
MT
801 free_pdp(dev, pdp);
802
8776f02b 803 gen8_free_scratch(vm);
b45a6715
BW
804}
805
d7b2633d
MT
806/**
807 * gen8_ppgtt_alloc_pagetabs() - Allocate page tables for VA range.
d4ec9da0
MT
808 * @vm: Master vm structure.
809 * @pd: Page directory for this address range.
d7b2633d 810 * @start: Starting virtual address to begin allocations.
d4ec9da0 811 * @length: Size of the allocations.
d7b2633d
MT
812 * @new_pts: Bitmap set by function with new allocations. Likely used by the
813 * caller to free on error.
814 *
815 * Allocate the required number of page tables. Extremely similar to
816 * gen8_ppgtt_alloc_page_directories(). The main difference is here we are limited by
817 * the page directory boundary (instead of the page directory pointer). That
818 * boundary is 1GB virtual. Therefore, unlike gen8_ppgtt_alloc_page_directories(), it is
819 * possible, and likely that the caller will need to use multiple calls of this
820 * function to achieve the appropriate allocation.
821 *
822 * Return: 0 if success; negative error code otherwise.
823 */
d4ec9da0 824static int gen8_ppgtt_alloc_pagetabs(struct i915_address_space *vm,
e5815a2e 825 struct i915_page_directory *pd,
5441f0cb 826 uint64_t start,
d7b2633d
MT
827 uint64_t length,
828 unsigned long *new_pts)
bf2b4ed2 829{
d4ec9da0 830 struct drm_device *dev = vm->dev;
d7b2633d 831 struct i915_page_table *pt;
5441f0cb
MT
832 uint64_t temp;
833 uint32_t pde;
bf2b4ed2 834
d7b2633d
MT
835 gen8_for_each_pde(pt, pd, start, length, temp, pde) {
836 /* Don't reallocate page tables */
6ac18502 837 if (test_bit(pde, pd->used_pdes)) {
d7b2633d 838 /* Scratch is never allocated this way */
d4ec9da0 839 WARN_ON(pt == vm->scratch_pt);
d7b2633d
MT
840 continue;
841 }
842
8a1ebd74 843 pt = alloc_pt(dev);
d7b2633d 844 if (IS_ERR(pt))
5441f0cb
MT
845 goto unwind_out;
846
d4ec9da0 847 gen8_initialize_pt(vm, pt);
d7b2633d 848 pd->page_table[pde] = pt;
966082c9 849 __set_bit(pde, new_pts);
4c06ec8d 850 trace_i915_page_table_entry_alloc(vm, pde, start, GEN8_PDE_SHIFT);
7ad47cf2
BW
851 }
852
bf2b4ed2 853 return 0;
7ad47cf2
BW
854
855unwind_out:
d7b2633d 856 for_each_set_bit(pde, new_pts, I915_PDES)
a08e111a 857 free_pt(dev, pd->page_table[pde]);
7ad47cf2 858
d7b3de91 859 return -ENOMEM;
bf2b4ed2
BW
860}
861
d7b2633d
MT
862/**
863 * gen8_ppgtt_alloc_page_directories() - Allocate page directories for VA range.
d4ec9da0 864 * @vm: Master vm structure.
d7b2633d
MT
865 * @pdp: Page directory pointer for this address range.
866 * @start: Starting virtual address to begin allocations.
d4ec9da0
MT
867 * @length: Size of the allocations.
868 * @new_pds: Bitmap set by function with new allocations. Likely used by the
d7b2633d
MT
869 * caller to free on error.
870 *
871 * Allocate the required number of page directories starting at the pde index of
872 * @start, and ending at the pde index @start + @length. This function will skip
873 * over already allocated page directories within the range, and only allocate
874 * new ones, setting the appropriate pointer within the pdp as well as the
875 * correct position in the bitmap @new_pds.
876 *
877 * The function will only allocate the pages within the range for a give page
878 * directory pointer. In other words, if @start + @length straddles a virtually
879 * addressed PDP boundary (512GB for 4k pages), there will be more allocations
880 * required by the caller, This is not currently possible, and the BUG in the
881 * code will prevent it.
882 *
883 * Return: 0 if success; negative error code otherwise.
884 */
d4ec9da0
MT
885static int
886gen8_ppgtt_alloc_page_directories(struct i915_address_space *vm,
887 struct i915_page_directory_pointer *pdp,
888 uint64_t start,
889 uint64_t length,
890 unsigned long *new_pds)
bf2b4ed2 891{
d4ec9da0 892 struct drm_device *dev = vm->dev;
d7b2633d 893 struct i915_page_directory *pd;
69876bed
MT
894 uint64_t temp;
895 uint32_t pdpe;
6ac18502 896 uint32_t pdpes = I915_PDPES_PER_PDP(dev);
69876bed 897
6ac18502 898 WARN_ON(!bitmap_empty(new_pds, pdpes));
d7b2633d 899
d7b2633d 900 gen8_for_each_pdpe(pd, pdp, start, length, temp, pdpe) {
6ac18502 901 if (test_bit(pdpe, pdp->used_pdpes))
d7b2633d 902 continue;
33c8819f 903
8a1ebd74 904 pd = alloc_pd(dev);
d7b2633d 905 if (IS_ERR(pd))
d7b3de91 906 goto unwind_out;
69876bed 907
d4ec9da0 908 gen8_initialize_pd(vm, pd);
d7b2633d 909 pdp->page_directory[pdpe] = pd;
966082c9 910 __set_bit(pdpe, new_pds);
4c06ec8d 911 trace_i915_page_directory_entry_alloc(vm, pdpe, start, GEN8_PDPE_SHIFT);
d7b3de91
BW
912 }
913
bf2b4ed2 914 return 0;
d7b3de91
BW
915
916unwind_out:
6ac18502 917 for_each_set_bit(pdpe, new_pds, pdpes)
a08e111a 918 free_pd(dev, pdp->page_directory[pdpe]);
d7b3de91
BW
919
920 return -ENOMEM;
bf2b4ed2
BW
921}
922
d7b2633d 923static void
6ac18502
MT
924free_gen8_temp_bitmaps(unsigned long *new_pds, unsigned long **new_pts,
925 uint32_t pdpes)
d7b2633d
MT
926{
927 int i;
928
6ac18502 929 for (i = 0; i < pdpes; i++)
d7b2633d
MT
930 kfree(new_pts[i]);
931 kfree(new_pts);
932 kfree(new_pds);
933}
934
935/* Fills in the page directory bitmap, and the array of page tables bitmap. Both
936 * of these are based on the number of PDPEs in the system.
937 */
938static
939int __must_check alloc_gen8_temp_bitmaps(unsigned long **new_pds,
6ac18502
MT
940 unsigned long ***new_pts,
941 uint32_t pdpes)
d7b2633d
MT
942{
943 int i;
944 unsigned long *pds;
945 unsigned long **pts;
946
6ac18502 947 pds = kcalloc(BITS_TO_LONGS(pdpes), sizeof(unsigned long), GFP_KERNEL);
d7b2633d
MT
948 if (!pds)
949 return -ENOMEM;
950
6ac18502 951 pts = kcalloc(pdpes, sizeof(unsigned long *), GFP_KERNEL);
d7b2633d
MT
952 if (!pts) {
953 kfree(pds);
954 return -ENOMEM;
955 }
956
6ac18502 957 for (i = 0; i < pdpes; i++) {
d7b2633d
MT
958 pts[i] = kcalloc(BITS_TO_LONGS(I915_PDES),
959 sizeof(unsigned long), GFP_KERNEL);
960 if (!pts[i])
961 goto err_out;
962 }
963
964 *new_pds = pds;
965 *new_pts = pts;
966
967 return 0;
968
969err_out:
6ac18502 970 free_gen8_temp_bitmaps(pds, pts, pdpes);
d7b2633d
MT
971 return -ENOMEM;
972}
973
5b7e4c9c
MK
974/* PDE TLBs are a pain to invalidate on GEN8+. When we modify
975 * the page table structures, we mark them dirty so that
976 * context switching/execlist queuing code takes extra steps
977 * to ensure that tlbs are flushed.
978 */
979static void mark_tlbs_dirty(struct i915_hw_ppgtt *ppgtt)
980{
981 ppgtt->pd_dirty_rings = INTEL_INFO(ppgtt->base.dev)->ring_mask;
982}
983
e5815a2e 984static int gen8_alloc_va_range(struct i915_address_space *vm,
d4ec9da0 985 uint64_t start, uint64_t length)
bf2b4ed2 986{
e5815a2e
MT
987 struct i915_hw_ppgtt *ppgtt =
988 container_of(vm, struct i915_hw_ppgtt, base);
d7b2633d 989 unsigned long *new_page_dirs, **new_page_tables;
d4ec9da0
MT
990 struct drm_device *dev = vm->dev;
991 struct i915_page_directory_pointer *pdp = &ppgtt->pdp; /* FIXME: 48b */
5441f0cb 992 struct i915_page_directory *pd;
33c8819f
MT
993 const uint64_t orig_start = start;
994 const uint64_t orig_length = length;
5441f0cb
MT
995 uint64_t temp;
996 uint32_t pdpe;
d4ec9da0 997 uint32_t pdpes = I915_PDPES_PER_PDP(dev);
bf2b4ed2
BW
998 int ret;
999
d7b2633d
MT
1000 /* Wrap is never okay since we can only represent 48b, and we don't
1001 * actually use the other side of the canonical address space.
1002 */
1003 if (WARN_ON(start + length < start))
a05d80ee
MK
1004 return -ENODEV;
1005
d4ec9da0 1006 if (WARN_ON(start + length > vm->total))
a05d80ee 1007 return -ENODEV;
d7b2633d 1008
6ac18502 1009 ret = alloc_gen8_temp_bitmaps(&new_page_dirs, &new_page_tables, pdpes);
bf2b4ed2
BW
1010 if (ret)
1011 return ret;
1012
d7b2633d 1013 /* Do the allocations first so we can easily bail out */
d4ec9da0
MT
1014 ret = gen8_ppgtt_alloc_page_directories(vm, pdp, start, length,
1015 new_page_dirs);
d7b2633d 1016 if (ret) {
6ac18502 1017 free_gen8_temp_bitmaps(new_page_dirs, new_page_tables, pdpes);
d7b2633d
MT
1018 return ret;
1019 }
1020
1021 /* For every page directory referenced, allocate page tables */
d4ec9da0
MT
1022 gen8_for_each_pdpe(pd, pdp, start, length, temp, pdpe) {
1023 ret = gen8_ppgtt_alloc_pagetabs(vm, pd, start, length,
d7b2633d 1024 new_page_tables[pdpe]);
5441f0cb
MT
1025 if (ret)
1026 goto err_out;
5441f0cb
MT
1027 }
1028
33c8819f
MT
1029 start = orig_start;
1030 length = orig_length;
1031
d7b2633d
MT
1032 /* Allocations have completed successfully, so set the bitmaps, and do
1033 * the mappings. */
d4ec9da0 1034 gen8_for_each_pdpe(pd, pdp, start, length, temp, pdpe) {
d1c54acd 1035 gen8_pde_t *const page_directory = kmap_px(pd);
33c8819f 1036 struct i915_page_table *pt;
09120d4e 1037 uint64_t pd_len = length;
33c8819f
MT
1038 uint64_t pd_start = start;
1039 uint32_t pde;
1040
d7b2633d
MT
1041 /* Every pd should be allocated, we just did that above. */
1042 WARN_ON(!pd);
1043
1044 gen8_for_each_pde(pt, pd, pd_start, pd_len, temp, pde) {
1045 /* Same reasoning as pd */
1046 WARN_ON(!pt);
1047 WARN_ON(!pd_len);
1048 WARN_ON(!gen8_pte_count(pd_start, pd_len));
1049
1050 /* Set our used ptes within the page table */
1051 bitmap_set(pt->used_ptes,
1052 gen8_pte_index(pd_start),
1053 gen8_pte_count(pd_start, pd_len));
1054
1055 /* Our pde is now pointing to the pagetable, pt */
966082c9 1056 __set_bit(pde, pd->used_pdes);
d7b2633d
MT
1057
1058 /* Map the PDE to the page table */
fe36f55d
MK
1059 page_directory[pde] = gen8_pde_encode(px_dma(pt),
1060 I915_CACHE_LLC);
4c06ec8d
MT
1061 trace_i915_page_table_entry_map(&ppgtt->base, pde, pt,
1062 gen8_pte_index(start),
1063 gen8_pte_count(start, length),
1064 GEN8_PTES);
d7b2633d
MT
1065
1066 /* NB: We haven't yet mapped ptes to pages. At this
1067 * point we're still relying on insert_entries() */
33c8819f 1068 }
d7b2633d 1069
d1c54acd 1070 kunmap_px(ppgtt, page_directory);
d4ec9da0 1071 __set_bit(pdpe, pdp->used_pdpes);
33c8819f
MT
1072 }
1073
6ac18502 1074 free_gen8_temp_bitmaps(new_page_dirs, new_page_tables, pdpes);
5b7e4c9c 1075 mark_tlbs_dirty(ppgtt);
d7b3de91 1076 return 0;
bf2b4ed2 1077
d7b3de91 1078err_out:
d7b2633d
MT
1079 while (pdpe--) {
1080 for_each_set_bit(temp, new_page_tables[pdpe], I915_PDES)
d4ec9da0 1081 free_pt(dev, pdp->page_directory[pdpe]->page_table[temp]);
d7b2633d
MT
1082 }
1083
6ac18502 1084 for_each_set_bit(pdpe, new_page_dirs, pdpes)
d4ec9da0 1085 free_pd(dev, pdp->page_directory[pdpe]);
d7b2633d 1086
6ac18502 1087 free_gen8_temp_bitmaps(new_page_dirs, new_page_tables, pdpes);
5b7e4c9c 1088 mark_tlbs_dirty(ppgtt);
bf2b4ed2
BW
1089 return ret;
1090}
1091
eb0b44ad 1092/*
f3a964b9
BW
1093 * GEN8 legacy ppgtt programming is accomplished through a max 4 PDP registers
1094 * with a net effect resembling a 2-level page table in normal x86 terms. Each
1095 * PDP represents 1GB of memory 4 * 512 * 512 * 4096 = 4GB legacy 32b address
1096 * space.
37aca44a 1097 *
f3a964b9 1098 */
5c5f6457 1099static int gen8_ppgtt_init(struct i915_hw_ppgtt *ppgtt)
37aca44a 1100{
8776f02b 1101 int ret;
7cb6d7ac 1102
8776f02b
MK
1103 ret = gen8_init_scratch(&ppgtt->base);
1104 if (ret)
1105 return ret;
69876bed 1106
d7b2633d 1107 ppgtt->base.start = 0;
5c5f6457 1108 ppgtt->base.total = 1ULL << 32;
501fd70f
MT
1109 if (IS_ENABLED(CONFIG_X86_32))
1110 /* While we have a proliferation of size_t variables
1111 * we cannot represent the full ppgtt size on 32bit,
1112 * so limit it to the same size as the GGTT (currently
1113 * 2GiB).
1114 */
1115 ppgtt->base.total = to_i915(ppgtt->base.dev)->gtt.base.total;
d7b2633d 1116 ppgtt->base.cleanup = gen8_ppgtt_cleanup;
5c5f6457 1117 ppgtt->base.allocate_va_range = gen8_alloc_va_range;
d7b2633d 1118 ppgtt->base.insert_entries = gen8_ppgtt_insert_entries;
c7e16f22 1119 ppgtt->base.clear_range = gen8_ppgtt_clear_range;
777dc5bb
DV
1120 ppgtt->base.unbind_vma = ppgtt_unbind_vma;
1121 ppgtt->base.bind_vma = ppgtt_bind_vma;
d7b2633d
MT
1122
1123 ppgtt->switch_mm = gen8_mm_switch;
1124
6ac18502
MT
1125 ret = __pdp_init(false, &ppgtt->pdp);
1126
1127 if (ret)
1128 goto free_scratch;
1129
d7b2633d 1130 return 0;
6ac18502
MT
1131
1132free_scratch:
1133 gen8_free_scratch(&ppgtt->base);
1134 return ret;
d7b2633d
MT
1135}
1136
87d60b63
BW
1137static void gen6_dump_ppgtt(struct i915_hw_ppgtt *ppgtt, struct seq_file *m)
1138{
87d60b63 1139 struct i915_address_space *vm = &ppgtt->base;
09942c65 1140 struct i915_page_table *unused;
07749ef3 1141 gen6_pte_t scratch_pte;
87d60b63 1142 uint32_t pd_entry;
09942c65
MT
1143 uint32_t pte, pde, temp;
1144 uint32_t start = ppgtt->base.start, length = ppgtt->base.total;
87d60b63 1145
79ab9370
MK
1146 scratch_pte = vm->pte_encode(px_dma(vm->scratch_page),
1147 I915_CACHE_LLC, true, 0);
87d60b63 1148
09942c65 1149 gen6_for_each_pde(unused, &ppgtt->pd, start, length, temp, pde) {
87d60b63 1150 u32 expected;
07749ef3 1151 gen6_pte_t *pt_vaddr;
567047be 1152 const dma_addr_t pt_addr = px_dma(ppgtt->pd.page_table[pde]);
09942c65 1153 pd_entry = readl(ppgtt->pd_addr + pde);
87d60b63
BW
1154 expected = (GEN6_PDE_ADDR_ENCODE(pt_addr) | GEN6_PDE_VALID);
1155
1156 if (pd_entry != expected)
1157 seq_printf(m, "\tPDE #%d mismatch: Actual PDE: %x Expected PDE: %x\n",
1158 pde,
1159 pd_entry,
1160 expected);
1161 seq_printf(m, "\tPDE: %x\n", pd_entry);
1162
d1c54acd
MK
1163 pt_vaddr = kmap_px(ppgtt->pd.page_table[pde]);
1164
07749ef3 1165 for (pte = 0; pte < GEN6_PTES; pte+=4) {
87d60b63 1166 unsigned long va =
07749ef3 1167 (pde * PAGE_SIZE * GEN6_PTES) +
87d60b63
BW
1168 (pte * PAGE_SIZE);
1169 int i;
1170 bool found = false;
1171 for (i = 0; i < 4; i++)
1172 if (pt_vaddr[pte + i] != scratch_pte)
1173 found = true;
1174 if (!found)
1175 continue;
1176
1177 seq_printf(m, "\t\t0x%lx [%03d,%04d]: =", va, pde, pte);
1178 for (i = 0; i < 4; i++) {
1179 if (pt_vaddr[pte + i] != scratch_pte)
1180 seq_printf(m, " %08x", pt_vaddr[pte + i]);
1181 else
1182 seq_puts(m, " SCRATCH ");
1183 }
1184 seq_puts(m, "\n");
1185 }
d1c54acd 1186 kunmap_px(ppgtt, pt_vaddr);
87d60b63
BW
1187 }
1188}
1189
678d96fb 1190/* Write pde (index) from the page directory @pd to the page table @pt */
ec565b3c
MT
1191static void gen6_write_pde(struct i915_page_directory *pd,
1192 const int pde, struct i915_page_table *pt)
6197349b 1193{
678d96fb
BW
1194 /* Caller needs to make sure the write completes if necessary */
1195 struct i915_hw_ppgtt *ppgtt =
1196 container_of(pd, struct i915_hw_ppgtt, pd);
1197 u32 pd_entry;
6197349b 1198
567047be 1199 pd_entry = GEN6_PDE_ADDR_ENCODE(px_dma(pt));
678d96fb 1200 pd_entry |= GEN6_PDE_VALID;
6197349b 1201
678d96fb
BW
1202 writel(pd_entry, ppgtt->pd_addr + pde);
1203}
6197349b 1204
678d96fb
BW
1205/* Write all the page tables found in the ppgtt structure to incrementing page
1206 * directories. */
1207static void gen6_write_page_range(struct drm_i915_private *dev_priv,
ec565b3c 1208 struct i915_page_directory *pd,
678d96fb
BW
1209 uint32_t start, uint32_t length)
1210{
ec565b3c 1211 struct i915_page_table *pt;
678d96fb
BW
1212 uint32_t pde, temp;
1213
1214 gen6_for_each_pde(pt, pd, start, length, temp, pde)
1215 gen6_write_pde(pd, pde, pt);
1216
1217 /* Make sure write is complete before other code can use this page
1218 * table. Also require for WC mapped PTEs */
1219 readl(dev_priv->gtt.gsm);
3e302542
BW
1220}
1221
b4a74e3a 1222static uint32_t get_pd_offset(struct i915_hw_ppgtt *ppgtt)
3e302542 1223{
44159ddb 1224 BUG_ON(ppgtt->pd.base.ggtt_offset & 0x3f);
b4a74e3a 1225
44159ddb 1226 return (ppgtt->pd.base.ggtt_offset / 64) << 16;
b4a74e3a
BW
1227}
1228
90252e5c 1229static int hsw_mm_switch(struct i915_hw_ppgtt *ppgtt,
e85b26dc 1230 struct drm_i915_gem_request *req)
90252e5c 1231{
e85b26dc 1232 struct intel_engine_cs *ring = req->ring;
90252e5c
BW
1233 int ret;
1234
90252e5c 1235 /* NB: TLBs must be flushed and invalidated before a switch */
a84c3ae1 1236 ret = ring->flush(req, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);
90252e5c
BW
1237 if (ret)
1238 return ret;
1239
5fb9de1a 1240 ret = intel_ring_begin(req, 6);
90252e5c
BW
1241 if (ret)
1242 return ret;
1243
1244 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(2));
1245 intel_ring_emit(ring, RING_PP_DIR_DCLV(ring));
1246 intel_ring_emit(ring, PP_DIR_DCLV_2G);
1247 intel_ring_emit(ring, RING_PP_DIR_BASE(ring));
1248 intel_ring_emit(ring, get_pd_offset(ppgtt));
1249 intel_ring_emit(ring, MI_NOOP);
1250 intel_ring_advance(ring);
1251
1252 return 0;
1253}
1254
71ba2d64 1255static int vgpu_mm_switch(struct i915_hw_ppgtt *ppgtt,
e85b26dc 1256 struct drm_i915_gem_request *req)
71ba2d64 1257{
e85b26dc 1258 struct intel_engine_cs *ring = req->ring;
71ba2d64
YZ
1259 struct drm_i915_private *dev_priv = to_i915(ppgtt->base.dev);
1260
1261 I915_WRITE(RING_PP_DIR_DCLV(ring), PP_DIR_DCLV_2G);
1262 I915_WRITE(RING_PP_DIR_BASE(ring), get_pd_offset(ppgtt));
1263 return 0;
1264}
1265
48a10389 1266static int gen7_mm_switch(struct i915_hw_ppgtt *ppgtt,
e85b26dc 1267 struct drm_i915_gem_request *req)
48a10389 1268{
e85b26dc 1269 struct intel_engine_cs *ring = req->ring;
48a10389
BW
1270 int ret;
1271
48a10389 1272 /* NB: TLBs must be flushed and invalidated before a switch */
a84c3ae1 1273 ret = ring->flush(req, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);
48a10389
BW
1274 if (ret)
1275 return ret;
1276
5fb9de1a 1277 ret = intel_ring_begin(req, 6);
48a10389
BW
1278 if (ret)
1279 return ret;
1280
1281 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(2));
1282 intel_ring_emit(ring, RING_PP_DIR_DCLV(ring));
1283 intel_ring_emit(ring, PP_DIR_DCLV_2G);
1284 intel_ring_emit(ring, RING_PP_DIR_BASE(ring));
1285 intel_ring_emit(ring, get_pd_offset(ppgtt));
1286 intel_ring_emit(ring, MI_NOOP);
1287 intel_ring_advance(ring);
1288
90252e5c
BW
1289 /* XXX: RCS is the only one to auto invalidate the TLBs? */
1290 if (ring->id != RCS) {
a84c3ae1 1291 ret = ring->flush(req, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);
90252e5c
BW
1292 if (ret)
1293 return ret;
1294 }
1295
48a10389
BW
1296 return 0;
1297}
1298
eeb9488e 1299static int gen6_mm_switch(struct i915_hw_ppgtt *ppgtt,
e85b26dc 1300 struct drm_i915_gem_request *req)
eeb9488e 1301{
e85b26dc 1302 struct intel_engine_cs *ring = req->ring;
eeb9488e
BW
1303 struct drm_device *dev = ppgtt->base.dev;
1304 struct drm_i915_private *dev_priv = dev->dev_private;
1305
48a10389 1306
eeb9488e
BW
1307 I915_WRITE(RING_PP_DIR_DCLV(ring), PP_DIR_DCLV_2G);
1308 I915_WRITE(RING_PP_DIR_BASE(ring), get_pd_offset(ppgtt));
1309
1310 POSTING_READ(RING_PP_DIR_DCLV(ring));
1311
1312 return 0;
1313}
1314
82460d97 1315static void gen8_ppgtt_enable(struct drm_device *dev)
eeb9488e 1316{
eeb9488e 1317 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 1318 struct intel_engine_cs *ring;
82460d97 1319 int j;
3e302542 1320
eeb9488e
BW
1321 for_each_ring(ring, dev_priv, j) {
1322 I915_WRITE(RING_MODE_GEN7(ring),
1323 _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
eeb9488e 1324 }
eeb9488e 1325}
6197349b 1326
82460d97 1327static void gen7_ppgtt_enable(struct drm_device *dev)
3e302542 1328{
50227e1c 1329 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 1330 struct intel_engine_cs *ring;
b4a74e3a 1331 uint32_t ecochk, ecobits;
3e302542 1332 int i;
6197349b 1333
b4a74e3a
BW
1334 ecobits = I915_READ(GAC_ECO_BITS);
1335 I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_PPGTT_CACHE64B);
a65c2fcd 1336
b4a74e3a
BW
1337 ecochk = I915_READ(GAM_ECOCHK);
1338 if (IS_HASWELL(dev)) {
1339 ecochk |= ECOCHK_PPGTT_WB_HSW;
1340 } else {
1341 ecochk |= ECOCHK_PPGTT_LLC_IVB;
1342 ecochk &= ~ECOCHK_PPGTT_GFDT_IVB;
1343 }
1344 I915_WRITE(GAM_ECOCHK, ecochk);
a65c2fcd 1345
b4a74e3a 1346 for_each_ring(ring, dev_priv, i) {
6197349b 1347 /* GFX_MODE is per-ring on gen7+ */
b4a74e3a
BW
1348 I915_WRITE(RING_MODE_GEN7(ring),
1349 _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
6197349b 1350 }
b4a74e3a 1351}
6197349b 1352
82460d97 1353static void gen6_ppgtt_enable(struct drm_device *dev)
b4a74e3a 1354{
50227e1c 1355 struct drm_i915_private *dev_priv = dev->dev_private;
b4a74e3a 1356 uint32_t ecochk, gab_ctl, ecobits;
a65c2fcd 1357
b4a74e3a
BW
1358 ecobits = I915_READ(GAC_ECO_BITS);
1359 I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_SNB_BIT |
1360 ECOBITS_PPGTT_CACHE64B);
6197349b 1361
b4a74e3a
BW
1362 gab_ctl = I915_READ(GAB_CTL);
1363 I915_WRITE(GAB_CTL, gab_ctl | GAB_CTL_CONT_AFTER_PAGEFAULT);
1364
1365 ecochk = I915_READ(GAM_ECOCHK);
1366 I915_WRITE(GAM_ECOCHK, ecochk | ECOCHK_SNB_BIT | ECOCHK_PPGTT_CACHE64B);
1367
1368 I915_WRITE(GFX_MODE, _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
6197349b
BW
1369}
1370
1d2a314c 1371/* PPGTT support for Sandybdrige/Gen6 and later */
853ba5d2 1372static void gen6_ppgtt_clear_range(struct i915_address_space *vm,
782f1495
BW
1373 uint64_t start,
1374 uint64_t length,
828c7908 1375 bool use_scratch)
1d2a314c 1376{
853ba5d2
BW
1377 struct i915_hw_ppgtt *ppgtt =
1378 container_of(vm, struct i915_hw_ppgtt, base);
07749ef3 1379 gen6_pte_t *pt_vaddr, scratch_pte;
782f1495
BW
1380 unsigned first_entry = start >> PAGE_SHIFT;
1381 unsigned num_entries = length >> PAGE_SHIFT;
07749ef3
MT
1382 unsigned act_pt = first_entry / GEN6_PTES;
1383 unsigned first_pte = first_entry % GEN6_PTES;
7bddb01f 1384 unsigned last_pte, i;
1d2a314c 1385
c114f76a
MK
1386 scratch_pte = vm->pte_encode(px_dma(vm->scratch_page),
1387 I915_CACHE_LLC, true, 0);
1d2a314c 1388
7bddb01f
DV
1389 while (num_entries) {
1390 last_pte = first_pte + num_entries;
07749ef3
MT
1391 if (last_pte > GEN6_PTES)
1392 last_pte = GEN6_PTES;
7bddb01f 1393
d1c54acd 1394 pt_vaddr = kmap_px(ppgtt->pd.page_table[act_pt]);
1d2a314c 1395
7bddb01f
DV
1396 for (i = first_pte; i < last_pte; i++)
1397 pt_vaddr[i] = scratch_pte;
1d2a314c 1398
d1c54acd 1399 kunmap_px(ppgtt, pt_vaddr);
1d2a314c 1400
7bddb01f
DV
1401 num_entries -= last_pte - first_pte;
1402 first_pte = 0;
a15326a5 1403 act_pt++;
7bddb01f 1404 }
1d2a314c
DV
1405}
1406
853ba5d2 1407static void gen6_ppgtt_insert_entries(struct i915_address_space *vm,
def886c3 1408 struct sg_table *pages,
782f1495 1409 uint64_t start,
24f3a8cf 1410 enum i915_cache_level cache_level, u32 flags)
def886c3 1411{
853ba5d2
BW
1412 struct i915_hw_ppgtt *ppgtt =
1413 container_of(vm, struct i915_hw_ppgtt, base);
07749ef3 1414 gen6_pte_t *pt_vaddr;
782f1495 1415 unsigned first_entry = start >> PAGE_SHIFT;
07749ef3
MT
1416 unsigned act_pt = first_entry / GEN6_PTES;
1417 unsigned act_pte = first_entry % GEN6_PTES;
6e995e23
ID
1418 struct sg_page_iter sg_iter;
1419
cc79714f 1420 pt_vaddr = NULL;
6e995e23 1421 for_each_sg_page(pages->sgl, &sg_iter, pages->nents, 0) {
cc79714f 1422 if (pt_vaddr == NULL)
d1c54acd 1423 pt_vaddr = kmap_px(ppgtt->pd.page_table[act_pt]);
6e995e23 1424
cc79714f
CW
1425 pt_vaddr[act_pte] =
1426 vm->pte_encode(sg_page_iter_dma_address(&sg_iter),
24f3a8cf
AG
1427 cache_level, true, flags);
1428
07749ef3 1429 if (++act_pte == GEN6_PTES) {
d1c54acd 1430 kunmap_px(ppgtt, pt_vaddr);
cc79714f 1431 pt_vaddr = NULL;
a15326a5 1432 act_pt++;
6e995e23 1433 act_pte = 0;
def886c3 1434 }
def886c3 1435 }
cc79714f 1436 if (pt_vaddr)
d1c54acd 1437 kunmap_px(ppgtt, pt_vaddr);
def886c3
DV
1438}
1439
678d96fb 1440static int gen6_alloc_va_range(struct i915_address_space *vm,
a05d80ee 1441 uint64_t start_in, uint64_t length_in)
678d96fb 1442{
4933d519
MT
1443 DECLARE_BITMAP(new_page_tables, I915_PDES);
1444 struct drm_device *dev = vm->dev;
1445 struct drm_i915_private *dev_priv = dev->dev_private;
678d96fb
BW
1446 struct i915_hw_ppgtt *ppgtt =
1447 container_of(vm, struct i915_hw_ppgtt, base);
ec565b3c 1448 struct i915_page_table *pt;
a05d80ee 1449 uint32_t start, length, start_save, length_save;
678d96fb 1450 uint32_t pde, temp;
4933d519
MT
1451 int ret;
1452
a05d80ee
MK
1453 if (WARN_ON(start_in + length_in > ppgtt->base.total))
1454 return -ENODEV;
1455
1456 start = start_save = start_in;
1457 length = length_save = length_in;
4933d519
MT
1458
1459 bitmap_zero(new_page_tables, I915_PDES);
1460
1461 /* The allocation is done in two stages so that we can bail out with
1462 * minimal amount of pain. The first stage finds new page tables that
1463 * need allocation. The second stage marks use ptes within the page
1464 * tables.
1465 */
1466 gen6_for_each_pde(pt, &ppgtt->pd, start, length, temp, pde) {
79ab9370 1467 if (pt != vm->scratch_pt) {
4933d519
MT
1468 WARN_ON(bitmap_empty(pt->used_ptes, GEN6_PTES));
1469 continue;
1470 }
1471
1472 /* We've already allocated a page table */
1473 WARN_ON(!bitmap_empty(pt->used_ptes, GEN6_PTES));
1474
8a1ebd74 1475 pt = alloc_pt(dev);
4933d519
MT
1476 if (IS_ERR(pt)) {
1477 ret = PTR_ERR(pt);
1478 goto unwind_out;
1479 }
1480
1481 gen6_initialize_pt(vm, pt);
1482
1483 ppgtt->pd.page_table[pde] = pt;
966082c9 1484 __set_bit(pde, new_page_tables);
72744cb1 1485 trace_i915_page_table_entry_alloc(vm, pde, start, GEN6_PDE_SHIFT);
4933d519
MT
1486 }
1487
1488 start = start_save;
1489 length = length_save;
678d96fb
BW
1490
1491 gen6_for_each_pde(pt, &ppgtt->pd, start, length, temp, pde) {
1492 DECLARE_BITMAP(tmp_bitmap, GEN6_PTES);
1493
1494 bitmap_zero(tmp_bitmap, GEN6_PTES);
1495 bitmap_set(tmp_bitmap, gen6_pte_index(start),
1496 gen6_pte_count(start, length));
1497
966082c9 1498 if (__test_and_clear_bit(pde, new_page_tables))
4933d519
MT
1499 gen6_write_pde(&ppgtt->pd, pde, pt);
1500
72744cb1
MT
1501 trace_i915_page_table_entry_map(vm, pde, pt,
1502 gen6_pte_index(start),
1503 gen6_pte_count(start, length),
1504 GEN6_PTES);
4933d519 1505 bitmap_or(pt->used_ptes, tmp_bitmap, pt->used_ptes,
678d96fb
BW
1506 GEN6_PTES);
1507 }
1508
4933d519
MT
1509 WARN_ON(!bitmap_empty(new_page_tables, I915_PDES));
1510
1511 /* Make sure write is complete before other code can use this page
1512 * table. Also require for WC mapped PTEs */
1513 readl(dev_priv->gtt.gsm);
1514
563222a7 1515 mark_tlbs_dirty(ppgtt);
678d96fb 1516 return 0;
4933d519
MT
1517
1518unwind_out:
1519 for_each_set_bit(pde, new_page_tables, I915_PDES) {
ec565b3c 1520 struct i915_page_table *pt = ppgtt->pd.page_table[pde];
4933d519 1521
79ab9370 1522 ppgtt->pd.page_table[pde] = vm->scratch_pt;
a08e111a 1523 free_pt(vm->dev, pt);
4933d519
MT
1524 }
1525
1526 mark_tlbs_dirty(ppgtt);
1527 return ret;
678d96fb
BW
1528}
1529
8776f02b
MK
1530static int gen6_init_scratch(struct i915_address_space *vm)
1531{
1532 struct drm_device *dev = vm->dev;
1533
1534 vm->scratch_page = alloc_scratch_page(dev);
1535 if (IS_ERR(vm->scratch_page))
1536 return PTR_ERR(vm->scratch_page);
1537
1538 vm->scratch_pt = alloc_pt(dev);
1539 if (IS_ERR(vm->scratch_pt)) {
1540 free_scratch_page(dev, vm->scratch_page);
1541 return PTR_ERR(vm->scratch_pt);
1542 }
1543
1544 gen6_initialize_pt(vm, vm->scratch_pt);
1545
1546 return 0;
1547}
1548
1549static void gen6_free_scratch(struct i915_address_space *vm)
1550{
1551 struct drm_device *dev = vm->dev;
1552
1553 free_pt(dev, vm->scratch_pt);
1554 free_scratch_page(dev, vm->scratch_page);
1555}
1556
061dd493 1557static void gen6_ppgtt_cleanup(struct i915_address_space *vm)
a00d825d 1558{
061dd493
DV
1559 struct i915_hw_ppgtt *ppgtt =
1560 container_of(vm, struct i915_hw_ppgtt, base);
09942c65
MT
1561 struct i915_page_table *pt;
1562 uint32_t pde;
4933d519 1563
061dd493
DV
1564 drm_mm_remove_node(&ppgtt->node);
1565
09942c65 1566 gen6_for_all_pdes(pt, ppgtt, pde) {
79ab9370 1567 if (pt != vm->scratch_pt)
a08e111a 1568 free_pt(ppgtt->base.dev, pt);
4933d519 1569 }
06fda602 1570
8776f02b 1571 gen6_free_scratch(vm);
3440d265
DV
1572}
1573
b146520f 1574static int gen6_ppgtt_allocate_page_directories(struct i915_hw_ppgtt *ppgtt)
3440d265 1575{
8776f02b 1576 struct i915_address_space *vm = &ppgtt->base;
853ba5d2 1577 struct drm_device *dev = ppgtt->base.dev;
1d2a314c 1578 struct drm_i915_private *dev_priv = dev->dev_private;
e3cc1995 1579 bool retried = false;
b146520f 1580 int ret;
1d2a314c 1581
c8d4c0d6
BW
1582 /* PPGTT PDEs reside in the GGTT and consists of 512 entries. The
1583 * allocator works in address space sizes, so it's multiplied by page
1584 * size. We allocate at the top of the GTT to avoid fragmentation.
1585 */
1586 BUG_ON(!drm_mm_initialized(&dev_priv->gtt.base.mm));
4933d519 1587
8776f02b
MK
1588 ret = gen6_init_scratch(vm);
1589 if (ret)
1590 return ret;
4933d519 1591
e3cc1995 1592alloc:
c8d4c0d6
BW
1593 ret = drm_mm_insert_node_in_range_generic(&dev_priv->gtt.base.mm,
1594 &ppgtt->node, GEN6_PD_SIZE,
1595 GEN6_PD_ALIGN, 0,
1596 0, dev_priv->gtt.base.total,
3e8b5ae9 1597 DRM_MM_TOPDOWN);
e3cc1995
BW
1598 if (ret == -ENOSPC && !retried) {
1599 ret = i915_gem_evict_something(dev, &dev_priv->gtt.base,
1600 GEN6_PD_SIZE, GEN6_PD_ALIGN,
d23db88c
CW
1601 I915_CACHE_NONE,
1602 0, dev_priv->gtt.base.total,
1603 0);
e3cc1995 1604 if (ret)
678d96fb 1605 goto err_out;
e3cc1995
BW
1606
1607 retried = true;
1608 goto alloc;
1609 }
c8d4c0d6 1610
c8c26622 1611 if (ret)
678d96fb
BW
1612 goto err_out;
1613
c8c26622 1614
c8d4c0d6
BW
1615 if (ppgtt->node.start < dev_priv->gtt.mappable_end)
1616 DRM_DEBUG("Forced to use aperture for PDEs\n");
1d2a314c 1617
c8c26622 1618 return 0;
678d96fb
BW
1619
1620err_out:
8776f02b 1621 gen6_free_scratch(vm);
678d96fb 1622 return ret;
b146520f
BW
1623}
1624
b146520f
BW
1625static int gen6_ppgtt_alloc(struct i915_hw_ppgtt *ppgtt)
1626{
2f2cf682 1627 return gen6_ppgtt_allocate_page_directories(ppgtt);
4933d519 1628}
06dc68d6 1629
4933d519
MT
1630static void gen6_scratch_va_range(struct i915_hw_ppgtt *ppgtt,
1631 uint64_t start, uint64_t length)
1632{
ec565b3c 1633 struct i915_page_table *unused;
4933d519 1634 uint32_t pde, temp;
1d2a314c 1635
4933d519 1636 gen6_for_each_pde(unused, &ppgtt->pd, start, length, temp, pde)
79ab9370 1637 ppgtt->pd.page_table[pde] = ppgtt->base.scratch_pt;
b146520f
BW
1638}
1639
5c5f6457 1640static int gen6_ppgtt_init(struct i915_hw_ppgtt *ppgtt)
b146520f
BW
1641{
1642 struct drm_device *dev = ppgtt->base.dev;
1643 struct drm_i915_private *dev_priv = dev->dev_private;
1644 int ret;
1645
1646 ppgtt->base.pte_encode = dev_priv->gtt.base.pte_encode;
1647 if (IS_GEN6(dev)) {
b146520f
BW
1648 ppgtt->switch_mm = gen6_mm_switch;
1649 } else if (IS_HASWELL(dev)) {
b146520f
BW
1650 ppgtt->switch_mm = hsw_mm_switch;
1651 } else if (IS_GEN7(dev)) {
b146520f
BW
1652 ppgtt->switch_mm = gen7_mm_switch;
1653 } else
1654 BUG();
1655
71ba2d64
YZ
1656 if (intel_vgpu_active(dev))
1657 ppgtt->switch_mm = vgpu_mm_switch;
1658
b146520f
BW
1659 ret = gen6_ppgtt_alloc(ppgtt);
1660 if (ret)
1661 return ret;
1662
5c5f6457 1663 ppgtt->base.allocate_va_range = gen6_alloc_va_range;
b146520f
BW
1664 ppgtt->base.clear_range = gen6_ppgtt_clear_range;
1665 ppgtt->base.insert_entries = gen6_ppgtt_insert_entries;
777dc5bb
DV
1666 ppgtt->base.unbind_vma = ppgtt_unbind_vma;
1667 ppgtt->base.bind_vma = ppgtt_bind_vma;
b146520f 1668 ppgtt->base.cleanup = gen6_ppgtt_cleanup;
b146520f 1669 ppgtt->base.start = 0;
09942c65 1670 ppgtt->base.total = I915_PDES * GEN6_PTES * PAGE_SIZE;
87d60b63 1671 ppgtt->debug_dump = gen6_dump_ppgtt;
1d2a314c 1672
44159ddb 1673 ppgtt->pd.base.ggtt_offset =
07749ef3 1674 ppgtt->node.start / PAGE_SIZE * sizeof(gen6_pte_t);
1d2a314c 1675
678d96fb 1676 ppgtt->pd_addr = (gen6_pte_t __iomem *)dev_priv->gtt.gsm +
44159ddb 1677 ppgtt->pd.base.ggtt_offset / sizeof(gen6_pte_t);
678d96fb 1678
5c5f6457 1679 gen6_scratch_va_range(ppgtt, 0, ppgtt->base.total);
1d2a314c 1680
678d96fb
BW
1681 gen6_write_page_range(dev_priv, &ppgtt->pd, 0, ppgtt->base.total);
1682
440fd528 1683 DRM_DEBUG_DRIVER("Allocated pde space (%lldM) at GTT entry: %llx\n",
b146520f
BW
1684 ppgtt->node.size >> 20,
1685 ppgtt->node.start / PAGE_SIZE);
3440d265 1686
fa76da34 1687 DRM_DEBUG("Adding PPGTT at offset %x\n",
44159ddb 1688 ppgtt->pd.base.ggtt_offset << 10);
fa76da34 1689
b146520f 1690 return 0;
3440d265
DV
1691}
1692
5c5f6457 1693static int __hw_ppgtt_init(struct drm_device *dev, struct i915_hw_ppgtt *ppgtt)
3440d265 1694{
853ba5d2 1695 ppgtt->base.dev = dev;
3440d265 1696
3ed124b2 1697 if (INTEL_INFO(dev)->gen < 8)
5c5f6457 1698 return gen6_ppgtt_init(ppgtt);
3ed124b2 1699 else
d7b2633d 1700 return gen8_ppgtt_init(ppgtt);
fa76da34 1701}
c114f76a 1702
fa76da34
DV
1703int i915_ppgtt_init(struct drm_device *dev, struct i915_hw_ppgtt *ppgtt)
1704{
1705 struct drm_i915_private *dev_priv = dev->dev_private;
1706 int ret = 0;
3ed124b2 1707
5c5f6457 1708 ret = __hw_ppgtt_init(dev, ppgtt);
fa76da34 1709 if (ret == 0) {
c7c48dfd 1710 kref_init(&ppgtt->ref);
93bd8649
BW
1711 drm_mm_init(&ppgtt->base.mm, ppgtt->base.start,
1712 ppgtt->base.total);
7e0d96bc 1713 i915_init_vm(dev_priv, &ppgtt->base);
93bd8649 1714 }
1d2a314c
DV
1715
1716 return ret;
1717}
1718
82460d97
DV
1719int i915_ppgtt_init_hw(struct drm_device *dev)
1720{
671b5013
TD
1721 /* In the case of execlists, PPGTT is enabled by the context descriptor
1722 * and the PDPs are contained within the context itself. We don't
1723 * need to do anything here. */
1724 if (i915.enable_execlists)
1725 return 0;
1726
82460d97
DV
1727 if (!USES_PPGTT(dev))
1728 return 0;
1729
1730 if (IS_GEN6(dev))
1731 gen6_ppgtt_enable(dev);
1732 else if (IS_GEN7(dev))
1733 gen7_ppgtt_enable(dev);
1734 else if (INTEL_INFO(dev)->gen >= 8)
1735 gen8_ppgtt_enable(dev);
1736 else
5f77eeb0 1737 MISSING_CASE(INTEL_INFO(dev)->gen);
82460d97 1738
4ad2fd88
JH
1739 return 0;
1740}
1d2a314c 1741
b3dd6b96 1742int i915_ppgtt_init_ring(struct drm_i915_gem_request *req)
4ad2fd88 1743{
b3dd6b96 1744 struct drm_i915_private *dev_priv = req->ring->dev->dev_private;
4ad2fd88
JH
1745 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
1746
1747 if (i915.enable_execlists)
1748 return 0;
1749
1750 if (!ppgtt)
1751 return 0;
1752
e85b26dc 1753 return ppgtt->switch_mm(ppgtt, req);
1d2a314c 1754}
4ad2fd88 1755
4d884705
DV
1756struct i915_hw_ppgtt *
1757i915_ppgtt_create(struct drm_device *dev, struct drm_i915_file_private *fpriv)
1758{
1759 struct i915_hw_ppgtt *ppgtt;
1760 int ret;
1761
1762 ppgtt = kzalloc(sizeof(*ppgtt), GFP_KERNEL);
1763 if (!ppgtt)
1764 return ERR_PTR(-ENOMEM);
1765
1766 ret = i915_ppgtt_init(dev, ppgtt);
1767 if (ret) {
1768 kfree(ppgtt);
1769 return ERR_PTR(ret);
1770 }
1771
1772 ppgtt->file_priv = fpriv;
1773
198c974d
DCS
1774 trace_i915_ppgtt_create(&ppgtt->base);
1775
4d884705
DV
1776 return ppgtt;
1777}
1778
ee960be7
DV
1779void i915_ppgtt_release(struct kref *kref)
1780{
1781 struct i915_hw_ppgtt *ppgtt =
1782 container_of(kref, struct i915_hw_ppgtt, ref);
1783
198c974d
DCS
1784 trace_i915_ppgtt_release(&ppgtt->base);
1785
ee960be7
DV
1786 /* vmas should already be unbound */
1787 WARN_ON(!list_empty(&ppgtt->base.active_list));
1788 WARN_ON(!list_empty(&ppgtt->base.inactive_list));
1789
19dd120c
DV
1790 list_del(&ppgtt->base.global_link);
1791 drm_mm_takedown(&ppgtt->base.mm);
1792
ee960be7
DV
1793 ppgtt->base.cleanup(&ppgtt->base);
1794 kfree(ppgtt);
1795}
1d2a314c 1796
a81cc00c
BW
1797extern int intel_iommu_gfx_mapped;
1798/* Certain Gen5 chipsets require require idling the GPU before
1799 * unmapping anything from the GTT when VT-d is enabled.
1800 */
2c642b07 1801static bool needs_idle_maps(struct drm_device *dev)
a81cc00c
BW
1802{
1803#ifdef CONFIG_INTEL_IOMMU
1804 /* Query intel_iommu to see if we need the workaround. Presumably that
1805 * was loaded first.
1806 */
1807 if (IS_GEN5(dev) && IS_MOBILE(dev) && intel_iommu_gfx_mapped)
1808 return true;
1809#endif
1810 return false;
1811}
1812
5c042287
BW
1813static bool do_idling(struct drm_i915_private *dev_priv)
1814{
1815 bool ret = dev_priv->mm.interruptible;
1816
a81cc00c 1817 if (unlikely(dev_priv->gtt.do_idle_maps)) {
5c042287 1818 dev_priv->mm.interruptible = false;
b2da9fe5 1819 if (i915_gpu_idle(dev_priv->dev)) {
5c042287
BW
1820 DRM_ERROR("Couldn't idle GPU\n");
1821 /* Wait a bit, in hopes it avoids the hang */
1822 udelay(10);
1823 }
1824 }
1825
1826 return ret;
1827}
1828
1829static void undo_idling(struct drm_i915_private *dev_priv, bool interruptible)
1830{
a81cc00c 1831 if (unlikely(dev_priv->gtt.do_idle_maps))
5c042287
BW
1832 dev_priv->mm.interruptible = interruptible;
1833}
1834
828c7908
BW
1835void i915_check_and_clear_faults(struct drm_device *dev)
1836{
1837 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 1838 struct intel_engine_cs *ring;
828c7908
BW
1839 int i;
1840
1841 if (INTEL_INFO(dev)->gen < 6)
1842 return;
1843
1844 for_each_ring(ring, dev_priv, i) {
1845 u32 fault_reg;
1846 fault_reg = I915_READ(RING_FAULT_REG(ring));
1847 if (fault_reg & RING_FAULT_VALID) {
1848 DRM_DEBUG_DRIVER("Unexpected fault\n"
59a5d290 1849 "\tAddr: 0x%08lx\n"
828c7908
BW
1850 "\tAddress space: %s\n"
1851 "\tSource ID: %d\n"
1852 "\tType: %d\n",
1853 fault_reg & PAGE_MASK,
1854 fault_reg & RING_FAULT_GTTSEL_MASK ? "GGTT" : "PPGTT",
1855 RING_FAULT_SRCID(fault_reg),
1856 RING_FAULT_FAULT_TYPE(fault_reg));
1857 I915_WRITE(RING_FAULT_REG(ring),
1858 fault_reg & ~RING_FAULT_VALID);
1859 }
1860 }
1861 POSTING_READ(RING_FAULT_REG(&dev_priv->ring[RCS]));
1862}
1863
91e56499
CW
1864static void i915_ggtt_flush(struct drm_i915_private *dev_priv)
1865{
1866 if (INTEL_INFO(dev_priv->dev)->gen < 6) {
1867 intel_gtt_chipset_flush();
1868 } else {
1869 I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN);
1870 POSTING_READ(GFX_FLSH_CNTL_GEN6);
1871 }
1872}
1873
828c7908
BW
1874void i915_gem_suspend_gtt_mappings(struct drm_device *dev)
1875{
1876 struct drm_i915_private *dev_priv = dev->dev_private;
1877
1878 /* Don't bother messing with faults pre GEN6 as we have little
1879 * documentation supporting that it's a good idea.
1880 */
1881 if (INTEL_INFO(dev)->gen < 6)
1882 return;
1883
1884 i915_check_and_clear_faults(dev);
1885
1886 dev_priv->gtt.base.clear_range(&dev_priv->gtt.base,
782f1495
BW
1887 dev_priv->gtt.base.start,
1888 dev_priv->gtt.base.total,
e568af1c 1889 true);
91e56499
CW
1890
1891 i915_ggtt_flush(dev_priv);
828c7908
BW
1892}
1893
74163907 1894int i915_gem_gtt_prepare_object(struct drm_i915_gem_object *obj)
7c2e6fdf 1895{
9da3da66
CW
1896 if (!dma_map_sg(&obj->base.dev->pdev->dev,
1897 obj->pages->sgl, obj->pages->nents,
1898 PCI_DMA_BIDIRECTIONAL))
1899 return -ENOSPC;
1900
1901 return 0;
7c2e6fdf
DV
1902}
1903
2c642b07 1904static void gen8_set_pte(void __iomem *addr, gen8_pte_t pte)
94ec8f61
BW
1905{
1906#ifdef writeq
1907 writeq(pte, addr);
1908#else
1909 iowrite32((u32)pte, addr);
1910 iowrite32(pte >> 32, addr + 4);
1911#endif
1912}
1913
1914static void gen8_ggtt_insert_entries(struct i915_address_space *vm,
1915 struct sg_table *st,
782f1495 1916 uint64_t start,
24f3a8cf 1917 enum i915_cache_level level, u32 unused)
94ec8f61
BW
1918{
1919 struct drm_i915_private *dev_priv = vm->dev->dev_private;
782f1495 1920 unsigned first_entry = start >> PAGE_SHIFT;
07749ef3
MT
1921 gen8_pte_t __iomem *gtt_entries =
1922 (gen8_pte_t __iomem *)dev_priv->gtt.gsm + first_entry;
94ec8f61
BW
1923 int i = 0;
1924 struct sg_page_iter sg_iter;
57007df7 1925 dma_addr_t addr = 0; /* shut up gcc */
94ec8f61
BW
1926
1927 for_each_sg_page(st->sgl, &sg_iter, st->nents, 0) {
1928 addr = sg_dma_address(sg_iter.sg) +
1929 (sg_iter.sg_pgoffset << PAGE_SHIFT);
1930 gen8_set_pte(&gtt_entries[i],
1931 gen8_pte_encode(addr, level, true));
1932 i++;
1933 }
1934
1935 /*
1936 * XXX: This serves as a posting read to make sure that the PTE has
1937 * actually been updated. There is some concern that even though
1938 * registers and PTEs are within the same BAR that they are potentially
1939 * of NUMA access patterns. Therefore, even with the way we assume
1940 * hardware should work, we must keep this posting read for paranoia.
1941 */
1942 if (i != 0)
1943 WARN_ON(readq(&gtt_entries[i-1])
1944 != gen8_pte_encode(addr, level, true));
1945
94ec8f61
BW
1946 /* This next bit makes the above posting read even more important. We
1947 * want to flush the TLBs only after we're certain all the PTE updates
1948 * have finished.
1949 */
1950 I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN);
1951 POSTING_READ(GFX_FLSH_CNTL_GEN6);
94ec8f61
BW
1952}
1953
e76e9aeb
BW
1954/*
1955 * Binds an object into the global gtt with the specified cache level. The object
1956 * will be accessible to the GPU via commands whose operands reference offsets
1957 * within the global GTT as well as accessible by the GPU through the GMADR
1958 * mapped BAR (dev_priv->mm.gtt->gtt).
1959 */
853ba5d2 1960static void gen6_ggtt_insert_entries(struct i915_address_space *vm,
7faf1ab2 1961 struct sg_table *st,
782f1495 1962 uint64_t start,
24f3a8cf 1963 enum i915_cache_level level, u32 flags)
e76e9aeb 1964{
853ba5d2 1965 struct drm_i915_private *dev_priv = vm->dev->dev_private;
782f1495 1966 unsigned first_entry = start >> PAGE_SHIFT;
07749ef3
MT
1967 gen6_pte_t __iomem *gtt_entries =
1968 (gen6_pte_t __iomem *)dev_priv->gtt.gsm + first_entry;
6e995e23
ID
1969 int i = 0;
1970 struct sg_page_iter sg_iter;
57007df7 1971 dma_addr_t addr = 0;
e76e9aeb 1972
6e995e23 1973 for_each_sg_page(st->sgl, &sg_iter, st->nents, 0) {
2db76d7c 1974 addr = sg_page_iter_dma_address(&sg_iter);
24f3a8cf 1975 iowrite32(vm->pte_encode(addr, level, true, flags), &gtt_entries[i]);
6e995e23 1976 i++;
e76e9aeb
BW
1977 }
1978
e76e9aeb
BW
1979 /* XXX: This serves as a posting read to make sure that the PTE has
1980 * actually been updated. There is some concern that even though
1981 * registers and PTEs are within the same BAR that they are potentially
1982 * of NUMA access patterns. Therefore, even with the way we assume
1983 * hardware should work, we must keep this posting read for paranoia.
1984 */
57007df7
PM
1985 if (i != 0) {
1986 unsigned long gtt = readl(&gtt_entries[i-1]);
1987 WARN_ON(gtt != vm->pte_encode(addr, level, true, flags));
1988 }
0f9b91c7
BW
1989
1990 /* This next bit makes the above posting read even more important. We
1991 * want to flush the TLBs only after we're certain all the PTE updates
1992 * have finished.
1993 */
1994 I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN);
1995 POSTING_READ(GFX_FLSH_CNTL_GEN6);
e76e9aeb
BW
1996}
1997
94ec8f61 1998static void gen8_ggtt_clear_range(struct i915_address_space *vm,
782f1495
BW
1999 uint64_t start,
2000 uint64_t length,
94ec8f61
BW
2001 bool use_scratch)
2002{
2003 struct drm_i915_private *dev_priv = vm->dev->dev_private;
782f1495
BW
2004 unsigned first_entry = start >> PAGE_SHIFT;
2005 unsigned num_entries = length >> PAGE_SHIFT;
07749ef3
MT
2006 gen8_pte_t scratch_pte, __iomem *gtt_base =
2007 (gen8_pte_t __iomem *) dev_priv->gtt.gsm + first_entry;
94ec8f61
BW
2008 const int max_entries = gtt_total_entries(dev_priv->gtt) - first_entry;
2009 int i;
2010
2011 if (WARN(num_entries > max_entries,
2012 "First entry = %d; Num entries = %d (max=%d)\n",
2013 first_entry, num_entries, max_entries))
2014 num_entries = max_entries;
2015
c114f76a 2016 scratch_pte = gen8_pte_encode(px_dma(vm->scratch_page),
94ec8f61
BW
2017 I915_CACHE_LLC,
2018 use_scratch);
2019 for (i = 0; i < num_entries; i++)
2020 gen8_set_pte(&gtt_base[i], scratch_pte);
2021 readl(gtt_base);
2022}
2023
853ba5d2 2024static void gen6_ggtt_clear_range(struct i915_address_space *vm,
782f1495
BW
2025 uint64_t start,
2026 uint64_t length,
828c7908 2027 bool use_scratch)
7faf1ab2 2028{
853ba5d2 2029 struct drm_i915_private *dev_priv = vm->dev->dev_private;
782f1495
BW
2030 unsigned first_entry = start >> PAGE_SHIFT;
2031 unsigned num_entries = length >> PAGE_SHIFT;
07749ef3
MT
2032 gen6_pte_t scratch_pte, __iomem *gtt_base =
2033 (gen6_pte_t __iomem *) dev_priv->gtt.gsm + first_entry;
a54c0c27 2034 const int max_entries = gtt_total_entries(dev_priv->gtt) - first_entry;
7faf1ab2
DV
2035 int i;
2036
2037 if (WARN(num_entries > max_entries,
2038 "First entry = %d; Num entries = %d (max=%d)\n",
2039 first_entry, num_entries, max_entries))
2040 num_entries = max_entries;
2041
c114f76a
MK
2042 scratch_pte = vm->pte_encode(px_dma(vm->scratch_page),
2043 I915_CACHE_LLC, use_scratch, 0);
828c7908 2044
7faf1ab2
DV
2045 for (i = 0; i < num_entries; i++)
2046 iowrite32(scratch_pte, &gtt_base[i]);
2047 readl(gtt_base);
2048}
2049
d369d2d9
DV
2050static void i915_ggtt_insert_entries(struct i915_address_space *vm,
2051 struct sg_table *pages,
2052 uint64_t start,
2053 enum i915_cache_level cache_level, u32 unused)
7faf1ab2
DV
2054{
2055 unsigned int flags = (cache_level == I915_CACHE_NONE) ?
2056 AGP_USER_MEMORY : AGP_USER_CACHED_MEMORY;
2057
d369d2d9 2058 intel_gtt_insert_sg_entries(pages, start >> PAGE_SHIFT, flags);
0875546c 2059
7faf1ab2
DV
2060}
2061
853ba5d2 2062static void i915_ggtt_clear_range(struct i915_address_space *vm,
782f1495
BW
2063 uint64_t start,
2064 uint64_t length,
828c7908 2065 bool unused)
7faf1ab2 2066{
782f1495
BW
2067 unsigned first_entry = start >> PAGE_SHIFT;
2068 unsigned num_entries = length >> PAGE_SHIFT;
7faf1ab2
DV
2069 intel_gtt_clear_range(first_entry, num_entries);
2070}
2071
70b9f6f8
DV
2072static int ggtt_bind_vma(struct i915_vma *vma,
2073 enum i915_cache_level cache_level,
2074 u32 flags)
d5bd1449 2075{
6f65e29a 2076 struct drm_device *dev = vma->vm->dev;
7faf1ab2 2077 struct drm_i915_private *dev_priv = dev->dev_private;
6f65e29a 2078 struct drm_i915_gem_object *obj = vma->obj;
ec7adb6e 2079 struct sg_table *pages = obj->pages;
f329f5f6 2080 u32 pte_flags = 0;
70b9f6f8
DV
2081 int ret;
2082
2083 ret = i915_get_ggtt_vma_pages(vma);
2084 if (ret)
2085 return ret;
2086 pages = vma->ggtt_view.pages;
7faf1ab2 2087
24f3a8cf
AG
2088 /* Currently applicable only to VLV */
2089 if (obj->gt_ro)
f329f5f6 2090 pte_flags |= PTE_READ_ONLY;
24f3a8cf 2091
ec7adb6e 2092
6f65e29a 2093 if (!dev_priv->mm.aliasing_ppgtt || flags & GLOBAL_BIND) {
0875546c
DV
2094 vma->vm->insert_entries(vma->vm, pages,
2095 vma->node.start,
2096 cache_level, pte_flags);
d0e30adc
CW
2097
2098 /* Note the inconsistency here is due to absence of the
2099 * aliasing ppgtt on gen4 and earlier. Though we always
2100 * request PIN_USER for execbuffer (translated to LOCAL_BIND),
2101 * without the appgtt, we cannot honour that request and so
2102 * must substitute it with a global binding. Since we do this
2103 * behind the upper layers back, we need to explicitly set
2104 * the bound flag ourselves.
2105 */
2106 vma->bound |= GLOBAL_BIND;
2107
6f65e29a 2108 }
d5bd1449 2109
0875546c 2110 if (dev_priv->mm.aliasing_ppgtt && flags & LOCAL_BIND) {
6f65e29a 2111 struct i915_hw_ppgtt *appgtt = dev_priv->mm.aliasing_ppgtt;
ec7adb6e 2112 appgtt->base.insert_entries(&appgtt->base, pages,
782f1495 2113 vma->node.start,
f329f5f6 2114 cache_level, pte_flags);
6f65e29a 2115 }
70b9f6f8
DV
2116
2117 return 0;
d5bd1449
CW
2118}
2119
6f65e29a 2120static void ggtt_unbind_vma(struct i915_vma *vma)
74163907 2121{
6f65e29a 2122 struct drm_device *dev = vma->vm->dev;
7faf1ab2 2123 struct drm_i915_private *dev_priv = dev->dev_private;
6f65e29a 2124 struct drm_i915_gem_object *obj = vma->obj;
06615ee5
JL
2125 const uint64_t size = min_t(uint64_t,
2126 obj->base.size,
2127 vma->node.size);
6f65e29a 2128
aff43766 2129 if (vma->bound & GLOBAL_BIND) {
782f1495
BW
2130 vma->vm->clear_range(vma->vm,
2131 vma->node.start,
06615ee5 2132 size,
6f65e29a 2133 true);
6f65e29a 2134 }
74898d7e 2135
0875546c 2136 if (dev_priv->mm.aliasing_ppgtt && vma->bound & LOCAL_BIND) {
6f65e29a 2137 struct i915_hw_ppgtt *appgtt = dev_priv->mm.aliasing_ppgtt;
06615ee5 2138
6f65e29a 2139 appgtt->base.clear_range(&appgtt->base,
782f1495 2140 vma->node.start,
06615ee5 2141 size,
6f65e29a 2142 true);
6f65e29a 2143 }
74163907
DV
2144}
2145
2146void i915_gem_gtt_finish_object(struct drm_i915_gem_object *obj)
7c2e6fdf 2147{
5c042287
BW
2148 struct drm_device *dev = obj->base.dev;
2149 struct drm_i915_private *dev_priv = dev->dev_private;
2150 bool interruptible;
2151
2152 interruptible = do_idling(dev_priv);
2153
5ec5b516
ID
2154 dma_unmap_sg(&dev->pdev->dev, obj->pages->sgl, obj->pages->nents,
2155 PCI_DMA_BIDIRECTIONAL);
5c042287
BW
2156
2157 undo_idling(dev_priv, interruptible);
7c2e6fdf 2158}
644ec02b 2159
42d6ab48
CW
2160static void i915_gtt_color_adjust(struct drm_mm_node *node,
2161 unsigned long color,
440fd528
TR
2162 u64 *start,
2163 u64 *end)
42d6ab48
CW
2164{
2165 if (node->color != color)
2166 *start += 4096;
2167
2168 if (!list_empty(&node->node_list)) {
2169 node = list_entry(node->node_list.next,
2170 struct drm_mm_node,
2171 node_list);
2172 if (node->allocated && node->color != color)
2173 *end -= 4096;
2174 }
2175}
fbe5d36e 2176
f548c0e9
DV
2177static int i915_gem_setup_global_gtt(struct drm_device *dev,
2178 unsigned long start,
2179 unsigned long mappable_end,
2180 unsigned long end)
644ec02b 2181{
e78891ca
BW
2182 /* Let GEM Manage all of the aperture.
2183 *
2184 * However, leave one page at the end still bound to the scratch page.
2185 * There are a number of places where the hardware apparently prefetches
2186 * past the end of the object, and we've seen multiple hangs with the
2187 * GPU head pointer stuck in a batchbuffer bound at the last page of the
2188 * aperture. One page should be enough to keep any prefetching inside
2189 * of the aperture.
2190 */
40d74980
BW
2191 struct drm_i915_private *dev_priv = dev->dev_private;
2192 struct i915_address_space *ggtt_vm = &dev_priv->gtt.base;
ed2f3452
CW
2193 struct drm_mm_node *entry;
2194 struct drm_i915_gem_object *obj;
2195 unsigned long hole_start, hole_end;
fa76da34 2196 int ret;
644ec02b 2197
35451cb6
BW
2198 BUG_ON(mappable_end > end);
2199
ed2f3452 2200 /* Subtract the guard page ... */
40d74980 2201 drm_mm_init(&ggtt_vm->mm, start, end - start - PAGE_SIZE);
5dda8fa3
YZ
2202
2203 dev_priv->gtt.base.start = start;
2204 dev_priv->gtt.base.total = end - start;
2205
2206 if (intel_vgpu_active(dev)) {
2207 ret = intel_vgt_balloon(dev);
2208 if (ret)
2209 return ret;
2210 }
2211
42d6ab48 2212 if (!HAS_LLC(dev))
93bd8649 2213 dev_priv->gtt.base.mm.color_adjust = i915_gtt_color_adjust;
644ec02b 2214
ed2f3452 2215 /* Mark any preallocated objects as occupied */
35c20a60 2216 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
40d74980 2217 struct i915_vma *vma = i915_gem_obj_to_vma(obj, ggtt_vm);
fa76da34 2218
edd41a87 2219 DRM_DEBUG_KMS("reserving preallocated space: %lx + %zx\n",
c6cfb325
BW
2220 i915_gem_obj_ggtt_offset(obj), obj->base.size);
2221
2222 WARN_ON(i915_gem_obj_ggtt_bound(obj));
40d74980 2223 ret = drm_mm_reserve_node(&ggtt_vm->mm, &vma->node);
6c5566a8
DV
2224 if (ret) {
2225 DRM_DEBUG_KMS("Reservation failed: %i\n", ret);
2226 return ret;
2227 }
aff43766 2228 vma->bound |= GLOBAL_BIND;
ed2f3452
CW
2229 }
2230
ed2f3452 2231 /* Clear any non-preallocated blocks */
40d74980 2232 drm_mm_for_each_hole(entry, &ggtt_vm->mm, hole_start, hole_end) {
ed2f3452
CW
2233 DRM_DEBUG_KMS("clearing unused GTT space: [%lx, %lx]\n",
2234 hole_start, hole_end);
782f1495
BW
2235 ggtt_vm->clear_range(ggtt_vm, hole_start,
2236 hole_end - hole_start, true);
ed2f3452
CW
2237 }
2238
2239 /* And finally clear the reserved guard page */
782f1495 2240 ggtt_vm->clear_range(ggtt_vm, end - PAGE_SIZE, PAGE_SIZE, true);
6c5566a8 2241
fa76da34
DV
2242 if (USES_PPGTT(dev) && !USES_FULL_PPGTT(dev)) {
2243 struct i915_hw_ppgtt *ppgtt;
2244
2245 ppgtt = kzalloc(sizeof(*ppgtt), GFP_KERNEL);
2246 if (!ppgtt)
2247 return -ENOMEM;
2248
5c5f6457
DV
2249 ret = __hw_ppgtt_init(dev, ppgtt);
2250 if (ret) {
2251 ppgtt->base.cleanup(&ppgtt->base);
2252 kfree(ppgtt);
2253 return ret;
2254 }
2255
2256 if (ppgtt->base.allocate_va_range)
2257 ret = ppgtt->base.allocate_va_range(&ppgtt->base, 0,
2258 ppgtt->base.total);
4933d519 2259 if (ret) {
061dd493 2260 ppgtt->base.cleanup(&ppgtt->base);
4933d519 2261 kfree(ppgtt);
fa76da34 2262 return ret;
4933d519 2263 }
fa76da34 2264
5c5f6457
DV
2265 ppgtt->base.clear_range(&ppgtt->base,
2266 ppgtt->base.start,
2267 ppgtt->base.total,
2268 true);
2269
fa76da34
DV
2270 dev_priv->mm.aliasing_ppgtt = ppgtt;
2271 }
2272
6c5566a8 2273 return 0;
e76e9aeb
BW
2274}
2275
d7e5008f
BW
2276void i915_gem_init_global_gtt(struct drm_device *dev)
2277{
2278 struct drm_i915_private *dev_priv = dev->dev_private;
c44ef60e 2279 u64 gtt_size, mappable_size;
d7e5008f 2280
853ba5d2 2281 gtt_size = dev_priv->gtt.base.total;
93d18799 2282 mappable_size = dev_priv->gtt.mappable_end;
d7e5008f 2283
e78891ca 2284 i915_gem_setup_global_gtt(dev, 0, mappable_size, gtt_size);
e76e9aeb
BW
2285}
2286
90d0a0e8
DV
2287void i915_global_gtt_cleanup(struct drm_device *dev)
2288{
2289 struct drm_i915_private *dev_priv = dev->dev_private;
2290 struct i915_address_space *vm = &dev_priv->gtt.base;
2291
70e32544
DV
2292 if (dev_priv->mm.aliasing_ppgtt) {
2293 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
2294
2295 ppgtt->base.cleanup(&ppgtt->base);
2296 }
2297
90d0a0e8 2298 if (drm_mm_initialized(&vm->mm)) {
5dda8fa3
YZ
2299 if (intel_vgpu_active(dev))
2300 intel_vgt_deballoon();
2301
90d0a0e8
DV
2302 drm_mm_takedown(&vm->mm);
2303 list_del(&vm->global_link);
2304 }
2305
2306 vm->cleanup(vm);
2307}
70e32544 2308
2c642b07 2309static unsigned int gen6_get_total_gtt_size(u16 snb_gmch_ctl)
e76e9aeb
BW
2310{
2311 snb_gmch_ctl >>= SNB_GMCH_GGMS_SHIFT;
2312 snb_gmch_ctl &= SNB_GMCH_GGMS_MASK;
2313 return snb_gmch_ctl << 20;
2314}
2315
2c642b07 2316static unsigned int gen8_get_total_gtt_size(u16 bdw_gmch_ctl)
9459d252
BW
2317{
2318 bdw_gmch_ctl >>= BDW_GMCH_GGMS_SHIFT;
2319 bdw_gmch_ctl &= BDW_GMCH_GGMS_MASK;
2320 if (bdw_gmch_ctl)
2321 bdw_gmch_ctl = 1 << bdw_gmch_ctl;
562d55d9
BW
2322
2323#ifdef CONFIG_X86_32
2324 /* Limit 32b platforms to a 2GB GGTT: 4 << 20 / pte size * PAGE_SIZE */
2325 if (bdw_gmch_ctl > 4)
2326 bdw_gmch_ctl = 4;
2327#endif
2328
9459d252
BW
2329 return bdw_gmch_ctl << 20;
2330}
2331
2c642b07 2332static unsigned int chv_get_total_gtt_size(u16 gmch_ctrl)
d7f25f23
DL
2333{
2334 gmch_ctrl >>= SNB_GMCH_GGMS_SHIFT;
2335 gmch_ctrl &= SNB_GMCH_GGMS_MASK;
2336
2337 if (gmch_ctrl)
2338 return 1 << (20 + gmch_ctrl);
2339
2340 return 0;
2341}
2342
2c642b07 2343static size_t gen6_get_stolen_size(u16 snb_gmch_ctl)
e76e9aeb
BW
2344{
2345 snb_gmch_ctl >>= SNB_GMCH_GMS_SHIFT;
2346 snb_gmch_ctl &= SNB_GMCH_GMS_MASK;
2347 return snb_gmch_ctl << 25; /* 32 MB units */
2348}
2349
2c642b07 2350static size_t gen8_get_stolen_size(u16 bdw_gmch_ctl)
9459d252
BW
2351{
2352 bdw_gmch_ctl >>= BDW_GMCH_GMS_SHIFT;
2353 bdw_gmch_ctl &= BDW_GMCH_GMS_MASK;
2354 return bdw_gmch_ctl << 25; /* 32 MB units */
2355}
2356
d7f25f23
DL
2357static size_t chv_get_stolen_size(u16 gmch_ctrl)
2358{
2359 gmch_ctrl >>= SNB_GMCH_GMS_SHIFT;
2360 gmch_ctrl &= SNB_GMCH_GMS_MASK;
2361
2362 /*
2363 * 0x0 to 0x10: 32MB increments starting at 0MB
2364 * 0x11 to 0x16: 4MB increments starting at 8MB
2365 * 0x17 to 0x1d: 4MB increments start at 36MB
2366 */
2367 if (gmch_ctrl < 0x11)
2368 return gmch_ctrl << 25;
2369 else if (gmch_ctrl < 0x17)
2370 return (gmch_ctrl - 0x11 + 2) << 22;
2371 else
2372 return (gmch_ctrl - 0x17 + 9) << 22;
2373}
2374
66375014
DL
2375static size_t gen9_get_stolen_size(u16 gen9_gmch_ctl)
2376{
2377 gen9_gmch_ctl >>= BDW_GMCH_GMS_SHIFT;
2378 gen9_gmch_ctl &= BDW_GMCH_GMS_MASK;
2379
2380 if (gen9_gmch_ctl < 0xf0)
2381 return gen9_gmch_ctl << 25; /* 32 MB units */
2382 else
2383 /* 4MB increments starting at 0xf0 for 4MB */
2384 return (gen9_gmch_ctl - 0xf0 + 1) << 22;
2385}
2386
63340133
BW
2387static int ggtt_probe_common(struct drm_device *dev,
2388 size_t gtt_size)
2389{
2390 struct drm_i915_private *dev_priv = dev->dev_private;
4ad2af1e 2391 struct i915_page_scratch *scratch_page;
21c34607 2392 phys_addr_t gtt_phys_addr;
63340133
BW
2393
2394 /* For Modern GENs the PTEs and register space are split in the BAR */
21c34607 2395 gtt_phys_addr = pci_resource_start(dev->pdev, 0) +
63340133
BW
2396 (pci_resource_len(dev->pdev, 0) / 2);
2397
2a073f89
ID
2398 /*
2399 * On BXT writes larger than 64 bit to the GTT pagetable range will be
2400 * dropped. For WC mappings in general we have 64 byte burst writes
2401 * when the WC buffer is flushed, so we can't use it, but have to
2402 * resort to an uncached mapping. The WC issue is easily caught by the
2403 * readback check when writing GTT PTE entries.
2404 */
2405 if (IS_BROXTON(dev))
2406 dev_priv->gtt.gsm = ioremap_nocache(gtt_phys_addr, gtt_size);
2407 else
2408 dev_priv->gtt.gsm = ioremap_wc(gtt_phys_addr, gtt_size);
63340133
BW
2409 if (!dev_priv->gtt.gsm) {
2410 DRM_ERROR("Failed to map the gtt page table\n");
2411 return -ENOMEM;
2412 }
2413
4ad2af1e
MK
2414 scratch_page = alloc_scratch_page(dev);
2415 if (IS_ERR(scratch_page)) {
63340133
BW
2416 DRM_ERROR("Scratch setup failed\n");
2417 /* iounmap will also get called at remove, but meh */
2418 iounmap(dev_priv->gtt.gsm);
4ad2af1e 2419 return PTR_ERR(scratch_page);
63340133
BW
2420 }
2421
4ad2af1e
MK
2422 dev_priv->gtt.base.scratch_page = scratch_page;
2423
2424 return 0;
63340133
BW
2425}
2426
fbe5d36e
BW
2427/* The GGTT and PPGTT need a private PPAT setup in order to handle cacheability
2428 * bits. When using advanced contexts each context stores its own PAT, but
2429 * writing this data shouldn't be harmful even in those cases. */
ee0ce478 2430static void bdw_setup_private_ppat(struct drm_i915_private *dev_priv)
fbe5d36e 2431{
fbe5d36e
BW
2432 uint64_t pat;
2433
2434 pat = GEN8_PPAT(0, GEN8_PPAT_WB | GEN8_PPAT_LLC) | /* for normal objects, no eLLC */
2435 GEN8_PPAT(1, GEN8_PPAT_WC | GEN8_PPAT_LLCELLC) | /* for something pointing to ptes? */
2436 GEN8_PPAT(2, GEN8_PPAT_WT | GEN8_PPAT_LLCELLC) | /* for scanout with eLLC */
2437 GEN8_PPAT(3, GEN8_PPAT_UC) | /* Uncached objects, mostly for scanout */
2438 GEN8_PPAT(4, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(0)) |
2439 GEN8_PPAT(5, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(1)) |
2440 GEN8_PPAT(6, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(2)) |
2441 GEN8_PPAT(7, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(3));
2442
d6a8b72e
RV
2443 if (!USES_PPGTT(dev_priv->dev))
2444 /* Spec: "For GGTT, there is NO pat_sel[2:0] from the entry,
2445 * so RTL will always use the value corresponding to
2446 * pat_sel = 000".
2447 * So let's disable cache for GGTT to avoid screen corruptions.
2448 * MOCS still can be used though.
2449 * - System agent ggtt writes (i.e. cpu gtt mmaps) already work
2450 * before this patch, i.e. the same uncached + snooping access
2451 * like on gen6/7 seems to be in effect.
2452 * - So this just fixes blitter/render access. Again it looks
2453 * like it's not just uncached access, but uncached + snooping.
2454 * So we can still hold onto all our assumptions wrt cpu
2455 * clflushing on LLC machines.
2456 */
2457 pat = GEN8_PPAT(0, GEN8_PPAT_UC);
2458
fbe5d36e
BW
2459 /* XXX: spec defines this as 2 distinct registers. It's unclear if a 64b
2460 * write would work. */
2461 I915_WRITE(GEN8_PRIVATE_PAT, pat);
2462 I915_WRITE(GEN8_PRIVATE_PAT + 4, pat >> 32);
2463}
2464
ee0ce478
VS
2465static void chv_setup_private_ppat(struct drm_i915_private *dev_priv)
2466{
2467 uint64_t pat;
2468
2469 /*
2470 * Map WB on BDW to snooped on CHV.
2471 *
2472 * Only the snoop bit has meaning for CHV, the rest is
2473 * ignored.
2474 *
cf3d262e
VS
2475 * The hardware will never snoop for certain types of accesses:
2476 * - CPU GTT (GMADR->GGTT->no snoop->memory)
2477 * - PPGTT page tables
2478 * - some other special cycles
2479 *
2480 * As with BDW, we also need to consider the following for GT accesses:
2481 * "For GGTT, there is NO pat_sel[2:0] from the entry,
2482 * so RTL will always use the value corresponding to
2483 * pat_sel = 000".
2484 * Which means we must set the snoop bit in PAT entry 0
2485 * in order to keep the global status page working.
ee0ce478
VS
2486 */
2487 pat = GEN8_PPAT(0, CHV_PPAT_SNOOP) |
2488 GEN8_PPAT(1, 0) |
2489 GEN8_PPAT(2, 0) |
2490 GEN8_PPAT(3, 0) |
2491 GEN8_PPAT(4, CHV_PPAT_SNOOP) |
2492 GEN8_PPAT(5, CHV_PPAT_SNOOP) |
2493 GEN8_PPAT(6, CHV_PPAT_SNOOP) |
2494 GEN8_PPAT(7, CHV_PPAT_SNOOP);
2495
2496 I915_WRITE(GEN8_PRIVATE_PAT, pat);
2497 I915_WRITE(GEN8_PRIVATE_PAT + 4, pat >> 32);
2498}
2499
63340133 2500static int gen8_gmch_probe(struct drm_device *dev,
c44ef60e 2501 u64 *gtt_total,
63340133
BW
2502 size_t *stolen,
2503 phys_addr_t *mappable_base,
c44ef60e 2504 u64 *mappable_end)
63340133
BW
2505{
2506 struct drm_i915_private *dev_priv = dev->dev_private;
c44ef60e 2507 u64 gtt_size;
63340133
BW
2508 u16 snb_gmch_ctl;
2509 int ret;
2510
2511 /* TODO: We're not aware of mappable constraints on gen8 yet */
2512 *mappable_base = pci_resource_start(dev->pdev, 2);
2513 *mappable_end = pci_resource_len(dev->pdev, 2);
2514
2515 if (!pci_set_dma_mask(dev->pdev, DMA_BIT_MASK(39)))
2516 pci_set_consistent_dma_mask(dev->pdev, DMA_BIT_MASK(39));
2517
2518 pci_read_config_word(dev->pdev, SNB_GMCH_CTRL, &snb_gmch_ctl);
2519
66375014
DL
2520 if (INTEL_INFO(dev)->gen >= 9) {
2521 *stolen = gen9_get_stolen_size(snb_gmch_ctl);
2522 gtt_size = gen8_get_total_gtt_size(snb_gmch_ctl);
2523 } else if (IS_CHERRYVIEW(dev)) {
d7f25f23
DL
2524 *stolen = chv_get_stolen_size(snb_gmch_ctl);
2525 gtt_size = chv_get_total_gtt_size(snb_gmch_ctl);
2526 } else {
2527 *stolen = gen8_get_stolen_size(snb_gmch_ctl);
2528 gtt_size = gen8_get_total_gtt_size(snb_gmch_ctl);
2529 }
63340133 2530
07749ef3 2531 *gtt_total = (gtt_size / sizeof(gen8_pte_t)) << PAGE_SHIFT;
63340133 2532
5a4e33a3 2533 if (IS_CHERRYVIEW(dev) || IS_BROXTON(dev))
ee0ce478
VS
2534 chv_setup_private_ppat(dev_priv);
2535 else
2536 bdw_setup_private_ppat(dev_priv);
fbe5d36e 2537
63340133
BW
2538 ret = ggtt_probe_common(dev, gtt_size);
2539
94ec8f61
BW
2540 dev_priv->gtt.base.clear_range = gen8_ggtt_clear_range;
2541 dev_priv->gtt.base.insert_entries = gen8_ggtt_insert_entries;
777dc5bb
DV
2542 dev_priv->gtt.base.bind_vma = ggtt_bind_vma;
2543 dev_priv->gtt.base.unbind_vma = ggtt_unbind_vma;
63340133
BW
2544
2545 return ret;
2546}
2547
baa09f5f 2548static int gen6_gmch_probe(struct drm_device *dev,
c44ef60e 2549 u64 *gtt_total,
41907ddc
BW
2550 size_t *stolen,
2551 phys_addr_t *mappable_base,
c44ef60e 2552 u64 *mappable_end)
e76e9aeb
BW
2553{
2554 struct drm_i915_private *dev_priv = dev->dev_private;
baa09f5f 2555 unsigned int gtt_size;
e76e9aeb 2556 u16 snb_gmch_ctl;
e76e9aeb
BW
2557 int ret;
2558
41907ddc
BW
2559 *mappable_base = pci_resource_start(dev->pdev, 2);
2560 *mappable_end = pci_resource_len(dev->pdev, 2);
2561
baa09f5f
BW
2562 /* 64/512MB is the current min/max we actually know of, but this is just
2563 * a coarse sanity check.
e76e9aeb 2564 */
41907ddc 2565 if ((*mappable_end < (64<<20) || (*mappable_end > (512<<20)))) {
c44ef60e 2566 DRM_ERROR("Unknown GMADR size (%llx)\n",
baa09f5f
BW
2567 dev_priv->gtt.mappable_end);
2568 return -ENXIO;
e76e9aeb
BW
2569 }
2570
e76e9aeb
BW
2571 if (!pci_set_dma_mask(dev->pdev, DMA_BIT_MASK(40)))
2572 pci_set_consistent_dma_mask(dev->pdev, DMA_BIT_MASK(40));
e76e9aeb 2573 pci_read_config_word(dev->pdev, SNB_GMCH_CTRL, &snb_gmch_ctl);
e76e9aeb 2574
c4ae25ec 2575 *stolen = gen6_get_stolen_size(snb_gmch_ctl);
a93e4161 2576
63340133 2577 gtt_size = gen6_get_total_gtt_size(snb_gmch_ctl);
07749ef3 2578 *gtt_total = (gtt_size / sizeof(gen6_pte_t)) << PAGE_SHIFT;
e76e9aeb 2579
63340133 2580 ret = ggtt_probe_common(dev, gtt_size);
e76e9aeb 2581
853ba5d2
BW
2582 dev_priv->gtt.base.clear_range = gen6_ggtt_clear_range;
2583 dev_priv->gtt.base.insert_entries = gen6_ggtt_insert_entries;
777dc5bb
DV
2584 dev_priv->gtt.base.bind_vma = ggtt_bind_vma;
2585 dev_priv->gtt.base.unbind_vma = ggtt_unbind_vma;
7faf1ab2 2586
e76e9aeb
BW
2587 return ret;
2588}
2589
853ba5d2 2590static void gen6_gmch_remove(struct i915_address_space *vm)
e76e9aeb 2591{
853ba5d2
BW
2592
2593 struct i915_gtt *gtt = container_of(vm, struct i915_gtt, base);
5ed16782 2594
853ba5d2 2595 iounmap(gtt->gsm);
4ad2af1e 2596 free_scratch_page(vm->dev, vm->scratch_page);
644ec02b 2597}
baa09f5f
BW
2598
2599static int i915_gmch_probe(struct drm_device *dev,
c44ef60e 2600 u64 *gtt_total,
41907ddc
BW
2601 size_t *stolen,
2602 phys_addr_t *mappable_base,
c44ef60e 2603 u64 *mappable_end)
baa09f5f
BW
2604{
2605 struct drm_i915_private *dev_priv = dev->dev_private;
2606 int ret;
2607
baa09f5f
BW
2608 ret = intel_gmch_probe(dev_priv->bridge_dev, dev_priv->dev->pdev, NULL);
2609 if (!ret) {
2610 DRM_ERROR("failed to set up gmch\n");
2611 return -EIO;
2612 }
2613
41907ddc 2614 intel_gtt_get(gtt_total, stolen, mappable_base, mappable_end);
baa09f5f
BW
2615
2616 dev_priv->gtt.do_idle_maps = needs_idle_maps(dev_priv->dev);
d369d2d9 2617 dev_priv->gtt.base.insert_entries = i915_ggtt_insert_entries;
853ba5d2 2618 dev_priv->gtt.base.clear_range = i915_ggtt_clear_range;
d369d2d9
DV
2619 dev_priv->gtt.base.bind_vma = ggtt_bind_vma;
2620 dev_priv->gtt.base.unbind_vma = ggtt_unbind_vma;
baa09f5f 2621
c0a7f818
CW
2622 if (unlikely(dev_priv->gtt.do_idle_maps))
2623 DRM_INFO("applying Ironlake quirks for intel_iommu\n");
2624
baa09f5f
BW
2625 return 0;
2626}
2627
853ba5d2 2628static void i915_gmch_remove(struct i915_address_space *vm)
baa09f5f
BW
2629{
2630 intel_gmch_remove();
2631}
2632
2633int i915_gem_gtt_init(struct drm_device *dev)
2634{
2635 struct drm_i915_private *dev_priv = dev->dev_private;
2636 struct i915_gtt *gtt = &dev_priv->gtt;
baa09f5f
BW
2637 int ret;
2638
baa09f5f 2639 if (INTEL_INFO(dev)->gen <= 5) {
b2f21b4d 2640 gtt->gtt_probe = i915_gmch_probe;
853ba5d2 2641 gtt->base.cleanup = i915_gmch_remove;
63340133 2642 } else if (INTEL_INFO(dev)->gen < 8) {
b2f21b4d 2643 gtt->gtt_probe = gen6_gmch_probe;
853ba5d2 2644 gtt->base.cleanup = gen6_gmch_remove;
4d15c145 2645 if (IS_HASWELL(dev) && dev_priv->ellc_size)
853ba5d2 2646 gtt->base.pte_encode = iris_pte_encode;
4d15c145 2647 else if (IS_HASWELL(dev))
853ba5d2 2648 gtt->base.pte_encode = hsw_pte_encode;
b2f21b4d 2649 else if (IS_VALLEYVIEW(dev))
853ba5d2 2650 gtt->base.pte_encode = byt_pte_encode;
350ec881
CW
2651 else if (INTEL_INFO(dev)->gen >= 7)
2652 gtt->base.pte_encode = ivb_pte_encode;
b2f21b4d 2653 else
350ec881 2654 gtt->base.pte_encode = snb_pte_encode;
63340133
BW
2655 } else {
2656 dev_priv->gtt.gtt_probe = gen8_gmch_probe;
2657 dev_priv->gtt.base.cleanup = gen6_gmch_remove;
baa09f5f
BW
2658 }
2659
c114f76a
MK
2660 gtt->base.dev = dev;
2661
853ba5d2 2662 ret = gtt->gtt_probe(dev, &gtt->base.total, &gtt->stolen_size,
b2f21b4d 2663 &gtt->mappable_base, &gtt->mappable_end);
a54c0c27 2664 if (ret)
baa09f5f 2665 return ret;
baa09f5f 2666
baa09f5f 2667 /* GMADR is the PCI mmio aperture into the global GTT. */
c44ef60e 2668 DRM_INFO("Memory usable by graphics device = %lluM\n",
853ba5d2 2669 gtt->base.total >> 20);
c44ef60e 2670 DRM_DEBUG_DRIVER("GMADR size = %lldM\n", gtt->mappable_end >> 20);
b2f21b4d 2671 DRM_DEBUG_DRIVER("GTT stolen size = %zdM\n", gtt->stolen_size >> 20);
5db6c735
DV
2672#ifdef CONFIG_INTEL_IOMMU
2673 if (intel_iommu_gfx_mapped)
2674 DRM_INFO("VT-d active for gfx access\n");
2675#endif
cfa7c862
DV
2676 /*
2677 * i915.enable_ppgtt is read-only, so do an early pass to validate the
2678 * user's requested state against the hardware/driver capabilities. We
2679 * do this now so that we can print out any log messages once rather
2680 * than every time we check intel_enable_ppgtt().
2681 */
2682 i915.enable_ppgtt = sanitize_enable_ppgtt(dev, i915.enable_ppgtt);
2683 DRM_DEBUG_DRIVER("ppgtt mode: %i\n", i915.enable_ppgtt);
baa09f5f
BW
2684
2685 return 0;
2686}
6f65e29a 2687
fa42331b
DV
2688void i915_gem_restore_gtt_mappings(struct drm_device *dev)
2689{
2690 struct drm_i915_private *dev_priv = dev->dev_private;
2691 struct drm_i915_gem_object *obj;
2692 struct i915_address_space *vm;
2c3d9984
TU
2693 struct i915_vma *vma;
2694 bool flush;
fa42331b
DV
2695
2696 i915_check_and_clear_faults(dev);
2697
2698 /* First fill our portion of the GTT with scratch pages */
2699 dev_priv->gtt.base.clear_range(&dev_priv->gtt.base,
2700 dev_priv->gtt.base.start,
2701 dev_priv->gtt.base.total,
2702 true);
2703
2c3d9984
TU
2704 /* Cache flush objects bound into GGTT and rebind them. */
2705 vm = &dev_priv->gtt.base;
fa42331b 2706 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
2c3d9984
TU
2707 flush = false;
2708 list_for_each_entry(vma, &obj->vma_list, vma_link) {
2709 if (vma->vm != vm)
2710 continue;
fa42331b 2711
2c3d9984
TU
2712 WARN_ON(i915_vma_bind(vma, obj->cache_level,
2713 PIN_UPDATE));
fa42331b 2714
2c3d9984
TU
2715 flush = true;
2716 }
2717
2718 if (flush)
2719 i915_gem_clflush_object(obj, obj->pin_display);
2720 }
fa42331b
DV
2721
2722 if (INTEL_INFO(dev)->gen >= 8) {
2723 if (IS_CHERRYVIEW(dev) || IS_BROXTON(dev))
2724 chv_setup_private_ppat(dev_priv);
2725 else
2726 bdw_setup_private_ppat(dev_priv);
2727
2728 return;
2729 }
2730
2731 if (USES_PPGTT(dev)) {
2732 list_for_each_entry(vm, &dev_priv->vm_list, global_link) {
2733 /* TODO: Perhaps it shouldn't be gen6 specific */
2734
2735 struct i915_hw_ppgtt *ppgtt =
2736 container_of(vm, struct i915_hw_ppgtt,
2737 base);
2738
2739 if (i915_is_ggtt(vm))
2740 ppgtt = dev_priv->mm.aliasing_ppgtt;
2741
2742 gen6_write_page_range(dev_priv, &ppgtt->pd,
2743 0, ppgtt->base.total);
2744 }
2745 }
2746
2747 i915_ggtt_flush(dev_priv);
2748}
2749
ec7adb6e
JL
2750static struct i915_vma *
2751__i915_gem_vma_create(struct drm_i915_gem_object *obj,
2752 struct i915_address_space *vm,
2753 const struct i915_ggtt_view *ggtt_view)
6f65e29a 2754{
dabde5c7 2755 struct i915_vma *vma;
6f65e29a 2756
ec7adb6e
JL
2757 if (WARN_ON(i915_is_ggtt(vm) != !!ggtt_view))
2758 return ERR_PTR(-EINVAL);
e20d2ab7
CW
2759
2760 vma = kmem_cache_zalloc(to_i915(obj->base.dev)->vmas, GFP_KERNEL);
dabde5c7
DC
2761 if (vma == NULL)
2762 return ERR_PTR(-ENOMEM);
ec7adb6e 2763
6f65e29a
BW
2764 INIT_LIST_HEAD(&vma->vma_link);
2765 INIT_LIST_HEAD(&vma->mm_list);
2766 INIT_LIST_HEAD(&vma->exec_list);
2767 vma->vm = vm;
2768 vma->obj = obj;
2769
777dc5bb 2770 if (i915_is_ggtt(vm))
ec7adb6e 2771 vma->ggtt_view = *ggtt_view;
6f65e29a 2772
f7635669
TU
2773 list_add_tail(&vma->vma_link, &obj->vma_list);
2774 if (!i915_is_ggtt(vm))
e07f0552 2775 i915_ppgtt_get(i915_vm_to_ppgtt(vm));
6f65e29a
BW
2776
2777 return vma;
2778}
2779
2780struct i915_vma *
ec7adb6e
JL
2781i915_gem_obj_lookup_or_create_vma(struct drm_i915_gem_object *obj,
2782 struct i915_address_space *vm)
2783{
2784 struct i915_vma *vma;
2785
2786 vma = i915_gem_obj_to_vma(obj, vm);
2787 if (!vma)
2788 vma = __i915_gem_vma_create(obj, vm,
2789 i915_is_ggtt(vm) ? &i915_ggtt_view_normal : NULL);
2790
2791 return vma;
2792}
2793
2794struct i915_vma *
2795i915_gem_obj_lookup_or_create_ggtt_vma(struct drm_i915_gem_object *obj,
fe14d5f4 2796 const struct i915_ggtt_view *view)
6f65e29a 2797{
ec7adb6e 2798 struct i915_address_space *ggtt = i915_obj_to_ggtt(obj);
6f65e29a
BW
2799 struct i915_vma *vma;
2800
ec7adb6e
JL
2801 if (WARN_ON(!view))
2802 return ERR_PTR(-EINVAL);
2803
2804 vma = i915_gem_obj_to_ggtt_view(obj, view);
2805
2806 if (IS_ERR(vma))
2807 return vma;
2808
6f65e29a 2809 if (!vma)
ec7adb6e 2810 vma = __i915_gem_vma_create(obj, ggtt, view);
6f65e29a
BW
2811
2812 return vma;
ec7adb6e 2813
6f65e29a 2814}
fe14d5f4 2815
50470bb0
TU
2816static void
2817rotate_pages(dma_addr_t *in, unsigned int width, unsigned int height,
2818 struct sg_table *st)
2819{
2820 unsigned int column, row;
2821 unsigned int src_idx;
2822 struct scatterlist *sg = st->sgl;
2823
2824 st->nents = 0;
2825
2826 for (column = 0; column < width; column++) {
2827 src_idx = width * (height - 1) + column;
2828 for (row = 0; row < height; row++) {
2829 st->nents++;
2830 /* We don't need the pages, but need to initialize
2831 * the entries so the sg list can be happily traversed.
2832 * The only thing we need are DMA addresses.
2833 */
2834 sg_set_page(sg, NULL, PAGE_SIZE, 0);
2835 sg_dma_address(sg) = in[src_idx];
2836 sg_dma_len(sg) = PAGE_SIZE;
2837 sg = sg_next(sg);
2838 src_idx -= width;
2839 }
2840 }
2841}
2842
2843static struct sg_table *
2844intel_rotate_fb_obj_pages(struct i915_ggtt_view *ggtt_view,
2845 struct drm_i915_gem_object *obj)
2846{
50470bb0 2847 struct intel_rotation_info *rot_info = &ggtt_view->rotation_info;
84fe03f7 2848 unsigned int size_pages = rot_info->size >> PAGE_SHIFT;
50470bb0
TU
2849 struct sg_page_iter sg_iter;
2850 unsigned long i;
2851 dma_addr_t *page_addr_list;
2852 struct sg_table *st;
1d00dad5 2853 int ret = -ENOMEM;
50470bb0 2854
50470bb0 2855 /* Allocate a temporary list of source pages for random access. */
84fe03f7
TU
2856 page_addr_list = drm_malloc_ab(obj->base.size / PAGE_SIZE,
2857 sizeof(dma_addr_t));
50470bb0
TU
2858 if (!page_addr_list)
2859 return ERR_PTR(ret);
2860
2861 /* Allocate target SG list. */
2862 st = kmalloc(sizeof(*st), GFP_KERNEL);
2863 if (!st)
2864 goto err_st_alloc;
2865
84fe03f7 2866 ret = sg_alloc_table(st, size_pages, GFP_KERNEL);
50470bb0
TU
2867 if (ret)
2868 goto err_sg_alloc;
2869
2870 /* Populate source page list from the object. */
2871 i = 0;
2872 for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, 0) {
2873 page_addr_list[i] = sg_page_iter_dma_address(&sg_iter);
2874 i++;
2875 }
2876
2877 /* Rotate the pages. */
84fe03f7
TU
2878 rotate_pages(page_addr_list,
2879 rot_info->width_pages, rot_info->height_pages,
2880 st);
50470bb0
TU
2881
2882 DRM_DEBUG_KMS(
84fe03f7 2883 "Created rotated page mapping for object size %zu (pitch=%u, height=%u, pixel_format=0x%x, %ux%u tiles, %u pages).\n",
c9f8fd2d 2884 obj->base.size, rot_info->pitch, rot_info->height,
84fe03f7
TU
2885 rot_info->pixel_format, rot_info->width_pages,
2886 rot_info->height_pages, size_pages);
50470bb0
TU
2887
2888 drm_free_large(page_addr_list);
2889
2890 return st;
2891
2892err_sg_alloc:
2893 kfree(st);
2894err_st_alloc:
2895 drm_free_large(page_addr_list);
2896
2897 DRM_DEBUG_KMS(
84fe03f7 2898 "Failed to create rotated mapping for object size %zu! (%d) (pitch=%u, height=%u, pixel_format=0x%x, %ux%u tiles, %u pages)\n",
c9f8fd2d 2899 obj->base.size, ret, rot_info->pitch, rot_info->height,
84fe03f7
TU
2900 rot_info->pixel_format, rot_info->width_pages,
2901 rot_info->height_pages, size_pages);
50470bb0
TU
2902 return ERR_PTR(ret);
2903}
ec7adb6e 2904
8bd7ef16
JL
2905static struct sg_table *
2906intel_partial_pages(const struct i915_ggtt_view *view,
2907 struct drm_i915_gem_object *obj)
2908{
2909 struct sg_table *st;
2910 struct scatterlist *sg;
2911 struct sg_page_iter obj_sg_iter;
2912 int ret = -ENOMEM;
2913
2914 st = kmalloc(sizeof(*st), GFP_KERNEL);
2915 if (!st)
2916 goto err_st_alloc;
2917
2918 ret = sg_alloc_table(st, view->params.partial.size, GFP_KERNEL);
2919 if (ret)
2920 goto err_sg_alloc;
2921
2922 sg = st->sgl;
2923 st->nents = 0;
2924 for_each_sg_page(obj->pages->sgl, &obj_sg_iter, obj->pages->nents,
2925 view->params.partial.offset)
2926 {
2927 if (st->nents >= view->params.partial.size)
2928 break;
2929
2930 sg_set_page(sg, NULL, PAGE_SIZE, 0);
2931 sg_dma_address(sg) = sg_page_iter_dma_address(&obj_sg_iter);
2932 sg_dma_len(sg) = PAGE_SIZE;
2933
2934 sg = sg_next(sg);
2935 st->nents++;
2936 }
2937
2938 return st;
2939
2940err_sg_alloc:
2941 kfree(st);
2942err_st_alloc:
2943 return ERR_PTR(ret);
2944}
2945
70b9f6f8 2946static int
50470bb0 2947i915_get_ggtt_vma_pages(struct i915_vma *vma)
fe14d5f4 2948{
50470bb0
TU
2949 int ret = 0;
2950
fe14d5f4
TU
2951 if (vma->ggtt_view.pages)
2952 return 0;
2953
2954 if (vma->ggtt_view.type == I915_GGTT_VIEW_NORMAL)
2955 vma->ggtt_view.pages = vma->obj->pages;
50470bb0
TU
2956 else if (vma->ggtt_view.type == I915_GGTT_VIEW_ROTATED)
2957 vma->ggtt_view.pages =
2958 intel_rotate_fb_obj_pages(&vma->ggtt_view, vma->obj);
8bd7ef16
JL
2959 else if (vma->ggtt_view.type == I915_GGTT_VIEW_PARTIAL)
2960 vma->ggtt_view.pages =
2961 intel_partial_pages(&vma->ggtt_view, vma->obj);
fe14d5f4
TU
2962 else
2963 WARN_ONCE(1, "GGTT view %u not implemented!\n",
2964 vma->ggtt_view.type);
2965
2966 if (!vma->ggtt_view.pages) {
ec7adb6e 2967 DRM_ERROR("Failed to get pages for GGTT view type %u!\n",
fe14d5f4 2968 vma->ggtt_view.type);
50470bb0
TU
2969 ret = -EINVAL;
2970 } else if (IS_ERR(vma->ggtt_view.pages)) {
2971 ret = PTR_ERR(vma->ggtt_view.pages);
2972 vma->ggtt_view.pages = NULL;
2973 DRM_ERROR("Failed to get pages for VMA view type %u (%d)!\n",
2974 vma->ggtt_view.type, ret);
fe14d5f4
TU
2975 }
2976
50470bb0 2977 return ret;
fe14d5f4
TU
2978}
2979
2980/**
2981 * i915_vma_bind - Sets up PTEs for an VMA in it's corresponding address space.
2982 * @vma: VMA to map
2983 * @cache_level: mapping cache level
2984 * @flags: flags like global or local mapping
2985 *
2986 * DMA addresses are taken from the scatter-gather table of this object (or of
2987 * this VMA in case of non-default GGTT views) and PTE entries set up.
2988 * Note that DMA addresses are also the only part of the SG table we care about.
2989 */
2990int i915_vma_bind(struct i915_vma *vma, enum i915_cache_level cache_level,
2991 u32 flags)
2992{
75d04a37
MK
2993 int ret;
2994 u32 bind_flags;
1d335d1b 2995
75d04a37
MK
2996 if (WARN_ON(flags == 0))
2997 return -EINVAL;
1d335d1b 2998
75d04a37 2999 bind_flags = 0;
0875546c
DV
3000 if (flags & PIN_GLOBAL)
3001 bind_flags |= GLOBAL_BIND;
3002 if (flags & PIN_USER)
3003 bind_flags |= LOCAL_BIND;
3004
3005 if (flags & PIN_UPDATE)
3006 bind_flags |= vma->bound;
3007 else
3008 bind_flags &= ~vma->bound;
3009
75d04a37
MK
3010 if (bind_flags == 0)
3011 return 0;
3012
3013 if (vma->bound == 0 && vma->vm->allocate_va_range) {
3014 trace_i915_va_alloc(vma->vm,
3015 vma->node.start,
3016 vma->node.size,
3017 VM_TO_TRACE_NAME(vma->vm));
3018
b2dd4511
MK
3019 /* XXX: i915_vma_pin() will fix this +- hack */
3020 vma->pin_count++;
75d04a37
MK
3021 ret = vma->vm->allocate_va_range(vma->vm,
3022 vma->node.start,
3023 vma->node.size);
b2dd4511 3024 vma->pin_count--;
75d04a37
MK
3025 if (ret)
3026 return ret;
3027 }
3028
3029 ret = vma->vm->bind_vma(vma, cache_level, bind_flags);
70b9f6f8
DV
3030 if (ret)
3031 return ret;
0875546c
DV
3032
3033 vma->bound |= bind_flags;
fe14d5f4
TU
3034
3035 return 0;
3036}
91e6711e
JL
3037
3038/**
3039 * i915_ggtt_view_size - Get the size of a GGTT view.
3040 * @obj: Object the view is of.
3041 * @view: The view in question.
3042 *
3043 * @return The size of the GGTT view in bytes.
3044 */
3045size_t
3046i915_ggtt_view_size(struct drm_i915_gem_object *obj,
3047 const struct i915_ggtt_view *view)
3048{
9e759ff1 3049 if (view->type == I915_GGTT_VIEW_NORMAL) {
91e6711e 3050 return obj->base.size;
9e759ff1
TU
3051 } else if (view->type == I915_GGTT_VIEW_ROTATED) {
3052 return view->rotation_info.size;
8bd7ef16
JL
3053 } else if (view->type == I915_GGTT_VIEW_PARTIAL) {
3054 return view->params.partial.size << PAGE_SHIFT;
91e6711e
JL
3055 } else {
3056 WARN_ONCE(1, "GGTT view %u not implemented!\n", view->type);
3057 return obj->base.size;
3058 }
3059}
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