Commit | Line | Data |
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76aaf220 DV |
1 | /* |
2 | * Copyright © 2010 Daniel Vetter | |
c4ac524c | 3 | * Copyright © 2011-2014 Intel Corporation |
76aaf220 DV |
4 | * |
5 | * Permission is hereby granted, free of charge, to any person obtaining a | |
6 | * copy of this software and associated documentation files (the "Software"), | |
7 | * to deal in the Software without restriction, including without limitation | |
8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
9 | * and/or sell copies of the Software, and to permit persons to whom the | |
10 | * Software is furnished to do so, subject to the following conditions: | |
11 | * | |
12 | * The above copyright notice and this permission notice (including the next | |
13 | * paragraph) shall be included in all copies or substantial portions of the | |
14 | * Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
21 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
22 | * IN THE SOFTWARE. | |
23 | * | |
24 | */ | |
25 | ||
0e46ce2e | 26 | #include <linux/seq_file.h> |
760285e7 DH |
27 | #include <drm/drmP.h> |
28 | #include <drm/i915_drm.h> | |
76aaf220 | 29 | #include "i915_drv.h" |
5dda8fa3 | 30 | #include "i915_vgpu.h" |
76aaf220 DV |
31 | #include "i915_trace.h" |
32 | #include "intel_drv.h" | |
33 | ||
45f8f69a TU |
34 | /** |
35 | * DOC: Global GTT views | |
36 | * | |
37 | * Background and previous state | |
38 | * | |
39 | * Historically objects could exists (be bound) in global GTT space only as | |
40 | * singular instances with a view representing all of the object's backing pages | |
41 | * in a linear fashion. This view will be called a normal view. | |
42 | * | |
43 | * To support multiple views of the same object, where the number of mapped | |
44 | * pages is not equal to the backing store, or where the layout of the pages | |
45 | * is not linear, concept of a GGTT view was added. | |
46 | * | |
47 | * One example of an alternative view is a stereo display driven by a single | |
48 | * image. In this case we would have a framebuffer looking like this | |
49 | * (2x2 pages): | |
50 | * | |
51 | * 12 | |
52 | * 34 | |
53 | * | |
54 | * Above would represent a normal GGTT view as normally mapped for GPU or CPU | |
55 | * rendering. In contrast, fed to the display engine would be an alternative | |
56 | * view which could look something like this: | |
57 | * | |
58 | * 1212 | |
59 | * 3434 | |
60 | * | |
61 | * In this example both the size and layout of pages in the alternative view is | |
62 | * different from the normal view. | |
63 | * | |
64 | * Implementation and usage | |
65 | * | |
66 | * GGTT views are implemented using VMAs and are distinguished via enum | |
67 | * i915_ggtt_view_type and struct i915_ggtt_view. | |
68 | * | |
69 | * A new flavour of core GEM functions which work with GGTT bound objects were | |
ec7adb6e JL |
70 | * added with the _ggtt_ infix, and sometimes with _view postfix to avoid |
71 | * renaming in large amounts of code. They take the struct i915_ggtt_view | |
72 | * parameter encapsulating all metadata required to implement a view. | |
45f8f69a TU |
73 | * |
74 | * As a helper for callers which are only interested in the normal view, | |
75 | * globally const i915_ggtt_view_normal singleton instance exists. All old core | |
76 | * GEM API functions, the ones not taking the view parameter, are operating on, | |
77 | * or with the normal GGTT view. | |
78 | * | |
79 | * Code wanting to add or use a new GGTT view needs to: | |
80 | * | |
81 | * 1. Add a new enum with a suitable name. | |
82 | * 2. Extend the metadata in the i915_ggtt_view structure if required. | |
83 | * 3. Add support to i915_get_vma_pages(). | |
84 | * | |
85 | * New views are required to build a scatter-gather table from within the | |
86 | * i915_get_vma_pages function. This table is stored in the vma.ggtt_view and | |
87 | * exists for the lifetime of an VMA. | |
88 | * | |
89 | * Core API is designed to have copy semantics which means that passed in | |
90 | * struct i915_ggtt_view does not need to be persistent (left around after | |
91 | * calling the core API functions). | |
92 | * | |
93 | */ | |
94 | ||
70b9f6f8 DV |
95 | static int |
96 | i915_get_ggtt_vma_pages(struct i915_vma *vma); | |
97 | ||
fe14d5f4 | 98 | const struct i915_ggtt_view i915_ggtt_view_normal; |
9abc4648 JL |
99 | const struct i915_ggtt_view i915_ggtt_view_rotated = { |
100 | .type = I915_GGTT_VIEW_ROTATED | |
101 | }; | |
fe14d5f4 | 102 | |
cfa7c862 DV |
103 | static int sanitize_enable_ppgtt(struct drm_device *dev, int enable_ppgtt) |
104 | { | |
1893a71b CW |
105 | bool has_aliasing_ppgtt; |
106 | bool has_full_ppgtt; | |
107 | ||
108 | has_aliasing_ppgtt = INTEL_INFO(dev)->gen >= 6; | |
109 | has_full_ppgtt = INTEL_INFO(dev)->gen >= 7; | |
1893a71b | 110 | |
71ba2d64 YZ |
111 | if (intel_vgpu_active(dev)) |
112 | has_full_ppgtt = false; /* emulation is too hard */ | |
113 | ||
70ee45e1 DL |
114 | /* |
115 | * We don't allow disabling PPGTT for gen9+ as it's a requirement for | |
116 | * execlists, the sole mechanism available to submit work. | |
117 | */ | |
118 | if (INTEL_INFO(dev)->gen < 9 && | |
119 | (enable_ppgtt == 0 || !has_aliasing_ppgtt)) | |
cfa7c862 DV |
120 | return 0; |
121 | ||
122 | if (enable_ppgtt == 1) | |
123 | return 1; | |
124 | ||
1893a71b | 125 | if (enable_ppgtt == 2 && has_full_ppgtt) |
cfa7c862 DV |
126 | return 2; |
127 | ||
93a25a9e DV |
128 | #ifdef CONFIG_INTEL_IOMMU |
129 | /* Disable ppgtt on SNB if VT-d is on. */ | |
130 | if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped) { | |
131 | DRM_INFO("Disabling PPGTT because VT-d is on\n"); | |
cfa7c862 | 132 | return 0; |
93a25a9e DV |
133 | } |
134 | #endif | |
135 | ||
62942ed7 | 136 | /* Early VLV doesn't have this */ |
ca2aed6c VS |
137 | if (IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) && |
138 | dev->pdev->revision < 0xb) { | |
62942ed7 JB |
139 | DRM_DEBUG_DRIVER("disabling PPGTT on pre-B3 step VLV\n"); |
140 | return 0; | |
141 | } | |
142 | ||
2f82bbdf MT |
143 | if (INTEL_INFO(dev)->gen >= 8 && i915.enable_execlists) |
144 | return 2; | |
145 | else | |
146 | return has_aliasing_ppgtt ? 1 : 0; | |
93a25a9e DV |
147 | } |
148 | ||
70b9f6f8 DV |
149 | static int ppgtt_bind_vma(struct i915_vma *vma, |
150 | enum i915_cache_level cache_level, | |
151 | u32 unused) | |
47552659 DV |
152 | { |
153 | u32 pte_flags = 0; | |
154 | ||
155 | /* Currently applicable only to VLV */ | |
156 | if (vma->obj->gt_ro) | |
157 | pte_flags |= PTE_READ_ONLY; | |
158 | ||
159 | vma->vm->insert_entries(vma->vm, vma->obj->pages, vma->node.start, | |
160 | cache_level, pte_flags); | |
70b9f6f8 DV |
161 | |
162 | return 0; | |
47552659 DV |
163 | } |
164 | ||
165 | static void ppgtt_unbind_vma(struct i915_vma *vma) | |
166 | { | |
167 | vma->vm->clear_range(vma->vm, | |
168 | vma->node.start, | |
169 | vma->obj->base.size, | |
170 | true); | |
171 | } | |
6f65e29a | 172 | |
2c642b07 DV |
173 | static gen8_pte_t gen8_pte_encode(dma_addr_t addr, |
174 | enum i915_cache_level level, | |
175 | bool valid) | |
94ec8f61 | 176 | { |
07749ef3 | 177 | gen8_pte_t pte = valid ? _PAGE_PRESENT | _PAGE_RW : 0; |
94ec8f61 | 178 | pte |= addr; |
63c42e56 BW |
179 | |
180 | switch (level) { | |
181 | case I915_CACHE_NONE: | |
fbe5d36e | 182 | pte |= PPAT_UNCACHED_INDEX; |
63c42e56 BW |
183 | break; |
184 | case I915_CACHE_WT: | |
185 | pte |= PPAT_DISPLAY_ELLC_INDEX; | |
186 | break; | |
187 | default: | |
188 | pte |= PPAT_CACHED_INDEX; | |
189 | break; | |
190 | } | |
191 | ||
94ec8f61 BW |
192 | return pte; |
193 | } | |
194 | ||
fe36f55d MK |
195 | static gen8_pde_t gen8_pde_encode(const dma_addr_t addr, |
196 | const enum i915_cache_level level) | |
b1fe6673 | 197 | { |
07749ef3 | 198 | gen8_pde_t pde = _PAGE_PRESENT | _PAGE_RW; |
b1fe6673 BW |
199 | pde |= addr; |
200 | if (level != I915_CACHE_NONE) | |
201 | pde |= PPAT_CACHED_PDE_INDEX; | |
202 | else | |
203 | pde |= PPAT_UNCACHED_INDEX; | |
204 | return pde; | |
205 | } | |
206 | ||
07749ef3 MT |
207 | static gen6_pte_t snb_pte_encode(dma_addr_t addr, |
208 | enum i915_cache_level level, | |
209 | bool valid, u32 unused) | |
54d12527 | 210 | { |
07749ef3 | 211 | gen6_pte_t pte = valid ? GEN6_PTE_VALID : 0; |
54d12527 | 212 | pte |= GEN6_PTE_ADDR_ENCODE(addr); |
e7210c3c BW |
213 | |
214 | switch (level) { | |
350ec881 CW |
215 | case I915_CACHE_L3_LLC: |
216 | case I915_CACHE_LLC: | |
217 | pte |= GEN6_PTE_CACHE_LLC; | |
218 | break; | |
219 | case I915_CACHE_NONE: | |
220 | pte |= GEN6_PTE_UNCACHED; | |
221 | break; | |
222 | default: | |
5f77eeb0 | 223 | MISSING_CASE(level); |
350ec881 CW |
224 | } |
225 | ||
226 | return pte; | |
227 | } | |
228 | ||
07749ef3 MT |
229 | static gen6_pte_t ivb_pte_encode(dma_addr_t addr, |
230 | enum i915_cache_level level, | |
231 | bool valid, u32 unused) | |
350ec881 | 232 | { |
07749ef3 | 233 | gen6_pte_t pte = valid ? GEN6_PTE_VALID : 0; |
350ec881 CW |
234 | pte |= GEN6_PTE_ADDR_ENCODE(addr); |
235 | ||
236 | switch (level) { | |
237 | case I915_CACHE_L3_LLC: | |
238 | pte |= GEN7_PTE_CACHE_L3_LLC; | |
e7210c3c BW |
239 | break; |
240 | case I915_CACHE_LLC: | |
241 | pte |= GEN6_PTE_CACHE_LLC; | |
242 | break; | |
243 | case I915_CACHE_NONE: | |
9119708c | 244 | pte |= GEN6_PTE_UNCACHED; |
e7210c3c BW |
245 | break; |
246 | default: | |
5f77eeb0 | 247 | MISSING_CASE(level); |
e7210c3c BW |
248 | } |
249 | ||
54d12527 BW |
250 | return pte; |
251 | } | |
252 | ||
07749ef3 MT |
253 | static gen6_pte_t byt_pte_encode(dma_addr_t addr, |
254 | enum i915_cache_level level, | |
255 | bool valid, u32 flags) | |
93c34e70 | 256 | { |
07749ef3 | 257 | gen6_pte_t pte = valid ? GEN6_PTE_VALID : 0; |
93c34e70 KG |
258 | pte |= GEN6_PTE_ADDR_ENCODE(addr); |
259 | ||
24f3a8cf AG |
260 | if (!(flags & PTE_READ_ONLY)) |
261 | pte |= BYT_PTE_WRITEABLE; | |
93c34e70 KG |
262 | |
263 | if (level != I915_CACHE_NONE) | |
264 | pte |= BYT_PTE_SNOOPED_BY_CPU_CACHES; | |
265 | ||
266 | return pte; | |
267 | } | |
268 | ||
07749ef3 MT |
269 | static gen6_pte_t hsw_pte_encode(dma_addr_t addr, |
270 | enum i915_cache_level level, | |
271 | bool valid, u32 unused) | |
9119708c | 272 | { |
07749ef3 | 273 | gen6_pte_t pte = valid ? GEN6_PTE_VALID : 0; |
0d8ff15e | 274 | pte |= HSW_PTE_ADDR_ENCODE(addr); |
9119708c KG |
275 | |
276 | if (level != I915_CACHE_NONE) | |
87a6b688 | 277 | pte |= HSW_WB_LLC_AGE3; |
9119708c KG |
278 | |
279 | return pte; | |
280 | } | |
281 | ||
07749ef3 MT |
282 | static gen6_pte_t iris_pte_encode(dma_addr_t addr, |
283 | enum i915_cache_level level, | |
284 | bool valid, u32 unused) | |
4d15c145 | 285 | { |
07749ef3 | 286 | gen6_pte_t pte = valid ? GEN6_PTE_VALID : 0; |
4d15c145 BW |
287 | pte |= HSW_PTE_ADDR_ENCODE(addr); |
288 | ||
651d794f CW |
289 | switch (level) { |
290 | case I915_CACHE_NONE: | |
291 | break; | |
292 | case I915_CACHE_WT: | |
c51e9701 | 293 | pte |= HSW_WT_ELLC_LLC_AGE3; |
651d794f CW |
294 | break; |
295 | default: | |
c51e9701 | 296 | pte |= HSW_WB_ELLC_LLC_AGE3; |
651d794f CW |
297 | break; |
298 | } | |
4d15c145 BW |
299 | |
300 | return pte; | |
301 | } | |
302 | ||
c114f76a MK |
303 | static int __setup_page_dma(struct drm_device *dev, |
304 | struct i915_page_dma *p, gfp_t flags) | |
678d96fb BW |
305 | { |
306 | struct device *device = &dev->pdev->dev; | |
307 | ||
c114f76a | 308 | p->page = alloc_page(flags); |
44159ddb MK |
309 | if (!p->page) |
310 | return -ENOMEM; | |
678d96fb | 311 | |
44159ddb MK |
312 | p->daddr = dma_map_page(device, |
313 | p->page, 0, 4096, PCI_DMA_BIDIRECTIONAL); | |
678d96fb | 314 | |
44159ddb MK |
315 | if (dma_mapping_error(device, p->daddr)) { |
316 | __free_page(p->page); | |
317 | return -EINVAL; | |
318 | } | |
1266cdb1 MT |
319 | |
320 | return 0; | |
678d96fb BW |
321 | } |
322 | ||
c114f76a MK |
323 | static int setup_page_dma(struct drm_device *dev, struct i915_page_dma *p) |
324 | { | |
325 | return __setup_page_dma(dev, p, GFP_KERNEL); | |
326 | } | |
327 | ||
44159ddb | 328 | static void cleanup_page_dma(struct drm_device *dev, struct i915_page_dma *p) |
06fda602 | 329 | { |
44159ddb | 330 | if (WARN_ON(!p->page)) |
06fda602 | 331 | return; |
678d96fb | 332 | |
44159ddb MK |
333 | dma_unmap_page(&dev->pdev->dev, p->daddr, 4096, PCI_DMA_BIDIRECTIONAL); |
334 | __free_page(p->page); | |
335 | memset(p, 0, sizeof(*p)); | |
336 | } | |
337 | ||
d1c54acd | 338 | static void *kmap_page_dma(struct i915_page_dma *p) |
73eeea53 | 339 | { |
d1c54acd MK |
340 | return kmap_atomic(p->page); |
341 | } | |
73eeea53 | 342 | |
d1c54acd MK |
343 | /* We use the flushing unmap only with ppgtt structures: |
344 | * page directories, page tables and scratch pages. | |
345 | */ | |
346 | static void kunmap_page_dma(struct drm_device *dev, void *vaddr) | |
347 | { | |
73eeea53 MK |
348 | /* There are only few exceptions for gen >=6. chv and bxt. |
349 | * And we are not sure about the latter so play safe for now. | |
350 | */ | |
351 | if (IS_CHERRYVIEW(dev) || IS_BROXTON(dev)) | |
352 | drm_clflush_virt_range(vaddr, PAGE_SIZE); | |
353 | ||
354 | kunmap_atomic(vaddr); | |
355 | } | |
356 | ||
567047be | 357 | #define kmap_px(px) kmap_page_dma(px_base(px)) |
d1c54acd MK |
358 | #define kunmap_px(ppgtt, vaddr) kunmap_page_dma((ppgtt)->base.dev, (vaddr)) |
359 | ||
567047be MK |
360 | #define setup_px(dev, px) setup_page_dma((dev), px_base(px)) |
361 | #define cleanup_px(dev, px) cleanup_page_dma((dev), px_base(px)) | |
362 | #define fill_px(dev, px, v) fill_page_dma((dev), px_base(px), (v)) | |
363 | #define fill32_px(dev, px, v) fill_page_dma_32((dev), px_base(px), (v)) | |
364 | ||
d1c54acd MK |
365 | static void fill_page_dma(struct drm_device *dev, struct i915_page_dma *p, |
366 | const uint64_t val) | |
367 | { | |
368 | int i; | |
369 | uint64_t * const vaddr = kmap_page_dma(p); | |
370 | ||
371 | for (i = 0; i < 512; i++) | |
372 | vaddr[i] = val; | |
373 | ||
374 | kunmap_page_dma(dev, vaddr); | |
375 | } | |
376 | ||
73eeea53 MK |
377 | static void fill_page_dma_32(struct drm_device *dev, struct i915_page_dma *p, |
378 | const uint32_t val32) | |
379 | { | |
380 | uint64_t v = val32; | |
381 | ||
382 | v = v << 32 | val32; | |
383 | ||
384 | fill_page_dma(dev, p, v); | |
385 | } | |
386 | ||
a08e111a | 387 | static void free_pt(struct drm_device *dev, struct i915_page_table *pt) |
44159ddb | 388 | { |
567047be | 389 | cleanup_px(dev, pt); |
678d96fb | 390 | kfree(pt->used_ptes); |
06fda602 BW |
391 | kfree(pt); |
392 | } | |
393 | ||
5a8e9943 | 394 | static void gen8_initialize_pt(struct i915_address_space *vm, |
e5815a2e | 395 | struct i915_page_table *pt) |
5a8e9943 | 396 | { |
73eeea53 | 397 | gen8_pte_t scratch_pte; |
5a8e9943 | 398 | |
c114f76a MK |
399 | scratch_pte = gen8_pte_encode(px_dma(vm->scratch_page), |
400 | I915_CACHE_LLC, true); | |
5a8e9943 | 401 | |
567047be | 402 | fill_px(vm->dev, pt, scratch_pte); |
5a8e9943 MT |
403 | } |
404 | ||
8a1ebd74 | 405 | static struct i915_page_table *alloc_pt(struct drm_device *dev) |
06fda602 | 406 | { |
ec565b3c | 407 | struct i915_page_table *pt; |
678d96fb BW |
408 | const size_t count = INTEL_INFO(dev)->gen >= 8 ? |
409 | GEN8_PTES : GEN6_PTES; | |
410 | int ret = -ENOMEM; | |
06fda602 BW |
411 | |
412 | pt = kzalloc(sizeof(*pt), GFP_KERNEL); | |
413 | if (!pt) | |
414 | return ERR_PTR(-ENOMEM); | |
415 | ||
678d96fb BW |
416 | pt->used_ptes = kcalloc(BITS_TO_LONGS(count), sizeof(*pt->used_ptes), |
417 | GFP_KERNEL); | |
418 | ||
419 | if (!pt->used_ptes) | |
420 | goto fail_bitmap; | |
421 | ||
567047be | 422 | ret = setup_px(dev, pt); |
678d96fb | 423 | if (ret) |
44159ddb | 424 | goto fail_page_m; |
06fda602 BW |
425 | |
426 | return pt; | |
678d96fb | 427 | |
44159ddb | 428 | fail_page_m: |
678d96fb BW |
429 | kfree(pt->used_ptes); |
430 | fail_bitmap: | |
431 | kfree(pt); | |
432 | ||
433 | return ERR_PTR(ret); | |
06fda602 BW |
434 | } |
435 | ||
a08e111a | 436 | static void free_pd(struct drm_device *dev, struct i915_page_directory *pd) |
06fda602 | 437 | { |
567047be MK |
438 | if (px_page(pd)) { |
439 | cleanup_px(dev, pd); | |
33c8819f | 440 | kfree(pd->used_pdes); |
06fda602 BW |
441 | kfree(pd); |
442 | } | |
443 | } | |
444 | ||
8a1ebd74 | 445 | static struct i915_page_directory *alloc_pd(struct drm_device *dev) |
06fda602 | 446 | { |
ec565b3c | 447 | struct i915_page_directory *pd; |
33c8819f | 448 | int ret = -ENOMEM; |
06fda602 BW |
449 | |
450 | pd = kzalloc(sizeof(*pd), GFP_KERNEL); | |
451 | if (!pd) | |
452 | return ERR_PTR(-ENOMEM); | |
453 | ||
33c8819f MT |
454 | pd->used_pdes = kcalloc(BITS_TO_LONGS(I915_PDES), |
455 | sizeof(*pd->used_pdes), GFP_KERNEL); | |
456 | if (!pd->used_pdes) | |
a08e111a | 457 | goto fail_bitmap; |
33c8819f | 458 | |
567047be | 459 | ret = setup_px(dev, pd); |
33c8819f | 460 | if (ret) |
a08e111a | 461 | goto fail_page_m; |
e5815a2e | 462 | |
06fda602 | 463 | return pd; |
33c8819f | 464 | |
a08e111a | 465 | fail_page_m: |
33c8819f | 466 | kfree(pd->used_pdes); |
a08e111a | 467 | fail_bitmap: |
33c8819f MT |
468 | kfree(pd); |
469 | ||
470 | return ERR_PTR(ret); | |
06fda602 BW |
471 | } |
472 | ||
94e409c1 | 473 | /* Broadwell Page Directory Pointer Descriptors */ |
e85b26dc | 474 | static int gen8_write_pdp(struct drm_i915_gem_request *req, |
7cb6d7ac MT |
475 | unsigned entry, |
476 | dma_addr_t addr) | |
94e409c1 | 477 | { |
e85b26dc | 478 | struct intel_engine_cs *ring = req->ring; |
94e409c1 BW |
479 | int ret; |
480 | ||
481 | BUG_ON(entry >= 4); | |
482 | ||
5fb9de1a | 483 | ret = intel_ring_begin(req, 6); |
94e409c1 BW |
484 | if (ret) |
485 | return ret; | |
486 | ||
487 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); | |
488 | intel_ring_emit(ring, GEN8_RING_PDP_UDW(ring, entry)); | |
7cb6d7ac | 489 | intel_ring_emit(ring, upper_32_bits(addr)); |
94e409c1 BW |
490 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); |
491 | intel_ring_emit(ring, GEN8_RING_PDP_LDW(ring, entry)); | |
7cb6d7ac | 492 | intel_ring_emit(ring, lower_32_bits(addr)); |
94e409c1 BW |
493 | intel_ring_advance(ring); |
494 | ||
495 | return 0; | |
496 | } | |
497 | ||
eeb9488e | 498 | static int gen8_mm_switch(struct i915_hw_ppgtt *ppgtt, |
e85b26dc | 499 | struct drm_i915_gem_request *req) |
94e409c1 | 500 | { |
eeb9488e | 501 | int i, ret; |
94e409c1 | 502 | |
7cb6d7ac | 503 | for (i = GEN8_LEGACY_PDPES - 1; i >= 0; i--) { |
d852c7bf MK |
504 | const dma_addr_t pd_daddr = i915_page_dir_dma_addr(ppgtt, i); |
505 | ||
e85b26dc | 506 | ret = gen8_write_pdp(req, i, pd_daddr); |
eeb9488e BW |
507 | if (ret) |
508 | return ret; | |
94e409c1 | 509 | } |
d595bd4b | 510 | |
eeb9488e | 511 | return 0; |
94e409c1 BW |
512 | } |
513 | ||
459108b8 | 514 | static void gen8_ppgtt_clear_range(struct i915_address_space *vm, |
782f1495 BW |
515 | uint64_t start, |
516 | uint64_t length, | |
459108b8 BW |
517 | bool use_scratch) |
518 | { | |
519 | struct i915_hw_ppgtt *ppgtt = | |
520 | container_of(vm, struct i915_hw_ppgtt, base); | |
07749ef3 | 521 | gen8_pte_t *pt_vaddr, scratch_pte; |
7ad47cf2 BW |
522 | unsigned pdpe = start >> GEN8_PDPE_SHIFT & GEN8_PDPE_MASK; |
523 | unsigned pde = start >> GEN8_PDE_SHIFT & GEN8_PDE_MASK; | |
524 | unsigned pte = start >> GEN8_PTE_SHIFT & GEN8_PTE_MASK; | |
782f1495 | 525 | unsigned num_entries = length >> PAGE_SHIFT; |
459108b8 BW |
526 | unsigned last_pte, i; |
527 | ||
c114f76a | 528 | scratch_pte = gen8_pte_encode(px_dma(ppgtt->base.scratch_page), |
459108b8 BW |
529 | I915_CACHE_LLC, use_scratch); |
530 | ||
531 | while (num_entries) { | |
ec565b3c MT |
532 | struct i915_page_directory *pd; |
533 | struct i915_page_table *pt; | |
06fda602 BW |
534 | |
535 | if (WARN_ON(!ppgtt->pdp.page_directory[pdpe])) | |
536 | continue; | |
537 | ||
538 | pd = ppgtt->pdp.page_directory[pdpe]; | |
539 | ||
540 | if (WARN_ON(!pd->page_table[pde])) | |
541 | continue; | |
542 | ||
543 | pt = pd->page_table[pde]; | |
544 | ||
567047be | 545 | if (WARN_ON(!px_page(pt))) |
06fda602 BW |
546 | continue; |
547 | ||
7ad47cf2 | 548 | last_pte = pte + num_entries; |
07749ef3 MT |
549 | if (last_pte > GEN8_PTES) |
550 | last_pte = GEN8_PTES; | |
459108b8 | 551 | |
d1c54acd | 552 | pt_vaddr = kmap_px(pt); |
459108b8 | 553 | |
7ad47cf2 | 554 | for (i = pte; i < last_pte; i++) { |
459108b8 | 555 | pt_vaddr[i] = scratch_pte; |
7ad47cf2 BW |
556 | num_entries--; |
557 | } | |
459108b8 | 558 | |
d1c54acd | 559 | kunmap_px(ppgtt, pt); |
459108b8 | 560 | |
7ad47cf2 | 561 | pte = 0; |
07749ef3 | 562 | if (++pde == I915_PDES) { |
7ad47cf2 BW |
563 | pdpe++; |
564 | pde = 0; | |
565 | } | |
459108b8 BW |
566 | } |
567 | } | |
568 | ||
9df15b49 BW |
569 | static void gen8_ppgtt_insert_entries(struct i915_address_space *vm, |
570 | struct sg_table *pages, | |
782f1495 | 571 | uint64_t start, |
24f3a8cf | 572 | enum i915_cache_level cache_level, u32 unused) |
9df15b49 BW |
573 | { |
574 | struct i915_hw_ppgtt *ppgtt = | |
575 | container_of(vm, struct i915_hw_ppgtt, base); | |
07749ef3 | 576 | gen8_pte_t *pt_vaddr; |
7ad47cf2 BW |
577 | unsigned pdpe = start >> GEN8_PDPE_SHIFT & GEN8_PDPE_MASK; |
578 | unsigned pde = start >> GEN8_PDE_SHIFT & GEN8_PDE_MASK; | |
579 | unsigned pte = start >> GEN8_PTE_SHIFT & GEN8_PTE_MASK; | |
9df15b49 BW |
580 | struct sg_page_iter sg_iter; |
581 | ||
6f1cc993 | 582 | pt_vaddr = NULL; |
7ad47cf2 | 583 | |
9df15b49 | 584 | for_each_sg_page(pages->sgl, &sg_iter, pages->nents, 0) { |
76643600 | 585 | if (WARN_ON(pdpe >= GEN8_LEGACY_PDPES)) |
7ad47cf2 BW |
586 | break; |
587 | ||
d7b3de91 | 588 | if (pt_vaddr == NULL) { |
ec565b3c MT |
589 | struct i915_page_directory *pd = ppgtt->pdp.page_directory[pdpe]; |
590 | struct i915_page_table *pt = pd->page_table[pde]; | |
d1c54acd | 591 | pt_vaddr = kmap_px(pt); |
d7b3de91 | 592 | } |
9df15b49 | 593 | |
7ad47cf2 | 594 | pt_vaddr[pte] = |
6f1cc993 CW |
595 | gen8_pte_encode(sg_page_iter_dma_address(&sg_iter), |
596 | cache_level, true); | |
07749ef3 | 597 | if (++pte == GEN8_PTES) { |
d1c54acd | 598 | kunmap_px(ppgtt, pt_vaddr); |
6f1cc993 | 599 | pt_vaddr = NULL; |
07749ef3 | 600 | if (++pde == I915_PDES) { |
7ad47cf2 BW |
601 | pdpe++; |
602 | pde = 0; | |
603 | } | |
604 | pte = 0; | |
9df15b49 BW |
605 | } |
606 | } | |
d1c54acd MK |
607 | |
608 | if (pt_vaddr) | |
609 | kunmap_px(ppgtt, pt_vaddr); | |
9df15b49 BW |
610 | } |
611 | ||
69876bed MT |
612 | static void gen8_initialize_pd(struct i915_address_space *vm, |
613 | struct i915_page_directory *pd) | |
614 | { | |
73eeea53 | 615 | gen8_pde_t scratch_pde; |
69876bed | 616 | |
79ab9370 | 617 | scratch_pde = gen8_pde_encode(px_dma(vm->scratch_pt), I915_CACHE_LLC); |
69876bed | 618 | |
567047be | 619 | fill_px(vm->dev, pd, scratch_pde); |
e5815a2e MT |
620 | } |
621 | ||
ec565b3c | 622 | static void gen8_free_page_tables(struct i915_page_directory *pd, struct drm_device *dev) |
7ad47cf2 BW |
623 | { |
624 | int i; | |
625 | ||
567047be | 626 | if (!px_page(pd)) |
7ad47cf2 BW |
627 | return; |
628 | ||
33c8819f | 629 | for_each_set_bit(i, pd->used_pdes, I915_PDES) { |
06fda602 BW |
630 | if (WARN_ON(!pd->page_table[i])) |
631 | continue; | |
7ad47cf2 | 632 | |
a08e111a | 633 | free_pt(dev, pd->page_table[i]); |
06fda602 BW |
634 | pd->page_table[i] = NULL; |
635 | } | |
d7b3de91 BW |
636 | } |
637 | ||
061dd493 | 638 | static void gen8_ppgtt_cleanup(struct i915_address_space *vm) |
b45a6715 | 639 | { |
061dd493 DV |
640 | struct i915_hw_ppgtt *ppgtt = |
641 | container_of(vm, struct i915_hw_ppgtt, base); | |
b45a6715 BW |
642 | int i; |
643 | ||
33c8819f | 644 | for_each_set_bit(i, ppgtt->pdp.used_pdpes, GEN8_LEGACY_PDPES) { |
06fda602 BW |
645 | if (WARN_ON(!ppgtt->pdp.page_directory[i])) |
646 | continue; | |
647 | ||
06dc68d6 | 648 | gen8_free_page_tables(ppgtt->pdp.page_directory[i], ppgtt->base.dev); |
a08e111a | 649 | free_pd(ppgtt->base.dev, ppgtt->pdp.page_directory[i]); |
7ad47cf2 | 650 | } |
69876bed | 651 | |
79ab9370 MK |
652 | free_pd(vm->dev, vm->scratch_pd); |
653 | free_pt(vm->dev, vm->scratch_pt); | |
b45a6715 BW |
654 | } |
655 | ||
d7b2633d MT |
656 | /** |
657 | * gen8_ppgtt_alloc_pagetabs() - Allocate page tables for VA range. | |
658 | * @ppgtt: Master ppgtt structure. | |
659 | * @pd: Page directory for this address range. | |
660 | * @start: Starting virtual address to begin allocations. | |
661 | * @length Size of the allocations. | |
662 | * @new_pts: Bitmap set by function with new allocations. Likely used by the | |
663 | * caller to free on error. | |
664 | * | |
665 | * Allocate the required number of page tables. Extremely similar to | |
666 | * gen8_ppgtt_alloc_page_directories(). The main difference is here we are limited by | |
667 | * the page directory boundary (instead of the page directory pointer). That | |
668 | * boundary is 1GB virtual. Therefore, unlike gen8_ppgtt_alloc_page_directories(), it is | |
669 | * possible, and likely that the caller will need to use multiple calls of this | |
670 | * function to achieve the appropriate allocation. | |
671 | * | |
672 | * Return: 0 if success; negative error code otherwise. | |
673 | */ | |
e5815a2e MT |
674 | static int gen8_ppgtt_alloc_pagetabs(struct i915_hw_ppgtt *ppgtt, |
675 | struct i915_page_directory *pd, | |
5441f0cb | 676 | uint64_t start, |
d7b2633d MT |
677 | uint64_t length, |
678 | unsigned long *new_pts) | |
bf2b4ed2 | 679 | { |
e5815a2e | 680 | struct drm_device *dev = ppgtt->base.dev; |
d7b2633d | 681 | struct i915_page_table *pt; |
5441f0cb MT |
682 | uint64_t temp; |
683 | uint32_t pde; | |
bf2b4ed2 | 684 | |
d7b2633d MT |
685 | gen8_for_each_pde(pt, pd, start, length, temp, pde) { |
686 | /* Don't reallocate page tables */ | |
687 | if (pt) { | |
688 | /* Scratch is never allocated this way */ | |
79ab9370 | 689 | WARN_ON(pt == ppgtt->base.scratch_pt); |
d7b2633d MT |
690 | continue; |
691 | } | |
692 | ||
8a1ebd74 | 693 | pt = alloc_pt(dev); |
d7b2633d | 694 | if (IS_ERR(pt)) |
5441f0cb MT |
695 | goto unwind_out; |
696 | ||
d7b2633d MT |
697 | gen8_initialize_pt(&ppgtt->base, pt); |
698 | pd->page_table[pde] = pt; | |
699 | set_bit(pde, new_pts); | |
7ad47cf2 BW |
700 | } |
701 | ||
bf2b4ed2 | 702 | return 0; |
7ad47cf2 BW |
703 | |
704 | unwind_out: | |
d7b2633d | 705 | for_each_set_bit(pde, new_pts, I915_PDES) |
a08e111a | 706 | free_pt(dev, pd->page_table[pde]); |
7ad47cf2 | 707 | |
d7b3de91 | 708 | return -ENOMEM; |
bf2b4ed2 BW |
709 | } |
710 | ||
d7b2633d MT |
711 | /** |
712 | * gen8_ppgtt_alloc_page_directories() - Allocate page directories for VA range. | |
713 | * @ppgtt: Master ppgtt structure. | |
714 | * @pdp: Page directory pointer for this address range. | |
715 | * @start: Starting virtual address to begin allocations. | |
716 | * @length Size of the allocations. | |
717 | * @new_pds Bitmap set by function with new allocations. Likely used by the | |
718 | * caller to free on error. | |
719 | * | |
720 | * Allocate the required number of page directories starting at the pde index of | |
721 | * @start, and ending at the pde index @start + @length. This function will skip | |
722 | * over already allocated page directories within the range, and only allocate | |
723 | * new ones, setting the appropriate pointer within the pdp as well as the | |
724 | * correct position in the bitmap @new_pds. | |
725 | * | |
726 | * The function will only allocate the pages within the range for a give page | |
727 | * directory pointer. In other words, if @start + @length straddles a virtually | |
728 | * addressed PDP boundary (512GB for 4k pages), there will be more allocations | |
729 | * required by the caller, This is not currently possible, and the BUG in the | |
730 | * code will prevent it. | |
731 | * | |
732 | * Return: 0 if success; negative error code otherwise. | |
733 | */ | |
c488dbba MT |
734 | static int gen8_ppgtt_alloc_page_directories(struct i915_hw_ppgtt *ppgtt, |
735 | struct i915_page_directory_pointer *pdp, | |
69876bed | 736 | uint64_t start, |
d7b2633d MT |
737 | uint64_t length, |
738 | unsigned long *new_pds) | |
bf2b4ed2 | 739 | { |
e5815a2e | 740 | struct drm_device *dev = ppgtt->base.dev; |
d7b2633d | 741 | struct i915_page_directory *pd; |
69876bed MT |
742 | uint64_t temp; |
743 | uint32_t pdpe; | |
744 | ||
d7b2633d MT |
745 | WARN_ON(!bitmap_empty(new_pds, GEN8_LEGACY_PDPES)); |
746 | ||
d7b2633d MT |
747 | gen8_for_each_pdpe(pd, pdp, start, length, temp, pdpe) { |
748 | if (pd) | |
749 | continue; | |
33c8819f | 750 | |
8a1ebd74 | 751 | pd = alloc_pd(dev); |
d7b2633d | 752 | if (IS_ERR(pd)) |
d7b3de91 | 753 | goto unwind_out; |
69876bed | 754 | |
d7b2633d MT |
755 | gen8_initialize_pd(&ppgtt->base, pd); |
756 | pdp->page_directory[pdpe] = pd; | |
757 | set_bit(pdpe, new_pds); | |
d7b3de91 BW |
758 | } |
759 | ||
bf2b4ed2 | 760 | return 0; |
d7b3de91 BW |
761 | |
762 | unwind_out: | |
d7b2633d | 763 | for_each_set_bit(pdpe, new_pds, GEN8_LEGACY_PDPES) |
a08e111a | 764 | free_pd(dev, pdp->page_directory[pdpe]); |
d7b3de91 BW |
765 | |
766 | return -ENOMEM; | |
bf2b4ed2 BW |
767 | } |
768 | ||
d7b2633d MT |
769 | static void |
770 | free_gen8_temp_bitmaps(unsigned long *new_pds, unsigned long **new_pts) | |
771 | { | |
772 | int i; | |
773 | ||
774 | for (i = 0; i < GEN8_LEGACY_PDPES; i++) | |
775 | kfree(new_pts[i]); | |
776 | kfree(new_pts); | |
777 | kfree(new_pds); | |
778 | } | |
779 | ||
780 | /* Fills in the page directory bitmap, and the array of page tables bitmap. Both | |
781 | * of these are based on the number of PDPEs in the system. | |
782 | */ | |
783 | static | |
784 | int __must_check alloc_gen8_temp_bitmaps(unsigned long **new_pds, | |
785 | unsigned long ***new_pts) | |
786 | { | |
787 | int i; | |
788 | unsigned long *pds; | |
789 | unsigned long **pts; | |
790 | ||
791 | pds = kcalloc(BITS_TO_LONGS(GEN8_LEGACY_PDPES), sizeof(unsigned long), GFP_KERNEL); | |
792 | if (!pds) | |
793 | return -ENOMEM; | |
794 | ||
795 | pts = kcalloc(GEN8_LEGACY_PDPES, sizeof(unsigned long *), GFP_KERNEL); | |
796 | if (!pts) { | |
797 | kfree(pds); | |
798 | return -ENOMEM; | |
799 | } | |
800 | ||
801 | for (i = 0; i < GEN8_LEGACY_PDPES; i++) { | |
802 | pts[i] = kcalloc(BITS_TO_LONGS(I915_PDES), | |
803 | sizeof(unsigned long), GFP_KERNEL); | |
804 | if (!pts[i]) | |
805 | goto err_out; | |
806 | } | |
807 | ||
808 | *new_pds = pds; | |
809 | *new_pts = pts; | |
810 | ||
811 | return 0; | |
812 | ||
813 | err_out: | |
814 | free_gen8_temp_bitmaps(pds, pts); | |
815 | return -ENOMEM; | |
816 | } | |
817 | ||
5b7e4c9c MK |
818 | /* PDE TLBs are a pain to invalidate on GEN8+. When we modify |
819 | * the page table structures, we mark them dirty so that | |
820 | * context switching/execlist queuing code takes extra steps | |
821 | * to ensure that tlbs are flushed. | |
822 | */ | |
823 | static void mark_tlbs_dirty(struct i915_hw_ppgtt *ppgtt) | |
824 | { | |
825 | ppgtt->pd_dirty_rings = INTEL_INFO(ppgtt->base.dev)->ring_mask; | |
826 | } | |
827 | ||
e5815a2e MT |
828 | static int gen8_alloc_va_range(struct i915_address_space *vm, |
829 | uint64_t start, | |
830 | uint64_t length) | |
bf2b4ed2 | 831 | { |
e5815a2e MT |
832 | struct i915_hw_ppgtt *ppgtt = |
833 | container_of(vm, struct i915_hw_ppgtt, base); | |
d7b2633d | 834 | unsigned long *new_page_dirs, **new_page_tables; |
5441f0cb | 835 | struct i915_page_directory *pd; |
33c8819f MT |
836 | const uint64_t orig_start = start; |
837 | const uint64_t orig_length = length; | |
5441f0cb MT |
838 | uint64_t temp; |
839 | uint32_t pdpe; | |
bf2b4ed2 BW |
840 | int ret; |
841 | ||
d7b2633d MT |
842 | /* Wrap is never okay since we can only represent 48b, and we don't |
843 | * actually use the other side of the canonical address space. | |
844 | */ | |
845 | if (WARN_ON(start + length < start)) | |
a05d80ee MK |
846 | return -ENODEV; |
847 | ||
848 | if (WARN_ON(start + length > ppgtt->base.total)) | |
849 | return -ENODEV; | |
d7b2633d MT |
850 | |
851 | ret = alloc_gen8_temp_bitmaps(&new_page_dirs, &new_page_tables); | |
bf2b4ed2 BW |
852 | if (ret) |
853 | return ret; | |
854 | ||
d7b2633d MT |
855 | /* Do the allocations first so we can easily bail out */ |
856 | ret = gen8_ppgtt_alloc_page_directories(ppgtt, &ppgtt->pdp, start, length, | |
857 | new_page_dirs); | |
858 | if (ret) { | |
859 | free_gen8_temp_bitmaps(new_page_dirs, new_page_tables); | |
860 | return ret; | |
861 | } | |
862 | ||
863 | /* For every page directory referenced, allocate page tables */ | |
5441f0cb | 864 | gen8_for_each_pdpe(pd, &ppgtt->pdp, start, length, temp, pdpe) { |
d7b2633d MT |
865 | ret = gen8_ppgtt_alloc_pagetabs(ppgtt, pd, start, length, |
866 | new_page_tables[pdpe]); | |
5441f0cb MT |
867 | if (ret) |
868 | goto err_out; | |
5441f0cb MT |
869 | } |
870 | ||
33c8819f MT |
871 | start = orig_start; |
872 | length = orig_length; | |
873 | ||
d7b2633d MT |
874 | /* Allocations have completed successfully, so set the bitmaps, and do |
875 | * the mappings. */ | |
33c8819f | 876 | gen8_for_each_pdpe(pd, &ppgtt->pdp, start, length, temp, pdpe) { |
d1c54acd | 877 | gen8_pde_t *const page_directory = kmap_px(pd); |
33c8819f MT |
878 | struct i915_page_table *pt; |
879 | uint64_t pd_len = gen8_clamp_pd(start, length); | |
880 | uint64_t pd_start = start; | |
881 | uint32_t pde; | |
882 | ||
d7b2633d MT |
883 | /* Every pd should be allocated, we just did that above. */ |
884 | WARN_ON(!pd); | |
885 | ||
886 | gen8_for_each_pde(pt, pd, pd_start, pd_len, temp, pde) { | |
887 | /* Same reasoning as pd */ | |
888 | WARN_ON(!pt); | |
889 | WARN_ON(!pd_len); | |
890 | WARN_ON(!gen8_pte_count(pd_start, pd_len)); | |
891 | ||
892 | /* Set our used ptes within the page table */ | |
893 | bitmap_set(pt->used_ptes, | |
894 | gen8_pte_index(pd_start), | |
895 | gen8_pte_count(pd_start, pd_len)); | |
896 | ||
897 | /* Our pde is now pointing to the pagetable, pt */ | |
33c8819f | 898 | set_bit(pde, pd->used_pdes); |
d7b2633d MT |
899 | |
900 | /* Map the PDE to the page table */ | |
fe36f55d MK |
901 | page_directory[pde] = gen8_pde_encode(px_dma(pt), |
902 | I915_CACHE_LLC); | |
d7b2633d MT |
903 | |
904 | /* NB: We haven't yet mapped ptes to pages. At this | |
905 | * point we're still relying on insert_entries() */ | |
33c8819f | 906 | } |
d7b2633d | 907 | |
d1c54acd | 908 | kunmap_px(ppgtt, page_directory); |
d7b2633d | 909 | |
33c8819f MT |
910 | set_bit(pdpe, ppgtt->pdp.used_pdpes); |
911 | } | |
912 | ||
d7b2633d | 913 | free_gen8_temp_bitmaps(new_page_dirs, new_page_tables); |
5b7e4c9c | 914 | mark_tlbs_dirty(ppgtt); |
d7b3de91 | 915 | return 0; |
bf2b4ed2 | 916 | |
d7b3de91 | 917 | err_out: |
d7b2633d MT |
918 | while (pdpe--) { |
919 | for_each_set_bit(temp, new_page_tables[pdpe], I915_PDES) | |
a08e111a | 920 | free_pt(vm->dev, ppgtt->pdp.page_directory[pdpe]->page_table[temp]); |
d7b2633d MT |
921 | } |
922 | ||
923 | for_each_set_bit(pdpe, new_page_dirs, GEN8_LEGACY_PDPES) | |
a08e111a | 924 | free_pd(vm->dev, ppgtt->pdp.page_directory[pdpe]); |
d7b2633d MT |
925 | |
926 | free_gen8_temp_bitmaps(new_page_dirs, new_page_tables); | |
5b7e4c9c | 927 | mark_tlbs_dirty(ppgtt); |
bf2b4ed2 BW |
928 | return ret; |
929 | } | |
930 | ||
eb0b44ad | 931 | /* |
f3a964b9 BW |
932 | * GEN8 legacy ppgtt programming is accomplished through a max 4 PDP registers |
933 | * with a net effect resembling a 2-level page table in normal x86 terms. Each | |
934 | * PDP represents 1GB of memory 4 * 512 * 512 * 4096 = 4GB legacy 32b address | |
935 | * space. | |
37aca44a | 936 | * |
f3a964b9 | 937 | */ |
5c5f6457 | 938 | static int gen8_ppgtt_init(struct i915_hw_ppgtt *ppgtt) |
37aca44a | 939 | { |
79ab9370 MK |
940 | ppgtt->base.scratch_pt = alloc_pt(ppgtt->base.dev); |
941 | if (IS_ERR(ppgtt->base.scratch_pt)) | |
942 | return PTR_ERR(ppgtt->base.scratch_pt); | |
69876bed | 943 | |
79ab9370 MK |
944 | ppgtt->base.scratch_pd = alloc_pd(ppgtt->base.dev); |
945 | if (IS_ERR(ppgtt->base.scratch_pd)) | |
946 | return PTR_ERR(ppgtt->base.scratch_pd); | |
7cb6d7ac | 947 | |
79ab9370 MK |
948 | gen8_initialize_pt(&ppgtt->base, ppgtt->base.scratch_pt); |
949 | gen8_initialize_pd(&ppgtt->base, ppgtt->base.scratch_pd); | |
69876bed | 950 | |
d7b2633d | 951 | ppgtt->base.start = 0; |
5c5f6457 | 952 | ppgtt->base.total = 1ULL << 32; |
501fd70f MT |
953 | if (IS_ENABLED(CONFIG_X86_32)) |
954 | /* While we have a proliferation of size_t variables | |
955 | * we cannot represent the full ppgtt size on 32bit, | |
956 | * so limit it to the same size as the GGTT (currently | |
957 | * 2GiB). | |
958 | */ | |
959 | ppgtt->base.total = to_i915(ppgtt->base.dev)->gtt.base.total; | |
d7b2633d | 960 | ppgtt->base.cleanup = gen8_ppgtt_cleanup; |
5c5f6457 | 961 | ppgtt->base.allocate_va_range = gen8_alloc_va_range; |
d7b2633d | 962 | ppgtt->base.insert_entries = gen8_ppgtt_insert_entries; |
c7e16f22 | 963 | ppgtt->base.clear_range = gen8_ppgtt_clear_range; |
777dc5bb DV |
964 | ppgtt->base.unbind_vma = ppgtt_unbind_vma; |
965 | ppgtt->base.bind_vma = ppgtt_bind_vma; | |
d7b2633d MT |
966 | |
967 | ppgtt->switch_mm = gen8_mm_switch; | |
968 | ||
969 | return 0; | |
970 | } | |
971 | ||
87d60b63 BW |
972 | static void gen6_dump_ppgtt(struct i915_hw_ppgtt *ppgtt, struct seq_file *m) |
973 | { | |
87d60b63 | 974 | struct i915_address_space *vm = &ppgtt->base; |
09942c65 | 975 | struct i915_page_table *unused; |
07749ef3 | 976 | gen6_pte_t scratch_pte; |
87d60b63 | 977 | uint32_t pd_entry; |
09942c65 MT |
978 | uint32_t pte, pde, temp; |
979 | uint32_t start = ppgtt->base.start, length = ppgtt->base.total; | |
87d60b63 | 980 | |
79ab9370 MK |
981 | scratch_pte = vm->pte_encode(px_dma(vm->scratch_page), |
982 | I915_CACHE_LLC, true, 0); | |
87d60b63 | 983 | |
09942c65 | 984 | gen6_for_each_pde(unused, &ppgtt->pd, start, length, temp, pde) { |
87d60b63 | 985 | u32 expected; |
07749ef3 | 986 | gen6_pte_t *pt_vaddr; |
567047be | 987 | const dma_addr_t pt_addr = px_dma(ppgtt->pd.page_table[pde]); |
09942c65 | 988 | pd_entry = readl(ppgtt->pd_addr + pde); |
87d60b63 BW |
989 | expected = (GEN6_PDE_ADDR_ENCODE(pt_addr) | GEN6_PDE_VALID); |
990 | ||
991 | if (pd_entry != expected) | |
992 | seq_printf(m, "\tPDE #%d mismatch: Actual PDE: %x Expected PDE: %x\n", | |
993 | pde, | |
994 | pd_entry, | |
995 | expected); | |
996 | seq_printf(m, "\tPDE: %x\n", pd_entry); | |
997 | ||
d1c54acd MK |
998 | pt_vaddr = kmap_px(ppgtt->pd.page_table[pde]); |
999 | ||
07749ef3 | 1000 | for (pte = 0; pte < GEN6_PTES; pte+=4) { |
87d60b63 | 1001 | unsigned long va = |
07749ef3 | 1002 | (pde * PAGE_SIZE * GEN6_PTES) + |
87d60b63 BW |
1003 | (pte * PAGE_SIZE); |
1004 | int i; | |
1005 | bool found = false; | |
1006 | for (i = 0; i < 4; i++) | |
1007 | if (pt_vaddr[pte + i] != scratch_pte) | |
1008 | found = true; | |
1009 | if (!found) | |
1010 | continue; | |
1011 | ||
1012 | seq_printf(m, "\t\t0x%lx [%03d,%04d]: =", va, pde, pte); | |
1013 | for (i = 0; i < 4; i++) { | |
1014 | if (pt_vaddr[pte + i] != scratch_pte) | |
1015 | seq_printf(m, " %08x", pt_vaddr[pte + i]); | |
1016 | else | |
1017 | seq_puts(m, " SCRATCH "); | |
1018 | } | |
1019 | seq_puts(m, "\n"); | |
1020 | } | |
d1c54acd | 1021 | kunmap_px(ppgtt, pt_vaddr); |
87d60b63 BW |
1022 | } |
1023 | } | |
1024 | ||
678d96fb | 1025 | /* Write pde (index) from the page directory @pd to the page table @pt */ |
ec565b3c MT |
1026 | static void gen6_write_pde(struct i915_page_directory *pd, |
1027 | const int pde, struct i915_page_table *pt) | |
6197349b | 1028 | { |
678d96fb BW |
1029 | /* Caller needs to make sure the write completes if necessary */ |
1030 | struct i915_hw_ppgtt *ppgtt = | |
1031 | container_of(pd, struct i915_hw_ppgtt, pd); | |
1032 | u32 pd_entry; | |
6197349b | 1033 | |
567047be | 1034 | pd_entry = GEN6_PDE_ADDR_ENCODE(px_dma(pt)); |
678d96fb | 1035 | pd_entry |= GEN6_PDE_VALID; |
6197349b | 1036 | |
678d96fb BW |
1037 | writel(pd_entry, ppgtt->pd_addr + pde); |
1038 | } | |
6197349b | 1039 | |
678d96fb BW |
1040 | /* Write all the page tables found in the ppgtt structure to incrementing page |
1041 | * directories. */ | |
1042 | static void gen6_write_page_range(struct drm_i915_private *dev_priv, | |
ec565b3c | 1043 | struct i915_page_directory *pd, |
678d96fb BW |
1044 | uint32_t start, uint32_t length) |
1045 | { | |
ec565b3c | 1046 | struct i915_page_table *pt; |
678d96fb BW |
1047 | uint32_t pde, temp; |
1048 | ||
1049 | gen6_for_each_pde(pt, pd, start, length, temp, pde) | |
1050 | gen6_write_pde(pd, pde, pt); | |
1051 | ||
1052 | /* Make sure write is complete before other code can use this page | |
1053 | * table. Also require for WC mapped PTEs */ | |
1054 | readl(dev_priv->gtt.gsm); | |
3e302542 BW |
1055 | } |
1056 | ||
b4a74e3a | 1057 | static uint32_t get_pd_offset(struct i915_hw_ppgtt *ppgtt) |
3e302542 | 1058 | { |
44159ddb | 1059 | BUG_ON(ppgtt->pd.base.ggtt_offset & 0x3f); |
b4a74e3a | 1060 | |
44159ddb | 1061 | return (ppgtt->pd.base.ggtt_offset / 64) << 16; |
b4a74e3a BW |
1062 | } |
1063 | ||
90252e5c | 1064 | static int hsw_mm_switch(struct i915_hw_ppgtt *ppgtt, |
e85b26dc | 1065 | struct drm_i915_gem_request *req) |
90252e5c | 1066 | { |
e85b26dc | 1067 | struct intel_engine_cs *ring = req->ring; |
90252e5c BW |
1068 | int ret; |
1069 | ||
90252e5c | 1070 | /* NB: TLBs must be flushed and invalidated before a switch */ |
a84c3ae1 | 1071 | ret = ring->flush(req, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS); |
90252e5c BW |
1072 | if (ret) |
1073 | return ret; | |
1074 | ||
5fb9de1a | 1075 | ret = intel_ring_begin(req, 6); |
90252e5c BW |
1076 | if (ret) |
1077 | return ret; | |
1078 | ||
1079 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(2)); | |
1080 | intel_ring_emit(ring, RING_PP_DIR_DCLV(ring)); | |
1081 | intel_ring_emit(ring, PP_DIR_DCLV_2G); | |
1082 | intel_ring_emit(ring, RING_PP_DIR_BASE(ring)); | |
1083 | intel_ring_emit(ring, get_pd_offset(ppgtt)); | |
1084 | intel_ring_emit(ring, MI_NOOP); | |
1085 | intel_ring_advance(ring); | |
1086 | ||
1087 | return 0; | |
1088 | } | |
1089 | ||
71ba2d64 | 1090 | static int vgpu_mm_switch(struct i915_hw_ppgtt *ppgtt, |
e85b26dc | 1091 | struct drm_i915_gem_request *req) |
71ba2d64 | 1092 | { |
e85b26dc | 1093 | struct intel_engine_cs *ring = req->ring; |
71ba2d64 YZ |
1094 | struct drm_i915_private *dev_priv = to_i915(ppgtt->base.dev); |
1095 | ||
1096 | I915_WRITE(RING_PP_DIR_DCLV(ring), PP_DIR_DCLV_2G); | |
1097 | I915_WRITE(RING_PP_DIR_BASE(ring), get_pd_offset(ppgtt)); | |
1098 | return 0; | |
1099 | } | |
1100 | ||
48a10389 | 1101 | static int gen7_mm_switch(struct i915_hw_ppgtt *ppgtt, |
e85b26dc | 1102 | struct drm_i915_gem_request *req) |
48a10389 | 1103 | { |
e85b26dc | 1104 | struct intel_engine_cs *ring = req->ring; |
48a10389 BW |
1105 | int ret; |
1106 | ||
48a10389 | 1107 | /* NB: TLBs must be flushed and invalidated before a switch */ |
a84c3ae1 | 1108 | ret = ring->flush(req, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS); |
48a10389 BW |
1109 | if (ret) |
1110 | return ret; | |
1111 | ||
5fb9de1a | 1112 | ret = intel_ring_begin(req, 6); |
48a10389 BW |
1113 | if (ret) |
1114 | return ret; | |
1115 | ||
1116 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(2)); | |
1117 | intel_ring_emit(ring, RING_PP_DIR_DCLV(ring)); | |
1118 | intel_ring_emit(ring, PP_DIR_DCLV_2G); | |
1119 | intel_ring_emit(ring, RING_PP_DIR_BASE(ring)); | |
1120 | intel_ring_emit(ring, get_pd_offset(ppgtt)); | |
1121 | intel_ring_emit(ring, MI_NOOP); | |
1122 | intel_ring_advance(ring); | |
1123 | ||
90252e5c BW |
1124 | /* XXX: RCS is the only one to auto invalidate the TLBs? */ |
1125 | if (ring->id != RCS) { | |
a84c3ae1 | 1126 | ret = ring->flush(req, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS); |
90252e5c BW |
1127 | if (ret) |
1128 | return ret; | |
1129 | } | |
1130 | ||
48a10389 BW |
1131 | return 0; |
1132 | } | |
1133 | ||
eeb9488e | 1134 | static int gen6_mm_switch(struct i915_hw_ppgtt *ppgtt, |
e85b26dc | 1135 | struct drm_i915_gem_request *req) |
eeb9488e | 1136 | { |
e85b26dc | 1137 | struct intel_engine_cs *ring = req->ring; |
eeb9488e BW |
1138 | struct drm_device *dev = ppgtt->base.dev; |
1139 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1140 | ||
48a10389 | 1141 | |
eeb9488e BW |
1142 | I915_WRITE(RING_PP_DIR_DCLV(ring), PP_DIR_DCLV_2G); |
1143 | I915_WRITE(RING_PP_DIR_BASE(ring), get_pd_offset(ppgtt)); | |
1144 | ||
1145 | POSTING_READ(RING_PP_DIR_DCLV(ring)); | |
1146 | ||
1147 | return 0; | |
1148 | } | |
1149 | ||
82460d97 | 1150 | static void gen8_ppgtt_enable(struct drm_device *dev) |
eeb9488e | 1151 | { |
eeb9488e | 1152 | struct drm_i915_private *dev_priv = dev->dev_private; |
a4872ba6 | 1153 | struct intel_engine_cs *ring; |
82460d97 | 1154 | int j; |
3e302542 | 1155 | |
eeb9488e BW |
1156 | for_each_ring(ring, dev_priv, j) { |
1157 | I915_WRITE(RING_MODE_GEN7(ring), | |
1158 | _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE)); | |
eeb9488e | 1159 | } |
eeb9488e | 1160 | } |
6197349b | 1161 | |
82460d97 | 1162 | static void gen7_ppgtt_enable(struct drm_device *dev) |
3e302542 | 1163 | { |
50227e1c | 1164 | struct drm_i915_private *dev_priv = dev->dev_private; |
a4872ba6 | 1165 | struct intel_engine_cs *ring; |
b4a74e3a | 1166 | uint32_t ecochk, ecobits; |
3e302542 | 1167 | int i; |
6197349b | 1168 | |
b4a74e3a BW |
1169 | ecobits = I915_READ(GAC_ECO_BITS); |
1170 | I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_PPGTT_CACHE64B); | |
a65c2fcd | 1171 | |
b4a74e3a BW |
1172 | ecochk = I915_READ(GAM_ECOCHK); |
1173 | if (IS_HASWELL(dev)) { | |
1174 | ecochk |= ECOCHK_PPGTT_WB_HSW; | |
1175 | } else { | |
1176 | ecochk |= ECOCHK_PPGTT_LLC_IVB; | |
1177 | ecochk &= ~ECOCHK_PPGTT_GFDT_IVB; | |
1178 | } | |
1179 | I915_WRITE(GAM_ECOCHK, ecochk); | |
a65c2fcd | 1180 | |
b4a74e3a | 1181 | for_each_ring(ring, dev_priv, i) { |
6197349b | 1182 | /* GFX_MODE is per-ring on gen7+ */ |
b4a74e3a BW |
1183 | I915_WRITE(RING_MODE_GEN7(ring), |
1184 | _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE)); | |
6197349b | 1185 | } |
b4a74e3a | 1186 | } |
6197349b | 1187 | |
82460d97 | 1188 | static void gen6_ppgtt_enable(struct drm_device *dev) |
b4a74e3a | 1189 | { |
50227e1c | 1190 | struct drm_i915_private *dev_priv = dev->dev_private; |
b4a74e3a | 1191 | uint32_t ecochk, gab_ctl, ecobits; |
a65c2fcd | 1192 | |
b4a74e3a BW |
1193 | ecobits = I915_READ(GAC_ECO_BITS); |
1194 | I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_SNB_BIT | | |
1195 | ECOBITS_PPGTT_CACHE64B); | |
6197349b | 1196 | |
b4a74e3a BW |
1197 | gab_ctl = I915_READ(GAB_CTL); |
1198 | I915_WRITE(GAB_CTL, gab_ctl | GAB_CTL_CONT_AFTER_PAGEFAULT); | |
1199 | ||
1200 | ecochk = I915_READ(GAM_ECOCHK); | |
1201 | I915_WRITE(GAM_ECOCHK, ecochk | ECOCHK_SNB_BIT | ECOCHK_PPGTT_CACHE64B); | |
1202 | ||
1203 | I915_WRITE(GFX_MODE, _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE)); | |
6197349b BW |
1204 | } |
1205 | ||
1d2a314c | 1206 | /* PPGTT support for Sandybdrige/Gen6 and later */ |
853ba5d2 | 1207 | static void gen6_ppgtt_clear_range(struct i915_address_space *vm, |
782f1495 BW |
1208 | uint64_t start, |
1209 | uint64_t length, | |
828c7908 | 1210 | bool use_scratch) |
1d2a314c | 1211 | { |
853ba5d2 BW |
1212 | struct i915_hw_ppgtt *ppgtt = |
1213 | container_of(vm, struct i915_hw_ppgtt, base); | |
07749ef3 | 1214 | gen6_pte_t *pt_vaddr, scratch_pte; |
782f1495 BW |
1215 | unsigned first_entry = start >> PAGE_SHIFT; |
1216 | unsigned num_entries = length >> PAGE_SHIFT; | |
07749ef3 MT |
1217 | unsigned act_pt = first_entry / GEN6_PTES; |
1218 | unsigned first_pte = first_entry % GEN6_PTES; | |
7bddb01f | 1219 | unsigned last_pte, i; |
1d2a314c | 1220 | |
c114f76a MK |
1221 | scratch_pte = vm->pte_encode(px_dma(vm->scratch_page), |
1222 | I915_CACHE_LLC, true, 0); | |
1d2a314c | 1223 | |
7bddb01f DV |
1224 | while (num_entries) { |
1225 | last_pte = first_pte + num_entries; | |
07749ef3 MT |
1226 | if (last_pte > GEN6_PTES) |
1227 | last_pte = GEN6_PTES; | |
7bddb01f | 1228 | |
d1c54acd | 1229 | pt_vaddr = kmap_px(ppgtt->pd.page_table[act_pt]); |
1d2a314c | 1230 | |
7bddb01f DV |
1231 | for (i = first_pte; i < last_pte; i++) |
1232 | pt_vaddr[i] = scratch_pte; | |
1d2a314c | 1233 | |
d1c54acd | 1234 | kunmap_px(ppgtt, pt_vaddr); |
1d2a314c | 1235 | |
7bddb01f DV |
1236 | num_entries -= last_pte - first_pte; |
1237 | first_pte = 0; | |
a15326a5 | 1238 | act_pt++; |
7bddb01f | 1239 | } |
1d2a314c DV |
1240 | } |
1241 | ||
853ba5d2 | 1242 | static void gen6_ppgtt_insert_entries(struct i915_address_space *vm, |
def886c3 | 1243 | struct sg_table *pages, |
782f1495 | 1244 | uint64_t start, |
24f3a8cf | 1245 | enum i915_cache_level cache_level, u32 flags) |
def886c3 | 1246 | { |
853ba5d2 BW |
1247 | struct i915_hw_ppgtt *ppgtt = |
1248 | container_of(vm, struct i915_hw_ppgtt, base); | |
07749ef3 | 1249 | gen6_pte_t *pt_vaddr; |
782f1495 | 1250 | unsigned first_entry = start >> PAGE_SHIFT; |
07749ef3 MT |
1251 | unsigned act_pt = first_entry / GEN6_PTES; |
1252 | unsigned act_pte = first_entry % GEN6_PTES; | |
6e995e23 ID |
1253 | struct sg_page_iter sg_iter; |
1254 | ||
cc79714f | 1255 | pt_vaddr = NULL; |
6e995e23 | 1256 | for_each_sg_page(pages->sgl, &sg_iter, pages->nents, 0) { |
cc79714f | 1257 | if (pt_vaddr == NULL) |
d1c54acd | 1258 | pt_vaddr = kmap_px(ppgtt->pd.page_table[act_pt]); |
6e995e23 | 1259 | |
cc79714f CW |
1260 | pt_vaddr[act_pte] = |
1261 | vm->pte_encode(sg_page_iter_dma_address(&sg_iter), | |
24f3a8cf AG |
1262 | cache_level, true, flags); |
1263 | ||
07749ef3 | 1264 | if (++act_pte == GEN6_PTES) { |
d1c54acd | 1265 | kunmap_px(ppgtt, pt_vaddr); |
cc79714f | 1266 | pt_vaddr = NULL; |
a15326a5 | 1267 | act_pt++; |
6e995e23 | 1268 | act_pte = 0; |
def886c3 | 1269 | } |
def886c3 | 1270 | } |
cc79714f | 1271 | if (pt_vaddr) |
d1c54acd | 1272 | kunmap_px(ppgtt, pt_vaddr); |
def886c3 DV |
1273 | } |
1274 | ||
4933d519 | 1275 | static void gen6_initialize_pt(struct i915_address_space *vm, |
73eeea53 | 1276 | struct i915_page_table *pt) |
4933d519 | 1277 | { |
73eeea53 | 1278 | gen6_pte_t scratch_pte; |
4933d519 | 1279 | |
c114f76a | 1280 | WARN_ON(px_dma(vm->scratch_page) == 0); |
4933d519 | 1281 | |
c114f76a MK |
1282 | scratch_pte = vm->pte_encode(px_dma(vm->scratch_page), |
1283 | I915_CACHE_LLC, true, 0); | |
4933d519 | 1284 | |
567047be | 1285 | fill32_px(vm->dev, pt, scratch_pte); |
4933d519 MT |
1286 | } |
1287 | ||
678d96fb | 1288 | static int gen6_alloc_va_range(struct i915_address_space *vm, |
a05d80ee | 1289 | uint64_t start_in, uint64_t length_in) |
678d96fb | 1290 | { |
4933d519 MT |
1291 | DECLARE_BITMAP(new_page_tables, I915_PDES); |
1292 | struct drm_device *dev = vm->dev; | |
1293 | struct drm_i915_private *dev_priv = dev->dev_private; | |
678d96fb BW |
1294 | struct i915_hw_ppgtt *ppgtt = |
1295 | container_of(vm, struct i915_hw_ppgtt, base); | |
ec565b3c | 1296 | struct i915_page_table *pt; |
a05d80ee | 1297 | uint32_t start, length, start_save, length_save; |
678d96fb | 1298 | uint32_t pde, temp; |
4933d519 MT |
1299 | int ret; |
1300 | ||
a05d80ee MK |
1301 | if (WARN_ON(start_in + length_in > ppgtt->base.total)) |
1302 | return -ENODEV; | |
1303 | ||
1304 | start = start_save = start_in; | |
1305 | length = length_save = length_in; | |
4933d519 MT |
1306 | |
1307 | bitmap_zero(new_page_tables, I915_PDES); | |
1308 | ||
1309 | /* The allocation is done in two stages so that we can bail out with | |
1310 | * minimal amount of pain. The first stage finds new page tables that | |
1311 | * need allocation. The second stage marks use ptes within the page | |
1312 | * tables. | |
1313 | */ | |
1314 | gen6_for_each_pde(pt, &ppgtt->pd, start, length, temp, pde) { | |
79ab9370 | 1315 | if (pt != vm->scratch_pt) { |
4933d519 MT |
1316 | WARN_ON(bitmap_empty(pt->used_ptes, GEN6_PTES)); |
1317 | continue; | |
1318 | } | |
1319 | ||
1320 | /* We've already allocated a page table */ | |
1321 | WARN_ON(!bitmap_empty(pt->used_ptes, GEN6_PTES)); | |
1322 | ||
8a1ebd74 | 1323 | pt = alloc_pt(dev); |
4933d519 MT |
1324 | if (IS_ERR(pt)) { |
1325 | ret = PTR_ERR(pt); | |
1326 | goto unwind_out; | |
1327 | } | |
1328 | ||
1329 | gen6_initialize_pt(vm, pt); | |
1330 | ||
1331 | ppgtt->pd.page_table[pde] = pt; | |
1332 | set_bit(pde, new_page_tables); | |
72744cb1 | 1333 | trace_i915_page_table_entry_alloc(vm, pde, start, GEN6_PDE_SHIFT); |
4933d519 MT |
1334 | } |
1335 | ||
1336 | start = start_save; | |
1337 | length = length_save; | |
678d96fb BW |
1338 | |
1339 | gen6_for_each_pde(pt, &ppgtt->pd, start, length, temp, pde) { | |
1340 | DECLARE_BITMAP(tmp_bitmap, GEN6_PTES); | |
1341 | ||
1342 | bitmap_zero(tmp_bitmap, GEN6_PTES); | |
1343 | bitmap_set(tmp_bitmap, gen6_pte_index(start), | |
1344 | gen6_pte_count(start, length)); | |
1345 | ||
4933d519 MT |
1346 | if (test_and_clear_bit(pde, new_page_tables)) |
1347 | gen6_write_pde(&ppgtt->pd, pde, pt); | |
1348 | ||
72744cb1 MT |
1349 | trace_i915_page_table_entry_map(vm, pde, pt, |
1350 | gen6_pte_index(start), | |
1351 | gen6_pte_count(start, length), | |
1352 | GEN6_PTES); | |
4933d519 | 1353 | bitmap_or(pt->used_ptes, tmp_bitmap, pt->used_ptes, |
678d96fb BW |
1354 | GEN6_PTES); |
1355 | } | |
1356 | ||
4933d519 MT |
1357 | WARN_ON(!bitmap_empty(new_page_tables, I915_PDES)); |
1358 | ||
1359 | /* Make sure write is complete before other code can use this page | |
1360 | * table. Also require for WC mapped PTEs */ | |
1361 | readl(dev_priv->gtt.gsm); | |
1362 | ||
563222a7 | 1363 | mark_tlbs_dirty(ppgtt); |
678d96fb | 1364 | return 0; |
4933d519 MT |
1365 | |
1366 | unwind_out: | |
1367 | for_each_set_bit(pde, new_page_tables, I915_PDES) { | |
ec565b3c | 1368 | struct i915_page_table *pt = ppgtt->pd.page_table[pde]; |
4933d519 | 1369 | |
79ab9370 | 1370 | ppgtt->pd.page_table[pde] = vm->scratch_pt; |
a08e111a | 1371 | free_pt(vm->dev, pt); |
4933d519 MT |
1372 | } |
1373 | ||
1374 | mark_tlbs_dirty(ppgtt); | |
1375 | return ret; | |
678d96fb BW |
1376 | } |
1377 | ||
061dd493 | 1378 | static void gen6_ppgtt_cleanup(struct i915_address_space *vm) |
a00d825d | 1379 | { |
061dd493 DV |
1380 | struct i915_hw_ppgtt *ppgtt = |
1381 | container_of(vm, struct i915_hw_ppgtt, base); | |
09942c65 MT |
1382 | struct i915_page_table *pt; |
1383 | uint32_t pde; | |
4933d519 | 1384 | |
061dd493 DV |
1385 | drm_mm_remove_node(&ppgtt->node); |
1386 | ||
09942c65 | 1387 | gen6_for_all_pdes(pt, ppgtt, pde) { |
79ab9370 | 1388 | if (pt != vm->scratch_pt) |
a08e111a | 1389 | free_pt(ppgtt->base.dev, pt); |
4933d519 | 1390 | } |
06fda602 | 1391 | |
79ab9370 | 1392 | free_pt(vm->dev, vm->scratch_pt); |
3440d265 DV |
1393 | } |
1394 | ||
b146520f | 1395 | static int gen6_ppgtt_allocate_page_directories(struct i915_hw_ppgtt *ppgtt) |
3440d265 | 1396 | { |
853ba5d2 | 1397 | struct drm_device *dev = ppgtt->base.dev; |
1d2a314c | 1398 | struct drm_i915_private *dev_priv = dev->dev_private; |
e3cc1995 | 1399 | bool retried = false; |
b146520f | 1400 | int ret; |
1d2a314c | 1401 | |
c8d4c0d6 BW |
1402 | /* PPGTT PDEs reside in the GGTT and consists of 512 entries. The |
1403 | * allocator works in address space sizes, so it's multiplied by page | |
1404 | * size. We allocate at the top of the GTT to avoid fragmentation. | |
1405 | */ | |
1406 | BUG_ON(!drm_mm_initialized(&dev_priv->gtt.base.mm)); | |
79ab9370 MK |
1407 | ppgtt->base.scratch_pt = alloc_pt(ppgtt->base.dev); |
1408 | if (IS_ERR(ppgtt->base.scratch_pt)) | |
1409 | return PTR_ERR(ppgtt->base.scratch_pt); | |
4933d519 | 1410 | |
79ab9370 | 1411 | gen6_initialize_pt(&ppgtt->base, ppgtt->base.scratch_pt); |
4933d519 | 1412 | |
e3cc1995 | 1413 | alloc: |
c8d4c0d6 BW |
1414 | ret = drm_mm_insert_node_in_range_generic(&dev_priv->gtt.base.mm, |
1415 | &ppgtt->node, GEN6_PD_SIZE, | |
1416 | GEN6_PD_ALIGN, 0, | |
1417 | 0, dev_priv->gtt.base.total, | |
3e8b5ae9 | 1418 | DRM_MM_TOPDOWN); |
e3cc1995 BW |
1419 | if (ret == -ENOSPC && !retried) { |
1420 | ret = i915_gem_evict_something(dev, &dev_priv->gtt.base, | |
1421 | GEN6_PD_SIZE, GEN6_PD_ALIGN, | |
d23db88c CW |
1422 | I915_CACHE_NONE, |
1423 | 0, dev_priv->gtt.base.total, | |
1424 | 0); | |
e3cc1995 | 1425 | if (ret) |
678d96fb | 1426 | goto err_out; |
e3cc1995 BW |
1427 | |
1428 | retried = true; | |
1429 | goto alloc; | |
1430 | } | |
c8d4c0d6 | 1431 | |
c8c26622 | 1432 | if (ret) |
678d96fb BW |
1433 | goto err_out; |
1434 | ||
c8c26622 | 1435 | |
c8d4c0d6 BW |
1436 | if (ppgtt->node.start < dev_priv->gtt.mappable_end) |
1437 | DRM_DEBUG("Forced to use aperture for PDEs\n"); | |
1d2a314c | 1438 | |
c8c26622 | 1439 | return 0; |
678d96fb BW |
1440 | |
1441 | err_out: | |
79ab9370 | 1442 | free_pt(ppgtt->base.dev, ppgtt->base.scratch_pt); |
678d96fb | 1443 | return ret; |
b146520f BW |
1444 | } |
1445 | ||
b146520f BW |
1446 | static int gen6_ppgtt_alloc(struct i915_hw_ppgtt *ppgtt) |
1447 | { | |
2f2cf682 | 1448 | return gen6_ppgtt_allocate_page_directories(ppgtt); |
4933d519 | 1449 | } |
06dc68d6 | 1450 | |
4933d519 MT |
1451 | static void gen6_scratch_va_range(struct i915_hw_ppgtt *ppgtt, |
1452 | uint64_t start, uint64_t length) | |
1453 | { | |
ec565b3c | 1454 | struct i915_page_table *unused; |
4933d519 | 1455 | uint32_t pde, temp; |
1d2a314c | 1456 | |
4933d519 | 1457 | gen6_for_each_pde(unused, &ppgtt->pd, start, length, temp, pde) |
79ab9370 | 1458 | ppgtt->pd.page_table[pde] = ppgtt->base.scratch_pt; |
b146520f BW |
1459 | } |
1460 | ||
5c5f6457 | 1461 | static int gen6_ppgtt_init(struct i915_hw_ppgtt *ppgtt) |
b146520f BW |
1462 | { |
1463 | struct drm_device *dev = ppgtt->base.dev; | |
1464 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1465 | int ret; | |
1466 | ||
1467 | ppgtt->base.pte_encode = dev_priv->gtt.base.pte_encode; | |
1468 | if (IS_GEN6(dev)) { | |
b146520f BW |
1469 | ppgtt->switch_mm = gen6_mm_switch; |
1470 | } else if (IS_HASWELL(dev)) { | |
b146520f BW |
1471 | ppgtt->switch_mm = hsw_mm_switch; |
1472 | } else if (IS_GEN7(dev)) { | |
b146520f BW |
1473 | ppgtt->switch_mm = gen7_mm_switch; |
1474 | } else | |
1475 | BUG(); | |
1476 | ||
71ba2d64 YZ |
1477 | if (intel_vgpu_active(dev)) |
1478 | ppgtt->switch_mm = vgpu_mm_switch; | |
1479 | ||
b146520f BW |
1480 | ret = gen6_ppgtt_alloc(ppgtt); |
1481 | if (ret) | |
1482 | return ret; | |
1483 | ||
5c5f6457 | 1484 | ppgtt->base.allocate_va_range = gen6_alloc_va_range; |
b146520f BW |
1485 | ppgtt->base.clear_range = gen6_ppgtt_clear_range; |
1486 | ppgtt->base.insert_entries = gen6_ppgtt_insert_entries; | |
777dc5bb DV |
1487 | ppgtt->base.unbind_vma = ppgtt_unbind_vma; |
1488 | ppgtt->base.bind_vma = ppgtt_bind_vma; | |
b146520f | 1489 | ppgtt->base.cleanup = gen6_ppgtt_cleanup; |
b146520f | 1490 | ppgtt->base.start = 0; |
09942c65 | 1491 | ppgtt->base.total = I915_PDES * GEN6_PTES * PAGE_SIZE; |
87d60b63 | 1492 | ppgtt->debug_dump = gen6_dump_ppgtt; |
1d2a314c | 1493 | |
44159ddb | 1494 | ppgtt->pd.base.ggtt_offset = |
07749ef3 | 1495 | ppgtt->node.start / PAGE_SIZE * sizeof(gen6_pte_t); |
1d2a314c | 1496 | |
678d96fb | 1497 | ppgtt->pd_addr = (gen6_pte_t __iomem *)dev_priv->gtt.gsm + |
44159ddb | 1498 | ppgtt->pd.base.ggtt_offset / sizeof(gen6_pte_t); |
678d96fb | 1499 | |
5c5f6457 | 1500 | gen6_scratch_va_range(ppgtt, 0, ppgtt->base.total); |
1d2a314c | 1501 | |
678d96fb BW |
1502 | gen6_write_page_range(dev_priv, &ppgtt->pd, 0, ppgtt->base.total); |
1503 | ||
440fd528 | 1504 | DRM_DEBUG_DRIVER("Allocated pde space (%lldM) at GTT entry: %llx\n", |
b146520f BW |
1505 | ppgtt->node.size >> 20, |
1506 | ppgtt->node.start / PAGE_SIZE); | |
3440d265 | 1507 | |
fa76da34 | 1508 | DRM_DEBUG("Adding PPGTT at offset %x\n", |
44159ddb | 1509 | ppgtt->pd.base.ggtt_offset << 10); |
fa76da34 | 1510 | |
b146520f | 1511 | return 0; |
3440d265 DV |
1512 | } |
1513 | ||
5c5f6457 | 1514 | static int __hw_ppgtt_init(struct drm_device *dev, struct i915_hw_ppgtt *ppgtt) |
3440d265 DV |
1515 | { |
1516 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3440d265 | 1517 | |
853ba5d2 | 1518 | ppgtt->base.dev = dev; |
c114f76a | 1519 | ppgtt->base.scratch_page = dev_priv->gtt.base.scratch_page; |
3440d265 | 1520 | |
3ed124b2 | 1521 | if (INTEL_INFO(dev)->gen < 8) |
5c5f6457 | 1522 | return gen6_ppgtt_init(ppgtt); |
3ed124b2 | 1523 | else |
d7b2633d | 1524 | return gen8_ppgtt_init(ppgtt); |
fa76da34 | 1525 | } |
c114f76a | 1526 | |
fa76da34 DV |
1527 | int i915_ppgtt_init(struct drm_device *dev, struct i915_hw_ppgtt *ppgtt) |
1528 | { | |
1529 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1530 | int ret = 0; | |
3ed124b2 | 1531 | |
5c5f6457 | 1532 | ret = __hw_ppgtt_init(dev, ppgtt); |
fa76da34 | 1533 | if (ret == 0) { |
c7c48dfd | 1534 | kref_init(&ppgtt->ref); |
93bd8649 BW |
1535 | drm_mm_init(&ppgtt->base.mm, ppgtt->base.start, |
1536 | ppgtt->base.total); | |
7e0d96bc | 1537 | i915_init_vm(dev_priv, &ppgtt->base); |
93bd8649 | 1538 | } |
1d2a314c DV |
1539 | |
1540 | return ret; | |
1541 | } | |
1542 | ||
82460d97 DV |
1543 | int i915_ppgtt_init_hw(struct drm_device *dev) |
1544 | { | |
671b5013 TD |
1545 | /* In the case of execlists, PPGTT is enabled by the context descriptor |
1546 | * and the PDPs are contained within the context itself. We don't | |
1547 | * need to do anything here. */ | |
1548 | if (i915.enable_execlists) | |
1549 | return 0; | |
1550 | ||
82460d97 DV |
1551 | if (!USES_PPGTT(dev)) |
1552 | return 0; | |
1553 | ||
1554 | if (IS_GEN6(dev)) | |
1555 | gen6_ppgtt_enable(dev); | |
1556 | else if (IS_GEN7(dev)) | |
1557 | gen7_ppgtt_enable(dev); | |
1558 | else if (INTEL_INFO(dev)->gen >= 8) | |
1559 | gen8_ppgtt_enable(dev); | |
1560 | else | |
5f77eeb0 | 1561 | MISSING_CASE(INTEL_INFO(dev)->gen); |
82460d97 | 1562 | |
4ad2fd88 JH |
1563 | return 0; |
1564 | } | |
1d2a314c | 1565 | |
b3dd6b96 | 1566 | int i915_ppgtt_init_ring(struct drm_i915_gem_request *req) |
4ad2fd88 | 1567 | { |
b3dd6b96 | 1568 | struct drm_i915_private *dev_priv = req->ring->dev->dev_private; |
4ad2fd88 JH |
1569 | struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt; |
1570 | ||
1571 | if (i915.enable_execlists) | |
1572 | return 0; | |
1573 | ||
1574 | if (!ppgtt) | |
1575 | return 0; | |
1576 | ||
e85b26dc | 1577 | return ppgtt->switch_mm(ppgtt, req); |
1d2a314c | 1578 | } |
4ad2fd88 | 1579 | |
4d884705 DV |
1580 | struct i915_hw_ppgtt * |
1581 | i915_ppgtt_create(struct drm_device *dev, struct drm_i915_file_private *fpriv) | |
1582 | { | |
1583 | struct i915_hw_ppgtt *ppgtt; | |
1584 | int ret; | |
1585 | ||
1586 | ppgtt = kzalloc(sizeof(*ppgtt), GFP_KERNEL); | |
1587 | if (!ppgtt) | |
1588 | return ERR_PTR(-ENOMEM); | |
1589 | ||
1590 | ret = i915_ppgtt_init(dev, ppgtt); | |
1591 | if (ret) { | |
1592 | kfree(ppgtt); | |
1593 | return ERR_PTR(ret); | |
1594 | } | |
1595 | ||
1596 | ppgtt->file_priv = fpriv; | |
1597 | ||
198c974d DCS |
1598 | trace_i915_ppgtt_create(&ppgtt->base); |
1599 | ||
4d884705 DV |
1600 | return ppgtt; |
1601 | } | |
1602 | ||
ee960be7 DV |
1603 | void i915_ppgtt_release(struct kref *kref) |
1604 | { | |
1605 | struct i915_hw_ppgtt *ppgtt = | |
1606 | container_of(kref, struct i915_hw_ppgtt, ref); | |
1607 | ||
198c974d DCS |
1608 | trace_i915_ppgtt_release(&ppgtt->base); |
1609 | ||
ee960be7 DV |
1610 | /* vmas should already be unbound */ |
1611 | WARN_ON(!list_empty(&ppgtt->base.active_list)); | |
1612 | WARN_ON(!list_empty(&ppgtt->base.inactive_list)); | |
1613 | ||
19dd120c DV |
1614 | list_del(&ppgtt->base.global_link); |
1615 | drm_mm_takedown(&ppgtt->base.mm); | |
1616 | ||
ee960be7 DV |
1617 | ppgtt->base.cleanup(&ppgtt->base); |
1618 | kfree(ppgtt); | |
1619 | } | |
1d2a314c | 1620 | |
a81cc00c BW |
1621 | extern int intel_iommu_gfx_mapped; |
1622 | /* Certain Gen5 chipsets require require idling the GPU before | |
1623 | * unmapping anything from the GTT when VT-d is enabled. | |
1624 | */ | |
2c642b07 | 1625 | static bool needs_idle_maps(struct drm_device *dev) |
a81cc00c BW |
1626 | { |
1627 | #ifdef CONFIG_INTEL_IOMMU | |
1628 | /* Query intel_iommu to see if we need the workaround. Presumably that | |
1629 | * was loaded first. | |
1630 | */ | |
1631 | if (IS_GEN5(dev) && IS_MOBILE(dev) && intel_iommu_gfx_mapped) | |
1632 | return true; | |
1633 | #endif | |
1634 | return false; | |
1635 | } | |
1636 | ||
5c042287 BW |
1637 | static bool do_idling(struct drm_i915_private *dev_priv) |
1638 | { | |
1639 | bool ret = dev_priv->mm.interruptible; | |
1640 | ||
a81cc00c | 1641 | if (unlikely(dev_priv->gtt.do_idle_maps)) { |
5c042287 | 1642 | dev_priv->mm.interruptible = false; |
b2da9fe5 | 1643 | if (i915_gpu_idle(dev_priv->dev)) { |
5c042287 BW |
1644 | DRM_ERROR("Couldn't idle GPU\n"); |
1645 | /* Wait a bit, in hopes it avoids the hang */ | |
1646 | udelay(10); | |
1647 | } | |
1648 | } | |
1649 | ||
1650 | return ret; | |
1651 | } | |
1652 | ||
1653 | static void undo_idling(struct drm_i915_private *dev_priv, bool interruptible) | |
1654 | { | |
a81cc00c | 1655 | if (unlikely(dev_priv->gtt.do_idle_maps)) |
5c042287 BW |
1656 | dev_priv->mm.interruptible = interruptible; |
1657 | } | |
1658 | ||
828c7908 BW |
1659 | void i915_check_and_clear_faults(struct drm_device *dev) |
1660 | { | |
1661 | struct drm_i915_private *dev_priv = dev->dev_private; | |
a4872ba6 | 1662 | struct intel_engine_cs *ring; |
828c7908 BW |
1663 | int i; |
1664 | ||
1665 | if (INTEL_INFO(dev)->gen < 6) | |
1666 | return; | |
1667 | ||
1668 | for_each_ring(ring, dev_priv, i) { | |
1669 | u32 fault_reg; | |
1670 | fault_reg = I915_READ(RING_FAULT_REG(ring)); | |
1671 | if (fault_reg & RING_FAULT_VALID) { | |
1672 | DRM_DEBUG_DRIVER("Unexpected fault\n" | |
59a5d290 | 1673 | "\tAddr: 0x%08lx\n" |
828c7908 BW |
1674 | "\tAddress space: %s\n" |
1675 | "\tSource ID: %d\n" | |
1676 | "\tType: %d\n", | |
1677 | fault_reg & PAGE_MASK, | |
1678 | fault_reg & RING_FAULT_GTTSEL_MASK ? "GGTT" : "PPGTT", | |
1679 | RING_FAULT_SRCID(fault_reg), | |
1680 | RING_FAULT_FAULT_TYPE(fault_reg)); | |
1681 | I915_WRITE(RING_FAULT_REG(ring), | |
1682 | fault_reg & ~RING_FAULT_VALID); | |
1683 | } | |
1684 | } | |
1685 | POSTING_READ(RING_FAULT_REG(&dev_priv->ring[RCS])); | |
1686 | } | |
1687 | ||
91e56499 CW |
1688 | static void i915_ggtt_flush(struct drm_i915_private *dev_priv) |
1689 | { | |
1690 | if (INTEL_INFO(dev_priv->dev)->gen < 6) { | |
1691 | intel_gtt_chipset_flush(); | |
1692 | } else { | |
1693 | I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN); | |
1694 | POSTING_READ(GFX_FLSH_CNTL_GEN6); | |
1695 | } | |
1696 | } | |
1697 | ||
828c7908 BW |
1698 | void i915_gem_suspend_gtt_mappings(struct drm_device *dev) |
1699 | { | |
1700 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1701 | ||
1702 | /* Don't bother messing with faults pre GEN6 as we have little | |
1703 | * documentation supporting that it's a good idea. | |
1704 | */ | |
1705 | if (INTEL_INFO(dev)->gen < 6) | |
1706 | return; | |
1707 | ||
1708 | i915_check_and_clear_faults(dev); | |
1709 | ||
1710 | dev_priv->gtt.base.clear_range(&dev_priv->gtt.base, | |
782f1495 BW |
1711 | dev_priv->gtt.base.start, |
1712 | dev_priv->gtt.base.total, | |
e568af1c | 1713 | true); |
91e56499 CW |
1714 | |
1715 | i915_ggtt_flush(dev_priv); | |
828c7908 BW |
1716 | } |
1717 | ||
74163907 | 1718 | int i915_gem_gtt_prepare_object(struct drm_i915_gem_object *obj) |
7c2e6fdf | 1719 | { |
9da3da66 | 1720 | if (obj->has_dma_mapping) |
74163907 | 1721 | return 0; |
9da3da66 CW |
1722 | |
1723 | if (!dma_map_sg(&obj->base.dev->pdev->dev, | |
1724 | obj->pages->sgl, obj->pages->nents, | |
1725 | PCI_DMA_BIDIRECTIONAL)) | |
1726 | return -ENOSPC; | |
1727 | ||
1728 | return 0; | |
7c2e6fdf DV |
1729 | } |
1730 | ||
2c642b07 | 1731 | static void gen8_set_pte(void __iomem *addr, gen8_pte_t pte) |
94ec8f61 BW |
1732 | { |
1733 | #ifdef writeq | |
1734 | writeq(pte, addr); | |
1735 | #else | |
1736 | iowrite32((u32)pte, addr); | |
1737 | iowrite32(pte >> 32, addr + 4); | |
1738 | #endif | |
1739 | } | |
1740 | ||
1741 | static void gen8_ggtt_insert_entries(struct i915_address_space *vm, | |
1742 | struct sg_table *st, | |
782f1495 | 1743 | uint64_t start, |
24f3a8cf | 1744 | enum i915_cache_level level, u32 unused) |
94ec8f61 BW |
1745 | { |
1746 | struct drm_i915_private *dev_priv = vm->dev->dev_private; | |
782f1495 | 1747 | unsigned first_entry = start >> PAGE_SHIFT; |
07749ef3 MT |
1748 | gen8_pte_t __iomem *gtt_entries = |
1749 | (gen8_pte_t __iomem *)dev_priv->gtt.gsm + first_entry; | |
94ec8f61 BW |
1750 | int i = 0; |
1751 | struct sg_page_iter sg_iter; | |
57007df7 | 1752 | dma_addr_t addr = 0; /* shut up gcc */ |
94ec8f61 BW |
1753 | |
1754 | for_each_sg_page(st->sgl, &sg_iter, st->nents, 0) { | |
1755 | addr = sg_dma_address(sg_iter.sg) + | |
1756 | (sg_iter.sg_pgoffset << PAGE_SHIFT); | |
1757 | gen8_set_pte(>t_entries[i], | |
1758 | gen8_pte_encode(addr, level, true)); | |
1759 | i++; | |
1760 | } | |
1761 | ||
1762 | /* | |
1763 | * XXX: This serves as a posting read to make sure that the PTE has | |
1764 | * actually been updated. There is some concern that even though | |
1765 | * registers and PTEs are within the same BAR that they are potentially | |
1766 | * of NUMA access patterns. Therefore, even with the way we assume | |
1767 | * hardware should work, we must keep this posting read for paranoia. | |
1768 | */ | |
1769 | if (i != 0) | |
1770 | WARN_ON(readq(>t_entries[i-1]) | |
1771 | != gen8_pte_encode(addr, level, true)); | |
1772 | ||
94ec8f61 BW |
1773 | /* This next bit makes the above posting read even more important. We |
1774 | * want to flush the TLBs only after we're certain all the PTE updates | |
1775 | * have finished. | |
1776 | */ | |
1777 | I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN); | |
1778 | POSTING_READ(GFX_FLSH_CNTL_GEN6); | |
94ec8f61 BW |
1779 | } |
1780 | ||
e76e9aeb BW |
1781 | /* |
1782 | * Binds an object into the global gtt with the specified cache level. The object | |
1783 | * will be accessible to the GPU via commands whose operands reference offsets | |
1784 | * within the global GTT as well as accessible by the GPU through the GMADR | |
1785 | * mapped BAR (dev_priv->mm.gtt->gtt). | |
1786 | */ | |
853ba5d2 | 1787 | static void gen6_ggtt_insert_entries(struct i915_address_space *vm, |
7faf1ab2 | 1788 | struct sg_table *st, |
782f1495 | 1789 | uint64_t start, |
24f3a8cf | 1790 | enum i915_cache_level level, u32 flags) |
e76e9aeb | 1791 | { |
853ba5d2 | 1792 | struct drm_i915_private *dev_priv = vm->dev->dev_private; |
782f1495 | 1793 | unsigned first_entry = start >> PAGE_SHIFT; |
07749ef3 MT |
1794 | gen6_pte_t __iomem *gtt_entries = |
1795 | (gen6_pte_t __iomem *)dev_priv->gtt.gsm + first_entry; | |
6e995e23 ID |
1796 | int i = 0; |
1797 | struct sg_page_iter sg_iter; | |
57007df7 | 1798 | dma_addr_t addr = 0; |
e76e9aeb | 1799 | |
6e995e23 | 1800 | for_each_sg_page(st->sgl, &sg_iter, st->nents, 0) { |
2db76d7c | 1801 | addr = sg_page_iter_dma_address(&sg_iter); |
24f3a8cf | 1802 | iowrite32(vm->pte_encode(addr, level, true, flags), >t_entries[i]); |
6e995e23 | 1803 | i++; |
e76e9aeb BW |
1804 | } |
1805 | ||
e76e9aeb BW |
1806 | /* XXX: This serves as a posting read to make sure that the PTE has |
1807 | * actually been updated. There is some concern that even though | |
1808 | * registers and PTEs are within the same BAR that they are potentially | |
1809 | * of NUMA access patterns. Therefore, even with the way we assume | |
1810 | * hardware should work, we must keep this posting read for paranoia. | |
1811 | */ | |
57007df7 PM |
1812 | if (i != 0) { |
1813 | unsigned long gtt = readl(>t_entries[i-1]); | |
1814 | WARN_ON(gtt != vm->pte_encode(addr, level, true, flags)); | |
1815 | } | |
0f9b91c7 BW |
1816 | |
1817 | /* This next bit makes the above posting read even more important. We | |
1818 | * want to flush the TLBs only after we're certain all the PTE updates | |
1819 | * have finished. | |
1820 | */ | |
1821 | I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN); | |
1822 | POSTING_READ(GFX_FLSH_CNTL_GEN6); | |
e76e9aeb BW |
1823 | } |
1824 | ||
94ec8f61 | 1825 | static void gen8_ggtt_clear_range(struct i915_address_space *vm, |
782f1495 BW |
1826 | uint64_t start, |
1827 | uint64_t length, | |
94ec8f61 BW |
1828 | bool use_scratch) |
1829 | { | |
1830 | struct drm_i915_private *dev_priv = vm->dev->dev_private; | |
782f1495 BW |
1831 | unsigned first_entry = start >> PAGE_SHIFT; |
1832 | unsigned num_entries = length >> PAGE_SHIFT; | |
07749ef3 MT |
1833 | gen8_pte_t scratch_pte, __iomem *gtt_base = |
1834 | (gen8_pte_t __iomem *) dev_priv->gtt.gsm + first_entry; | |
94ec8f61 BW |
1835 | const int max_entries = gtt_total_entries(dev_priv->gtt) - first_entry; |
1836 | int i; | |
1837 | ||
1838 | if (WARN(num_entries > max_entries, | |
1839 | "First entry = %d; Num entries = %d (max=%d)\n", | |
1840 | first_entry, num_entries, max_entries)) | |
1841 | num_entries = max_entries; | |
1842 | ||
c114f76a | 1843 | scratch_pte = gen8_pte_encode(px_dma(vm->scratch_page), |
94ec8f61 BW |
1844 | I915_CACHE_LLC, |
1845 | use_scratch); | |
1846 | for (i = 0; i < num_entries; i++) | |
1847 | gen8_set_pte(>t_base[i], scratch_pte); | |
1848 | readl(gtt_base); | |
1849 | } | |
1850 | ||
853ba5d2 | 1851 | static void gen6_ggtt_clear_range(struct i915_address_space *vm, |
782f1495 BW |
1852 | uint64_t start, |
1853 | uint64_t length, | |
828c7908 | 1854 | bool use_scratch) |
7faf1ab2 | 1855 | { |
853ba5d2 | 1856 | struct drm_i915_private *dev_priv = vm->dev->dev_private; |
782f1495 BW |
1857 | unsigned first_entry = start >> PAGE_SHIFT; |
1858 | unsigned num_entries = length >> PAGE_SHIFT; | |
07749ef3 MT |
1859 | gen6_pte_t scratch_pte, __iomem *gtt_base = |
1860 | (gen6_pte_t __iomem *) dev_priv->gtt.gsm + first_entry; | |
a54c0c27 | 1861 | const int max_entries = gtt_total_entries(dev_priv->gtt) - first_entry; |
7faf1ab2 DV |
1862 | int i; |
1863 | ||
1864 | if (WARN(num_entries > max_entries, | |
1865 | "First entry = %d; Num entries = %d (max=%d)\n", | |
1866 | first_entry, num_entries, max_entries)) | |
1867 | num_entries = max_entries; | |
1868 | ||
c114f76a MK |
1869 | scratch_pte = vm->pte_encode(px_dma(vm->scratch_page), |
1870 | I915_CACHE_LLC, use_scratch, 0); | |
828c7908 | 1871 | |
7faf1ab2 DV |
1872 | for (i = 0; i < num_entries; i++) |
1873 | iowrite32(scratch_pte, >t_base[i]); | |
1874 | readl(gtt_base); | |
1875 | } | |
1876 | ||
d369d2d9 DV |
1877 | static void i915_ggtt_insert_entries(struct i915_address_space *vm, |
1878 | struct sg_table *pages, | |
1879 | uint64_t start, | |
1880 | enum i915_cache_level cache_level, u32 unused) | |
7faf1ab2 DV |
1881 | { |
1882 | unsigned int flags = (cache_level == I915_CACHE_NONE) ? | |
1883 | AGP_USER_MEMORY : AGP_USER_CACHED_MEMORY; | |
1884 | ||
d369d2d9 | 1885 | intel_gtt_insert_sg_entries(pages, start >> PAGE_SHIFT, flags); |
0875546c | 1886 | |
7faf1ab2 DV |
1887 | } |
1888 | ||
853ba5d2 | 1889 | static void i915_ggtt_clear_range(struct i915_address_space *vm, |
782f1495 BW |
1890 | uint64_t start, |
1891 | uint64_t length, | |
828c7908 | 1892 | bool unused) |
7faf1ab2 | 1893 | { |
782f1495 BW |
1894 | unsigned first_entry = start >> PAGE_SHIFT; |
1895 | unsigned num_entries = length >> PAGE_SHIFT; | |
7faf1ab2 DV |
1896 | intel_gtt_clear_range(first_entry, num_entries); |
1897 | } | |
1898 | ||
70b9f6f8 DV |
1899 | static int ggtt_bind_vma(struct i915_vma *vma, |
1900 | enum i915_cache_level cache_level, | |
1901 | u32 flags) | |
d5bd1449 | 1902 | { |
6f65e29a | 1903 | struct drm_device *dev = vma->vm->dev; |
7faf1ab2 | 1904 | struct drm_i915_private *dev_priv = dev->dev_private; |
6f65e29a | 1905 | struct drm_i915_gem_object *obj = vma->obj; |
ec7adb6e | 1906 | struct sg_table *pages = obj->pages; |
f329f5f6 | 1907 | u32 pte_flags = 0; |
70b9f6f8 DV |
1908 | int ret; |
1909 | ||
1910 | ret = i915_get_ggtt_vma_pages(vma); | |
1911 | if (ret) | |
1912 | return ret; | |
1913 | pages = vma->ggtt_view.pages; | |
7faf1ab2 | 1914 | |
24f3a8cf AG |
1915 | /* Currently applicable only to VLV */ |
1916 | if (obj->gt_ro) | |
f329f5f6 | 1917 | pte_flags |= PTE_READ_ONLY; |
24f3a8cf | 1918 | |
ec7adb6e | 1919 | |
6f65e29a | 1920 | if (!dev_priv->mm.aliasing_ppgtt || flags & GLOBAL_BIND) { |
0875546c DV |
1921 | vma->vm->insert_entries(vma->vm, pages, |
1922 | vma->node.start, | |
1923 | cache_level, pte_flags); | |
6f65e29a | 1924 | } |
d5bd1449 | 1925 | |
0875546c | 1926 | if (dev_priv->mm.aliasing_ppgtt && flags & LOCAL_BIND) { |
6f65e29a | 1927 | struct i915_hw_ppgtt *appgtt = dev_priv->mm.aliasing_ppgtt; |
ec7adb6e | 1928 | appgtt->base.insert_entries(&appgtt->base, pages, |
782f1495 | 1929 | vma->node.start, |
f329f5f6 | 1930 | cache_level, pte_flags); |
6f65e29a | 1931 | } |
70b9f6f8 DV |
1932 | |
1933 | return 0; | |
d5bd1449 CW |
1934 | } |
1935 | ||
6f65e29a | 1936 | static void ggtt_unbind_vma(struct i915_vma *vma) |
74163907 | 1937 | { |
6f65e29a | 1938 | struct drm_device *dev = vma->vm->dev; |
7faf1ab2 | 1939 | struct drm_i915_private *dev_priv = dev->dev_private; |
6f65e29a | 1940 | struct drm_i915_gem_object *obj = vma->obj; |
06615ee5 JL |
1941 | const uint64_t size = min_t(uint64_t, |
1942 | obj->base.size, | |
1943 | vma->node.size); | |
6f65e29a | 1944 | |
aff43766 | 1945 | if (vma->bound & GLOBAL_BIND) { |
782f1495 BW |
1946 | vma->vm->clear_range(vma->vm, |
1947 | vma->node.start, | |
06615ee5 | 1948 | size, |
6f65e29a | 1949 | true); |
6f65e29a | 1950 | } |
74898d7e | 1951 | |
0875546c | 1952 | if (dev_priv->mm.aliasing_ppgtt && vma->bound & LOCAL_BIND) { |
6f65e29a | 1953 | struct i915_hw_ppgtt *appgtt = dev_priv->mm.aliasing_ppgtt; |
06615ee5 | 1954 | |
6f65e29a | 1955 | appgtt->base.clear_range(&appgtt->base, |
782f1495 | 1956 | vma->node.start, |
06615ee5 | 1957 | size, |
6f65e29a | 1958 | true); |
6f65e29a | 1959 | } |
74163907 DV |
1960 | } |
1961 | ||
1962 | void i915_gem_gtt_finish_object(struct drm_i915_gem_object *obj) | |
7c2e6fdf | 1963 | { |
5c042287 BW |
1964 | struct drm_device *dev = obj->base.dev; |
1965 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1966 | bool interruptible; | |
1967 | ||
1968 | interruptible = do_idling(dev_priv); | |
1969 | ||
9da3da66 CW |
1970 | if (!obj->has_dma_mapping) |
1971 | dma_unmap_sg(&dev->pdev->dev, | |
1972 | obj->pages->sgl, obj->pages->nents, | |
1973 | PCI_DMA_BIDIRECTIONAL); | |
5c042287 BW |
1974 | |
1975 | undo_idling(dev_priv, interruptible); | |
7c2e6fdf | 1976 | } |
644ec02b | 1977 | |
42d6ab48 CW |
1978 | static void i915_gtt_color_adjust(struct drm_mm_node *node, |
1979 | unsigned long color, | |
440fd528 TR |
1980 | u64 *start, |
1981 | u64 *end) | |
42d6ab48 CW |
1982 | { |
1983 | if (node->color != color) | |
1984 | *start += 4096; | |
1985 | ||
1986 | if (!list_empty(&node->node_list)) { | |
1987 | node = list_entry(node->node_list.next, | |
1988 | struct drm_mm_node, | |
1989 | node_list); | |
1990 | if (node->allocated && node->color != color) | |
1991 | *end -= 4096; | |
1992 | } | |
1993 | } | |
fbe5d36e | 1994 | |
f548c0e9 DV |
1995 | static int i915_gem_setup_global_gtt(struct drm_device *dev, |
1996 | unsigned long start, | |
1997 | unsigned long mappable_end, | |
1998 | unsigned long end) | |
644ec02b | 1999 | { |
e78891ca BW |
2000 | /* Let GEM Manage all of the aperture. |
2001 | * | |
2002 | * However, leave one page at the end still bound to the scratch page. | |
2003 | * There are a number of places where the hardware apparently prefetches | |
2004 | * past the end of the object, and we've seen multiple hangs with the | |
2005 | * GPU head pointer stuck in a batchbuffer bound at the last page of the | |
2006 | * aperture. One page should be enough to keep any prefetching inside | |
2007 | * of the aperture. | |
2008 | */ | |
40d74980 BW |
2009 | struct drm_i915_private *dev_priv = dev->dev_private; |
2010 | struct i915_address_space *ggtt_vm = &dev_priv->gtt.base; | |
ed2f3452 CW |
2011 | struct drm_mm_node *entry; |
2012 | struct drm_i915_gem_object *obj; | |
2013 | unsigned long hole_start, hole_end; | |
fa76da34 | 2014 | int ret; |
644ec02b | 2015 | |
35451cb6 BW |
2016 | BUG_ON(mappable_end > end); |
2017 | ||
ed2f3452 | 2018 | /* Subtract the guard page ... */ |
40d74980 | 2019 | drm_mm_init(&ggtt_vm->mm, start, end - start - PAGE_SIZE); |
5dda8fa3 YZ |
2020 | |
2021 | dev_priv->gtt.base.start = start; | |
2022 | dev_priv->gtt.base.total = end - start; | |
2023 | ||
2024 | if (intel_vgpu_active(dev)) { | |
2025 | ret = intel_vgt_balloon(dev); | |
2026 | if (ret) | |
2027 | return ret; | |
2028 | } | |
2029 | ||
42d6ab48 | 2030 | if (!HAS_LLC(dev)) |
93bd8649 | 2031 | dev_priv->gtt.base.mm.color_adjust = i915_gtt_color_adjust; |
644ec02b | 2032 | |
ed2f3452 | 2033 | /* Mark any preallocated objects as occupied */ |
35c20a60 | 2034 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) { |
40d74980 | 2035 | struct i915_vma *vma = i915_gem_obj_to_vma(obj, ggtt_vm); |
fa76da34 | 2036 | |
edd41a87 | 2037 | DRM_DEBUG_KMS("reserving preallocated space: %lx + %zx\n", |
c6cfb325 BW |
2038 | i915_gem_obj_ggtt_offset(obj), obj->base.size); |
2039 | ||
2040 | WARN_ON(i915_gem_obj_ggtt_bound(obj)); | |
40d74980 | 2041 | ret = drm_mm_reserve_node(&ggtt_vm->mm, &vma->node); |
6c5566a8 DV |
2042 | if (ret) { |
2043 | DRM_DEBUG_KMS("Reservation failed: %i\n", ret); | |
2044 | return ret; | |
2045 | } | |
aff43766 | 2046 | vma->bound |= GLOBAL_BIND; |
ed2f3452 CW |
2047 | } |
2048 | ||
ed2f3452 | 2049 | /* Clear any non-preallocated blocks */ |
40d74980 | 2050 | drm_mm_for_each_hole(entry, &ggtt_vm->mm, hole_start, hole_end) { |
ed2f3452 CW |
2051 | DRM_DEBUG_KMS("clearing unused GTT space: [%lx, %lx]\n", |
2052 | hole_start, hole_end); | |
782f1495 BW |
2053 | ggtt_vm->clear_range(ggtt_vm, hole_start, |
2054 | hole_end - hole_start, true); | |
ed2f3452 CW |
2055 | } |
2056 | ||
2057 | /* And finally clear the reserved guard page */ | |
782f1495 | 2058 | ggtt_vm->clear_range(ggtt_vm, end - PAGE_SIZE, PAGE_SIZE, true); |
6c5566a8 | 2059 | |
fa76da34 DV |
2060 | if (USES_PPGTT(dev) && !USES_FULL_PPGTT(dev)) { |
2061 | struct i915_hw_ppgtt *ppgtt; | |
2062 | ||
2063 | ppgtt = kzalloc(sizeof(*ppgtt), GFP_KERNEL); | |
2064 | if (!ppgtt) | |
2065 | return -ENOMEM; | |
2066 | ||
5c5f6457 DV |
2067 | ret = __hw_ppgtt_init(dev, ppgtt); |
2068 | if (ret) { | |
2069 | ppgtt->base.cleanup(&ppgtt->base); | |
2070 | kfree(ppgtt); | |
2071 | return ret; | |
2072 | } | |
2073 | ||
2074 | if (ppgtt->base.allocate_va_range) | |
2075 | ret = ppgtt->base.allocate_va_range(&ppgtt->base, 0, | |
2076 | ppgtt->base.total); | |
4933d519 | 2077 | if (ret) { |
061dd493 | 2078 | ppgtt->base.cleanup(&ppgtt->base); |
4933d519 | 2079 | kfree(ppgtt); |
fa76da34 | 2080 | return ret; |
4933d519 | 2081 | } |
fa76da34 | 2082 | |
5c5f6457 DV |
2083 | ppgtt->base.clear_range(&ppgtt->base, |
2084 | ppgtt->base.start, | |
2085 | ppgtt->base.total, | |
2086 | true); | |
2087 | ||
fa76da34 DV |
2088 | dev_priv->mm.aliasing_ppgtt = ppgtt; |
2089 | } | |
2090 | ||
6c5566a8 | 2091 | return 0; |
e76e9aeb BW |
2092 | } |
2093 | ||
d7e5008f BW |
2094 | void i915_gem_init_global_gtt(struct drm_device *dev) |
2095 | { | |
2096 | struct drm_i915_private *dev_priv = dev->dev_private; | |
c44ef60e | 2097 | u64 gtt_size, mappable_size; |
d7e5008f | 2098 | |
853ba5d2 | 2099 | gtt_size = dev_priv->gtt.base.total; |
93d18799 | 2100 | mappable_size = dev_priv->gtt.mappable_end; |
d7e5008f | 2101 | |
e78891ca | 2102 | i915_gem_setup_global_gtt(dev, 0, mappable_size, gtt_size); |
e76e9aeb BW |
2103 | } |
2104 | ||
90d0a0e8 DV |
2105 | void i915_global_gtt_cleanup(struct drm_device *dev) |
2106 | { | |
2107 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2108 | struct i915_address_space *vm = &dev_priv->gtt.base; | |
2109 | ||
70e32544 DV |
2110 | if (dev_priv->mm.aliasing_ppgtt) { |
2111 | struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt; | |
2112 | ||
2113 | ppgtt->base.cleanup(&ppgtt->base); | |
2114 | } | |
2115 | ||
90d0a0e8 | 2116 | if (drm_mm_initialized(&vm->mm)) { |
5dda8fa3 YZ |
2117 | if (intel_vgpu_active(dev)) |
2118 | intel_vgt_deballoon(); | |
2119 | ||
90d0a0e8 DV |
2120 | drm_mm_takedown(&vm->mm); |
2121 | list_del(&vm->global_link); | |
2122 | } | |
2123 | ||
2124 | vm->cleanup(vm); | |
2125 | } | |
70e32544 | 2126 | |
c114f76a | 2127 | static int alloc_scratch_page(struct i915_address_space *vm) |
e76e9aeb | 2128 | { |
c114f76a MK |
2129 | struct i915_page_scratch *sp; |
2130 | int ret; | |
2131 | ||
2132 | WARN_ON(vm->scratch_page); | |
e76e9aeb | 2133 | |
c114f76a MK |
2134 | sp = kzalloc(sizeof(*sp), GFP_KERNEL); |
2135 | if (sp == NULL) | |
e76e9aeb | 2136 | return -ENOMEM; |
e76e9aeb | 2137 | |
c114f76a MK |
2138 | ret = __setup_page_dma(vm->dev, px_base(sp), GFP_DMA32 | __GFP_ZERO); |
2139 | if (ret) { | |
2140 | kfree(sp); | |
2141 | return ret; | |
ea3f5d26 | 2142 | } |
c114f76a MK |
2143 | |
2144 | set_pages_uc(px_page(sp), 1); | |
2145 | ||
2146 | vm->scratch_page = sp; | |
e76e9aeb BW |
2147 | |
2148 | return 0; | |
2149 | } | |
2150 | ||
c114f76a | 2151 | static void free_scratch_page(struct i915_address_space *vm) |
e76e9aeb | 2152 | { |
c114f76a | 2153 | struct i915_page_scratch *sp = vm->scratch_page; |
853ba5d2 | 2154 | |
c114f76a MK |
2155 | set_pages_wb(px_page(sp), 1); |
2156 | ||
2157 | cleanup_px(vm->dev, sp); | |
2158 | kfree(sp); | |
2159 | ||
2160 | vm->scratch_page = NULL; | |
e76e9aeb BW |
2161 | } |
2162 | ||
2c642b07 | 2163 | static unsigned int gen6_get_total_gtt_size(u16 snb_gmch_ctl) |
e76e9aeb BW |
2164 | { |
2165 | snb_gmch_ctl >>= SNB_GMCH_GGMS_SHIFT; | |
2166 | snb_gmch_ctl &= SNB_GMCH_GGMS_MASK; | |
2167 | return snb_gmch_ctl << 20; | |
2168 | } | |
2169 | ||
2c642b07 | 2170 | static unsigned int gen8_get_total_gtt_size(u16 bdw_gmch_ctl) |
9459d252 BW |
2171 | { |
2172 | bdw_gmch_ctl >>= BDW_GMCH_GGMS_SHIFT; | |
2173 | bdw_gmch_ctl &= BDW_GMCH_GGMS_MASK; | |
2174 | if (bdw_gmch_ctl) | |
2175 | bdw_gmch_ctl = 1 << bdw_gmch_ctl; | |
562d55d9 BW |
2176 | |
2177 | #ifdef CONFIG_X86_32 | |
2178 | /* Limit 32b platforms to a 2GB GGTT: 4 << 20 / pte size * PAGE_SIZE */ | |
2179 | if (bdw_gmch_ctl > 4) | |
2180 | bdw_gmch_ctl = 4; | |
2181 | #endif | |
2182 | ||
9459d252 BW |
2183 | return bdw_gmch_ctl << 20; |
2184 | } | |
2185 | ||
2c642b07 | 2186 | static unsigned int chv_get_total_gtt_size(u16 gmch_ctrl) |
d7f25f23 DL |
2187 | { |
2188 | gmch_ctrl >>= SNB_GMCH_GGMS_SHIFT; | |
2189 | gmch_ctrl &= SNB_GMCH_GGMS_MASK; | |
2190 | ||
2191 | if (gmch_ctrl) | |
2192 | return 1 << (20 + gmch_ctrl); | |
2193 | ||
2194 | return 0; | |
2195 | } | |
2196 | ||
2c642b07 | 2197 | static size_t gen6_get_stolen_size(u16 snb_gmch_ctl) |
e76e9aeb BW |
2198 | { |
2199 | snb_gmch_ctl >>= SNB_GMCH_GMS_SHIFT; | |
2200 | snb_gmch_ctl &= SNB_GMCH_GMS_MASK; | |
2201 | return snb_gmch_ctl << 25; /* 32 MB units */ | |
2202 | } | |
2203 | ||
2c642b07 | 2204 | static size_t gen8_get_stolen_size(u16 bdw_gmch_ctl) |
9459d252 BW |
2205 | { |
2206 | bdw_gmch_ctl >>= BDW_GMCH_GMS_SHIFT; | |
2207 | bdw_gmch_ctl &= BDW_GMCH_GMS_MASK; | |
2208 | return bdw_gmch_ctl << 25; /* 32 MB units */ | |
2209 | } | |
2210 | ||
d7f25f23 DL |
2211 | static size_t chv_get_stolen_size(u16 gmch_ctrl) |
2212 | { | |
2213 | gmch_ctrl >>= SNB_GMCH_GMS_SHIFT; | |
2214 | gmch_ctrl &= SNB_GMCH_GMS_MASK; | |
2215 | ||
2216 | /* | |
2217 | * 0x0 to 0x10: 32MB increments starting at 0MB | |
2218 | * 0x11 to 0x16: 4MB increments starting at 8MB | |
2219 | * 0x17 to 0x1d: 4MB increments start at 36MB | |
2220 | */ | |
2221 | if (gmch_ctrl < 0x11) | |
2222 | return gmch_ctrl << 25; | |
2223 | else if (gmch_ctrl < 0x17) | |
2224 | return (gmch_ctrl - 0x11 + 2) << 22; | |
2225 | else | |
2226 | return (gmch_ctrl - 0x17 + 9) << 22; | |
2227 | } | |
2228 | ||
66375014 DL |
2229 | static size_t gen9_get_stolen_size(u16 gen9_gmch_ctl) |
2230 | { | |
2231 | gen9_gmch_ctl >>= BDW_GMCH_GMS_SHIFT; | |
2232 | gen9_gmch_ctl &= BDW_GMCH_GMS_MASK; | |
2233 | ||
2234 | if (gen9_gmch_ctl < 0xf0) | |
2235 | return gen9_gmch_ctl << 25; /* 32 MB units */ | |
2236 | else | |
2237 | /* 4MB increments starting at 0xf0 for 4MB */ | |
2238 | return (gen9_gmch_ctl - 0xf0 + 1) << 22; | |
2239 | } | |
2240 | ||
63340133 BW |
2241 | static int ggtt_probe_common(struct drm_device *dev, |
2242 | size_t gtt_size) | |
2243 | { | |
2244 | struct drm_i915_private *dev_priv = dev->dev_private; | |
21c34607 | 2245 | phys_addr_t gtt_phys_addr; |
63340133 BW |
2246 | int ret; |
2247 | ||
2248 | /* For Modern GENs the PTEs and register space are split in the BAR */ | |
21c34607 | 2249 | gtt_phys_addr = pci_resource_start(dev->pdev, 0) + |
63340133 BW |
2250 | (pci_resource_len(dev->pdev, 0) / 2); |
2251 | ||
2a073f89 ID |
2252 | /* |
2253 | * On BXT writes larger than 64 bit to the GTT pagetable range will be | |
2254 | * dropped. For WC mappings in general we have 64 byte burst writes | |
2255 | * when the WC buffer is flushed, so we can't use it, but have to | |
2256 | * resort to an uncached mapping. The WC issue is easily caught by the | |
2257 | * readback check when writing GTT PTE entries. | |
2258 | */ | |
2259 | if (IS_BROXTON(dev)) | |
2260 | dev_priv->gtt.gsm = ioremap_nocache(gtt_phys_addr, gtt_size); | |
2261 | else | |
2262 | dev_priv->gtt.gsm = ioremap_wc(gtt_phys_addr, gtt_size); | |
63340133 BW |
2263 | if (!dev_priv->gtt.gsm) { |
2264 | DRM_ERROR("Failed to map the gtt page table\n"); | |
2265 | return -ENOMEM; | |
2266 | } | |
2267 | ||
c114f76a | 2268 | ret = alloc_scratch_page(&dev_priv->gtt.base); |
63340133 BW |
2269 | if (ret) { |
2270 | DRM_ERROR("Scratch setup failed\n"); | |
2271 | /* iounmap will also get called at remove, but meh */ | |
2272 | iounmap(dev_priv->gtt.gsm); | |
2273 | } | |
2274 | ||
2275 | return ret; | |
2276 | } | |
2277 | ||
fbe5d36e BW |
2278 | /* The GGTT and PPGTT need a private PPAT setup in order to handle cacheability |
2279 | * bits. When using advanced contexts each context stores its own PAT, but | |
2280 | * writing this data shouldn't be harmful even in those cases. */ | |
ee0ce478 | 2281 | static void bdw_setup_private_ppat(struct drm_i915_private *dev_priv) |
fbe5d36e | 2282 | { |
fbe5d36e BW |
2283 | uint64_t pat; |
2284 | ||
2285 | pat = GEN8_PPAT(0, GEN8_PPAT_WB | GEN8_PPAT_LLC) | /* for normal objects, no eLLC */ | |
2286 | GEN8_PPAT(1, GEN8_PPAT_WC | GEN8_PPAT_LLCELLC) | /* for something pointing to ptes? */ | |
2287 | GEN8_PPAT(2, GEN8_PPAT_WT | GEN8_PPAT_LLCELLC) | /* for scanout with eLLC */ | |
2288 | GEN8_PPAT(3, GEN8_PPAT_UC) | /* Uncached objects, mostly for scanout */ | |
2289 | GEN8_PPAT(4, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(0)) | | |
2290 | GEN8_PPAT(5, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(1)) | | |
2291 | GEN8_PPAT(6, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(2)) | | |
2292 | GEN8_PPAT(7, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(3)); | |
2293 | ||
d6a8b72e RV |
2294 | if (!USES_PPGTT(dev_priv->dev)) |
2295 | /* Spec: "For GGTT, there is NO pat_sel[2:0] from the entry, | |
2296 | * so RTL will always use the value corresponding to | |
2297 | * pat_sel = 000". | |
2298 | * So let's disable cache for GGTT to avoid screen corruptions. | |
2299 | * MOCS still can be used though. | |
2300 | * - System agent ggtt writes (i.e. cpu gtt mmaps) already work | |
2301 | * before this patch, i.e. the same uncached + snooping access | |
2302 | * like on gen6/7 seems to be in effect. | |
2303 | * - So this just fixes blitter/render access. Again it looks | |
2304 | * like it's not just uncached access, but uncached + snooping. | |
2305 | * So we can still hold onto all our assumptions wrt cpu | |
2306 | * clflushing on LLC machines. | |
2307 | */ | |
2308 | pat = GEN8_PPAT(0, GEN8_PPAT_UC); | |
2309 | ||
fbe5d36e BW |
2310 | /* XXX: spec defines this as 2 distinct registers. It's unclear if a 64b |
2311 | * write would work. */ | |
2312 | I915_WRITE(GEN8_PRIVATE_PAT, pat); | |
2313 | I915_WRITE(GEN8_PRIVATE_PAT + 4, pat >> 32); | |
2314 | } | |
2315 | ||
ee0ce478 VS |
2316 | static void chv_setup_private_ppat(struct drm_i915_private *dev_priv) |
2317 | { | |
2318 | uint64_t pat; | |
2319 | ||
2320 | /* | |
2321 | * Map WB on BDW to snooped on CHV. | |
2322 | * | |
2323 | * Only the snoop bit has meaning for CHV, the rest is | |
2324 | * ignored. | |
2325 | * | |
cf3d262e VS |
2326 | * The hardware will never snoop for certain types of accesses: |
2327 | * - CPU GTT (GMADR->GGTT->no snoop->memory) | |
2328 | * - PPGTT page tables | |
2329 | * - some other special cycles | |
2330 | * | |
2331 | * As with BDW, we also need to consider the following for GT accesses: | |
2332 | * "For GGTT, there is NO pat_sel[2:0] from the entry, | |
2333 | * so RTL will always use the value corresponding to | |
2334 | * pat_sel = 000". | |
2335 | * Which means we must set the snoop bit in PAT entry 0 | |
2336 | * in order to keep the global status page working. | |
ee0ce478 VS |
2337 | */ |
2338 | pat = GEN8_PPAT(0, CHV_PPAT_SNOOP) | | |
2339 | GEN8_PPAT(1, 0) | | |
2340 | GEN8_PPAT(2, 0) | | |
2341 | GEN8_PPAT(3, 0) | | |
2342 | GEN8_PPAT(4, CHV_PPAT_SNOOP) | | |
2343 | GEN8_PPAT(5, CHV_PPAT_SNOOP) | | |
2344 | GEN8_PPAT(6, CHV_PPAT_SNOOP) | | |
2345 | GEN8_PPAT(7, CHV_PPAT_SNOOP); | |
2346 | ||
2347 | I915_WRITE(GEN8_PRIVATE_PAT, pat); | |
2348 | I915_WRITE(GEN8_PRIVATE_PAT + 4, pat >> 32); | |
2349 | } | |
2350 | ||
63340133 | 2351 | static int gen8_gmch_probe(struct drm_device *dev, |
c44ef60e | 2352 | u64 *gtt_total, |
63340133 BW |
2353 | size_t *stolen, |
2354 | phys_addr_t *mappable_base, | |
c44ef60e | 2355 | u64 *mappable_end) |
63340133 BW |
2356 | { |
2357 | struct drm_i915_private *dev_priv = dev->dev_private; | |
c44ef60e | 2358 | u64 gtt_size; |
63340133 BW |
2359 | u16 snb_gmch_ctl; |
2360 | int ret; | |
2361 | ||
2362 | /* TODO: We're not aware of mappable constraints on gen8 yet */ | |
2363 | *mappable_base = pci_resource_start(dev->pdev, 2); | |
2364 | *mappable_end = pci_resource_len(dev->pdev, 2); | |
2365 | ||
2366 | if (!pci_set_dma_mask(dev->pdev, DMA_BIT_MASK(39))) | |
2367 | pci_set_consistent_dma_mask(dev->pdev, DMA_BIT_MASK(39)); | |
2368 | ||
2369 | pci_read_config_word(dev->pdev, SNB_GMCH_CTRL, &snb_gmch_ctl); | |
2370 | ||
66375014 DL |
2371 | if (INTEL_INFO(dev)->gen >= 9) { |
2372 | *stolen = gen9_get_stolen_size(snb_gmch_ctl); | |
2373 | gtt_size = gen8_get_total_gtt_size(snb_gmch_ctl); | |
2374 | } else if (IS_CHERRYVIEW(dev)) { | |
d7f25f23 DL |
2375 | *stolen = chv_get_stolen_size(snb_gmch_ctl); |
2376 | gtt_size = chv_get_total_gtt_size(snb_gmch_ctl); | |
2377 | } else { | |
2378 | *stolen = gen8_get_stolen_size(snb_gmch_ctl); | |
2379 | gtt_size = gen8_get_total_gtt_size(snb_gmch_ctl); | |
2380 | } | |
63340133 | 2381 | |
07749ef3 | 2382 | *gtt_total = (gtt_size / sizeof(gen8_pte_t)) << PAGE_SHIFT; |
63340133 | 2383 | |
5a4e33a3 | 2384 | if (IS_CHERRYVIEW(dev) || IS_BROXTON(dev)) |
ee0ce478 VS |
2385 | chv_setup_private_ppat(dev_priv); |
2386 | else | |
2387 | bdw_setup_private_ppat(dev_priv); | |
fbe5d36e | 2388 | |
63340133 BW |
2389 | ret = ggtt_probe_common(dev, gtt_size); |
2390 | ||
94ec8f61 BW |
2391 | dev_priv->gtt.base.clear_range = gen8_ggtt_clear_range; |
2392 | dev_priv->gtt.base.insert_entries = gen8_ggtt_insert_entries; | |
777dc5bb DV |
2393 | dev_priv->gtt.base.bind_vma = ggtt_bind_vma; |
2394 | dev_priv->gtt.base.unbind_vma = ggtt_unbind_vma; | |
63340133 BW |
2395 | |
2396 | return ret; | |
2397 | } | |
2398 | ||
baa09f5f | 2399 | static int gen6_gmch_probe(struct drm_device *dev, |
c44ef60e | 2400 | u64 *gtt_total, |
41907ddc BW |
2401 | size_t *stolen, |
2402 | phys_addr_t *mappable_base, | |
c44ef60e | 2403 | u64 *mappable_end) |
e76e9aeb BW |
2404 | { |
2405 | struct drm_i915_private *dev_priv = dev->dev_private; | |
baa09f5f | 2406 | unsigned int gtt_size; |
e76e9aeb | 2407 | u16 snb_gmch_ctl; |
e76e9aeb BW |
2408 | int ret; |
2409 | ||
41907ddc BW |
2410 | *mappable_base = pci_resource_start(dev->pdev, 2); |
2411 | *mappable_end = pci_resource_len(dev->pdev, 2); | |
2412 | ||
baa09f5f BW |
2413 | /* 64/512MB is the current min/max we actually know of, but this is just |
2414 | * a coarse sanity check. | |
e76e9aeb | 2415 | */ |
41907ddc | 2416 | if ((*mappable_end < (64<<20) || (*mappable_end > (512<<20)))) { |
c44ef60e | 2417 | DRM_ERROR("Unknown GMADR size (%llx)\n", |
baa09f5f BW |
2418 | dev_priv->gtt.mappable_end); |
2419 | return -ENXIO; | |
e76e9aeb BW |
2420 | } |
2421 | ||
e76e9aeb BW |
2422 | if (!pci_set_dma_mask(dev->pdev, DMA_BIT_MASK(40))) |
2423 | pci_set_consistent_dma_mask(dev->pdev, DMA_BIT_MASK(40)); | |
e76e9aeb | 2424 | pci_read_config_word(dev->pdev, SNB_GMCH_CTRL, &snb_gmch_ctl); |
e76e9aeb | 2425 | |
c4ae25ec | 2426 | *stolen = gen6_get_stolen_size(snb_gmch_ctl); |
a93e4161 | 2427 | |
63340133 | 2428 | gtt_size = gen6_get_total_gtt_size(snb_gmch_ctl); |
07749ef3 | 2429 | *gtt_total = (gtt_size / sizeof(gen6_pte_t)) << PAGE_SHIFT; |
e76e9aeb | 2430 | |
63340133 | 2431 | ret = ggtt_probe_common(dev, gtt_size); |
e76e9aeb | 2432 | |
853ba5d2 BW |
2433 | dev_priv->gtt.base.clear_range = gen6_ggtt_clear_range; |
2434 | dev_priv->gtt.base.insert_entries = gen6_ggtt_insert_entries; | |
777dc5bb DV |
2435 | dev_priv->gtt.base.bind_vma = ggtt_bind_vma; |
2436 | dev_priv->gtt.base.unbind_vma = ggtt_unbind_vma; | |
7faf1ab2 | 2437 | |
e76e9aeb BW |
2438 | return ret; |
2439 | } | |
2440 | ||
853ba5d2 | 2441 | static void gen6_gmch_remove(struct i915_address_space *vm) |
e76e9aeb | 2442 | { |
853ba5d2 BW |
2443 | |
2444 | struct i915_gtt *gtt = container_of(vm, struct i915_gtt, base); | |
5ed16782 | 2445 | |
853ba5d2 | 2446 | iounmap(gtt->gsm); |
c114f76a | 2447 | free_scratch_page(vm); |
644ec02b | 2448 | } |
baa09f5f BW |
2449 | |
2450 | static int i915_gmch_probe(struct drm_device *dev, | |
c44ef60e | 2451 | u64 *gtt_total, |
41907ddc BW |
2452 | size_t *stolen, |
2453 | phys_addr_t *mappable_base, | |
c44ef60e | 2454 | u64 *mappable_end) |
baa09f5f BW |
2455 | { |
2456 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2457 | int ret; | |
2458 | ||
baa09f5f BW |
2459 | ret = intel_gmch_probe(dev_priv->bridge_dev, dev_priv->dev->pdev, NULL); |
2460 | if (!ret) { | |
2461 | DRM_ERROR("failed to set up gmch\n"); | |
2462 | return -EIO; | |
2463 | } | |
2464 | ||
41907ddc | 2465 | intel_gtt_get(gtt_total, stolen, mappable_base, mappable_end); |
baa09f5f BW |
2466 | |
2467 | dev_priv->gtt.do_idle_maps = needs_idle_maps(dev_priv->dev); | |
d369d2d9 | 2468 | dev_priv->gtt.base.insert_entries = i915_ggtt_insert_entries; |
853ba5d2 | 2469 | dev_priv->gtt.base.clear_range = i915_ggtt_clear_range; |
d369d2d9 DV |
2470 | dev_priv->gtt.base.bind_vma = ggtt_bind_vma; |
2471 | dev_priv->gtt.base.unbind_vma = ggtt_unbind_vma; | |
baa09f5f | 2472 | |
c0a7f818 CW |
2473 | if (unlikely(dev_priv->gtt.do_idle_maps)) |
2474 | DRM_INFO("applying Ironlake quirks for intel_iommu\n"); | |
2475 | ||
baa09f5f BW |
2476 | return 0; |
2477 | } | |
2478 | ||
853ba5d2 | 2479 | static void i915_gmch_remove(struct i915_address_space *vm) |
baa09f5f BW |
2480 | { |
2481 | intel_gmch_remove(); | |
2482 | } | |
2483 | ||
2484 | int i915_gem_gtt_init(struct drm_device *dev) | |
2485 | { | |
2486 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2487 | struct i915_gtt *gtt = &dev_priv->gtt; | |
baa09f5f BW |
2488 | int ret; |
2489 | ||
baa09f5f | 2490 | if (INTEL_INFO(dev)->gen <= 5) { |
b2f21b4d | 2491 | gtt->gtt_probe = i915_gmch_probe; |
853ba5d2 | 2492 | gtt->base.cleanup = i915_gmch_remove; |
63340133 | 2493 | } else if (INTEL_INFO(dev)->gen < 8) { |
b2f21b4d | 2494 | gtt->gtt_probe = gen6_gmch_probe; |
853ba5d2 | 2495 | gtt->base.cleanup = gen6_gmch_remove; |
4d15c145 | 2496 | if (IS_HASWELL(dev) && dev_priv->ellc_size) |
853ba5d2 | 2497 | gtt->base.pte_encode = iris_pte_encode; |
4d15c145 | 2498 | else if (IS_HASWELL(dev)) |
853ba5d2 | 2499 | gtt->base.pte_encode = hsw_pte_encode; |
b2f21b4d | 2500 | else if (IS_VALLEYVIEW(dev)) |
853ba5d2 | 2501 | gtt->base.pte_encode = byt_pte_encode; |
350ec881 CW |
2502 | else if (INTEL_INFO(dev)->gen >= 7) |
2503 | gtt->base.pte_encode = ivb_pte_encode; | |
b2f21b4d | 2504 | else |
350ec881 | 2505 | gtt->base.pte_encode = snb_pte_encode; |
63340133 BW |
2506 | } else { |
2507 | dev_priv->gtt.gtt_probe = gen8_gmch_probe; | |
2508 | dev_priv->gtt.base.cleanup = gen6_gmch_remove; | |
baa09f5f BW |
2509 | } |
2510 | ||
c114f76a MK |
2511 | gtt->base.dev = dev; |
2512 | ||
853ba5d2 | 2513 | ret = gtt->gtt_probe(dev, >t->base.total, >t->stolen_size, |
b2f21b4d | 2514 | >t->mappable_base, >t->mappable_end); |
a54c0c27 | 2515 | if (ret) |
baa09f5f | 2516 | return ret; |
baa09f5f | 2517 | |
baa09f5f | 2518 | /* GMADR is the PCI mmio aperture into the global GTT. */ |
c44ef60e | 2519 | DRM_INFO("Memory usable by graphics device = %lluM\n", |
853ba5d2 | 2520 | gtt->base.total >> 20); |
c44ef60e | 2521 | DRM_DEBUG_DRIVER("GMADR size = %lldM\n", gtt->mappable_end >> 20); |
b2f21b4d | 2522 | DRM_DEBUG_DRIVER("GTT stolen size = %zdM\n", gtt->stolen_size >> 20); |
5db6c735 DV |
2523 | #ifdef CONFIG_INTEL_IOMMU |
2524 | if (intel_iommu_gfx_mapped) | |
2525 | DRM_INFO("VT-d active for gfx access\n"); | |
2526 | #endif | |
cfa7c862 DV |
2527 | /* |
2528 | * i915.enable_ppgtt is read-only, so do an early pass to validate the | |
2529 | * user's requested state against the hardware/driver capabilities. We | |
2530 | * do this now so that we can print out any log messages once rather | |
2531 | * than every time we check intel_enable_ppgtt(). | |
2532 | */ | |
2533 | i915.enable_ppgtt = sanitize_enable_ppgtt(dev, i915.enable_ppgtt); | |
2534 | DRM_DEBUG_DRIVER("ppgtt mode: %i\n", i915.enable_ppgtt); | |
baa09f5f BW |
2535 | |
2536 | return 0; | |
2537 | } | |
6f65e29a | 2538 | |
fa42331b DV |
2539 | void i915_gem_restore_gtt_mappings(struct drm_device *dev) |
2540 | { | |
2541 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2542 | struct drm_i915_gem_object *obj; | |
2543 | struct i915_address_space *vm; | |
2544 | ||
2545 | i915_check_and_clear_faults(dev); | |
2546 | ||
2547 | /* First fill our portion of the GTT with scratch pages */ | |
2548 | dev_priv->gtt.base.clear_range(&dev_priv->gtt.base, | |
2549 | dev_priv->gtt.base.start, | |
2550 | dev_priv->gtt.base.total, | |
2551 | true); | |
2552 | ||
2553 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) { | |
2554 | struct i915_vma *vma = i915_gem_obj_to_vma(obj, | |
2555 | &dev_priv->gtt.base); | |
2556 | if (!vma) | |
2557 | continue; | |
2558 | ||
2559 | i915_gem_clflush_object(obj, obj->pin_display); | |
2560 | WARN_ON(i915_vma_bind(vma, obj->cache_level, PIN_UPDATE)); | |
2561 | } | |
2562 | ||
2563 | ||
2564 | if (INTEL_INFO(dev)->gen >= 8) { | |
2565 | if (IS_CHERRYVIEW(dev) || IS_BROXTON(dev)) | |
2566 | chv_setup_private_ppat(dev_priv); | |
2567 | else | |
2568 | bdw_setup_private_ppat(dev_priv); | |
2569 | ||
2570 | return; | |
2571 | } | |
2572 | ||
2573 | if (USES_PPGTT(dev)) { | |
2574 | list_for_each_entry(vm, &dev_priv->vm_list, global_link) { | |
2575 | /* TODO: Perhaps it shouldn't be gen6 specific */ | |
2576 | ||
2577 | struct i915_hw_ppgtt *ppgtt = | |
2578 | container_of(vm, struct i915_hw_ppgtt, | |
2579 | base); | |
2580 | ||
2581 | if (i915_is_ggtt(vm)) | |
2582 | ppgtt = dev_priv->mm.aliasing_ppgtt; | |
2583 | ||
2584 | gen6_write_page_range(dev_priv, &ppgtt->pd, | |
2585 | 0, ppgtt->base.total); | |
2586 | } | |
2587 | } | |
2588 | ||
2589 | i915_ggtt_flush(dev_priv); | |
2590 | } | |
2591 | ||
ec7adb6e JL |
2592 | static struct i915_vma * |
2593 | __i915_gem_vma_create(struct drm_i915_gem_object *obj, | |
2594 | struct i915_address_space *vm, | |
2595 | const struct i915_ggtt_view *ggtt_view) | |
6f65e29a | 2596 | { |
dabde5c7 | 2597 | struct i915_vma *vma; |
6f65e29a | 2598 | |
ec7adb6e JL |
2599 | if (WARN_ON(i915_is_ggtt(vm) != !!ggtt_view)) |
2600 | return ERR_PTR(-EINVAL); | |
e20d2ab7 CW |
2601 | |
2602 | vma = kmem_cache_zalloc(to_i915(obj->base.dev)->vmas, GFP_KERNEL); | |
dabde5c7 DC |
2603 | if (vma == NULL) |
2604 | return ERR_PTR(-ENOMEM); | |
ec7adb6e | 2605 | |
6f65e29a BW |
2606 | INIT_LIST_HEAD(&vma->vma_link); |
2607 | INIT_LIST_HEAD(&vma->mm_list); | |
2608 | INIT_LIST_HEAD(&vma->exec_list); | |
2609 | vma->vm = vm; | |
2610 | vma->obj = obj; | |
2611 | ||
777dc5bb | 2612 | if (i915_is_ggtt(vm)) |
ec7adb6e | 2613 | vma->ggtt_view = *ggtt_view; |
6f65e29a | 2614 | |
f7635669 TU |
2615 | list_add_tail(&vma->vma_link, &obj->vma_list); |
2616 | if (!i915_is_ggtt(vm)) | |
e07f0552 | 2617 | i915_ppgtt_get(i915_vm_to_ppgtt(vm)); |
6f65e29a BW |
2618 | |
2619 | return vma; | |
2620 | } | |
2621 | ||
2622 | struct i915_vma * | |
ec7adb6e JL |
2623 | i915_gem_obj_lookup_or_create_vma(struct drm_i915_gem_object *obj, |
2624 | struct i915_address_space *vm) | |
2625 | { | |
2626 | struct i915_vma *vma; | |
2627 | ||
2628 | vma = i915_gem_obj_to_vma(obj, vm); | |
2629 | if (!vma) | |
2630 | vma = __i915_gem_vma_create(obj, vm, | |
2631 | i915_is_ggtt(vm) ? &i915_ggtt_view_normal : NULL); | |
2632 | ||
2633 | return vma; | |
2634 | } | |
2635 | ||
2636 | struct i915_vma * | |
2637 | i915_gem_obj_lookup_or_create_ggtt_vma(struct drm_i915_gem_object *obj, | |
fe14d5f4 | 2638 | const struct i915_ggtt_view *view) |
6f65e29a | 2639 | { |
ec7adb6e | 2640 | struct i915_address_space *ggtt = i915_obj_to_ggtt(obj); |
6f65e29a BW |
2641 | struct i915_vma *vma; |
2642 | ||
ec7adb6e JL |
2643 | if (WARN_ON(!view)) |
2644 | return ERR_PTR(-EINVAL); | |
2645 | ||
2646 | vma = i915_gem_obj_to_ggtt_view(obj, view); | |
2647 | ||
2648 | if (IS_ERR(vma)) | |
2649 | return vma; | |
2650 | ||
6f65e29a | 2651 | if (!vma) |
ec7adb6e | 2652 | vma = __i915_gem_vma_create(obj, ggtt, view); |
6f65e29a BW |
2653 | |
2654 | return vma; | |
ec7adb6e | 2655 | |
6f65e29a | 2656 | } |
fe14d5f4 | 2657 | |
50470bb0 TU |
2658 | static void |
2659 | rotate_pages(dma_addr_t *in, unsigned int width, unsigned int height, | |
2660 | struct sg_table *st) | |
2661 | { | |
2662 | unsigned int column, row; | |
2663 | unsigned int src_idx; | |
2664 | struct scatterlist *sg = st->sgl; | |
2665 | ||
2666 | st->nents = 0; | |
2667 | ||
2668 | for (column = 0; column < width; column++) { | |
2669 | src_idx = width * (height - 1) + column; | |
2670 | for (row = 0; row < height; row++) { | |
2671 | st->nents++; | |
2672 | /* We don't need the pages, but need to initialize | |
2673 | * the entries so the sg list can be happily traversed. | |
2674 | * The only thing we need are DMA addresses. | |
2675 | */ | |
2676 | sg_set_page(sg, NULL, PAGE_SIZE, 0); | |
2677 | sg_dma_address(sg) = in[src_idx]; | |
2678 | sg_dma_len(sg) = PAGE_SIZE; | |
2679 | sg = sg_next(sg); | |
2680 | src_idx -= width; | |
2681 | } | |
2682 | } | |
2683 | } | |
2684 | ||
2685 | static struct sg_table * | |
2686 | intel_rotate_fb_obj_pages(struct i915_ggtt_view *ggtt_view, | |
2687 | struct drm_i915_gem_object *obj) | |
2688 | { | |
50470bb0 | 2689 | struct intel_rotation_info *rot_info = &ggtt_view->rotation_info; |
84fe03f7 | 2690 | unsigned int size_pages = rot_info->size >> PAGE_SHIFT; |
50470bb0 TU |
2691 | struct sg_page_iter sg_iter; |
2692 | unsigned long i; | |
2693 | dma_addr_t *page_addr_list; | |
2694 | struct sg_table *st; | |
1d00dad5 | 2695 | int ret = -ENOMEM; |
50470bb0 | 2696 | |
50470bb0 | 2697 | /* Allocate a temporary list of source pages for random access. */ |
84fe03f7 TU |
2698 | page_addr_list = drm_malloc_ab(obj->base.size / PAGE_SIZE, |
2699 | sizeof(dma_addr_t)); | |
50470bb0 TU |
2700 | if (!page_addr_list) |
2701 | return ERR_PTR(ret); | |
2702 | ||
2703 | /* Allocate target SG list. */ | |
2704 | st = kmalloc(sizeof(*st), GFP_KERNEL); | |
2705 | if (!st) | |
2706 | goto err_st_alloc; | |
2707 | ||
84fe03f7 | 2708 | ret = sg_alloc_table(st, size_pages, GFP_KERNEL); |
50470bb0 TU |
2709 | if (ret) |
2710 | goto err_sg_alloc; | |
2711 | ||
2712 | /* Populate source page list from the object. */ | |
2713 | i = 0; | |
2714 | for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, 0) { | |
2715 | page_addr_list[i] = sg_page_iter_dma_address(&sg_iter); | |
2716 | i++; | |
2717 | } | |
2718 | ||
2719 | /* Rotate the pages. */ | |
84fe03f7 TU |
2720 | rotate_pages(page_addr_list, |
2721 | rot_info->width_pages, rot_info->height_pages, | |
2722 | st); | |
50470bb0 TU |
2723 | |
2724 | DRM_DEBUG_KMS( | |
84fe03f7 | 2725 | "Created rotated page mapping for object size %zu (pitch=%u, height=%u, pixel_format=0x%x, %ux%u tiles, %u pages).\n", |
c9f8fd2d | 2726 | obj->base.size, rot_info->pitch, rot_info->height, |
84fe03f7 TU |
2727 | rot_info->pixel_format, rot_info->width_pages, |
2728 | rot_info->height_pages, size_pages); | |
50470bb0 TU |
2729 | |
2730 | drm_free_large(page_addr_list); | |
2731 | ||
2732 | return st; | |
2733 | ||
2734 | err_sg_alloc: | |
2735 | kfree(st); | |
2736 | err_st_alloc: | |
2737 | drm_free_large(page_addr_list); | |
2738 | ||
2739 | DRM_DEBUG_KMS( | |
84fe03f7 | 2740 | "Failed to create rotated mapping for object size %zu! (%d) (pitch=%u, height=%u, pixel_format=0x%x, %ux%u tiles, %u pages)\n", |
c9f8fd2d | 2741 | obj->base.size, ret, rot_info->pitch, rot_info->height, |
84fe03f7 TU |
2742 | rot_info->pixel_format, rot_info->width_pages, |
2743 | rot_info->height_pages, size_pages); | |
50470bb0 TU |
2744 | return ERR_PTR(ret); |
2745 | } | |
ec7adb6e | 2746 | |
8bd7ef16 JL |
2747 | static struct sg_table * |
2748 | intel_partial_pages(const struct i915_ggtt_view *view, | |
2749 | struct drm_i915_gem_object *obj) | |
2750 | { | |
2751 | struct sg_table *st; | |
2752 | struct scatterlist *sg; | |
2753 | struct sg_page_iter obj_sg_iter; | |
2754 | int ret = -ENOMEM; | |
2755 | ||
2756 | st = kmalloc(sizeof(*st), GFP_KERNEL); | |
2757 | if (!st) | |
2758 | goto err_st_alloc; | |
2759 | ||
2760 | ret = sg_alloc_table(st, view->params.partial.size, GFP_KERNEL); | |
2761 | if (ret) | |
2762 | goto err_sg_alloc; | |
2763 | ||
2764 | sg = st->sgl; | |
2765 | st->nents = 0; | |
2766 | for_each_sg_page(obj->pages->sgl, &obj_sg_iter, obj->pages->nents, | |
2767 | view->params.partial.offset) | |
2768 | { | |
2769 | if (st->nents >= view->params.partial.size) | |
2770 | break; | |
2771 | ||
2772 | sg_set_page(sg, NULL, PAGE_SIZE, 0); | |
2773 | sg_dma_address(sg) = sg_page_iter_dma_address(&obj_sg_iter); | |
2774 | sg_dma_len(sg) = PAGE_SIZE; | |
2775 | ||
2776 | sg = sg_next(sg); | |
2777 | st->nents++; | |
2778 | } | |
2779 | ||
2780 | return st; | |
2781 | ||
2782 | err_sg_alloc: | |
2783 | kfree(st); | |
2784 | err_st_alloc: | |
2785 | return ERR_PTR(ret); | |
2786 | } | |
2787 | ||
70b9f6f8 | 2788 | static int |
50470bb0 | 2789 | i915_get_ggtt_vma_pages(struct i915_vma *vma) |
fe14d5f4 | 2790 | { |
50470bb0 TU |
2791 | int ret = 0; |
2792 | ||
fe14d5f4 TU |
2793 | if (vma->ggtt_view.pages) |
2794 | return 0; | |
2795 | ||
2796 | if (vma->ggtt_view.type == I915_GGTT_VIEW_NORMAL) | |
2797 | vma->ggtt_view.pages = vma->obj->pages; | |
50470bb0 TU |
2798 | else if (vma->ggtt_view.type == I915_GGTT_VIEW_ROTATED) |
2799 | vma->ggtt_view.pages = | |
2800 | intel_rotate_fb_obj_pages(&vma->ggtt_view, vma->obj); | |
8bd7ef16 JL |
2801 | else if (vma->ggtt_view.type == I915_GGTT_VIEW_PARTIAL) |
2802 | vma->ggtt_view.pages = | |
2803 | intel_partial_pages(&vma->ggtt_view, vma->obj); | |
fe14d5f4 TU |
2804 | else |
2805 | WARN_ONCE(1, "GGTT view %u not implemented!\n", | |
2806 | vma->ggtt_view.type); | |
2807 | ||
2808 | if (!vma->ggtt_view.pages) { | |
ec7adb6e | 2809 | DRM_ERROR("Failed to get pages for GGTT view type %u!\n", |
fe14d5f4 | 2810 | vma->ggtt_view.type); |
50470bb0 TU |
2811 | ret = -EINVAL; |
2812 | } else if (IS_ERR(vma->ggtt_view.pages)) { | |
2813 | ret = PTR_ERR(vma->ggtt_view.pages); | |
2814 | vma->ggtt_view.pages = NULL; | |
2815 | DRM_ERROR("Failed to get pages for VMA view type %u (%d)!\n", | |
2816 | vma->ggtt_view.type, ret); | |
fe14d5f4 TU |
2817 | } |
2818 | ||
50470bb0 | 2819 | return ret; |
fe14d5f4 TU |
2820 | } |
2821 | ||
2822 | /** | |
2823 | * i915_vma_bind - Sets up PTEs for an VMA in it's corresponding address space. | |
2824 | * @vma: VMA to map | |
2825 | * @cache_level: mapping cache level | |
2826 | * @flags: flags like global or local mapping | |
2827 | * | |
2828 | * DMA addresses are taken from the scatter-gather table of this object (or of | |
2829 | * this VMA in case of non-default GGTT views) and PTE entries set up. | |
2830 | * Note that DMA addresses are also the only part of the SG table we care about. | |
2831 | */ | |
2832 | int i915_vma_bind(struct i915_vma *vma, enum i915_cache_level cache_level, | |
2833 | u32 flags) | |
2834 | { | |
75d04a37 MK |
2835 | int ret; |
2836 | u32 bind_flags; | |
1d335d1b | 2837 | |
75d04a37 MK |
2838 | if (WARN_ON(flags == 0)) |
2839 | return -EINVAL; | |
1d335d1b | 2840 | |
75d04a37 | 2841 | bind_flags = 0; |
0875546c DV |
2842 | if (flags & PIN_GLOBAL) |
2843 | bind_flags |= GLOBAL_BIND; | |
2844 | if (flags & PIN_USER) | |
2845 | bind_flags |= LOCAL_BIND; | |
2846 | ||
2847 | if (flags & PIN_UPDATE) | |
2848 | bind_flags |= vma->bound; | |
2849 | else | |
2850 | bind_flags &= ~vma->bound; | |
2851 | ||
75d04a37 MK |
2852 | if (bind_flags == 0) |
2853 | return 0; | |
2854 | ||
2855 | if (vma->bound == 0 && vma->vm->allocate_va_range) { | |
2856 | trace_i915_va_alloc(vma->vm, | |
2857 | vma->node.start, | |
2858 | vma->node.size, | |
2859 | VM_TO_TRACE_NAME(vma->vm)); | |
2860 | ||
b2dd4511 MK |
2861 | /* XXX: i915_vma_pin() will fix this +- hack */ |
2862 | vma->pin_count++; | |
75d04a37 MK |
2863 | ret = vma->vm->allocate_va_range(vma->vm, |
2864 | vma->node.start, | |
2865 | vma->node.size); | |
b2dd4511 | 2866 | vma->pin_count--; |
75d04a37 MK |
2867 | if (ret) |
2868 | return ret; | |
2869 | } | |
2870 | ||
2871 | ret = vma->vm->bind_vma(vma, cache_level, bind_flags); | |
70b9f6f8 DV |
2872 | if (ret) |
2873 | return ret; | |
0875546c DV |
2874 | |
2875 | vma->bound |= bind_flags; | |
fe14d5f4 TU |
2876 | |
2877 | return 0; | |
2878 | } | |
91e6711e JL |
2879 | |
2880 | /** | |
2881 | * i915_ggtt_view_size - Get the size of a GGTT view. | |
2882 | * @obj: Object the view is of. | |
2883 | * @view: The view in question. | |
2884 | * | |
2885 | * @return The size of the GGTT view in bytes. | |
2886 | */ | |
2887 | size_t | |
2888 | i915_ggtt_view_size(struct drm_i915_gem_object *obj, | |
2889 | const struct i915_ggtt_view *view) | |
2890 | { | |
9e759ff1 | 2891 | if (view->type == I915_GGTT_VIEW_NORMAL) { |
91e6711e | 2892 | return obj->base.size; |
9e759ff1 TU |
2893 | } else if (view->type == I915_GGTT_VIEW_ROTATED) { |
2894 | return view->rotation_info.size; | |
8bd7ef16 JL |
2895 | } else if (view->type == I915_GGTT_VIEW_PARTIAL) { |
2896 | return view->params.partial.size << PAGE_SHIFT; | |
91e6711e JL |
2897 | } else { |
2898 | WARN_ONCE(1, "GGTT view %u not implemented!\n", view->type); | |
2899 | return obj->base.size; | |
2900 | } | |
2901 | } |