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76aaf220 DV |
1 | /* |
2 | * Copyright © 2010 Daniel Vetter | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | */ | |
24 | ||
760285e7 DH |
25 | #include <drm/drmP.h> |
26 | #include <drm/i915_drm.h> | |
76aaf220 DV |
27 | #include "i915_drv.h" |
28 | #include "i915_trace.h" | |
29 | #include "intel_drv.h" | |
30 | ||
6670a5a5 BW |
31 | #define GEN6_PPGTT_PD_ENTRIES 512 |
32 | #define I915_PPGTT_PT_ENTRIES (PAGE_SIZE / sizeof(gen6_gtt_pte_t)) | |
d31eb10e | 33 | typedef uint64_t gen8_gtt_pte_t; |
37aca44a | 34 | typedef gen8_gtt_pte_t gen8_ppgtt_pde_t; |
6670a5a5 | 35 | |
26b1ff35 BW |
36 | /* PPGTT stuff */ |
37 | #define GEN6_GTT_ADDR_ENCODE(addr) ((addr) | (((addr) >> 28) & 0xff0)) | |
0d8ff15e | 38 | #define HSW_GTT_ADDR_ENCODE(addr) ((addr) | (((addr) >> 28) & 0x7f0)) |
26b1ff35 BW |
39 | |
40 | #define GEN6_PDE_VALID (1 << 0) | |
41 | /* gen6+ has bit 11-4 for physical addr bit 39-32 */ | |
42 | #define GEN6_PDE_ADDR_ENCODE(addr) GEN6_GTT_ADDR_ENCODE(addr) | |
43 | ||
44 | #define GEN6_PTE_VALID (1 << 0) | |
45 | #define GEN6_PTE_UNCACHED (1 << 1) | |
46 | #define HSW_PTE_UNCACHED (0) | |
47 | #define GEN6_PTE_CACHE_LLC (2 << 1) | |
350ec881 | 48 | #define GEN7_PTE_CACHE_L3_LLC (3 << 1) |
26b1ff35 | 49 | #define GEN6_PTE_ADDR_ENCODE(addr) GEN6_GTT_ADDR_ENCODE(addr) |
0d8ff15e BW |
50 | #define HSW_PTE_ADDR_ENCODE(addr) HSW_GTT_ADDR_ENCODE(addr) |
51 | ||
52 | /* Cacheability Control is a 4-bit value. The low three bits are stored in * | |
53 | * bits 3:1 of the PTE, while the fourth bit is stored in bit 11 of the PTE. | |
54 | */ | |
55 | #define HSW_CACHEABILITY_CONTROL(bits) ((((bits) & 0x7) << 1) | \ | |
56 | (((bits) & 0x8) << (11 - 3))) | |
87a6b688 | 57 | #define HSW_WB_LLC_AGE3 HSW_CACHEABILITY_CONTROL(0x2) |
0d8ff15e | 58 | #define HSW_WB_LLC_AGE0 HSW_CACHEABILITY_CONTROL(0x3) |
4d15c145 | 59 | #define HSW_WB_ELLC_LLC_AGE0 HSW_CACHEABILITY_CONTROL(0xb) |
651d794f | 60 | #define HSW_WT_ELLC_LLC_AGE0 HSW_CACHEABILITY_CONTROL(0x6) |
26b1ff35 | 61 | |
459108b8 | 62 | #define GEN8_PTES_PER_PAGE (PAGE_SIZE / sizeof(gen8_gtt_pte_t)) |
37aca44a BW |
63 | #define GEN8_PDES_PER_PAGE (PAGE_SIZE / sizeof(gen8_ppgtt_pde_t)) |
64 | #define GEN8_LEGACY_PDPS 4 | |
65 | ||
fbe5d36e BW |
66 | #define PPAT_UNCACHED_INDEX (_PAGE_PWT | _PAGE_PCD) |
67 | #define PPAT_CACHED_PDE_INDEX 0 /* WB LLC */ | |
68 | #define PPAT_CACHED_INDEX _PAGE_PAT /* WB LLCeLLC */ | |
69 | #define PPAT_DISPLAY_ELLC_INDEX _PAGE_PCD /* WT eLLC */ | |
70 | ||
6f65e29a BW |
71 | static void ppgtt_bind_vma(struct i915_vma *vma, |
72 | enum i915_cache_level cache_level, | |
73 | u32 flags); | |
74 | static void ppgtt_unbind_vma(struct i915_vma *vma); | |
75 | ||
94ec8f61 BW |
76 | static inline gen8_gtt_pte_t gen8_pte_encode(dma_addr_t addr, |
77 | enum i915_cache_level level, | |
78 | bool valid) | |
79 | { | |
80 | gen8_gtt_pte_t pte = valid ? _PAGE_PRESENT | _PAGE_RW : 0; | |
81 | pte |= addr; | |
fbe5d36e BW |
82 | if (level != I915_CACHE_NONE) |
83 | pte |= PPAT_CACHED_INDEX; | |
84 | else | |
85 | pte |= PPAT_UNCACHED_INDEX; | |
94ec8f61 BW |
86 | return pte; |
87 | } | |
88 | ||
b1fe6673 BW |
89 | static inline gen8_ppgtt_pde_t gen8_pde_encode(struct drm_device *dev, |
90 | dma_addr_t addr, | |
91 | enum i915_cache_level level) | |
92 | { | |
93 | gen8_ppgtt_pde_t pde = _PAGE_PRESENT | _PAGE_RW; | |
94 | pde |= addr; | |
95 | if (level != I915_CACHE_NONE) | |
96 | pde |= PPAT_CACHED_PDE_INDEX; | |
97 | else | |
98 | pde |= PPAT_UNCACHED_INDEX; | |
99 | return pde; | |
100 | } | |
101 | ||
350ec881 | 102 | static gen6_gtt_pte_t snb_pte_encode(dma_addr_t addr, |
b35b380e BW |
103 | enum i915_cache_level level, |
104 | bool valid) | |
54d12527 | 105 | { |
b35b380e | 106 | gen6_gtt_pte_t pte = valid ? GEN6_PTE_VALID : 0; |
54d12527 | 107 | pte |= GEN6_PTE_ADDR_ENCODE(addr); |
e7210c3c BW |
108 | |
109 | switch (level) { | |
350ec881 CW |
110 | case I915_CACHE_L3_LLC: |
111 | case I915_CACHE_LLC: | |
112 | pte |= GEN6_PTE_CACHE_LLC; | |
113 | break; | |
114 | case I915_CACHE_NONE: | |
115 | pte |= GEN6_PTE_UNCACHED; | |
116 | break; | |
117 | default: | |
118 | WARN_ON(1); | |
119 | } | |
120 | ||
121 | return pte; | |
122 | } | |
123 | ||
124 | static gen6_gtt_pte_t ivb_pte_encode(dma_addr_t addr, | |
b35b380e BW |
125 | enum i915_cache_level level, |
126 | bool valid) | |
350ec881 | 127 | { |
b35b380e | 128 | gen6_gtt_pte_t pte = valid ? GEN6_PTE_VALID : 0; |
350ec881 CW |
129 | pte |= GEN6_PTE_ADDR_ENCODE(addr); |
130 | ||
131 | switch (level) { | |
132 | case I915_CACHE_L3_LLC: | |
133 | pte |= GEN7_PTE_CACHE_L3_LLC; | |
e7210c3c BW |
134 | break; |
135 | case I915_CACHE_LLC: | |
136 | pte |= GEN6_PTE_CACHE_LLC; | |
137 | break; | |
138 | case I915_CACHE_NONE: | |
9119708c | 139 | pte |= GEN6_PTE_UNCACHED; |
e7210c3c BW |
140 | break; |
141 | default: | |
350ec881 | 142 | WARN_ON(1); |
e7210c3c BW |
143 | } |
144 | ||
54d12527 BW |
145 | return pte; |
146 | } | |
147 | ||
93c34e70 KG |
148 | #define BYT_PTE_WRITEABLE (1 << 1) |
149 | #define BYT_PTE_SNOOPED_BY_CPU_CACHES (1 << 2) | |
150 | ||
80a74f7f | 151 | static gen6_gtt_pte_t byt_pte_encode(dma_addr_t addr, |
b35b380e BW |
152 | enum i915_cache_level level, |
153 | bool valid) | |
93c34e70 | 154 | { |
b35b380e | 155 | gen6_gtt_pte_t pte = valid ? GEN6_PTE_VALID : 0; |
93c34e70 KG |
156 | pte |= GEN6_PTE_ADDR_ENCODE(addr); |
157 | ||
158 | /* Mark the page as writeable. Other platforms don't have a | |
159 | * setting for read-only/writable, so this matches that behavior. | |
160 | */ | |
161 | pte |= BYT_PTE_WRITEABLE; | |
162 | ||
163 | if (level != I915_CACHE_NONE) | |
164 | pte |= BYT_PTE_SNOOPED_BY_CPU_CACHES; | |
165 | ||
166 | return pte; | |
167 | } | |
168 | ||
80a74f7f | 169 | static gen6_gtt_pte_t hsw_pte_encode(dma_addr_t addr, |
b35b380e BW |
170 | enum i915_cache_level level, |
171 | bool valid) | |
9119708c | 172 | { |
b35b380e | 173 | gen6_gtt_pte_t pte = valid ? GEN6_PTE_VALID : 0; |
0d8ff15e | 174 | pte |= HSW_PTE_ADDR_ENCODE(addr); |
9119708c KG |
175 | |
176 | if (level != I915_CACHE_NONE) | |
87a6b688 | 177 | pte |= HSW_WB_LLC_AGE3; |
9119708c KG |
178 | |
179 | return pte; | |
180 | } | |
181 | ||
4d15c145 | 182 | static gen6_gtt_pte_t iris_pte_encode(dma_addr_t addr, |
b35b380e BW |
183 | enum i915_cache_level level, |
184 | bool valid) | |
4d15c145 | 185 | { |
b35b380e | 186 | gen6_gtt_pte_t pte = valid ? GEN6_PTE_VALID : 0; |
4d15c145 BW |
187 | pte |= HSW_PTE_ADDR_ENCODE(addr); |
188 | ||
651d794f CW |
189 | switch (level) { |
190 | case I915_CACHE_NONE: | |
191 | break; | |
192 | case I915_CACHE_WT: | |
193 | pte |= HSW_WT_ELLC_LLC_AGE0; | |
194 | break; | |
195 | default: | |
4d15c145 | 196 | pte |= HSW_WB_ELLC_LLC_AGE0; |
651d794f CW |
197 | break; |
198 | } | |
4d15c145 BW |
199 | |
200 | return pte; | |
201 | } | |
202 | ||
94e409c1 BW |
203 | /* Broadwell Page Directory Pointer Descriptors */ |
204 | static int gen8_write_pdp(struct intel_ring_buffer *ring, unsigned entry, | |
e178f705 | 205 | uint64_t val, bool synchronous) |
94e409c1 | 206 | { |
e178f705 | 207 | struct drm_i915_private *dev_priv = ring->dev->dev_private; |
94e409c1 BW |
208 | int ret; |
209 | ||
210 | BUG_ON(entry >= 4); | |
211 | ||
e178f705 BW |
212 | if (synchronous) { |
213 | I915_WRITE(GEN8_RING_PDP_UDW(ring, entry), val >> 32); | |
214 | I915_WRITE(GEN8_RING_PDP_LDW(ring, entry), (u32)val); | |
215 | return 0; | |
216 | } | |
217 | ||
94e409c1 BW |
218 | ret = intel_ring_begin(ring, 6); |
219 | if (ret) | |
220 | return ret; | |
221 | ||
222 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); | |
223 | intel_ring_emit(ring, GEN8_RING_PDP_UDW(ring, entry)); | |
224 | intel_ring_emit(ring, (u32)(val >> 32)); | |
225 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); | |
226 | intel_ring_emit(ring, GEN8_RING_PDP_LDW(ring, entry)); | |
227 | intel_ring_emit(ring, (u32)(val)); | |
228 | intel_ring_advance(ring); | |
229 | ||
230 | return 0; | |
231 | } | |
232 | ||
a3d67d23 | 233 | static int gen8_ppgtt_enable(struct i915_hw_ppgtt *ppgtt) |
94e409c1 | 234 | { |
a3d67d23 | 235 | struct drm_device *dev = ppgtt->base.dev; |
94e409c1 BW |
236 | struct drm_i915_private *dev_priv = dev->dev_private; |
237 | struct intel_ring_buffer *ring; | |
94e409c1 BW |
238 | int i, j, ret; |
239 | ||
240 | /* bit of a hack to find the actual last used pd */ | |
241 | int used_pd = ppgtt->num_pd_entries / GEN8_PDES_PER_PAGE; | |
242 | ||
243 | for_each_ring(ring, dev_priv, j) { | |
244 | I915_WRITE(RING_MODE_GEN7(ring), | |
245 | _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE)); | |
246 | } | |
247 | ||
248 | for (i = used_pd - 1; i >= 0; i--) { | |
249 | dma_addr_t addr = ppgtt->pd_dma_addr[i]; | |
250 | for_each_ring(ring, dev_priv, j) { | |
e178f705 BW |
251 | ret = gen8_write_pdp(ring, i, addr, |
252 | i915_reset_in_progress(&dev_priv->gpu_error)); | |
94e409c1 | 253 | if (ret) |
d595bd4b | 254 | goto err_out; |
94e409c1 BW |
255 | } |
256 | } | |
257 | return 0; | |
d595bd4b BW |
258 | |
259 | err_out: | |
260 | for_each_ring(ring, dev_priv, j) | |
261 | I915_WRITE(RING_MODE_GEN7(ring), | |
262 | _MASKED_BIT_DISABLE(GFX_PPGTT_ENABLE)); | |
263 | return ret; | |
94e409c1 BW |
264 | } |
265 | ||
459108b8 BW |
266 | static void gen8_ppgtt_clear_range(struct i915_address_space *vm, |
267 | unsigned first_entry, | |
268 | unsigned num_entries, | |
269 | bool use_scratch) | |
270 | { | |
271 | struct i915_hw_ppgtt *ppgtt = | |
272 | container_of(vm, struct i915_hw_ppgtt, base); | |
273 | gen8_gtt_pte_t *pt_vaddr, scratch_pte; | |
274 | unsigned act_pt = first_entry / GEN8_PTES_PER_PAGE; | |
275 | unsigned first_pte = first_entry % GEN8_PTES_PER_PAGE; | |
276 | unsigned last_pte, i; | |
277 | ||
278 | scratch_pte = gen8_pte_encode(ppgtt->base.scratch.addr, | |
279 | I915_CACHE_LLC, use_scratch); | |
280 | ||
281 | while (num_entries) { | |
282 | struct page *page_table = &ppgtt->gen8_pt_pages[act_pt]; | |
283 | ||
284 | last_pte = first_pte + num_entries; | |
285 | if (last_pte > GEN8_PTES_PER_PAGE) | |
286 | last_pte = GEN8_PTES_PER_PAGE; | |
287 | ||
288 | pt_vaddr = kmap_atomic(page_table); | |
289 | ||
290 | for (i = first_pte; i < last_pte; i++) | |
291 | pt_vaddr[i] = scratch_pte; | |
292 | ||
293 | kunmap_atomic(pt_vaddr); | |
294 | ||
295 | num_entries -= last_pte - first_pte; | |
296 | first_pte = 0; | |
297 | act_pt++; | |
298 | } | |
299 | } | |
300 | ||
9df15b49 BW |
301 | static void gen8_ppgtt_insert_entries(struct i915_address_space *vm, |
302 | struct sg_table *pages, | |
303 | unsigned first_entry, | |
304 | enum i915_cache_level cache_level) | |
305 | { | |
306 | struct i915_hw_ppgtt *ppgtt = | |
307 | container_of(vm, struct i915_hw_ppgtt, base); | |
308 | gen8_gtt_pte_t *pt_vaddr; | |
309 | unsigned act_pt = first_entry / GEN8_PTES_PER_PAGE; | |
310 | unsigned act_pte = first_entry % GEN8_PTES_PER_PAGE; | |
311 | struct sg_page_iter sg_iter; | |
312 | ||
313 | pt_vaddr = kmap_atomic(&ppgtt->gen8_pt_pages[act_pt]); | |
314 | for_each_sg_page(pages->sgl, &sg_iter, pages->nents, 0) { | |
315 | dma_addr_t page_addr; | |
316 | ||
317 | page_addr = sg_dma_address(sg_iter.sg) + | |
318 | (sg_iter.sg_pgoffset << PAGE_SHIFT); | |
319 | pt_vaddr[act_pte] = gen8_pte_encode(page_addr, cache_level, | |
320 | true); | |
321 | if (++act_pte == GEN8_PTES_PER_PAGE) { | |
322 | kunmap_atomic(pt_vaddr); | |
323 | act_pt++; | |
324 | pt_vaddr = kmap_atomic(&ppgtt->gen8_pt_pages[act_pt]); | |
325 | act_pte = 0; | |
326 | ||
327 | } | |
328 | } | |
329 | kunmap_atomic(pt_vaddr); | |
330 | } | |
331 | ||
37aca44a BW |
332 | static void gen8_ppgtt_cleanup(struct i915_address_space *vm) |
333 | { | |
334 | struct i915_hw_ppgtt *ppgtt = | |
335 | container_of(vm, struct i915_hw_ppgtt, base); | |
336 | int i, j; | |
337 | ||
686e1f6f BW |
338 | drm_mm_takedown(&vm->mm); |
339 | ||
37aca44a BW |
340 | for (i = 0; i < ppgtt->num_pd_pages ; i++) { |
341 | if (ppgtt->pd_dma_addr[i]) { | |
342 | pci_unmap_page(ppgtt->base.dev->pdev, | |
343 | ppgtt->pd_dma_addr[i], | |
344 | PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); | |
345 | ||
346 | for (j = 0; j < GEN8_PDES_PER_PAGE; j++) { | |
347 | dma_addr_t addr = ppgtt->gen8_pt_dma_addr[i][j]; | |
348 | if (addr) | |
349 | pci_unmap_page(ppgtt->base.dev->pdev, | |
350 | addr, | |
351 | PAGE_SIZE, | |
352 | PCI_DMA_BIDIRECTIONAL); | |
353 | ||
354 | } | |
355 | } | |
356 | kfree(ppgtt->gen8_pt_dma_addr[i]); | |
357 | } | |
358 | ||
230f955f BW |
359 | __free_pages(ppgtt->gen8_pt_pages, get_order(ppgtt->num_pt_pages << PAGE_SHIFT)); |
360 | __free_pages(ppgtt->pd_pages, get_order(ppgtt->num_pd_pages << PAGE_SHIFT)); | |
37aca44a BW |
361 | } |
362 | ||
363 | /** | |
364 | * GEN8 legacy ppgtt programming is accomplished through 4 PDP registers with a | |
365 | * net effect resembling a 2-level page table in normal x86 terms. Each PDP | |
366 | * represents 1GB of memory | |
367 | * 4 * 512 * 512 * 4096 = 4GB legacy 32b address space. | |
368 | * | |
369 | * TODO: Do something with the size parameter | |
370 | **/ | |
371 | static int gen8_ppgtt_init(struct i915_hw_ppgtt *ppgtt, uint64_t size) | |
372 | { | |
373 | struct page *pt_pages; | |
374 | int i, j, ret = -ENOMEM; | |
375 | const int max_pdp = DIV_ROUND_UP(size, 1 << 30); | |
376 | const int num_pt_pages = GEN8_PDES_PER_PAGE * max_pdp; | |
377 | ||
378 | if (size % (1<<30)) | |
379 | DRM_INFO("Pages will be wasted unless GTT size (%llu) is divisible by 1GB\n", size); | |
380 | ||
381 | /* FIXME: split allocation into smaller pieces. For now we only ever do | |
382 | * this once, but with full PPGTT, the multiple contiguous allocations | |
383 | * will be bad. | |
384 | */ | |
385 | ppgtt->pd_pages = alloc_pages(GFP_KERNEL, get_order(max_pdp << PAGE_SHIFT)); | |
386 | if (!ppgtt->pd_pages) | |
387 | return -ENOMEM; | |
388 | ||
389 | pt_pages = alloc_pages(GFP_KERNEL, get_order(num_pt_pages << PAGE_SHIFT)); | |
390 | if (!pt_pages) { | |
391 | __free_pages(ppgtt->pd_pages, get_order(max_pdp << PAGE_SHIFT)); | |
392 | return -ENOMEM; | |
393 | } | |
394 | ||
395 | ppgtt->gen8_pt_pages = pt_pages; | |
396 | ppgtt->num_pd_pages = 1 << get_order(max_pdp << PAGE_SHIFT); | |
397 | ppgtt->num_pt_pages = 1 << get_order(num_pt_pages << PAGE_SHIFT); | |
398 | ppgtt->num_pd_entries = max_pdp * GEN8_PDES_PER_PAGE; | |
94e409c1 | 399 | ppgtt->enable = gen8_ppgtt_enable; |
459108b8 | 400 | ppgtt->base.clear_range = gen8_ppgtt_clear_range; |
9df15b49 | 401 | ppgtt->base.insert_entries = gen8_ppgtt_insert_entries; |
37aca44a | 402 | ppgtt->base.cleanup = gen8_ppgtt_cleanup; |
686e1f6f BW |
403 | ppgtt->base.start = 0; |
404 | ppgtt->base.total = ppgtt->num_pt_pages * GEN8_PTES_PER_PAGE * PAGE_SIZE; | |
37aca44a BW |
405 | |
406 | BUG_ON(ppgtt->num_pd_pages > GEN8_LEGACY_PDPS); | |
407 | ||
408 | /* | |
409 | * - Create a mapping for the page directories. | |
410 | * - For each page directory: | |
411 | * allocate space for page table mappings. | |
412 | * map each page table | |
413 | */ | |
414 | for (i = 0; i < max_pdp; i++) { | |
415 | dma_addr_t temp; | |
416 | temp = pci_map_page(ppgtt->base.dev->pdev, | |
417 | &ppgtt->pd_pages[i], 0, | |
418 | PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); | |
419 | if (pci_dma_mapping_error(ppgtt->base.dev->pdev, temp)) | |
420 | goto err_out; | |
421 | ||
422 | ppgtt->pd_dma_addr[i] = temp; | |
423 | ||
424 | ppgtt->gen8_pt_dma_addr[i] = kmalloc(sizeof(dma_addr_t) * GEN8_PDES_PER_PAGE, GFP_KERNEL); | |
425 | if (!ppgtt->gen8_pt_dma_addr[i]) | |
426 | goto err_out; | |
427 | ||
428 | for (j = 0; j < GEN8_PDES_PER_PAGE; j++) { | |
429 | struct page *p = &pt_pages[i * GEN8_PDES_PER_PAGE + j]; | |
430 | temp = pci_map_page(ppgtt->base.dev->pdev, | |
431 | p, 0, PAGE_SIZE, | |
432 | PCI_DMA_BIDIRECTIONAL); | |
433 | ||
434 | if (pci_dma_mapping_error(ppgtt->base.dev->pdev, temp)) | |
435 | goto err_out; | |
436 | ||
437 | ppgtt->gen8_pt_dma_addr[i][j] = temp; | |
438 | } | |
439 | } | |
440 | ||
b1fe6673 BW |
441 | /* For now, the PPGTT helper functions all require that the PDEs are |
442 | * plugged in correctly. So we do that now/here. For aliasing PPGTT, we | |
443 | * will never need to touch the PDEs again */ | |
444 | for (i = 0; i < max_pdp; i++) { | |
445 | gen8_ppgtt_pde_t *pd_vaddr; | |
446 | pd_vaddr = kmap_atomic(&ppgtt->pd_pages[i]); | |
447 | for (j = 0; j < GEN8_PDES_PER_PAGE; j++) { | |
448 | dma_addr_t addr = ppgtt->gen8_pt_dma_addr[i][j]; | |
449 | pd_vaddr[j] = gen8_pde_encode(ppgtt->base.dev, addr, | |
450 | I915_CACHE_LLC); | |
451 | } | |
452 | kunmap_atomic(pd_vaddr); | |
453 | } | |
454 | ||
459108b8 BW |
455 | ppgtt->base.clear_range(&ppgtt->base, 0, |
456 | ppgtt->num_pd_entries * GEN8_PTES_PER_PAGE, | |
457 | true); | |
458 | ||
37aca44a BW |
459 | DRM_DEBUG_DRIVER("Allocated %d pages for page directories (%d wasted)\n", |
460 | ppgtt->num_pd_pages, ppgtt->num_pd_pages - max_pdp); | |
461 | DRM_DEBUG_DRIVER("Allocated %d pages for page tables (%lld wasted)\n", | |
462 | ppgtt->num_pt_pages, | |
463 | (ppgtt->num_pt_pages - num_pt_pages) + | |
464 | size % (1<<30)); | |
28cf5415 | 465 | return 0; |
37aca44a BW |
466 | |
467 | err_out: | |
468 | ppgtt->base.cleanup(&ppgtt->base); | |
469 | return ret; | |
470 | } | |
471 | ||
3e302542 | 472 | static void gen6_write_pdes(struct i915_hw_ppgtt *ppgtt) |
6197349b | 473 | { |
853ba5d2 | 474 | struct drm_i915_private *dev_priv = ppgtt->base.dev->dev_private; |
6197349b BW |
475 | gen6_gtt_pte_t __iomem *pd_addr; |
476 | uint32_t pd_entry; | |
477 | int i; | |
478 | ||
0a732870 | 479 | WARN_ON(ppgtt->pd_offset & 0x3f); |
6197349b BW |
480 | pd_addr = (gen6_gtt_pte_t __iomem*)dev_priv->gtt.gsm + |
481 | ppgtt->pd_offset / sizeof(gen6_gtt_pte_t); | |
482 | for (i = 0; i < ppgtt->num_pd_entries; i++) { | |
483 | dma_addr_t pt_addr; | |
484 | ||
485 | pt_addr = ppgtt->pt_dma_addr[i]; | |
486 | pd_entry = GEN6_PDE_ADDR_ENCODE(pt_addr); | |
487 | pd_entry |= GEN6_PDE_VALID; | |
488 | ||
489 | writel(pd_entry, pd_addr + i); | |
490 | } | |
491 | readl(pd_addr); | |
3e302542 BW |
492 | } |
493 | ||
a3d67d23 | 494 | static int gen6_ppgtt_enable(struct i915_hw_ppgtt *ppgtt) |
3e302542 | 495 | { |
a3d67d23 | 496 | struct drm_device *dev = ppgtt->base.dev; |
3e302542 BW |
497 | drm_i915_private_t *dev_priv = dev->dev_private; |
498 | uint32_t pd_offset; | |
499 | struct intel_ring_buffer *ring; | |
3e302542 BW |
500 | int i; |
501 | ||
502 | BUG_ON(ppgtt->pd_offset & 0x3f); | |
503 | ||
504 | gen6_write_pdes(ppgtt); | |
6197349b BW |
505 | |
506 | pd_offset = ppgtt->pd_offset; | |
507 | pd_offset /= 64; /* in cachelines, */ | |
508 | pd_offset <<= 16; | |
509 | ||
510 | if (INTEL_INFO(dev)->gen == 6) { | |
511 | uint32_t ecochk, gab_ctl, ecobits; | |
512 | ||
513 | ecobits = I915_READ(GAC_ECO_BITS); | |
3b9d7888 VS |
514 | I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_SNB_BIT | |
515 | ECOBITS_PPGTT_CACHE64B); | |
6197349b BW |
516 | |
517 | gab_ctl = I915_READ(GAB_CTL); | |
518 | I915_WRITE(GAB_CTL, gab_ctl | GAB_CTL_CONT_AFTER_PAGEFAULT); | |
519 | ||
520 | ecochk = I915_READ(GAM_ECOCHK); | |
521 | I915_WRITE(GAM_ECOCHK, ecochk | ECOCHK_SNB_BIT | | |
522 | ECOCHK_PPGTT_CACHE64B); | |
523 | I915_WRITE(GFX_MODE, _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE)); | |
524 | } else if (INTEL_INFO(dev)->gen >= 7) { | |
a6f429a5 | 525 | uint32_t ecochk, ecobits; |
a65c2fcd VS |
526 | |
527 | ecobits = I915_READ(GAC_ECO_BITS); | |
528 | I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_PPGTT_CACHE64B); | |
529 | ||
a6f429a5 VS |
530 | ecochk = I915_READ(GAM_ECOCHK); |
531 | if (IS_HASWELL(dev)) { | |
532 | ecochk |= ECOCHK_PPGTT_WB_HSW; | |
533 | } else { | |
534 | ecochk |= ECOCHK_PPGTT_LLC_IVB; | |
535 | ecochk &= ~ECOCHK_PPGTT_GFDT_IVB; | |
536 | } | |
537 | I915_WRITE(GAM_ECOCHK, ecochk); | |
6197349b BW |
538 | /* GFX_MODE is per-ring on gen7+ */ |
539 | } | |
540 | ||
541 | for_each_ring(ring, dev_priv, i) { | |
542 | if (INTEL_INFO(dev)->gen >= 7) | |
543 | I915_WRITE(RING_MODE_GEN7(ring), | |
544 | _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE)); | |
545 | ||
546 | I915_WRITE(RING_PP_DIR_DCLV(ring), PP_DIR_DCLV_2G); | |
547 | I915_WRITE(RING_PP_DIR_BASE(ring), pd_offset); | |
548 | } | |
b7c36d25 | 549 | return 0; |
6197349b BW |
550 | } |
551 | ||
1d2a314c | 552 | /* PPGTT support for Sandybdrige/Gen6 and later */ |
853ba5d2 | 553 | static void gen6_ppgtt_clear_range(struct i915_address_space *vm, |
1d2a314c | 554 | unsigned first_entry, |
828c7908 BW |
555 | unsigned num_entries, |
556 | bool use_scratch) | |
1d2a314c | 557 | { |
853ba5d2 BW |
558 | struct i915_hw_ppgtt *ppgtt = |
559 | container_of(vm, struct i915_hw_ppgtt, base); | |
e7c2b58b | 560 | gen6_gtt_pte_t *pt_vaddr, scratch_pte; |
a15326a5 | 561 | unsigned act_pt = first_entry / I915_PPGTT_PT_ENTRIES; |
7bddb01f DV |
562 | unsigned first_pte = first_entry % I915_PPGTT_PT_ENTRIES; |
563 | unsigned last_pte, i; | |
1d2a314c | 564 | |
b35b380e | 565 | scratch_pte = vm->pte_encode(vm->scratch.addr, I915_CACHE_LLC, true); |
1d2a314c | 566 | |
7bddb01f DV |
567 | while (num_entries) { |
568 | last_pte = first_pte + num_entries; | |
569 | if (last_pte > I915_PPGTT_PT_ENTRIES) | |
570 | last_pte = I915_PPGTT_PT_ENTRIES; | |
571 | ||
a15326a5 | 572 | pt_vaddr = kmap_atomic(ppgtt->pt_pages[act_pt]); |
1d2a314c | 573 | |
7bddb01f DV |
574 | for (i = first_pte; i < last_pte; i++) |
575 | pt_vaddr[i] = scratch_pte; | |
1d2a314c DV |
576 | |
577 | kunmap_atomic(pt_vaddr); | |
1d2a314c | 578 | |
7bddb01f DV |
579 | num_entries -= last_pte - first_pte; |
580 | first_pte = 0; | |
a15326a5 | 581 | act_pt++; |
7bddb01f | 582 | } |
1d2a314c DV |
583 | } |
584 | ||
853ba5d2 | 585 | static void gen6_ppgtt_insert_entries(struct i915_address_space *vm, |
def886c3 DV |
586 | struct sg_table *pages, |
587 | unsigned first_entry, | |
588 | enum i915_cache_level cache_level) | |
589 | { | |
853ba5d2 BW |
590 | struct i915_hw_ppgtt *ppgtt = |
591 | container_of(vm, struct i915_hw_ppgtt, base); | |
e7c2b58b | 592 | gen6_gtt_pte_t *pt_vaddr; |
a15326a5 | 593 | unsigned act_pt = first_entry / I915_PPGTT_PT_ENTRIES; |
6e995e23 ID |
594 | unsigned act_pte = first_entry % I915_PPGTT_PT_ENTRIES; |
595 | struct sg_page_iter sg_iter; | |
596 | ||
a15326a5 | 597 | pt_vaddr = kmap_atomic(ppgtt->pt_pages[act_pt]); |
6e995e23 ID |
598 | for_each_sg_page(pages->sgl, &sg_iter, pages->nents, 0) { |
599 | dma_addr_t page_addr; | |
600 | ||
2db76d7c | 601 | page_addr = sg_page_iter_dma_address(&sg_iter); |
b35b380e | 602 | pt_vaddr[act_pte] = vm->pte_encode(page_addr, cache_level, true); |
6e995e23 ID |
603 | if (++act_pte == I915_PPGTT_PT_ENTRIES) { |
604 | kunmap_atomic(pt_vaddr); | |
a15326a5 DV |
605 | act_pt++; |
606 | pt_vaddr = kmap_atomic(ppgtt->pt_pages[act_pt]); | |
6e995e23 | 607 | act_pte = 0; |
def886c3 | 608 | |
def886c3 | 609 | } |
def886c3 | 610 | } |
6e995e23 | 611 | kunmap_atomic(pt_vaddr); |
def886c3 DV |
612 | } |
613 | ||
853ba5d2 | 614 | static void gen6_ppgtt_cleanup(struct i915_address_space *vm) |
1d2a314c | 615 | { |
853ba5d2 BW |
616 | struct i915_hw_ppgtt *ppgtt = |
617 | container_of(vm, struct i915_hw_ppgtt, base); | |
3440d265 DV |
618 | int i; |
619 | ||
93bd8649 BW |
620 | drm_mm_takedown(&ppgtt->base.mm); |
621 | ||
3440d265 DV |
622 | if (ppgtt->pt_dma_addr) { |
623 | for (i = 0; i < ppgtt->num_pd_entries; i++) | |
853ba5d2 | 624 | pci_unmap_page(ppgtt->base.dev->pdev, |
3440d265 DV |
625 | ppgtt->pt_dma_addr[i], |
626 | 4096, PCI_DMA_BIDIRECTIONAL); | |
627 | } | |
628 | ||
629 | kfree(ppgtt->pt_dma_addr); | |
630 | for (i = 0; i < ppgtt->num_pd_entries; i++) | |
631 | __free_page(ppgtt->pt_pages[i]); | |
632 | kfree(ppgtt->pt_pages); | |
633 | kfree(ppgtt); | |
634 | } | |
635 | ||
636 | static int gen6_ppgtt_init(struct i915_hw_ppgtt *ppgtt) | |
637 | { | |
853ba5d2 | 638 | struct drm_device *dev = ppgtt->base.dev; |
1d2a314c | 639 | struct drm_i915_private *dev_priv = dev->dev_private; |
1d2a314c | 640 | unsigned first_pd_entry_in_global_pt; |
1d2a314c DV |
641 | int i; |
642 | int ret = -ENOMEM; | |
643 | ||
644 | /* ppgtt PDEs reside in the global gtt pagetable, which has 512*1024 | |
645 | * entries. For aliasing ppgtt support we just steal them at the end for | |
646 | * now. */ | |
e1b73cba | 647 | first_pd_entry_in_global_pt = gtt_total_entries(dev_priv->gtt); |
1d2a314c | 648 | |
08c45263 | 649 | ppgtt->base.pte_encode = dev_priv->gtt.base.pte_encode; |
6670a5a5 | 650 | ppgtt->num_pd_entries = GEN6_PPGTT_PD_ENTRIES; |
6197349b | 651 | ppgtt->enable = gen6_ppgtt_enable; |
853ba5d2 BW |
652 | ppgtt->base.clear_range = gen6_ppgtt_clear_range; |
653 | ppgtt->base.insert_entries = gen6_ppgtt_insert_entries; | |
654 | ppgtt->base.cleanup = gen6_ppgtt_cleanup; | |
655 | ppgtt->base.scratch = dev_priv->gtt.base.scratch; | |
686e1f6f BW |
656 | ppgtt->base.start = 0; |
657 | ppgtt->base.total = GEN6_PPGTT_PD_ENTRIES * I915_PPGTT_PT_ENTRIES * PAGE_SIZE; | |
a1e22653 | 658 | ppgtt->pt_pages = kcalloc(ppgtt->num_pd_entries, sizeof(struct page *), |
1d2a314c DV |
659 | GFP_KERNEL); |
660 | if (!ppgtt->pt_pages) | |
3440d265 | 661 | return -ENOMEM; |
1d2a314c DV |
662 | |
663 | for (i = 0; i < ppgtt->num_pd_entries; i++) { | |
664 | ppgtt->pt_pages[i] = alloc_page(GFP_KERNEL); | |
665 | if (!ppgtt->pt_pages[i]) | |
666 | goto err_pt_alloc; | |
667 | } | |
668 | ||
a1e22653 | 669 | ppgtt->pt_dma_addr = kcalloc(ppgtt->num_pd_entries, sizeof(dma_addr_t), |
8d2e6308 BW |
670 | GFP_KERNEL); |
671 | if (!ppgtt->pt_dma_addr) | |
672 | goto err_pt_alloc; | |
1d2a314c | 673 | |
8d2e6308 BW |
674 | for (i = 0; i < ppgtt->num_pd_entries; i++) { |
675 | dma_addr_t pt_addr; | |
211c568b | 676 | |
8d2e6308 BW |
677 | pt_addr = pci_map_page(dev->pdev, ppgtt->pt_pages[i], 0, 4096, |
678 | PCI_DMA_BIDIRECTIONAL); | |
1d2a314c | 679 | |
8d2e6308 BW |
680 | if (pci_dma_mapping_error(dev->pdev, pt_addr)) { |
681 | ret = -EIO; | |
682 | goto err_pd_pin; | |
1d2a314c | 683 | |
211c568b | 684 | } |
8d2e6308 | 685 | ppgtt->pt_dma_addr[i] = pt_addr; |
1d2a314c | 686 | } |
1d2a314c | 687 | |
853ba5d2 | 688 | ppgtt->base.clear_range(&ppgtt->base, 0, |
828c7908 | 689 | ppgtt->num_pd_entries * I915_PPGTT_PT_ENTRIES, true); |
1d2a314c | 690 | |
e7c2b58b | 691 | ppgtt->pd_offset = first_pd_entry_in_global_pt * sizeof(gen6_gtt_pte_t); |
1d2a314c | 692 | |
1d2a314c DV |
693 | return 0; |
694 | ||
695 | err_pd_pin: | |
696 | if (ppgtt->pt_dma_addr) { | |
697 | for (i--; i >= 0; i--) | |
698 | pci_unmap_page(dev->pdev, ppgtt->pt_dma_addr[i], | |
699 | 4096, PCI_DMA_BIDIRECTIONAL); | |
700 | } | |
701 | err_pt_alloc: | |
702 | kfree(ppgtt->pt_dma_addr); | |
703 | for (i = 0; i < ppgtt->num_pd_entries; i++) { | |
704 | if (ppgtt->pt_pages[i]) | |
705 | __free_page(ppgtt->pt_pages[i]); | |
706 | } | |
707 | kfree(ppgtt->pt_pages); | |
3440d265 DV |
708 | |
709 | return ret; | |
710 | } | |
711 | ||
712 | static int i915_gem_init_aliasing_ppgtt(struct drm_device *dev) | |
713 | { | |
714 | struct drm_i915_private *dev_priv = dev->dev_private; | |
715 | struct i915_hw_ppgtt *ppgtt; | |
716 | int ret; | |
717 | ||
718 | ppgtt = kzalloc(sizeof(*ppgtt), GFP_KERNEL); | |
719 | if (!ppgtt) | |
720 | return -ENOMEM; | |
721 | ||
853ba5d2 | 722 | ppgtt->base.dev = dev; |
3440d265 | 723 | |
3ed124b2 BW |
724 | if (INTEL_INFO(dev)->gen < 8) |
725 | ret = gen6_ppgtt_init(ppgtt); | |
8fe6bd23 | 726 | else if (IS_GEN8(dev)) |
37aca44a | 727 | ret = gen8_ppgtt_init(ppgtt, dev_priv->gtt.base.total); |
3ed124b2 BW |
728 | else |
729 | BUG(); | |
730 | ||
3440d265 DV |
731 | if (ret) |
732 | kfree(ppgtt); | |
93bd8649 | 733 | else { |
3440d265 | 734 | dev_priv->mm.aliasing_ppgtt = ppgtt; |
93bd8649 BW |
735 | drm_mm_init(&ppgtt->base.mm, ppgtt->base.start, |
736 | ppgtt->base.total); | |
737 | } | |
1d2a314c DV |
738 | |
739 | return ret; | |
740 | } | |
741 | ||
742 | void i915_gem_cleanup_aliasing_ppgtt(struct drm_device *dev) | |
743 | { | |
744 | struct drm_i915_private *dev_priv = dev->dev_private; | |
745 | struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt; | |
1d2a314c DV |
746 | |
747 | if (!ppgtt) | |
748 | return; | |
749 | ||
853ba5d2 | 750 | ppgtt->base.cleanup(&ppgtt->base); |
5963cf04 | 751 | dev_priv->mm.aliasing_ppgtt = NULL; |
1d2a314c DV |
752 | } |
753 | ||
6f65e29a BW |
754 | static void __always_unused |
755 | ppgtt_bind_vma(struct i915_vma *vma, | |
756 | enum i915_cache_level cache_level, | |
757 | u32 flags) | |
7bddb01f | 758 | { |
6f65e29a BW |
759 | const unsigned long entry = vma->node.start >> PAGE_SHIFT; |
760 | ||
761 | WARN_ON(flags); | |
762 | ||
763 | vma->vm->insert_entries(vma->vm, vma->obj->pages, entry, cache_level); | |
7bddb01f DV |
764 | } |
765 | ||
6f65e29a | 766 | static void __always_unused ppgtt_unbind_vma(struct i915_vma *vma) |
7bddb01f | 767 | { |
6f65e29a BW |
768 | const unsigned long entry = vma->node.start >> PAGE_SHIFT; |
769 | ||
770 | vma->vm->clear_range(vma->vm, | |
771 | entry, | |
772 | vma->obj->base.size >> PAGE_SHIFT, | |
773 | true); | |
7bddb01f DV |
774 | } |
775 | ||
a81cc00c BW |
776 | extern int intel_iommu_gfx_mapped; |
777 | /* Certain Gen5 chipsets require require idling the GPU before | |
778 | * unmapping anything from the GTT when VT-d is enabled. | |
779 | */ | |
780 | static inline bool needs_idle_maps(struct drm_device *dev) | |
781 | { | |
782 | #ifdef CONFIG_INTEL_IOMMU | |
783 | /* Query intel_iommu to see if we need the workaround. Presumably that | |
784 | * was loaded first. | |
785 | */ | |
786 | if (IS_GEN5(dev) && IS_MOBILE(dev) && intel_iommu_gfx_mapped) | |
787 | return true; | |
788 | #endif | |
789 | return false; | |
790 | } | |
791 | ||
5c042287 BW |
792 | static bool do_idling(struct drm_i915_private *dev_priv) |
793 | { | |
794 | bool ret = dev_priv->mm.interruptible; | |
795 | ||
a81cc00c | 796 | if (unlikely(dev_priv->gtt.do_idle_maps)) { |
5c042287 | 797 | dev_priv->mm.interruptible = false; |
b2da9fe5 | 798 | if (i915_gpu_idle(dev_priv->dev)) { |
5c042287 BW |
799 | DRM_ERROR("Couldn't idle GPU\n"); |
800 | /* Wait a bit, in hopes it avoids the hang */ | |
801 | udelay(10); | |
802 | } | |
803 | } | |
804 | ||
805 | return ret; | |
806 | } | |
807 | ||
808 | static void undo_idling(struct drm_i915_private *dev_priv, bool interruptible) | |
809 | { | |
a81cc00c | 810 | if (unlikely(dev_priv->gtt.do_idle_maps)) |
5c042287 BW |
811 | dev_priv->mm.interruptible = interruptible; |
812 | } | |
813 | ||
828c7908 BW |
814 | void i915_check_and_clear_faults(struct drm_device *dev) |
815 | { | |
816 | struct drm_i915_private *dev_priv = dev->dev_private; | |
817 | struct intel_ring_buffer *ring; | |
818 | int i; | |
819 | ||
820 | if (INTEL_INFO(dev)->gen < 6) | |
821 | return; | |
822 | ||
823 | for_each_ring(ring, dev_priv, i) { | |
824 | u32 fault_reg; | |
825 | fault_reg = I915_READ(RING_FAULT_REG(ring)); | |
826 | if (fault_reg & RING_FAULT_VALID) { | |
827 | DRM_DEBUG_DRIVER("Unexpected fault\n" | |
828 | "\tAddr: 0x%08lx\\n" | |
829 | "\tAddress space: %s\n" | |
830 | "\tSource ID: %d\n" | |
831 | "\tType: %d\n", | |
832 | fault_reg & PAGE_MASK, | |
833 | fault_reg & RING_FAULT_GTTSEL_MASK ? "GGTT" : "PPGTT", | |
834 | RING_FAULT_SRCID(fault_reg), | |
835 | RING_FAULT_FAULT_TYPE(fault_reg)); | |
836 | I915_WRITE(RING_FAULT_REG(ring), | |
837 | fault_reg & ~RING_FAULT_VALID); | |
838 | } | |
839 | } | |
840 | POSTING_READ(RING_FAULT_REG(&dev_priv->ring[RCS])); | |
841 | } | |
842 | ||
843 | void i915_gem_suspend_gtt_mappings(struct drm_device *dev) | |
844 | { | |
845 | struct drm_i915_private *dev_priv = dev->dev_private; | |
846 | ||
847 | /* Don't bother messing with faults pre GEN6 as we have little | |
848 | * documentation supporting that it's a good idea. | |
849 | */ | |
850 | if (INTEL_INFO(dev)->gen < 6) | |
851 | return; | |
852 | ||
853 | i915_check_and_clear_faults(dev); | |
854 | ||
855 | dev_priv->gtt.base.clear_range(&dev_priv->gtt.base, | |
856 | dev_priv->gtt.base.start / PAGE_SIZE, | |
857 | dev_priv->gtt.base.total / PAGE_SIZE, | |
858 | false); | |
859 | } | |
860 | ||
76aaf220 DV |
861 | void i915_gem_restore_gtt_mappings(struct drm_device *dev) |
862 | { | |
863 | struct drm_i915_private *dev_priv = dev->dev_private; | |
05394f39 | 864 | struct drm_i915_gem_object *obj; |
76aaf220 | 865 | |
828c7908 BW |
866 | i915_check_and_clear_faults(dev); |
867 | ||
bee4a186 | 868 | /* First fill our portion of the GTT with scratch pages */ |
853ba5d2 BW |
869 | dev_priv->gtt.base.clear_range(&dev_priv->gtt.base, |
870 | dev_priv->gtt.base.start / PAGE_SIZE, | |
828c7908 BW |
871 | dev_priv->gtt.base.total / PAGE_SIZE, |
872 | true); | |
bee4a186 | 873 | |
35c20a60 | 874 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) { |
6f65e29a BW |
875 | struct i915_vma *vma = i915_gem_obj_to_vma(obj, |
876 | &dev_priv->gtt.base); | |
877 | if (!vma) | |
878 | continue; | |
879 | ||
2c22569b | 880 | i915_gem_clflush_object(obj, obj->pin_display); |
6f65e29a BW |
881 | /* The bind_vma code tries to be smart about tracking mappings. |
882 | * Unfortunately above, we've just wiped out the mappings | |
883 | * without telling our object about it. So we need to fake it. | |
884 | */ | |
885 | obj->has_global_gtt_mapping = 0; | |
886 | vma->bind_vma(vma, obj->cache_level, GLOBAL_BIND); | |
76aaf220 DV |
887 | } |
888 | ||
e76e9aeb | 889 | i915_gem_chipset_flush(dev); |
76aaf220 | 890 | } |
7c2e6fdf | 891 | |
74163907 | 892 | int i915_gem_gtt_prepare_object(struct drm_i915_gem_object *obj) |
7c2e6fdf | 893 | { |
9da3da66 | 894 | if (obj->has_dma_mapping) |
74163907 | 895 | return 0; |
9da3da66 CW |
896 | |
897 | if (!dma_map_sg(&obj->base.dev->pdev->dev, | |
898 | obj->pages->sgl, obj->pages->nents, | |
899 | PCI_DMA_BIDIRECTIONAL)) | |
900 | return -ENOSPC; | |
901 | ||
902 | return 0; | |
7c2e6fdf DV |
903 | } |
904 | ||
94ec8f61 BW |
905 | static inline void gen8_set_pte(void __iomem *addr, gen8_gtt_pte_t pte) |
906 | { | |
907 | #ifdef writeq | |
908 | writeq(pte, addr); | |
909 | #else | |
910 | iowrite32((u32)pte, addr); | |
911 | iowrite32(pte >> 32, addr + 4); | |
912 | #endif | |
913 | } | |
914 | ||
915 | static void gen8_ggtt_insert_entries(struct i915_address_space *vm, | |
916 | struct sg_table *st, | |
917 | unsigned int first_entry, | |
918 | enum i915_cache_level level) | |
919 | { | |
920 | struct drm_i915_private *dev_priv = vm->dev->dev_private; | |
921 | gen8_gtt_pte_t __iomem *gtt_entries = | |
922 | (gen8_gtt_pte_t __iomem *)dev_priv->gtt.gsm + first_entry; | |
923 | int i = 0; | |
924 | struct sg_page_iter sg_iter; | |
925 | dma_addr_t addr; | |
926 | ||
927 | for_each_sg_page(st->sgl, &sg_iter, st->nents, 0) { | |
928 | addr = sg_dma_address(sg_iter.sg) + | |
929 | (sg_iter.sg_pgoffset << PAGE_SHIFT); | |
930 | gen8_set_pte(>t_entries[i], | |
931 | gen8_pte_encode(addr, level, true)); | |
932 | i++; | |
933 | } | |
934 | ||
935 | /* | |
936 | * XXX: This serves as a posting read to make sure that the PTE has | |
937 | * actually been updated. There is some concern that even though | |
938 | * registers and PTEs are within the same BAR that they are potentially | |
939 | * of NUMA access patterns. Therefore, even with the way we assume | |
940 | * hardware should work, we must keep this posting read for paranoia. | |
941 | */ | |
942 | if (i != 0) | |
943 | WARN_ON(readq(>t_entries[i-1]) | |
944 | != gen8_pte_encode(addr, level, true)); | |
945 | ||
946 | #if 0 /* TODO: Still needed on GEN8? */ | |
947 | /* This next bit makes the above posting read even more important. We | |
948 | * want to flush the TLBs only after we're certain all the PTE updates | |
949 | * have finished. | |
950 | */ | |
951 | I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN); | |
952 | POSTING_READ(GFX_FLSH_CNTL_GEN6); | |
953 | #endif | |
954 | } | |
955 | ||
e76e9aeb BW |
956 | /* |
957 | * Binds an object into the global gtt with the specified cache level. The object | |
958 | * will be accessible to the GPU via commands whose operands reference offsets | |
959 | * within the global GTT as well as accessible by the GPU through the GMADR | |
960 | * mapped BAR (dev_priv->mm.gtt->gtt). | |
961 | */ | |
853ba5d2 | 962 | static void gen6_ggtt_insert_entries(struct i915_address_space *vm, |
7faf1ab2 DV |
963 | struct sg_table *st, |
964 | unsigned int first_entry, | |
965 | enum i915_cache_level level) | |
e76e9aeb | 966 | { |
853ba5d2 | 967 | struct drm_i915_private *dev_priv = vm->dev->dev_private; |
e7c2b58b BW |
968 | gen6_gtt_pte_t __iomem *gtt_entries = |
969 | (gen6_gtt_pte_t __iomem *)dev_priv->gtt.gsm + first_entry; | |
6e995e23 ID |
970 | int i = 0; |
971 | struct sg_page_iter sg_iter; | |
e76e9aeb BW |
972 | dma_addr_t addr; |
973 | ||
6e995e23 | 974 | for_each_sg_page(st->sgl, &sg_iter, st->nents, 0) { |
2db76d7c | 975 | addr = sg_page_iter_dma_address(&sg_iter); |
b35b380e | 976 | iowrite32(vm->pte_encode(addr, level, true), >t_entries[i]); |
6e995e23 | 977 | i++; |
e76e9aeb BW |
978 | } |
979 | ||
e76e9aeb BW |
980 | /* XXX: This serves as a posting read to make sure that the PTE has |
981 | * actually been updated. There is some concern that even though | |
982 | * registers and PTEs are within the same BAR that they are potentially | |
983 | * of NUMA access patterns. Therefore, even with the way we assume | |
984 | * hardware should work, we must keep this posting read for paranoia. | |
985 | */ | |
986 | if (i != 0) | |
853ba5d2 | 987 | WARN_ON(readl(>t_entries[i-1]) != |
b35b380e | 988 | vm->pte_encode(addr, level, true)); |
0f9b91c7 BW |
989 | |
990 | /* This next bit makes the above posting read even more important. We | |
991 | * want to flush the TLBs only after we're certain all the PTE updates | |
992 | * have finished. | |
993 | */ | |
994 | I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN); | |
995 | POSTING_READ(GFX_FLSH_CNTL_GEN6); | |
e76e9aeb BW |
996 | } |
997 | ||
94ec8f61 BW |
998 | static void gen8_ggtt_clear_range(struct i915_address_space *vm, |
999 | unsigned int first_entry, | |
1000 | unsigned int num_entries, | |
1001 | bool use_scratch) | |
1002 | { | |
1003 | struct drm_i915_private *dev_priv = vm->dev->dev_private; | |
1004 | gen8_gtt_pte_t scratch_pte, __iomem *gtt_base = | |
1005 | (gen8_gtt_pte_t __iomem *) dev_priv->gtt.gsm + first_entry; | |
1006 | const int max_entries = gtt_total_entries(dev_priv->gtt) - first_entry; | |
1007 | int i; | |
1008 | ||
1009 | if (WARN(num_entries > max_entries, | |
1010 | "First entry = %d; Num entries = %d (max=%d)\n", | |
1011 | first_entry, num_entries, max_entries)) | |
1012 | num_entries = max_entries; | |
1013 | ||
1014 | scratch_pte = gen8_pte_encode(vm->scratch.addr, | |
1015 | I915_CACHE_LLC, | |
1016 | use_scratch); | |
1017 | for (i = 0; i < num_entries; i++) | |
1018 | gen8_set_pte(>t_base[i], scratch_pte); | |
1019 | readl(gtt_base); | |
1020 | } | |
1021 | ||
853ba5d2 | 1022 | static void gen6_ggtt_clear_range(struct i915_address_space *vm, |
7faf1ab2 | 1023 | unsigned int first_entry, |
828c7908 BW |
1024 | unsigned int num_entries, |
1025 | bool use_scratch) | |
7faf1ab2 | 1026 | { |
853ba5d2 | 1027 | struct drm_i915_private *dev_priv = vm->dev->dev_private; |
e7c2b58b BW |
1028 | gen6_gtt_pte_t scratch_pte, __iomem *gtt_base = |
1029 | (gen6_gtt_pte_t __iomem *) dev_priv->gtt.gsm + first_entry; | |
a54c0c27 | 1030 | const int max_entries = gtt_total_entries(dev_priv->gtt) - first_entry; |
7faf1ab2 DV |
1031 | int i; |
1032 | ||
1033 | if (WARN(num_entries > max_entries, | |
1034 | "First entry = %d; Num entries = %d (max=%d)\n", | |
1035 | first_entry, num_entries, max_entries)) | |
1036 | num_entries = max_entries; | |
1037 | ||
828c7908 BW |
1038 | scratch_pte = vm->pte_encode(vm->scratch.addr, I915_CACHE_LLC, use_scratch); |
1039 | ||
7faf1ab2 DV |
1040 | for (i = 0; i < num_entries; i++) |
1041 | iowrite32(scratch_pte, >t_base[i]); | |
1042 | readl(gtt_base); | |
1043 | } | |
1044 | ||
6f65e29a BW |
1045 | |
1046 | static void i915_ggtt_bind_vma(struct i915_vma *vma, | |
1047 | enum i915_cache_level cache_level, | |
1048 | u32 unused) | |
7faf1ab2 | 1049 | { |
6f65e29a | 1050 | const unsigned long entry = vma->node.start >> PAGE_SHIFT; |
7faf1ab2 DV |
1051 | unsigned int flags = (cache_level == I915_CACHE_NONE) ? |
1052 | AGP_USER_MEMORY : AGP_USER_CACHED_MEMORY; | |
1053 | ||
6f65e29a BW |
1054 | BUG_ON(!i915_is_ggtt(vma->vm)); |
1055 | intel_gtt_insert_sg_entries(vma->obj->pages, entry, flags); | |
1056 | vma->obj->has_global_gtt_mapping = 1; | |
7faf1ab2 DV |
1057 | } |
1058 | ||
853ba5d2 | 1059 | static void i915_ggtt_clear_range(struct i915_address_space *vm, |
7faf1ab2 | 1060 | unsigned int first_entry, |
828c7908 BW |
1061 | unsigned int num_entries, |
1062 | bool unused) | |
7faf1ab2 DV |
1063 | { |
1064 | intel_gtt_clear_range(first_entry, num_entries); | |
1065 | } | |
1066 | ||
6f65e29a BW |
1067 | static void i915_ggtt_unbind_vma(struct i915_vma *vma) |
1068 | { | |
1069 | const unsigned int first = vma->node.start >> PAGE_SHIFT; | |
1070 | const unsigned int size = vma->obj->base.size >> PAGE_SHIFT; | |
7faf1ab2 | 1071 | |
6f65e29a BW |
1072 | BUG_ON(!i915_is_ggtt(vma->vm)); |
1073 | vma->obj->has_global_gtt_mapping = 0; | |
1074 | intel_gtt_clear_range(first, size); | |
1075 | } | |
1076 | ||
1077 | static void ggtt_bind_vma(struct i915_vma *vma, | |
1078 | enum i915_cache_level cache_level, | |
1079 | u32 flags) | |
d5bd1449 | 1080 | { |
6f65e29a | 1081 | struct drm_device *dev = vma->vm->dev; |
7faf1ab2 | 1082 | struct drm_i915_private *dev_priv = dev->dev_private; |
6f65e29a BW |
1083 | struct drm_i915_gem_object *obj = vma->obj; |
1084 | const unsigned long entry = vma->node.start >> PAGE_SHIFT; | |
7faf1ab2 | 1085 | |
6f65e29a BW |
1086 | /* If there is no aliasing PPGTT, or the caller needs a global mapping, |
1087 | * or we have a global mapping already but the cacheability flags have | |
1088 | * changed, set the global PTEs. | |
1089 | * | |
1090 | * If there is an aliasing PPGTT it is anecdotally faster, so use that | |
1091 | * instead if none of the above hold true. | |
1092 | * | |
1093 | * NB: A global mapping should only be needed for special regions like | |
1094 | * "gtt mappable", SNB errata, or if specified via special execbuf | |
1095 | * flags. At all other times, the GPU will use the aliasing PPGTT. | |
1096 | */ | |
1097 | if (!dev_priv->mm.aliasing_ppgtt || flags & GLOBAL_BIND) { | |
1098 | if (!obj->has_global_gtt_mapping || | |
1099 | (cache_level != obj->cache_level)) { | |
1100 | vma->vm->insert_entries(vma->vm, obj->pages, entry, | |
1101 | cache_level); | |
1102 | obj->has_global_gtt_mapping = 1; | |
1103 | } | |
1104 | } | |
d5bd1449 | 1105 | |
6f65e29a BW |
1106 | if (dev_priv->mm.aliasing_ppgtt && |
1107 | (!obj->has_aliasing_ppgtt_mapping || | |
1108 | (cache_level != obj->cache_level))) { | |
1109 | struct i915_hw_ppgtt *appgtt = dev_priv->mm.aliasing_ppgtt; | |
1110 | appgtt->base.insert_entries(&appgtt->base, | |
1111 | vma->obj->pages, entry, cache_level); | |
1112 | vma->obj->has_aliasing_ppgtt_mapping = 1; | |
1113 | } | |
d5bd1449 CW |
1114 | } |
1115 | ||
6f65e29a | 1116 | static void ggtt_unbind_vma(struct i915_vma *vma) |
74163907 | 1117 | { |
6f65e29a | 1118 | struct drm_device *dev = vma->vm->dev; |
7faf1ab2 | 1119 | struct drm_i915_private *dev_priv = dev->dev_private; |
6f65e29a BW |
1120 | struct drm_i915_gem_object *obj = vma->obj; |
1121 | const unsigned long entry = vma->node.start >> PAGE_SHIFT; | |
1122 | ||
1123 | if (obj->has_global_gtt_mapping) { | |
1124 | vma->vm->clear_range(vma->vm, entry, | |
1125 | vma->obj->base.size >> PAGE_SHIFT, | |
1126 | true); | |
1127 | obj->has_global_gtt_mapping = 0; | |
1128 | } | |
74898d7e | 1129 | |
6f65e29a BW |
1130 | if (obj->has_aliasing_ppgtt_mapping) { |
1131 | struct i915_hw_ppgtt *appgtt = dev_priv->mm.aliasing_ppgtt; | |
1132 | appgtt->base.clear_range(&appgtt->base, | |
1133 | entry, | |
1134 | obj->base.size >> PAGE_SHIFT, | |
1135 | true); | |
1136 | obj->has_aliasing_ppgtt_mapping = 0; | |
1137 | } | |
74163907 DV |
1138 | } |
1139 | ||
1140 | void i915_gem_gtt_finish_object(struct drm_i915_gem_object *obj) | |
7c2e6fdf | 1141 | { |
5c042287 BW |
1142 | struct drm_device *dev = obj->base.dev; |
1143 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1144 | bool interruptible; | |
1145 | ||
1146 | interruptible = do_idling(dev_priv); | |
1147 | ||
9da3da66 CW |
1148 | if (!obj->has_dma_mapping) |
1149 | dma_unmap_sg(&dev->pdev->dev, | |
1150 | obj->pages->sgl, obj->pages->nents, | |
1151 | PCI_DMA_BIDIRECTIONAL); | |
5c042287 BW |
1152 | |
1153 | undo_idling(dev_priv, interruptible); | |
7c2e6fdf | 1154 | } |
644ec02b | 1155 | |
42d6ab48 CW |
1156 | static void i915_gtt_color_adjust(struct drm_mm_node *node, |
1157 | unsigned long color, | |
1158 | unsigned long *start, | |
1159 | unsigned long *end) | |
1160 | { | |
1161 | if (node->color != color) | |
1162 | *start += 4096; | |
1163 | ||
1164 | if (!list_empty(&node->node_list)) { | |
1165 | node = list_entry(node->node_list.next, | |
1166 | struct drm_mm_node, | |
1167 | node_list); | |
1168 | if (node->allocated && node->color != color) | |
1169 | *end -= 4096; | |
1170 | } | |
1171 | } | |
fbe5d36e | 1172 | |
d7e5008f BW |
1173 | void i915_gem_setup_global_gtt(struct drm_device *dev, |
1174 | unsigned long start, | |
1175 | unsigned long mappable_end, | |
1176 | unsigned long end) | |
644ec02b | 1177 | { |
e78891ca BW |
1178 | /* Let GEM Manage all of the aperture. |
1179 | * | |
1180 | * However, leave one page at the end still bound to the scratch page. | |
1181 | * There are a number of places where the hardware apparently prefetches | |
1182 | * past the end of the object, and we've seen multiple hangs with the | |
1183 | * GPU head pointer stuck in a batchbuffer bound at the last page of the | |
1184 | * aperture. One page should be enough to keep any prefetching inside | |
1185 | * of the aperture. | |
1186 | */ | |
40d74980 BW |
1187 | struct drm_i915_private *dev_priv = dev->dev_private; |
1188 | struct i915_address_space *ggtt_vm = &dev_priv->gtt.base; | |
ed2f3452 CW |
1189 | struct drm_mm_node *entry; |
1190 | struct drm_i915_gem_object *obj; | |
1191 | unsigned long hole_start, hole_end; | |
644ec02b | 1192 | |
35451cb6 BW |
1193 | BUG_ON(mappable_end > end); |
1194 | ||
ed2f3452 | 1195 | /* Subtract the guard page ... */ |
40d74980 | 1196 | drm_mm_init(&ggtt_vm->mm, start, end - start - PAGE_SIZE); |
42d6ab48 | 1197 | if (!HAS_LLC(dev)) |
93bd8649 | 1198 | dev_priv->gtt.base.mm.color_adjust = i915_gtt_color_adjust; |
644ec02b | 1199 | |
ed2f3452 | 1200 | /* Mark any preallocated objects as occupied */ |
35c20a60 | 1201 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) { |
40d74980 | 1202 | struct i915_vma *vma = i915_gem_obj_to_vma(obj, ggtt_vm); |
b3a070cc | 1203 | int ret; |
edd41a87 | 1204 | DRM_DEBUG_KMS("reserving preallocated space: %lx + %zx\n", |
c6cfb325 BW |
1205 | i915_gem_obj_ggtt_offset(obj), obj->base.size); |
1206 | ||
1207 | WARN_ON(i915_gem_obj_ggtt_bound(obj)); | |
40d74980 | 1208 | ret = drm_mm_reserve_node(&ggtt_vm->mm, &vma->node); |
c6cfb325 | 1209 | if (ret) |
b3a070cc | 1210 | DRM_DEBUG_KMS("Reservation failed\n"); |
ed2f3452 CW |
1211 | obj->has_global_gtt_mapping = 1; |
1212 | } | |
1213 | ||
853ba5d2 BW |
1214 | dev_priv->gtt.base.start = start; |
1215 | dev_priv->gtt.base.total = end - start; | |
644ec02b | 1216 | |
ed2f3452 | 1217 | /* Clear any non-preallocated blocks */ |
40d74980 | 1218 | drm_mm_for_each_hole(entry, &ggtt_vm->mm, hole_start, hole_end) { |
853ba5d2 | 1219 | const unsigned long count = (hole_end - hole_start) / PAGE_SIZE; |
ed2f3452 CW |
1220 | DRM_DEBUG_KMS("clearing unused GTT space: [%lx, %lx]\n", |
1221 | hole_start, hole_end); | |
828c7908 | 1222 | ggtt_vm->clear_range(ggtt_vm, hole_start / PAGE_SIZE, count, true); |
ed2f3452 CW |
1223 | } |
1224 | ||
1225 | /* And finally clear the reserved guard page */ | |
828c7908 | 1226 | ggtt_vm->clear_range(ggtt_vm, end / PAGE_SIZE - 1, 1, true); |
e76e9aeb BW |
1227 | } |
1228 | ||
d7e5008f BW |
1229 | static bool |
1230 | intel_enable_ppgtt(struct drm_device *dev) | |
1231 | { | |
1232 | if (i915_enable_ppgtt >= 0) | |
1233 | return i915_enable_ppgtt; | |
1234 | ||
1235 | #ifdef CONFIG_INTEL_IOMMU | |
1236 | /* Disable ppgtt on SNB if VT-d is on. */ | |
1237 | if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped) | |
1238 | return false; | |
1239 | #endif | |
1240 | ||
1241 | return true; | |
1242 | } | |
1243 | ||
1244 | void i915_gem_init_global_gtt(struct drm_device *dev) | |
1245 | { | |
1246 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1247 | unsigned long gtt_size, mappable_size; | |
d7e5008f | 1248 | |
853ba5d2 | 1249 | gtt_size = dev_priv->gtt.base.total; |
93d18799 | 1250 | mappable_size = dev_priv->gtt.mappable_end; |
d7e5008f BW |
1251 | |
1252 | if (intel_enable_ppgtt(dev) && HAS_ALIASING_PPGTT(dev)) { | |
e78891ca | 1253 | int ret; |
3eb1c005 BW |
1254 | |
1255 | if (INTEL_INFO(dev)->gen <= 7) { | |
1256 | /* PPGTT pdes are stolen from global gtt ptes, so shrink the | |
1257 | * aperture accordingly when using aliasing ppgtt. */ | |
6670a5a5 | 1258 | gtt_size -= GEN6_PPGTT_PD_ENTRIES * PAGE_SIZE; |
3eb1c005 | 1259 | } |
d7e5008f BW |
1260 | |
1261 | i915_gem_setup_global_gtt(dev, 0, mappable_size, gtt_size); | |
1262 | ||
1263 | ret = i915_gem_init_aliasing_ppgtt(dev); | |
e78891ca | 1264 | if (!ret) |
d7e5008f | 1265 | return; |
e78891ca BW |
1266 | |
1267 | DRM_ERROR("Aliased PPGTT setup failed %d\n", ret); | |
93bd8649 | 1268 | drm_mm_takedown(&dev_priv->gtt.base.mm); |
b42218c1 VS |
1269 | if (INTEL_INFO(dev)->gen < 8) |
1270 | gtt_size += GEN6_PPGTT_PD_ENTRIES*PAGE_SIZE; | |
d7e5008f | 1271 | } |
e78891ca | 1272 | i915_gem_setup_global_gtt(dev, 0, mappable_size, gtt_size); |
e76e9aeb BW |
1273 | } |
1274 | ||
1275 | static int setup_scratch_page(struct drm_device *dev) | |
1276 | { | |
1277 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1278 | struct page *page; | |
1279 | dma_addr_t dma_addr; | |
1280 | ||
1281 | page = alloc_page(GFP_KERNEL | GFP_DMA32 | __GFP_ZERO); | |
1282 | if (page == NULL) | |
1283 | return -ENOMEM; | |
1284 | get_page(page); | |
1285 | set_pages_uc(page, 1); | |
1286 | ||
1287 | #ifdef CONFIG_INTEL_IOMMU | |
1288 | dma_addr = pci_map_page(dev->pdev, page, 0, PAGE_SIZE, | |
1289 | PCI_DMA_BIDIRECTIONAL); | |
1290 | if (pci_dma_mapping_error(dev->pdev, dma_addr)) | |
1291 | return -EINVAL; | |
1292 | #else | |
1293 | dma_addr = page_to_phys(page); | |
1294 | #endif | |
853ba5d2 BW |
1295 | dev_priv->gtt.base.scratch.page = page; |
1296 | dev_priv->gtt.base.scratch.addr = dma_addr; | |
e76e9aeb BW |
1297 | |
1298 | return 0; | |
1299 | } | |
1300 | ||
1301 | static void teardown_scratch_page(struct drm_device *dev) | |
1302 | { | |
1303 | struct drm_i915_private *dev_priv = dev->dev_private; | |
853ba5d2 BW |
1304 | struct page *page = dev_priv->gtt.base.scratch.page; |
1305 | ||
1306 | set_pages_wb(page, 1); | |
1307 | pci_unmap_page(dev->pdev, dev_priv->gtt.base.scratch.addr, | |
e76e9aeb | 1308 | PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); |
853ba5d2 BW |
1309 | put_page(page); |
1310 | __free_page(page); | |
e76e9aeb BW |
1311 | } |
1312 | ||
1313 | static inline unsigned int gen6_get_total_gtt_size(u16 snb_gmch_ctl) | |
1314 | { | |
1315 | snb_gmch_ctl >>= SNB_GMCH_GGMS_SHIFT; | |
1316 | snb_gmch_ctl &= SNB_GMCH_GGMS_MASK; | |
1317 | return snb_gmch_ctl << 20; | |
1318 | } | |
1319 | ||
9459d252 BW |
1320 | static inline unsigned int gen8_get_total_gtt_size(u16 bdw_gmch_ctl) |
1321 | { | |
1322 | bdw_gmch_ctl >>= BDW_GMCH_GGMS_SHIFT; | |
1323 | bdw_gmch_ctl &= BDW_GMCH_GGMS_MASK; | |
1324 | if (bdw_gmch_ctl) | |
1325 | bdw_gmch_ctl = 1 << bdw_gmch_ctl; | |
3a2ffb65 BW |
1326 | if (bdw_gmch_ctl > 4) { |
1327 | WARN_ON(!i915_preliminary_hw_support); | |
1328 | return 4<<20; | |
1329 | } | |
1330 | ||
9459d252 BW |
1331 | return bdw_gmch_ctl << 20; |
1332 | } | |
1333 | ||
baa09f5f | 1334 | static inline size_t gen6_get_stolen_size(u16 snb_gmch_ctl) |
e76e9aeb BW |
1335 | { |
1336 | snb_gmch_ctl >>= SNB_GMCH_GMS_SHIFT; | |
1337 | snb_gmch_ctl &= SNB_GMCH_GMS_MASK; | |
1338 | return snb_gmch_ctl << 25; /* 32 MB units */ | |
1339 | } | |
1340 | ||
9459d252 BW |
1341 | static inline size_t gen8_get_stolen_size(u16 bdw_gmch_ctl) |
1342 | { | |
1343 | bdw_gmch_ctl >>= BDW_GMCH_GMS_SHIFT; | |
1344 | bdw_gmch_ctl &= BDW_GMCH_GMS_MASK; | |
1345 | return bdw_gmch_ctl << 25; /* 32 MB units */ | |
1346 | } | |
1347 | ||
63340133 BW |
1348 | static int ggtt_probe_common(struct drm_device *dev, |
1349 | size_t gtt_size) | |
1350 | { | |
1351 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1352 | phys_addr_t gtt_bus_addr; | |
1353 | int ret; | |
1354 | ||
1355 | /* For Modern GENs the PTEs and register space are split in the BAR */ | |
1356 | gtt_bus_addr = pci_resource_start(dev->pdev, 0) + | |
1357 | (pci_resource_len(dev->pdev, 0) / 2); | |
1358 | ||
1359 | dev_priv->gtt.gsm = ioremap_wc(gtt_bus_addr, gtt_size); | |
1360 | if (!dev_priv->gtt.gsm) { | |
1361 | DRM_ERROR("Failed to map the gtt page table\n"); | |
1362 | return -ENOMEM; | |
1363 | } | |
1364 | ||
1365 | ret = setup_scratch_page(dev); | |
1366 | if (ret) { | |
1367 | DRM_ERROR("Scratch setup failed\n"); | |
1368 | /* iounmap will also get called at remove, but meh */ | |
1369 | iounmap(dev_priv->gtt.gsm); | |
1370 | } | |
1371 | ||
1372 | return ret; | |
1373 | } | |
1374 | ||
fbe5d36e BW |
1375 | /* The GGTT and PPGTT need a private PPAT setup in order to handle cacheability |
1376 | * bits. When using advanced contexts each context stores its own PAT, but | |
1377 | * writing this data shouldn't be harmful even in those cases. */ | |
1378 | static void gen8_setup_private_ppat(struct drm_i915_private *dev_priv) | |
1379 | { | |
1380 | #define GEN8_PPAT_UC (0<<0) | |
1381 | #define GEN8_PPAT_WC (1<<0) | |
1382 | #define GEN8_PPAT_WT (2<<0) | |
1383 | #define GEN8_PPAT_WB (3<<0) | |
1384 | #define GEN8_PPAT_ELLC_OVERRIDE (0<<2) | |
1385 | /* FIXME(BDW): Bspec is completely confused about cache control bits. */ | |
1386 | #define GEN8_PPAT_LLC (1<<2) | |
1387 | #define GEN8_PPAT_LLCELLC (2<<2) | |
1388 | #define GEN8_PPAT_LLCeLLC (3<<2) | |
1389 | #define GEN8_PPAT_AGE(x) (x<<4) | |
1390 | #define GEN8_PPAT(i, x) ((uint64_t) (x) << ((i) * 8)) | |
1391 | uint64_t pat; | |
1392 | ||
1393 | pat = GEN8_PPAT(0, GEN8_PPAT_WB | GEN8_PPAT_LLC) | /* for normal objects, no eLLC */ | |
1394 | GEN8_PPAT(1, GEN8_PPAT_WC | GEN8_PPAT_LLCELLC) | /* for something pointing to ptes? */ | |
1395 | GEN8_PPAT(2, GEN8_PPAT_WT | GEN8_PPAT_LLCELLC) | /* for scanout with eLLC */ | |
1396 | GEN8_PPAT(3, GEN8_PPAT_UC) | /* Uncached objects, mostly for scanout */ | |
1397 | GEN8_PPAT(4, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(0)) | | |
1398 | GEN8_PPAT(5, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(1)) | | |
1399 | GEN8_PPAT(6, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(2)) | | |
1400 | GEN8_PPAT(7, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(3)); | |
1401 | ||
1402 | /* XXX: spec defines this as 2 distinct registers. It's unclear if a 64b | |
1403 | * write would work. */ | |
1404 | I915_WRITE(GEN8_PRIVATE_PAT, pat); | |
1405 | I915_WRITE(GEN8_PRIVATE_PAT + 4, pat >> 32); | |
1406 | } | |
1407 | ||
63340133 BW |
1408 | static int gen8_gmch_probe(struct drm_device *dev, |
1409 | size_t *gtt_total, | |
1410 | size_t *stolen, | |
1411 | phys_addr_t *mappable_base, | |
1412 | unsigned long *mappable_end) | |
1413 | { | |
1414 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1415 | unsigned int gtt_size; | |
1416 | u16 snb_gmch_ctl; | |
1417 | int ret; | |
1418 | ||
1419 | /* TODO: We're not aware of mappable constraints on gen8 yet */ | |
1420 | *mappable_base = pci_resource_start(dev->pdev, 2); | |
1421 | *mappable_end = pci_resource_len(dev->pdev, 2); | |
1422 | ||
1423 | if (!pci_set_dma_mask(dev->pdev, DMA_BIT_MASK(39))) | |
1424 | pci_set_consistent_dma_mask(dev->pdev, DMA_BIT_MASK(39)); | |
1425 | ||
1426 | pci_read_config_word(dev->pdev, SNB_GMCH_CTRL, &snb_gmch_ctl); | |
1427 | ||
1428 | *stolen = gen8_get_stolen_size(snb_gmch_ctl); | |
1429 | ||
1430 | gtt_size = gen8_get_total_gtt_size(snb_gmch_ctl); | |
d31eb10e | 1431 | *gtt_total = (gtt_size / sizeof(gen8_gtt_pte_t)) << PAGE_SHIFT; |
63340133 | 1432 | |
fbe5d36e BW |
1433 | gen8_setup_private_ppat(dev_priv); |
1434 | ||
63340133 BW |
1435 | ret = ggtt_probe_common(dev, gtt_size); |
1436 | ||
94ec8f61 BW |
1437 | dev_priv->gtt.base.clear_range = gen8_ggtt_clear_range; |
1438 | dev_priv->gtt.base.insert_entries = gen8_ggtt_insert_entries; | |
63340133 BW |
1439 | |
1440 | return ret; | |
1441 | } | |
1442 | ||
baa09f5f BW |
1443 | static int gen6_gmch_probe(struct drm_device *dev, |
1444 | size_t *gtt_total, | |
41907ddc BW |
1445 | size_t *stolen, |
1446 | phys_addr_t *mappable_base, | |
1447 | unsigned long *mappable_end) | |
e76e9aeb BW |
1448 | { |
1449 | struct drm_i915_private *dev_priv = dev->dev_private; | |
baa09f5f | 1450 | unsigned int gtt_size; |
e76e9aeb | 1451 | u16 snb_gmch_ctl; |
e76e9aeb BW |
1452 | int ret; |
1453 | ||
41907ddc BW |
1454 | *mappable_base = pci_resource_start(dev->pdev, 2); |
1455 | *mappable_end = pci_resource_len(dev->pdev, 2); | |
1456 | ||
baa09f5f BW |
1457 | /* 64/512MB is the current min/max we actually know of, but this is just |
1458 | * a coarse sanity check. | |
e76e9aeb | 1459 | */ |
41907ddc | 1460 | if ((*mappable_end < (64<<20) || (*mappable_end > (512<<20)))) { |
baa09f5f BW |
1461 | DRM_ERROR("Unknown GMADR size (%lx)\n", |
1462 | dev_priv->gtt.mappable_end); | |
1463 | return -ENXIO; | |
e76e9aeb BW |
1464 | } |
1465 | ||
e76e9aeb BW |
1466 | if (!pci_set_dma_mask(dev->pdev, DMA_BIT_MASK(40))) |
1467 | pci_set_consistent_dma_mask(dev->pdev, DMA_BIT_MASK(40)); | |
e76e9aeb | 1468 | pci_read_config_word(dev->pdev, SNB_GMCH_CTRL, &snb_gmch_ctl); |
e76e9aeb | 1469 | |
c4ae25ec | 1470 | *stolen = gen6_get_stolen_size(snb_gmch_ctl); |
a93e4161 | 1471 | |
63340133 BW |
1472 | gtt_size = gen6_get_total_gtt_size(snb_gmch_ctl); |
1473 | *gtt_total = (gtt_size / sizeof(gen6_gtt_pte_t)) << PAGE_SHIFT; | |
e76e9aeb | 1474 | |
63340133 | 1475 | ret = ggtt_probe_common(dev, gtt_size); |
e76e9aeb | 1476 | |
853ba5d2 BW |
1477 | dev_priv->gtt.base.clear_range = gen6_ggtt_clear_range; |
1478 | dev_priv->gtt.base.insert_entries = gen6_ggtt_insert_entries; | |
7faf1ab2 | 1479 | |
e76e9aeb BW |
1480 | return ret; |
1481 | } | |
1482 | ||
853ba5d2 | 1483 | static void gen6_gmch_remove(struct i915_address_space *vm) |
e76e9aeb | 1484 | { |
853ba5d2 BW |
1485 | |
1486 | struct i915_gtt *gtt = container_of(vm, struct i915_gtt, base); | |
5ed16782 BW |
1487 | |
1488 | drm_mm_takedown(&vm->mm); | |
853ba5d2 BW |
1489 | iounmap(gtt->gsm); |
1490 | teardown_scratch_page(vm->dev); | |
644ec02b | 1491 | } |
baa09f5f BW |
1492 | |
1493 | static int i915_gmch_probe(struct drm_device *dev, | |
1494 | size_t *gtt_total, | |
41907ddc BW |
1495 | size_t *stolen, |
1496 | phys_addr_t *mappable_base, | |
1497 | unsigned long *mappable_end) | |
baa09f5f BW |
1498 | { |
1499 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1500 | int ret; | |
1501 | ||
baa09f5f BW |
1502 | ret = intel_gmch_probe(dev_priv->bridge_dev, dev_priv->dev->pdev, NULL); |
1503 | if (!ret) { | |
1504 | DRM_ERROR("failed to set up gmch\n"); | |
1505 | return -EIO; | |
1506 | } | |
1507 | ||
41907ddc | 1508 | intel_gtt_get(gtt_total, stolen, mappable_base, mappable_end); |
baa09f5f BW |
1509 | |
1510 | dev_priv->gtt.do_idle_maps = needs_idle_maps(dev_priv->dev); | |
853ba5d2 | 1511 | dev_priv->gtt.base.clear_range = i915_ggtt_clear_range; |
baa09f5f BW |
1512 | |
1513 | return 0; | |
1514 | } | |
1515 | ||
853ba5d2 | 1516 | static void i915_gmch_remove(struct i915_address_space *vm) |
baa09f5f BW |
1517 | { |
1518 | intel_gmch_remove(); | |
1519 | } | |
1520 | ||
1521 | int i915_gem_gtt_init(struct drm_device *dev) | |
1522 | { | |
1523 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1524 | struct i915_gtt *gtt = &dev_priv->gtt; | |
baa09f5f BW |
1525 | int ret; |
1526 | ||
baa09f5f | 1527 | if (INTEL_INFO(dev)->gen <= 5) { |
b2f21b4d | 1528 | gtt->gtt_probe = i915_gmch_probe; |
853ba5d2 | 1529 | gtt->base.cleanup = i915_gmch_remove; |
63340133 | 1530 | } else if (INTEL_INFO(dev)->gen < 8) { |
b2f21b4d | 1531 | gtt->gtt_probe = gen6_gmch_probe; |
853ba5d2 | 1532 | gtt->base.cleanup = gen6_gmch_remove; |
4d15c145 | 1533 | if (IS_HASWELL(dev) && dev_priv->ellc_size) |
853ba5d2 | 1534 | gtt->base.pte_encode = iris_pte_encode; |
4d15c145 | 1535 | else if (IS_HASWELL(dev)) |
853ba5d2 | 1536 | gtt->base.pte_encode = hsw_pte_encode; |
b2f21b4d | 1537 | else if (IS_VALLEYVIEW(dev)) |
853ba5d2 | 1538 | gtt->base.pte_encode = byt_pte_encode; |
350ec881 CW |
1539 | else if (INTEL_INFO(dev)->gen >= 7) |
1540 | gtt->base.pte_encode = ivb_pte_encode; | |
b2f21b4d | 1541 | else |
350ec881 | 1542 | gtt->base.pte_encode = snb_pte_encode; |
63340133 BW |
1543 | } else { |
1544 | dev_priv->gtt.gtt_probe = gen8_gmch_probe; | |
1545 | dev_priv->gtt.base.cleanup = gen6_gmch_remove; | |
baa09f5f BW |
1546 | } |
1547 | ||
853ba5d2 | 1548 | ret = gtt->gtt_probe(dev, >t->base.total, >t->stolen_size, |
b2f21b4d | 1549 | >t->mappable_base, >t->mappable_end); |
a54c0c27 | 1550 | if (ret) |
baa09f5f | 1551 | return ret; |
baa09f5f | 1552 | |
853ba5d2 BW |
1553 | gtt->base.dev = dev; |
1554 | ||
baa09f5f | 1555 | /* GMADR is the PCI mmio aperture into the global GTT. */ |
853ba5d2 BW |
1556 | DRM_INFO("Memory usable by graphics device = %zdM\n", |
1557 | gtt->base.total >> 20); | |
b2f21b4d BW |
1558 | DRM_DEBUG_DRIVER("GMADR size = %ldM\n", gtt->mappable_end >> 20); |
1559 | DRM_DEBUG_DRIVER("GTT stolen size = %zdM\n", gtt->stolen_size >> 20); | |
baa09f5f BW |
1560 | |
1561 | return 0; | |
1562 | } | |
6f65e29a BW |
1563 | |
1564 | static struct i915_vma *__i915_gem_vma_create(struct drm_i915_gem_object *obj, | |
1565 | struct i915_address_space *vm) | |
1566 | { | |
1567 | struct i915_vma *vma = kzalloc(sizeof(*vma), GFP_KERNEL); | |
1568 | if (vma == NULL) | |
1569 | return ERR_PTR(-ENOMEM); | |
1570 | ||
1571 | INIT_LIST_HEAD(&vma->vma_link); | |
1572 | INIT_LIST_HEAD(&vma->mm_list); | |
1573 | INIT_LIST_HEAD(&vma->exec_list); | |
1574 | vma->vm = vm; | |
1575 | vma->obj = obj; | |
1576 | ||
1577 | switch (INTEL_INFO(vm->dev)->gen) { | |
1578 | case 8: | |
1579 | case 7: | |
1580 | case 6: | |
1581 | vma->unbind_vma = ggtt_unbind_vma; | |
1582 | vma->bind_vma = ggtt_bind_vma; | |
1583 | break; | |
1584 | case 5: | |
1585 | case 4: | |
1586 | case 3: | |
1587 | case 2: | |
1588 | BUG_ON(!i915_is_ggtt(vm)); | |
1589 | vma->unbind_vma = i915_ggtt_unbind_vma; | |
1590 | vma->bind_vma = i915_ggtt_bind_vma; | |
1591 | break; | |
1592 | default: | |
1593 | BUG(); | |
1594 | } | |
1595 | ||
1596 | /* Keep GGTT vmas first to make debug easier */ | |
1597 | if (i915_is_ggtt(vm)) | |
1598 | list_add(&vma->vma_link, &obj->vma_list); | |
1599 | else | |
1600 | list_add_tail(&vma->vma_link, &obj->vma_list); | |
1601 | ||
1602 | return vma; | |
1603 | } | |
1604 | ||
1605 | struct i915_vma * | |
1606 | i915_gem_obj_lookup_or_create_vma(struct drm_i915_gem_object *obj, | |
1607 | struct i915_address_space *vm) | |
1608 | { | |
1609 | struct i915_vma *vma; | |
1610 | ||
1611 | vma = i915_gem_obj_to_vma(obj, vm); | |
1612 | if (!vma) | |
1613 | vma = __i915_gem_vma_create(obj, vm); | |
1614 | ||
1615 | return vma; | |
1616 | } |