[deliverable/linux.git] / drivers / gpu / drm / i915 / i915_gem_gtt.c

/*
 * Copyright © 2010 Daniel Vetter
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice (including the next
 * paragraph) shall be included in all copies or substantial portions of the
 * Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
 * IN THE SOFTWARE.
 *
 */

#include "drmP.h"
#include "drm.h"
#include "i915_drm.h"
#include "i915_drv.h"
#include "i915_trace.h"
#include "intel_drv.h"

static void i915_gem_gtt_rebind_object(struct drm_i915_gem_object *obj,
				       enum i915_cache_level cache_level);

/* XXX kill agp_type! */
static unsigned int cache_level_to_agp_type(struct drm_device *dev,
					    enum i915_cache_level cache_level)
{
	switch (cache_level) {
	case I915_CACHE_LLC_MLC:
		if (INTEL_INFO(dev)->gen >= 6)
			return AGP_USER_CACHED_MEMORY_LLC_MLC;
		/* Older chipsets do not have this extra level of CPU
		 * cacheing, so fallthrough and request the PTE simply
		 * as cached.
		 */
	case I915_CACHE_LLC:
		return AGP_USER_CACHED_MEMORY;
	default:
	case I915_CACHE_NONE:
		return AGP_USER_MEMORY;
	}
}

void i915_gem_restore_gtt_mappings(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct drm_i915_gem_object *obj;

	/* First fill our portion of the GTT with scratch pages */
	intel_gtt_clear_range(dev_priv->mm.gtt_start / PAGE_SIZE,
			      (dev_priv->mm.gtt_end - dev_priv->mm.gtt_start) / PAGE_SIZE);

	list_for_each_entry(obj, &dev_priv->mm.gtt_list, gtt_list) {
		i915_gem_clflush_object(obj);
		i915_gem_gtt_rebind_object(obj, obj->cache_level);
	}

	intel_gtt_chipset_flush();
}

int i915_gem_gtt_bind_object(struct drm_i915_gem_object *obj)
{
	struct drm_device *dev = obj->base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	unsigned int agp_type = cache_level_to_agp_type(dev, obj->cache_level);
	int ret;

	if (dev_priv->mm.gtt->needs_dmar) {
		ret = intel_gtt_map_memory(obj->pages,
					   obj->base.size >> PAGE_SHIFT,
					   &obj->sg_list,
					   &obj->num_sg);
		if (ret != 0)
			return ret;

		intel_gtt_insert_sg_entries(obj->sg_list,
					    obj->num_sg,
					    obj->gtt_space->start >> PAGE_SHIFT,
					    agp_type);
	} else
		intel_gtt_insert_pages(obj->gtt_space->start >> PAGE_SHIFT,
				       obj->base.size >> PAGE_SHIFT,
				       obj->pages,
				       agp_type);

	return 0;
}

static void i915_gem_gtt_rebind_object(struct drm_i915_gem_object *obj,
				       enum i915_cache_level cache_level)
{
	struct drm_device *dev = obj->base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	unsigned int agp_type = cache_level_to_agp_type(dev, cache_level);

	if (dev_priv->mm.gtt->needs_dmar) {
		BUG_ON(!obj->sg_list);

		intel_gtt_insert_sg_entries(obj->sg_list,
					    obj->num_sg,
					    obj->gtt_space->start >> PAGE_SHIFT,
					    agp_type);
	} else
		intel_gtt_insert_pages(obj->gtt_space->start >> PAGE_SHIFT,
				       obj->base.size >> PAGE_SHIFT,
				       obj->pages,
				       agp_type);
}

void i915_gem_gtt_unbind_object(struct drm_i915_gem_object *obj)
{
	intel_gtt_clear_range(obj->gtt_space->start >> PAGE_SHIFT,
			      obj->base.size >> PAGE_SHIFT);

	if (obj->sg_list) {
		intel_gtt_unmap_memory(obj->sg_list, obj->num_sg);
		obj->sg_list = NULL;
	}
}
Commit	Line	Data
76aaf220 DV	1	/*
	2	* Copyright © 2010 Daniel Vetter
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice (including the next
	12	* paragraph) shall be included in all copies or substantial portions of the
	13	* Software.
	14	*
	15	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	16	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	17	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	18	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	19	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
	20	* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
	21	* IN THE SOFTWARE.
	22	*
	23	*/
	24
	25	#include "drmP.h"
	26	#include "drm.h"
	27	#include "i915_drm.h"
	28	#include "i915_drv.h"
	29	#include "i915_trace.h"
	30	#include "intel_drv.h"
	31
d5bd1449 CW	32	static void i915_gem_gtt_rebind_object(struct drm_i915_gem_object *obj,
	33	enum i915_cache_level cache_level);
	34
93dfb40c CW	35	/* XXX kill agp_type! */
	36	static unsigned int cache_level_to_agp_type(struct drm_device *dev,
	37	enum i915_cache_level cache_level)
	38	{
	39	switch (cache_level) {
	40	case I915_CACHE_LLC_MLC:
	41	if (INTEL_INFO(dev)->gen >= 6)
	42	return AGP_USER_CACHED_MEMORY_LLC_MLC;
	43	/* Older chipsets do not have this extra level of CPU
	44	* cacheing, so fallthrough and request the PTE simply
	45	* as cached.
	46	*/
	47	case I915_CACHE_LLC:
	48	return AGP_USER_CACHED_MEMORY;
	49	default:
	50	case I915_CACHE_NONE:
	51	return AGP_USER_MEMORY;
	52	}
	53	}
	54
76aaf220 DV	55	void i915_gem_restore_gtt_mappings(struct drm_device *dev)
	56	{
	57	struct drm_i915_private *dev_priv = dev->dev_private;
05394f39	58	struct drm_i915_gem_object *obj;
76aaf220	59
bee4a186 CW	60	/* First fill our portion of the GTT with scratch pages */
	61	intel_gtt_clear_range(dev_priv->mm.gtt_start / PAGE_SIZE,
	62	(dev_priv->mm.gtt_end - dev_priv->mm.gtt_start) / PAGE_SIZE);
	63
05394f39	64	list_for_each_entry(obj, &dev_priv->mm.gtt_list, gtt_list) {
a8e93126	65	i915_gem_clflush_object(obj);
d5bd1449	66	i915_gem_gtt_rebind_object(obj, obj->cache_level);
76aaf220 DV	67	}
76aaf220 DV	68
76aaf220 DV	69	intel_gtt_chipset_flush();
76aaf220 DV	70	}
7c2e6fdf	71
05394f39	72	int i915_gem_gtt_bind_object(struct drm_i915_gem_object *obj)
7c2e6fdf	73	{
05394f39	74	struct drm_device *dev = obj->base.dev;
185cbcb3	75	struct drm_i915_private *dev_priv = dev->dev_private;
93dfb40c	76	unsigned int agp_type = cache_level_to_agp_type(dev, obj->cache_level);
185cbcb3	77	int ret;
7c2e6fdf	78
185cbcb3	79	if (dev_priv->mm.gtt->needs_dmar) {
05394f39 CW	80	ret = intel_gtt_map_memory(obj->pages,
	81	obj->base.size >> PAGE_SHIFT,
	82	&obj->sg_list,
	83	&obj->num_sg);
185cbcb3 DV	84	if (ret != 0)
	85	return ret;
	86
05394f39 CW	87	intel_gtt_insert_sg_entries(obj->sg_list,
	88	obj->num_sg,
	89	obj->gtt_space->start >> PAGE_SHIFT,
93dfb40c	90	agp_type);
185cbcb3	91	} else
05394f39 CW	92	intel_gtt_insert_pages(obj->gtt_space->start >> PAGE_SHIFT,
	93	obj->base.size >> PAGE_SHIFT,
	94	obj->pages,
93dfb40c	95	agp_type);
7c2e6fdf	96
185cbcb3	97	return 0;
7c2e6fdf DV	98	}
7c2e6fdf DV	99
d5bd1449 CW	100	static void i915_gem_gtt_rebind_object(struct drm_i915_gem_object *obj,
	101	enum i915_cache_level cache_level)
	102	{
	103	struct drm_device *dev = obj->base.dev;
	104	struct drm_i915_private *dev_priv = dev->dev_private;
	105	unsigned int agp_type = cache_level_to_agp_type(dev, cache_level);
	106
	107	if (dev_priv->mm.gtt->needs_dmar) {
	108	BUG_ON(!obj->sg_list);
	109
	110	intel_gtt_insert_sg_entries(obj->sg_list,
	111	obj->num_sg,
	112	obj->gtt_space->start >> PAGE_SHIFT,
	113	agp_type);
	114	} else
	115	intel_gtt_insert_pages(obj->gtt_space->start >> PAGE_SHIFT,
	116	obj->base.size >> PAGE_SHIFT,
	117	obj->pages,
	118	agp_type);
	119	}
	120
05394f39	121	void i915_gem_gtt_unbind_object(struct drm_i915_gem_object *obj)
7c2e6fdf	122	{
d9126400 CW	123	intel_gtt_clear_range(obj->gtt_space->start >> PAGE_SHIFT,
d9126400 CW	124	obj->base.size >> PAGE_SHIFT);
7c2e6fdf	125
d9126400	126	if (obj->sg_list) {
05394f39 CW	127	intel_gtt_unmap_memory(obj->sg_list, obj->num_sg);
05394f39 CW	128	obj->sg_list = NULL;
185cbcb3	129	}
7c2e6fdf	130	}