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76aaf220 DV |
1 | /* |
2 | * Copyright © 2010 Daniel Vetter | |
c4ac524c | 3 | * Copyright © 2011-2014 Intel Corporation |
76aaf220 DV |
4 | * |
5 | * Permission is hereby granted, free of charge, to any person obtaining a | |
6 | * copy of this software and associated documentation files (the "Software"), | |
7 | * to deal in the Software without restriction, including without limitation | |
8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
9 | * and/or sell copies of the Software, and to permit persons to whom the | |
10 | * Software is furnished to do so, subject to the following conditions: | |
11 | * | |
12 | * The above copyright notice and this permission notice (including the next | |
13 | * paragraph) shall be included in all copies or substantial portions of the | |
14 | * Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
21 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
22 | * IN THE SOFTWARE. | |
23 | * | |
24 | */ | |
25 | ||
0e46ce2e | 26 | #include <linux/seq_file.h> |
760285e7 DH |
27 | #include <drm/drmP.h> |
28 | #include <drm/i915_drm.h> | |
76aaf220 | 29 | #include "i915_drv.h" |
5dda8fa3 | 30 | #include "i915_vgpu.h" |
76aaf220 DV |
31 | #include "i915_trace.h" |
32 | #include "intel_drv.h" | |
33 | ||
45f8f69a TU |
34 | /** |
35 | * DOC: Global GTT views | |
36 | * | |
37 | * Background and previous state | |
38 | * | |
39 | * Historically objects could exists (be bound) in global GTT space only as | |
40 | * singular instances with a view representing all of the object's backing pages | |
41 | * in a linear fashion. This view will be called a normal view. | |
42 | * | |
43 | * To support multiple views of the same object, where the number of mapped | |
44 | * pages is not equal to the backing store, or where the layout of the pages | |
45 | * is not linear, concept of a GGTT view was added. | |
46 | * | |
47 | * One example of an alternative view is a stereo display driven by a single | |
48 | * image. In this case we would have a framebuffer looking like this | |
49 | * (2x2 pages): | |
50 | * | |
51 | * 12 | |
52 | * 34 | |
53 | * | |
54 | * Above would represent a normal GGTT view as normally mapped for GPU or CPU | |
55 | * rendering. In contrast, fed to the display engine would be an alternative | |
56 | * view which could look something like this: | |
57 | * | |
58 | * 1212 | |
59 | * 3434 | |
60 | * | |
61 | * In this example both the size and layout of pages in the alternative view is | |
62 | * different from the normal view. | |
63 | * | |
64 | * Implementation and usage | |
65 | * | |
66 | * GGTT views are implemented using VMAs and are distinguished via enum | |
67 | * i915_ggtt_view_type and struct i915_ggtt_view. | |
68 | * | |
69 | * A new flavour of core GEM functions which work with GGTT bound objects were | |
ec7adb6e JL |
70 | * added with the _ggtt_ infix, and sometimes with _view postfix to avoid |
71 | * renaming in large amounts of code. They take the struct i915_ggtt_view | |
72 | * parameter encapsulating all metadata required to implement a view. | |
45f8f69a TU |
73 | * |
74 | * As a helper for callers which are only interested in the normal view, | |
75 | * globally const i915_ggtt_view_normal singleton instance exists. All old core | |
76 | * GEM API functions, the ones not taking the view parameter, are operating on, | |
77 | * or with the normal GGTT view. | |
78 | * | |
79 | * Code wanting to add or use a new GGTT view needs to: | |
80 | * | |
81 | * 1. Add a new enum with a suitable name. | |
82 | * 2. Extend the metadata in the i915_ggtt_view structure if required. | |
83 | * 3. Add support to i915_get_vma_pages(). | |
84 | * | |
85 | * New views are required to build a scatter-gather table from within the | |
86 | * i915_get_vma_pages function. This table is stored in the vma.ggtt_view and | |
87 | * exists for the lifetime of an VMA. | |
88 | * | |
89 | * Core API is designed to have copy semantics which means that passed in | |
90 | * struct i915_ggtt_view does not need to be persistent (left around after | |
91 | * calling the core API functions). | |
92 | * | |
93 | */ | |
94 | ||
fe14d5f4 TU |
95 | const struct i915_ggtt_view i915_ggtt_view_normal; |
96 | ||
ee0ce478 VS |
97 | static void bdw_setup_private_ppat(struct drm_i915_private *dev_priv); |
98 | static void chv_setup_private_ppat(struct drm_i915_private *dev_priv); | |
a2319c08 | 99 | |
cfa7c862 DV |
100 | static int sanitize_enable_ppgtt(struct drm_device *dev, int enable_ppgtt) |
101 | { | |
1893a71b CW |
102 | bool has_aliasing_ppgtt; |
103 | bool has_full_ppgtt; | |
104 | ||
105 | has_aliasing_ppgtt = INTEL_INFO(dev)->gen >= 6; | |
106 | has_full_ppgtt = INTEL_INFO(dev)->gen >= 7; | |
1893a71b | 107 | |
71ba2d64 YZ |
108 | if (intel_vgpu_active(dev)) |
109 | has_full_ppgtt = false; /* emulation is too hard */ | |
110 | ||
70ee45e1 DL |
111 | /* |
112 | * We don't allow disabling PPGTT for gen9+ as it's a requirement for | |
113 | * execlists, the sole mechanism available to submit work. | |
114 | */ | |
115 | if (INTEL_INFO(dev)->gen < 9 && | |
116 | (enable_ppgtt == 0 || !has_aliasing_ppgtt)) | |
cfa7c862 DV |
117 | return 0; |
118 | ||
119 | if (enable_ppgtt == 1) | |
120 | return 1; | |
121 | ||
1893a71b | 122 | if (enable_ppgtt == 2 && has_full_ppgtt) |
cfa7c862 DV |
123 | return 2; |
124 | ||
93a25a9e DV |
125 | #ifdef CONFIG_INTEL_IOMMU |
126 | /* Disable ppgtt on SNB if VT-d is on. */ | |
127 | if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped) { | |
128 | DRM_INFO("Disabling PPGTT because VT-d is on\n"); | |
cfa7c862 | 129 | return 0; |
93a25a9e DV |
130 | } |
131 | #endif | |
132 | ||
62942ed7 | 133 | /* Early VLV doesn't have this */ |
ca2aed6c VS |
134 | if (IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) && |
135 | dev->pdev->revision < 0xb) { | |
62942ed7 JB |
136 | DRM_DEBUG_DRIVER("disabling PPGTT on pre-B3 step VLV\n"); |
137 | return 0; | |
138 | } | |
139 | ||
2f82bbdf MT |
140 | if (INTEL_INFO(dev)->gen >= 8 && i915.enable_execlists) |
141 | return 2; | |
142 | else | |
143 | return has_aliasing_ppgtt ? 1 : 0; | |
93a25a9e DV |
144 | } |
145 | ||
6f65e29a BW |
146 | static void ppgtt_bind_vma(struct i915_vma *vma, |
147 | enum i915_cache_level cache_level, | |
148 | u32 flags); | |
149 | static void ppgtt_unbind_vma(struct i915_vma *vma); | |
150 | ||
07749ef3 MT |
151 | static inline gen8_pte_t gen8_pte_encode(dma_addr_t addr, |
152 | enum i915_cache_level level, | |
153 | bool valid) | |
94ec8f61 | 154 | { |
07749ef3 | 155 | gen8_pte_t pte = valid ? _PAGE_PRESENT | _PAGE_RW : 0; |
94ec8f61 | 156 | pte |= addr; |
63c42e56 BW |
157 | |
158 | switch (level) { | |
159 | case I915_CACHE_NONE: | |
fbe5d36e | 160 | pte |= PPAT_UNCACHED_INDEX; |
63c42e56 BW |
161 | break; |
162 | case I915_CACHE_WT: | |
163 | pte |= PPAT_DISPLAY_ELLC_INDEX; | |
164 | break; | |
165 | default: | |
166 | pte |= PPAT_CACHED_INDEX; | |
167 | break; | |
168 | } | |
169 | ||
94ec8f61 BW |
170 | return pte; |
171 | } | |
172 | ||
07749ef3 MT |
173 | static inline gen8_pde_t gen8_pde_encode(struct drm_device *dev, |
174 | dma_addr_t addr, | |
175 | enum i915_cache_level level) | |
b1fe6673 | 176 | { |
07749ef3 | 177 | gen8_pde_t pde = _PAGE_PRESENT | _PAGE_RW; |
b1fe6673 BW |
178 | pde |= addr; |
179 | if (level != I915_CACHE_NONE) | |
180 | pde |= PPAT_CACHED_PDE_INDEX; | |
181 | else | |
182 | pde |= PPAT_UNCACHED_INDEX; | |
183 | return pde; | |
184 | } | |
185 | ||
07749ef3 MT |
186 | static gen6_pte_t snb_pte_encode(dma_addr_t addr, |
187 | enum i915_cache_level level, | |
188 | bool valid, u32 unused) | |
54d12527 | 189 | { |
07749ef3 | 190 | gen6_pte_t pte = valid ? GEN6_PTE_VALID : 0; |
54d12527 | 191 | pte |= GEN6_PTE_ADDR_ENCODE(addr); |
e7210c3c BW |
192 | |
193 | switch (level) { | |
350ec881 CW |
194 | case I915_CACHE_L3_LLC: |
195 | case I915_CACHE_LLC: | |
196 | pte |= GEN6_PTE_CACHE_LLC; | |
197 | break; | |
198 | case I915_CACHE_NONE: | |
199 | pte |= GEN6_PTE_UNCACHED; | |
200 | break; | |
201 | default: | |
5f77eeb0 | 202 | MISSING_CASE(level); |
350ec881 CW |
203 | } |
204 | ||
205 | return pte; | |
206 | } | |
207 | ||
07749ef3 MT |
208 | static gen6_pte_t ivb_pte_encode(dma_addr_t addr, |
209 | enum i915_cache_level level, | |
210 | bool valid, u32 unused) | |
350ec881 | 211 | { |
07749ef3 | 212 | gen6_pte_t pte = valid ? GEN6_PTE_VALID : 0; |
350ec881 CW |
213 | pte |= GEN6_PTE_ADDR_ENCODE(addr); |
214 | ||
215 | switch (level) { | |
216 | case I915_CACHE_L3_LLC: | |
217 | pte |= GEN7_PTE_CACHE_L3_LLC; | |
e7210c3c BW |
218 | break; |
219 | case I915_CACHE_LLC: | |
220 | pte |= GEN6_PTE_CACHE_LLC; | |
221 | break; | |
222 | case I915_CACHE_NONE: | |
9119708c | 223 | pte |= GEN6_PTE_UNCACHED; |
e7210c3c BW |
224 | break; |
225 | default: | |
5f77eeb0 | 226 | MISSING_CASE(level); |
e7210c3c BW |
227 | } |
228 | ||
54d12527 BW |
229 | return pte; |
230 | } | |
231 | ||
07749ef3 MT |
232 | static gen6_pte_t byt_pte_encode(dma_addr_t addr, |
233 | enum i915_cache_level level, | |
234 | bool valid, u32 flags) | |
93c34e70 | 235 | { |
07749ef3 | 236 | gen6_pte_t pte = valid ? GEN6_PTE_VALID : 0; |
93c34e70 KG |
237 | pte |= GEN6_PTE_ADDR_ENCODE(addr); |
238 | ||
24f3a8cf AG |
239 | if (!(flags & PTE_READ_ONLY)) |
240 | pte |= BYT_PTE_WRITEABLE; | |
93c34e70 KG |
241 | |
242 | if (level != I915_CACHE_NONE) | |
243 | pte |= BYT_PTE_SNOOPED_BY_CPU_CACHES; | |
244 | ||
245 | return pte; | |
246 | } | |
247 | ||
07749ef3 MT |
248 | static gen6_pte_t hsw_pte_encode(dma_addr_t addr, |
249 | enum i915_cache_level level, | |
250 | bool valid, u32 unused) | |
9119708c | 251 | { |
07749ef3 | 252 | gen6_pte_t pte = valid ? GEN6_PTE_VALID : 0; |
0d8ff15e | 253 | pte |= HSW_PTE_ADDR_ENCODE(addr); |
9119708c KG |
254 | |
255 | if (level != I915_CACHE_NONE) | |
87a6b688 | 256 | pte |= HSW_WB_LLC_AGE3; |
9119708c KG |
257 | |
258 | return pte; | |
259 | } | |
260 | ||
07749ef3 MT |
261 | static gen6_pte_t iris_pte_encode(dma_addr_t addr, |
262 | enum i915_cache_level level, | |
263 | bool valid, u32 unused) | |
4d15c145 | 264 | { |
07749ef3 | 265 | gen6_pte_t pte = valid ? GEN6_PTE_VALID : 0; |
4d15c145 BW |
266 | pte |= HSW_PTE_ADDR_ENCODE(addr); |
267 | ||
651d794f CW |
268 | switch (level) { |
269 | case I915_CACHE_NONE: | |
270 | break; | |
271 | case I915_CACHE_WT: | |
c51e9701 | 272 | pte |= HSW_WT_ELLC_LLC_AGE3; |
651d794f CW |
273 | break; |
274 | default: | |
c51e9701 | 275 | pte |= HSW_WB_ELLC_LLC_AGE3; |
651d794f CW |
276 | break; |
277 | } | |
4d15c145 BW |
278 | |
279 | return pte; | |
280 | } | |
281 | ||
678d96fb BW |
282 | #define i915_dma_unmap_single(px, dev) \ |
283 | __i915_dma_unmap_single((px)->daddr, dev) | |
284 | ||
285 | static inline void __i915_dma_unmap_single(dma_addr_t daddr, | |
286 | struct drm_device *dev) | |
287 | { | |
288 | struct device *device = &dev->pdev->dev; | |
289 | ||
290 | dma_unmap_page(device, daddr, 4096, PCI_DMA_BIDIRECTIONAL); | |
291 | } | |
292 | ||
293 | /** | |
294 | * i915_dma_map_single() - Create a dma mapping for a page table/dir/etc. | |
295 | * @px: Page table/dir/etc to get a DMA map for | |
296 | * @dev: drm device | |
297 | * | |
298 | * Page table allocations are unified across all gens. They always require a | |
299 | * single 4k allocation, as well as a DMA mapping. If we keep the structs | |
300 | * symmetric here, the simple macro covers us for every page table type. | |
301 | * | |
302 | * Return: 0 if success. | |
303 | */ | |
304 | #define i915_dma_map_single(px, dev) \ | |
305 | i915_dma_map_page_single((px)->page, (dev), &(px)->daddr) | |
306 | ||
307 | static inline int i915_dma_map_page_single(struct page *page, | |
308 | struct drm_device *dev, | |
309 | dma_addr_t *daddr) | |
310 | { | |
311 | struct device *device = &dev->pdev->dev; | |
312 | ||
313 | *daddr = dma_map_page(device, page, 0, 4096, PCI_DMA_BIDIRECTIONAL); | |
314 | return dma_mapping_error(device, *daddr); | |
315 | } | |
316 | ||
317 | static void unmap_and_free_pt(struct i915_page_table_entry *pt, | |
318 | struct drm_device *dev) | |
06fda602 BW |
319 | { |
320 | if (WARN_ON(!pt->page)) | |
321 | return; | |
678d96fb BW |
322 | |
323 | i915_dma_unmap_single(pt, dev); | |
06fda602 | 324 | __free_page(pt->page); |
678d96fb | 325 | kfree(pt->used_ptes); |
06fda602 BW |
326 | kfree(pt); |
327 | } | |
328 | ||
06dc68d6 | 329 | static struct i915_page_table_entry *alloc_pt_single(struct drm_device *dev) |
06fda602 BW |
330 | { |
331 | struct i915_page_table_entry *pt; | |
678d96fb BW |
332 | const size_t count = INTEL_INFO(dev)->gen >= 8 ? |
333 | GEN8_PTES : GEN6_PTES; | |
334 | int ret = -ENOMEM; | |
06fda602 BW |
335 | |
336 | pt = kzalloc(sizeof(*pt), GFP_KERNEL); | |
337 | if (!pt) | |
338 | return ERR_PTR(-ENOMEM); | |
339 | ||
678d96fb BW |
340 | pt->used_ptes = kcalloc(BITS_TO_LONGS(count), sizeof(*pt->used_ptes), |
341 | GFP_KERNEL); | |
342 | ||
343 | if (!pt->used_ptes) | |
344 | goto fail_bitmap; | |
345 | ||
06fda602 | 346 | pt->page = alloc_page(GFP_KERNEL | __GFP_ZERO); |
678d96fb BW |
347 | if (!pt->page) |
348 | goto fail_page; | |
349 | ||
350 | ret = i915_dma_map_single(pt, dev); | |
351 | if (ret) | |
352 | goto fail_dma; | |
06fda602 BW |
353 | |
354 | return pt; | |
678d96fb BW |
355 | |
356 | fail_dma: | |
357 | __free_page(pt->page); | |
358 | fail_page: | |
359 | kfree(pt->used_ptes); | |
360 | fail_bitmap: | |
361 | kfree(pt); | |
362 | ||
363 | return ERR_PTR(ret); | |
06fda602 BW |
364 | } |
365 | ||
366 | /** | |
367 | * alloc_pt_range() - Allocate a multiple page tables | |
368 | * @pd: The page directory which will have at least @count entries | |
369 | * available to point to the allocated page tables. | |
370 | * @pde: First page directory entry for which we are allocating. | |
371 | * @count: Number of pages to allocate. | |
719cd21c | 372 | * @dev: DRM device. |
06fda602 BW |
373 | * |
374 | * Allocates multiple page table pages and sets the appropriate entries in the | |
375 | * page table structure within the page directory. Function cleans up after | |
376 | * itself on any failures. | |
377 | * | |
378 | * Return: 0 if allocation succeeded. | |
379 | */ | |
06dc68d6 MT |
380 | static int alloc_pt_range(struct i915_page_directory_entry *pd, uint16_t pde, size_t count, |
381 | struct drm_device *dev) | |
06fda602 BW |
382 | { |
383 | int i, ret; | |
384 | ||
385 | /* 512 is the max page tables per page_directory on any platform. */ | |
07749ef3 | 386 | if (WARN_ON(pde + count > I915_PDES)) |
06fda602 BW |
387 | return -EINVAL; |
388 | ||
389 | for (i = pde; i < pde + count; i++) { | |
06dc68d6 | 390 | struct i915_page_table_entry *pt = alloc_pt_single(dev); |
06fda602 BW |
391 | |
392 | if (IS_ERR(pt)) { | |
393 | ret = PTR_ERR(pt); | |
394 | goto err_out; | |
395 | } | |
396 | WARN(pd->page_table[i], | |
686135da | 397 | "Leaking page directory entry %d (%p)\n", |
06fda602 BW |
398 | i, pd->page_table[i]); |
399 | pd->page_table[i] = pt; | |
400 | } | |
401 | ||
402 | return 0; | |
403 | ||
404 | err_out: | |
405 | while (i-- > pde) | |
06dc68d6 | 406 | unmap_and_free_pt(pd->page_table[i], dev); |
06fda602 BW |
407 | return ret; |
408 | } | |
409 | ||
410 | static void unmap_and_free_pd(struct i915_page_directory_entry *pd) | |
411 | { | |
412 | if (pd->page) { | |
413 | __free_page(pd->page); | |
414 | kfree(pd); | |
415 | } | |
416 | } | |
417 | ||
418 | static struct i915_page_directory_entry *alloc_pd_single(void) | |
419 | { | |
420 | struct i915_page_directory_entry *pd; | |
421 | ||
422 | pd = kzalloc(sizeof(*pd), GFP_KERNEL); | |
423 | if (!pd) | |
424 | return ERR_PTR(-ENOMEM); | |
425 | ||
426 | pd->page = alloc_page(GFP_KERNEL | __GFP_ZERO); | |
427 | if (!pd->page) { | |
428 | kfree(pd); | |
429 | return ERR_PTR(-ENOMEM); | |
430 | } | |
431 | ||
432 | return pd; | |
433 | } | |
434 | ||
94e409c1 | 435 | /* Broadwell Page Directory Pointer Descriptors */ |
a4872ba6 | 436 | static int gen8_write_pdp(struct intel_engine_cs *ring, unsigned entry, |
6689c167 | 437 | uint64_t val) |
94e409c1 BW |
438 | { |
439 | int ret; | |
440 | ||
441 | BUG_ON(entry >= 4); | |
442 | ||
443 | ret = intel_ring_begin(ring, 6); | |
444 | if (ret) | |
445 | return ret; | |
446 | ||
447 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); | |
448 | intel_ring_emit(ring, GEN8_RING_PDP_UDW(ring, entry)); | |
449 | intel_ring_emit(ring, (u32)(val >> 32)); | |
450 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); | |
451 | intel_ring_emit(ring, GEN8_RING_PDP_LDW(ring, entry)); | |
452 | intel_ring_emit(ring, (u32)(val)); | |
453 | intel_ring_advance(ring); | |
454 | ||
455 | return 0; | |
456 | } | |
457 | ||
eeb9488e | 458 | static int gen8_mm_switch(struct i915_hw_ppgtt *ppgtt, |
6689c167 | 459 | struct intel_engine_cs *ring) |
94e409c1 | 460 | { |
eeb9488e | 461 | int i, ret; |
94e409c1 BW |
462 | |
463 | /* bit of a hack to find the actual last used pd */ | |
07749ef3 | 464 | int used_pd = ppgtt->num_pd_entries / I915_PDES; |
94e409c1 | 465 | |
94e409c1 | 466 | for (i = used_pd - 1; i >= 0; i--) { |
06fda602 | 467 | dma_addr_t addr = ppgtt->pdp.page_directory[i]->daddr; |
6689c167 | 468 | ret = gen8_write_pdp(ring, i, addr); |
eeb9488e BW |
469 | if (ret) |
470 | return ret; | |
94e409c1 | 471 | } |
d595bd4b | 472 | |
eeb9488e | 473 | return 0; |
94e409c1 BW |
474 | } |
475 | ||
459108b8 | 476 | static void gen8_ppgtt_clear_range(struct i915_address_space *vm, |
782f1495 BW |
477 | uint64_t start, |
478 | uint64_t length, | |
459108b8 BW |
479 | bool use_scratch) |
480 | { | |
481 | struct i915_hw_ppgtt *ppgtt = | |
482 | container_of(vm, struct i915_hw_ppgtt, base); | |
07749ef3 | 483 | gen8_pte_t *pt_vaddr, scratch_pte; |
7ad47cf2 BW |
484 | unsigned pdpe = start >> GEN8_PDPE_SHIFT & GEN8_PDPE_MASK; |
485 | unsigned pde = start >> GEN8_PDE_SHIFT & GEN8_PDE_MASK; | |
486 | unsigned pte = start >> GEN8_PTE_SHIFT & GEN8_PTE_MASK; | |
782f1495 | 487 | unsigned num_entries = length >> PAGE_SHIFT; |
459108b8 BW |
488 | unsigned last_pte, i; |
489 | ||
490 | scratch_pte = gen8_pte_encode(ppgtt->base.scratch.addr, | |
491 | I915_CACHE_LLC, use_scratch); | |
492 | ||
493 | while (num_entries) { | |
06fda602 BW |
494 | struct i915_page_directory_entry *pd; |
495 | struct i915_page_table_entry *pt; | |
496 | struct page *page_table; | |
497 | ||
498 | if (WARN_ON(!ppgtt->pdp.page_directory[pdpe])) | |
499 | continue; | |
500 | ||
501 | pd = ppgtt->pdp.page_directory[pdpe]; | |
502 | ||
503 | if (WARN_ON(!pd->page_table[pde])) | |
504 | continue; | |
505 | ||
506 | pt = pd->page_table[pde]; | |
507 | ||
508 | if (WARN_ON(!pt->page)) | |
509 | continue; | |
510 | ||
511 | page_table = pt->page; | |
459108b8 | 512 | |
7ad47cf2 | 513 | last_pte = pte + num_entries; |
07749ef3 MT |
514 | if (last_pte > GEN8_PTES) |
515 | last_pte = GEN8_PTES; | |
459108b8 BW |
516 | |
517 | pt_vaddr = kmap_atomic(page_table); | |
518 | ||
7ad47cf2 | 519 | for (i = pte; i < last_pte; i++) { |
459108b8 | 520 | pt_vaddr[i] = scratch_pte; |
7ad47cf2 BW |
521 | num_entries--; |
522 | } | |
459108b8 | 523 | |
fd1ab8f4 RB |
524 | if (!HAS_LLC(ppgtt->base.dev)) |
525 | drm_clflush_virt_range(pt_vaddr, PAGE_SIZE); | |
459108b8 BW |
526 | kunmap_atomic(pt_vaddr); |
527 | ||
7ad47cf2 | 528 | pte = 0; |
07749ef3 | 529 | if (++pde == I915_PDES) { |
7ad47cf2 BW |
530 | pdpe++; |
531 | pde = 0; | |
532 | } | |
459108b8 BW |
533 | } |
534 | } | |
535 | ||
9df15b49 BW |
536 | static void gen8_ppgtt_insert_entries(struct i915_address_space *vm, |
537 | struct sg_table *pages, | |
782f1495 | 538 | uint64_t start, |
24f3a8cf | 539 | enum i915_cache_level cache_level, u32 unused) |
9df15b49 BW |
540 | { |
541 | struct i915_hw_ppgtt *ppgtt = | |
542 | container_of(vm, struct i915_hw_ppgtt, base); | |
07749ef3 | 543 | gen8_pte_t *pt_vaddr; |
7ad47cf2 BW |
544 | unsigned pdpe = start >> GEN8_PDPE_SHIFT & GEN8_PDPE_MASK; |
545 | unsigned pde = start >> GEN8_PDE_SHIFT & GEN8_PDE_MASK; | |
546 | unsigned pte = start >> GEN8_PTE_SHIFT & GEN8_PTE_MASK; | |
9df15b49 BW |
547 | struct sg_page_iter sg_iter; |
548 | ||
6f1cc993 | 549 | pt_vaddr = NULL; |
7ad47cf2 | 550 | |
9df15b49 | 551 | for_each_sg_page(pages->sgl, &sg_iter, pages->nents, 0) { |
76643600 | 552 | if (WARN_ON(pdpe >= GEN8_LEGACY_PDPES)) |
7ad47cf2 BW |
553 | break; |
554 | ||
d7b3de91 | 555 | if (pt_vaddr == NULL) { |
06fda602 BW |
556 | struct i915_page_directory_entry *pd = ppgtt->pdp.page_directory[pdpe]; |
557 | struct i915_page_table_entry *pt = pd->page_table[pde]; | |
558 | struct page *page_table = pt->page; | |
d7b3de91 BW |
559 | |
560 | pt_vaddr = kmap_atomic(page_table); | |
561 | } | |
9df15b49 | 562 | |
7ad47cf2 | 563 | pt_vaddr[pte] = |
6f1cc993 CW |
564 | gen8_pte_encode(sg_page_iter_dma_address(&sg_iter), |
565 | cache_level, true); | |
07749ef3 | 566 | if (++pte == GEN8_PTES) { |
fd1ab8f4 RB |
567 | if (!HAS_LLC(ppgtt->base.dev)) |
568 | drm_clflush_virt_range(pt_vaddr, PAGE_SIZE); | |
9df15b49 | 569 | kunmap_atomic(pt_vaddr); |
6f1cc993 | 570 | pt_vaddr = NULL; |
07749ef3 | 571 | if (++pde == I915_PDES) { |
7ad47cf2 BW |
572 | pdpe++; |
573 | pde = 0; | |
574 | } | |
575 | pte = 0; | |
9df15b49 BW |
576 | } |
577 | } | |
fd1ab8f4 RB |
578 | if (pt_vaddr) { |
579 | if (!HAS_LLC(ppgtt->base.dev)) | |
580 | drm_clflush_virt_range(pt_vaddr, PAGE_SIZE); | |
6f1cc993 | 581 | kunmap_atomic(pt_vaddr); |
fd1ab8f4 | 582 | } |
9df15b49 BW |
583 | } |
584 | ||
06dc68d6 | 585 | static void gen8_free_page_tables(struct i915_page_directory_entry *pd, struct drm_device *dev) |
7ad47cf2 BW |
586 | { |
587 | int i; | |
588 | ||
06fda602 | 589 | if (!pd->page) |
7ad47cf2 BW |
590 | return; |
591 | ||
07749ef3 | 592 | for (i = 0; i < I915_PDES; i++) { |
06fda602 BW |
593 | if (WARN_ON(!pd->page_table[i])) |
594 | continue; | |
7ad47cf2 | 595 | |
06dc68d6 | 596 | unmap_and_free_pt(pd->page_table[i], dev); |
06fda602 BW |
597 | pd->page_table[i] = NULL; |
598 | } | |
d7b3de91 BW |
599 | } |
600 | ||
601 | static void gen8_ppgtt_free(struct i915_hw_ppgtt *ppgtt) | |
b45a6715 BW |
602 | { |
603 | int i; | |
604 | ||
7ad47cf2 | 605 | for (i = 0; i < ppgtt->num_pd_pages; i++) { |
06fda602 BW |
606 | if (WARN_ON(!ppgtt->pdp.page_directory[i])) |
607 | continue; | |
608 | ||
06dc68d6 | 609 | gen8_free_page_tables(ppgtt->pdp.page_directory[i], ppgtt->base.dev); |
06fda602 | 610 | unmap_and_free_pd(ppgtt->pdp.page_directory[i]); |
7ad47cf2 | 611 | } |
b45a6715 BW |
612 | } |
613 | ||
614 | static void gen8_ppgtt_unmap_pages(struct i915_hw_ppgtt *ppgtt) | |
615 | { | |
f3a964b9 | 616 | struct pci_dev *hwdev = ppgtt->base.dev->pdev; |
b45a6715 BW |
617 | int i, j; |
618 | ||
619 | for (i = 0; i < ppgtt->num_pd_pages; i++) { | |
620 | /* TODO: In the future we'll support sparse mappings, so this | |
621 | * will have to change. */ | |
06fda602 | 622 | if (!ppgtt->pdp.page_directory[i]->daddr) |
b45a6715 BW |
623 | continue; |
624 | ||
06fda602 | 625 | pci_unmap_page(hwdev, ppgtt->pdp.page_directory[i]->daddr, PAGE_SIZE, |
f3a964b9 | 626 | PCI_DMA_BIDIRECTIONAL); |
b45a6715 | 627 | |
07749ef3 | 628 | for (j = 0; j < I915_PDES; j++) { |
06fda602 BW |
629 | struct i915_page_directory_entry *pd = ppgtt->pdp.page_directory[i]; |
630 | struct i915_page_table_entry *pt; | |
631 | dma_addr_t addr; | |
632 | ||
633 | if (WARN_ON(!pd->page_table[j])) | |
634 | continue; | |
635 | ||
636 | pt = pd->page_table[j]; | |
637 | addr = pt->daddr; | |
638 | ||
b45a6715 | 639 | if (addr) |
f3a964b9 BW |
640 | pci_unmap_page(hwdev, addr, PAGE_SIZE, |
641 | PCI_DMA_BIDIRECTIONAL); | |
b45a6715 BW |
642 | } |
643 | } | |
644 | } | |
645 | ||
37aca44a BW |
646 | static void gen8_ppgtt_cleanup(struct i915_address_space *vm) |
647 | { | |
648 | struct i915_hw_ppgtt *ppgtt = | |
649 | container_of(vm, struct i915_hw_ppgtt, base); | |
37aca44a | 650 | |
b45a6715 BW |
651 | gen8_ppgtt_unmap_pages(ppgtt); |
652 | gen8_ppgtt_free(ppgtt); | |
37aca44a BW |
653 | } |
654 | ||
d7b3de91 | 655 | static int gen8_ppgtt_allocate_page_tables(struct i915_hw_ppgtt *ppgtt) |
bf2b4ed2 | 656 | { |
06fda602 | 657 | int i, ret; |
bf2b4ed2 | 658 | |
d7b3de91 | 659 | for (i = 0; i < ppgtt->num_pd_pages; i++) { |
06fda602 | 660 | ret = alloc_pt_range(ppgtt->pdp.page_directory[i], |
07749ef3 | 661 | 0, I915_PDES, ppgtt->base.dev); |
06fda602 BW |
662 | if (ret) |
663 | goto unwind_out; | |
7ad47cf2 BW |
664 | } |
665 | ||
bf2b4ed2 | 666 | return 0; |
7ad47cf2 BW |
667 | |
668 | unwind_out: | |
d7b3de91 | 669 | while (i--) |
06dc68d6 | 670 | gen8_free_page_tables(ppgtt->pdp.page_directory[i], ppgtt->base.dev); |
7ad47cf2 | 671 | |
d7b3de91 | 672 | return -ENOMEM; |
bf2b4ed2 BW |
673 | } |
674 | ||
d7b3de91 BW |
675 | static int gen8_ppgtt_allocate_page_directories(struct i915_hw_ppgtt *ppgtt, |
676 | const int max_pdp) | |
bf2b4ed2 BW |
677 | { |
678 | int i; | |
679 | ||
d7b3de91 | 680 | for (i = 0; i < max_pdp; i++) { |
06fda602 BW |
681 | ppgtt->pdp.page_directory[i] = alloc_pd_single(); |
682 | if (IS_ERR(ppgtt->pdp.page_directory[i])) | |
d7b3de91 | 683 | goto unwind_out; |
d7b3de91 BW |
684 | } |
685 | ||
686 | ppgtt->num_pd_pages = max_pdp; | |
76643600 | 687 | BUG_ON(ppgtt->num_pd_pages > GEN8_LEGACY_PDPES); |
bf2b4ed2 BW |
688 | |
689 | return 0; | |
d7b3de91 BW |
690 | |
691 | unwind_out: | |
06fda602 BW |
692 | while (i--) |
693 | unmap_and_free_pd(ppgtt->pdp.page_directory[i]); | |
d7b3de91 BW |
694 | |
695 | return -ENOMEM; | |
bf2b4ed2 BW |
696 | } |
697 | ||
698 | static int gen8_ppgtt_alloc(struct i915_hw_ppgtt *ppgtt, | |
699 | const int max_pdp) | |
700 | { | |
701 | int ret; | |
702 | ||
703 | ret = gen8_ppgtt_allocate_page_directories(ppgtt, max_pdp); | |
704 | if (ret) | |
705 | return ret; | |
706 | ||
d7b3de91 BW |
707 | ret = gen8_ppgtt_allocate_page_tables(ppgtt); |
708 | if (ret) | |
709 | goto err_out; | |
bf2b4ed2 | 710 | |
07749ef3 | 711 | ppgtt->num_pd_entries = max_pdp * I915_PDES; |
bf2b4ed2 | 712 | |
d7b3de91 | 713 | return 0; |
bf2b4ed2 | 714 | |
d7b3de91 BW |
715 | err_out: |
716 | gen8_ppgtt_free(ppgtt); | |
bf2b4ed2 BW |
717 | return ret; |
718 | } | |
719 | ||
720 | static int gen8_ppgtt_setup_page_directories(struct i915_hw_ppgtt *ppgtt, | |
721 | const int pd) | |
722 | { | |
723 | dma_addr_t pd_addr; | |
724 | int ret; | |
725 | ||
726 | pd_addr = pci_map_page(ppgtt->base.dev->pdev, | |
06fda602 | 727 | ppgtt->pdp.page_directory[pd]->page, 0, |
bf2b4ed2 BW |
728 | PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); |
729 | ||
730 | ret = pci_dma_mapping_error(ppgtt->base.dev->pdev, pd_addr); | |
731 | if (ret) | |
732 | return ret; | |
733 | ||
06fda602 | 734 | ppgtt->pdp.page_directory[pd]->daddr = pd_addr; |
bf2b4ed2 BW |
735 | |
736 | return 0; | |
737 | } | |
738 | ||
739 | static int gen8_ppgtt_setup_page_tables(struct i915_hw_ppgtt *ppgtt, | |
740 | const int pd, | |
741 | const int pt) | |
742 | { | |
743 | dma_addr_t pt_addr; | |
06fda602 BW |
744 | struct i915_page_directory_entry *pdir = ppgtt->pdp.page_directory[pd]; |
745 | struct i915_page_table_entry *ptab = pdir->page_table[pt]; | |
7324cc04 | 746 | struct page *p = ptab->page; |
bf2b4ed2 BW |
747 | int ret; |
748 | ||
bf2b4ed2 BW |
749 | pt_addr = pci_map_page(ppgtt->base.dev->pdev, |
750 | p, 0, PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); | |
751 | ret = pci_dma_mapping_error(ppgtt->base.dev->pdev, pt_addr); | |
752 | if (ret) | |
753 | return ret; | |
754 | ||
7324cc04 | 755 | ptab->daddr = pt_addr; |
bf2b4ed2 BW |
756 | |
757 | return 0; | |
758 | } | |
759 | ||
eb0b44ad | 760 | /* |
f3a964b9 BW |
761 | * GEN8 legacy ppgtt programming is accomplished through a max 4 PDP registers |
762 | * with a net effect resembling a 2-level page table in normal x86 terms. Each | |
763 | * PDP represents 1GB of memory 4 * 512 * 512 * 4096 = 4GB legacy 32b address | |
764 | * space. | |
37aca44a | 765 | * |
f3a964b9 BW |
766 | * FIXME: split allocation into smaller pieces. For now we only ever do this |
767 | * once, but with full PPGTT, the multiple contiguous allocations will be bad. | |
37aca44a | 768 | * TODO: Do something with the size parameter |
f3a964b9 | 769 | */ |
37aca44a BW |
770 | static int gen8_ppgtt_init(struct i915_hw_ppgtt *ppgtt, uint64_t size) |
771 | { | |
37aca44a | 772 | const int max_pdp = DIV_ROUND_UP(size, 1 << 30); |
07749ef3 | 773 | const int min_pt_pages = I915_PDES * max_pdp; |
f3a964b9 | 774 | int i, j, ret; |
37aca44a BW |
775 | |
776 | if (size % (1<<30)) | |
777 | DRM_INFO("Pages will be wasted unless GTT size (%llu) is divisible by 1GB\n", size); | |
778 | ||
2934368e MK |
779 | /* 1. Do all our allocations for page directories and page tables. |
780 | * We allocate more than was asked so that we can point the unused parts | |
781 | * to valid entries that point to scratch page. Dynamic page tables | |
782 | * will fix this eventually. | |
783 | */ | |
784 | ret = gen8_ppgtt_alloc(ppgtt, GEN8_LEGACY_PDPES); | |
bf2b4ed2 BW |
785 | if (ret) |
786 | return ret; | |
f3a964b9 | 787 | |
37aca44a | 788 | /* |
bf2b4ed2 | 789 | * 2. Create DMA mappings for the page directories and page tables. |
37aca44a | 790 | */ |
2934368e | 791 | for (i = 0; i < GEN8_LEGACY_PDPES; i++) { |
bf2b4ed2 | 792 | ret = gen8_ppgtt_setup_page_directories(ppgtt, i); |
f3a964b9 BW |
793 | if (ret) |
794 | goto bail; | |
37aca44a | 795 | |
07749ef3 | 796 | for (j = 0; j < I915_PDES; j++) { |
bf2b4ed2 | 797 | ret = gen8_ppgtt_setup_page_tables(ppgtt, i, j); |
f3a964b9 BW |
798 | if (ret) |
799 | goto bail; | |
37aca44a BW |
800 | } |
801 | } | |
802 | ||
f3a964b9 BW |
803 | /* |
804 | * 3. Map all the page directory entires to point to the page tables | |
805 | * we've allocated. | |
806 | * | |
807 | * For now, the PPGTT helper functions all require that the PDEs are | |
b1fe6673 | 808 | * plugged in correctly. So we do that now/here. For aliasing PPGTT, we |
f3a964b9 BW |
809 | * will never need to touch the PDEs again. |
810 | */ | |
2934368e | 811 | for (i = 0; i < GEN8_LEGACY_PDPES; i++) { |
06fda602 | 812 | struct i915_page_directory_entry *pd = ppgtt->pdp.page_directory[i]; |
07749ef3 | 813 | gen8_pde_t *pd_vaddr; |
06fda602 | 814 | pd_vaddr = kmap_atomic(ppgtt->pdp.page_directory[i]->page); |
07749ef3 | 815 | for (j = 0; j < I915_PDES; j++) { |
06fda602 BW |
816 | struct i915_page_table_entry *pt = pd->page_table[j]; |
817 | dma_addr_t addr = pt->daddr; | |
b1fe6673 BW |
818 | pd_vaddr[j] = gen8_pde_encode(ppgtt->base.dev, addr, |
819 | I915_CACHE_LLC); | |
820 | } | |
fd1ab8f4 RB |
821 | if (!HAS_LLC(ppgtt->base.dev)) |
822 | drm_clflush_virt_range(pd_vaddr, PAGE_SIZE); | |
b1fe6673 BW |
823 | kunmap_atomic(pd_vaddr); |
824 | } | |
825 | ||
f3a964b9 BW |
826 | ppgtt->switch_mm = gen8_mm_switch; |
827 | ppgtt->base.clear_range = gen8_ppgtt_clear_range; | |
828 | ppgtt->base.insert_entries = gen8_ppgtt_insert_entries; | |
829 | ppgtt->base.cleanup = gen8_ppgtt_cleanup; | |
830 | ppgtt->base.start = 0; | |
f3a964b9 | 831 | |
2934368e | 832 | /* This is the area that we advertise as usable for the caller */ |
07749ef3 | 833 | ppgtt->base.total = max_pdp * I915_PDES * GEN8_PTES * PAGE_SIZE; |
2934368e MK |
834 | |
835 | /* Set all ptes to a valid scratch page. Also above requested space */ | |
836 | ppgtt->base.clear_range(&ppgtt->base, 0, | |
07749ef3 | 837 | ppgtt->num_pd_pages * GEN8_PTES * PAGE_SIZE, |
2934368e | 838 | true); |
459108b8 | 839 | |
37aca44a BW |
840 | DRM_DEBUG_DRIVER("Allocated %d pages for page directories (%d wasted)\n", |
841 | ppgtt->num_pd_pages, ppgtt->num_pd_pages - max_pdp); | |
842 | DRM_DEBUG_DRIVER("Allocated %d pages for page tables (%lld wasted)\n", | |
5abbcca3 BW |
843 | ppgtt->num_pd_entries, |
844 | (ppgtt->num_pd_entries - min_pt_pages) + size % (1<<30)); | |
28cf5415 | 845 | return 0; |
37aca44a | 846 | |
f3a964b9 BW |
847 | bail: |
848 | gen8_ppgtt_unmap_pages(ppgtt); | |
849 | gen8_ppgtt_free(ppgtt); | |
37aca44a BW |
850 | return ret; |
851 | } | |
852 | ||
87d60b63 BW |
853 | static void gen6_dump_ppgtt(struct i915_hw_ppgtt *ppgtt, struct seq_file *m) |
854 | { | |
855 | struct drm_i915_private *dev_priv = ppgtt->base.dev->dev_private; | |
856 | struct i915_address_space *vm = &ppgtt->base; | |
07749ef3 MT |
857 | gen6_pte_t __iomem *pd_addr; |
858 | gen6_pte_t scratch_pte; | |
87d60b63 BW |
859 | uint32_t pd_entry; |
860 | int pte, pde; | |
861 | ||
24f3a8cf | 862 | scratch_pte = vm->pte_encode(vm->scratch.addr, I915_CACHE_LLC, true, 0); |
87d60b63 | 863 | |
07749ef3 MT |
864 | pd_addr = (gen6_pte_t __iomem *)dev_priv->gtt.gsm + |
865 | ppgtt->pd.pd_offset / sizeof(gen6_pte_t); | |
87d60b63 BW |
866 | |
867 | seq_printf(m, " VM %p (pd_offset %x-%x):\n", vm, | |
7324cc04 BW |
868 | ppgtt->pd.pd_offset, |
869 | ppgtt->pd.pd_offset + ppgtt->num_pd_entries); | |
87d60b63 BW |
870 | for (pde = 0; pde < ppgtt->num_pd_entries; pde++) { |
871 | u32 expected; | |
07749ef3 | 872 | gen6_pte_t *pt_vaddr; |
06fda602 | 873 | dma_addr_t pt_addr = ppgtt->pd.page_table[pde]->daddr; |
87d60b63 BW |
874 | pd_entry = readl(pd_addr + pde); |
875 | expected = (GEN6_PDE_ADDR_ENCODE(pt_addr) | GEN6_PDE_VALID); | |
876 | ||
877 | if (pd_entry != expected) | |
878 | seq_printf(m, "\tPDE #%d mismatch: Actual PDE: %x Expected PDE: %x\n", | |
879 | pde, | |
880 | pd_entry, | |
881 | expected); | |
882 | seq_printf(m, "\tPDE: %x\n", pd_entry); | |
883 | ||
06fda602 | 884 | pt_vaddr = kmap_atomic(ppgtt->pd.page_table[pde]->page); |
07749ef3 | 885 | for (pte = 0; pte < GEN6_PTES; pte+=4) { |
87d60b63 | 886 | unsigned long va = |
07749ef3 | 887 | (pde * PAGE_SIZE * GEN6_PTES) + |
87d60b63 BW |
888 | (pte * PAGE_SIZE); |
889 | int i; | |
890 | bool found = false; | |
891 | for (i = 0; i < 4; i++) | |
892 | if (pt_vaddr[pte + i] != scratch_pte) | |
893 | found = true; | |
894 | if (!found) | |
895 | continue; | |
896 | ||
897 | seq_printf(m, "\t\t0x%lx [%03d,%04d]: =", va, pde, pte); | |
898 | for (i = 0; i < 4; i++) { | |
899 | if (pt_vaddr[pte + i] != scratch_pte) | |
900 | seq_printf(m, " %08x", pt_vaddr[pte + i]); | |
901 | else | |
902 | seq_puts(m, " SCRATCH "); | |
903 | } | |
904 | seq_puts(m, "\n"); | |
905 | } | |
906 | kunmap_atomic(pt_vaddr); | |
907 | } | |
908 | } | |
909 | ||
678d96fb BW |
910 | /* Write pde (index) from the page directory @pd to the page table @pt */ |
911 | static void gen6_write_pde(struct i915_page_directory_entry *pd, | |
912 | const int pde, struct i915_page_table_entry *pt) | |
6197349b | 913 | { |
678d96fb BW |
914 | /* Caller needs to make sure the write completes if necessary */ |
915 | struct i915_hw_ppgtt *ppgtt = | |
916 | container_of(pd, struct i915_hw_ppgtt, pd); | |
917 | u32 pd_entry; | |
6197349b | 918 | |
678d96fb BW |
919 | pd_entry = GEN6_PDE_ADDR_ENCODE(pt->daddr); |
920 | pd_entry |= GEN6_PDE_VALID; | |
6197349b | 921 | |
678d96fb BW |
922 | writel(pd_entry, ppgtt->pd_addr + pde); |
923 | } | |
6197349b | 924 | |
678d96fb BW |
925 | /* Write all the page tables found in the ppgtt structure to incrementing page |
926 | * directories. */ | |
927 | static void gen6_write_page_range(struct drm_i915_private *dev_priv, | |
928 | struct i915_page_directory_entry *pd, | |
929 | uint32_t start, uint32_t length) | |
930 | { | |
931 | struct i915_page_table_entry *pt; | |
932 | uint32_t pde, temp; | |
933 | ||
934 | gen6_for_each_pde(pt, pd, start, length, temp, pde) | |
935 | gen6_write_pde(pd, pde, pt); | |
936 | ||
937 | /* Make sure write is complete before other code can use this page | |
938 | * table. Also require for WC mapped PTEs */ | |
939 | readl(dev_priv->gtt.gsm); | |
3e302542 BW |
940 | } |
941 | ||
b4a74e3a | 942 | static uint32_t get_pd_offset(struct i915_hw_ppgtt *ppgtt) |
3e302542 | 943 | { |
7324cc04 | 944 | BUG_ON(ppgtt->pd.pd_offset & 0x3f); |
b4a74e3a | 945 | |
7324cc04 | 946 | return (ppgtt->pd.pd_offset / 64) << 16; |
b4a74e3a BW |
947 | } |
948 | ||
90252e5c | 949 | static int hsw_mm_switch(struct i915_hw_ppgtt *ppgtt, |
6689c167 | 950 | struct intel_engine_cs *ring) |
90252e5c | 951 | { |
90252e5c BW |
952 | int ret; |
953 | ||
90252e5c BW |
954 | /* NB: TLBs must be flushed and invalidated before a switch */ |
955 | ret = ring->flush(ring, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS); | |
956 | if (ret) | |
957 | return ret; | |
958 | ||
959 | ret = intel_ring_begin(ring, 6); | |
960 | if (ret) | |
961 | return ret; | |
962 | ||
963 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(2)); | |
964 | intel_ring_emit(ring, RING_PP_DIR_DCLV(ring)); | |
965 | intel_ring_emit(ring, PP_DIR_DCLV_2G); | |
966 | intel_ring_emit(ring, RING_PP_DIR_BASE(ring)); | |
967 | intel_ring_emit(ring, get_pd_offset(ppgtt)); | |
968 | intel_ring_emit(ring, MI_NOOP); | |
969 | intel_ring_advance(ring); | |
970 | ||
971 | return 0; | |
972 | } | |
973 | ||
71ba2d64 YZ |
974 | static int vgpu_mm_switch(struct i915_hw_ppgtt *ppgtt, |
975 | struct intel_engine_cs *ring) | |
976 | { | |
977 | struct drm_i915_private *dev_priv = to_i915(ppgtt->base.dev); | |
978 | ||
979 | I915_WRITE(RING_PP_DIR_DCLV(ring), PP_DIR_DCLV_2G); | |
980 | I915_WRITE(RING_PP_DIR_BASE(ring), get_pd_offset(ppgtt)); | |
981 | return 0; | |
982 | } | |
983 | ||
48a10389 | 984 | static int gen7_mm_switch(struct i915_hw_ppgtt *ppgtt, |
6689c167 | 985 | struct intel_engine_cs *ring) |
48a10389 | 986 | { |
48a10389 BW |
987 | int ret; |
988 | ||
48a10389 BW |
989 | /* NB: TLBs must be flushed and invalidated before a switch */ |
990 | ret = ring->flush(ring, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS); | |
991 | if (ret) | |
992 | return ret; | |
993 | ||
994 | ret = intel_ring_begin(ring, 6); | |
995 | if (ret) | |
996 | return ret; | |
997 | ||
998 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(2)); | |
999 | intel_ring_emit(ring, RING_PP_DIR_DCLV(ring)); | |
1000 | intel_ring_emit(ring, PP_DIR_DCLV_2G); | |
1001 | intel_ring_emit(ring, RING_PP_DIR_BASE(ring)); | |
1002 | intel_ring_emit(ring, get_pd_offset(ppgtt)); | |
1003 | intel_ring_emit(ring, MI_NOOP); | |
1004 | intel_ring_advance(ring); | |
1005 | ||
90252e5c BW |
1006 | /* XXX: RCS is the only one to auto invalidate the TLBs? */ |
1007 | if (ring->id != RCS) { | |
1008 | ret = ring->flush(ring, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS); | |
1009 | if (ret) | |
1010 | return ret; | |
1011 | } | |
1012 | ||
48a10389 BW |
1013 | return 0; |
1014 | } | |
1015 | ||
eeb9488e | 1016 | static int gen6_mm_switch(struct i915_hw_ppgtt *ppgtt, |
6689c167 | 1017 | struct intel_engine_cs *ring) |
eeb9488e BW |
1018 | { |
1019 | struct drm_device *dev = ppgtt->base.dev; | |
1020 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1021 | ||
48a10389 | 1022 | |
eeb9488e BW |
1023 | I915_WRITE(RING_PP_DIR_DCLV(ring), PP_DIR_DCLV_2G); |
1024 | I915_WRITE(RING_PP_DIR_BASE(ring), get_pd_offset(ppgtt)); | |
1025 | ||
1026 | POSTING_READ(RING_PP_DIR_DCLV(ring)); | |
1027 | ||
1028 | return 0; | |
1029 | } | |
1030 | ||
82460d97 | 1031 | static void gen8_ppgtt_enable(struct drm_device *dev) |
eeb9488e | 1032 | { |
eeb9488e | 1033 | struct drm_i915_private *dev_priv = dev->dev_private; |
a4872ba6 | 1034 | struct intel_engine_cs *ring; |
82460d97 | 1035 | int j; |
3e302542 | 1036 | |
eeb9488e BW |
1037 | for_each_ring(ring, dev_priv, j) { |
1038 | I915_WRITE(RING_MODE_GEN7(ring), | |
1039 | _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE)); | |
eeb9488e | 1040 | } |
eeb9488e | 1041 | } |
6197349b | 1042 | |
82460d97 | 1043 | static void gen7_ppgtt_enable(struct drm_device *dev) |
3e302542 | 1044 | { |
50227e1c | 1045 | struct drm_i915_private *dev_priv = dev->dev_private; |
a4872ba6 | 1046 | struct intel_engine_cs *ring; |
b4a74e3a | 1047 | uint32_t ecochk, ecobits; |
3e302542 | 1048 | int i; |
6197349b | 1049 | |
b4a74e3a BW |
1050 | ecobits = I915_READ(GAC_ECO_BITS); |
1051 | I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_PPGTT_CACHE64B); | |
a65c2fcd | 1052 | |
b4a74e3a BW |
1053 | ecochk = I915_READ(GAM_ECOCHK); |
1054 | if (IS_HASWELL(dev)) { | |
1055 | ecochk |= ECOCHK_PPGTT_WB_HSW; | |
1056 | } else { | |
1057 | ecochk |= ECOCHK_PPGTT_LLC_IVB; | |
1058 | ecochk &= ~ECOCHK_PPGTT_GFDT_IVB; | |
1059 | } | |
1060 | I915_WRITE(GAM_ECOCHK, ecochk); | |
a65c2fcd | 1061 | |
b4a74e3a | 1062 | for_each_ring(ring, dev_priv, i) { |
6197349b | 1063 | /* GFX_MODE is per-ring on gen7+ */ |
b4a74e3a BW |
1064 | I915_WRITE(RING_MODE_GEN7(ring), |
1065 | _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE)); | |
6197349b | 1066 | } |
b4a74e3a | 1067 | } |
6197349b | 1068 | |
82460d97 | 1069 | static void gen6_ppgtt_enable(struct drm_device *dev) |
b4a74e3a | 1070 | { |
50227e1c | 1071 | struct drm_i915_private *dev_priv = dev->dev_private; |
b4a74e3a | 1072 | uint32_t ecochk, gab_ctl, ecobits; |
a65c2fcd | 1073 | |
b4a74e3a BW |
1074 | ecobits = I915_READ(GAC_ECO_BITS); |
1075 | I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_SNB_BIT | | |
1076 | ECOBITS_PPGTT_CACHE64B); | |
6197349b | 1077 | |
b4a74e3a BW |
1078 | gab_ctl = I915_READ(GAB_CTL); |
1079 | I915_WRITE(GAB_CTL, gab_ctl | GAB_CTL_CONT_AFTER_PAGEFAULT); | |
1080 | ||
1081 | ecochk = I915_READ(GAM_ECOCHK); | |
1082 | I915_WRITE(GAM_ECOCHK, ecochk | ECOCHK_SNB_BIT | ECOCHK_PPGTT_CACHE64B); | |
1083 | ||
1084 | I915_WRITE(GFX_MODE, _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE)); | |
6197349b BW |
1085 | } |
1086 | ||
1d2a314c | 1087 | /* PPGTT support for Sandybdrige/Gen6 and later */ |
853ba5d2 | 1088 | static void gen6_ppgtt_clear_range(struct i915_address_space *vm, |
782f1495 BW |
1089 | uint64_t start, |
1090 | uint64_t length, | |
828c7908 | 1091 | bool use_scratch) |
1d2a314c | 1092 | { |
853ba5d2 BW |
1093 | struct i915_hw_ppgtt *ppgtt = |
1094 | container_of(vm, struct i915_hw_ppgtt, base); | |
07749ef3 | 1095 | gen6_pte_t *pt_vaddr, scratch_pte; |
782f1495 BW |
1096 | unsigned first_entry = start >> PAGE_SHIFT; |
1097 | unsigned num_entries = length >> PAGE_SHIFT; | |
07749ef3 MT |
1098 | unsigned act_pt = first_entry / GEN6_PTES; |
1099 | unsigned first_pte = first_entry % GEN6_PTES; | |
7bddb01f | 1100 | unsigned last_pte, i; |
1d2a314c | 1101 | |
24f3a8cf | 1102 | scratch_pte = vm->pte_encode(vm->scratch.addr, I915_CACHE_LLC, true, 0); |
1d2a314c | 1103 | |
7bddb01f DV |
1104 | while (num_entries) { |
1105 | last_pte = first_pte + num_entries; | |
07749ef3 MT |
1106 | if (last_pte > GEN6_PTES) |
1107 | last_pte = GEN6_PTES; | |
7bddb01f | 1108 | |
06fda602 | 1109 | pt_vaddr = kmap_atomic(ppgtt->pd.page_table[act_pt]->page); |
1d2a314c | 1110 | |
7bddb01f DV |
1111 | for (i = first_pte; i < last_pte; i++) |
1112 | pt_vaddr[i] = scratch_pte; | |
1d2a314c DV |
1113 | |
1114 | kunmap_atomic(pt_vaddr); | |
1d2a314c | 1115 | |
7bddb01f DV |
1116 | num_entries -= last_pte - first_pte; |
1117 | first_pte = 0; | |
a15326a5 | 1118 | act_pt++; |
7bddb01f | 1119 | } |
1d2a314c DV |
1120 | } |
1121 | ||
853ba5d2 | 1122 | static void gen6_ppgtt_insert_entries(struct i915_address_space *vm, |
def886c3 | 1123 | struct sg_table *pages, |
782f1495 | 1124 | uint64_t start, |
24f3a8cf | 1125 | enum i915_cache_level cache_level, u32 flags) |
def886c3 | 1126 | { |
853ba5d2 BW |
1127 | struct i915_hw_ppgtt *ppgtt = |
1128 | container_of(vm, struct i915_hw_ppgtt, base); | |
07749ef3 | 1129 | gen6_pte_t *pt_vaddr; |
782f1495 | 1130 | unsigned first_entry = start >> PAGE_SHIFT; |
07749ef3 MT |
1131 | unsigned act_pt = first_entry / GEN6_PTES; |
1132 | unsigned act_pte = first_entry % GEN6_PTES; | |
6e995e23 ID |
1133 | struct sg_page_iter sg_iter; |
1134 | ||
cc79714f | 1135 | pt_vaddr = NULL; |
6e995e23 | 1136 | for_each_sg_page(pages->sgl, &sg_iter, pages->nents, 0) { |
cc79714f | 1137 | if (pt_vaddr == NULL) |
06fda602 | 1138 | pt_vaddr = kmap_atomic(ppgtt->pd.page_table[act_pt]->page); |
6e995e23 | 1139 | |
cc79714f CW |
1140 | pt_vaddr[act_pte] = |
1141 | vm->pte_encode(sg_page_iter_dma_address(&sg_iter), | |
24f3a8cf AG |
1142 | cache_level, true, flags); |
1143 | ||
07749ef3 | 1144 | if (++act_pte == GEN6_PTES) { |
6e995e23 | 1145 | kunmap_atomic(pt_vaddr); |
cc79714f | 1146 | pt_vaddr = NULL; |
a15326a5 | 1147 | act_pt++; |
6e995e23 | 1148 | act_pte = 0; |
def886c3 | 1149 | } |
def886c3 | 1150 | } |
cc79714f CW |
1151 | if (pt_vaddr) |
1152 | kunmap_atomic(pt_vaddr); | |
def886c3 DV |
1153 | } |
1154 | ||
a00d825d | 1155 | static void gen6_ppgtt_unmap_pages(struct i915_hw_ppgtt *ppgtt) |
1d2a314c | 1156 | { |
3440d265 DV |
1157 | int i; |
1158 | ||
7324cc04 BW |
1159 | for (i = 0; i < ppgtt->num_pd_entries; i++) |
1160 | pci_unmap_page(ppgtt->base.dev->pdev, | |
06fda602 | 1161 | ppgtt->pd.page_table[i]->daddr, |
7324cc04 | 1162 | 4096, PCI_DMA_BIDIRECTIONAL); |
a00d825d BW |
1163 | } |
1164 | ||
563222a7 BW |
1165 | /* PDE TLBs are a pain invalidate pre GEN8. It requires a context reload. If we |
1166 | * are switching between contexts with the same LRCA, we also must do a force | |
1167 | * restore. | |
1168 | */ | |
1169 | static inline void mark_tlbs_dirty(struct i915_hw_ppgtt *ppgtt) | |
1170 | { | |
1171 | /* If current vm != vm, */ | |
1172 | ppgtt->pd_dirty_rings = INTEL_INFO(ppgtt->base.dev)->ring_mask; | |
1173 | } | |
1174 | ||
678d96fb BW |
1175 | static int gen6_alloc_va_range(struct i915_address_space *vm, |
1176 | uint64_t start, uint64_t length) | |
1177 | { | |
1178 | struct i915_hw_ppgtt *ppgtt = | |
1179 | container_of(vm, struct i915_hw_ppgtt, base); | |
1180 | struct i915_page_table_entry *pt; | |
1181 | uint32_t pde, temp; | |
1182 | ||
1183 | gen6_for_each_pde(pt, &ppgtt->pd, start, length, temp, pde) { | |
1184 | DECLARE_BITMAP(tmp_bitmap, GEN6_PTES); | |
1185 | ||
1186 | bitmap_zero(tmp_bitmap, GEN6_PTES); | |
1187 | bitmap_set(tmp_bitmap, gen6_pte_index(start), | |
1188 | gen6_pte_count(start, length)); | |
1189 | ||
1190 | bitmap_or(pt->used_ptes, pt->used_ptes, tmp_bitmap, | |
1191 | GEN6_PTES); | |
1192 | } | |
1193 | ||
563222a7 | 1194 | mark_tlbs_dirty(ppgtt); |
678d96fb BW |
1195 | return 0; |
1196 | } | |
1197 | ||
a00d825d BW |
1198 | static void gen6_ppgtt_free(struct i915_hw_ppgtt *ppgtt) |
1199 | { | |
1200 | int i; | |
3440d265 | 1201 | |
3440d265 | 1202 | for (i = 0; i < ppgtt->num_pd_entries; i++) |
06dc68d6 | 1203 | unmap_and_free_pt(ppgtt->pd.page_table[i], ppgtt->base.dev); |
06fda602 BW |
1204 | |
1205 | unmap_and_free_pd(&ppgtt->pd); | |
3440d265 DV |
1206 | } |
1207 | ||
a00d825d BW |
1208 | static void gen6_ppgtt_cleanup(struct i915_address_space *vm) |
1209 | { | |
1210 | struct i915_hw_ppgtt *ppgtt = | |
1211 | container_of(vm, struct i915_hw_ppgtt, base); | |
1212 | ||
a00d825d BW |
1213 | drm_mm_remove_node(&ppgtt->node); |
1214 | ||
1215 | gen6_ppgtt_unmap_pages(ppgtt); | |
1216 | gen6_ppgtt_free(ppgtt); | |
1217 | } | |
1218 | ||
b146520f | 1219 | static int gen6_ppgtt_allocate_page_directories(struct i915_hw_ppgtt *ppgtt) |
3440d265 | 1220 | { |
853ba5d2 | 1221 | struct drm_device *dev = ppgtt->base.dev; |
1d2a314c | 1222 | struct drm_i915_private *dev_priv = dev->dev_private; |
e3cc1995 | 1223 | bool retried = false; |
b146520f | 1224 | int ret; |
1d2a314c | 1225 | |
c8d4c0d6 BW |
1226 | /* PPGTT PDEs reside in the GGTT and consists of 512 entries. The |
1227 | * allocator works in address space sizes, so it's multiplied by page | |
1228 | * size. We allocate at the top of the GTT to avoid fragmentation. | |
1229 | */ | |
1230 | BUG_ON(!drm_mm_initialized(&dev_priv->gtt.base.mm)); | |
e3cc1995 | 1231 | alloc: |
c8d4c0d6 BW |
1232 | ret = drm_mm_insert_node_in_range_generic(&dev_priv->gtt.base.mm, |
1233 | &ppgtt->node, GEN6_PD_SIZE, | |
1234 | GEN6_PD_ALIGN, 0, | |
1235 | 0, dev_priv->gtt.base.total, | |
3e8b5ae9 | 1236 | DRM_MM_TOPDOWN); |
e3cc1995 BW |
1237 | if (ret == -ENOSPC && !retried) { |
1238 | ret = i915_gem_evict_something(dev, &dev_priv->gtt.base, | |
1239 | GEN6_PD_SIZE, GEN6_PD_ALIGN, | |
d23db88c CW |
1240 | I915_CACHE_NONE, |
1241 | 0, dev_priv->gtt.base.total, | |
1242 | 0); | |
e3cc1995 | 1243 | if (ret) |
678d96fb | 1244 | goto err_out; |
e3cc1995 BW |
1245 | |
1246 | retried = true; | |
1247 | goto alloc; | |
1248 | } | |
c8d4c0d6 | 1249 | |
c8c26622 | 1250 | if (ret) |
678d96fb BW |
1251 | goto err_out; |
1252 | ||
c8c26622 | 1253 | |
c8d4c0d6 BW |
1254 | if (ppgtt->node.start < dev_priv->gtt.mappable_end) |
1255 | DRM_DEBUG("Forced to use aperture for PDEs\n"); | |
1d2a314c | 1256 | |
07749ef3 | 1257 | ppgtt->num_pd_entries = I915_PDES; |
c8c26622 | 1258 | return 0; |
678d96fb BW |
1259 | |
1260 | err_out: | |
1261 | return ret; | |
b146520f BW |
1262 | } |
1263 | ||
b146520f BW |
1264 | static int gen6_ppgtt_alloc(struct i915_hw_ppgtt *ppgtt) |
1265 | { | |
1266 | int ret; | |
1267 | ||
1268 | ret = gen6_ppgtt_allocate_page_directories(ppgtt); | |
1269 | if (ret) | |
1270 | return ret; | |
1271 | ||
06dc68d6 MT |
1272 | ret = alloc_pt_range(&ppgtt->pd, 0, ppgtt->num_pd_entries, |
1273 | ppgtt->base.dev); | |
1274 | ||
b146520f BW |
1275 | if (ret) { |
1276 | drm_mm_remove_node(&ppgtt->node); | |
1277 | return ret; | |
1d2a314c DV |
1278 | } |
1279 | ||
b146520f BW |
1280 | return 0; |
1281 | } | |
1282 | ||
b146520f BW |
1283 | static int gen6_ppgtt_init(struct i915_hw_ppgtt *ppgtt) |
1284 | { | |
1285 | struct drm_device *dev = ppgtt->base.dev; | |
1286 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1287 | int ret; | |
1288 | ||
1289 | ppgtt->base.pte_encode = dev_priv->gtt.base.pte_encode; | |
1290 | if (IS_GEN6(dev)) { | |
b146520f BW |
1291 | ppgtt->switch_mm = gen6_mm_switch; |
1292 | } else if (IS_HASWELL(dev)) { | |
b146520f BW |
1293 | ppgtt->switch_mm = hsw_mm_switch; |
1294 | } else if (IS_GEN7(dev)) { | |
b146520f BW |
1295 | ppgtt->switch_mm = gen7_mm_switch; |
1296 | } else | |
1297 | BUG(); | |
1298 | ||
71ba2d64 YZ |
1299 | if (intel_vgpu_active(dev)) |
1300 | ppgtt->switch_mm = vgpu_mm_switch; | |
1301 | ||
b146520f BW |
1302 | ret = gen6_ppgtt_alloc(ppgtt); |
1303 | if (ret) | |
1304 | return ret; | |
1305 | ||
678d96fb | 1306 | ppgtt->base.allocate_va_range = gen6_alloc_va_range; |
b146520f BW |
1307 | ppgtt->base.clear_range = gen6_ppgtt_clear_range; |
1308 | ppgtt->base.insert_entries = gen6_ppgtt_insert_entries; | |
1309 | ppgtt->base.cleanup = gen6_ppgtt_cleanup; | |
b146520f | 1310 | ppgtt->base.start = 0; |
07749ef3 | 1311 | ppgtt->base.total = ppgtt->num_pd_entries * GEN6_PTES * PAGE_SIZE; |
87d60b63 | 1312 | ppgtt->debug_dump = gen6_dump_ppgtt; |
1d2a314c | 1313 | |
7324cc04 | 1314 | ppgtt->pd.pd_offset = |
07749ef3 | 1315 | ppgtt->node.start / PAGE_SIZE * sizeof(gen6_pte_t); |
1d2a314c | 1316 | |
678d96fb BW |
1317 | ppgtt->pd_addr = (gen6_pte_t __iomem *)dev_priv->gtt.gsm + |
1318 | ppgtt->pd.pd_offset / sizeof(gen6_pte_t); | |
1319 | ||
b146520f | 1320 | ppgtt->base.clear_range(&ppgtt->base, 0, ppgtt->base.total, true); |
1d2a314c | 1321 | |
678d96fb BW |
1322 | gen6_write_page_range(dev_priv, &ppgtt->pd, 0, ppgtt->base.total); |
1323 | ||
440fd528 | 1324 | DRM_DEBUG_DRIVER("Allocated pde space (%lldM) at GTT entry: %llx\n", |
b146520f BW |
1325 | ppgtt->node.size >> 20, |
1326 | ppgtt->node.start / PAGE_SIZE); | |
3440d265 | 1327 | |
fa76da34 | 1328 | DRM_DEBUG("Adding PPGTT at offset %x\n", |
7324cc04 | 1329 | ppgtt->pd.pd_offset << 10); |
fa76da34 | 1330 | |
b146520f | 1331 | return 0; |
3440d265 DV |
1332 | } |
1333 | ||
fa76da34 | 1334 | static int __hw_ppgtt_init(struct drm_device *dev, struct i915_hw_ppgtt *ppgtt) |
3440d265 DV |
1335 | { |
1336 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3440d265 | 1337 | |
853ba5d2 | 1338 | ppgtt->base.dev = dev; |
8407bb91 | 1339 | ppgtt->base.scratch = dev_priv->gtt.base.scratch; |
3440d265 | 1340 | |
3ed124b2 | 1341 | if (INTEL_INFO(dev)->gen < 8) |
fa76da34 | 1342 | return gen6_ppgtt_init(ppgtt); |
3ed124b2 | 1343 | else |
1eb0f006 | 1344 | return gen8_ppgtt_init(ppgtt, dev_priv->gtt.base.total); |
fa76da34 DV |
1345 | } |
1346 | int i915_ppgtt_init(struct drm_device *dev, struct i915_hw_ppgtt *ppgtt) | |
1347 | { | |
1348 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1349 | int ret = 0; | |
3ed124b2 | 1350 | |
fa76da34 DV |
1351 | ret = __hw_ppgtt_init(dev, ppgtt); |
1352 | if (ret == 0) { | |
c7c48dfd | 1353 | kref_init(&ppgtt->ref); |
93bd8649 BW |
1354 | drm_mm_init(&ppgtt->base.mm, ppgtt->base.start, |
1355 | ppgtt->base.total); | |
7e0d96bc | 1356 | i915_init_vm(dev_priv, &ppgtt->base); |
93bd8649 | 1357 | } |
1d2a314c DV |
1358 | |
1359 | return ret; | |
1360 | } | |
1361 | ||
82460d97 DV |
1362 | int i915_ppgtt_init_hw(struct drm_device *dev) |
1363 | { | |
1364 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1365 | struct intel_engine_cs *ring; | |
1366 | struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt; | |
1367 | int i, ret = 0; | |
1368 | ||
671b5013 TD |
1369 | /* In the case of execlists, PPGTT is enabled by the context descriptor |
1370 | * and the PDPs are contained within the context itself. We don't | |
1371 | * need to do anything here. */ | |
1372 | if (i915.enable_execlists) | |
1373 | return 0; | |
1374 | ||
82460d97 DV |
1375 | if (!USES_PPGTT(dev)) |
1376 | return 0; | |
1377 | ||
1378 | if (IS_GEN6(dev)) | |
1379 | gen6_ppgtt_enable(dev); | |
1380 | else if (IS_GEN7(dev)) | |
1381 | gen7_ppgtt_enable(dev); | |
1382 | else if (INTEL_INFO(dev)->gen >= 8) | |
1383 | gen8_ppgtt_enable(dev); | |
1384 | else | |
5f77eeb0 | 1385 | MISSING_CASE(INTEL_INFO(dev)->gen); |
82460d97 DV |
1386 | |
1387 | if (ppgtt) { | |
1388 | for_each_ring(ring, dev_priv, i) { | |
6689c167 | 1389 | ret = ppgtt->switch_mm(ppgtt, ring); |
82460d97 DV |
1390 | if (ret != 0) |
1391 | return ret; | |
7e0d96bc | 1392 | } |
93bd8649 | 1393 | } |
1d2a314c DV |
1394 | |
1395 | return ret; | |
1396 | } | |
4d884705 DV |
1397 | struct i915_hw_ppgtt * |
1398 | i915_ppgtt_create(struct drm_device *dev, struct drm_i915_file_private *fpriv) | |
1399 | { | |
1400 | struct i915_hw_ppgtt *ppgtt; | |
1401 | int ret; | |
1402 | ||
1403 | ppgtt = kzalloc(sizeof(*ppgtt), GFP_KERNEL); | |
1404 | if (!ppgtt) | |
1405 | return ERR_PTR(-ENOMEM); | |
1406 | ||
1407 | ret = i915_ppgtt_init(dev, ppgtt); | |
1408 | if (ret) { | |
1409 | kfree(ppgtt); | |
1410 | return ERR_PTR(ret); | |
1411 | } | |
1412 | ||
1413 | ppgtt->file_priv = fpriv; | |
1414 | ||
198c974d DCS |
1415 | trace_i915_ppgtt_create(&ppgtt->base); |
1416 | ||
4d884705 DV |
1417 | return ppgtt; |
1418 | } | |
1419 | ||
ee960be7 DV |
1420 | void i915_ppgtt_release(struct kref *kref) |
1421 | { | |
1422 | struct i915_hw_ppgtt *ppgtt = | |
1423 | container_of(kref, struct i915_hw_ppgtt, ref); | |
1424 | ||
198c974d DCS |
1425 | trace_i915_ppgtt_release(&ppgtt->base); |
1426 | ||
ee960be7 DV |
1427 | /* vmas should already be unbound */ |
1428 | WARN_ON(!list_empty(&ppgtt->base.active_list)); | |
1429 | WARN_ON(!list_empty(&ppgtt->base.inactive_list)); | |
1430 | ||
19dd120c DV |
1431 | list_del(&ppgtt->base.global_link); |
1432 | drm_mm_takedown(&ppgtt->base.mm); | |
1433 | ||
ee960be7 DV |
1434 | ppgtt->base.cleanup(&ppgtt->base); |
1435 | kfree(ppgtt); | |
1436 | } | |
1d2a314c | 1437 | |
7e0d96bc | 1438 | static void |
6f65e29a BW |
1439 | ppgtt_bind_vma(struct i915_vma *vma, |
1440 | enum i915_cache_level cache_level, | |
1441 | u32 flags) | |
1d2a314c | 1442 | { |
24f3a8cf AG |
1443 | /* Currently applicable only to VLV */ |
1444 | if (vma->obj->gt_ro) | |
1445 | flags |= PTE_READ_ONLY; | |
1446 | ||
782f1495 | 1447 | vma->vm->insert_entries(vma->vm, vma->obj->pages, vma->node.start, |
24f3a8cf | 1448 | cache_level, flags); |
1d2a314c DV |
1449 | } |
1450 | ||
7e0d96bc | 1451 | static void ppgtt_unbind_vma(struct i915_vma *vma) |
7bddb01f | 1452 | { |
6f65e29a | 1453 | vma->vm->clear_range(vma->vm, |
782f1495 BW |
1454 | vma->node.start, |
1455 | vma->obj->base.size, | |
6f65e29a | 1456 | true); |
7bddb01f DV |
1457 | } |
1458 | ||
a81cc00c BW |
1459 | extern int intel_iommu_gfx_mapped; |
1460 | /* Certain Gen5 chipsets require require idling the GPU before | |
1461 | * unmapping anything from the GTT when VT-d is enabled. | |
1462 | */ | |
1463 | static inline bool needs_idle_maps(struct drm_device *dev) | |
1464 | { | |
1465 | #ifdef CONFIG_INTEL_IOMMU | |
1466 | /* Query intel_iommu to see if we need the workaround. Presumably that | |
1467 | * was loaded first. | |
1468 | */ | |
1469 | if (IS_GEN5(dev) && IS_MOBILE(dev) && intel_iommu_gfx_mapped) | |
1470 | return true; | |
1471 | #endif | |
1472 | return false; | |
1473 | } | |
1474 | ||
5c042287 BW |
1475 | static bool do_idling(struct drm_i915_private *dev_priv) |
1476 | { | |
1477 | bool ret = dev_priv->mm.interruptible; | |
1478 | ||
a81cc00c | 1479 | if (unlikely(dev_priv->gtt.do_idle_maps)) { |
5c042287 | 1480 | dev_priv->mm.interruptible = false; |
b2da9fe5 | 1481 | if (i915_gpu_idle(dev_priv->dev)) { |
5c042287 BW |
1482 | DRM_ERROR("Couldn't idle GPU\n"); |
1483 | /* Wait a bit, in hopes it avoids the hang */ | |
1484 | udelay(10); | |
1485 | } | |
1486 | } | |
1487 | ||
1488 | return ret; | |
1489 | } | |
1490 | ||
1491 | static void undo_idling(struct drm_i915_private *dev_priv, bool interruptible) | |
1492 | { | |
a81cc00c | 1493 | if (unlikely(dev_priv->gtt.do_idle_maps)) |
5c042287 BW |
1494 | dev_priv->mm.interruptible = interruptible; |
1495 | } | |
1496 | ||
828c7908 BW |
1497 | void i915_check_and_clear_faults(struct drm_device *dev) |
1498 | { | |
1499 | struct drm_i915_private *dev_priv = dev->dev_private; | |
a4872ba6 | 1500 | struct intel_engine_cs *ring; |
828c7908 BW |
1501 | int i; |
1502 | ||
1503 | if (INTEL_INFO(dev)->gen < 6) | |
1504 | return; | |
1505 | ||
1506 | for_each_ring(ring, dev_priv, i) { | |
1507 | u32 fault_reg; | |
1508 | fault_reg = I915_READ(RING_FAULT_REG(ring)); | |
1509 | if (fault_reg & RING_FAULT_VALID) { | |
1510 | DRM_DEBUG_DRIVER("Unexpected fault\n" | |
59a5d290 | 1511 | "\tAddr: 0x%08lx\n" |
828c7908 BW |
1512 | "\tAddress space: %s\n" |
1513 | "\tSource ID: %d\n" | |
1514 | "\tType: %d\n", | |
1515 | fault_reg & PAGE_MASK, | |
1516 | fault_reg & RING_FAULT_GTTSEL_MASK ? "GGTT" : "PPGTT", | |
1517 | RING_FAULT_SRCID(fault_reg), | |
1518 | RING_FAULT_FAULT_TYPE(fault_reg)); | |
1519 | I915_WRITE(RING_FAULT_REG(ring), | |
1520 | fault_reg & ~RING_FAULT_VALID); | |
1521 | } | |
1522 | } | |
1523 | POSTING_READ(RING_FAULT_REG(&dev_priv->ring[RCS])); | |
1524 | } | |
1525 | ||
91e56499 CW |
1526 | static void i915_ggtt_flush(struct drm_i915_private *dev_priv) |
1527 | { | |
1528 | if (INTEL_INFO(dev_priv->dev)->gen < 6) { | |
1529 | intel_gtt_chipset_flush(); | |
1530 | } else { | |
1531 | I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN); | |
1532 | POSTING_READ(GFX_FLSH_CNTL_GEN6); | |
1533 | } | |
1534 | } | |
1535 | ||
828c7908 BW |
1536 | void i915_gem_suspend_gtt_mappings(struct drm_device *dev) |
1537 | { | |
1538 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1539 | ||
1540 | /* Don't bother messing with faults pre GEN6 as we have little | |
1541 | * documentation supporting that it's a good idea. | |
1542 | */ | |
1543 | if (INTEL_INFO(dev)->gen < 6) | |
1544 | return; | |
1545 | ||
1546 | i915_check_and_clear_faults(dev); | |
1547 | ||
1548 | dev_priv->gtt.base.clear_range(&dev_priv->gtt.base, | |
782f1495 BW |
1549 | dev_priv->gtt.base.start, |
1550 | dev_priv->gtt.base.total, | |
e568af1c | 1551 | true); |
91e56499 CW |
1552 | |
1553 | i915_ggtt_flush(dev_priv); | |
828c7908 BW |
1554 | } |
1555 | ||
76aaf220 DV |
1556 | void i915_gem_restore_gtt_mappings(struct drm_device *dev) |
1557 | { | |
1558 | struct drm_i915_private *dev_priv = dev->dev_private; | |
05394f39 | 1559 | struct drm_i915_gem_object *obj; |
80da2161 | 1560 | struct i915_address_space *vm; |
76aaf220 | 1561 | |
828c7908 BW |
1562 | i915_check_and_clear_faults(dev); |
1563 | ||
bee4a186 | 1564 | /* First fill our portion of the GTT with scratch pages */ |
853ba5d2 | 1565 | dev_priv->gtt.base.clear_range(&dev_priv->gtt.base, |
782f1495 BW |
1566 | dev_priv->gtt.base.start, |
1567 | dev_priv->gtt.base.total, | |
828c7908 | 1568 | true); |
bee4a186 | 1569 | |
35c20a60 | 1570 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) { |
6f65e29a BW |
1571 | struct i915_vma *vma = i915_gem_obj_to_vma(obj, |
1572 | &dev_priv->gtt.base); | |
1573 | if (!vma) | |
1574 | continue; | |
1575 | ||
2c22569b | 1576 | i915_gem_clflush_object(obj, obj->pin_display); |
6f65e29a BW |
1577 | /* The bind_vma code tries to be smart about tracking mappings. |
1578 | * Unfortunately above, we've just wiped out the mappings | |
1579 | * without telling our object about it. So we need to fake it. | |
fe14d5f4 TU |
1580 | * |
1581 | * Bind is not expected to fail since this is only called on | |
1582 | * resume and assumption is all requirements exist already. | |
6f65e29a | 1583 | */ |
aff43766 | 1584 | vma->bound &= ~GLOBAL_BIND; |
fe14d5f4 | 1585 | WARN_ON(i915_vma_bind(vma, obj->cache_level, GLOBAL_BIND)); |
76aaf220 DV |
1586 | } |
1587 | ||
80da2161 | 1588 | |
a2319c08 | 1589 | if (INTEL_INFO(dev)->gen >= 8) { |
ee0ce478 VS |
1590 | if (IS_CHERRYVIEW(dev)) |
1591 | chv_setup_private_ppat(dev_priv); | |
1592 | else | |
1593 | bdw_setup_private_ppat(dev_priv); | |
1594 | ||
80da2161 | 1595 | return; |
a2319c08 | 1596 | } |
80da2161 | 1597 | |
678d96fb BW |
1598 | if (USES_PPGTT(dev)) { |
1599 | list_for_each_entry(vm, &dev_priv->vm_list, global_link) { | |
1600 | /* TODO: Perhaps it shouldn't be gen6 specific */ | |
1601 | ||
1602 | struct i915_hw_ppgtt *ppgtt = | |
1603 | container_of(vm, struct i915_hw_ppgtt, | |
1604 | base); | |
80da2161 | 1605 | |
678d96fb BW |
1606 | if (i915_is_ggtt(vm)) |
1607 | ppgtt = dev_priv->mm.aliasing_ppgtt; | |
1608 | ||
1609 | gen6_write_page_range(dev_priv, &ppgtt->pd, | |
1610 | 0, ppgtt->base.total); | |
1611 | } | |
76aaf220 DV |
1612 | } |
1613 | ||
91e56499 | 1614 | i915_ggtt_flush(dev_priv); |
76aaf220 | 1615 | } |
7c2e6fdf | 1616 | |
74163907 | 1617 | int i915_gem_gtt_prepare_object(struct drm_i915_gem_object *obj) |
7c2e6fdf | 1618 | { |
9da3da66 | 1619 | if (obj->has_dma_mapping) |
74163907 | 1620 | return 0; |
9da3da66 CW |
1621 | |
1622 | if (!dma_map_sg(&obj->base.dev->pdev->dev, | |
1623 | obj->pages->sgl, obj->pages->nents, | |
1624 | PCI_DMA_BIDIRECTIONAL)) | |
1625 | return -ENOSPC; | |
1626 | ||
1627 | return 0; | |
7c2e6fdf DV |
1628 | } |
1629 | ||
07749ef3 | 1630 | static inline void gen8_set_pte(void __iomem *addr, gen8_pte_t pte) |
94ec8f61 BW |
1631 | { |
1632 | #ifdef writeq | |
1633 | writeq(pte, addr); | |
1634 | #else | |
1635 | iowrite32((u32)pte, addr); | |
1636 | iowrite32(pte >> 32, addr + 4); | |
1637 | #endif | |
1638 | } | |
1639 | ||
1640 | static void gen8_ggtt_insert_entries(struct i915_address_space *vm, | |
1641 | struct sg_table *st, | |
782f1495 | 1642 | uint64_t start, |
24f3a8cf | 1643 | enum i915_cache_level level, u32 unused) |
94ec8f61 BW |
1644 | { |
1645 | struct drm_i915_private *dev_priv = vm->dev->dev_private; | |
782f1495 | 1646 | unsigned first_entry = start >> PAGE_SHIFT; |
07749ef3 MT |
1647 | gen8_pte_t __iomem *gtt_entries = |
1648 | (gen8_pte_t __iomem *)dev_priv->gtt.gsm + first_entry; | |
94ec8f61 BW |
1649 | int i = 0; |
1650 | struct sg_page_iter sg_iter; | |
57007df7 | 1651 | dma_addr_t addr = 0; /* shut up gcc */ |
94ec8f61 BW |
1652 | |
1653 | for_each_sg_page(st->sgl, &sg_iter, st->nents, 0) { | |
1654 | addr = sg_dma_address(sg_iter.sg) + | |
1655 | (sg_iter.sg_pgoffset << PAGE_SHIFT); | |
1656 | gen8_set_pte(>t_entries[i], | |
1657 | gen8_pte_encode(addr, level, true)); | |
1658 | i++; | |
1659 | } | |
1660 | ||
1661 | /* | |
1662 | * XXX: This serves as a posting read to make sure that the PTE has | |
1663 | * actually been updated. There is some concern that even though | |
1664 | * registers and PTEs are within the same BAR that they are potentially | |
1665 | * of NUMA access patterns. Therefore, even with the way we assume | |
1666 | * hardware should work, we must keep this posting read for paranoia. | |
1667 | */ | |
1668 | if (i != 0) | |
1669 | WARN_ON(readq(>t_entries[i-1]) | |
1670 | != gen8_pte_encode(addr, level, true)); | |
1671 | ||
94ec8f61 BW |
1672 | /* This next bit makes the above posting read even more important. We |
1673 | * want to flush the TLBs only after we're certain all the PTE updates | |
1674 | * have finished. | |
1675 | */ | |
1676 | I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN); | |
1677 | POSTING_READ(GFX_FLSH_CNTL_GEN6); | |
94ec8f61 BW |
1678 | } |
1679 | ||
e76e9aeb BW |
1680 | /* |
1681 | * Binds an object into the global gtt with the specified cache level. The object | |
1682 | * will be accessible to the GPU via commands whose operands reference offsets | |
1683 | * within the global GTT as well as accessible by the GPU through the GMADR | |
1684 | * mapped BAR (dev_priv->mm.gtt->gtt). | |
1685 | */ | |
853ba5d2 | 1686 | static void gen6_ggtt_insert_entries(struct i915_address_space *vm, |
7faf1ab2 | 1687 | struct sg_table *st, |
782f1495 | 1688 | uint64_t start, |
24f3a8cf | 1689 | enum i915_cache_level level, u32 flags) |
e76e9aeb | 1690 | { |
853ba5d2 | 1691 | struct drm_i915_private *dev_priv = vm->dev->dev_private; |
782f1495 | 1692 | unsigned first_entry = start >> PAGE_SHIFT; |
07749ef3 MT |
1693 | gen6_pte_t __iomem *gtt_entries = |
1694 | (gen6_pte_t __iomem *)dev_priv->gtt.gsm + first_entry; | |
6e995e23 ID |
1695 | int i = 0; |
1696 | struct sg_page_iter sg_iter; | |
57007df7 | 1697 | dma_addr_t addr = 0; |
e76e9aeb | 1698 | |
6e995e23 | 1699 | for_each_sg_page(st->sgl, &sg_iter, st->nents, 0) { |
2db76d7c | 1700 | addr = sg_page_iter_dma_address(&sg_iter); |
24f3a8cf | 1701 | iowrite32(vm->pte_encode(addr, level, true, flags), >t_entries[i]); |
6e995e23 | 1702 | i++; |
e76e9aeb BW |
1703 | } |
1704 | ||
e76e9aeb BW |
1705 | /* XXX: This serves as a posting read to make sure that the PTE has |
1706 | * actually been updated. There is some concern that even though | |
1707 | * registers and PTEs are within the same BAR that they are potentially | |
1708 | * of NUMA access patterns. Therefore, even with the way we assume | |
1709 | * hardware should work, we must keep this posting read for paranoia. | |
1710 | */ | |
57007df7 PM |
1711 | if (i != 0) { |
1712 | unsigned long gtt = readl(>t_entries[i-1]); | |
1713 | WARN_ON(gtt != vm->pte_encode(addr, level, true, flags)); | |
1714 | } | |
0f9b91c7 BW |
1715 | |
1716 | /* This next bit makes the above posting read even more important. We | |
1717 | * want to flush the TLBs only after we're certain all the PTE updates | |
1718 | * have finished. | |
1719 | */ | |
1720 | I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN); | |
1721 | POSTING_READ(GFX_FLSH_CNTL_GEN6); | |
e76e9aeb BW |
1722 | } |
1723 | ||
94ec8f61 | 1724 | static void gen8_ggtt_clear_range(struct i915_address_space *vm, |
782f1495 BW |
1725 | uint64_t start, |
1726 | uint64_t length, | |
94ec8f61 BW |
1727 | bool use_scratch) |
1728 | { | |
1729 | struct drm_i915_private *dev_priv = vm->dev->dev_private; | |
782f1495 BW |
1730 | unsigned first_entry = start >> PAGE_SHIFT; |
1731 | unsigned num_entries = length >> PAGE_SHIFT; | |
07749ef3 MT |
1732 | gen8_pte_t scratch_pte, __iomem *gtt_base = |
1733 | (gen8_pte_t __iomem *) dev_priv->gtt.gsm + first_entry; | |
94ec8f61 BW |
1734 | const int max_entries = gtt_total_entries(dev_priv->gtt) - first_entry; |
1735 | int i; | |
1736 | ||
1737 | if (WARN(num_entries > max_entries, | |
1738 | "First entry = %d; Num entries = %d (max=%d)\n", | |
1739 | first_entry, num_entries, max_entries)) | |
1740 | num_entries = max_entries; | |
1741 | ||
1742 | scratch_pte = gen8_pte_encode(vm->scratch.addr, | |
1743 | I915_CACHE_LLC, | |
1744 | use_scratch); | |
1745 | for (i = 0; i < num_entries; i++) | |
1746 | gen8_set_pte(>t_base[i], scratch_pte); | |
1747 | readl(gtt_base); | |
1748 | } | |
1749 | ||
853ba5d2 | 1750 | static void gen6_ggtt_clear_range(struct i915_address_space *vm, |
782f1495 BW |
1751 | uint64_t start, |
1752 | uint64_t length, | |
828c7908 | 1753 | bool use_scratch) |
7faf1ab2 | 1754 | { |
853ba5d2 | 1755 | struct drm_i915_private *dev_priv = vm->dev->dev_private; |
782f1495 BW |
1756 | unsigned first_entry = start >> PAGE_SHIFT; |
1757 | unsigned num_entries = length >> PAGE_SHIFT; | |
07749ef3 MT |
1758 | gen6_pte_t scratch_pte, __iomem *gtt_base = |
1759 | (gen6_pte_t __iomem *) dev_priv->gtt.gsm + first_entry; | |
a54c0c27 | 1760 | const int max_entries = gtt_total_entries(dev_priv->gtt) - first_entry; |
7faf1ab2 DV |
1761 | int i; |
1762 | ||
1763 | if (WARN(num_entries > max_entries, | |
1764 | "First entry = %d; Num entries = %d (max=%d)\n", | |
1765 | first_entry, num_entries, max_entries)) | |
1766 | num_entries = max_entries; | |
1767 | ||
24f3a8cf | 1768 | scratch_pte = vm->pte_encode(vm->scratch.addr, I915_CACHE_LLC, use_scratch, 0); |
828c7908 | 1769 | |
7faf1ab2 DV |
1770 | for (i = 0; i < num_entries; i++) |
1771 | iowrite32(scratch_pte, >t_base[i]); | |
1772 | readl(gtt_base); | |
1773 | } | |
1774 | ||
6f65e29a BW |
1775 | |
1776 | static void i915_ggtt_bind_vma(struct i915_vma *vma, | |
1777 | enum i915_cache_level cache_level, | |
1778 | u32 unused) | |
7faf1ab2 | 1779 | { |
6f65e29a | 1780 | const unsigned long entry = vma->node.start >> PAGE_SHIFT; |
7faf1ab2 DV |
1781 | unsigned int flags = (cache_level == I915_CACHE_NONE) ? |
1782 | AGP_USER_MEMORY : AGP_USER_CACHED_MEMORY; | |
1783 | ||
6f65e29a | 1784 | BUG_ON(!i915_is_ggtt(vma->vm)); |
fe14d5f4 | 1785 | intel_gtt_insert_sg_entries(vma->ggtt_view.pages, entry, flags); |
aff43766 | 1786 | vma->bound = GLOBAL_BIND; |
7faf1ab2 DV |
1787 | } |
1788 | ||
853ba5d2 | 1789 | static void i915_ggtt_clear_range(struct i915_address_space *vm, |
782f1495 BW |
1790 | uint64_t start, |
1791 | uint64_t length, | |
828c7908 | 1792 | bool unused) |
7faf1ab2 | 1793 | { |
782f1495 BW |
1794 | unsigned first_entry = start >> PAGE_SHIFT; |
1795 | unsigned num_entries = length >> PAGE_SHIFT; | |
7faf1ab2 DV |
1796 | intel_gtt_clear_range(first_entry, num_entries); |
1797 | } | |
1798 | ||
6f65e29a BW |
1799 | static void i915_ggtt_unbind_vma(struct i915_vma *vma) |
1800 | { | |
1801 | const unsigned int first = vma->node.start >> PAGE_SHIFT; | |
1802 | const unsigned int size = vma->obj->base.size >> PAGE_SHIFT; | |
7faf1ab2 | 1803 | |
6f65e29a | 1804 | BUG_ON(!i915_is_ggtt(vma->vm)); |
aff43766 | 1805 | vma->bound = 0; |
6f65e29a BW |
1806 | intel_gtt_clear_range(first, size); |
1807 | } | |
7faf1ab2 | 1808 | |
6f65e29a BW |
1809 | static void ggtt_bind_vma(struct i915_vma *vma, |
1810 | enum i915_cache_level cache_level, | |
1811 | u32 flags) | |
d5bd1449 | 1812 | { |
6f65e29a | 1813 | struct drm_device *dev = vma->vm->dev; |
7faf1ab2 | 1814 | struct drm_i915_private *dev_priv = dev->dev_private; |
6f65e29a | 1815 | struct drm_i915_gem_object *obj = vma->obj; |
ec7adb6e | 1816 | struct sg_table *pages = obj->pages; |
7faf1ab2 | 1817 | |
24f3a8cf AG |
1818 | /* Currently applicable only to VLV */ |
1819 | if (obj->gt_ro) | |
1820 | flags |= PTE_READ_ONLY; | |
1821 | ||
ec7adb6e JL |
1822 | if (i915_is_ggtt(vma->vm)) |
1823 | pages = vma->ggtt_view.pages; | |
1824 | ||
6f65e29a BW |
1825 | /* If there is no aliasing PPGTT, or the caller needs a global mapping, |
1826 | * or we have a global mapping already but the cacheability flags have | |
1827 | * changed, set the global PTEs. | |
1828 | * | |
1829 | * If there is an aliasing PPGTT it is anecdotally faster, so use that | |
1830 | * instead if none of the above hold true. | |
1831 | * | |
1832 | * NB: A global mapping should only be needed for special regions like | |
1833 | * "gtt mappable", SNB errata, or if specified via special execbuf | |
1834 | * flags. At all other times, the GPU will use the aliasing PPGTT. | |
1835 | */ | |
1836 | if (!dev_priv->mm.aliasing_ppgtt || flags & GLOBAL_BIND) { | |
aff43766 | 1837 | if (!(vma->bound & GLOBAL_BIND) || |
6f65e29a | 1838 | (cache_level != obj->cache_level)) { |
ec7adb6e | 1839 | vma->vm->insert_entries(vma->vm, pages, |
782f1495 | 1840 | vma->node.start, |
24f3a8cf | 1841 | cache_level, flags); |
aff43766 | 1842 | vma->bound |= GLOBAL_BIND; |
6f65e29a BW |
1843 | } |
1844 | } | |
d5bd1449 | 1845 | |
6f65e29a | 1846 | if (dev_priv->mm.aliasing_ppgtt && |
aff43766 | 1847 | (!(vma->bound & LOCAL_BIND) || |
6f65e29a BW |
1848 | (cache_level != obj->cache_level))) { |
1849 | struct i915_hw_ppgtt *appgtt = dev_priv->mm.aliasing_ppgtt; | |
ec7adb6e | 1850 | appgtt->base.insert_entries(&appgtt->base, pages, |
782f1495 | 1851 | vma->node.start, |
24f3a8cf | 1852 | cache_level, flags); |
aff43766 | 1853 | vma->bound |= LOCAL_BIND; |
6f65e29a | 1854 | } |
d5bd1449 CW |
1855 | } |
1856 | ||
6f65e29a | 1857 | static void ggtt_unbind_vma(struct i915_vma *vma) |
74163907 | 1858 | { |
6f65e29a | 1859 | struct drm_device *dev = vma->vm->dev; |
7faf1ab2 | 1860 | struct drm_i915_private *dev_priv = dev->dev_private; |
6f65e29a | 1861 | struct drm_i915_gem_object *obj = vma->obj; |
6f65e29a | 1862 | |
aff43766 | 1863 | if (vma->bound & GLOBAL_BIND) { |
782f1495 BW |
1864 | vma->vm->clear_range(vma->vm, |
1865 | vma->node.start, | |
1866 | obj->base.size, | |
6f65e29a | 1867 | true); |
aff43766 | 1868 | vma->bound &= ~GLOBAL_BIND; |
6f65e29a | 1869 | } |
74898d7e | 1870 | |
aff43766 | 1871 | if (vma->bound & LOCAL_BIND) { |
6f65e29a BW |
1872 | struct i915_hw_ppgtt *appgtt = dev_priv->mm.aliasing_ppgtt; |
1873 | appgtt->base.clear_range(&appgtt->base, | |
782f1495 BW |
1874 | vma->node.start, |
1875 | obj->base.size, | |
6f65e29a | 1876 | true); |
aff43766 | 1877 | vma->bound &= ~LOCAL_BIND; |
6f65e29a | 1878 | } |
74163907 DV |
1879 | } |
1880 | ||
1881 | void i915_gem_gtt_finish_object(struct drm_i915_gem_object *obj) | |
7c2e6fdf | 1882 | { |
5c042287 BW |
1883 | struct drm_device *dev = obj->base.dev; |
1884 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1885 | bool interruptible; | |
1886 | ||
1887 | interruptible = do_idling(dev_priv); | |
1888 | ||
9da3da66 CW |
1889 | if (!obj->has_dma_mapping) |
1890 | dma_unmap_sg(&dev->pdev->dev, | |
1891 | obj->pages->sgl, obj->pages->nents, | |
1892 | PCI_DMA_BIDIRECTIONAL); | |
5c042287 BW |
1893 | |
1894 | undo_idling(dev_priv, interruptible); | |
7c2e6fdf | 1895 | } |
644ec02b | 1896 | |
42d6ab48 CW |
1897 | static void i915_gtt_color_adjust(struct drm_mm_node *node, |
1898 | unsigned long color, | |
440fd528 TR |
1899 | u64 *start, |
1900 | u64 *end) | |
42d6ab48 CW |
1901 | { |
1902 | if (node->color != color) | |
1903 | *start += 4096; | |
1904 | ||
1905 | if (!list_empty(&node->node_list)) { | |
1906 | node = list_entry(node->node_list.next, | |
1907 | struct drm_mm_node, | |
1908 | node_list); | |
1909 | if (node->allocated && node->color != color) | |
1910 | *end -= 4096; | |
1911 | } | |
1912 | } | |
fbe5d36e | 1913 | |
f548c0e9 DV |
1914 | static int i915_gem_setup_global_gtt(struct drm_device *dev, |
1915 | unsigned long start, | |
1916 | unsigned long mappable_end, | |
1917 | unsigned long end) | |
644ec02b | 1918 | { |
e78891ca BW |
1919 | /* Let GEM Manage all of the aperture. |
1920 | * | |
1921 | * However, leave one page at the end still bound to the scratch page. | |
1922 | * There are a number of places where the hardware apparently prefetches | |
1923 | * past the end of the object, and we've seen multiple hangs with the | |
1924 | * GPU head pointer stuck in a batchbuffer bound at the last page of the | |
1925 | * aperture. One page should be enough to keep any prefetching inside | |
1926 | * of the aperture. | |
1927 | */ | |
40d74980 BW |
1928 | struct drm_i915_private *dev_priv = dev->dev_private; |
1929 | struct i915_address_space *ggtt_vm = &dev_priv->gtt.base; | |
ed2f3452 CW |
1930 | struct drm_mm_node *entry; |
1931 | struct drm_i915_gem_object *obj; | |
1932 | unsigned long hole_start, hole_end; | |
fa76da34 | 1933 | int ret; |
644ec02b | 1934 | |
35451cb6 BW |
1935 | BUG_ON(mappable_end > end); |
1936 | ||
ed2f3452 | 1937 | /* Subtract the guard page ... */ |
40d74980 | 1938 | drm_mm_init(&ggtt_vm->mm, start, end - start - PAGE_SIZE); |
5dda8fa3 YZ |
1939 | |
1940 | dev_priv->gtt.base.start = start; | |
1941 | dev_priv->gtt.base.total = end - start; | |
1942 | ||
1943 | if (intel_vgpu_active(dev)) { | |
1944 | ret = intel_vgt_balloon(dev); | |
1945 | if (ret) | |
1946 | return ret; | |
1947 | } | |
1948 | ||
42d6ab48 | 1949 | if (!HAS_LLC(dev)) |
93bd8649 | 1950 | dev_priv->gtt.base.mm.color_adjust = i915_gtt_color_adjust; |
644ec02b | 1951 | |
ed2f3452 | 1952 | /* Mark any preallocated objects as occupied */ |
35c20a60 | 1953 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) { |
40d74980 | 1954 | struct i915_vma *vma = i915_gem_obj_to_vma(obj, ggtt_vm); |
fa76da34 | 1955 | |
edd41a87 | 1956 | DRM_DEBUG_KMS("reserving preallocated space: %lx + %zx\n", |
c6cfb325 BW |
1957 | i915_gem_obj_ggtt_offset(obj), obj->base.size); |
1958 | ||
1959 | WARN_ON(i915_gem_obj_ggtt_bound(obj)); | |
40d74980 | 1960 | ret = drm_mm_reserve_node(&ggtt_vm->mm, &vma->node); |
6c5566a8 DV |
1961 | if (ret) { |
1962 | DRM_DEBUG_KMS("Reservation failed: %i\n", ret); | |
1963 | return ret; | |
1964 | } | |
aff43766 | 1965 | vma->bound |= GLOBAL_BIND; |
ed2f3452 CW |
1966 | } |
1967 | ||
ed2f3452 | 1968 | /* Clear any non-preallocated blocks */ |
40d74980 | 1969 | drm_mm_for_each_hole(entry, &ggtt_vm->mm, hole_start, hole_end) { |
ed2f3452 CW |
1970 | DRM_DEBUG_KMS("clearing unused GTT space: [%lx, %lx]\n", |
1971 | hole_start, hole_end); | |
782f1495 BW |
1972 | ggtt_vm->clear_range(ggtt_vm, hole_start, |
1973 | hole_end - hole_start, true); | |
ed2f3452 CW |
1974 | } |
1975 | ||
1976 | /* And finally clear the reserved guard page */ | |
782f1495 | 1977 | ggtt_vm->clear_range(ggtt_vm, end - PAGE_SIZE, PAGE_SIZE, true); |
6c5566a8 | 1978 | |
fa76da34 DV |
1979 | if (USES_PPGTT(dev) && !USES_FULL_PPGTT(dev)) { |
1980 | struct i915_hw_ppgtt *ppgtt; | |
1981 | ||
1982 | ppgtt = kzalloc(sizeof(*ppgtt), GFP_KERNEL); | |
1983 | if (!ppgtt) | |
1984 | return -ENOMEM; | |
1985 | ||
1986 | ret = __hw_ppgtt_init(dev, ppgtt); | |
1987 | if (ret != 0) | |
1988 | return ret; | |
1989 | ||
1990 | dev_priv->mm.aliasing_ppgtt = ppgtt; | |
1991 | } | |
1992 | ||
6c5566a8 | 1993 | return 0; |
e76e9aeb BW |
1994 | } |
1995 | ||
d7e5008f BW |
1996 | void i915_gem_init_global_gtt(struct drm_device *dev) |
1997 | { | |
1998 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1999 | unsigned long gtt_size, mappable_size; | |
d7e5008f | 2000 | |
853ba5d2 | 2001 | gtt_size = dev_priv->gtt.base.total; |
93d18799 | 2002 | mappable_size = dev_priv->gtt.mappable_end; |
d7e5008f | 2003 | |
e78891ca | 2004 | i915_gem_setup_global_gtt(dev, 0, mappable_size, gtt_size); |
e76e9aeb BW |
2005 | } |
2006 | ||
90d0a0e8 DV |
2007 | void i915_global_gtt_cleanup(struct drm_device *dev) |
2008 | { | |
2009 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2010 | struct i915_address_space *vm = &dev_priv->gtt.base; | |
2011 | ||
70e32544 DV |
2012 | if (dev_priv->mm.aliasing_ppgtt) { |
2013 | struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt; | |
2014 | ||
2015 | ppgtt->base.cleanup(&ppgtt->base); | |
2016 | } | |
2017 | ||
90d0a0e8 | 2018 | if (drm_mm_initialized(&vm->mm)) { |
5dda8fa3 YZ |
2019 | if (intel_vgpu_active(dev)) |
2020 | intel_vgt_deballoon(); | |
2021 | ||
90d0a0e8 DV |
2022 | drm_mm_takedown(&vm->mm); |
2023 | list_del(&vm->global_link); | |
2024 | } | |
2025 | ||
2026 | vm->cleanup(vm); | |
2027 | } | |
70e32544 | 2028 | |
e76e9aeb BW |
2029 | static int setup_scratch_page(struct drm_device *dev) |
2030 | { | |
2031 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2032 | struct page *page; | |
2033 | dma_addr_t dma_addr; | |
2034 | ||
2035 | page = alloc_page(GFP_KERNEL | GFP_DMA32 | __GFP_ZERO); | |
2036 | if (page == NULL) | |
2037 | return -ENOMEM; | |
e76e9aeb BW |
2038 | set_pages_uc(page, 1); |
2039 | ||
2040 | #ifdef CONFIG_INTEL_IOMMU | |
2041 | dma_addr = pci_map_page(dev->pdev, page, 0, PAGE_SIZE, | |
2042 | PCI_DMA_BIDIRECTIONAL); | |
2043 | if (pci_dma_mapping_error(dev->pdev, dma_addr)) | |
2044 | return -EINVAL; | |
2045 | #else | |
2046 | dma_addr = page_to_phys(page); | |
2047 | #endif | |
853ba5d2 BW |
2048 | dev_priv->gtt.base.scratch.page = page; |
2049 | dev_priv->gtt.base.scratch.addr = dma_addr; | |
e76e9aeb BW |
2050 | |
2051 | return 0; | |
2052 | } | |
2053 | ||
2054 | static void teardown_scratch_page(struct drm_device *dev) | |
2055 | { | |
2056 | struct drm_i915_private *dev_priv = dev->dev_private; | |
853ba5d2 BW |
2057 | struct page *page = dev_priv->gtt.base.scratch.page; |
2058 | ||
2059 | set_pages_wb(page, 1); | |
2060 | pci_unmap_page(dev->pdev, dev_priv->gtt.base.scratch.addr, | |
e76e9aeb | 2061 | PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); |
853ba5d2 | 2062 | __free_page(page); |
e76e9aeb BW |
2063 | } |
2064 | ||
2065 | static inline unsigned int gen6_get_total_gtt_size(u16 snb_gmch_ctl) | |
2066 | { | |
2067 | snb_gmch_ctl >>= SNB_GMCH_GGMS_SHIFT; | |
2068 | snb_gmch_ctl &= SNB_GMCH_GGMS_MASK; | |
2069 | return snb_gmch_ctl << 20; | |
2070 | } | |
2071 | ||
9459d252 BW |
2072 | static inline unsigned int gen8_get_total_gtt_size(u16 bdw_gmch_ctl) |
2073 | { | |
2074 | bdw_gmch_ctl >>= BDW_GMCH_GGMS_SHIFT; | |
2075 | bdw_gmch_ctl &= BDW_GMCH_GGMS_MASK; | |
2076 | if (bdw_gmch_ctl) | |
2077 | bdw_gmch_ctl = 1 << bdw_gmch_ctl; | |
562d55d9 BW |
2078 | |
2079 | #ifdef CONFIG_X86_32 | |
2080 | /* Limit 32b platforms to a 2GB GGTT: 4 << 20 / pte size * PAGE_SIZE */ | |
2081 | if (bdw_gmch_ctl > 4) | |
2082 | bdw_gmch_ctl = 4; | |
2083 | #endif | |
2084 | ||
9459d252 BW |
2085 | return bdw_gmch_ctl << 20; |
2086 | } | |
2087 | ||
d7f25f23 DL |
2088 | static inline unsigned int chv_get_total_gtt_size(u16 gmch_ctrl) |
2089 | { | |
2090 | gmch_ctrl >>= SNB_GMCH_GGMS_SHIFT; | |
2091 | gmch_ctrl &= SNB_GMCH_GGMS_MASK; | |
2092 | ||
2093 | if (gmch_ctrl) | |
2094 | return 1 << (20 + gmch_ctrl); | |
2095 | ||
2096 | return 0; | |
2097 | } | |
2098 | ||
baa09f5f | 2099 | static inline size_t gen6_get_stolen_size(u16 snb_gmch_ctl) |
e76e9aeb BW |
2100 | { |
2101 | snb_gmch_ctl >>= SNB_GMCH_GMS_SHIFT; | |
2102 | snb_gmch_ctl &= SNB_GMCH_GMS_MASK; | |
2103 | return snb_gmch_ctl << 25; /* 32 MB units */ | |
2104 | } | |
2105 | ||
9459d252 BW |
2106 | static inline size_t gen8_get_stolen_size(u16 bdw_gmch_ctl) |
2107 | { | |
2108 | bdw_gmch_ctl >>= BDW_GMCH_GMS_SHIFT; | |
2109 | bdw_gmch_ctl &= BDW_GMCH_GMS_MASK; | |
2110 | return bdw_gmch_ctl << 25; /* 32 MB units */ | |
2111 | } | |
2112 | ||
d7f25f23 DL |
2113 | static size_t chv_get_stolen_size(u16 gmch_ctrl) |
2114 | { | |
2115 | gmch_ctrl >>= SNB_GMCH_GMS_SHIFT; | |
2116 | gmch_ctrl &= SNB_GMCH_GMS_MASK; | |
2117 | ||
2118 | /* | |
2119 | * 0x0 to 0x10: 32MB increments starting at 0MB | |
2120 | * 0x11 to 0x16: 4MB increments starting at 8MB | |
2121 | * 0x17 to 0x1d: 4MB increments start at 36MB | |
2122 | */ | |
2123 | if (gmch_ctrl < 0x11) | |
2124 | return gmch_ctrl << 25; | |
2125 | else if (gmch_ctrl < 0x17) | |
2126 | return (gmch_ctrl - 0x11 + 2) << 22; | |
2127 | else | |
2128 | return (gmch_ctrl - 0x17 + 9) << 22; | |
2129 | } | |
2130 | ||
66375014 DL |
2131 | static size_t gen9_get_stolen_size(u16 gen9_gmch_ctl) |
2132 | { | |
2133 | gen9_gmch_ctl >>= BDW_GMCH_GMS_SHIFT; | |
2134 | gen9_gmch_ctl &= BDW_GMCH_GMS_MASK; | |
2135 | ||
2136 | if (gen9_gmch_ctl < 0xf0) | |
2137 | return gen9_gmch_ctl << 25; /* 32 MB units */ | |
2138 | else | |
2139 | /* 4MB increments starting at 0xf0 for 4MB */ | |
2140 | return (gen9_gmch_ctl - 0xf0 + 1) << 22; | |
2141 | } | |
2142 | ||
63340133 BW |
2143 | static int ggtt_probe_common(struct drm_device *dev, |
2144 | size_t gtt_size) | |
2145 | { | |
2146 | struct drm_i915_private *dev_priv = dev->dev_private; | |
21c34607 | 2147 | phys_addr_t gtt_phys_addr; |
63340133 BW |
2148 | int ret; |
2149 | ||
2150 | /* For Modern GENs the PTEs and register space are split in the BAR */ | |
21c34607 | 2151 | gtt_phys_addr = pci_resource_start(dev->pdev, 0) + |
63340133 BW |
2152 | (pci_resource_len(dev->pdev, 0) / 2); |
2153 | ||
21c34607 | 2154 | dev_priv->gtt.gsm = ioremap_wc(gtt_phys_addr, gtt_size); |
63340133 BW |
2155 | if (!dev_priv->gtt.gsm) { |
2156 | DRM_ERROR("Failed to map the gtt page table\n"); | |
2157 | return -ENOMEM; | |
2158 | } | |
2159 | ||
2160 | ret = setup_scratch_page(dev); | |
2161 | if (ret) { | |
2162 | DRM_ERROR("Scratch setup failed\n"); | |
2163 | /* iounmap will also get called at remove, but meh */ | |
2164 | iounmap(dev_priv->gtt.gsm); | |
2165 | } | |
2166 | ||
2167 | return ret; | |
2168 | } | |
2169 | ||
fbe5d36e BW |
2170 | /* The GGTT and PPGTT need a private PPAT setup in order to handle cacheability |
2171 | * bits. When using advanced contexts each context stores its own PAT, but | |
2172 | * writing this data shouldn't be harmful even in those cases. */ | |
ee0ce478 | 2173 | static void bdw_setup_private_ppat(struct drm_i915_private *dev_priv) |
fbe5d36e | 2174 | { |
fbe5d36e BW |
2175 | uint64_t pat; |
2176 | ||
2177 | pat = GEN8_PPAT(0, GEN8_PPAT_WB | GEN8_PPAT_LLC) | /* for normal objects, no eLLC */ | |
2178 | GEN8_PPAT(1, GEN8_PPAT_WC | GEN8_PPAT_LLCELLC) | /* for something pointing to ptes? */ | |
2179 | GEN8_PPAT(2, GEN8_PPAT_WT | GEN8_PPAT_LLCELLC) | /* for scanout with eLLC */ | |
2180 | GEN8_PPAT(3, GEN8_PPAT_UC) | /* Uncached objects, mostly for scanout */ | |
2181 | GEN8_PPAT(4, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(0)) | | |
2182 | GEN8_PPAT(5, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(1)) | | |
2183 | GEN8_PPAT(6, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(2)) | | |
2184 | GEN8_PPAT(7, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(3)); | |
2185 | ||
d6a8b72e RV |
2186 | if (!USES_PPGTT(dev_priv->dev)) |
2187 | /* Spec: "For GGTT, there is NO pat_sel[2:0] from the entry, | |
2188 | * so RTL will always use the value corresponding to | |
2189 | * pat_sel = 000". | |
2190 | * So let's disable cache for GGTT to avoid screen corruptions. | |
2191 | * MOCS still can be used though. | |
2192 | * - System agent ggtt writes (i.e. cpu gtt mmaps) already work | |
2193 | * before this patch, i.e. the same uncached + snooping access | |
2194 | * like on gen6/7 seems to be in effect. | |
2195 | * - So this just fixes blitter/render access. Again it looks | |
2196 | * like it's not just uncached access, but uncached + snooping. | |
2197 | * So we can still hold onto all our assumptions wrt cpu | |
2198 | * clflushing on LLC machines. | |
2199 | */ | |
2200 | pat = GEN8_PPAT(0, GEN8_PPAT_UC); | |
2201 | ||
fbe5d36e BW |
2202 | /* XXX: spec defines this as 2 distinct registers. It's unclear if a 64b |
2203 | * write would work. */ | |
2204 | I915_WRITE(GEN8_PRIVATE_PAT, pat); | |
2205 | I915_WRITE(GEN8_PRIVATE_PAT + 4, pat >> 32); | |
2206 | } | |
2207 | ||
ee0ce478 VS |
2208 | static void chv_setup_private_ppat(struct drm_i915_private *dev_priv) |
2209 | { | |
2210 | uint64_t pat; | |
2211 | ||
2212 | /* | |
2213 | * Map WB on BDW to snooped on CHV. | |
2214 | * | |
2215 | * Only the snoop bit has meaning for CHV, the rest is | |
2216 | * ignored. | |
2217 | * | |
cf3d262e VS |
2218 | * The hardware will never snoop for certain types of accesses: |
2219 | * - CPU GTT (GMADR->GGTT->no snoop->memory) | |
2220 | * - PPGTT page tables | |
2221 | * - some other special cycles | |
2222 | * | |
2223 | * As with BDW, we also need to consider the following for GT accesses: | |
2224 | * "For GGTT, there is NO pat_sel[2:0] from the entry, | |
2225 | * so RTL will always use the value corresponding to | |
2226 | * pat_sel = 000". | |
2227 | * Which means we must set the snoop bit in PAT entry 0 | |
2228 | * in order to keep the global status page working. | |
ee0ce478 VS |
2229 | */ |
2230 | pat = GEN8_PPAT(0, CHV_PPAT_SNOOP) | | |
2231 | GEN8_PPAT(1, 0) | | |
2232 | GEN8_PPAT(2, 0) | | |
2233 | GEN8_PPAT(3, 0) | | |
2234 | GEN8_PPAT(4, CHV_PPAT_SNOOP) | | |
2235 | GEN8_PPAT(5, CHV_PPAT_SNOOP) | | |
2236 | GEN8_PPAT(6, CHV_PPAT_SNOOP) | | |
2237 | GEN8_PPAT(7, CHV_PPAT_SNOOP); | |
2238 | ||
2239 | I915_WRITE(GEN8_PRIVATE_PAT, pat); | |
2240 | I915_WRITE(GEN8_PRIVATE_PAT + 4, pat >> 32); | |
2241 | } | |
2242 | ||
63340133 BW |
2243 | static int gen8_gmch_probe(struct drm_device *dev, |
2244 | size_t *gtt_total, | |
2245 | size_t *stolen, | |
2246 | phys_addr_t *mappable_base, | |
2247 | unsigned long *mappable_end) | |
2248 | { | |
2249 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2250 | unsigned int gtt_size; | |
2251 | u16 snb_gmch_ctl; | |
2252 | int ret; | |
2253 | ||
2254 | /* TODO: We're not aware of mappable constraints on gen8 yet */ | |
2255 | *mappable_base = pci_resource_start(dev->pdev, 2); | |
2256 | *mappable_end = pci_resource_len(dev->pdev, 2); | |
2257 | ||
2258 | if (!pci_set_dma_mask(dev->pdev, DMA_BIT_MASK(39))) | |
2259 | pci_set_consistent_dma_mask(dev->pdev, DMA_BIT_MASK(39)); | |
2260 | ||
2261 | pci_read_config_word(dev->pdev, SNB_GMCH_CTRL, &snb_gmch_ctl); | |
2262 | ||
66375014 DL |
2263 | if (INTEL_INFO(dev)->gen >= 9) { |
2264 | *stolen = gen9_get_stolen_size(snb_gmch_ctl); | |
2265 | gtt_size = gen8_get_total_gtt_size(snb_gmch_ctl); | |
2266 | } else if (IS_CHERRYVIEW(dev)) { | |
d7f25f23 DL |
2267 | *stolen = chv_get_stolen_size(snb_gmch_ctl); |
2268 | gtt_size = chv_get_total_gtt_size(snb_gmch_ctl); | |
2269 | } else { | |
2270 | *stolen = gen8_get_stolen_size(snb_gmch_ctl); | |
2271 | gtt_size = gen8_get_total_gtt_size(snb_gmch_ctl); | |
2272 | } | |
63340133 | 2273 | |
07749ef3 | 2274 | *gtt_total = (gtt_size / sizeof(gen8_pte_t)) << PAGE_SHIFT; |
63340133 | 2275 | |
ee0ce478 VS |
2276 | if (IS_CHERRYVIEW(dev)) |
2277 | chv_setup_private_ppat(dev_priv); | |
2278 | else | |
2279 | bdw_setup_private_ppat(dev_priv); | |
fbe5d36e | 2280 | |
63340133 BW |
2281 | ret = ggtt_probe_common(dev, gtt_size); |
2282 | ||
94ec8f61 BW |
2283 | dev_priv->gtt.base.clear_range = gen8_ggtt_clear_range; |
2284 | dev_priv->gtt.base.insert_entries = gen8_ggtt_insert_entries; | |
63340133 BW |
2285 | |
2286 | return ret; | |
2287 | } | |
2288 | ||
baa09f5f BW |
2289 | static int gen6_gmch_probe(struct drm_device *dev, |
2290 | size_t *gtt_total, | |
41907ddc BW |
2291 | size_t *stolen, |
2292 | phys_addr_t *mappable_base, | |
2293 | unsigned long *mappable_end) | |
e76e9aeb BW |
2294 | { |
2295 | struct drm_i915_private *dev_priv = dev->dev_private; | |
baa09f5f | 2296 | unsigned int gtt_size; |
e76e9aeb | 2297 | u16 snb_gmch_ctl; |
e76e9aeb BW |
2298 | int ret; |
2299 | ||
41907ddc BW |
2300 | *mappable_base = pci_resource_start(dev->pdev, 2); |
2301 | *mappable_end = pci_resource_len(dev->pdev, 2); | |
2302 | ||
baa09f5f BW |
2303 | /* 64/512MB is the current min/max we actually know of, but this is just |
2304 | * a coarse sanity check. | |
e76e9aeb | 2305 | */ |
41907ddc | 2306 | if ((*mappable_end < (64<<20) || (*mappable_end > (512<<20)))) { |
baa09f5f BW |
2307 | DRM_ERROR("Unknown GMADR size (%lx)\n", |
2308 | dev_priv->gtt.mappable_end); | |
2309 | return -ENXIO; | |
e76e9aeb BW |
2310 | } |
2311 | ||
e76e9aeb BW |
2312 | if (!pci_set_dma_mask(dev->pdev, DMA_BIT_MASK(40))) |
2313 | pci_set_consistent_dma_mask(dev->pdev, DMA_BIT_MASK(40)); | |
e76e9aeb | 2314 | pci_read_config_word(dev->pdev, SNB_GMCH_CTRL, &snb_gmch_ctl); |
e76e9aeb | 2315 | |
c4ae25ec | 2316 | *stolen = gen6_get_stolen_size(snb_gmch_ctl); |
a93e4161 | 2317 | |
63340133 | 2318 | gtt_size = gen6_get_total_gtt_size(snb_gmch_ctl); |
07749ef3 | 2319 | *gtt_total = (gtt_size / sizeof(gen6_pte_t)) << PAGE_SHIFT; |
e76e9aeb | 2320 | |
63340133 | 2321 | ret = ggtt_probe_common(dev, gtt_size); |
e76e9aeb | 2322 | |
853ba5d2 BW |
2323 | dev_priv->gtt.base.clear_range = gen6_ggtt_clear_range; |
2324 | dev_priv->gtt.base.insert_entries = gen6_ggtt_insert_entries; | |
7faf1ab2 | 2325 | |
e76e9aeb BW |
2326 | return ret; |
2327 | } | |
2328 | ||
853ba5d2 | 2329 | static void gen6_gmch_remove(struct i915_address_space *vm) |
e76e9aeb | 2330 | { |
853ba5d2 BW |
2331 | |
2332 | struct i915_gtt *gtt = container_of(vm, struct i915_gtt, base); | |
5ed16782 | 2333 | |
853ba5d2 BW |
2334 | iounmap(gtt->gsm); |
2335 | teardown_scratch_page(vm->dev); | |
644ec02b | 2336 | } |
baa09f5f BW |
2337 | |
2338 | static int i915_gmch_probe(struct drm_device *dev, | |
2339 | size_t *gtt_total, | |
41907ddc BW |
2340 | size_t *stolen, |
2341 | phys_addr_t *mappable_base, | |
2342 | unsigned long *mappable_end) | |
baa09f5f BW |
2343 | { |
2344 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2345 | int ret; | |
2346 | ||
baa09f5f BW |
2347 | ret = intel_gmch_probe(dev_priv->bridge_dev, dev_priv->dev->pdev, NULL); |
2348 | if (!ret) { | |
2349 | DRM_ERROR("failed to set up gmch\n"); | |
2350 | return -EIO; | |
2351 | } | |
2352 | ||
41907ddc | 2353 | intel_gtt_get(gtt_total, stolen, mappable_base, mappable_end); |
baa09f5f BW |
2354 | |
2355 | dev_priv->gtt.do_idle_maps = needs_idle_maps(dev_priv->dev); | |
853ba5d2 | 2356 | dev_priv->gtt.base.clear_range = i915_ggtt_clear_range; |
baa09f5f | 2357 | |
c0a7f818 CW |
2358 | if (unlikely(dev_priv->gtt.do_idle_maps)) |
2359 | DRM_INFO("applying Ironlake quirks for intel_iommu\n"); | |
2360 | ||
baa09f5f BW |
2361 | return 0; |
2362 | } | |
2363 | ||
853ba5d2 | 2364 | static void i915_gmch_remove(struct i915_address_space *vm) |
baa09f5f BW |
2365 | { |
2366 | intel_gmch_remove(); | |
2367 | } | |
2368 | ||
2369 | int i915_gem_gtt_init(struct drm_device *dev) | |
2370 | { | |
2371 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2372 | struct i915_gtt *gtt = &dev_priv->gtt; | |
baa09f5f BW |
2373 | int ret; |
2374 | ||
baa09f5f | 2375 | if (INTEL_INFO(dev)->gen <= 5) { |
b2f21b4d | 2376 | gtt->gtt_probe = i915_gmch_probe; |
853ba5d2 | 2377 | gtt->base.cleanup = i915_gmch_remove; |
63340133 | 2378 | } else if (INTEL_INFO(dev)->gen < 8) { |
b2f21b4d | 2379 | gtt->gtt_probe = gen6_gmch_probe; |
853ba5d2 | 2380 | gtt->base.cleanup = gen6_gmch_remove; |
4d15c145 | 2381 | if (IS_HASWELL(dev) && dev_priv->ellc_size) |
853ba5d2 | 2382 | gtt->base.pte_encode = iris_pte_encode; |
4d15c145 | 2383 | else if (IS_HASWELL(dev)) |
853ba5d2 | 2384 | gtt->base.pte_encode = hsw_pte_encode; |
b2f21b4d | 2385 | else if (IS_VALLEYVIEW(dev)) |
853ba5d2 | 2386 | gtt->base.pte_encode = byt_pte_encode; |
350ec881 CW |
2387 | else if (INTEL_INFO(dev)->gen >= 7) |
2388 | gtt->base.pte_encode = ivb_pte_encode; | |
b2f21b4d | 2389 | else |
350ec881 | 2390 | gtt->base.pte_encode = snb_pte_encode; |
63340133 BW |
2391 | } else { |
2392 | dev_priv->gtt.gtt_probe = gen8_gmch_probe; | |
2393 | dev_priv->gtt.base.cleanup = gen6_gmch_remove; | |
baa09f5f BW |
2394 | } |
2395 | ||
853ba5d2 | 2396 | ret = gtt->gtt_probe(dev, >t->base.total, >t->stolen_size, |
b2f21b4d | 2397 | >t->mappable_base, >t->mappable_end); |
a54c0c27 | 2398 | if (ret) |
baa09f5f | 2399 | return ret; |
baa09f5f | 2400 | |
853ba5d2 BW |
2401 | gtt->base.dev = dev; |
2402 | ||
baa09f5f | 2403 | /* GMADR is the PCI mmio aperture into the global GTT. */ |
853ba5d2 BW |
2404 | DRM_INFO("Memory usable by graphics device = %zdM\n", |
2405 | gtt->base.total >> 20); | |
b2f21b4d BW |
2406 | DRM_DEBUG_DRIVER("GMADR size = %ldM\n", gtt->mappable_end >> 20); |
2407 | DRM_DEBUG_DRIVER("GTT stolen size = %zdM\n", gtt->stolen_size >> 20); | |
5db6c735 DV |
2408 | #ifdef CONFIG_INTEL_IOMMU |
2409 | if (intel_iommu_gfx_mapped) | |
2410 | DRM_INFO("VT-d active for gfx access\n"); | |
2411 | #endif | |
cfa7c862 DV |
2412 | /* |
2413 | * i915.enable_ppgtt is read-only, so do an early pass to validate the | |
2414 | * user's requested state against the hardware/driver capabilities. We | |
2415 | * do this now so that we can print out any log messages once rather | |
2416 | * than every time we check intel_enable_ppgtt(). | |
2417 | */ | |
2418 | i915.enable_ppgtt = sanitize_enable_ppgtt(dev, i915.enable_ppgtt); | |
2419 | DRM_DEBUG_DRIVER("ppgtt mode: %i\n", i915.enable_ppgtt); | |
baa09f5f BW |
2420 | |
2421 | return 0; | |
2422 | } | |
6f65e29a | 2423 | |
ec7adb6e JL |
2424 | static struct i915_vma * |
2425 | __i915_gem_vma_create(struct drm_i915_gem_object *obj, | |
2426 | struct i915_address_space *vm, | |
2427 | const struct i915_ggtt_view *ggtt_view) | |
6f65e29a | 2428 | { |
dabde5c7 | 2429 | struct i915_vma *vma; |
6f65e29a | 2430 | |
ec7adb6e JL |
2431 | if (WARN_ON(i915_is_ggtt(vm) != !!ggtt_view)) |
2432 | return ERR_PTR(-EINVAL); | |
dabde5c7 DC |
2433 | vma = kzalloc(sizeof(*vma), GFP_KERNEL); |
2434 | if (vma == NULL) | |
2435 | return ERR_PTR(-ENOMEM); | |
ec7adb6e | 2436 | |
6f65e29a BW |
2437 | INIT_LIST_HEAD(&vma->vma_link); |
2438 | INIT_LIST_HEAD(&vma->mm_list); | |
2439 | INIT_LIST_HEAD(&vma->exec_list); | |
2440 | vma->vm = vm; | |
2441 | vma->obj = obj; | |
2442 | ||
b1252bcf | 2443 | if (INTEL_INFO(vm->dev)->gen >= 6) { |
7e0d96bc | 2444 | if (i915_is_ggtt(vm)) { |
ec7adb6e JL |
2445 | vma->ggtt_view = *ggtt_view; |
2446 | ||
7e0d96bc BW |
2447 | vma->unbind_vma = ggtt_unbind_vma; |
2448 | vma->bind_vma = ggtt_bind_vma; | |
2449 | } else { | |
2450 | vma->unbind_vma = ppgtt_unbind_vma; | |
2451 | vma->bind_vma = ppgtt_bind_vma; | |
2452 | } | |
b1252bcf | 2453 | } else { |
6f65e29a | 2454 | BUG_ON(!i915_is_ggtt(vm)); |
ec7adb6e | 2455 | vma->ggtt_view = *ggtt_view; |
6f65e29a BW |
2456 | vma->unbind_vma = i915_ggtt_unbind_vma; |
2457 | vma->bind_vma = i915_ggtt_bind_vma; | |
6f65e29a BW |
2458 | } |
2459 | ||
f7635669 TU |
2460 | list_add_tail(&vma->vma_link, &obj->vma_list); |
2461 | if (!i915_is_ggtt(vm)) | |
e07f0552 | 2462 | i915_ppgtt_get(i915_vm_to_ppgtt(vm)); |
6f65e29a BW |
2463 | |
2464 | return vma; | |
2465 | } | |
2466 | ||
2467 | struct i915_vma * | |
ec7adb6e JL |
2468 | i915_gem_obj_lookup_or_create_vma(struct drm_i915_gem_object *obj, |
2469 | struct i915_address_space *vm) | |
2470 | { | |
2471 | struct i915_vma *vma; | |
2472 | ||
2473 | vma = i915_gem_obj_to_vma(obj, vm); | |
2474 | if (!vma) | |
2475 | vma = __i915_gem_vma_create(obj, vm, | |
2476 | i915_is_ggtt(vm) ? &i915_ggtt_view_normal : NULL); | |
2477 | ||
2478 | return vma; | |
2479 | } | |
2480 | ||
2481 | struct i915_vma * | |
2482 | i915_gem_obj_lookup_or_create_ggtt_vma(struct drm_i915_gem_object *obj, | |
fe14d5f4 | 2483 | const struct i915_ggtt_view *view) |
6f65e29a | 2484 | { |
ec7adb6e | 2485 | struct i915_address_space *ggtt = i915_obj_to_ggtt(obj); |
6f65e29a BW |
2486 | struct i915_vma *vma; |
2487 | ||
ec7adb6e JL |
2488 | if (WARN_ON(!view)) |
2489 | return ERR_PTR(-EINVAL); | |
2490 | ||
2491 | vma = i915_gem_obj_to_ggtt_view(obj, view); | |
2492 | ||
2493 | if (IS_ERR(vma)) | |
2494 | return vma; | |
2495 | ||
6f65e29a | 2496 | if (!vma) |
ec7adb6e | 2497 | vma = __i915_gem_vma_create(obj, ggtt, view); |
6f65e29a BW |
2498 | |
2499 | return vma; | |
ec7adb6e | 2500 | |
6f65e29a | 2501 | } |
fe14d5f4 | 2502 | |
50470bb0 TU |
2503 | static void |
2504 | rotate_pages(dma_addr_t *in, unsigned int width, unsigned int height, | |
2505 | struct sg_table *st) | |
2506 | { | |
2507 | unsigned int column, row; | |
2508 | unsigned int src_idx; | |
2509 | struct scatterlist *sg = st->sgl; | |
2510 | ||
2511 | st->nents = 0; | |
2512 | ||
2513 | for (column = 0; column < width; column++) { | |
2514 | src_idx = width * (height - 1) + column; | |
2515 | for (row = 0; row < height; row++) { | |
2516 | st->nents++; | |
2517 | /* We don't need the pages, but need to initialize | |
2518 | * the entries so the sg list can be happily traversed. | |
2519 | * The only thing we need are DMA addresses. | |
2520 | */ | |
2521 | sg_set_page(sg, NULL, PAGE_SIZE, 0); | |
2522 | sg_dma_address(sg) = in[src_idx]; | |
2523 | sg_dma_len(sg) = PAGE_SIZE; | |
2524 | sg = sg_next(sg); | |
2525 | src_idx -= width; | |
2526 | } | |
2527 | } | |
2528 | } | |
2529 | ||
2530 | static struct sg_table * | |
2531 | intel_rotate_fb_obj_pages(struct i915_ggtt_view *ggtt_view, | |
2532 | struct drm_i915_gem_object *obj) | |
2533 | { | |
2534 | struct drm_device *dev = obj->base.dev; | |
2535 | struct intel_rotation_info *rot_info = &ggtt_view->rotation_info; | |
2536 | unsigned long size, pages, rot_pages; | |
2537 | struct sg_page_iter sg_iter; | |
2538 | unsigned long i; | |
2539 | dma_addr_t *page_addr_list; | |
2540 | struct sg_table *st; | |
2541 | unsigned int tile_pitch, tile_height; | |
2542 | unsigned int width_pages, height_pages; | |
1d00dad5 | 2543 | int ret = -ENOMEM; |
50470bb0 TU |
2544 | |
2545 | pages = obj->base.size / PAGE_SIZE; | |
2546 | ||
2547 | /* Calculate tiling geometry. */ | |
2548 | tile_height = intel_tile_height(dev, rot_info->pixel_format, | |
2549 | rot_info->fb_modifier); | |
2550 | tile_pitch = PAGE_SIZE / tile_height; | |
2551 | width_pages = DIV_ROUND_UP(rot_info->pitch, tile_pitch); | |
2552 | height_pages = DIV_ROUND_UP(rot_info->height, tile_height); | |
2553 | rot_pages = width_pages * height_pages; | |
2554 | size = rot_pages * PAGE_SIZE; | |
2555 | ||
2556 | /* Allocate a temporary list of source pages for random access. */ | |
2557 | page_addr_list = drm_malloc_ab(pages, sizeof(dma_addr_t)); | |
2558 | if (!page_addr_list) | |
2559 | return ERR_PTR(ret); | |
2560 | ||
2561 | /* Allocate target SG list. */ | |
2562 | st = kmalloc(sizeof(*st), GFP_KERNEL); | |
2563 | if (!st) | |
2564 | goto err_st_alloc; | |
2565 | ||
2566 | ret = sg_alloc_table(st, rot_pages, GFP_KERNEL); | |
2567 | if (ret) | |
2568 | goto err_sg_alloc; | |
2569 | ||
2570 | /* Populate source page list from the object. */ | |
2571 | i = 0; | |
2572 | for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, 0) { | |
2573 | page_addr_list[i] = sg_page_iter_dma_address(&sg_iter); | |
2574 | i++; | |
2575 | } | |
2576 | ||
2577 | /* Rotate the pages. */ | |
2578 | rotate_pages(page_addr_list, width_pages, height_pages, st); | |
2579 | ||
2580 | DRM_DEBUG_KMS( | |
2581 | "Created rotated page mapping for object size %lu (pitch=%u, height=%u, pixel_format=0x%x, %ux%u tiles, %lu pages).\n", | |
2582 | size, rot_info->pitch, rot_info->height, | |
2583 | rot_info->pixel_format, width_pages, height_pages, | |
2584 | rot_pages); | |
2585 | ||
2586 | drm_free_large(page_addr_list); | |
2587 | ||
2588 | return st; | |
2589 | ||
2590 | err_sg_alloc: | |
2591 | kfree(st); | |
2592 | err_st_alloc: | |
2593 | drm_free_large(page_addr_list); | |
2594 | ||
2595 | DRM_DEBUG_KMS( | |
2596 | "Failed to create rotated mapping for object size %lu! (%d) (pitch=%u, height=%u, pixel_format=0x%x, %ux%u tiles, %lu pages)\n", | |
2597 | size, ret, rot_info->pitch, rot_info->height, | |
2598 | rot_info->pixel_format, width_pages, height_pages, | |
2599 | rot_pages); | |
2600 | return ERR_PTR(ret); | |
2601 | } | |
ec7adb6e | 2602 | |
50470bb0 TU |
2603 | static inline int |
2604 | i915_get_ggtt_vma_pages(struct i915_vma *vma) | |
fe14d5f4 | 2605 | { |
50470bb0 TU |
2606 | int ret = 0; |
2607 | ||
fe14d5f4 TU |
2608 | if (vma->ggtt_view.pages) |
2609 | return 0; | |
2610 | ||
2611 | if (vma->ggtt_view.type == I915_GGTT_VIEW_NORMAL) | |
2612 | vma->ggtt_view.pages = vma->obj->pages; | |
50470bb0 TU |
2613 | else if (vma->ggtt_view.type == I915_GGTT_VIEW_ROTATED) |
2614 | vma->ggtt_view.pages = | |
2615 | intel_rotate_fb_obj_pages(&vma->ggtt_view, vma->obj); | |
fe14d5f4 TU |
2616 | else |
2617 | WARN_ONCE(1, "GGTT view %u not implemented!\n", | |
2618 | vma->ggtt_view.type); | |
2619 | ||
2620 | if (!vma->ggtt_view.pages) { | |
ec7adb6e | 2621 | DRM_ERROR("Failed to get pages for GGTT view type %u!\n", |
fe14d5f4 | 2622 | vma->ggtt_view.type); |
50470bb0 TU |
2623 | ret = -EINVAL; |
2624 | } else if (IS_ERR(vma->ggtt_view.pages)) { | |
2625 | ret = PTR_ERR(vma->ggtt_view.pages); | |
2626 | vma->ggtt_view.pages = NULL; | |
2627 | DRM_ERROR("Failed to get pages for VMA view type %u (%d)!\n", | |
2628 | vma->ggtt_view.type, ret); | |
fe14d5f4 TU |
2629 | } |
2630 | ||
50470bb0 | 2631 | return ret; |
fe14d5f4 TU |
2632 | } |
2633 | ||
2634 | /** | |
2635 | * i915_vma_bind - Sets up PTEs for an VMA in it's corresponding address space. | |
2636 | * @vma: VMA to map | |
2637 | * @cache_level: mapping cache level | |
2638 | * @flags: flags like global or local mapping | |
2639 | * | |
2640 | * DMA addresses are taken from the scatter-gather table of this object (or of | |
2641 | * this VMA in case of non-default GGTT views) and PTE entries set up. | |
2642 | * Note that DMA addresses are also the only part of the SG table we care about. | |
2643 | */ | |
2644 | int i915_vma_bind(struct i915_vma *vma, enum i915_cache_level cache_level, | |
2645 | u32 flags) | |
2646 | { | |
ec7adb6e JL |
2647 | if (i915_is_ggtt(vma->vm)) { |
2648 | int ret = i915_get_ggtt_vma_pages(vma); | |
fe14d5f4 | 2649 | |
ec7adb6e JL |
2650 | if (ret) |
2651 | return ret; | |
2652 | } | |
fe14d5f4 TU |
2653 | |
2654 | vma->bind_vma(vma, cache_level, flags); | |
2655 | ||
2656 | return 0; | |
2657 | } |