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0260c420 BW |
1 | /* |
2 | * Copyright © 2014 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Please try to maintain the following order within this file unless it makes | |
24 | * sense to do otherwise. From top to bottom: | |
25 | * 1. typedefs | |
26 | * 2. #defines, and macros | |
27 | * 3. structure definitions | |
28 | * 4. function prototypes | |
29 | * | |
30 | * Within each section, please try to order by generation in ascending order, | |
31 | * from top to bottom (ie. gen6 on the top, gen8 on the bottom). | |
32 | */ | |
33 | ||
34 | #ifndef __I915_GEM_GTT_H__ | |
35 | #define __I915_GEM_GTT_H__ | |
36 | ||
4d884705 DV |
37 | struct drm_i915_file_private; |
38 | ||
07749ef3 MT |
39 | typedef uint32_t gen6_pte_t; |
40 | typedef uint64_t gen8_pte_t; | |
41 | typedef uint64_t gen8_pde_t; | |
0260c420 BW |
42 | |
43 | #define gtt_total_entries(gtt) ((gtt).base.total >> PAGE_SHIFT) | |
44 | ||
07749ef3 | 45 | |
0260c420 BW |
46 | /* gen6-hsw has bit 11-4 for physical addr bit 39-32 */ |
47 | #define GEN6_GTT_ADDR_ENCODE(addr) ((addr) | (((addr) >> 28) & 0xff0)) | |
48 | #define GEN6_PTE_ADDR_ENCODE(addr) GEN6_GTT_ADDR_ENCODE(addr) | |
49 | #define GEN6_PDE_ADDR_ENCODE(addr) GEN6_GTT_ADDR_ENCODE(addr) | |
50 | #define GEN6_PTE_CACHE_LLC (2 << 1) | |
51 | #define GEN6_PTE_UNCACHED (1 << 1) | |
52 | #define GEN6_PTE_VALID (1 << 0) | |
53 | ||
07749ef3 MT |
54 | #define I915_PTES(pte_len) (PAGE_SIZE / (pte_len)) |
55 | #define I915_PTE_MASK(pte_len) (I915_PTES(pte_len) - 1) | |
56 | #define I915_PDES 512 | |
57 | #define I915_PDE_MASK (I915_PDES - 1) | |
678d96fb | 58 | #define NUM_PTE(pde_shift) (1 << (pde_shift - PAGE_SHIFT)) |
07749ef3 MT |
59 | |
60 | #define GEN6_PTES I915_PTES(sizeof(gen6_pte_t)) | |
61 | #define GEN6_PD_SIZE (I915_PDES * PAGE_SIZE) | |
0260c420 | 62 | #define GEN6_PD_ALIGN (PAGE_SIZE * 16) |
678d96fb | 63 | #define GEN6_PDE_SHIFT 22 |
0260c420 BW |
64 | #define GEN6_PDE_VALID (1 << 0) |
65 | ||
66 | #define GEN7_PTE_CACHE_L3_LLC (3 << 1) | |
67 | ||
68 | #define BYT_PTE_SNOOPED_BY_CPU_CACHES (1 << 2) | |
69 | #define BYT_PTE_WRITEABLE (1 << 1) | |
70 | ||
71 | /* Cacheability Control is a 4-bit value. The low three bits are stored in bits | |
72 | * 3:1 of the PTE, while the fourth bit is stored in bit 11 of the PTE. | |
73 | */ | |
74 | #define HSW_CACHEABILITY_CONTROL(bits) ((((bits) & 0x7) << 1) | \ | |
75 | (((bits) & 0x8) << (11 - 3))) | |
76 | #define HSW_WB_LLC_AGE3 HSW_CACHEABILITY_CONTROL(0x2) | |
77 | #define HSW_WB_LLC_AGE0 HSW_CACHEABILITY_CONTROL(0x3) | |
78 | #define HSW_WB_ELLC_LLC_AGE3 HSW_CACHEABILITY_CONTROL(0x8) | |
79 | #define HSW_WB_ELLC_LLC_AGE0 HSW_CACHEABILITY_CONTROL(0xb) | |
80 | #define HSW_WT_ELLC_LLC_AGE3 HSW_CACHEABILITY_CONTROL(0x7) | |
81 | #define HSW_WT_ELLC_LLC_AGE0 HSW_CACHEABILITY_CONTROL(0x6) | |
82 | #define HSW_PTE_UNCACHED (0) | |
83 | #define HSW_GTT_ADDR_ENCODE(addr) ((addr) | (((addr) >> 28) & 0x7f0)) | |
84 | #define HSW_PTE_ADDR_ENCODE(addr) HSW_GTT_ADDR_ENCODE(addr) | |
85 | ||
86 | /* GEN8 legacy style address is defined as a 3 level page table: | |
87 | * 31:30 | 29:21 | 20:12 | 11:0 | |
88 | * PDPE | PDE | PTE | offset | |
89 | * The difference as compared to normal x86 3 level page table is the PDPEs are | |
90 | * programmed via register. | |
91 | */ | |
92 | #define GEN8_PDPE_SHIFT 30 | |
93 | #define GEN8_PDPE_MASK 0x3 | |
94 | #define GEN8_PDE_SHIFT 21 | |
95 | #define GEN8_PDE_MASK 0x1ff | |
96 | #define GEN8_PTE_SHIFT 12 | |
97 | #define GEN8_PTE_MASK 0x1ff | |
76643600 | 98 | #define GEN8_LEGACY_PDPES 4 |
07749ef3 | 99 | #define GEN8_PTES I915_PTES(sizeof(gen8_pte_t)) |
0260c420 BW |
100 | |
101 | #define PPAT_UNCACHED_INDEX (_PAGE_PWT | _PAGE_PCD) | |
102 | #define PPAT_CACHED_PDE_INDEX 0 /* WB LLC */ | |
103 | #define PPAT_CACHED_INDEX _PAGE_PAT /* WB LLCeLLC */ | |
104 | #define PPAT_DISPLAY_ELLC_INDEX _PAGE_PCD /* WT eLLC */ | |
105 | ||
ee0ce478 | 106 | #define CHV_PPAT_SNOOP (1<<6) |
0260c420 BW |
107 | #define GEN8_PPAT_AGE(x) (x<<4) |
108 | #define GEN8_PPAT_LLCeLLC (3<<2) | |
109 | #define GEN8_PPAT_LLCELLC (2<<2) | |
110 | #define GEN8_PPAT_LLC (1<<2) | |
111 | #define GEN8_PPAT_WB (3<<0) | |
112 | #define GEN8_PPAT_WT (2<<0) | |
113 | #define GEN8_PPAT_WC (1<<0) | |
114 | #define GEN8_PPAT_UC (0<<0) | |
115 | #define GEN8_PPAT_ELLC_OVERRIDE (0<<2) | |
116 | #define GEN8_PPAT(i, x) ((uint64_t) (x) << ((i) * 8)) | |
117 | ||
fe14d5f4 TU |
118 | enum i915_ggtt_view_type { |
119 | I915_GGTT_VIEW_NORMAL = 0, | |
8bd7ef16 JL |
120 | I915_GGTT_VIEW_ROTATED, |
121 | I915_GGTT_VIEW_PARTIAL, | |
50470bb0 TU |
122 | }; |
123 | ||
124 | struct intel_rotation_info { | |
125 | unsigned int height; | |
126 | unsigned int pitch; | |
127 | uint32_t pixel_format; | |
128 | uint64_t fb_modifier; | |
84fe03f7 TU |
129 | unsigned int width_pages, height_pages; |
130 | uint64_t size; | |
fe14d5f4 TU |
131 | }; |
132 | ||
133 | struct i915_ggtt_view { | |
134 | enum i915_ggtt_view_type type; | |
135 | ||
8bd7ef16 JL |
136 | union { |
137 | struct { | |
138 | unsigned long offset; | |
139 | unsigned int size; | |
140 | } partial; | |
141 | } params; | |
142 | ||
fe14d5f4 | 143 | struct sg_table *pages; |
50470bb0 TU |
144 | |
145 | union { | |
146 | struct intel_rotation_info rotation_info; | |
147 | }; | |
fe14d5f4 TU |
148 | }; |
149 | ||
150 | extern const struct i915_ggtt_view i915_ggtt_view_normal; | |
9abc4648 | 151 | extern const struct i915_ggtt_view i915_ggtt_view_rotated; |
fe14d5f4 | 152 | |
0260c420 | 153 | enum i915_cache_level; |
fe14d5f4 | 154 | |
0260c420 BW |
155 | /** |
156 | * A VMA represents a GEM BO that is bound into an address space. Therefore, a | |
157 | * VMA's presence cannot be guaranteed before binding, or after unbinding the | |
158 | * object into/from the address space. | |
159 | * | |
160 | * To make things as simple as possible (ie. no refcounting), a VMA's lifetime | |
161 | * will always be <= an objects lifetime. So object refcounting should cover us. | |
162 | */ | |
163 | struct i915_vma { | |
164 | struct drm_mm_node node; | |
165 | struct drm_i915_gem_object *obj; | |
166 | struct i915_address_space *vm; | |
167 | ||
aff43766 TU |
168 | /** Flags and address space this VMA is bound to */ |
169 | #define GLOBAL_BIND (1<<0) | |
170 | #define LOCAL_BIND (1<<1) | |
aff43766 TU |
171 | unsigned int bound : 4; |
172 | ||
fe14d5f4 TU |
173 | /** |
174 | * Support different GGTT views into the same object. | |
175 | * This means there can be multiple VMA mappings per object and per VM. | |
176 | * i915_ggtt_view_type is used to distinguish between those entries. | |
177 | * The default one of zero (I915_GGTT_VIEW_NORMAL) is default and also | |
178 | * assumed in GEM functions which take no ggtt view parameter. | |
179 | */ | |
180 | struct i915_ggtt_view ggtt_view; | |
181 | ||
0260c420 BW |
182 | /** This object's place on the active/inactive lists */ |
183 | struct list_head mm_list; | |
184 | ||
185 | struct list_head vma_link; /* Link in the object's VMA list */ | |
186 | ||
187 | /** This vma's place in the batchbuffer or on the eviction list */ | |
188 | struct list_head exec_list; | |
189 | ||
190 | /** | |
191 | * Used for performing relocations during execbuffer insertion. | |
192 | */ | |
193 | struct hlist_node exec_node; | |
194 | unsigned long exec_handle; | |
195 | struct drm_i915_gem_exec_object2 *exec_entry; | |
196 | ||
197 | /** | |
198 | * How many users have pinned this object in GTT space. The following | |
4feb7659 DV |
199 | * users can each hold at most one reference: pwrite/pread, execbuffer |
200 | * (objects are not allowed multiple times for the same batchbuffer), | |
201 | * and the framebuffer code. When switching/pageflipping, the | |
202 | * framebuffer code has at most two buffers pinned per crtc. | |
0260c420 BW |
203 | * |
204 | * In the worst case this is 1 + 1 + 1 + 2*2 = 7. That would fit into 3 | |
205 | * bits with absolutely no headroom. So use 4 bits. */ | |
206 | unsigned int pin_count:4; | |
207 | #define DRM_I915_GEM_OBJECT_MAX_PIN_COUNT 0xf | |
0260c420 BW |
208 | }; |
209 | ||
44159ddb | 210 | struct i915_page_dma { |
d7b3de91 | 211 | struct page *page; |
44159ddb MK |
212 | union { |
213 | dma_addr_t daddr; | |
214 | ||
215 | /* For gen6/gen7 only. This is the offset in the GGTT | |
216 | * where the page directory entries for PPGTT begin | |
217 | */ | |
218 | uint32_t ggtt_offset; | |
219 | }; | |
220 | }; | |
221 | ||
567047be MK |
222 | #define px_base(px) (&(px)->base) |
223 | #define px_page(px) (px_base(px)->page) | |
224 | #define px_dma(px) (px_base(px)->daddr) | |
225 | ||
c114f76a MK |
226 | struct i915_page_scratch { |
227 | struct i915_page_dma base; | |
228 | }; | |
229 | ||
44159ddb MK |
230 | struct i915_page_table { |
231 | struct i915_page_dma base; | |
678d96fb BW |
232 | |
233 | unsigned long *used_ptes; | |
d7b3de91 BW |
234 | }; |
235 | ||
ec565b3c | 236 | struct i915_page_directory { |
44159ddb | 237 | struct i915_page_dma base; |
7324cc04 | 238 | |
33c8819f | 239 | unsigned long *used_pdes; |
ec565b3c | 240 | struct i915_page_table *page_table[I915_PDES]; /* PDEs */ |
d7b3de91 BW |
241 | }; |
242 | ||
ec565b3c | 243 | struct i915_page_directory_pointer { |
d7b3de91 | 244 | /* struct page *page; */ |
33c8819f | 245 | DECLARE_BITMAP(used_pdpes, GEN8_LEGACY_PDPES); |
ec565b3c | 246 | struct i915_page_directory *page_directory[GEN8_LEGACY_PDPES]; |
d7b3de91 BW |
247 | }; |
248 | ||
0260c420 BW |
249 | struct i915_address_space { |
250 | struct drm_mm mm; | |
251 | struct drm_device *dev; | |
252 | struct list_head global_link; | |
c44ef60e MK |
253 | u64 start; /* Start offset always 0 for dri2 */ |
254 | u64 total; /* size addr space maps (ex. 2GB for ggtt) */ | |
0260c420 | 255 | |
c114f76a | 256 | struct i915_page_scratch *scratch_page; |
79ab9370 MK |
257 | struct i915_page_table *scratch_pt; |
258 | struct i915_page_directory *scratch_pd; | |
0260c420 BW |
259 | |
260 | /** | |
261 | * List of objects currently involved in rendering. | |
262 | * | |
263 | * Includes buffers having the contents of their GPU caches | |
97b2a6a1 | 264 | * flushed, not necessarily primitives. last_read_req |
0260c420 BW |
265 | * represents when the rendering involved will be completed. |
266 | * | |
267 | * A reference is held on the buffer while on this list. | |
268 | */ | |
269 | struct list_head active_list; | |
270 | ||
271 | /** | |
272 | * LRU list of objects which are not in the ringbuffer and | |
273 | * are ready to unbind, but are still in the GTT. | |
274 | * | |
97b2a6a1 | 275 | * last_read_req is NULL while an object is in this list. |
0260c420 BW |
276 | * |
277 | * A reference is not held on the buffer while on this list, | |
278 | * as merely being GTT-bound shouldn't prevent its being | |
279 | * freed, and we'll pull it off the list in the free path. | |
280 | */ | |
281 | struct list_head inactive_list; | |
282 | ||
283 | /* FIXME: Need a more generic return type */ | |
07749ef3 MT |
284 | gen6_pte_t (*pte_encode)(dma_addr_t addr, |
285 | enum i915_cache_level level, | |
286 | bool valid, u32 flags); /* Create a valid PTE */ | |
f329f5f6 DV |
287 | /* flags for pte_encode */ |
288 | #define PTE_READ_ONLY (1<<0) | |
678d96fb BW |
289 | int (*allocate_va_range)(struct i915_address_space *vm, |
290 | uint64_t start, | |
291 | uint64_t length); | |
0260c420 BW |
292 | void (*clear_range)(struct i915_address_space *vm, |
293 | uint64_t start, | |
294 | uint64_t length, | |
295 | bool use_scratch); | |
296 | void (*insert_entries)(struct i915_address_space *vm, | |
297 | struct sg_table *st, | |
298 | uint64_t start, | |
24f3a8cf | 299 | enum i915_cache_level cache_level, u32 flags); |
0260c420 | 300 | void (*cleanup)(struct i915_address_space *vm); |
777dc5bb DV |
301 | /** Unmap an object from an address space. This usually consists of |
302 | * setting the valid PTE entries to a reserved scratch page. */ | |
303 | void (*unbind_vma)(struct i915_vma *vma); | |
304 | /* Map an object into an address space with the given cache flags. */ | |
70b9f6f8 DV |
305 | int (*bind_vma)(struct i915_vma *vma, |
306 | enum i915_cache_level cache_level, | |
307 | u32 flags); | |
0260c420 BW |
308 | }; |
309 | ||
310 | /* The Graphics Translation Table is the way in which GEN hardware translates a | |
311 | * Graphics Virtual Address into a Physical Address. In addition to the normal | |
312 | * collateral associated with any va->pa translations GEN hardware also has a | |
313 | * portion of the GTT which can be mapped by the CPU and remain both coherent | |
314 | * and correct (in cases like swizzling). That region is referred to as GMADR in | |
315 | * the spec. | |
316 | */ | |
317 | struct i915_gtt { | |
318 | struct i915_address_space base; | |
0260c420 | 319 | |
c44ef60e MK |
320 | size_t stolen_size; /* Total size of stolen memory */ |
321 | u64 mappable_end; /* End offset that we can CPU map */ | |
0260c420 BW |
322 | struct io_mapping *mappable; /* Mapping to our CPU mappable region */ |
323 | phys_addr_t mappable_base; /* PA of our GMADR */ | |
324 | ||
325 | /** "Graphics Stolen Memory" holds the global PTEs */ | |
326 | void __iomem *gsm; | |
327 | ||
328 | bool do_idle_maps; | |
329 | ||
330 | int mtrr; | |
331 | ||
332 | /* global gtt ops */ | |
c44ef60e | 333 | int (*gtt_probe)(struct drm_device *dev, u64 *gtt_total, |
0260c420 | 334 | size_t *stolen, phys_addr_t *mappable_base, |
c44ef60e | 335 | u64 *mappable_end); |
0260c420 BW |
336 | }; |
337 | ||
338 | struct i915_hw_ppgtt { | |
339 | struct i915_address_space base; | |
340 | struct kref ref; | |
341 | struct drm_mm_node node; | |
563222a7 | 342 | unsigned long pd_dirty_rings; |
d7b3de91 | 343 | union { |
ec565b3c MT |
344 | struct i915_page_directory_pointer pdp; |
345 | struct i915_page_directory pd; | |
d7b3de91 | 346 | }; |
0260c420 | 347 | |
4d884705 | 348 | struct drm_i915_file_private *file_priv; |
0260c420 | 349 | |
678d96fb BW |
350 | gen6_pte_t __iomem *pd_addr; |
351 | ||
0260c420 BW |
352 | int (*enable)(struct i915_hw_ppgtt *ppgtt); |
353 | int (*switch_mm)(struct i915_hw_ppgtt *ppgtt, | |
e85b26dc | 354 | struct drm_i915_gem_request *req); |
0260c420 BW |
355 | void (*debug_dump)(struct i915_hw_ppgtt *ppgtt, struct seq_file *m); |
356 | }; | |
357 | ||
678d96fb BW |
358 | /* For each pde iterates over every pde between from start until start + length. |
359 | * If start, and start+length are not perfectly divisible, the macro will round | |
360 | * down, and up as needed. The macro modifies pde, start, and length. Dev is | |
361 | * only used to differentiate shift values. Temp is temp. On gen6/7, start = 0, | |
362 | * and length = 2G effectively iterates over every PDE in the system. | |
363 | * | |
364 | * XXX: temp is not actually needed, but it saves doing the ALIGN operation. | |
365 | */ | |
366 | #define gen6_for_each_pde(pt, pd, start, length, temp, iter) \ | |
fdc454c1 MT |
367 | for (iter = gen6_pde_index(start); \ |
368 | pt = (pd)->page_table[iter], length > 0 && iter < I915_PDES; \ | |
369 | iter++, \ | |
678d96fb BW |
370 | temp = ALIGN(start+1, 1 << GEN6_PDE_SHIFT) - start, \ |
371 | temp = min_t(unsigned, temp, length), \ | |
372 | start += temp, length -= temp) | |
373 | ||
09942c65 MT |
374 | #define gen6_for_all_pdes(pt, ppgtt, iter) \ |
375 | for (iter = 0; \ | |
376 | pt = ppgtt->pd.page_table[iter], iter < I915_PDES; \ | |
377 | iter++) | |
378 | ||
678d96fb BW |
379 | static inline uint32_t i915_pte_index(uint64_t address, uint32_t pde_shift) |
380 | { | |
381 | const uint32_t mask = NUM_PTE(pde_shift) - 1; | |
382 | ||
383 | return (address >> PAGE_SHIFT) & mask; | |
384 | } | |
385 | ||
386 | /* Helper to counts the number of PTEs within the given length. This count | |
387 | * does not cross a page table boundary, so the max value would be | |
388 | * GEN6_PTES for GEN6, and GEN8_PTES for GEN8. | |
389 | */ | |
390 | static inline uint32_t i915_pte_count(uint64_t addr, size_t length, | |
391 | uint32_t pde_shift) | |
392 | { | |
393 | const uint64_t mask = ~((1 << pde_shift) - 1); | |
394 | uint64_t end; | |
395 | ||
396 | WARN_ON(length == 0); | |
397 | WARN_ON(offset_in_page(addr|length)); | |
398 | ||
399 | end = addr + length; | |
400 | ||
401 | if ((addr & mask) != (end & mask)) | |
402 | return NUM_PTE(pde_shift) - i915_pte_index(addr, pde_shift); | |
403 | ||
404 | return i915_pte_index(end, pde_shift) - i915_pte_index(addr, pde_shift); | |
405 | } | |
406 | ||
407 | static inline uint32_t i915_pde_index(uint64_t addr, uint32_t shift) | |
408 | { | |
409 | return (addr >> shift) & I915_PDE_MASK; | |
410 | } | |
411 | ||
412 | static inline uint32_t gen6_pte_index(uint32_t addr) | |
413 | { | |
414 | return i915_pte_index(addr, GEN6_PDE_SHIFT); | |
415 | } | |
416 | ||
417 | static inline size_t gen6_pte_count(uint32_t addr, uint32_t length) | |
418 | { | |
419 | return i915_pte_count(addr, length, GEN6_PDE_SHIFT); | |
420 | } | |
421 | ||
422 | static inline uint32_t gen6_pde_index(uint32_t addr) | |
423 | { | |
424 | return i915_pde_index(addr, GEN6_PDE_SHIFT); | |
425 | } | |
426 | ||
9271d959 MT |
427 | /* Equivalent to the gen6 version, For each pde iterates over every pde |
428 | * between from start until start + length. On gen8+ it simply iterates | |
429 | * over every page directory entry in a page directory. | |
430 | */ | |
431 | #define gen8_for_each_pde(pt, pd, start, length, temp, iter) \ | |
432 | for (iter = gen8_pde_index(start); \ | |
433 | pt = (pd)->page_table[iter], length > 0 && iter < I915_PDES; \ | |
434 | iter++, \ | |
435 | temp = ALIGN(start+1, 1 << GEN8_PDE_SHIFT) - start, \ | |
436 | temp = min(temp, length), \ | |
437 | start += temp, length -= temp) | |
438 | ||
439 | #define gen8_for_each_pdpe(pd, pdp, start, length, temp, iter) \ | |
440 | for (iter = gen8_pdpe_index(start); \ | |
441 | pd = (pdp)->page_directory[iter], length > 0 && iter < GEN8_LEGACY_PDPES; \ | |
442 | iter++, \ | |
443 | temp = ALIGN(start+1, 1 << GEN8_PDPE_SHIFT) - start, \ | |
444 | temp = min(temp, length), \ | |
445 | start += temp, length -= temp) | |
446 | ||
447 | /* Clamp length to the next page_directory boundary */ | |
448 | static inline uint64_t gen8_clamp_pd(uint64_t start, uint64_t length) | |
449 | { | |
450 | uint64_t next_pd = ALIGN(start + 1, 1 << GEN8_PDPE_SHIFT); | |
451 | ||
452 | if (next_pd > (start + length)) | |
453 | return length; | |
454 | ||
455 | return next_pd - start; | |
456 | } | |
457 | ||
458 | static inline uint32_t gen8_pte_index(uint64_t address) | |
459 | { | |
460 | return i915_pte_index(address, GEN8_PDE_SHIFT); | |
461 | } | |
462 | ||
463 | static inline uint32_t gen8_pde_index(uint64_t address) | |
464 | { | |
465 | return i915_pde_index(address, GEN8_PDE_SHIFT); | |
466 | } | |
467 | ||
468 | static inline uint32_t gen8_pdpe_index(uint64_t address) | |
469 | { | |
470 | return (address >> GEN8_PDPE_SHIFT) & GEN8_PDPE_MASK; | |
471 | } | |
472 | ||
473 | static inline uint32_t gen8_pml4e_index(uint64_t address) | |
474 | { | |
475 | WARN_ON(1); /* For 64B */ | |
476 | return 0; | |
477 | } | |
478 | ||
33c8819f MT |
479 | static inline size_t gen8_pte_count(uint64_t address, uint64_t length) |
480 | { | |
481 | return i915_pte_count(address, length, GEN8_PDE_SHIFT); | |
482 | } | |
483 | ||
d852c7bf MK |
484 | static inline dma_addr_t |
485 | i915_page_dir_dma_addr(const struct i915_hw_ppgtt *ppgtt, const unsigned n) | |
486 | { | |
487 | return test_bit(n, ppgtt->pdp.used_pdpes) ? | |
567047be | 488 | px_dma(ppgtt->pdp.page_directory[n]) : |
79ab9370 | 489 | px_dma(ppgtt->base.scratch_pd); |
d852c7bf MK |
490 | } |
491 | ||
0260c420 BW |
492 | int i915_gem_gtt_init(struct drm_device *dev); |
493 | void i915_gem_init_global_gtt(struct drm_device *dev); | |
90d0a0e8 | 494 | void i915_global_gtt_cleanup(struct drm_device *dev); |
0260c420 | 495 | |
ee960be7 DV |
496 | |
497 | int i915_ppgtt_init(struct drm_device *dev, struct i915_hw_ppgtt *ppgtt); | |
82460d97 | 498 | int i915_ppgtt_init_hw(struct drm_device *dev); |
b3dd6b96 | 499 | int i915_ppgtt_init_ring(struct drm_i915_gem_request *req); |
ee960be7 | 500 | void i915_ppgtt_release(struct kref *kref); |
4d884705 DV |
501 | struct i915_hw_ppgtt *i915_ppgtt_create(struct drm_device *dev, |
502 | struct drm_i915_file_private *fpriv); | |
ee960be7 DV |
503 | static inline void i915_ppgtt_get(struct i915_hw_ppgtt *ppgtt) |
504 | { | |
505 | if (ppgtt) | |
506 | kref_get(&ppgtt->ref); | |
507 | } | |
508 | static inline void i915_ppgtt_put(struct i915_hw_ppgtt *ppgtt) | |
509 | { | |
510 | if (ppgtt) | |
511 | kref_put(&ppgtt->ref, i915_ppgtt_release); | |
512 | } | |
0260c420 BW |
513 | |
514 | void i915_check_and_clear_faults(struct drm_device *dev); | |
515 | void i915_gem_suspend_gtt_mappings(struct drm_device *dev); | |
516 | void i915_gem_restore_gtt_mappings(struct drm_device *dev); | |
517 | ||
518 | int __must_check i915_gem_gtt_prepare_object(struct drm_i915_gem_object *obj); | |
519 | void i915_gem_gtt_finish_object(struct drm_i915_gem_object *obj); | |
520 | ||
9abc4648 JL |
521 | static inline bool |
522 | i915_ggtt_view_equal(const struct i915_ggtt_view *a, | |
523 | const struct i915_ggtt_view *b) | |
524 | { | |
525 | if (WARN_ON(!a || !b)) | |
526 | return false; | |
527 | ||
8bd7ef16 JL |
528 | if (a->type != b->type) |
529 | return false; | |
530 | if (a->type == I915_GGTT_VIEW_PARTIAL) | |
531 | return !memcmp(&a->params, &b->params, sizeof(a->params)); | |
532 | return true; | |
9abc4648 JL |
533 | } |
534 | ||
91e6711e JL |
535 | size_t |
536 | i915_ggtt_view_size(struct drm_i915_gem_object *obj, | |
537 | const struct i915_ggtt_view *view); | |
538 | ||
0260c420 | 539 | #endif |