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0260c420 BW |
1 | /* |
2 | * Copyright © 2014 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Please try to maintain the following order within this file unless it makes | |
24 | * sense to do otherwise. From top to bottom: | |
25 | * 1. typedefs | |
26 | * 2. #defines, and macros | |
27 | * 3. structure definitions | |
28 | * 4. function prototypes | |
29 | * | |
30 | * Within each section, please try to order by generation in ascending order, | |
31 | * from top to bottom (ie. gen6 on the top, gen8 on the bottom). | |
32 | */ | |
33 | ||
34 | #ifndef __I915_GEM_GTT_H__ | |
35 | #define __I915_GEM_GTT_H__ | |
36 | ||
8ef8561f CW |
37 | #include <linux/io-mapping.h> |
38 | ||
b0decaf7 CW |
39 | #include "i915_gem_request.h" |
40 | ||
49ef5294 CW |
41 | #define I915_FENCE_REG_NONE -1 |
42 | #define I915_MAX_NUM_FENCES 32 | |
43 | /* 32 fences + sign bit for FENCE_REG_NONE */ | |
44 | #define I915_MAX_NUM_FENCE_BITS 6 | |
45 | ||
4d884705 | 46 | struct drm_i915_file_private; |
49ef5294 | 47 | struct drm_i915_fence_reg; |
4d884705 | 48 | |
07749ef3 MT |
49 | typedef uint32_t gen6_pte_t; |
50 | typedef uint64_t gen8_pte_t; | |
51 | typedef uint64_t gen8_pde_t; | |
762d9936 MT |
52 | typedef uint64_t gen8_ppgtt_pdpe_t; |
53 | typedef uint64_t gen8_ppgtt_pml4e_t; | |
0260c420 | 54 | |
72e96d64 | 55 | #define ggtt_total_entries(ggtt) ((ggtt)->base.total >> PAGE_SHIFT) |
0260c420 | 56 | |
0260c420 BW |
57 | /* gen6-hsw has bit 11-4 for physical addr bit 39-32 */ |
58 | #define GEN6_GTT_ADDR_ENCODE(addr) ((addr) | (((addr) >> 28) & 0xff0)) | |
59 | #define GEN6_PTE_ADDR_ENCODE(addr) GEN6_GTT_ADDR_ENCODE(addr) | |
60 | #define GEN6_PDE_ADDR_ENCODE(addr) GEN6_GTT_ADDR_ENCODE(addr) | |
61 | #define GEN6_PTE_CACHE_LLC (2 << 1) | |
62 | #define GEN6_PTE_UNCACHED (1 << 1) | |
63 | #define GEN6_PTE_VALID (1 << 0) | |
64 | ||
07749ef3 MT |
65 | #define I915_PTES(pte_len) (PAGE_SIZE / (pte_len)) |
66 | #define I915_PTE_MASK(pte_len) (I915_PTES(pte_len) - 1) | |
67 | #define I915_PDES 512 | |
68 | #define I915_PDE_MASK (I915_PDES - 1) | |
678d96fb | 69 | #define NUM_PTE(pde_shift) (1 << (pde_shift - PAGE_SHIFT)) |
07749ef3 MT |
70 | |
71 | #define GEN6_PTES I915_PTES(sizeof(gen6_pte_t)) | |
72 | #define GEN6_PD_SIZE (I915_PDES * PAGE_SIZE) | |
0260c420 | 73 | #define GEN6_PD_ALIGN (PAGE_SIZE * 16) |
678d96fb | 74 | #define GEN6_PDE_SHIFT 22 |
0260c420 BW |
75 | #define GEN6_PDE_VALID (1 << 0) |
76 | ||
77 | #define GEN7_PTE_CACHE_L3_LLC (3 << 1) | |
78 | ||
79 | #define BYT_PTE_SNOOPED_BY_CPU_CACHES (1 << 2) | |
80 | #define BYT_PTE_WRITEABLE (1 << 1) | |
81 | ||
82 | /* Cacheability Control is a 4-bit value. The low three bits are stored in bits | |
83 | * 3:1 of the PTE, while the fourth bit is stored in bit 11 of the PTE. | |
84 | */ | |
85 | #define HSW_CACHEABILITY_CONTROL(bits) ((((bits) & 0x7) << 1) | \ | |
86 | (((bits) & 0x8) << (11 - 3))) | |
87 | #define HSW_WB_LLC_AGE3 HSW_CACHEABILITY_CONTROL(0x2) | |
88 | #define HSW_WB_LLC_AGE0 HSW_CACHEABILITY_CONTROL(0x3) | |
89 | #define HSW_WB_ELLC_LLC_AGE3 HSW_CACHEABILITY_CONTROL(0x8) | |
90 | #define HSW_WB_ELLC_LLC_AGE0 HSW_CACHEABILITY_CONTROL(0xb) | |
91 | #define HSW_WT_ELLC_LLC_AGE3 HSW_CACHEABILITY_CONTROL(0x7) | |
92 | #define HSW_WT_ELLC_LLC_AGE0 HSW_CACHEABILITY_CONTROL(0x6) | |
93 | #define HSW_PTE_UNCACHED (0) | |
94 | #define HSW_GTT_ADDR_ENCODE(addr) ((addr) | (((addr) >> 28) & 0x7f0)) | |
95 | #define HSW_PTE_ADDR_ENCODE(addr) HSW_GTT_ADDR_ENCODE(addr) | |
96 | ||
97 | /* GEN8 legacy style address is defined as a 3 level page table: | |
98 | * 31:30 | 29:21 | 20:12 | 11:0 | |
99 | * PDPE | PDE | PTE | offset | |
100 | * The difference as compared to normal x86 3 level page table is the PDPEs are | |
101 | * programmed via register. | |
81ba8aef MT |
102 | * |
103 | * GEN8 48b legacy style address is defined as a 4 level page table: | |
104 | * 47:39 | 38:30 | 29:21 | 20:12 | 11:0 | |
105 | * PML4E | PDPE | PDE | PTE | offset | |
0260c420 | 106 | */ |
81ba8aef MT |
107 | #define GEN8_PML4ES_PER_PML4 512 |
108 | #define GEN8_PML4E_SHIFT 39 | |
762d9936 | 109 | #define GEN8_PML4E_MASK (GEN8_PML4ES_PER_PML4 - 1) |
0260c420 | 110 | #define GEN8_PDPE_SHIFT 30 |
81ba8aef MT |
111 | /* NB: GEN8_PDPE_MASK is untrue for 32b platforms, but it has no impact on 32b page |
112 | * tables */ | |
113 | #define GEN8_PDPE_MASK 0x1ff | |
0260c420 BW |
114 | #define GEN8_PDE_SHIFT 21 |
115 | #define GEN8_PDE_MASK 0x1ff | |
116 | #define GEN8_PTE_SHIFT 12 | |
117 | #define GEN8_PTE_MASK 0x1ff | |
76643600 | 118 | #define GEN8_LEGACY_PDPES 4 |
07749ef3 | 119 | #define GEN8_PTES I915_PTES(sizeof(gen8_pte_t)) |
0260c420 | 120 | |
81ba8aef MT |
121 | #define I915_PDPES_PER_PDP(dev) (USES_FULL_48BIT_PPGTT(dev) ?\ |
122 | GEN8_PML4ES_PER_PML4 : GEN8_LEGACY_PDPES) | |
6ac18502 | 123 | |
0260c420 BW |
124 | #define PPAT_UNCACHED_INDEX (_PAGE_PWT | _PAGE_PCD) |
125 | #define PPAT_CACHED_PDE_INDEX 0 /* WB LLC */ | |
126 | #define PPAT_CACHED_INDEX _PAGE_PAT /* WB LLCeLLC */ | |
127 | #define PPAT_DISPLAY_ELLC_INDEX _PAGE_PCD /* WT eLLC */ | |
128 | ||
ee0ce478 | 129 | #define CHV_PPAT_SNOOP (1<<6) |
0260c420 BW |
130 | #define GEN8_PPAT_AGE(x) (x<<4) |
131 | #define GEN8_PPAT_LLCeLLC (3<<2) | |
132 | #define GEN8_PPAT_LLCELLC (2<<2) | |
133 | #define GEN8_PPAT_LLC (1<<2) | |
134 | #define GEN8_PPAT_WB (3<<0) | |
135 | #define GEN8_PPAT_WT (2<<0) | |
136 | #define GEN8_PPAT_WC (1<<0) | |
137 | #define GEN8_PPAT_UC (0<<0) | |
138 | #define GEN8_PPAT_ELLC_OVERRIDE (0<<2) | |
139 | #define GEN8_PPAT(i, x) ((uint64_t) (x) << ((i) * 8)) | |
140 | ||
fe14d5f4 TU |
141 | enum i915_ggtt_view_type { |
142 | I915_GGTT_VIEW_NORMAL = 0, | |
8bd7ef16 JL |
143 | I915_GGTT_VIEW_ROTATED, |
144 | I915_GGTT_VIEW_PARTIAL, | |
50470bb0 TU |
145 | }; |
146 | ||
147 | struct intel_rotation_info { | |
1663b9d6 VS |
148 | struct { |
149 | /* tiles */ | |
6687c906 | 150 | unsigned int width, height, stride, offset; |
1663b9d6 | 151 | } plane[2]; |
fe14d5f4 TU |
152 | }; |
153 | ||
154 | struct i915_ggtt_view { | |
155 | enum i915_ggtt_view_type type; | |
156 | ||
8bd7ef16 JL |
157 | union { |
158 | struct { | |
088e0df4 | 159 | u64 offset; |
8bd7ef16 JL |
160 | unsigned int size; |
161 | } partial; | |
7723f47d | 162 | struct intel_rotation_info rotated; |
8bd7ef16 | 163 | } params; |
fe14d5f4 TU |
164 | }; |
165 | ||
166 | extern const struct i915_ggtt_view i915_ggtt_view_normal; | |
9abc4648 | 167 | extern const struct i915_ggtt_view i915_ggtt_view_rotated; |
fe14d5f4 | 168 | |
0260c420 | 169 | enum i915_cache_level; |
fe14d5f4 | 170 | |
0260c420 BW |
171 | /** |
172 | * A VMA represents a GEM BO that is bound into an address space. Therefore, a | |
173 | * VMA's presence cannot be guaranteed before binding, or after unbinding the | |
174 | * object into/from the address space. | |
175 | * | |
176 | * To make things as simple as possible (ie. no refcounting), a VMA's lifetime | |
177 | * will always be <= an objects lifetime. So object refcounting should cover us. | |
178 | */ | |
179 | struct i915_vma { | |
180 | struct drm_mm_node node; | |
181 | struct drm_i915_gem_object *obj; | |
182 | struct i915_address_space *vm; | |
49ef5294 | 183 | struct drm_i915_fence_reg *fence; |
247177dd | 184 | struct sg_table *pages; |
8ef8561f | 185 | void __iomem *iomap; |
de180033 | 186 | u64 size; |
d8923dcf | 187 | u64 display_alignment; |
0260c420 | 188 | |
3272db53 CW |
189 | unsigned int flags; |
190 | /** | |
191 | * How many users have pinned this object in GTT space. The following | |
192 | * users can each hold at most one reference: pwrite/pread, execbuffer | |
193 | * (objects are not allowed multiple times for the same batchbuffer), | |
194 | * and the framebuffer code. When switching/pageflipping, the | |
195 | * framebuffer code has at most two buffers pinned per crtc. | |
196 | * | |
197 | * In the worst case this is 1 + 1 + 1 + 2*2 = 7. That would fit into 3 | |
198 | * bits with absolutely no headroom. So use 4 bits. | |
199 | */ | |
200 | #define I915_VMA_PIN_MASK 0xf | |
305bc234 | 201 | #define I915_VMA_PIN_OVERFLOW BIT(5) |
b0decaf7 | 202 | |
aff43766 | 203 | /** Flags and address space this VMA is bound to */ |
305bc234 CW |
204 | #define I915_VMA_GLOBAL_BIND BIT(6) |
205 | #define I915_VMA_LOCAL_BIND BIT(7) | |
206 | #define I915_VMA_BIND_MASK (I915_VMA_GLOBAL_BIND | I915_VMA_LOCAL_BIND | I915_VMA_PIN_OVERFLOW) | |
3272db53 | 207 | |
05a20d09 CW |
208 | #define I915_VMA_GGTT BIT(8) |
209 | #define I915_VMA_CAN_FENCE BIT(9) | |
210 | #define I915_VMA_CLOSED BIT(10) | |
3272db53 CW |
211 | |
212 | unsigned int active; | |
213 | struct i915_gem_active last_read[I915_NUM_ENGINES]; | |
49ef5294 | 214 | struct i915_gem_active last_fence; |
aff43766 | 215 | |
fe14d5f4 TU |
216 | /** |
217 | * Support different GGTT views into the same object. | |
218 | * This means there can be multiple VMA mappings per object and per VM. | |
219 | * i915_ggtt_view_type is used to distinguish between those entries. | |
220 | * The default one of zero (I915_GGTT_VIEW_NORMAL) is default and also | |
221 | * assumed in GEM functions which take no ggtt view parameter. | |
222 | */ | |
223 | struct i915_ggtt_view ggtt_view; | |
224 | ||
0260c420 | 225 | /** This object's place on the active/inactive lists */ |
1c7f4bca | 226 | struct list_head vm_link; |
0260c420 | 227 | |
1c7f4bca | 228 | struct list_head obj_link; /* Link in the object's VMA list */ |
0260c420 BW |
229 | |
230 | /** This vma's place in the batchbuffer or on the eviction list */ | |
231 | struct list_head exec_list; | |
232 | ||
233 | /** | |
234 | * Used for performing relocations during execbuffer insertion. | |
235 | */ | |
236 | struct hlist_node exec_node; | |
237 | unsigned long exec_handle; | |
238 | struct drm_i915_gem_exec_object2 *exec_entry; | |
0260c420 BW |
239 | }; |
240 | ||
81a8aa4a CW |
241 | struct i915_vma * |
242 | i915_vma_create(struct drm_i915_gem_object *obj, | |
243 | struct i915_address_space *vm, | |
244 | const struct i915_ggtt_view *view); | |
19880c4a | 245 | void i915_vma_unpin_and_release(struct i915_vma **p_vma); |
81a8aa4a | 246 | |
3272db53 CW |
247 | static inline bool i915_vma_is_ggtt(const struct i915_vma *vma) |
248 | { | |
249 | return vma->flags & I915_VMA_GGTT; | |
250 | } | |
251 | ||
05a20d09 CW |
252 | static inline bool i915_vma_is_map_and_fenceable(const struct i915_vma *vma) |
253 | { | |
254 | return vma->flags & I915_VMA_CAN_FENCE; | |
255 | } | |
256 | ||
3272db53 CW |
257 | static inline bool i915_vma_is_closed(const struct i915_vma *vma) |
258 | { | |
259 | return vma->flags & I915_VMA_CLOSED; | |
260 | } | |
261 | ||
b0decaf7 CW |
262 | static inline unsigned int i915_vma_get_active(const struct i915_vma *vma) |
263 | { | |
264 | return vma->active; | |
265 | } | |
266 | ||
267 | static inline bool i915_vma_is_active(const struct i915_vma *vma) | |
268 | { | |
269 | return i915_vma_get_active(vma); | |
270 | } | |
271 | ||
272 | static inline void i915_vma_set_active(struct i915_vma *vma, | |
273 | unsigned int engine) | |
274 | { | |
275 | vma->active |= BIT(engine); | |
276 | } | |
277 | ||
278 | static inline void i915_vma_clear_active(struct i915_vma *vma, | |
279 | unsigned int engine) | |
280 | { | |
281 | vma->active &= ~BIT(engine); | |
282 | } | |
283 | ||
284 | static inline bool i915_vma_has_active_engine(const struct i915_vma *vma, | |
285 | unsigned int engine) | |
286 | { | |
287 | return vma->active & BIT(engine); | |
288 | } | |
289 | ||
bde13ebd CW |
290 | static inline u32 i915_ggtt_offset(const struct i915_vma *vma) |
291 | { | |
292 | GEM_BUG_ON(!i915_vma_is_ggtt(vma)); | |
293 | GEM_BUG_ON(!vma->node.allocated); | |
294 | GEM_BUG_ON(upper_32_bits(vma->node.start)); | |
295 | GEM_BUG_ON(upper_32_bits(vma->node.start + vma->node.size - 1)); | |
296 | return lower_32_bits(vma->node.start); | |
297 | } | |
298 | ||
44159ddb | 299 | struct i915_page_dma { |
d7b3de91 | 300 | struct page *page; |
44159ddb MK |
301 | union { |
302 | dma_addr_t daddr; | |
303 | ||
304 | /* For gen6/gen7 only. This is the offset in the GGTT | |
305 | * where the page directory entries for PPGTT begin | |
306 | */ | |
307 | uint32_t ggtt_offset; | |
308 | }; | |
309 | }; | |
310 | ||
567047be MK |
311 | #define px_base(px) (&(px)->base) |
312 | #define px_page(px) (px_base(px)->page) | |
313 | #define px_dma(px) (px_base(px)->daddr) | |
314 | ||
44159ddb MK |
315 | struct i915_page_table { |
316 | struct i915_page_dma base; | |
678d96fb BW |
317 | |
318 | unsigned long *used_ptes; | |
d7b3de91 BW |
319 | }; |
320 | ||
ec565b3c | 321 | struct i915_page_directory { |
44159ddb | 322 | struct i915_page_dma base; |
7324cc04 | 323 | |
33c8819f | 324 | unsigned long *used_pdes; |
ec565b3c | 325 | struct i915_page_table *page_table[I915_PDES]; /* PDEs */ |
d7b3de91 BW |
326 | }; |
327 | ||
ec565b3c | 328 | struct i915_page_directory_pointer { |
6ac18502 MT |
329 | struct i915_page_dma base; |
330 | ||
331 | unsigned long *used_pdpes; | |
332 | struct i915_page_directory **page_directory; | |
d7b3de91 BW |
333 | }; |
334 | ||
81ba8aef MT |
335 | struct i915_pml4 { |
336 | struct i915_page_dma base; | |
337 | ||
338 | DECLARE_BITMAP(used_pml4es, GEN8_PML4ES_PER_PML4); | |
339 | struct i915_page_directory_pointer *pdps[GEN8_PML4ES_PER_PML4]; | |
340 | }; | |
341 | ||
0260c420 BW |
342 | struct i915_address_space { |
343 | struct drm_mm mm; | |
344 | struct drm_device *dev; | |
2bfa996e CW |
345 | /* Every address space belongs to a struct file - except for the global |
346 | * GTT that is owned by the driver (and so @file is set to NULL). In | |
347 | * principle, no information should leak from one context to another | |
348 | * (or between files/processes etc) unless explicitly shared by the | |
349 | * owner. Tracking the owner is important in order to free up per-file | |
350 | * objects along with the file, to aide resource tracking, and to | |
351 | * assign blame. | |
352 | */ | |
353 | struct drm_i915_file_private *file; | |
0260c420 | 354 | struct list_head global_link; |
c44ef60e MK |
355 | u64 start; /* Start offset always 0 for dri2 */ |
356 | u64 total; /* size addr space maps (ex. 2GB for ggtt) */ | |
0260c420 | 357 | |
50e046b6 CW |
358 | bool closed; |
359 | ||
8bcdd0f7 | 360 | struct i915_page_dma scratch_page; |
79ab9370 MK |
361 | struct i915_page_table *scratch_pt; |
362 | struct i915_page_directory *scratch_pd; | |
69ab76fd | 363 | struct i915_page_directory_pointer *scratch_pdp; /* GEN8+ & 48b PPGTT */ |
0260c420 BW |
364 | |
365 | /** | |
366 | * List of objects currently involved in rendering. | |
367 | * | |
368 | * Includes buffers having the contents of their GPU caches | |
97b2a6a1 | 369 | * flushed, not necessarily primitives. last_read_req |
0260c420 BW |
370 | * represents when the rendering involved will be completed. |
371 | * | |
372 | * A reference is held on the buffer while on this list. | |
373 | */ | |
374 | struct list_head active_list; | |
375 | ||
376 | /** | |
377 | * LRU list of objects which are not in the ringbuffer and | |
378 | * are ready to unbind, but are still in the GTT. | |
379 | * | |
97b2a6a1 | 380 | * last_read_req is NULL while an object is in this list. |
0260c420 BW |
381 | * |
382 | * A reference is not held on the buffer while on this list, | |
383 | * as merely being GTT-bound shouldn't prevent its being | |
384 | * freed, and we'll pull it off the list in the free path. | |
385 | */ | |
386 | struct list_head inactive_list; | |
387 | ||
50e046b6 CW |
388 | /** |
389 | * List of vma that have been unbound. | |
390 | * | |
391 | * A reference is not held on the buffer while on this list. | |
392 | */ | |
393 | struct list_head unbound_list; | |
394 | ||
0260c420 | 395 | /* FIXME: Need a more generic return type */ |
07749ef3 MT |
396 | gen6_pte_t (*pte_encode)(dma_addr_t addr, |
397 | enum i915_cache_level level, | |
398 | bool valid, u32 flags); /* Create a valid PTE */ | |
f329f5f6 DV |
399 | /* flags for pte_encode */ |
400 | #define PTE_READ_ONLY (1<<0) | |
678d96fb BW |
401 | int (*allocate_va_range)(struct i915_address_space *vm, |
402 | uint64_t start, | |
403 | uint64_t length); | |
0260c420 BW |
404 | void (*clear_range)(struct i915_address_space *vm, |
405 | uint64_t start, | |
406 | uint64_t length, | |
407 | bool use_scratch); | |
d6473f56 CW |
408 | void (*insert_page)(struct i915_address_space *vm, |
409 | dma_addr_t addr, | |
410 | uint64_t offset, | |
411 | enum i915_cache_level cache_level, | |
412 | u32 flags); | |
0260c420 BW |
413 | void (*insert_entries)(struct i915_address_space *vm, |
414 | struct sg_table *st, | |
415 | uint64_t start, | |
24f3a8cf | 416 | enum i915_cache_level cache_level, u32 flags); |
0260c420 | 417 | void (*cleanup)(struct i915_address_space *vm); |
777dc5bb DV |
418 | /** Unmap an object from an address space. This usually consists of |
419 | * setting the valid PTE entries to a reserved scratch page. */ | |
420 | void (*unbind_vma)(struct i915_vma *vma); | |
421 | /* Map an object into an address space with the given cache flags. */ | |
70b9f6f8 DV |
422 | int (*bind_vma)(struct i915_vma *vma, |
423 | enum i915_cache_level cache_level, | |
424 | u32 flags); | |
0260c420 BW |
425 | }; |
426 | ||
2bfa996e | 427 | #define i915_is_ggtt(V) (!(V)->file) |
596c5923 | 428 | |
0260c420 BW |
429 | /* The Graphics Translation Table is the way in which GEN hardware translates a |
430 | * Graphics Virtual Address into a Physical Address. In addition to the normal | |
431 | * collateral associated with any va->pa translations GEN hardware also has a | |
432 | * portion of the GTT which can be mapped by the CPU and remain both coherent | |
433 | * and correct (in cases like swizzling). That region is referred to as GMADR in | |
434 | * the spec. | |
435 | */ | |
62106b4f | 436 | struct i915_ggtt { |
0260c420 | 437 | struct i915_address_space base; |
f7bbe788 | 438 | struct io_mapping mappable; /* Mapping to our CPU mappable region */ |
0260c420 | 439 | |
c44ef60e | 440 | size_t stolen_size; /* Total size of stolen memory */ |
a9da512b | 441 | size_t stolen_usable_size; /* Total size minus BIOS reserved */ |
274008e8 SAK |
442 | size_t stolen_reserved_base; |
443 | size_t stolen_reserved_size; | |
c44ef60e | 444 | u64 mappable_end; /* End offset that we can CPU map */ |
0260c420 BW |
445 | phys_addr_t mappable_base; /* PA of our GMADR */ |
446 | ||
447 | /** "Graphics Stolen Memory" holds the global PTEs */ | |
448 | void __iomem *gsm; | |
449 | ||
450 | bool do_idle_maps; | |
451 | ||
452 | int mtrr; | |
0260c420 BW |
453 | }; |
454 | ||
455 | struct i915_hw_ppgtt { | |
456 | struct i915_address_space base; | |
457 | struct kref ref; | |
458 | struct drm_mm_node node; | |
563222a7 | 459 | unsigned long pd_dirty_rings; |
d7b3de91 | 460 | union { |
81ba8aef MT |
461 | struct i915_pml4 pml4; /* GEN8+ & 48b PPGTT */ |
462 | struct i915_page_directory_pointer pdp; /* GEN8+ */ | |
463 | struct i915_page_directory pd; /* GEN6-7 */ | |
d7b3de91 | 464 | }; |
0260c420 | 465 | |
678d96fb BW |
466 | gen6_pte_t __iomem *pd_addr; |
467 | ||
0260c420 BW |
468 | int (*enable)(struct i915_hw_ppgtt *ppgtt); |
469 | int (*switch_mm)(struct i915_hw_ppgtt *ppgtt, | |
e85b26dc | 470 | struct drm_i915_gem_request *req); |
0260c420 BW |
471 | void (*debug_dump)(struct i915_hw_ppgtt *ppgtt, struct seq_file *m); |
472 | }; | |
473 | ||
731f74c5 DG |
474 | /* |
475 | * gen6_for_each_pde() iterates over every pde from start until start+length. | |
476 | * If start and start+length are not perfectly divisible, the macro will round | |
477 | * down and up as needed. Start=0 and length=2G effectively iterates over | |
478 | * every PDE in the system. The macro modifies ALL its parameters except 'pd', | |
479 | * so each of the other parameters should preferably be a simple variable, or | |
480 | * at most an lvalue with no side-effects! | |
678d96fb | 481 | */ |
731f74c5 DG |
482 | #define gen6_for_each_pde(pt, pd, start, length, iter) \ |
483 | for (iter = gen6_pde_index(start); \ | |
484 | length > 0 && iter < I915_PDES && \ | |
485 | (pt = (pd)->page_table[iter], true); \ | |
486 | ({ u32 temp = ALIGN(start+1, 1 << GEN6_PDE_SHIFT); \ | |
487 | temp = min(temp - start, length); \ | |
488 | start += temp, length -= temp; }), ++iter) | |
489 | ||
490 | #define gen6_for_all_pdes(pt, pd, iter) \ | |
491 | for (iter = 0; \ | |
492 | iter < I915_PDES && \ | |
493 | (pt = (pd)->page_table[iter], true); \ | |
494 | ++iter) | |
09942c65 | 495 | |
678d96fb BW |
496 | static inline uint32_t i915_pte_index(uint64_t address, uint32_t pde_shift) |
497 | { | |
498 | const uint32_t mask = NUM_PTE(pde_shift) - 1; | |
499 | ||
500 | return (address >> PAGE_SHIFT) & mask; | |
501 | } | |
502 | ||
503 | /* Helper to counts the number of PTEs within the given length. This count | |
504 | * does not cross a page table boundary, so the max value would be | |
505 | * GEN6_PTES for GEN6, and GEN8_PTES for GEN8. | |
506 | */ | |
507 | static inline uint32_t i915_pte_count(uint64_t addr, size_t length, | |
508 | uint32_t pde_shift) | |
509 | { | |
69603dbb | 510 | const uint64_t mask = ~((1ULL << pde_shift) - 1); |
678d96fb BW |
511 | uint64_t end; |
512 | ||
513 | WARN_ON(length == 0); | |
514 | WARN_ON(offset_in_page(addr|length)); | |
515 | ||
516 | end = addr + length; | |
517 | ||
518 | if ((addr & mask) != (end & mask)) | |
519 | return NUM_PTE(pde_shift) - i915_pte_index(addr, pde_shift); | |
520 | ||
521 | return i915_pte_index(end, pde_shift) - i915_pte_index(addr, pde_shift); | |
522 | } | |
523 | ||
524 | static inline uint32_t i915_pde_index(uint64_t addr, uint32_t shift) | |
525 | { | |
526 | return (addr >> shift) & I915_PDE_MASK; | |
527 | } | |
528 | ||
529 | static inline uint32_t gen6_pte_index(uint32_t addr) | |
530 | { | |
531 | return i915_pte_index(addr, GEN6_PDE_SHIFT); | |
532 | } | |
533 | ||
534 | static inline size_t gen6_pte_count(uint32_t addr, uint32_t length) | |
535 | { | |
536 | return i915_pte_count(addr, length, GEN6_PDE_SHIFT); | |
537 | } | |
538 | ||
539 | static inline uint32_t gen6_pde_index(uint32_t addr) | |
540 | { | |
541 | return i915_pde_index(addr, GEN6_PDE_SHIFT); | |
542 | } | |
543 | ||
9271d959 MT |
544 | /* Equivalent to the gen6 version, For each pde iterates over every pde |
545 | * between from start until start + length. On gen8+ it simply iterates | |
546 | * over every page directory entry in a page directory. | |
547 | */ | |
e8ebd8e2 DG |
548 | #define gen8_for_each_pde(pt, pd, start, length, iter) \ |
549 | for (iter = gen8_pde_index(start); \ | |
550 | length > 0 && iter < I915_PDES && \ | |
551 | (pt = (pd)->page_table[iter], true); \ | |
552 | ({ u64 temp = ALIGN(start+1, 1 << GEN8_PDE_SHIFT); \ | |
553 | temp = min(temp - start, length); \ | |
554 | start += temp, length -= temp; }), ++iter) | |
555 | ||
556 | #define gen8_for_each_pdpe(pd, pdp, start, length, iter) \ | |
557 | for (iter = gen8_pdpe_index(start); \ | |
558 | length > 0 && iter < I915_PDPES_PER_PDP(dev) && \ | |
559 | (pd = (pdp)->page_directory[iter], true); \ | |
560 | ({ u64 temp = ALIGN(start+1, 1 << GEN8_PDPE_SHIFT); \ | |
561 | temp = min(temp - start, length); \ | |
562 | start += temp, length -= temp; }), ++iter) | |
563 | ||
564 | #define gen8_for_each_pml4e(pdp, pml4, start, length, iter) \ | |
565 | for (iter = gen8_pml4e_index(start); \ | |
566 | length > 0 && iter < GEN8_PML4ES_PER_PML4 && \ | |
567 | (pdp = (pml4)->pdps[iter], true); \ | |
568 | ({ u64 temp = ALIGN(start+1, 1ULL << GEN8_PML4E_SHIFT); \ | |
569 | temp = min(temp - start, length); \ | |
570 | start += temp, length -= temp; }), ++iter) | |
762d9936 | 571 | |
9271d959 MT |
572 | static inline uint32_t gen8_pte_index(uint64_t address) |
573 | { | |
574 | return i915_pte_index(address, GEN8_PDE_SHIFT); | |
575 | } | |
576 | ||
577 | static inline uint32_t gen8_pde_index(uint64_t address) | |
578 | { | |
579 | return i915_pde_index(address, GEN8_PDE_SHIFT); | |
580 | } | |
581 | ||
582 | static inline uint32_t gen8_pdpe_index(uint64_t address) | |
583 | { | |
584 | return (address >> GEN8_PDPE_SHIFT) & GEN8_PDPE_MASK; | |
585 | } | |
586 | ||
587 | static inline uint32_t gen8_pml4e_index(uint64_t address) | |
588 | { | |
762d9936 | 589 | return (address >> GEN8_PML4E_SHIFT) & GEN8_PML4E_MASK; |
9271d959 MT |
590 | } |
591 | ||
33c8819f MT |
592 | static inline size_t gen8_pte_count(uint64_t address, uint64_t length) |
593 | { | |
594 | return i915_pte_count(address, length, GEN8_PDE_SHIFT); | |
595 | } | |
596 | ||
d852c7bf MK |
597 | static inline dma_addr_t |
598 | i915_page_dir_dma_addr(const struct i915_hw_ppgtt *ppgtt, const unsigned n) | |
599 | { | |
600 | return test_bit(n, ppgtt->pdp.used_pdpes) ? | |
567047be | 601 | px_dma(ppgtt->pdp.page_directory[n]) : |
79ab9370 | 602 | px_dma(ppgtt->base.scratch_pd); |
d852c7bf MK |
603 | } |
604 | ||
97d6d7ab CW |
605 | int i915_ggtt_probe_hw(struct drm_i915_private *dev_priv); |
606 | int i915_ggtt_init_hw(struct drm_i915_private *dev_priv); | |
607 | int i915_ggtt_enable_hw(struct drm_i915_private *dev_priv); | |
f6b9d5ca | 608 | int i915_gem_init_ggtt(struct drm_i915_private *dev_priv); |
97d6d7ab | 609 | void i915_ggtt_cleanup_hw(struct drm_i915_private *dev_priv); |
ee960be7 | 610 | |
82460d97 | 611 | int i915_ppgtt_init_hw(struct drm_device *dev); |
ee960be7 | 612 | void i915_ppgtt_release(struct kref *kref); |
2bfa996e | 613 | struct i915_hw_ppgtt *i915_ppgtt_create(struct drm_i915_private *dev_priv, |
4d884705 | 614 | struct drm_i915_file_private *fpriv); |
ee960be7 DV |
615 | static inline void i915_ppgtt_get(struct i915_hw_ppgtt *ppgtt) |
616 | { | |
617 | if (ppgtt) | |
618 | kref_get(&ppgtt->ref); | |
619 | } | |
620 | static inline void i915_ppgtt_put(struct i915_hw_ppgtt *ppgtt) | |
621 | { | |
622 | if (ppgtt) | |
623 | kref_put(&ppgtt->ref, i915_ppgtt_release); | |
624 | } | |
0260c420 | 625 | |
dc97997a | 626 | void i915_check_and_clear_faults(struct drm_i915_private *dev_priv); |
0260c420 BW |
627 | void i915_gem_suspend_gtt_mappings(struct drm_device *dev); |
628 | void i915_gem_restore_gtt_mappings(struct drm_device *dev); | |
629 | ||
630 | int __must_check i915_gem_gtt_prepare_object(struct drm_i915_gem_object *obj); | |
631 | void i915_gem_gtt_finish_object(struct drm_i915_gem_object *obj); | |
632 | ||
59bfa124 | 633 | /* Flags used by pin/bind&friends. */ |
305bc234 CW |
634 | #define PIN_NONBLOCK BIT(0) |
635 | #define PIN_MAPPABLE BIT(1) | |
636 | #define PIN_ZONE_4G BIT(2) | |
82118877 | 637 | #define PIN_NONFAULT BIT(3) |
305bc234 CW |
638 | |
639 | #define PIN_MBZ BIT(5) /* I915_VMA_PIN_OVERFLOW */ | |
640 | #define PIN_GLOBAL BIT(6) /* I915_VMA_GLOBAL_BIND */ | |
641 | #define PIN_USER BIT(7) /* I915_VMA_LOCAL_BIND */ | |
642 | #define PIN_UPDATE BIT(8) | |
643 | ||
644 | #define PIN_HIGH BIT(9) | |
645 | #define PIN_OFFSET_BIAS BIT(10) | |
646 | #define PIN_OFFSET_FIXED BIT(11) | |
59bfa124 CW |
647 | #define PIN_OFFSET_MASK (~4095) |
648 | ||
305bc234 CW |
649 | int __i915_vma_do_pin(struct i915_vma *vma, |
650 | u64 size, u64 alignment, u64 flags); | |
651 | static inline int __must_check | |
652 | i915_vma_pin(struct i915_vma *vma, u64 size, u64 alignment, u64 flags) | |
653 | { | |
654 | BUILD_BUG_ON(PIN_MBZ != I915_VMA_PIN_OVERFLOW); | |
655 | BUILD_BUG_ON(PIN_GLOBAL != I915_VMA_GLOBAL_BIND); | |
656 | BUILD_BUG_ON(PIN_USER != I915_VMA_LOCAL_BIND); | |
657 | ||
658 | /* Pin early to prevent the shrinker/eviction logic from destroying | |
659 | * our vma as we insert and bind. | |
660 | */ | |
661 | if (likely(((++vma->flags ^ flags) & I915_VMA_BIND_MASK) == 0)) | |
662 | return 0; | |
663 | ||
664 | return __i915_vma_do_pin(vma, size, alignment, flags); | |
665 | } | |
666 | ||
20dfbde4 CW |
667 | static inline int i915_vma_pin_count(const struct i915_vma *vma) |
668 | { | |
3272db53 | 669 | return vma->flags & I915_VMA_PIN_MASK; |
20dfbde4 CW |
670 | } |
671 | ||
672 | static inline bool i915_vma_is_pinned(const struct i915_vma *vma) | |
673 | { | |
674 | return i915_vma_pin_count(vma); | |
675 | } | |
676 | ||
677 | static inline void __i915_vma_pin(struct i915_vma *vma) | |
678 | { | |
3272db53 | 679 | vma->flags++; |
305bc234 | 680 | GEM_BUG_ON(vma->flags & I915_VMA_PIN_OVERFLOW); |
20dfbde4 CW |
681 | } |
682 | ||
683 | static inline void __i915_vma_unpin(struct i915_vma *vma) | |
684 | { | |
685 | GEM_BUG_ON(!i915_vma_is_pinned(vma)); | |
3272db53 | 686 | vma->flags--; |
20dfbde4 CW |
687 | } |
688 | ||
689 | static inline void i915_vma_unpin(struct i915_vma *vma) | |
690 | { | |
691 | GEM_BUG_ON(!drm_mm_node_allocated(&vma->node)); | |
692 | __i915_vma_unpin(vma); | |
693 | } | |
694 | ||
8ef8561f CW |
695 | /** |
696 | * i915_vma_pin_iomap - calls ioremap_wc to map the GGTT VMA via the aperture | |
697 | * @vma: VMA to iomap | |
698 | * | |
699 | * The passed in VMA has to be pinned in the global GTT mappable region. | |
700 | * An extra pinning of the VMA is acquired for the return iomapping, | |
701 | * the caller must call i915_vma_unpin_iomap to relinquish the pinning | |
702 | * after the iomapping is no longer required. | |
703 | * | |
704 | * Callers must hold the struct_mutex. | |
705 | * | |
706 | * Returns a valid iomapped pointer or ERR_PTR. | |
707 | */ | |
708 | void __iomem *i915_vma_pin_iomap(struct i915_vma *vma); | |
406ea8d2 | 709 | #define IO_ERR_PTR(x) ((void __iomem *)ERR_PTR(x)) |
8ef8561f CW |
710 | |
711 | /** | |
712 | * i915_vma_unpin_iomap - unpins the mapping returned from i915_vma_iomap | |
713 | * @vma: VMA to unpin | |
714 | * | |
715 | * Unpins the previously iomapped VMA from i915_vma_pin_iomap(). | |
716 | * | |
717 | * Callers must hold the struct_mutex. This function is only valid to be | |
718 | * called on a VMA previously iomapped by the caller with i915_vma_pin_iomap(). | |
719 | */ | |
720 | static inline void i915_vma_unpin_iomap(struct i915_vma *vma) | |
721 | { | |
722 | lockdep_assert_held(&vma->vm->dev->struct_mutex); | |
8ef8561f | 723 | GEM_BUG_ON(vma->iomap == NULL); |
20dfbde4 | 724 | i915_vma_unpin(vma); |
8ef8561f CW |
725 | } |
726 | ||
8b797af1 CW |
727 | static inline struct page *i915_vma_first_page(struct i915_vma *vma) |
728 | { | |
729 | GEM_BUG_ON(!vma->pages); | |
730 | return sg_page(vma->pages->sgl); | |
731 | } | |
732 | ||
0260c420 | 733 | #endif |