[deliverable/linux.git] / drivers / gpu / drm / i915 / i915_gem_gtt.h

/*
 * Copyright © 2014 Intel Corporation
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice (including the next
 * paragraph) shall be included in all copies or substantial portions of the
 * Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
 * IN THE SOFTWARE.
 *
 * Please try to maintain the following order within this file unless it makes
 * sense to do otherwise. From top to bottom:
 * 1. typedefs
 * 2. #defines, and macros
 * 3. structure definitions
 * 4. function prototypes
 *
 * Within each section, please try to order by generation in ascending order,
 * from top to bottom (ie. gen6 on the top, gen8 on the bottom).
 */

#ifndef __I915_GEM_GTT_H__
#define __I915_GEM_GTT_H__

struct drm_i915_file_private;

typedef uint32_t gen6_pte_t;
typedef uint64_t gen8_pte_t;
typedef uint64_t gen8_pde_t;

#define gtt_total_entries(gtt) ((gtt).base.total >> PAGE_SHIFT)


/* gen6-hsw has bit 11-4 for physical addr bit 39-32 */
#define GEN6_GTT_ADDR_ENCODE(addr)	((addr) | (((addr) >> 28) & 0xff0))
#define GEN6_PTE_ADDR_ENCODE(addr)	GEN6_GTT_ADDR_ENCODE(addr)
#define GEN6_PDE_ADDR_ENCODE(addr)	GEN6_GTT_ADDR_ENCODE(addr)
#define GEN6_PTE_CACHE_LLC		(2 << 1)
#define GEN6_PTE_UNCACHED		(1 << 1)
#define GEN6_PTE_VALID			(1 << 0)

#define I915_PTES(pte_len)		(PAGE_SIZE / (pte_len))
#define I915_PTE_MASK(pte_len)		(I915_PTES(pte_len) - 1)
#define I915_PDES			512
#define I915_PDE_MASK			(I915_PDES - 1)
#define NUM_PTE(pde_shift)     (1 << (pde_shift - PAGE_SHIFT))

#define GEN6_PTES			I915_PTES(sizeof(gen6_pte_t))
#define GEN6_PD_SIZE		        (I915_PDES * PAGE_SIZE)
#define GEN6_PD_ALIGN			(PAGE_SIZE * 16)
#define GEN6_PDE_SHIFT			22
#define GEN6_PDE_VALID			(1 << 0)

#define GEN7_PTE_CACHE_L3_LLC		(3 << 1)

#define BYT_PTE_SNOOPED_BY_CPU_CACHES	(1 << 2)
#define BYT_PTE_WRITEABLE		(1 << 1)

/* Cacheability Control is a 4-bit value. The low three bits are stored in bits
 * 3:1 of the PTE, while the fourth bit is stored in bit 11 of the PTE.
 */
#define HSW_CACHEABILITY_CONTROL(bits)	((((bits) & 0x7) << 1) | \
					 (((bits) & 0x8) << (11 - 3)))
#define HSW_WB_LLC_AGE3			HSW_CACHEABILITY_CONTROL(0x2)
#define HSW_WB_LLC_AGE0			HSW_CACHEABILITY_CONTROL(0x3)
#define HSW_WB_ELLC_LLC_AGE3		HSW_CACHEABILITY_CONTROL(0x8)
#define HSW_WB_ELLC_LLC_AGE0		HSW_CACHEABILITY_CONTROL(0xb)
#define HSW_WT_ELLC_LLC_AGE3		HSW_CACHEABILITY_CONTROL(0x7)
#define HSW_WT_ELLC_LLC_AGE0		HSW_CACHEABILITY_CONTROL(0x6)
#define HSW_PTE_UNCACHED		(0)
#define HSW_GTT_ADDR_ENCODE(addr)	((addr) | (((addr) >> 28) & 0x7f0))
#define HSW_PTE_ADDR_ENCODE(addr)	HSW_GTT_ADDR_ENCODE(addr)

/* GEN8 legacy style address is defined as a 3 level page table:
 * 31:30 | 29:21 | 20:12 |  11:0
 * PDPE  |  PDE  |  PTE  | offset
 * The difference as compared to normal x86 3 level page table is the PDPEs are
 * programmed via register.
 */
#define GEN8_PDPE_SHIFT			30
#define GEN8_PDPE_MASK			0x3
#define GEN8_PDE_SHIFT			21
#define GEN8_PDE_MASK			0x1ff
#define GEN8_PTE_SHIFT			12
#define GEN8_PTE_MASK			0x1ff
#define GEN8_LEGACY_PDPES		4
#define GEN8_PTES			I915_PTES(sizeof(gen8_pte_t))

#define PPAT_UNCACHED_INDEX		(_PAGE_PWT | _PAGE_PCD)
#define PPAT_CACHED_PDE_INDEX		0 /* WB LLC */
#define PPAT_CACHED_INDEX		_PAGE_PAT /* WB LLCeLLC */
#define PPAT_DISPLAY_ELLC_INDEX		_PAGE_PCD /* WT eLLC */

#define CHV_PPAT_SNOOP			(1<<6)
#define GEN8_PPAT_AGE(x)		(x<<4)
#define GEN8_PPAT_LLCeLLC		(3<<2)
#define GEN8_PPAT_LLCELLC		(2<<2)
#define GEN8_PPAT_LLC			(1<<2)
#define GEN8_PPAT_WB			(3<<0)
#define GEN8_PPAT_WT			(2<<0)
#define GEN8_PPAT_WC			(1<<0)
#define GEN8_PPAT_UC			(0<<0)
#define GEN8_PPAT_ELLC_OVERRIDE		(0<<2)
#define GEN8_PPAT(i, x)			((uint64_t) (x) << ((i) * 8))

enum i915_ggtt_view_type {
	I915_GGTT_VIEW_NORMAL = 0,
	I915_GGTT_VIEW_ROTATED,
	I915_GGTT_VIEW_PARTIAL,
};

struct intel_rotation_info {
	unsigned int height;
	unsigned int pitch;
	uint32_t pixel_format;
	uint64_t fb_modifier;
	unsigned int width_pages, height_pages;
	uint64_t size;
};

struct i915_ggtt_view {
	enum i915_ggtt_view_type type;

	union {
		struct {
			unsigned long offset;
			unsigned int size;
		} partial;
	} params;

	struct sg_table *pages;

	union {
		struct intel_rotation_info rotation_info;
	};
};

extern const struct i915_ggtt_view i915_ggtt_view_normal;
extern const struct i915_ggtt_view i915_ggtt_view_rotated;

enum i915_cache_level;

/**
 * A VMA represents a GEM BO that is bound into an address space. Therefore, a
 * VMA's presence cannot be guaranteed before binding, or after unbinding the
 * object into/from the address space.
 *
 * To make things as simple as possible (ie. no refcounting), a VMA's lifetime
 * will always be <= an objects lifetime. So object refcounting should cover us.
 */
struct i915_vma {
	struct drm_mm_node node;
	struct drm_i915_gem_object *obj;
	struct i915_address_space *vm;

	/** Flags and address space this VMA is bound to */
#define GLOBAL_BIND	(1<<0)
#define LOCAL_BIND	(1<<1)
	unsigned int bound : 4;

	/**
	 * Support different GGTT views into the same object.
	 * This means there can be multiple VMA mappings per object and per VM.
	 * i915_ggtt_view_type is used to distinguish between those entries.
	 * The default one of zero (I915_GGTT_VIEW_NORMAL) is default and also
	 * assumed in GEM functions which take no ggtt view parameter.
	 */
	struct i915_ggtt_view ggtt_view;

	/** This object's place on the active/inactive lists */
	struct list_head mm_list;

	struct list_head vma_link; /* Link in the object's VMA list */

	/** This vma's place in the batchbuffer or on the eviction list */
	struct list_head exec_list;

	/**
	 * Used for performing relocations during execbuffer insertion.
	 */
	struct hlist_node exec_node;
	unsigned long exec_handle;
	struct drm_i915_gem_exec_object2 *exec_entry;

	/**
	 * How many users have pinned this object in GTT space. The following
	 * users can each hold at most one reference: pwrite/pread, execbuffer
	 * (objects are not allowed multiple times for the same batchbuffer),
	 * and the framebuffer code. When switching/pageflipping, the
	 * framebuffer code has at most two buffers pinned per crtc.
	 *
	 * In the worst case this is 1 + 1 + 1 + 2*2 = 7. That would fit into 3
	 * bits with absolutely no headroom. So use 4 bits. */
	unsigned int pin_count:4;
#define DRM_I915_GEM_OBJECT_MAX_PIN_COUNT 0xf
};

struct i915_page_dma {
	struct page *page;
	union {
		dma_addr_t daddr;

		/* For gen6/gen7 only. This is the offset in the GGTT
		 * where the page directory entries for PPGTT begin
		 */
		uint32_t ggtt_offset;
	};
};

struct i915_page_table {
	struct i915_page_dma base;

	unsigned long *used_ptes;
};

struct i915_page_directory {
	struct i915_page_dma base;

	unsigned long *used_pdes;
	struct i915_page_table *page_table[I915_PDES]; /* PDEs */
};

struct i915_page_directory_pointer {
	/* struct page *page; */
	DECLARE_BITMAP(used_pdpes, GEN8_LEGACY_PDPES);
	struct i915_page_directory *page_directory[GEN8_LEGACY_PDPES];
};

struct i915_address_space {
	struct drm_mm mm;
	struct drm_device *dev;
	struct list_head global_link;
	u64 start;		/* Start offset always 0 for dri2 */
	u64 total;		/* size addr space maps (ex. 2GB for ggtt) */

	struct {
		dma_addr_t addr;
		struct page *page;
	} scratch;

	/**
	 * List of objects currently involved in rendering.
	 *
	 * Includes buffers having the contents of their GPU caches
	 * flushed, not necessarily primitives. last_read_req
	 * represents when the rendering involved will be completed.
	 *
	 * A reference is held on the buffer while on this list.
	 */
	struct list_head active_list;

	/**
	 * LRU list of objects which are not in the ringbuffer and
	 * are ready to unbind, but are still in the GTT.
	 *
	 * last_read_req is NULL while an object is in this list.
	 *
	 * A reference is not held on the buffer while on this list,
	 * as merely being GTT-bound shouldn't prevent its being
	 * freed, and we'll pull it off the list in the free path.
	 */
	struct list_head inactive_list;

	/* FIXME: Need a more generic return type */
	gen6_pte_t (*pte_encode)(dma_addr_t addr,
				 enum i915_cache_level level,
				 bool valid, u32 flags); /* Create a valid PTE */
	/* flags for pte_encode */
#define PTE_READ_ONLY	(1<<0)
	int (*allocate_va_range)(struct i915_address_space *vm,
				 uint64_t start,
				 uint64_t length);
	void (*clear_range)(struct i915_address_space *vm,
			    uint64_t start,
			    uint64_t length,
			    bool use_scratch);
	void (*insert_entries)(struct i915_address_space *vm,
			       struct sg_table *st,
			       uint64_t start,
			       enum i915_cache_level cache_level, u32 flags);
	void (*cleanup)(struct i915_address_space *vm);
	/** Unmap an object from an address space. This usually consists of
	 * setting the valid PTE entries to a reserved scratch page. */
	void (*unbind_vma)(struct i915_vma *vma);
	/* Map an object into an address space with the given cache flags. */
	int (*bind_vma)(struct i915_vma *vma,
			enum i915_cache_level cache_level,
			u32 flags);
};

/* The Graphics Translation Table is the way in which GEN hardware translates a
 * Graphics Virtual Address into a Physical Address. In addition to the normal
 * collateral associated with any va->pa translations GEN hardware also has a
 * portion of the GTT which can be mapped by the CPU and remain both coherent
 * and correct (in cases like swizzling). That region is referred to as GMADR in
 * the spec.
 */
struct i915_gtt {
	struct i915_address_space base;

	size_t stolen_size;		/* Total size of stolen memory */
	u64 mappable_end;		/* End offset that we can CPU map */
	struct io_mapping *mappable;	/* Mapping to our CPU mappable region */
	phys_addr_t mappable_base;	/* PA of our GMADR */

	/** "Graphics Stolen Memory" holds the global PTEs */
	void __iomem *gsm;

	bool do_idle_maps;

	int mtrr;

	/* global gtt ops */
	int (*gtt_probe)(struct drm_device *dev, u64 *gtt_total,
			  size_t *stolen, phys_addr_t *mappable_base,
			  u64 *mappable_end);
};

struct i915_hw_ppgtt {
	struct i915_address_space base;
	struct kref ref;
	struct drm_mm_node node;
	unsigned long pd_dirty_rings;
	union {
		struct i915_page_directory_pointer pdp;
		struct i915_page_directory pd;
	};

	struct i915_page_table *scratch_pt;
	struct i915_page_directory *scratch_pd;

	struct drm_i915_file_private *file_priv;

	gen6_pte_t __iomem *pd_addr;

	int (*enable)(struct i915_hw_ppgtt *ppgtt);
	int (*switch_mm)(struct i915_hw_ppgtt *ppgtt,
			 struct drm_i915_gem_request *req);
	void (*debug_dump)(struct i915_hw_ppgtt *ppgtt, struct seq_file *m);
};

/* For each pde iterates over every pde between from start until start + length.
 * If start, and start+length are not perfectly divisible, the macro will round
 * down, and up as needed. The macro modifies pde, start, and length. Dev is
 * only used to differentiate shift values. Temp is temp.  On gen6/7, start = 0,
 * and length = 2G effectively iterates over every PDE in the system.
 *
 * XXX: temp is not actually needed, but it saves doing the ALIGN operation.
 */
#define gen6_for_each_pde(pt, pd, start, length, temp, iter) \
	for (iter = gen6_pde_index(start); \
	     pt = (pd)->page_table[iter], length > 0 && iter < I915_PDES; \
	     iter++, \
	     temp = ALIGN(start+1, 1 << GEN6_PDE_SHIFT) - start, \
	     temp = min_t(unsigned, temp, length), \
	     start += temp, length -= temp)

#define gen6_for_all_pdes(pt, ppgtt, iter)  \
	for (iter = 0;		\
	     pt = ppgtt->pd.page_table[iter], iter < I915_PDES;	\
	     iter++)

static inline uint32_t i915_pte_index(uint64_t address, uint32_t pde_shift)
{
	const uint32_t mask = NUM_PTE(pde_shift) - 1;

	return (address >> PAGE_SHIFT) & mask;
}

/* Helper to counts the number of PTEs within the given length. This count
 * does not cross a page table boundary, so the max value would be
 * GEN6_PTES for GEN6, and GEN8_PTES for GEN8.
*/
static inline uint32_t i915_pte_count(uint64_t addr, size_t length,
				      uint32_t pde_shift)
{
	const uint64_t mask = ~((1 << pde_shift) - 1);
	uint64_t end;

	WARN_ON(length == 0);
	WARN_ON(offset_in_page(addr|length));

	end = addr + length;

	if ((addr & mask) != (end & mask))
		return NUM_PTE(pde_shift) - i915_pte_index(addr, pde_shift);

	return i915_pte_index(end, pde_shift) - i915_pte_index(addr, pde_shift);
}

static inline uint32_t i915_pde_index(uint64_t addr, uint32_t shift)
{
	return (addr >> shift) & I915_PDE_MASK;
}

static inline uint32_t gen6_pte_index(uint32_t addr)
{
	return i915_pte_index(addr, GEN6_PDE_SHIFT);
}

static inline size_t gen6_pte_count(uint32_t addr, uint32_t length)
{
	return i915_pte_count(addr, length, GEN6_PDE_SHIFT);
}

static inline uint32_t gen6_pde_index(uint32_t addr)
{
	return i915_pde_index(addr, GEN6_PDE_SHIFT);
}

/* Equivalent to the gen6 version, For each pde iterates over every pde
 * between from start until start + length. On gen8+ it simply iterates
 * over every page directory entry in a page directory.
 */
#define gen8_for_each_pde(pt, pd, start, length, temp, iter)		\
	for (iter = gen8_pde_index(start); \
	     pt = (pd)->page_table[iter], length > 0 && iter < I915_PDES;	\
	     iter++,				\
	     temp = ALIGN(start+1, 1 << GEN8_PDE_SHIFT) - start,	\
	     temp = min(temp, length),					\
	     start += temp, length -= temp)

#define gen8_for_each_pdpe(pd, pdp, start, length, temp, iter)		\
	for (iter = gen8_pdpe_index(start);	\
	     pd = (pdp)->page_directory[iter], length > 0 && iter < GEN8_LEGACY_PDPES;	\
	     iter++,				\
	     temp = ALIGN(start+1, 1 << GEN8_PDPE_SHIFT) - start,	\
	     temp = min(temp, length),					\
	     start += temp, length -= temp)

/* Clamp length to the next page_directory boundary */
static inline uint64_t gen8_clamp_pd(uint64_t start, uint64_t length)
{
	uint64_t next_pd = ALIGN(start + 1, 1 << GEN8_PDPE_SHIFT);

	if (next_pd > (start + length))
		return length;

	return next_pd - start;
}

static inline uint32_t gen8_pte_index(uint64_t address)
{
	return i915_pte_index(address, GEN8_PDE_SHIFT);
}

static inline uint32_t gen8_pde_index(uint64_t address)
{
	return i915_pde_index(address, GEN8_PDE_SHIFT);
}

static inline uint32_t gen8_pdpe_index(uint64_t address)
{
	return (address >> GEN8_PDPE_SHIFT) & GEN8_PDPE_MASK;
}

static inline uint32_t gen8_pml4e_index(uint64_t address)
{
	WARN_ON(1); /* For 64B */
	return 0;
}

static inline size_t gen8_pte_count(uint64_t address, uint64_t length)
{
	return i915_pte_count(address, length, GEN8_PDE_SHIFT);
}

static inline dma_addr_t
i915_page_dir_dma_addr(const struct i915_hw_ppgtt *ppgtt, const unsigned n)
{
	return test_bit(n, ppgtt->pdp.used_pdpes) ?
		ppgtt->pdp.page_directory[n]->base.daddr :
		ppgtt->scratch_pd->base.daddr;
}

int i915_gem_gtt_init(struct drm_device *dev);
void i915_gem_init_global_gtt(struct drm_device *dev);
void i915_global_gtt_cleanup(struct drm_device *dev);


int i915_ppgtt_init(struct drm_device *dev, struct i915_hw_ppgtt *ppgtt);
int i915_ppgtt_init_hw(struct drm_device *dev);
int i915_ppgtt_init_ring(struct drm_i915_gem_request *req);
void i915_ppgtt_release(struct kref *kref);
struct i915_hw_ppgtt *i915_ppgtt_create(struct drm_device *dev,
					struct drm_i915_file_private *fpriv);
static inline void i915_ppgtt_get(struct i915_hw_ppgtt *ppgtt)
{
	if (ppgtt)
		kref_get(&ppgtt->ref);
}
static inline void i915_ppgtt_put(struct i915_hw_ppgtt *ppgtt)
{
	if (ppgtt)
		kref_put(&ppgtt->ref, i915_ppgtt_release);
}

void i915_check_and_clear_faults(struct drm_device *dev);
void i915_gem_suspend_gtt_mappings(struct drm_device *dev);
void i915_gem_restore_gtt_mappings(struct drm_device *dev);

int __must_check i915_gem_gtt_prepare_object(struct drm_i915_gem_object *obj);
void i915_gem_gtt_finish_object(struct drm_i915_gem_object *obj);

static inline bool
i915_ggtt_view_equal(const struct i915_ggtt_view *a,
                     const struct i915_ggtt_view *b)
{
	if (WARN_ON(!a || !b))
		return false;

	if (a->type != b->type)
		return false;
	if (a->type == I915_GGTT_VIEW_PARTIAL)
		return !memcmp(&a->params, &b->params, sizeof(a->params));
	return true;
}

size_t
i915_ggtt_view_size(struct drm_i915_gem_object *obj,
		    const struct i915_ggtt_view *view);

#endif
Commit	Line	Data
0260c420 BW	1	/*
	2	* Copyright © 2014 Intel Corporation
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice (including the next
	12	* paragraph) shall be included in all copies or substantial portions of the
	13	* Software.
	14	*
	15	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	16	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	17	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	18	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	19	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
	20	* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
	21	* IN THE SOFTWARE.
	22	*
	23	* Please try to maintain the following order within this file unless it makes
	24	* sense to do otherwise. From top to bottom:
	25	* 1. typedefs
	26	* 2. #defines, and macros
	27	* 3. structure definitions
	28	* 4. function prototypes
	29	*
	30	* Within each section, please try to order by generation in ascending order,
	31	* from top to bottom (ie. gen6 on the top, gen8 on the bottom).
	32	*/
	33
	34	#ifndef __I915_GEM_GTT_H__
	35	#define __I915_GEM_GTT_H__
	36
4d884705 DV	37	struct drm_i915_file_private;
4d884705 DV	38
07749ef3 MT	39	typedef uint32_t gen6_pte_t;
	40	typedef uint64_t gen8_pte_t;
	41	typedef uint64_t gen8_pde_t;
0260c420 BW	42
	43	#define gtt_total_entries(gtt) ((gtt).base.total >> PAGE_SHIFT)
	44
07749ef3	45
0260c420 BW	46	/* gen6-hsw has bit 11-4 for physical addr bit 39-32 */
	47	#define GEN6_GTT_ADDR_ENCODE(addr) ((addr) \| (((addr) >> 28) & 0xff0))
	48	#define GEN6_PTE_ADDR_ENCODE(addr) GEN6_GTT_ADDR_ENCODE(addr)
	49	#define GEN6_PDE_ADDR_ENCODE(addr) GEN6_GTT_ADDR_ENCODE(addr)
	50	#define GEN6_PTE_CACHE_LLC (2 << 1)
	51	#define GEN6_PTE_UNCACHED (1 << 1)
	52	#define GEN6_PTE_VALID (1 << 0)
	53
07749ef3 MT	54	#define I915_PTES(pte_len) (PAGE_SIZE / (pte_len))
	55	#define I915_PTE_MASK(pte_len) (I915_PTES(pte_len) - 1)
	56	#define I915_PDES 512
	57	#define I915_PDE_MASK (I915_PDES - 1)
678d96fb	58	#define NUM_PTE(pde_shift) (1 << (pde_shift - PAGE_SHIFT))
07749ef3 MT	59
	60	#define GEN6_PTES I915_PTES(sizeof(gen6_pte_t))
	61	#define GEN6_PD_SIZE (I915_PDES * PAGE_SIZE)
0260c420	62	#define GEN6_PD_ALIGN (PAGE_SIZE * 16)
678d96fb	63	#define GEN6_PDE_SHIFT 22
0260c420 BW	64	#define GEN6_PDE_VALID (1 << 0)
	65
	66	#define GEN7_PTE_CACHE_L3_LLC (3 << 1)
	67
	68	#define BYT_PTE_SNOOPED_BY_CPU_CACHES (1 << 2)
	69	#define BYT_PTE_WRITEABLE (1 << 1)
	70
	71	/* Cacheability Control is a 4-bit value. The low three bits are stored in bits
	72	* 3:1 of the PTE, while the fourth bit is stored in bit 11 of the PTE.
	73	*/
	74	#define HSW_CACHEABILITY_CONTROL(bits) ((((bits) & 0x7) << 1) \| \
	75	(((bits) & 0x8) << (11 - 3)))
	76	#define HSW_WB_LLC_AGE3 HSW_CACHEABILITY_CONTROL(0x2)
	77	#define HSW_WB_LLC_AGE0 HSW_CACHEABILITY_CONTROL(0x3)
	78	#define HSW_WB_ELLC_LLC_AGE3 HSW_CACHEABILITY_CONTROL(0x8)
	79	#define HSW_WB_ELLC_LLC_AGE0 HSW_CACHEABILITY_CONTROL(0xb)
	80	#define HSW_WT_ELLC_LLC_AGE3 HSW_CACHEABILITY_CONTROL(0x7)
	81	#define HSW_WT_ELLC_LLC_AGE0 HSW_CACHEABILITY_CONTROL(0x6)
	82	#define HSW_PTE_UNCACHED (0)
	83	#define HSW_GTT_ADDR_ENCODE(addr) ((addr) \| (((addr) >> 28) & 0x7f0))
	84	#define HSW_PTE_ADDR_ENCODE(addr) HSW_GTT_ADDR_ENCODE(addr)
	85
	86	/* GEN8 legacy style address is defined as a 3 level page table:
	87	* 31:30 \| 29:21 \| 20:12 \| 11:0
	88	* PDPE \| PDE \| PTE \| offset
	89	* The difference as compared to normal x86 3 level page table is the PDPEs are
	90	* programmed via register.
	91	*/
	92	#define GEN8_PDPE_SHIFT 30
	93	#define GEN8_PDPE_MASK 0x3
	94	#define GEN8_PDE_SHIFT 21
	95	#define GEN8_PDE_MASK 0x1ff
	96	#define GEN8_PTE_SHIFT 12
	97	#define GEN8_PTE_MASK 0x1ff
76643600	98	#define GEN8_LEGACY_PDPES 4
07749ef3	99	#define GEN8_PTES I915_PTES(sizeof(gen8_pte_t))
0260c420 BW	100
	101	#define PPAT_UNCACHED_INDEX (_PAGE_PWT \| _PAGE_PCD)
	102	#define PPAT_CACHED_PDE_INDEX 0 /* WB LLC */
	103	#define PPAT_CACHED_INDEX _PAGE_PAT /* WB LLCeLLC */
	104	#define PPAT_DISPLAY_ELLC_INDEX _PAGE_PCD /* WT eLLC */
	105
ee0ce478	106	#define CHV_PPAT_SNOOP (1<<6)
0260c420 BW	107	#define GEN8_PPAT_AGE(x) (x<<4)
	108	#define GEN8_PPAT_LLCeLLC (3<<2)
	109	#define GEN8_PPAT_LLCELLC (2<<2)
	110	#define GEN8_PPAT_LLC (1<<2)
	111	#define GEN8_PPAT_WB (3<<0)
	112	#define GEN8_PPAT_WT (2<<0)
	113	#define GEN8_PPAT_WC (1<<0)
	114	#define GEN8_PPAT_UC (0<<0)
	115	#define GEN8_PPAT_ELLC_OVERRIDE (0<<2)
	116	#define GEN8_PPAT(i, x) ((uint64_t) (x) << ((i) * 8))
	117
fe14d5f4 TU	118	enum i915_ggtt_view_type {
fe14d5f4 TU	119	I915_GGTT_VIEW_NORMAL = 0,
8bd7ef16 JL	120	I915_GGTT_VIEW_ROTATED,
8bd7ef16 JL	121	I915_GGTT_VIEW_PARTIAL,
50470bb0 TU	122	};
	123
	124	struct intel_rotation_info {
	125	unsigned int height;
	126	unsigned int pitch;
	127	uint32_t pixel_format;
	128	uint64_t fb_modifier;
84fe03f7 TU	129	unsigned int width_pages, height_pages;
84fe03f7 TU	130	uint64_t size;
fe14d5f4 TU	131	};
	132
	133	struct i915_ggtt_view {
	134	enum i915_ggtt_view_type type;
	135
8bd7ef16 JL	136	union {
	137	struct {
	138	unsigned long offset;
	139	unsigned int size;
	140	} partial;
	141	} params;
	142
fe14d5f4	143	struct sg_table *pages;
50470bb0 TU	144
	145	union {
	146	struct intel_rotation_info rotation_info;
	147	};
fe14d5f4 TU	148	};
	149
	150	extern const struct i915_ggtt_view i915_ggtt_view_normal;
9abc4648	151	extern const struct i915_ggtt_view i915_ggtt_view_rotated;
fe14d5f4	152
0260c420	153	enum i915_cache_level;
fe14d5f4	154
0260c420 BW	155	/**
	156	* A VMA represents a GEM BO that is bound into an address space. Therefore, a
	157	* VMA's presence cannot be guaranteed before binding, or after unbinding the
	158	* object into/from the address space.
	159	*
	160	* To make things as simple as possible (ie. no refcounting), a VMA's lifetime
	161	* will always be <= an objects lifetime. So object refcounting should cover us.
	162	*/
	163	struct i915_vma {
	164	struct drm_mm_node node;
	165	struct drm_i915_gem_object *obj;
	166	struct i915_address_space *vm;
	167
aff43766 TU	168	/** Flags and address space this VMA is bound to */
	169	#define GLOBAL_BIND (1<<0)
	170	#define LOCAL_BIND (1<<1)
aff43766 TU	171	unsigned int bound : 4;
aff43766 TU	172
fe14d5f4 TU	173	/**
	174	* Support different GGTT views into the same object.
	175	* This means there can be multiple VMA mappings per object and per VM.
	176	* i915_ggtt_view_type is used to distinguish between those entries.
	177	* The default one of zero (I915_GGTT_VIEW_NORMAL) is default and also
	178	* assumed in GEM functions which take no ggtt view parameter.
	179	*/
	180	struct i915_ggtt_view ggtt_view;
	181
0260c420 BW	182	/** This object's place on the active/inactive lists */
	183	struct list_head mm_list;
	184
	185	struct list_head vma_link; /* Link in the object's VMA list */
	186
	187	/** This vma's place in the batchbuffer or on the eviction list */
	188	struct list_head exec_list;
	189
	190	/**
	191	* Used for performing relocations during execbuffer insertion.
	192	*/
	193	struct hlist_node exec_node;
	194	unsigned long exec_handle;
	195	struct drm_i915_gem_exec_object2 *exec_entry;
	196
	197	/**
	198	* How many users have pinned this object in GTT space. The following
4feb7659 DV	199	* users can each hold at most one reference: pwrite/pread, execbuffer
	200	* (objects are not allowed multiple times for the same batchbuffer),
	201	* and the framebuffer code. When switching/pageflipping, the
	202	* framebuffer code has at most two buffers pinned per crtc.
0260c420 BW	203	*
	204	* In the worst case this is 1 + 1 + 1 + 2*2 = 7. That would fit into 3
	205	* bits with absolutely no headroom. So use 4 bits. */
	206	unsigned int pin_count:4;
	207	#define DRM_I915_GEM_OBJECT_MAX_PIN_COUNT 0xf
0260c420 BW	208	};
0260c420 BW	209
44159ddb	210	struct i915_page_dma {
d7b3de91	211	struct page *page;
44159ddb MK	212	union {
	213	dma_addr_t daddr;
	214
	215	/* For gen6/gen7 only. This is the offset in the GGTT
	216	* where the page directory entries for PPGTT begin
	217	*/
	218	uint32_t ggtt_offset;
	219	};
	220	};
	221
	222	struct i915_page_table {
	223	struct i915_page_dma base;
678d96fb BW	224
678d96fb BW	225	unsigned long *used_ptes;
d7b3de91 BW	226	};
d7b3de91 BW	227
ec565b3c	228	struct i915_page_directory {
44159ddb	229	struct i915_page_dma base;
7324cc04	230
33c8819f	231	unsigned long *used_pdes;
ec565b3c	232	struct i915_page_table page_table[I915_PDES]; / PDEs */
d7b3de91 BW	233	};
d7b3de91 BW	234
ec565b3c	235	struct i915_page_directory_pointer {
d7b3de91	236	/* struct page page; /
33c8819f	237	DECLARE_BITMAP(used_pdpes, GEN8_LEGACY_PDPES);
ec565b3c	238	struct i915_page_directory *page_directory[GEN8_LEGACY_PDPES];
d7b3de91 BW	239	};
d7b3de91 BW	240
0260c420 BW	241	struct i915_address_space {
	242	struct drm_mm mm;
	243	struct drm_device *dev;
	244	struct list_head global_link;
c44ef60e MK	245	u64 start; /* Start offset always 0 for dri2 */
c44ef60e MK	246	u64 total; /* size addr space maps (ex. 2GB for ggtt) */
0260c420 BW	247
	248	struct {
	249	dma_addr_t addr;
	250	struct page *page;
	251	} scratch;
	252
	253	/**
	254	* List of objects currently involved in rendering.
	255	*
	256	* Includes buffers having the contents of their GPU caches
97b2a6a1	257	* flushed, not necessarily primitives. last_read_req
0260c420 BW	258	* represents when the rendering involved will be completed.
	259	*
	260	* A reference is held on the buffer while on this list.
	261	*/
	262	struct list_head active_list;
	263
	264	/**
	265	* LRU list of objects which are not in the ringbuffer and
	266	* are ready to unbind, but are still in the GTT.
	267	*
97b2a6a1	268	* last_read_req is NULL while an object is in this list.
0260c420 BW	269	*
	270	* A reference is not held on the buffer while on this list,
	271	* as merely being GTT-bound shouldn't prevent its being
	272	* freed, and we'll pull it off the list in the free path.
	273	*/
	274	struct list_head inactive_list;
	275
	276	/* FIXME: Need a more generic return type */
07749ef3 MT	277	gen6_pte_t (*pte_encode)(dma_addr_t addr,
	278	enum i915_cache_level level,
	279	bool valid, u32 flags); /* Create a valid PTE */
f329f5f6 DV	280	/* flags for pte_encode */
f329f5f6 DV	281	#define PTE_READ_ONLY (1<<0)
678d96fb BW	282	int (allocate_va_range)(struct i915_address_space vm,
	283	uint64_t start,
	284	uint64_t length);
0260c420 BW	285	void (clear_range)(struct i915_address_space vm,
	286	uint64_t start,
	287	uint64_t length,
	288	bool use_scratch);
	289	void (insert_entries)(struct i915_address_space vm,
	290	struct sg_table *st,
	291	uint64_t start,
24f3a8cf	292	enum i915_cache_level cache_level, u32 flags);
0260c420	293	void (cleanup)(struct i915_address_space vm);
777dc5bb DV	294	/** Unmap an object from an address space. This usually consists of
	295	* setting the valid PTE entries to a reserved scratch page. */
	296	void (unbind_vma)(struct i915_vma vma);
	297	/* Map an object into an address space with the given cache flags. */
70b9f6f8 DV	298	int (bind_vma)(struct i915_vma vma,
	299	enum i915_cache_level cache_level,
	300	u32 flags);
0260c420 BW	301	};
	302
	303	/* The Graphics Translation Table is the way in which GEN hardware translates a
	304	* Graphics Virtual Address into a Physical Address. In addition to the normal
	305	* collateral associated with any va->pa translations GEN hardware also has a
	306	* portion of the GTT which can be mapped by the CPU and remain both coherent
	307	* and correct (in cases like swizzling). That region is referred to as GMADR in
	308	* the spec.
	309	*/
	310	struct i915_gtt {
	311	struct i915_address_space base;
0260c420	312
c44ef60e MK	313	size_t stolen_size; /* Total size of stolen memory */
c44ef60e MK	314	u64 mappable_end; /* End offset that we can CPU map */
0260c420 BW	315	struct io_mapping mappable; / Mapping to our CPU mappable region */
	316	phys_addr_t mappable_base; /* PA of our GMADR */
	317
	318	/** "Graphics Stolen Memory" holds the global PTEs */
	319	void __iomem *gsm;
	320
	321	bool do_idle_maps;
	322
	323	int mtrr;
	324
	325	/* global gtt ops */
c44ef60e	326	int (gtt_probe)(struct drm_device dev, u64 *gtt_total,
0260c420	327	size_t stolen, phys_addr_t mappable_base,
c44ef60e	328	u64 *mappable_end);
0260c420 BW	329	};
	330
	331	struct i915_hw_ppgtt {
	332	struct i915_address_space base;
	333	struct kref ref;
	334	struct drm_mm_node node;
563222a7	335	unsigned long pd_dirty_rings;
d7b3de91	336	union {
ec565b3c MT	337	struct i915_page_directory_pointer pdp;
ec565b3c MT	338	struct i915_page_directory pd;
d7b3de91	339	};
0260c420	340
ec565b3c	341	struct i915_page_table *scratch_pt;
7cb6d7ac	342	struct i915_page_directory *scratch_pd;
4933d519	343
4d884705	344	struct drm_i915_file_private *file_priv;
0260c420	345
678d96fb BW	346	gen6_pte_t __iomem *pd_addr;
678d96fb BW	347
0260c420 BW	348	int (enable)(struct i915_hw_ppgtt ppgtt);
0260c420 BW	349	int (switch_mm)(struct i915_hw_ppgtt ppgtt,
e85b26dc	350	struct drm_i915_gem_request *req);
0260c420 BW	351	void (debug_dump)(struct i915_hw_ppgtt ppgtt, struct seq_file *m);
	352	};
	353
678d96fb BW	354	/* For each pde iterates over every pde between from start until start + length.
	355	* If start, and start+length are not perfectly divisible, the macro will round
	356	* down, and up as needed. The macro modifies pde, start, and length. Dev is
	357	* only used to differentiate shift values. Temp is temp. On gen6/7, start = 0,
	358	* and length = 2G effectively iterates over every PDE in the system.
	359	*
	360	* XXX: temp is not actually needed, but it saves doing the ALIGN operation.
	361	*/
	362	#define gen6_for_each_pde(pt, pd, start, length, temp, iter) \
fdc454c1 MT	363	for (iter = gen6_pde_index(start); \
	364	pt = (pd)->page_table[iter], length > 0 && iter < I915_PDES; \
	365	iter++, \
678d96fb BW	366	temp = ALIGN(start+1, 1 << GEN6_PDE_SHIFT) - start, \
	367	temp = min_t(unsigned, temp, length), \
	368	start += temp, length -= temp)
	369
09942c65 MT	370	#define gen6_for_all_pdes(pt, ppgtt, iter) \
	371	for (iter = 0; \
	372	pt = ppgtt->pd.page_table[iter], iter < I915_PDES; \
	373	iter++)
	374
678d96fb BW	375	static inline uint32_t i915_pte_index(uint64_t address, uint32_t pde_shift)
	376	{
	377	const uint32_t mask = NUM_PTE(pde_shift) - 1;
	378
	379	return (address >> PAGE_SHIFT) & mask;
	380	}
	381
	382	/* Helper to counts the number of PTEs within the given length. This count
	383	* does not cross a page table boundary, so the max value would be
	384	* GEN6_PTES for GEN6, and GEN8_PTES for GEN8.
	385	*/
	386	static inline uint32_t i915_pte_count(uint64_t addr, size_t length,
	387	uint32_t pde_shift)
	388	{
	389	const uint64_t mask = ~((1 << pde_shift) - 1);
	390	uint64_t end;
	391
	392	WARN_ON(length == 0);
	393	WARN_ON(offset_in_page(addr\|length));
	394
	395	end = addr + length;
	396
	397	if ((addr & mask) != (end & mask))
	398	return NUM_PTE(pde_shift) - i915_pte_index(addr, pde_shift);
	399
	400	return i915_pte_index(end, pde_shift) - i915_pte_index(addr, pde_shift);
	401	}
	402
	403	static inline uint32_t i915_pde_index(uint64_t addr, uint32_t shift)
	404	{
	405	return (addr >> shift) & I915_PDE_MASK;
	406	}
	407
	408	static inline uint32_t gen6_pte_index(uint32_t addr)
	409	{
	410	return i915_pte_index(addr, GEN6_PDE_SHIFT);
	411	}
	412
	413	static inline size_t gen6_pte_count(uint32_t addr, uint32_t length)
	414	{
	415	return i915_pte_count(addr, length, GEN6_PDE_SHIFT);
	416	}
	417
	418	static inline uint32_t gen6_pde_index(uint32_t addr)
	419	{
	420	return i915_pde_index(addr, GEN6_PDE_SHIFT);
	421	}
	422
9271d959 MT	423	/* Equivalent to the gen6 version, For each pde iterates over every pde
	424	* between from start until start + length. On gen8+ it simply iterates
	425	* over every page directory entry in a page directory.
	426	*/
	427	#define gen8_for_each_pde(pt, pd, start, length, temp, iter) \
	428	for (iter = gen8_pde_index(start); \
	429	pt = (pd)->page_table[iter], length > 0 && iter < I915_PDES; \
	430	iter++, \
	431	temp = ALIGN(start+1, 1 << GEN8_PDE_SHIFT) - start, \
	432	temp = min(temp, length), \
	433	start += temp, length -= temp)
	434
	435	#define gen8_for_each_pdpe(pd, pdp, start, length, temp, iter) \
	436	for (iter = gen8_pdpe_index(start); \
	437	pd = (pdp)->page_directory[iter], length > 0 && iter < GEN8_LEGACY_PDPES; \
	438	iter++, \
	439	temp = ALIGN(start+1, 1 << GEN8_PDPE_SHIFT) - start, \
	440	temp = min(temp, length), \
	441	start += temp, length -= temp)
	442
	443	/* Clamp length to the next page_directory boundary */
	444	static inline uint64_t gen8_clamp_pd(uint64_t start, uint64_t length)
	445	{
	446	uint64_t next_pd = ALIGN(start + 1, 1 << GEN8_PDPE_SHIFT);
	447
	448	if (next_pd > (start + length))
	449	return length;
	450
	451	return next_pd - start;
	452	}
	453
	454	static inline uint32_t gen8_pte_index(uint64_t address)
	455	{
	456	return i915_pte_index(address, GEN8_PDE_SHIFT);
	457	}
	458
	459	static inline uint32_t gen8_pde_index(uint64_t address)
	460	{
	461	return i915_pde_index(address, GEN8_PDE_SHIFT);
	462	}
	463
	464	static inline uint32_t gen8_pdpe_index(uint64_t address)
	465	{
	466	return (address >> GEN8_PDPE_SHIFT) & GEN8_PDPE_MASK;
	467	}
	468
	469	static inline uint32_t gen8_pml4e_index(uint64_t address)
	470	{
	471	WARN_ON(1); /* For 64B */
	472	return 0;
	473	}
	474
33c8819f MT	475	static inline size_t gen8_pte_count(uint64_t address, uint64_t length)
	476	{
	477	return i915_pte_count(address, length, GEN8_PDE_SHIFT);
	478	}
	479
d852c7bf MK	480	static inline dma_addr_t
	481	i915_page_dir_dma_addr(const struct i915_hw_ppgtt *ppgtt, const unsigned n)
	482	{
	483	return test_bit(n, ppgtt->pdp.used_pdpes) ?
44159ddb MK	484	ppgtt->pdp.page_directory[n]->base.daddr :
44159ddb MK	485	ppgtt->scratch_pd->base.daddr;
d852c7bf MK	486	}
d852c7bf MK	487
0260c420 BW	488	int i915_gem_gtt_init(struct drm_device *dev);
0260c420 BW	489	void i915_gem_init_global_gtt(struct drm_device *dev);
90d0a0e8	490	void i915_global_gtt_cleanup(struct drm_device *dev);
0260c420	491
ee960be7 DV	492
ee960be7 DV	493	int i915_ppgtt_init(struct drm_device dev, struct i915_hw_ppgtt ppgtt);
82460d97	494	int i915_ppgtt_init_hw(struct drm_device *dev);
b3dd6b96	495	int i915_ppgtt_init_ring(struct drm_i915_gem_request *req);
ee960be7	496	void i915_ppgtt_release(struct kref *kref);
4d884705 DV	497	struct i915_hw_ppgtt i915_ppgtt_create(struct drm_device dev,
4d884705 DV	498	struct drm_i915_file_private *fpriv);
ee960be7 DV	499	static inline void i915_ppgtt_get(struct i915_hw_ppgtt *ppgtt)
	500	{
	501	if (ppgtt)
	502	kref_get(&ppgtt->ref);
	503	}
	504	static inline void i915_ppgtt_put(struct i915_hw_ppgtt *ppgtt)
	505	{
	506	if (ppgtt)
	507	kref_put(&ppgtt->ref, i915_ppgtt_release);
	508	}
0260c420 BW	509
	510	void i915_check_and_clear_faults(struct drm_device *dev);
	511	void i915_gem_suspend_gtt_mappings(struct drm_device *dev);
	512	void i915_gem_restore_gtt_mappings(struct drm_device *dev);
	513
	514	int __must_check i915_gem_gtt_prepare_object(struct drm_i915_gem_object *obj);
	515	void i915_gem_gtt_finish_object(struct drm_i915_gem_object *obj);
	516
9abc4648 JL	517	static inline bool
	518	i915_ggtt_view_equal(const struct i915_ggtt_view *a,
	519	const struct i915_ggtt_view *b)
	520	{
	521	if (WARN_ON(!a \|\| !b))
	522	return false;
	523
8bd7ef16 JL	524	if (a->type != b->type)
	525	return false;
	526	if (a->type == I915_GGTT_VIEW_PARTIAL)
	527	return !memcmp(&a->params, &b->params, sizeof(a->params));
	528	return true;
9abc4648 JL	529	}
9abc4648 JL	530
91e6711e JL	531	size_t
	532	i915_ggtt_view_size(struct drm_i915_gem_object *obj,
	533	const struct i915_ggtt_view *view);
	534
0260c420	535	#endif