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0260c420 BW |
1 | /* |
2 | * Copyright © 2014 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Please try to maintain the following order within this file unless it makes | |
24 | * sense to do otherwise. From top to bottom: | |
25 | * 1. typedefs | |
26 | * 2. #defines, and macros | |
27 | * 3. structure definitions | |
28 | * 4. function prototypes | |
29 | * | |
30 | * Within each section, please try to order by generation in ascending order, | |
31 | * from top to bottom (ie. gen6 on the top, gen8 on the bottom). | |
32 | */ | |
33 | ||
34 | #ifndef __I915_GEM_GTT_H__ | |
35 | #define __I915_GEM_GTT_H__ | |
36 | ||
4d884705 DV |
37 | struct drm_i915_file_private; |
38 | ||
07749ef3 MT |
39 | typedef uint32_t gen6_pte_t; |
40 | typedef uint64_t gen8_pte_t; | |
41 | typedef uint64_t gen8_pde_t; | |
762d9936 MT |
42 | typedef uint64_t gen8_ppgtt_pdpe_t; |
43 | typedef uint64_t gen8_ppgtt_pml4e_t; | |
0260c420 BW |
44 | |
45 | #define gtt_total_entries(gtt) ((gtt).base.total >> PAGE_SHIFT) | |
46 | ||
07749ef3 | 47 | |
0260c420 BW |
48 | /* gen6-hsw has bit 11-4 for physical addr bit 39-32 */ |
49 | #define GEN6_GTT_ADDR_ENCODE(addr) ((addr) | (((addr) >> 28) & 0xff0)) | |
50 | #define GEN6_PTE_ADDR_ENCODE(addr) GEN6_GTT_ADDR_ENCODE(addr) | |
51 | #define GEN6_PDE_ADDR_ENCODE(addr) GEN6_GTT_ADDR_ENCODE(addr) | |
52 | #define GEN6_PTE_CACHE_LLC (2 << 1) | |
53 | #define GEN6_PTE_UNCACHED (1 << 1) | |
54 | #define GEN6_PTE_VALID (1 << 0) | |
55 | ||
07749ef3 MT |
56 | #define I915_PTES(pte_len) (PAGE_SIZE / (pte_len)) |
57 | #define I915_PTE_MASK(pte_len) (I915_PTES(pte_len) - 1) | |
58 | #define I915_PDES 512 | |
59 | #define I915_PDE_MASK (I915_PDES - 1) | |
678d96fb | 60 | #define NUM_PTE(pde_shift) (1 << (pde_shift - PAGE_SHIFT)) |
07749ef3 MT |
61 | |
62 | #define GEN6_PTES I915_PTES(sizeof(gen6_pte_t)) | |
63 | #define GEN6_PD_SIZE (I915_PDES * PAGE_SIZE) | |
0260c420 | 64 | #define GEN6_PD_ALIGN (PAGE_SIZE * 16) |
678d96fb | 65 | #define GEN6_PDE_SHIFT 22 |
0260c420 BW |
66 | #define GEN6_PDE_VALID (1 << 0) |
67 | ||
68 | #define GEN7_PTE_CACHE_L3_LLC (3 << 1) | |
69 | ||
70 | #define BYT_PTE_SNOOPED_BY_CPU_CACHES (1 << 2) | |
71 | #define BYT_PTE_WRITEABLE (1 << 1) | |
72 | ||
73 | /* Cacheability Control is a 4-bit value. The low three bits are stored in bits | |
74 | * 3:1 of the PTE, while the fourth bit is stored in bit 11 of the PTE. | |
75 | */ | |
76 | #define HSW_CACHEABILITY_CONTROL(bits) ((((bits) & 0x7) << 1) | \ | |
77 | (((bits) & 0x8) << (11 - 3))) | |
78 | #define HSW_WB_LLC_AGE3 HSW_CACHEABILITY_CONTROL(0x2) | |
79 | #define HSW_WB_LLC_AGE0 HSW_CACHEABILITY_CONTROL(0x3) | |
80 | #define HSW_WB_ELLC_LLC_AGE3 HSW_CACHEABILITY_CONTROL(0x8) | |
81 | #define HSW_WB_ELLC_LLC_AGE0 HSW_CACHEABILITY_CONTROL(0xb) | |
82 | #define HSW_WT_ELLC_LLC_AGE3 HSW_CACHEABILITY_CONTROL(0x7) | |
83 | #define HSW_WT_ELLC_LLC_AGE0 HSW_CACHEABILITY_CONTROL(0x6) | |
84 | #define HSW_PTE_UNCACHED (0) | |
85 | #define HSW_GTT_ADDR_ENCODE(addr) ((addr) | (((addr) >> 28) & 0x7f0)) | |
86 | #define HSW_PTE_ADDR_ENCODE(addr) HSW_GTT_ADDR_ENCODE(addr) | |
87 | ||
88 | /* GEN8 legacy style address is defined as a 3 level page table: | |
89 | * 31:30 | 29:21 | 20:12 | 11:0 | |
90 | * PDPE | PDE | PTE | offset | |
91 | * The difference as compared to normal x86 3 level page table is the PDPEs are | |
92 | * programmed via register. | |
81ba8aef MT |
93 | * |
94 | * GEN8 48b legacy style address is defined as a 4 level page table: | |
95 | * 47:39 | 38:30 | 29:21 | 20:12 | 11:0 | |
96 | * PML4E | PDPE | PDE | PTE | offset | |
0260c420 | 97 | */ |
81ba8aef MT |
98 | #define GEN8_PML4ES_PER_PML4 512 |
99 | #define GEN8_PML4E_SHIFT 39 | |
762d9936 | 100 | #define GEN8_PML4E_MASK (GEN8_PML4ES_PER_PML4 - 1) |
0260c420 | 101 | #define GEN8_PDPE_SHIFT 30 |
81ba8aef MT |
102 | /* NB: GEN8_PDPE_MASK is untrue for 32b platforms, but it has no impact on 32b page |
103 | * tables */ | |
104 | #define GEN8_PDPE_MASK 0x1ff | |
0260c420 BW |
105 | #define GEN8_PDE_SHIFT 21 |
106 | #define GEN8_PDE_MASK 0x1ff | |
107 | #define GEN8_PTE_SHIFT 12 | |
108 | #define GEN8_PTE_MASK 0x1ff | |
76643600 | 109 | #define GEN8_LEGACY_PDPES 4 |
07749ef3 | 110 | #define GEN8_PTES I915_PTES(sizeof(gen8_pte_t)) |
0260c420 | 111 | |
81ba8aef MT |
112 | #define I915_PDPES_PER_PDP(dev) (USES_FULL_48BIT_PPGTT(dev) ?\ |
113 | GEN8_PML4ES_PER_PML4 : GEN8_LEGACY_PDPES) | |
6ac18502 | 114 | |
0260c420 BW |
115 | #define PPAT_UNCACHED_INDEX (_PAGE_PWT | _PAGE_PCD) |
116 | #define PPAT_CACHED_PDE_INDEX 0 /* WB LLC */ | |
117 | #define PPAT_CACHED_INDEX _PAGE_PAT /* WB LLCeLLC */ | |
118 | #define PPAT_DISPLAY_ELLC_INDEX _PAGE_PCD /* WT eLLC */ | |
119 | ||
ee0ce478 | 120 | #define CHV_PPAT_SNOOP (1<<6) |
0260c420 BW |
121 | #define GEN8_PPAT_AGE(x) (x<<4) |
122 | #define GEN8_PPAT_LLCeLLC (3<<2) | |
123 | #define GEN8_PPAT_LLCELLC (2<<2) | |
124 | #define GEN8_PPAT_LLC (1<<2) | |
125 | #define GEN8_PPAT_WB (3<<0) | |
126 | #define GEN8_PPAT_WT (2<<0) | |
127 | #define GEN8_PPAT_WC (1<<0) | |
128 | #define GEN8_PPAT_UC (0<<0) | |
129 | #define GEN8_PPAT_ELLC_OVERRIDE (0<<2) | |
130 | #define GEN8_PPAT(i, x) ((uint64_t) (x) << ((i) * 8)) | |
131 | ||
fe14d5f4 TU |
132 | enum i915_ggtt_view_type { |
133 | I915_GGTT_VIEW_NORMAL = 0, | |
8bd7ef16 JL |
134 | I915_GGTT_VIEW_ROTATED, |
135 | I915_GGTT_VIEW_PARTIAL, | |
50470bb0 TU |
136 | }; |
137 | ||
138 | struct intel_rotation_info { | |
139 | unsigned int height; | |
140 | unsigned int pitch; | |
141 | uint32_t pixel_format; | |
142 | uint64_t fb_modifier; | |
84fe03f7 TU |
143 | unsigned int width_pages, height_pages; |
144 | uint64_t size; | |
fe14d5f4 TU |
145 | }; |
146 | ||
147 | struct i915_ggtt_view { | |
148 | enum i915_ggtt_view_type type; | |
149 | ||
8bd7ef16 JL |
150 | union { |
151 | struct { | |
152 | unsigned long offset; | |
153 | unsigned int size; | |
154 | } partial; | |
155 | } params; | |
156 | ||
fe14d5f4 | 157 | struct sg_table *pages; |
50470bb0 TU |
158 | |
159 | union { | |
160 | struct intel_rotation_info rotation_info; | |
161 | }; | |
fe14d5f4 TU |
162 | }; |
163 | ||
164 | extern const struct i915_ggtt_view i915_ggtt_view_normal; | |
9abc4648 | 165 | extern const struct i915_ggtt_view i915_ggtt_view_rotated; |
fe14d5f4 | 166 | |
0260c420 | 167 | enum i915_cache_level; |
fe14d5f4 | 168 | |
0260c420 BW |
169 | /** |
170 | * A VMA represents a GEM BO that is bound into an address space. Therefore, a | |
171 | * VMA's presence cannot be guaranteed before binding, or after unbinding the | |
172 | * object into/from the address space. | |
173 | * | |
174 | * To make things as simple as possible (ie. no refcounting), a VMA's lifetime | |
175 | * will always be <= an objects lifetime. So object refcounting should cover us. | |
176 | */ | |
177 | struct i915_vma { | |
178 | struct drm_mm_node node; | |
179 | struct drm_i915_gem_object *obj; | |
180 | struct i915_address_space *vm; | |
181 | ||
aff43766 TU |
182 | /** Flags and address space this VMA is bound to */ |
183 | #define GLOBAL_BIND (1<<0) | |
184 | #define LOCAL_BIND (1<<1) | |
aff43766 TU |
185 | unsigned int bound : 4; |
186 | ||
fe14d5f4 TU |
187 | /** |
188 | * Support different GGTT views into the same object. | |
189 | * This means there can be multiple VMA mappings per object and per VM. | |
190 | * i915_ggtt_view_type is used to distinguish between those entries. | |
191 | * The default one of zero (I915_GGTT_VIEW_NORMAL) is default and also | |
192 | * assumed in GEM functions which take no ggtt view parameter. | |
193 | */ | |
194 | struct i915_ggtt_view ggtt_view; | |
195 | ||
0260c420 BW |
196 | /** This object's place on the active/inactive lists */ |
197 | struct list_head mm_list; | |
198 | ||
199 | struct list_head vma_link; /* Link in the object's VMA list */ | |
200 | ||
201 | /** This vma's place in the batchbuffer or on the eviction list */ | |
202 | struct list_head exec_list; | |
203 | ||
204 | /** | |
205 | * Used for performing relocations during execbuffer insertion. | |
206 | */ | |
207 | struct hlist_node exec_node; | |
208 | unsigned long exec_handle; | |
209 | struct drm_i915_gem_exec_object2 *exec_entry; | |
210 | ||
211 | /** | |
212 | * How many users have pinned this object in GTT space. The following | |
4feb7659 DV |
213 | * users can each hold at most one reference: pwrite/pread, execbuffer |
214 | * (objects are not allowed multiple times for the same batchbuffer), | |
215 | * and the framebuffer code. When switching/pageflipping, the | |
216 | * framebuffer code has at most two buffers pinned per crtc. | |
0260c420 BW |
217 | * |
218 | * In the worst case this is 1 + 1 + 1 + 2*2 = 7. That would fit into 3 | |
219 | * bits with absolutely no headroom. So use 4 bits. */ | |
220 | unsigned int pin_count:4; | |
221 | #define DRM_I915_GEM_OBJECT_MAX_PIN_COUNT 0xf | |
0260c420 BW |
222 | }; |
223 | ||
44159ddb | 224 | struct i915_page_dma { |
d7b3de91 | 225 | struct page *page; |
44159ddb MK |
226 | union { |
227 | dma_addr_t daddr; | |
228 | ||
229 | /* For gen6/gen7 only. This is the offset in the GGTT | |
230 | * where the page directory entries for PPGTT begin | |
231 | */ | |
232 | uint32_t ggtt_offset; | |
233 | }; | |
234 | }; | |
235 | ||
567047be MK |
236 | #define px_base(px) (&(px)->base) |
237 | #define px_page(px) (px_base(px)->page) | |
238 | #define px_dma(px) (px_base(px)->daddr) | |
239 | ||
c114f76a MK |
240 | struct i915_page_scratch { |
241 | struct i915_page_dma base; | |
242 | }; | |
243 | ||
44159ddb MK |
244 | struct i915_page_table { |
245 | struct i915_page_dma base; | |
678d96fb BW |
246 | |
247 | unsigned long *used_ptes; | |
d7b3de91 BW |
248 | }; |
249 | ||
ec565b3c | 250 | struct i915_page_directory { |
44159ddb | 251 | struct i915_page_dma base; |
7324cc04 | 252 | |
33c8819f | 253 | unsigned long *used_pdes; |
ec565b3c | 254 | struct i915_page_table *page_table[I915_PDES]; /* PDEs */ |
d7b3de91 BW |
255 | }; |
256 | ||
ec565b3c | 257 | struct i915_page_directory_pointer { |
6ac18502 MT |
258 | struct i915_page_dma base; |
259 | ||
260 | unsigned long *used_pdpes; | |
261 | struct i915_page_directory **page_directory; | |
d7b3de91 BW |
262 | }; |
263 | ||
81ba8aef MT |
264 | struct i915_pml4 { |
265 | struct i915_page_dma base; | |
266 | ||
267 | DECLARE_BITMAP(used_pml4es, GEN8_PML4ES_PER_PML4); | |
268 | struct i915_page_directory_pointer *pdps[GEN8_PML4ES_PER_PML4]; | |
269 | }; | |
270 | ||
0260c420 BW |
271 | struct i915_address_space { |
272 | struct drm_mm mm; | |
273 | struct drm_device *dev; | |
274 | struct list_head global_link; | |
c44ef60e MK |
275 | u64 start; /* Start offset always 0 for dri2 */ |
276 | u64 total; /* size addr space maps (ex. 2GB for ggtt) */ | |
0260c420 | 277 | |
c114f76a | 278 | struct i915_page_scratch *scratch_page; |
79ab9370 MK |
279 | struct i915_page_table *scratch_pt; |
280 | struct i915_page_directory *scratch_pd; | |
0260c420 BW |
281 | |
282 | /** | |
283 | * List of objects currently involved in rendering. | |
284 | * | |
285 | * Includes buffers having the contents of their GPU caches | |
97b2a6a1 | 286 | * flushed, not necessarily primitives. last_read_req |
0260c420 BW |
287 | * represents when the rendering involved will be completed. |
288 | * | |
289 | * A reference is held on the buffer while on this list. | |
290 | */ | |
291 | struct list_head active_list; | |
292 | ||
293 | /** | |
294 | * LRU list of objects which are not in the ringbuffer and | |
295 | * are ready to unbind, but are still in the GTT. | |
296 | * | |
97b2a6a1 | 297 | * last_read_req is NULL while an object is in this list. |
0260c420 BW |
298 | * |
299 | * A reference is not held on the buffer while on this list, | |
300 | * as merely being GTT-bound shouldn't prevent its being | |
301 | * freed, and we'll pull it off the list in the free path. | |
302 | */ | |
303 | struct list_head inactive_list; | |
304 | ||
305 | /* FIXME: Need a more generic return type */ | |
07749ef3 MT |
306 | gen6_pte_t (*pte_encode)(dma_addr_t addr, |
307 | enum i915_cache_level level, | |
308 | bool valid, u32 flags); /* Create a valid PTE */ | |
f329f5f6 DV |
309 | /* flags for pte_encode */ |
310 | #define PTE_READ_ONLY (1<<0) | |
678d96fb BW |
311 | int (*allocate_va_range)(struct i915_address_space *vm, |
312 | uint64_t start, | |
313 | uint64_t length); | |
0260c420 BW |
314 | void (*clear_range)(struct i915_address_space *vm, |
315 | uint64_t start, | |
316 | uint64_t length, | |
317 | bool use_scratch); | |
318 | void (*insert_entries)(struct i915_address_space *vm, | |
319 | struct sg_table *st, | |
320 | uint64_t start, | |
24f3a8cf | 321 | enum i915_cache_level cache_level, u32 flags); |
0260c420 | 322 | void (*cleanup)(struct i915_address_space *vm); |
777dc5bb DV |
323 | /** Unmap an object from an address space. This usually consists of |
324 | * setting the valid PTE entries to a reserved scratch page. */ | |
325 | void (*unbind_vma)(struct i915_vma *vma); | |
326 | /* Map an object into an address space with the given cache flags. */ | |
70b9f6f8 DV |
327 | int (*bind_vma)(struct i915_vma *vma, |
328 | enum i915_cache_level cache_level, | |
329 | u32 flags); | |
0260c420 BW |
330 | }; |
331 | ||
332 | /* The Graphics Translation Table is the way in which GEN hardware translates a | |
333 | * Graphics Virtual Address into a Physical Address. In addition to the normal | |
334 | * collateral associated with any va->pa translations GEN hardware also has a | |
335 | * portion of the GTT which can be mapped by the CPU and remain both coherent | |
336 | * and correct (in cases like swizzling). That region is referred to as GMADR in | |
337 | * the spec. | |
338 | */ | |
339 | struct i915_gtt { | |
340 | struct i915_address_space base; | |
0260c420 | 341 | |
c44ef60e MK |
342 | size_t stolen_size; /* Total size of stolen memory */ |
343 | u64 mappable_end; /* End offset that we can CPU map */ | |
0260c420 BW |
344 | struct io_mapping *mappable; /* Mapping to our CPU mappable region */ |
345 | phys_addr_t mappable_base; /* PA of our GMADR */ | |
346 | ||
347 | /** "Graphics Stolen Memory" holds the global PTEs */ | |
348 | void __iomem *gsm; | |
349 | ||
350 | bool do_idle_maps; | |
351 | ||
352 | int mtrr; | |
353 | ||
354 | /* global gtt ops */ | |
c44ef60e | 355 | int (*gtt_probe)(struct drm_device *dev, u64 *gtt_total, |
0260c420 | 356 | size_t *stolen, phys_addr_t *mappable_base, |
c44ef60e | 357 | u64 *mappable_end); |
0260c420 BW |
358 | }; |
359 | ||
360 | struct i915_hw_ppgtt { | |
361 | struct i915_address_space base; | |
362 | struct kref ref; | |
363 | struct drm_mm_node node; | |
563222a7 | 364 | unsigned long pd_dirty_rings; |
d7b3de91 | 365 | union { |
81ba8aef MT |
366 | struct i915_pml4 pml4; /* GEN8+ & 48b PPGTT */ |
367 | struct i915_page_directory_pointer pdp; /* GEN8+ */ | |
368 | struct i915_page_directory pd; /* GEN6-7 */ | |
d7b3de91 | 369 | }; |
0260c420 | 370 | |
4d884705 | 371 | struct drm_i915_file_private *file_priv; |
0260c420 | 372 | |
678d96fb BW |
373 | gen6_pte_t __iomem *pd_addr; |
374 | ||
0260c420 BW |
375 | int (*enable)(struct i915_hw_ppgtt *ppgtt); |
376 | int (*switch_mm)(struct i915_hw_ppgtt *ppgtt, | |
e85b26dc | 377 | struct drm_i915_gem_request *req); |
0260c420 BW |
378 | void (*debug_dump)(struct i915_hw_ppgtt *ppgtt, struct seq_file *m); |
379 | }; | |
380 | ||
678d96fb BW |
381 | /* For each pde iterates over every pde between from start until start + length. |
382 | * If start, and start+length are not perfectly divisible, the macro will round | |
383 | * down, and up as needed. The macro modifies pde, start, and length. Dev is | |
384 | * only used to differentiate shift values. Temp is temp. On gen6/7, start = 0, | |
385 | * and length = 2G effectively iterates over every PDE in the system. | |
386 | * | |
387 | * XXX: temp is not actually needed, but it saves doing the ALIGN operation. | |
388 | */ | |
389 | #define gen6_for_each_pde(pt, pd, start, length, temp, iter) \ | |
fdc454c1 MT |
390 | for (iter = gen6_pde_index(start); \ |
391 | pt = (pd)->page_table[iter], length > 0 && iter < I915_PDES; \ | |
392 | iter++, \ | |
678d96fb BW |
393 | temp = ALIGN(start+1, 1 << GEN6_PDE_SHIFT) - start, \ |
394 | temp = min_t(unsigned, temp, length), \ | |
395 | start += temp, length -= temp) | |
396 | ||
09942c65 MT |
397 | #define gen6_for_all_pdes(pt, ppgtt, iter) \ |
398 | for (iter = 0; \ | |
399 | pt = ppgtt->pd.page_table[iter], iter < I915_PDES; \ | |
400 | iter++) | |
401 | ||
678d96fb BW |
402 | static inline uint32_t i915_pte_index(uint64_t address, uint32_t pde_shift) |
403 | { | |
404 | const uint32_t mask = NUM_PTE(pde_shift) - 1; | |
405 | ||
406 | return (address >> PAGE_SHIFT) & mask; | |
407 | } | |
408 | ||
409 | /* Helper to counts the number of PTEs within the given length. This count | |
410 | * does not cross a page table boundary, so the max value would be | |
411 | * GEN6_PTES for GEN6, and GEN8_PTES for GEN8. | |
412 | */ | |
413 | static inline uint32_t i915_pte_count(uint64_t addr, size_t length, | |
414 | uint32_t pde_shift) | |
415 | { | |
416 | const uint64_t mask = ~((1 << pde_shift) - 1); | |
417 | uint64_t end; | |
418 | ||
419 | WARN_ON(length == 0); | |
420 | WARN_ON(offset_in_page(addr|length)); | |
421 | ||
422 | end = addr + length; | |
423 | ||
424 | if ((addr & mask) != (end & mask)) | |
425 | return NUM_PTE(pde_shift) - i915_pte_index(addr, pde_shift); | |
426 | ||
427 | return i915_pte_index(end, pde_shift) - i915_pte_index(addr, pde_shift); | |
428 | } | |
429 | ||
430 | static inline uint32_t i915_pde_index(uint64_t addr, uint32_t shift) | |
431 | { | |
432 | return (addr >> shift) & I915_PDE_MASK; | |
433 | } | |
434 | ||
435 | static inline uint32_t gen6_pte_index(uint32_t addr) | |
436 | { | |
437 | return i915_pte_index(addr, GEN6_PDE_SHIFT); | |
438 | } | |
439 | ||
440 | static inline size_t gen6_pte_count(uint32_t addr, uint32_t length) | |
441 | { | |
442 | return i915_pte_count(addr, length, GEN6_PDE_SHIFT); | |
443 | } | |
444 | ||
445 | static inline uint32_t gen6_pde_index(uint32_t addr) | |
446 | { | |
447 | return i915_pde_index(addr, GEN6_PDE_SHIFT); | |
448 | } | |
449 | ||
9271d959 MT |
450 | /* Equivalent to the gen6 version, For each pde iterates over every pde |
451 | * between from start until start + length. On gen8+ it simply iterates | |
452 | * over every page directory entry in a page directory. | |
453 | */ | |
454 | #define gen8_for_each_pde(pt, pd, start, length, temp, iter) \ | |
455 | for (iter = gen8_pde_index(start); \ | |
456 | pt = (pd)->page_table[iter], length > 0 && iter < I915_PDES; \ | |
457 | iter++, \ | |
458 | temp = ALIGN(start+1, 1 << GEN8_PDE_SHIFT) - start, \ | |
459 | temp = min(temp, length), \ | |
460 | start += temp, length -= temp) | |
461 | ||
6ac18502 MT |
462 | #define gen8_for_each_pdpe(pd, pdp, start, length, temp, iter) \ |
463 | for (iter = gen8_pdpe_index(start); \ | |
464 | pd = (pdp)->page_directory[iter], \ | |
465 | length > 0 && (iter < I915_PDPES_PER_PDP(dev)); \ | |
9271d959 MT |
466 | iter++, \ |
467 | temp = ALIGN(start+1, 1 << GEN8_PDPE_SHIFT) - start, \ | |
468 | temp = min(temp, length), \ | |
469 | start += temp, length -= temp) | |
470 | ||
762d9936 MT |
471 | #define gen8_for_each_pml4e(pdp, pml4, start, length, temp, iter) \ |
472 | for (iter = gen8_pml4e_index(start); \ | |
473 | pdp = (pml4)->pdps[iter], \ | |
474 | length > 0 && iter < GEN8_PML4ES_PER_PML4; \ | |
475 | iter++, \ | |
476 | temp = ALIGN(start+1, 1ULL << GEN8_PML4E_SHIFT) - start, \ | |
477 | temp = min(temp, length), \ | |
478 | start += temp, length -= temp) | |
479 | ||
9271d959 MT |
480 | static inline uint32_t gen8_pte_index(uint64_t address) |
481 | { | |
482 | return i915_pte_index(address, GEN8_PDE_SHIFT); | |
483 | } | |
484 | ||
485 | static inline uint32_t gen8_pde_index(uint64_t address) | |
486 | { | |
487 | return i915_pde_index(address, GEN8_PDE_SHIFT); | |
488 | } | |
489 | ||
490 | static inline uint32_t gen8_pdpe_index(uint64_t address) | |
491 | { | |
492 | return (address >> GEN8_PDPE_SHIFT) & GEN8_PDPE_MASK; | |
493 | } | |
494 | ||
495 | static inline uint32_t gen8_pml4e_index(uint64_t address) | |
496 | { | |
762d9936 | 497 | return (address >> GEN8_PML4E_SHIFT) & GEN8_PML4E_MASK; |
9271d959 MT |
498 | } |
499 | ||
33c8819f MT |
500 | static inline size_t gen8_pte_count(uint64_t address, uint64_t length) |
501 | { | |
502 | return i915_pte_count(address, length, GEN8_PDE_SHIFT); | |
503 | } | |
504 | ||
d852c7bf MK |
505 | static inline dma_addr_t |
506 | i915_page_dir_dma_addr(const struct i915_hw_ppgtt *ppgtt, const unsigned n) | |
507 | { | |
508 | return test_bit(n, ppgtt->pdp.used_pdpes) ? | |
567047be | 509 | px_dma(ppgtt->pdp.page_directory[n]) : |
79ab9370 | 510 | px_dma(ppgtt->base.scratch_pd); |
d852c7bf MK |
511 | } |
512 | ||
0260c420 BW |
513 | int i915_gem_gtt_init(struct drm_device *dev); |
514 | void i915_gem_init_global_gtt(struct drm_device *dev); | |
90d0a0e8 | 515 | void i915_global_gtt_cleanup(struct drm_device *dev); |
0260c420 | 516 | |
ee960be7 DV |
517 | |
518 | int i915_ppgtt_init(struct drm_device *dev, struct i915_hw_ppgtt *ppgtt); | |
82460d97 | 519 | int i915_ppgtt_init_hw(struct drm_device *dev); |
b3dd6b96 | 520 | int i915_ppgtt_init_ring(struct drm_i915_gem_request *req); |
ee960be7 | 521 | void i915_ppgtt_release(struct kref *kref); |
4d884705 DV |
522 | struct i915_hw_ppgtt *i915_ppgtt_create(struct drm_device *dev, |
523 | struct drm_i915_file_private *fpriv); | |
ee960be7 DV |
524 | static inline void i915_ppgtt_get(struct i915_hw_ppgtt *ppgtt) |
525 | { | |
526 | if (ppgtt) | |
527 | kref_get(&ppgtt->ref); | |
528 | } | |
529 | static inline void i915_ppgtt_put(struct i915_hw_ppgtt *ppgtt) | |
530 | { | |
531 | if (ppgtt) | |
532 | kref_put(&ppgtt->ref, i915_ppgtt_release); | |
533 | } | |
0260c420 BW |
534 | |
535 | void i915_check_and_clear_faults(struct drm_device *dev); | |
536 | void i915_gem_suspend_gtt_mappings(struct drm_device *dev); | |
537 | void i915_gem_restore_gtt_mappings(struct drm_device *dev); | |
538 | ||
539 | int __must_check i915_gem_gtt_prepare_object(struct drm_i915_gem_object *obj); | |
540 | void i915_gem_gtt_finish_object(struct drm_i915_gem_object *obj); | |
541 | ||
9abc4648 JL |
542 | static inline bool |
543 | i915_ggtt_view_equal(const struct i915_ggtt_view *a, | |
544 | const struct i915_ggtt_view *b) | |
545 | { | |
546 | if (WARN_ON(!a || !b)) | |
547 | return false; | |
548 | ||
8bd7ef16 JL |
549 | if (a->type != b->type) |
550 | return false; | |
551 | if (a->type == I915_GGTT_VIEW_PARTIAL) | |
552 | return !memcmp(&a->params, &b->params, sizeof(a->params)); | |
553 | return true; | |
9abc4648 JL |
554 | } |
555 | ||
91e6711e JL |
556 | size_t |
557 | i915_ggtt_view_size(struct drm_i915_gem_object *obj, | |
558 | const struct i915_ggtt_view *view); | |
559 | ||
0260c420 | 560 | #endif |