[deliverable/linux.git] / drivers / gpu / drm / i915 / i915_gem_gtt.h

/*
 * Copyright © 2014 Intel Corporation
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice (including the next
 * paragraph) shall be included in all copies or substantial portions of the
 * Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
 * IN THE SOFTWARE.
 *
 * Please try to maintain the following order within this file unless it makes
 * sense to do otherwise. From top to bottom:
 * 1. typedefs
 * 2. #defines, and macros
 * 3. structure definitions
 * 4. function prototypes
 *
 * Within each section, please try to order by generation in ascending order,
 * from top to bottom (ie. gen6 on the top, gen8 on the bottom).
 */

#ifndef __I915_GEM_GTT_H__
#define __I915_GEM_GTT_H__

struct drm_i915_file_private;

typedef uint32_t gen6_pte_t;
typedef uint64_t gen8_pte_t;
typedef uint64_t gen8_pde_t;

#define gtt_total_entries(gtt) ((gtt).base.total >> PAGE_SHIFT)


/* gen6-hsw has bit 11-4 for physical addr bit 39-32 */
#define GEN6_GTT_ADDR_ENCODE(addr)	((addr) | (((addr) >> 28) & 0xff0))
#define GEN6_PTE_ADDR_ENCODE(addr)	GEN6_GTT_ADDR_ENCODE(addr)
#define GEN6_PDE_ADDR_ENCODE(addr)	GEN6_GTT_ADDR_ENCODE(addr)
#define GEN6_PTE_CACHE_LLC		(2 << 1)
#define GEN6_PTE_UNCACHED		(1 << 1)
#define GEN6_PTE_VALID			(1 << 0)

#define I915_PTES(pte_len)		(PAGE_SIZE / (pte_len))
#define I915_PTE_MASK(pte_len)		(I915_PTES(pte_len) - 1)
#define I915_PDES			512
#define I915_PDE_MASK			(I915_PDES - 1)
#define NUM_PTE(pde_shift)     (1 << (pde_shift - PAGE_SHIFT))

#define GEN6_PTES			I915_PTES(sizeof(gen6_pte_t))
#define GEN6_PD_SIZE		        (I915_PDES * PAGE_SIZE)
#define GEN6_PD_ALIGN			(PAGE_SIZE * 16)
#define GEN6_PDE_SHIFT			22
#define GEN6_PDE_VALID			(1 << 0)

#define GEN7_PTE_CACHE_L3_LLC		(3 << 1)

#define BYT_PTE_SNOOPED_BY_CPU_CACHES	(1 << 2)
#define BYT_PTE_WRITEABLE		(1 << 1)

/* Cacheability Control is a 4-bit value. The low three bits are stored in bits
 * 3:1 of the PTE, while the fourth bit is stored in bit 11 of the PTE.
 */
#define HSW_CACHEABILITY_CONTROL(bits)	((((bits) & 0x7) << 1) | \
					 (((bits) & 0x8) << (11 - 3)))
#define HSW_WB_LLC_AGE3			HSW_CACHEABILITY_CONTROL(0x2)
#define HSW_WB_LLC_AGE0			HSW_CACHEABILITY_CONTROL(0x3)
#define HSW_WB_ELLC_LLC_AGE3		HSW_CACHEABILITY_CONTROL(0x8)
#define HSW_WB_ELLC_LLC_AGE0		HSW_CACHEABILITY_CONTROL(0xb)
#define HSW_WT_ELLC_LLC_AGE3		HSW_CACHEABILITY_CONTROL(0x7)
#define HSW_WT_ELLC_LLC_AGE0		HSW_CACHEABILITY_CONTROL(0x6)
#define HSW_PTE_UNCACHED		(0)
#define HSW_GTT_ADDR_ENCODE(addr)	((addr) | (((addr) >> 28) & 0x7f0))
#define HSW_PTE_ADDR_ENCODE(addr)	HSW_GTT_ADDR_ENCODE(addr)

/* GEN8 legacy style address is defined as a 3 level page table:
 * 31:30 | 29:21 | 20:12 |  11:0
 * PDPE  |  PDE  |  PTE  | offset
 * The difference as compared to normal x86 3 level page table is the PDPEs are
 * programmed via register.
 */
#define GEN8_PDPE_SHIFT			30
#define GEN8_PDPE_MASK			0x3
#define GEN8_PDE_SHIFT			21
#define GEN8_PDE_MASK			0x1ff
#define GEN8_PTE_SHIFT			12
#define GEN8_PTE_MASK			0x1ff
#define GEN8_LEGACY_PDPES		4
#define GEN8_PTES			I915_PTES(sizeof(gen8_pte_t))

#define PPAT_UNCACHED_INDEX		(_PAGE_PWT | _PAGE_PCD)
#define PPAT_CACHED_PDE_INDEX		0 /* WB LLC */
#define PPAT_CACHED_INDEX		_PAGE_PAT /* WB LLCeLLC */
#define PPAT_DISPLAY_ELLC_INDEX		_PAGE_PCD /* WT eLLC */

#define CHV_PPAT_SNOOP			(1<<6)
#define GEN8_PPAT_AGE(x)		(x<<4)
#define GEN8_PPAT_LLCeLLC		(3<<2)
#define GEN8_PPAT_LLCELLC		(2<<2)
#define GEN8_PPAT_LLC			(1<<2)
#define GEN8_PPAT_WB			(3<<0)
#define GEN8_PPAT_WT			(2<<0)
#define GEN8_PPAT_WC			(1<<0)
#define GEN8_PPAT_UC			(0<<0)
#define GEN8_PPAT_ELLC_OVERRIDE		(0<<2)
#define GEN8_PPAT(i, x)			((uint64_t) (x) << ((i) * 8))

enum i915_ggtt_view_type {
	I915_GGTT_VIEW_NORMAL = 0,
	I915_GGTT_VIEW_ROTATED
};

struct intel_rotation_info {
	unsigned int height;
	unsigned int pitch;
	uint32_t pixel_format;
	uint64_t fb_modifier;
};

struct i915_ggtt_view {
	enum i915_ggtt_view_type type;

	struct sg_table *pages;

	union {
		struct intel_rotation_info rotation_info;
	};
};

extern const struct i915_ggtt_view i915_ggtt_view_normal;
extern const struct i915_ggtt_view i915_ggtt_view_rotated;

enum i915_cache_level;

/**
 * A VMA represents a GEM BO that is bound into an address space. Therefore, a
 * VMA's presence cannot be guaranteed before binding, or after unbinding the
 * object into/from the address space.
 *
 * To make things as simple as possible (ie. no refcounting), a VMA's lifetime
 * will always be <= an objects lifetime. So object refcounting should cover us.
 */
struct i915_vma {
	struct drm_mm_node node;
	struct drm_i915_gem_object *obj;
	struct i915_address_space *vm;

	/** Flags and address space this VMA is bound to */
#define GLOBAL_BIND	(1<<0)
#define LOCAL_BIND	(1<<1)
#define PTE_READ_ONLY	(1<<2)
	unsigned int bound : 4;

	/**
	 * Support different GGTT views into the same object.
	 * This means there can be multiple VMA mappings per object and per VM.
	 * i915_ggtt_view_type is used to distinguish between those entries.
	 * The default one of zero (I915_GGTT_VIEW_NORMAL) is default and also
	 * assumed in GEM functions which take no ggtt view parameter.
	 */
	struct i915_ggtt_view ggtt_view;

	/** This object's place on the active/inactive lists */
	struct list_head mm_list;

	struct list_head vma_link; /* Link in the object's VMA list */

	/** This vma's place in the batchbuffer or on the eviction list */
	struct list_head exec_list;

	/**
	 * Used for performing relocations during execbuffer insertion.
	 */
	struct hlist_node exec_node;
	unsigned long exec_handle;
	struct drm_i915_gem_exec_object2 *exec_entry;

	/**
	 * How many users have pinned this object in GTT space. The following
	 * users can each hold at most one reference: pwrite/pread, execbuffer
	 * (objects are not allowed multiple times for the same batchbuffer),
	 * and the framebuffer code. When switching/pageflipping, the
	 * framebuffer code has at most two buffers pinned per crtc.
	 *
	 * In the worst case this is 1 + 1 + 1 + 2*2 = 7. That would fit into 3
	 * bits with absolutely no headroom. So use 4 bits. */
	unsigned int pin_count:4;
#define DRM_I915_GEM_OBJECT_MAX_PIN_COUNT 0xf

	/** Unmap an object from an address space. This usually consists of
	 * setting the valid PTE entries to a reserved scratch page. */
	void (*unbind_vma)(struct i915_vma *vma);
	/* Map an object into an address space with the given cache flags. */
	void (*bind_vma)(struct i915_vma *vma,
			 enum i915_cache_level cache_level,
			 u32 flags);
};

struct i915_page_table {
	struct page *page;
	dma_addr_t daddr;

	unsigned long *used_ptes;
};

struct i915_page_directory {
	struct page *page; /* NULL for GEN6-GEN7 */
	union {
		uint32_t pd_offset;
		dma_addr_t daddr;
	};

	struct i915_page_table *page_table[I915_PDES]; /* PDEs */
};

struct i915_page_directory_pointer {
	/* struct page *page; */
	struct i915_page_directory *page_directory[GEN8_LEGACY_PDPES];
};

struct i915_address_space {
	struct drm_mm mm;
	struct drm_device *dev;
	struct list_head global_link;
	unsigned long start;		/* Start offset always 0 for dri2 */
	size_t total;		/* size addr space maps (ex. 2GB for ggtt) */

	struct {
		dma_addr_t addr;
		struct page *page;
	} scratch;

	/**
	 * List of objects currently involved in rendering.
	 *
	 * Includes buffers having the contents of their GPU caches
	 * flushed, not necessarily primitives. last_read_req
	 * represents when the rendering involved will be completed.
	 *
	 * A reference is held on the buffer while on this list.
	 */
	struct list_head active_list;

	/**
	 * LRU list of objects which are not in the ringbuffer and
	 * are ready to unbind, but are still in the GTT.
	 *
	 * last_read_req is NULL while an object is in this list.
	 *
	 * A reference is not held on the buffer while on this list,
	 * as merely being GTT-bound shouldn't prevent its being
	 * freed, and we'll pull it off the list in the free path.
	 */
	struct list_head inactive_list;

	/* FIXME: Need a more generic return type */
	gen6_pte_t (*pte_encode)(dma_addr_t addr,
				 enum i915_cache_level level,
				 bool valid, u32 flags); /* Create a valid PTE */
	int (*allocate_va_range)(struct i915_address_space *vm,
				 uint64_t start,
				 uint64_t length);
	void (*clear_range)(struct i915_address_space *vm,
			    uint64_t start,
			    uint64_t length,
			    bool use_scratch);
	void (*insert_entries)(struct i915_address_space *vm,
			       struct sg_table *st,
			       uint64_t start,
			       enum i915_cache_level cache_level, u32 flags);
	void (*cleanup)(struct i915_address_space *vm);
};

/* The Graphics Translation Table is the way in which GEN hardware translates a
 * Graphics Virtual Address into a Physical Address. In addition to the normal
 * collateral associated with any va->pa translations GEN hardware also has a
 * portion of the GTT which can be mapped by the CPU and remain both coherent
 * and correct (in cases like swizzling). That region is referred to as GMADR in
 * the spec.
 */
struct i915_gtt {
	struct i915_address_space base;
	size_t stolen_size;		/* Total size of stolen memory */

	unsigned long mappable_end;	/* End offset that we can CPU map */
	struct io_mapping *mappable;	/* Mapping to our CPU mappable region */
	phys_addr_t mappable_base;	/* PA of our GMADR */

	/** "Graphics Stolen Memory" holds the global PTEs */
	void __iomem *gsm;

	bool do_idle_maps;

	int mtrr;

	/* global gtt ops */
	int (*gtt_probe)(struct drm_device *dev, size_t *gtt_total,
			  size_t *stolen, phys_addr_t *mappable_base,
			  unsigned long *mappable_end);
};

struct i915_hw_ppgtt {
	struct i915_address_space base;
	struct kref ref;
	struct drm_mm_node node;
	unsigned long pd_dirty_rings;
	union {
		struct i915_page_directory_pointer pdp;
		struct i915_page_directory pd;
	};

	struct i915_page_table *scratch_pt;
	struct i915_page_directory *scratch_pd;

	struct drm_i915_file_private *file_priv;

	gen6_pte_t __iomem *pd_addr;

	int (*enable)(struct i915_hw_ppgtt *ppgtt);
	int (*switch_mm)(struct i915_hw_ppgtt *ppgtt,
			 struct intel_engine_cs *ring);
	void (*debug_dump)(struct i915_hw_ppgtt *ppgtt, struct seq_file *m);
};

/* For each pde iterates over every pde between from start until start + length.
 * If start, and start+length are not perfectly divisible, the macro will round
 * down, and up as needed. The macro modifies pde, start, and length. Dev is
 * only used to differentiate shift values. Temp is temp.  On gen6/7, start = 0,
 * and length = 2G effectively iterates over every PDE in the system.
 *
 * XXX: temp is not actually needed, but it saves doing the ALIGN operation.
 */
#define gen6_for_each_pde(pt, pd, start, length, temp, iter) \
	for (iter = gen6_pde_index(start); \
	     pt = (pd)->page_table[iter], length > 0 && iter < I915_PDES; \
	     iter++, \
	     temp = ALIGN(start+1, 1 << GEN6_PDE_SHIFT) - start, \
	     temp = min_t(unsigned, temp, length), \
	     start += temp, length -= temp)

#define gen6_for_all_pdes(pt, ppgtt, iter)  \
	for (iter = 0;		\
	     pt = ppgtt->pd.page_table[iter], iter < I915_PDES;	\
	     iter++)

static inline uint32_t i915_pte_index(uint64_t address, uint32_t pde_shift)
{
	const uint32_t mask = NUM_PTE(pde_shift) - 1;

	return (address >> PAGE_SHIFT) & mask;
}

/* Helper to counts the number of PTEs within the given length. This count
 * does not cross a page table boundary, so the max value would be
 * GEN6_PTES for GEN6, and GEN8_PTES for GEN8.
*/
static inline uint32_t i915_pte_count(uint64_t addr, size_t length,
				      uint32_t pde_shift)
{
	const uint64_t mask = ~((1 << pde_shift) - 1);
	uint64_t end;

	WARN_ON(length == 0);
	WARN_ON(offset_in_page(addr|length));

	end = addr + length;

	if ((addr & mask) != (end & mask))
		return NUM_PTE(pde_shift) - i915_pte_index(addr, pde_shift);

	return i915_pte_index(end, pde_shift) - i915_pte_index(addr, pde_shift);
}

static inline uint32_t i915_pde_index(uint64_t addr, uint32_t shift)
{
	return (addr >> shift) & I915_PDE_MASK;
}

static inline uint32_t gen6_pte_index(uint32_t addr)
{
	return i915_pte_index(addr, GEN6_PDE_SHIFT);
}

static inline size_t gen6_pte_count(uint32_t addr, uint32_t length)
{
	return i915_pte_count(addr, length, GEN6_PDE_SHIFT);
}

static inline uint32_t gen6_pde_index(uint32_t addr)
{
	return i915_pde_index(addr, GEN6_PDE_SHIFT);
}

/* Equivalent to the gen6 version, For each pde iterates over every pde
 * between from start until start + length. On gen8+ it simply iterates
 * over every page directory entry in a page directory.
 */
#define gen8_for_each_pde(pt, pd, start, length, temp, iter)		\
	for (iter = gen8_pde_index(start); \
	     pt = (pd)->page_table[iter], length > 0 && iter < I915_PDES;	\
	     iter++,				\
	     temp = ALIGN(start+1, 1 << GEN8_PDE_SHIFT) - start,	\
	     temp = min(temp, length),					\
	     start += temp, length -= temp)

#define gen8_for_each_pdpe(pd, pdp, start, length, temp, iter)		\
	for (iter = gen8_pdpe_index(start);	\
	     pd = (pdp)->page_directory[iter], length > 0 && iter < GEN8_LEGACY_PDPES;	\
	     iter++,				\
	     temp = ALIGN(start+1, 1 << GEN8_PDPE_SHIFT) - start,	\
	     temp = min(temp, length),					\
	     start += temp, length -= temp)

/* Clamp length to the next page_directory boundary */
static inline uint64_t gen8_clamp_pd(uint64_t start, uint64_t length)
{
	uint64_t next_pd = ALIGN(start + 1, 1 << GEN8_PDPE_SHIFT);

	if (next_pd > (start + length))
		return length;

	return next_pd - start;
}

static inline uint32_t gen8_pte_index(uint64_t address)
{
	return i915_pte_index(address, GEN8_PDE_SHIFT);
}

static inline uint32_t gen8_pde_index(uint64_t address)
{
	return i915_pde_index(address, GEN8_PDE_SHIFT);
}

static inline uint32_t gen8_pdpe_index(uint64_t address)
{
	return (address >> GEN8_PDPE_SHIFT) & GEN8_PDPE_MASK;
}

static inline uint32_t gen8_pml4e_index(uint64_t address)
{
	WARN_ON(1); /* For 64B */
	return 0;
}

int i915_gem_gtt_init(struct drm_device *dev);
void i915_gem_init_global_gtt(struct drm_device *dev);
void i915_global_gtt_cleanup(struct drm_device *dev);


int i915_ppgtt_init(struct drm_device *dev, struct i915_hw_ppgtt *ppgtt);
int i915_ppgtt_init_hw(struct drm_device *dev);
void i915_ppgtt_release(struct kref *kref);
struct i915_hw_ppgtt *i915_ppgtt_create(struct drm_device *dev,
					struct drm_i915_file_private *fpriv);
static inline void i915_ppgtt_get(struct i915_hw_ppgtt *ppgtt)
{
	if (ppgtt)
		kref_get(&ppgtt->ref);
}
static inline void i915_ppgtt_put(struct i915_hw_ppgtt *ppgtt)
{
	if (ppgtt)
		kref_put(&ppgtt->ref, i915_ppgtt_release);
}

void i915_check_and_clear_faults(struct drm_device *dev);
void i915_gem_suspend_gtt_mappings(struct drm_device *dev);
void i915_gem_restore_gtt_mappings(struct drm_device *dev);

int __must_check i915_gem_gtt_prepare_object(struct drm_i915_gem_object *obj);
void i915_gem_gtt_finish_object(struct drm_i915_gem_object *obj);

static inline bool
i915_ggtt_view_equal(const struct i915_ggtt_view *a,
                     const struct i915_ggtt_view *b)
{
	if (WARN_ON(!a || !b))
		return false;

	return a->type == b->type;
}

#endif
Commit	Line	Data
0260c420 BW	1	/*
	2	* Copyright © 2014 Intel Corporation
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice (including the next
	12	* paragraph) shall be included in all copies or substantial portions of the
	13	* Software.
	14	*
	15	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	16	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	17	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	18	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	19	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
	20	* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
	21	* IN THE SOFTWARE.
	22	*
	23	* Please try to maintain the following order within this file unless it makes
	24	* sense to do otherwise. From top to bottom:
	25	* 1. typedefs
	26	* 2. #defines, and macros
	27	* 3. structure definitions
	28	* 4. function prototypes
	29	*
	30	* Within each section, please try to order by generation in ascending order,
	31	* from top to bottom (ie. gen6 on the top, gen8 on the bottom).
	32	*/
	33
	34	#ifndef __I915_GEM_GTT_H__
	35	#define __I915_GEM_GTT_H__
	36
4d884705 DV	37	struct drm_i915_file_private;
4d884705 DV	38
07749ef3 MT	39	typedef uint32_t gen6_pte_t;
	40	typedef uint64_t gen8_pte_t;
	41	typedef uint64_t gen8_pde_t;
0260c420 BW	42
	43	#define gtt_total_entries(gtt) ((gtt).base.total >> PAGE_SHIFT)
	44
07749ef3	45
0260c420 BW	46	/* gen6-hsw has bit 11-4 for physical addr bit 39-32 */
	47	#define GEN6_GTT_ADDR_ENCODE(addr) ((addr) \| (((addr) >> 28) & 0xff0))
	48	#define GEN6_PTE_ADDR_ENCODE(addr) GEN6_GTT_ADDR_ENCODE(addr)
	49	#define GEN6_PDE_ADDR_ENCODE(addr) GEN6_GTT_ADDR_ENCODE(addr)
	50	#define GEN6_PTE_CACHE_LLC (2 << 1)
	51	#define GEN6_PTE_UNCACHED (1 << 1)
	52	#define GEN6_PTE_VALID (1 << 0)
	53
07749ef3 MT	54	#define I915_PTES(pte_len) (PAGE_SIZE / (pte_len))
	55	#define I915_PTE_MASK(pte_len) (I915_PTES(pte_len) - 1)
	56	#define I915_PDES 512
	57	#define I915_PDE_MASK (I915_PDES - 1)
678d96fb	58	#define NUM_PTE(pde_shift) (1 << (pde_shift - PAGE_SHIFT))
07749ef3 MT	59
	60	#define GEN6_PTES I915_PTES(sizeof(gen6_pte_t))
	61	#define GEN6_PD_SIZE (I915_PDES * PAGE_SIZE)
0260c420	62	#define GEN6_PD_ALIGN (PAGE_SIZE * 16)
678d96fb	63	#define GEN6_PDE_SHIFT 22
0260c420 BW	64	#define GEN6_PDE_VALID (1 << 0)
	65
	66	#define GEN7_PTE_CACHE_L3_LLC (3 << 1)
	67
	68	#define BYT_PTE_SNOOPED_BY_CPU_CACHES (1 << 2)
	69	#define BYT_PTE_WRITEABLE (1 << 1)
	70
	71	/* Cacheability Control is a 4-bit value. The low three bits are stored in bits
	72	* 3:1 of the PTE, while the fourth bit is stored in bit 11 of the PTE.
	73	*/
	74	#define HSW_CACHEABILITY_CONTROL(bits) ((((bits) & 0x7) << 1) \| \
	75	(((bits) & 0x8) << (11 - 3)))
	76	#define HSW_WB_LLC_AGE3 HSW_CACHEABILITY_CONTROL(0x2)
	77	#define HSW_WB_LLC_AGE0 HSW_CACHEABILITY_CONTROL(0x3)
	78	#define HSW_WB_ELLC_LLC_AGE3 HSW_CACHEABILITY_CONTROL(0x8)
	79	#define HSW_WB_ELLC_LLC_AGE0 HSW_CACHEABILITY_CONTROL(0xb)
	80	#define HSW_WT_ELLC_LLC_AGE3 HSW_CACHEABILITY_CONTROL(0x7)
	81	#define HSW_WT_ELLC_LLC_AGE0 HSW_CACHEABILITY_CONTROL(0x6)
	82	#define HSW_PTE_UNCACHED (0)
	83	#define HSW_GTT_ADDR_ENCODE(addr) ((addr) \| (((addr) >> 28) & 0x7f0))
	84	#define HSW_PTE_ADDR_ENCODE(addr) HSW_GTT_ADDR_ENCODE(addr)
	85
	86	/* GEN8 legacy style address is defined as a 3 level page table:
	87	* 31:30 \| 29:21 \| 20:12 \| 11:0
	88	* PDPE \| PDE \| PTE \| offset
	89	* The difference as compared to normal x86 3 level page table is the PDPEs are
	90	* programmed via register.
	91	*/
	92	#define GEN8_PDPE_SHIFT 30
	93	#define GEN8_PDPE_MASK 0x3
	94	#define GEN8_PDE_SHIFT 21
	95	#define GEN8_PDE_MASK 0x1ff
	96	#define GEN8_PTE_SHIFT 12
	97	#define GEN8_PTE_MASK 0x1ff
76643600	98	#define GEN8_LEGACY_PDPES 4
07749ef3	99	#define GEN8_PTES I915_PTES(sizeof(gen8_pte_t))
0260c420 BW	100
	101	#define PPAT_UNCACHED_INDEX (_PAGE_PWT \| _PAGE_PCD)
	102	#define PPAT_CACHED_PDE_INDEX 0 /* WB LLC */
	103	#define PPAT_CACHED_INDEX _PAGE_PAT /* WB LLCeLLC */
	104	#define PPAT_DISPLAY_ELLC_INDEX _PAGE_PCD /* WT eLLC */
	105
ee0ce478	106	#define CHV_PPAT_SNOOP (1<<6)
0260c420 BW	107	#define GEN8_PPAT_AGE(x) (x<<4)
	108	#define GEN8_PPAT_LLCeLLC (3<<2)
	109	#define GEN8_PPAT_LLCELLC (2<<2)
	110	#define GEN8_PPAT_LLC (1<<2)
	111	#define GEN8_PPAT_WB (3<<0)
	112	#define GEN8_PPAT_WT (2<<0)
	113	#define GEN8_PPAT_WC (1<<0)
	114	#define GEN8_PPAT_UC (0<<0)
	115	#define GEN8_PPAT_ELLC_OVERRIDE (0<<2)
	116	#define GEN8_PPAT(i, x) ((uint64_t) (x) << ((i) * 8))
	117
fe14d5f4 TU	118	enum i915_ggtt_view_type {
fe14d5f4 TU	119	I915_GGTT_VIEW_NORMAL = 0,
50470bb0 TU	120	I915_GGTT_VIEW_ROTATED
	121	};
	122
	123	struct intel_rotation_info {
	124	unsigned int height;
	125	unsigned int pitch;
	126	uint32_t pixel_format;
	127	uint64_t fb_modifier;
fe14d5f4 TU	128	};
	129
	130	struct i915_ggtt_view {
	131	enum i915_ggtt_view_type type;
	132
	133	struct sg_table *pages;
50470bb0 TU	134
	135	union {
	136	struct intel_rotation_info rotation_info;
	137	};
fe14d5f4 TU	138	};
	139
	140	extern const struct i915_ggtt_view i915_ggtt_view_normal;
9abc4648	141	extern const struct i915_ggtt_view i915_ggtt_view_rotated;
fe14d5f4	142
0260c420	143	enum i915_cache_level;
fe14d5f4	144
0260c420 BW	145	/**
	146	* A VMA represents a GEM BO that is bound into an address space. Therefore, a
	147	* VMA's presence cannot be guaranteed before binding, or after unbinding the
	148	* object into/from the address space.
	149	*
	150	* To make things as simple as possible (ie. no refcounting), a VMA's lifetime
	151	* will always be <= an objects lifetime. So object refcounting should cover us.
	152	*/
	153	struct i915_vma {
	154	struct drm_mm_node node;
	155	struct drm_i915_gem_object *obj;
	156	struct i915_address_space *vm;
	157
aff43766 TU	158	/** Flags and address space this VMA is bound to */
	159	#define GLOBAL_BIND (1<<0)
	160	#define LOCAL_BIND (1<<1)
	161	#define PTE_READ_ONLY (1<<2)
	162	unsigned int bound : 4;
	163
fe14d5f4 TU	164	/**
	165	* Support different GGTT views into the same object.
	166	* This means there can be multiple VMA mappings per object and per VM.
	167	* i915_ggtt_view_type is used to distinguish between those entries.
	168	* The default one of zero (I915_GGTT_VIEW_NORMAL) is default and also
	169	* assumed in GEM functions which take no ggtt view parameter.
	170	*/
	171	struct i915_ggtt_view ggtt_view;
	172
0260c420 BW	173	/** This object's place on the active/inactive lists */
	174	struct list_head mm_list;
	175
	176	struct list_head vma_link; /* Link in the object's VMA list */
	177
	178	/** This vma's place in the batchbuffer or on the eviction list */
	179	struct list_head exec_list;
	180
	181	/**
	182	* Used for performing relocations during execbuffer insertion.
	183	*/
	184	struct hlist_node exec_node;
	185	unsigned long exec_handle;
	186	struct drm_i915_gem_exec_object2 *exec_entry;
	187
	188	/**
	189	* How many users have pinned this object in GTT space. The following
4feb7659 DV	190	* users can each hold at most one reference: pwrite/pread, execbuffer
	191	* (objects are not allowed multiple times for the same batchbuffer),
	192	* and the framebuffer code. When switching/pageflipping, the
	193	* framebuffer code has at most two buffers pinned per crtc.
0260c420 BW	194	*
	195	* In the worst case this is 1 + 1 + 1 + 2*2 = 7. That would fit into 3
	196	* bits with absolutely no headroom. So use 4 bits. */
	197	unsigned int pin_count:4;
	198	#define DRM_I915_GEM_OBJECT_MAX_PIN_COUNT 0xf
	199
	200	/** Unmap an object from an address space. This usually consists of
	201	* setting the valid PTE entries to a reserved scratch page. */
	202	void (unbind_vma)(struct i915_vma vma);
	203	/* Map an object into an address space with the given cache flags. */
0260c420 BW	204	void (bind_vma)(struct i915_vma vma,
	205	enum i915_cache_level cache_level,
	206	u32 flags);
	207	};
	208
ec565b3c	209	struct i915_page_table {
d7b3de91	210	struct page *page;
7324cc04	211	dma_addr_t daddr;
678d96fb BW	212
678d96fb BW	213	unsigned long *used_ptes;
d7b3de91 BW	214	};
d7b3de91 BW	215
ec565b3c	216	struct i915_page_directory {
d7b3de91	217	struct page page; / NULL for GEN6-GEN7 */
7324cc04 BW	218	union {
	219	uint32_t pd_offset;
	220	dma_addr_t daddr;
	221	};
	222
ec565b3c	223	struct i915_page_table page_table[I915_PDES]; / PDEs */
d7b3de91 BW	224	};
d7b3de91 BW	225
ec565b3c	226	struct i915_page_directory_pointer {
d7b3de91	227	/* struct page page; /
ec565b3c	228	struct i915_page_directory *page_directory[GEN8_LEGACY_PDPES];
d7b3de91 BW	229	};
d7b3de91 BW	230
0260c420 BW	231	struct i915_address_space {
	232	struct drm_mm mm;
	233	struct drm_device *dev;
	234	struct list_head global_link;
	235	unsigned long start; /* Start offset always 0 for dri2 */
	236	size_t total; /* size addr space maps (ex. 2GB for ggtt) */
	237
	238	struct {
	239	dma_addr_t addr;
	240	struct page *page;
	241	} scratch;
	242
	243	/**
	244	* List of objects currently involved in rendering.
	245	*
	246	* Includes buffers having the contents of their GPU caches
97b2a6a1	247	* flushed, not necessarily primitives. last_read_req
0260c420 BW	248	* represents when the rendering involved will be completed.
	249	*
	250	* A reference is held on the buffer while on this list.
	251	*/
	252	struct list_head active_list;
	253
	254	/**
	255	* LRU list of objects which are not in the ringbuffer and
	256	* are ready to unbind, but are still in the GTT.
	257	*
97b2a6a1	258	* last_read_req is NULL while an object is in this list.
0260c420 BW	259	*
	260	* A reference is not held on the buffer while on this list,
	261	* as merely being GTT-bound shouldn't prevent its being
	262	* freed, and we'll pull it off the list in the free path.
	263	*/
	264	struct list_head inactive_list;
	265
	266	/* FIXME: Need a more generic return type */
07749ef3 MT	267	gen6_pte_t (*pte_encode)(dma_addr_t addr,
	268	enum i915_cache_level level,
	269	bool valid, u32 flags); /* Create a valid PTE */
678d96fb BW	270	int (allocate_va_range)(struct i915_address_space vm,
	271	uint64_t start,
	272	uint64_t length);
0260c420 BW	273	void (clear_range)(struct i915_address_space vm,
	274	uint64_t start,
	275	uint64_t length,
	276	bool use_scratch);
	277	void (insert_entries)(struct i915_address_space vm,
	278	struct sg_table *st,
	279	uint64_t start,
24f3a8cf	280	enum i915_cache_level cache_level, u32 flags);
0260c420 BW	281	void (cleanup)(struct i915_address_space vm);
	282	};
	283
	284	/* The Graphics Translation Table is the way in which GEN hardware translates a
	285	* Graphics Virtual Address into a Physical Address. In addition to the normal
	286	* collateral associated with any va->pa translations GEN hardware also has a
	287	* portion of the GTT which can be mapped by the CPU and remain both coherent
	288	* and correct (in cases like swizzling). That region is referred to as GMADR in
	289	* the spec.
	290	*/
	291	struct i915_gtt {
	292	struct i915_address_space base;
	293	size_t stolen_size; /* Total size of stolen memory */
	294
	295	unsigned long mappable_end; /* End offset that we can CPU map */
	296	struct io_mapping mappable; / Mapping to our CPU mappable region */
	297	phys_addr_t mappable_base; /* PA of our GMADR */
	298
	299	/** "Graphics Stolen Memory" holds the global PTEs */
	300	void __iomem *gsm;
	301
	302	bool do_idle_maps;
	303
	304	int mtrr;
	305
	306	/* global gtt ops */
	307	int (gtt_probe)(struct drm_device dev, size_t *gtt_total,
	308	size_t stolen, phys_addr_t mappable_base,
	309	unsigned long *mappable_end);
	310	};
	311
	312	struct i915_hw_ppgtt {
	313	struct i915_address_space base;
	314	struct kref ref;
	315	struct drm_mm_node node;
563222a7	316	unsigned long pd_dirty_rings;
d7b3de91	317	union {
ec565b3c MT	318	struct i915_page_directory_pointer pdp;
ec565b3c MT	319	struct i915_page_directory pd;
d7b3de91	320	};
0260c420	321
ec565b3c	322	struct i915_page_table *scratch_pt;
7cb6d7ac	323	struct i915_page_directory *scratch_pd;
4933d519	324
4d884705	325	struct drm_i915_file_private *file_priv;
0260c420	326
678d96fb BW	327	gen6_pte_t __iomem *pd_addr;
678d96fb BW	328
0260c420 BW	329	int (enable)(struct i915_hw_ppgtt ppgtt);
0260c420 BW	330	int (switch_mm)(struct i915_hw_ppgtt ppgtt,
6689c167	331	struct intel_engine_cs *ring);
0260c420 BW	332	void (debug_dump)(struct i915_hw_ppgtt ppgtt, struct seq_file *m);
	333	};
	334
678d96fb BW	335	/* For each pde iterates over every pde between from start until start + length.
	336	* If start, and start+length are not perfectly divisible, the macro will round
	337	* down, and up as needed. The macro modifies pde, start, and length. Dev is
	338	* only used to differentiate shift values. Temp is temp. On gen6/7, start = 0,
	339	* and length = 2G effectively iterates over every PDE in the system.
	340	*
	341	* XXX: temp is not actually needed, but it saves doing the ALIGN operation.
	342	*/
	343	#define gen6_for_each_pde(pt, pd, start, length, temp, iter) \
fdc454c1 MT	344	for (iter = gen6_pde_index(start); \
	345	pt = (pd)->page_table[iter], length > 0 && iter < I915_PDES; \
	346	iter++, \
678d96fb BW	347	temp = ALIGN(start+1, 1 << GEN6_PDE_SHIFT) - start, \
	348	temp = min_t(unsigned, temp, length), \
	349	start += temp, length -= temp)
	350
09942c65 MT	351	#define gen6_for_all_pdes(pt, ppgtt, iter) \
	352	for (iter = 0; \
	353	pt = ppgtt->pd.page_table[iter], iter < I915_PDES; \
	354	iter++)
	355
678d96fb BW	356	static inline uint32_t i915_pte_index(uint64_t address, uint32_t pde_shift)
	357	{
	358	const uint32_t mask = NUM_PTE(pde_shift) - 1;
	359
	360	return (address >> PAGE_SHIFT) & mask;
	361	}
	362
	363	/* Helper to counts the number of PTEs within the given length. This count
	364	* does not cross a page table boundary, so the max value would be
	365	* GEN6_PTES for GEN6, and GEN8_PTES for GEN8.
	366	*/
	367	static inline uint32_t i915_pte_count(uint64_t addr, size_t length,
	368	uint32_t pde_shift)
	369	{
	370	const uint64_t mask = ~((1 << pde_shift) - 1);
	371	uint64_t end;
	372
	373	WARN_ON(length == 0);
	374	WARN_ON(offset_in_page(addr\|length));
	375
	376	end = addr + length;
	377
	378	if ((addr & mask) != (end & mask))
	379	return NUM_PTE(pde_shift) - i915_pte_index(addr, pde_shift);
	380
	381	return i915_pte_index(end, pde_shift) - i915_pte_index(addr, pde_shift);
	382	}
	383
	384	static inline uint32_t i915_pde_index(uint64_t addr, uint32_t shift)
	385	{
	386	return (addr >> shift) & I915_PDE_MASK;
	387	}
	388
	389	static inline uint32_t gen6_pte_index(uint32_t addr)
	390	{
	391	return i915_pte_index(addr, GEN6_PDE_SHIFT);
	392	}
	393
	394	static inline size_t gen6_pte_count(uint32_t addr, uint32_t length)
	395	{
	396	return i915_pte_count(addr, length, GEN6_PDE_SHIFT);
	397	}
	398
	399	static inline uint32_t gen6_pde_index(uint32_t addr)
	400	{
	401	return i915_pde_index(addr, GEN6_PDE_SHIFT);
	402	}
	403
9271d959 MT	404	/* Equivalent to the gen6 version, For each pde iterates over every pde
	405	* between from start until start + length. On gen8+ it simply iterates
	406	* over every page directory entry in a page directory.
	407	*/
	408	#define gen8_for_each_pde(pt, pd, start, length, temp, iter) \
	409	for (iter = gen8_pde_index(start); \
	410	pt = (pd)->page_table[iter], length > 0 && iter < I915_PDES; \
	411	iter++, \
	412	temp = ALIGN(start+1, 1 << GEN8_PDE_SHIFT) - start, \
	413	temp = min(temp, length), \
	414	start += temp, length -= temp)
	415
	416	#define gen8_for_each_pdpe(pd, pdp, start, length, temp, iter) \
	417	for (iter = gen8_pdpe_index(start); \
	418	pd = (pdp)->page_directory[iter], length > 0 && iter < GEN8_LEGACY_PDPES; \
	419	iter++, \
	420	temp = ALIGN(start+1, 1 << GEN8_PDPE_SHIFT) - start, \
	421	temp = min(temp, length), \
	422	start += temp, length -= temp)
	423
	424	/* Clamp length to the next page_directory boundary */
	425	static inline uint64_t gen8_clamp_pd(uint64_t start, uint64_t length)
	426	{
	427	uint64_t next_pd = ALIGN(start + 1, 1 << GEN8_PDPE_SHIFT);
	428
	429	if (next_pd > (start + length))
	430	return length;
	431
	432	return next_pd - start;
	433	}
	434
	435	static inline uint32_t gen8_pte_index(uint64_t address)
	436	{
	437	return i915_pte_index(address, GEN8_PDE_SHIFT);
	438	}
	439
	440	static inline uint32_t gen8_pde_index(uint64_t address)
	441	{
	442	return i915_pde_index(address, GEN8_PDE_SHIFT);
	443	}
	444
	445	static inline uint32_t gen8_pdpe_index(uint64_t address)
	446	{
	447	return (address >> GEN8_PDPE_SHIFT) & GEN8_PDPE_MASK;
	448	}
	449
	450	static inline uint32_t gen8_pml4e_index(uint64_t address)
	451	{
	452	WARN_ON(1); /* For 64B */
	453	return 0;
	454	}
	455
0260c420 BW	456	int i915_gem_gtt_init(struct drm_device *dev);
0260c420 BW	457	void i915_gem_init_global_gtt(struct drm_device *dev);
90d0a0e8	458	void i915_global_gtt_cleanup(struct drm_device *dev);
0260c420	459
ee960be7 DV	460
ee960be7 DV	461	int i915_ppgtt_init(struct drm_device dev, struct i915_hw_ppgtt ppgtt);
82460d97	462	int i915_ppgtt_init_hw(struct drm_device *dev);
ee960be7	463	void i915_ppgtt_release(struct kref *kref);
4d884705 DV	464	struct i915_hw_ppgtt i915_ppgtt_create(struct drm_device dev,
4d884705 DV	465	struct drm_i915_file_private *fpriv);
ee960be7 DV	466	static inline void i915_ppgtt_get(struct i915_hw_ppgtt *ppgtt)
	467	{
	468	if (ppgtt)
	469	kref_get(&ppgtt->ref);
	470	}
	471	static inline void i915_ppgtt_put(struct i915_hw_ppgtt *ppgtt)
	472	{
	473	if (ppgtt)
	474	kref_put(&ppgtt->ref, i915_ppgtt_release);
	475	}
0260c420 BW	476
	477	void i915_check_and_clear_faults(struct drm_device *dev);
	478	void i915_gem_suspend_gtt_mappings(struct drm_device *dev);
	479	void i915_gem_restore_gtt_mappings(struct drm_device *dev);
	480
	481	int __must_check i915_gem_gtt_prepare_object(struct drm_i915_gem_object *obj);
	482	void i915_gem_gtt_finish_object(struct drm_i915_gem_object *obj);
	483
9abc4648 JL	484	static inline bool
	485	i915_ggtt_view_equal(const struct i915_ggtt_view *a,
	486	const struct i915_ggtt_view *b)
	487	{
	488	if (WARN_ON(!a \|\| !b))
	489	return false;
	490
	491	return a->type == b->type;
	492	}
	493
0260c420	494	#endif