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bac427f8 AD |
1 | /* |
2 | * Copyright © 2014 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | */ | |
24 | #include <linux/firmware.h> | |
25 | #include <linux/circ_buf.h> | |
26 | #include "i915_drv.h" | |
27 | #include "intel_guc.h" | |
28 | ||
44a28b1d | 29 | /** |
feda33ef | 30 | * DOC: GuC-based command submission |
44a28b1d DG |
31 | * |
32 | * i915_guc_client: | |
33 | * We use the term client to avoid confusion with contexts. A i915_guc_client is | |
34 | * equivalent to GuC object guc_context_desc. This context descriptor is | |
35 | * allocated from a pool of 1024 entries. Kernel driver will allocate doorbell | |
36 | * and workqueue for it. Also the process descriptor (guc_process_desc), which | |
37 | * is mapped to client space. So the client can write Work Item then ring the | |
38 | * doorbell. | |
39 | * | |
40 | * To simplify the implementation, we allocate one gem object that contains all | |
41 | * pages for doorbell, process descriptor and workqueue. | |
42 | * | |
43 | * The Scratch registers: | |
44 | * There are 16 MMIO-based registers start from 0xC180. The kernel driver writes | |
45 | * a value to the action register (SOFT_SCRATCH_0) along with any data. It then | |
46 | * triggers an interrupt on the GuC via another register write (0xC4C8). | |
47 | * Firmware writes a success/fail code back to the action register after | |
48 | * processes the request. The kernel driver polls waiting for this update and | |
49 | * then proceeds. | |
50 | * See host2guc_action() | |
51 | * | |
52 | * Doorbells: | |
53 | * Doorbells are interrupts to uKernel. A doorbell is a single cache line (QW) | |
54 | * mapped into process space. | |
55 | * | |
56 | * Work Items: | |
57 | * There are several types of work items that the host may place into a | |
58 | * workqueue, each with its own requirements and limitations. Currently only | |
59 | * WQ_TYPE_INORDER is needed to support legacy submission via GuC, which | |
60 | * represents in-order queue. The kernel driver packs ring tail pointer and an | |
61 | * ELSP context descriptor dword into Work Item. | |
62 | * See guc_add_workqueue_item() | |
63 | * | |
64 | */ | |
65 | ||
66 | /* | |
67 | * Read GuC command/status register (SOFT_SCRATCH_0) | |
68 | * Return true if it contains a response rather than a command | |
69 | */ | |
70 | static inline bool host2guc_action_response(struct drm_i915_private *dev_priv, | |
71 | u32 *status) | |
72 | { | |
73 | u32 val = I915_READ(SOFT_SCRATCH(0)); | |
74 | *status = val; | |
75 | return GUC2HOST_IS_RESPONSE(val); | |
76 | } | |
77 | ||
78 | static int host2guc_action(struct intel_guc *guc, u32 *data, u32 len) | |
79 | { | |
80 | struct drm_i915_private *dev_priv = guc_to_i915(guc); | |
81 | u32 status; | |
82 | int i; | |
83 | int ret; | |
84 | ||
85 | if (WARN_ON(len < 1 || len > 15)) | |
86 | return -EINVAL; | |
87 | ||
88 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); | |
44a28b1d DG |
89 | |
90 | dev_priv->guc.action_count += 1; | |
91 | dev_priv->guc.action_cmd = data[0]; | |
92 | ||
93 | for (i = 0; i < len; i++) | |
94 | I915_WRITE(SOFT_SCRATCH(i), data[i]); | |
95 | ||
96 | POSTING_READ(SOFT_SCRATCH(i - 1)); | |
97 | ||
98 | I915_WRITE(HOST2GUC_INTERRUPT, HOST2GUC_TRIGGER); | |
99 | ||
100 | /* No HOST2GUC command should take longer than 10ms */ | |
101 | ret = wait_for_atomic(host2guc_action_response(dev_priv, &status), 10); | |
102 | if (status != GUC2HOST_STATUS_SUCCESS) { | |
103 | /* | |
104 | * Either the GuC explicitly returned an error (which | |
105 | * we convert to -EIO here) or no response at all was | |
106 | * received within the timeout limit (-ETIMEDOUT) | |
107 | */ | |
108 | if (ret != -ETIMEDOUT) | |
109 | ret = -EIO; | |
110 | ||
111 | DRM_ERROR("GUC: host2guc action 0x%X failed. ret=%d " | |
112 | "status=0x%08X response=0x%08X\n", | |
113 | data[0], ret, status, | |
114 | I915_READ(SOFT_SCRATCH(15))); | |
115 | ||
116 | dev_priv->guc.action_fail += 1; | |
117 | dev_priv->guc.action_err = ret; | |
118 | } | |
119 | dev_priv->guc.action_status = status; | |
120 | ||
44a28b1d DG |
121 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); |
122 | ||
123 | return ret; | |
124 | } | |
125 | ||
126 | /* | |
127 | * Tell the GuC to allocate or deallocate a specific doorbell | |
128 | */ | |
129 | ||
130 | static int host2guc_allocate_doorbell(struct intel_guc *guc, | |
131 | struct i915_guc_client *client) | |
132 | { | |
133 | u32 data[2]; | |
134 | ||
135 | data[0] = HOST2GUC_ACTION_ALLOCATE_DOORBELL; | |
136 | data[1] = client->ctx_index; | |
137 | ||
138 | return host2guc_action(guc, data, 2); | |
139 | } | |
140 | ||
141 | static int host2guc_release_doorbell(struct intel_guc *guc, | |
142 | struct i915_guc_client *client) | |
143 | { | |
144 | u32 data[2]; | |
145 | ||
146 | data[0] = HOST2GUC_ACTION_DEALLOCATE_DOORBELL; | |
147 | data[1] = client->ctx_index; | |
148 | ||
149 | return host2guc_action(guc, data, 2); | |
150 | } | |
151 | ||
f5d3c3ea AD |
152 | static int host2guc_sample_forcewake(struct intel_guc *guc, |
153 | struct i915_guc_client *client) | |
154 | { | |
155 | struct drm_i915_private *dev_priv = guc_to_i915(guc); | |
93f25318 | 156 | struct drm_device *dev = dev_priv->dev; |
f5d3c3ea AD |
157 | u32 data[2]; |
158 | ||
159 | data[0] = HOST2GUC_ACTION_SAMPLE_FORCEWAKE; | |
93f25318 | 160 | /* WaRsDisableCoarsePowerGating:skl,bxt */ |
06e668ac MK |
161 | if (!intel_enable_rc6(dev) || |
162 | NEEDS_WaRsDisableCoarsePowerGating(dev)) | |
93f25318 AD |
163 | data[1] = 0; |
164 | else | |
165 | /* bit 0 and 1 are for Render and Media domain separately */ | |
166 | data[1] = GUC_FORCEWAKE_RENDER | GUC_FORCEWAKE_MEDIA; | |
167 | ||
168 | return host2guc_action(guc, data, ARRAY_SIZE(data)); | |
f5d3c3ea AD |
169 | } |
170 | ||
44a28b1d DG |
171 | /* |
172 | * Initialise, update, or clear doorbell data shared with the GuC | |
173 | * | |
174 | * These functions modify shared data and so need access to the mapped | |
175 | * client object which contains the page being used for the doorbell | |
176 | */ | |
177 | ||
178 | static void guc_init_doorbell(struct intel_guc *guc, | |
179 | struct i915_guc_client *client) | |
180 | { | |
181 | struct guc_doorbell_info *doorbell; | |
182 | void *base; | |
183 | ||
184 | base = kmap_atomic(i915_gem_object_get_page(client->client_obj, 0)); | |
185 | doorbell = base + client->doorbell_offset; | |
186 | ||
187 | doorbell->db_status = 1; | |
188 | doorbell->cookie = 0; | |
189 | ||
190 | kunmap_atomic(base); | |
191 | } | |
192 | ||
193 | static int guc_ring_doorbell(struct i915_guc_client *gc) | |
194 | { | |
195 | struct guc_process_desc *desc; | |
196 | union guc_doorbell_qw db_cmp, db_exc, db_ret; | |
197 | union guc_doorbell_qw *db; | |
198 | void *base; | |
199 | int attempt = 2, ret = -EAGAIN; | |
200 | ||
201 | base = kmap_atomic(i915_gem_object_get_page(gc->client_obj, 0)); | |
202 | desc = base + gc->proc_desc_offset; | |
203 | ||
204 | /* Update the tail so it is visible to GuC */ | |
205 | desc->tail = gc->wq_tail; | |
206 | ||
207 | /* current cookie */ | |
208 | db_cmp.db_status = GUC_DOORBELL_ENABLED; | |
209 | db_cmp.cookie = gc->cookie; | |
210 | ||
211 | /* cookie to be updated */ | |
212 | db_exc.db_status = GUC_DOORBELL_ENABLED; | |
213 | db_exc.cookie = gc->cookie + 1; | |
214 | if (db_exc.cookie == 0) | |
215 | db_exc.cookie = 1; | |
216 | ||
217 | /* pointer of current doorbell cacheline */ | |
218 | db = base + gc->doorbell_offset; | |
219 | ||
220 | while (attempt--) { | |
221 | /* lets ring the doorbell */ | |
222 | db_ret.value_qw = atomic64_cmpxchg((atomic64_t *)db, | |
223 | db_cmp.value_qw, db_exc.value_qw); | |
224 | ||
225 | /* if the exchange was successfully executed */ | |
226 | if (db_ret.value_qw == db_cmp.value_qw) { | |
227 | /* db was successfully rung */ | |
228 | gc->cookie = db_exc.cookie; | |
229 | ret = 0; | |
230 | break; | |
231 | } | |
232 | ||
233 | /* XXX: doorbell was lost and need to acquire it again */ | |
234 | if (db_ret.db_status == GUC_DOORBELL_DISABLED) | |
235 | break; | |
236 | ||
237 | DRM_ERROR("Cookie mismatch. Expected %d, returned %d\n", | |
238 | db_cmp.cookie, db_ret.cookie); | |
239 | ||
240 | /* update the cookie to newly read cookie from GuC */ | |
241 | db_cmp.cookie = db_ret.cookie; | |
242 | db_exc.cookie = db_ret.cookie + 1; | |
243 | if (db_exc.cookie == 0) | |
244 | db_exc.cookie = 1; | |
245 | } | |
246 | ||
a7e02199 AD |
247 | /* Finally, update the cached copy of the GuC's WQ head */ |
248 | gc->wq_head = desc->head; | |
249 | ||
44a28b1d DG |
250 | kunmap_atomic(base); |
251 | return ret; | |
252 | } | |
253 | ||
254 | static void guc_disable_doorbell(struct intel_guc *guc, | |
255 | struct i915_guc_client *client) | |
256 | { | |
257 | struct drm_i915_private *dev_priv = guc_to_i915(guc); | |
258 | struct guc_doorbell_info *doorbell; | |
259 | void *base; | |
f0f59a00 | 260 | i915_reg_t drbreg = GEN8_DRBREGL(client->doorbell_id); |
44a28b1d DG |
261 | int value; |
262 | ||
263 | base = kmap_atomic(i915_gem_object_get_page(client->client_obj, 0)); | |
264 | doorbell = base + client->doorbell_offset; | |
265 | ||
266 | doorbell->db_status = 0; | |
267 | ||
268 | kunmap_atomic(base); | |
269 | ||
270 | I915_WRITE(drbreg, I915_READ(drbreg) & ~GEN8_DRB_VALID); | |
271 | ||
272 | value = I915_READ(drbreg); | |
273 | WARN_ON((value & GEN8_DRB_VALID) != 0); | |
274 | ||
275 | I915_WRITE(GEN8_DRBREGU(client->doorbell_id), 0); | |
276 | I915_WRITE(drbreg, 0); | |
277 | ||
278 | /* XXX: wait for any interrupts */ | |
279 | /* XXX: wait for workqueue to drain */ | |
280 | } | |
281 | ||
282 | /* | |
283 | * Select, assign and relase doorbell cachelines | |
284 | * | |
285 | * These functions track which doorbell cachelines are in use. | |
286 | * The data they manipulate is protected by the host2guc lock. | |
287 | */ | |
288 | ||
289 | static uint32_t select_doorbell_cacheline(struct intel_guc *guc) | |
290 | { | |
291 | const uint32_t cacheline_size = cache_line_size(); | |
292 | uint32_t offset; | |
293 | ||
44a28b1d DG |
294 | /* Doorbell uses a single cache line within a page */ |
295 | offset = offset_in_page(guc->db_cacheline); | |
296 | ||
297 | /* Moving to next cache line to reduce contention */ | |
298 | guc->db_cacheline += cacheline_size; | |
299 | ||
44a28b1d DG |
300 | DRM_DEBUG_DRIVER("selected doorbell cacheline 0x%x, next 0x%x, linesize %u\n", |
301 | offset, guc->db_cacheline, cacheline_size); | |
302 | ||
303 | return offset; | |
304 | } | |
305 | ||
306 | static uint16_t assign_doorbell(struct intel_guc *guc, uint32_t priority) | |
307 | { | |
308 | /* | |
309 | * The bitmap is split into two halves; the first half is used for | |
310 | * normal priority contexts, the second half for high-priority ones. | |
311 | * Note that logically higher priorities are numerically less than | |
312 | * normal ones, so the test below means "is it high-priority?" | |
313 | */ | |
314 | const bool hi_pri = (priority <= GUC_CTX_PRIORITY_HIGH); | |
315 | const uint16_t half = GUC_MAX_DOORBELLS / 2; | |
316 | const uint16_t start = hi_pri ? half : 0; | |
317 | const uint16_t end = start + half; | |
318 | uint16_t id; | |
319 | ||
44a28b1d DG |
320 | id = find_next_zero_bit(guc->doorbell_bitmap, end, start); |
321 | if (id == end) | |
322 | id = GUC_INVALID_DOORBELL_ID; | |
323 | else | |
324 | bitmap_set(guc->doorbell_bitmap, id, 1); | |
44a28b1d DG |
325 | |
326 | DRM_DEBUG_DRIVER("assigned %s priority doorbell id 0x%x\n", | |
327 | hi_pri ? "high" : "normal", id); | |
328 | ||
329 | return id; | |
330 | } | |
331 | ||
332 | static void release_doorbell(struct intel_guc *guc, uint16_t id) | |
333 | { | |
44a28b1d | 334 | bitmap_clear(guc->doorbell_bitmap, id, 1); |
44a28b1d DG |
335 | } |
336 | ||
337 | /* | |
338 | * Initialise the process descriptor shared with the GuC firmware. | |
339 | */ | |
340 | static void guc_init_proc_desc(struct intel_guc *guc, | |
341 | struct i915_guc_client *client) | |
342 | { | |
343 | struct guc_process_desc *desc; | |
344 | void *base; | |
345 | ||
346 | base = kmap_atomic(i915_gem_object_get_page(client->client_obj, 0)); | |
347 | desc = base + client->proc_desc_offset; | |
348 | ||
349 | memset(desc, 0, sizeof(*desc)); | |
350 | ||
351 | /* | |
352 | * XXX: pDoorbell and WQVBaseAddress are pointers in process address | |
353 | * space for ring3 clients (set them as in mmap_ioctl) or kernel | |
354 | * space for kernel clients (map on demand instead? May make debug | |
355 | * easier to have it mapped). | |
356 | */ | |
357 | desc->wq_base_addr = 0; | |
358 | desc->db_base_addr = 0; | |
359 | ||
360 | desc->context_id = client->ctx_index; | |
361 | desc->wq_size_bytes = client->wq_size; | |
362 | desc->wq_status = WQ_STATUS_ACTIVE; | |
363 | desc->priority = client->priority; | |
364 | ||
365 | kunmap_atomic(base); | |
366 | } | |
367 | ||
368 | /* | |
369 | * Initialise/clear the context descriptor shared with the GuC firmware. | |
370 | * | |
371 | * This descriptor tells the GuC where (in GGTT space) to find the important | |
372 | * data structures relating to this client (doorbell, process descriptor, | |
373 | * write queue, etc). | |
374 | */ | |
375 | ||
376 | static void guc_init_ctx_desc(struct intel_guc *guc, | |
377 | struct i915_guc_client *client) | |
378 | { | |
397097b0 | 379 | struct drm_i915_private *dev_priv = guc_to_i915(guc); |
e2f80391 | 380 | struct intel_engine_cs *engine; |
d1675198 | 381 | struct intel_context *ctx = client->owner; |
44a28b1d DG |
382 | struct guc_context_desc desc; |
383 | struct sg_table *sg; | |
d1675198 | 384 | int i; |
44a28b1d DG |
385 | |
386 | memset(&desc, 0, sizeof(desc)); | |
387 | ||
388 | desc.attribute = GUC_CTX_DESC_ATTR_ACTIVE | GUC_CTX_DESC_ATTR_KERNEL; | |
389 | desc.context_id = client->ctx_index; | |
390 | desc.priority = client->priority; | |
44a28b1d DG |
391 | desc.db_id = client->doorbell_id; |
392 | ||
666796da | 393 | for_each_engine(engine, dev_priv, i) { |
e2f80391 | 394 | struct guc_execlist_context *lrc = &desc.lrc[engine->guc_id]; |
d1675198 AD |
395 | struct drm_i915_gem_object *obj; |
396 | uint64_t ctx_desc; | |
397 | ||
398 | /* TODO: We have a design issue to be solved here. Only when we | |
399 | * receive the first batch, we know which engine is used by the | |
400 | * user. But here GuC expects the lrc and ring to be pinned. It | |
401 | * is not an issue for default context, which is the only one | |
402 | * for now who owns a GuC client. But for future owner of GuC | |
403 | * client, need to make sure lrc is pinned prior to enter here. | |
404 | */ | |
405 | obj = ctx->engine[i].state; | |
406 | if (!obj) | |
407 | break; /* XXX: continue? */ | |
408 | ||
e2f80391 | 409 | ctx_desc = intel_lr_context_descriptor(ctx, engine); |
d1675198 AD |
410 | lrc->context_desc = (u32)ctx_desc; |
411 | ||
412 | /* The state page is after PPHWSP */ | |
413 | lrc->ring_lcra = i915_gem_obj_ggtt_offset(obj) + | |
414 | LRC_STATE_PN * PAGE_SIZE; | |
415 | lrc->context_id = (client->ctx_index << GUC_ELC_CTXID_OFFSET) | | |
e2f80391 | 416 | (engine->guc_id << GUC_ELC_ENGINE_OFFSET); |
d1675198 | 417 | |
397097b0 | 418 | obj = ctx->engine[i].ringbuf->obj; |
d1675198 AD |
419 | |
420 | lrc->ring_begin = i915_gem_obj_ggtt_offset(obj); | |
421 | lrc->ring_end = lrc->ring_begin + obj->base.size - 1; | |
422 | lrc->ring_next_free_location = lrc->ring_begin; | |
423 | lrc->ring_current_tail_pointer_value = 0; | |
424 | ||
e2f80391 | 425 | desc.engines_used |= (1 << engine->guc_id); |
d1675198 AD |
426 | } |
427 | ||
428 | WARN_ON(desc.engines_used == 0); | |
429 | ||
44a28b1d DG |
430 | /* |
431 | * The CPU address is only needed at certain points, so kmap_atomic on | |
432 | * demand instead of storing it in the ctx descriptor. | |
433 | * XXX: May make debug easier to have it mapped | |
434 | */ | |
435 | desc.db_trigger_cpu = 0; | |
436 | desc.db_trigger_uk = client->doorbell_offset + | |
437 | i915_gem_obj_ggtt_offset(client->client_obj); | |
438 | desc.db_trigger_phy = client->doorbell_offset + | |
439 | sg_dma_address(client->client_obj->pages->sgl); | |
440 | ||
441 | desc.process_desc = client->proc_desc_offset + | |
442 | i915_gem_obj_ggtt_offset(client->client_obj); | |
443 | ||
444 | desc.wq_addr = client->wq_offset + | |
445 | i915_gem_obj_ggtt_offset(client->client_obj); | |
446 | ||
447 | desc.wq_size = client->wq_size; | |
448 | ||
449 | /* | |
450 | * XXX: Take LRCs from an existing intel_context if this is not an | |
451 | * IsKMDCreatedContext client | |
452 | */ | |
453 | desc.desc_private = (uintptr_t)client; | |
454 | ||
455 | /* Pool context is pinned already */ | |
456 | sg = guc->ctx_pool_obj->pages; | |
457 | sg_pcopy_from_buffer(sg->sgl, sg->nents, &desc, sizeof(desc), | |
458 | sizeof(desc) * client->ctx_index); | |
459 | } | |
460 | ||
461 | static void guc_fini_ctx_desc(struct intel_guc *guc, | |
462 | struct i915_guc_client *client) | |
463 | { | |
464 | struct guc_context_desc desc; | |
465 | struct sg_table *sg; | |
466 | ||
467 | memset(&desc, 0, sizeof(desc)); | |
468 | ||
469 | sg = guc->ctx_pool_obj->pages; | |
470 | sg_pcopy_from_buffer(sg->sgl, sg->nents, &desc, sizeof(desc), | |
471 | sizeof(desc) * client->ctx_index); | |
472 | } | |
473 | ||
a7e02199 | 474 | int i915_guc_wq_check_space(struct i915_guc_client *gc) |
44a28b1d DG |
475 | { |
476 | struct guc_process_desc *desc; | |
477 | void *base; | |
478 | u32 size = sizeof(struct guc_wq_item); | |
5a843307 | 479 | int ret = -ETIMEDOUT, timeout_counter = 200; |
44a28b1d | 480 | |
a7e02199 AD |
481 | if (!gc) |
482 | return 0; | |
483 | ||
484 | /* Quickly return if wq space is available since last time we cache the | |
485 | * head position. */ | |
486 | if (CIRC_SPACE(gc->wq_tail, gc->wq_head, gc->wq_size) >= size) | |
487 | return 0; | |
488 | ||
44a28b1d DG |
489 | base = kmap_atomic(i915_gem_object_get_page(gc->client_obj, 0)); |
490 | desc = base + gc->proc_desc_offset; | |
491 | ||
492 | while (timeout_counter-- > 0) { | |
a7e02199 | 493 | gc->wq_head = desc->head; |
44a28b1d | 494 | |
a7e02199 | 495 | if (CIRC_SPACE(gc->wq_tail, gc->wq_head, gc->wq_size) >= size) { |
5a843307 | 496 | ret = 0; |
a7e02199 | 497 | break; |
44a28b1d | 498 | } |
5a843307 AD |
499 | |
500 | if (timeout_counter) | |
501 | usleep_range(1000, 2000); | |
44a28b1d DG |
502 | }; |
503 | ||
504 | kunmap_atomic(base); | |
505 | ||
506 | return ret; | |
507 | } | |
508 | ||
509 | static int guc_add_workqueue_item(struct i915_guc_client *gc, | |
510 | struct drm_i915_gem_request *rq) | |
511 | { | |
44a28b1d DG |
512 | struct guc_wq_item *wqi; |
513 | void *base; | |
a7e02199 AD |
514 | u32 tail, wq_len, wq_off, space; |
515 | ||
516 | space = CIRC_SPACE(gc->wq_tail, gc->wq_head, gc->wq_size); | |
517 | if (WARN_ON(space < sizeof(struct guc_wq_item))) | |
518 | return -ENOSPC; /* shouldn't happen */ | |
44a28b1d | 519 | |
a7e02199 AD |
520 | /* postincrement WQ tail for next time */ |
521 | wq_off = gc->wq_tail; | |
522 | gc->wq_tail += sizeof(struct guc_wq_item); | |
523 | gc->wq_tail &= gc->wq_size - 1; | |
44a28b1d DG |
524 | |
525 | /* For now workqueue item is 4 DWs; workqueue buffer is 2 pages. So we | |
526 | * should not have the case where structure wqi is across page, neither | |
527 | * wrapped to the beginning. This simplifies the implementation below. | |
528 | * | |
529 | * XXX: if not the case, we need save data to a temp wqi and copy it to | |
530 | * workqueue buffer dw by dw. | |
531 | */ | |
532 | WARN_ON(sizeof(struct guc_wq_item) != 16); | |
533 | WARN_ON(wq_off & 3); | |
534 | ||
535 | /* wq starts from the page after doorbell / process_desc */ | |
536 | base = kmap_atomic(i915_gem_object_get_page(gc->client_obj, | |
537 | (wq_off + GUC_DB_SIZE) >> PAGE_SHIFT)); | |
538 | wq_off &= PAGE_SIZE - 1; | |
539 | wqi = (struct guc_wq_item *)((char *)base + wq_off); | |
540 | ||
541 | /* len does not include the header */ | |
542 | wq_len = sizeof(struct guc_wq_item) / sizeof(u32) - 1; | |
543 | wqi->header = WQ_TYPE_INORDER | | |
544 | (wq_len << WQ_LEN_SHIFT) | | |
4a570db5 | 545 | (rq->engine->guc_id << WQ_TARGET_SHIFT) | |
44a28b1d DG |
546 | WQ_NO_WCFLUSH_WAIT; |
547 | ||
548 | /* The GuC wants only the low-order word of the context descriptor */ | |
4a570db5 TU |
549 | wqi->context_desc = (u32)intel_lr_context_descriptor(rq->ctx, |
550 | rq->engine); | |
44a28b1d DG |
551 | |
552 | /* The GuC firmware wants the tail index in QWords, not bytes */ | |
553 | tail = rq->ringbuf->tail >> 3; | |
554 | wqi->ring_tail = tail << WQ_RING_TAIL_SHIFT; | |
555 | wqi->fence_id = 0; /*XXX: what fence to be here */ | |
556 | ||
557 | kunmap_atomic(base); | |
558 | ||
559 | return 0; | |
560 | } | |
561 | ||
562 | /** | |
563 | * i915_guc_submit() - Submit commands through GuC | |
564 | * @client: the guc client where commands will go through | |
feda33ef | 565 | * @rq: request associated with the commands |
44a28b1d DG |
566 | * |
567 | * Return: 0 if succeed | |
568 | */ | |
569 | int i915_guc_submit(struct i915_guc_client *client, | |
570 | struct drm_i915_gem_request *rq) | |
571 | { | |
572 | struct intel_guc *guc = client->guc; | |
4a570db5 | 573 | unsigned int engine_id = rq->engine->guc_id; |
44a28b1d DG |
574 | int q_ret, b_ret; |
575 | ||
44a28b1d DG |
576 | q_ret = guc_add_workqueue_item(client, rq); |
577 | if (q_ret == 0) | |
578 | b_ret = guc_ring_doorbell(client); | |
579 | ||
397097b0 | 580 | client->submissions[engine_id] += 1; |
44a28b1d DG |
581 | if (q_ret) { |
582 | client->q_fail += 1; | |
583 | client->retcode = q_ret; | |
584 | } else if (b_ret) { | |
585 | client->b_fail += 1; | |
586 | client->retcode = q_ret = b_ret; | |
587 | } else { | |
588 | client->retcode = 0; | |
589 | } | |
397097b0 AD |
590 | guc->submissions[engine_id] += 1; |
591 | guc->last_seqno[engine_id] = rq->seqno; | |
44a28b1d DG |
592 | |
593 | return q_ret; | |
594 | } | |
595 | ||
596 | /* | |
597 | * Everything below here is concerned with setup & teardown, and is | |
598 | * therefore not part of the somewhat time-critical batch-submission | |
599 | * path of i915_guc_submit() above. | |
600 | */ | |
601 | ||
bac427f8 AD |
602 | /** |
603 | * gem_allocate_guc_obj() - Allocate gem object for GuC usage | |
604 | * @dev: drm device | |
605 | * @size: size of object | |
606 | * | |
607 | * This is a wrapper to create a gem obj. In order to use it inside GuC, the | |
608 | * object needs to be pinned lifetime. Also we must pin it to gtt space other | |
609 | * than [0, GUC_WOPCM_TOP) because this range is reserved inside GuC. | |
610 | * | |
611 | * Return: A drm_i915_gem_object if successful, otherwise NULL. | |
612 | */ | |
613 | static struct drm_i915_gem_object *gem_allocate_guc_obj(struct drm_device *dev, | |
614 | u32 size) | |
615 | { | |
616 | struct drm_i915_private *dev_priv = dev->dev_private; | |
617 | struct drm_i915_gem_object *obj; | |
618 | ||
619 | obj = i915_gem_alloc_object(dev, size); | |
620 | if (!obj) | |
621 | return NULL; | |
622 | ||
623 | if (i915_gem_object_get_pages(obj)) { | |
624 | drm_gem_object_unreference(&obj->base); | |
625 | return NULL; | |
626 | } | |
627 | ||
628 | if (i915_gem_obj_ggtt_pin(obj, PAGE_SIZE, | |
629 | PIN_OFFSET_BIAS | GUC_WOPCM_TOP)) { | |
630 | drm_gem_object_unreference(&obj->base); | |
631 | return NULL; | |
632 | } | |
633 | ||
634 | /* Invalidate GuC TLB to let GuC take the latest updates to GTT. */ | |
635 | I915_WRITE(GEN8_GTCR, GEN8_GTCR_INVALIDATE); | |
636 | ||
637 | return obj; | |
638 | } | |
639 | ||
640 | /** | |
641 | * gem_release_guc_obj() - Release gem object allocated for GuC usage | |
642 | * @obj: gem obj to be released | |
81fd874e | 643 | */ |
bac427f8 AD |
644 | static void gem_release_guc_obj(struct drm_i915_gem_object *obj) |
645 | { | |
646 | if (!obj) | |
647 | return; | |
648 | ||
649 | if (i915_gem_obj_is_pinned(obj)) | |
650 | i915_gem_object_ggtt_unpin(obj); | |
651 | ||
652 | drm_gem_object_unreference(&obj->base); | |
653 | } | |
654 | ||
44a28b1d DG |
655 | static void guc_client_free(struct drm_device *dev, |
656 | struct i915_guc_client *client) | |
657 | { | |
658 | struct drm_i915_private *dev_priv = dev->dev_private; | |
659 | struct intel_guc *guc = &dev_priv->guc; | |
660 | ||
661 | if (!client) | |
662 | return; | |
663 | ||
664 | if (client->doorbell_id != GUC_INVALID_DOORBELL_ID) { | |
665 | /* | |
666 | * First disable the doorbell, then tell the GuC we've | |
667 | * finished with it, finally deallocate it in our bitmap | |
668 | */ | |
669 | guc_disable_doorbell(guc, client); | |
670 | host2guc_release_doorbell(guc, client); | |
671 | release_doorbell(guc, client->doorbell_id); | |
672 | } | |
673 | ||
674 | /* | |
675 | * XXX: wait for any outstanding submissions before freeing memory. | |
676 | * Be sure to drop any locks | |
677 | */ | |
678 | ||
679 | gem_release_guc_obj(client->client_obj); | |
680 | ||
681 | if (client->ctx_index != GUC_INVALID_CTX_ID) { | |
682 | guc_fini_ctx_desc(guc, client); | |
683 | ida_simple_remove(&guc->ctx_ids, client->ctx_index); | |
684 | } | |
685 | ||
686 | kfree(client); | |
687 | } | |
688 | ||
689 | /** | |
690 | * guc_client_alloc() - Allocate an i915_guc_client | |
691 | * @dev: drm device | |
692 | * @priority: four levels priority _CRITICAL, _HIGH, _NORMAL and _LOW | |
693 | * The kernel client to replace ExecList submission is created with | |
694 | * NORMAL priority. Priority of a client for scheduler can be HIGH, | |
695 | * while a preemption context can use CRITICAL. | |
feda33ef AD |
696 | * @ctx: the context that owns the client (we use the default render |
697 | * context) | |
44a28b1d DG |
698 | * |
699 | * Return: An i915_guc_client object if success. | |
700 | */ | |
701 | static struct i915_guc_client *guc_client_alloc(struct drm_device *dev, | |
d1675198 AD |
702 | uint32_t priority, |
703 | struct intel_context *ctx) | |
44a28b1d DG |
704 | { |
705 | struct i915_guc_client *client; | |
706 | struct drm_i915_private *dev_priv = dev->dev_private; | |
707 | struct intel_guc *guc = &dev_priv->guc; | |
708 | struct drm_i915_gem_object *obj; | |
709 | ||
710 | client = kzalloc(sizeof(*client), GFP_KERNEL); | |
711 | if (!client) | |
712 | return NULL; | |
713 | ||
714 | client->doorbell_id = GUC_INVALID_DOORBELL_ID; | |
715 | client->priority = priority; | |
d1675198 | 716 | client->owner = ctx; |
44a28b1d DG |
717 | client->guc = guc; |
718 | ||
719 | client->ctx_index = (uint32_t)ida_simple_get(&guc->ctx_ids, 0, | |
720 | GUC_MAX_GPU_CONTEXTS, GFP_KERNEL); | |
721 | if (client->ctx_index >= GUC_MAX_GPU_CONTEXTS) { | |
722 | client->ctx_index = GUC_INVALID_CTX_ID; | |
723 | goto err; | |
724 | } | |
725 | ||
726 | /* The first page is doorbell/proc_desc. Two followed pages are wq. */ | |
727 | obj = gem_allocate_guc_obj(dev, GUC_DB_SIZE + GUC_WQ_SIZE); | |
728 | if (!obj) | |
729 | goto err; | |
730 | ||
731 | client->client_obj = obj; | |
732 | client->wq_offset = GUC_DB_SIZE; | |
733 | client->wq_size = GUC_WQ_SIZE; | |
44a28b1d DG |
734 | |
735 | client->doorbell_offset = select_doorbell_cacheline(guc); | |
736 | ||
737 | /* | |
738 | * Since the doorbell only requires a single cacheline, we can save | |
739 | * space by putting the application process descriptor in the same | |
740 | * page. Use the half of the page that doesn't include the doorbell. | |
741 | */ | |
742 | if (client->doorbell_offset >= (GUC_DB_SIZE / 2)) | |
743 | client->proc_desc_offset = 0; | |
744 | else | |
745 | client->proc_desc_offset = (GUC_DB_SIZE / 2); | |
746 | ||
747 | client->doorbell_id = assign_doorbell(guc, client->priority); | |
748 | if (client->doorbell_id == GUC_INVALID_DOORBELL_ID) | |
749 | /* XXX: evict a doorbell instead */ | |
750 | goto err; | |
751 | ||
752 | guc_init_proc_desc(guc, client); | |
753 | guc_init_ctx_desc(guc, client); | |
754 | guc_init_doorbell(guc, client); | |
755 | ||
756 | /* XXX: Any cache flushes needed? General domain mgmt calls? */ | |
757 | ||
758 | if (host2guc_allocate_doorbell(guc, client)) | |
759 | goto err; | |
760 | ||
761 | DRM_DEBUG_DRIVER("new priority %u client %p: ctx_index %u db_id %u\n", | |
762 | priority, client, client->ctx_index, client->doorbell_id); | |
763 | ||
764 | return client; | |
765 | ||
766 | err: | |
767 | DRM_ERROR("FAILED to create priority %u GuC client!\n", priority); | |
768 | ||
769 | guc_client_free(dev, client); | |
770 | return NULL; | |
771 | } | |
772 | ||
4c7e77fc AD |
773 | static void guc_create_log(struct intel_guc *guc) |
774 | { | |
775 | struct drm_i915_private *dev_priv = guc_to_i915(guc); | |
776 | struct drm_i915_gem_object *obj; | |
777 | unsigned long offset; | |
778 | uint32_t size, flags; | |
779 | ||
780 | if (i915.guc_log_level < GUC_LOG_VERBOSITY_MIN) | |
781 | return; | |
782 | ||
783 | if (i915.guc_log_level > GUC_LOG_VERBOSITY_MAX) | |
784 | i915.guc_log_level = GUC_LOG_VERBOSITY_MAX; | |
785 | ||
786 | /* The first page is to save log buffer state. Allocate one | |
787 | * extra page for others in case for overlap */ | |
788 | size = (1 + GUC_LOG_DPC_PAGES + 1 + | |
789 | GUC_LOG_ISR_PAGES + 1 + | |
790 | GUC_LOG_CRASH_PAGES + 1) << PAGE_SHIFT; | |
791 | ||
792 | obj = guc->log_obj; | |
793 | if (!obj) { | |
794 | obj = gem_allocate_guc_obj(dev_priv->dev, size); | |
795 | if (!obj) { | |
796 | /* logging will be off */ | |
797 | i915.guc_log_level = -1; | |
798 | return; | |
799 | } | |
800 | ||
801 | guc->log_obj = obj; | |
802 | } | |
803 | ||
804 | /* each allocated unit is a page */ | |
805 | flags = GUC_LOG_VALID | GUC_LOG_NOTIFY_ON_HALF_FULL | | |
806 | (GUC_LOG_DPC_PAGES << GUC_LOG_DPC_SHIFT) | | |
807 | (GUC_LOG_ISR_PAGES << GUC_LOG_ISR_SHIFT) | | |
808 | (GUC_LOG_CRASH_PAGES << GUC_LOG_CRASH_SHIFT); | |
809 | ||
810 | offset = i915_gem_obj_ggtt_offset(obj) >> PAGE_SHIFT; /* in pages */ | |
811 | guc->log_flags = (offset << GUC_LOG_BUF_ADDR_SHIFT) | flags; | |
812 | } | |
813 | ||
463704d0 AD |
814 | static void init_guc_policies(struct guc_policies *policies) |
815 | { | |
816 | struct guc_policy *policy; | |
817 | u32 p, i; | |
818 | ||
819 | policies->dpc_promote_time = 500000; | |
820 | policies->max_num_work_items = POLICY_MAX_NUM_WI; | |
821 | ||
822 | for (p = 0; p < GUC_CTX_PRIORITY_NUM; p++) { | |
397097b0 | 823 | for (i = GUC_RENDER_ENGINE; i < GUC_MAX_ENGINES_NUM; i++) { |
463704d0 AD |
824 | policy = &policies->policy[p][i]; |
825 | ||
826 | policy->execution_quantum = 1000000; | |
827 | policy->preemption_time = 500000; | |
828 | policy->fault_time = 250000; | |
829 | policy->policy_flags = 0; | |
830 | } | |
831 | } | |
832 | ||
833 | policies->is_valid = 1; | |
834 | } | |
835 | ||
68371a95 AD |
836 | static void guc_create_ads(struct intel_guc *guc) |
837 | { | |
838 | struct drm_i915_private *dev_priv = guc_to_i915(guc); | |
839 | struct drm_i915_gem_object *obj; | |
840 | struct guc_ads *ads; | |
463704d0 | 841 | struct guc_policies *policies; |
5c148e04 | 842 | struct guc_mmio_reg_state *reg_state; |
e2f80391 | 843 | struct intel_engine_cs *engine; |
68371a95 AD |
844 | struct page *page; |
845 | u32 size, i; | |
846 | ||
847 | /* The ads obj includes the struct itself and buffers passed to GuC */ | |
5c148e04 AD |
848 | size = sizeof(struct guc_ads) + sizeof(struct guc_policies) + |
849 | sizeof(struct guc_mmio_reg_state) + | |
850 | GUC_S3_SAVE_SPACE_PAGES * PAGE_SIZE; | |
68371a95 AD |
851 | |
852 | obj = guc->ads_obj; | |
853 | if (!obj) { | |
854 | obj = gem_allocate_guc_obj(dev_priv->dev, PAGE_ALIGN(size)); | |
855 | if (!obj) | |
856 | return; | |
857 | ||
858 | guc->ads_obj = obj; | |
859 | } | |
860 | ||
861 | page = i915_gem_object_get_page(obj, 0); | |
862 | ads = kmap(page); | |
863 | ||
864 | /* | |
865 | * The GuC requires a "Golden Context" when it reinitialises | |
866 | * engines after a reset. Here we use the Render ring default | |
867 | * context, which must already exist and be pinned in the GGTT, | |
868 | * so its address won't change after we've told the GuC where | |
869 | * to find it. | |
870 | */ | |
4a570db5 | 871 | engine = &dev_priv->engine[RCS]; |
e2f80391 | 872 | ads->golden_context_lrca = engine->status_page.gfx_addr; |
68371a95 | 873 | |
666796da | 874 | for_each_engine(engine, dev_priv, i) |
e2f80391 | 875 | ads->eng_state_size[engine->guc_id] = intel_lr_context_size(engine); |
68371a95 | 876 | |
463704d0 AD |
877 | /* GuC scheduling policies */ |
878 | policies = (void *)ads + sizeof(struct guc_ads); | |
879 | init_guc_policies(policies); | |
880 | ||
881 | ads->scheduler_policies = i915_gem_obj_ggtt_offset(obj) + | |
882 | sizeof(struct guc_ads); | |
883 | ||
5c148e04 AD |
884 | /* MMIO reg state */ |
885 | reg_state = (void *)policies + sizeof(struct guc_policies); | |
886 | ||
666796da | 887 | for_each_engine(engine, dev_priv, i) { |
e2f80391 TU |
888 | reg_state->mmio_white_list[engine->guc_id].mmio_start = |
889 | engine->mmio_base + GUC_MMIO_WHITE_LIST_START; | |
5c148e04 AD |
890 | |
891 | /* Nothing to be saved or restored for now. */ | |
e2f80391 | 892 | reg_state->mmio_white_list[engine->guc_id].count = 0; |
5c148e04 AD |
893 | } |
894 | ||
895 | ads->reg_state_addr = ads->scheduler_policies + | |
896 | sizeof(struct guc_policies); | |
897 | ||
898 | ads->reg_state_buffer = ads->reg_state_addr + | |
899 | sizeof(struct guc_mmio_reg_state); | |
900 | ||
68371a95 AD |
901 | kunmap(page); |
902 | } | |
903 | ||
bac427f8 AD |
904 | /* |
905 | * Set up the memory resources to be shared with the GuC. At this point, | |
906 | * we require just one object that can be mapped through the GGTT. | |
907 | */ | |
908 | int i915_guc_submission_init(struct drm_device *dev) | |
909 | { | |
910 | struct drm_i915_private *dev_priv = dev->dev_private; | |
911 | const size_t ctxsize = sizeof(struct guc_context_desc); | |
912 | const size_t poolsize = GUC_MAX_GPU_CONTEXTS * ctxsize; | |
913 | const size_t gemsize = round_up(poolsize, PAGE_SIZE); | |
914 | struct intel_guc *guc = &dev_priv->guc; | |
915 | ||
916 | if (!i915.enable_guc_submission) | |
917 | return 0; /* not enabled */ | |
918 | ||
919 | if (guc->ctx_pool_obj) | |
920 | return 0; /* already allocated */ | |
921 | ||
922 | guc->ctx_pool_obj = gem_allocate_guc_obj(dev_priv->dev, gemsize); | |
923 | if (!guc->ctx_pool_obj) | |
924 | return -ENOMEM; | |
925 | ||
926 | ida_init(&guc->ctx_ids); | |
927 | ||
4c7e77fc AD |
928 | guc_create_log(guc); |
929 | ||
68371a95 AD |
930 | guc_create_ads(guc); |
931 | ||
bac427f8 AD |
932 | return 0; |
933 | } | |
934 | ||
44a28b1d DG |
935 | int i915_guc_submission_enable(struct drm_device *dev) |
936 | { | |
937 | struct drm_i915_private *dev_priv = dev->dev_private; | |
938 | struct intel_guc *guc = &dev_priv->guc; | |
ed54c1a1 | 939 | struct intel_context *ctx = dev_priv->kernel_context; |
44a28b1d DG |
940 | struct i915_guc_client *client; |
941 | ||
942 | /* client for execbuf submission */ | |
d1675198 | 943 | client = guc_client_alloc(dev, GUC_CTX_PRIORITY_KMD_NORMAL, ctx); |
44a28b1d DG |
944 | if (!client) { |
945 | DRM_ERROR("Failed to create execbuf guc_client\n"); | |
946 | return -ENOMEM; | |
947 | } | |
948 | ||
949 | guc->execbuf_client = client; | |
f5d3c3ea AD |
950 | |
951 | host2guc_sample_forcewake(guc, client); | |
952 | ||
44a28b1d DG |
953 | return 0; |
954 | } | |
955 | ||
956 | void i915_guc_submission_disable(struct drm_device *dev) | |
957 | { | |
958 | struct drm_i915_private *dev_priv = dev->dev_private; | |
959 | struct intel_guc *guc = &dev_priv->guc; | |
960 | ||
961 | guc_client_free(dev, guc->execbuf_client); | |
962 | guc->execbuf_client = NULL; | |
963 | } | |
964 | ||
bac427f8 AD |
965 | void i915_guc_submission_fini(struct drm_device *dev) |
966 | { | |
967 | struct drm_i915_private *dev_priv = dev->dev_private; | |
968 | struct intel_guc *guc = &dev_priv->guc; | |
969 | ||
68371a95 AD |
970 | gem_release_guc_obj(dev_priv->guc.ads_obj); |
971 | guc->ads_obj = NULL; | |
972 | ||
4c7e77fc AD |
973 | gem_release_guc_obj(dev_priv->guc.log_obj); |
974 | guc->log_obj = NULL; | |
975 | ||
bac427f8 AD |
976 | if (guc->ctx_pool_obj) |
977 | ida_destroy(&guc->ctx_ids); | |
978 | gem_release_guc_obj(guc->ctx_pool_obj); | |
979 | guc->ctx_pool_obj = NULL; | |
980 | } | |
a1c41994 AD |
981 | |
982 | /** | |
983 | * intel_guc_suspend() - notify GuC entering suspend state | |
984 | * @dev: drm device | |
985 | */ | |
986 | int intel_guc_suspend(struct drm_device *dev) | |
987 | { | |
988 | struct drm_i915_private *dev_priv = dev->dev_private; | |
989 | struct intel_guc *guc = &dev_priv->guc; | |
990 | struct intel_context *ctx; | |
991 | u32 data[3]; | |
992 | ||
993 | if (!i915.enable_guc_submission) | |
994 | return 0; | |
995 | ||
ed54c1a1 | 996 | ctx = dev_priv->kernel_context; |
a1c41994 AD |
997 | |
998 | data[0] = HOST2GUC_ACTION_ENTER_S_STATE; | |
999 | /* any value greater than GUC_POWER_D0 */ | |
1000 | data[1] = GUC_POWER_D1; | |
1001 | /* first page is shared data with GuC */ | |
1002 | data[2] = i915_gem_obj_ggtt_offset(ctx->engine[RCS].state); | |
1003 | ||
1004 | return host2guc_action(guc, data, ARRAY_SIZE(data)); | |
1005 | } | |
1006 | ||
1007 | ||
1008 | /** | |
1009 | * intel_guc_resume() - notify GuC resuming from suspend state | |
1010 | * @dev: drm device | |
1011 | */ | |
1012 | int intel_guc_resume(struct drm_device *dev) | |
1013 | { | |
1014 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1015 | struct intel_guc *guc = &dev_priv->guc; | |
1016 | struct intel_context *ctx; | |
1017 | u32 data[3]; | |
1018 | ||
1019 | if (!i915.enable_guc_submission) | |
1020 | return 0; | |
1021 | ||
ed54c1a1 | 1022 | ctx = dev_priv->kernel_context; |
a1c41994 AD |
1023 | |
1024 | data[0] = HOST2GUC_ACTION_EXIT_S_STATE; | |
1025 | data[1] = GUC_POWER_D0; | |
1026 | /* first page is shared data with GuC */ | |
1027 | data[2] = i915_gem_obj_ggtt_offset(ctx->engine[RCS].state); | |
1028 | ||
1029 | return host2guc_action(guc, data, ARRAY_SIZE(data)); | |
1030 | } |