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d330a953 JN |
1 | /* |
2 | * Copyright © 2014 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the | |
6 | * "Software"), to deal in the Software without restriction, including | |
7 | * without limitation the rights to use, copy, modify, merge, publish, | |
8 | * distribute, sub license, and/or sell copies of the Software, and to | |
9 | * permit persons to whom the Software is furnished to do so, subject to | |
10 | * the following conditions: | |
11 | * | |
12 | * The above copyright notice and this permission notice (including the | |
13 | * next paragraph) shall be included in all copies or substantial portions | |
14 | * of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
21 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
22 | * IN THE SOFTWARE. | |
23 | */ | |
24 | ||
c838d719 | 25 | #include "i915_params.h" |
d330a953 JN |
26 | #include "i915_drv.h" |
27 | ||
28 | struct i915_params i915 __read_mostly = { | |
29 | .modeset = -1, | |
30 | .panel_ignore_lid = 1, | |
d330a953 | 31 | .semaphores = -1, |
d330a953 JN |
32 | .lvds_channel_mode = 0, |
33 | .panel_use_ssc = -1, | |
34 | .vbt_sdvo_panel_type = -1, | |
35 | .enable_rc6 = -1, | |
443646c7 | 36 | .enable_dc = -1, |
d330a953 | 37 | .enable_fbc = -1, |
27401d12 | 38 | .enable_execlists = -1, |
d330a953 JN |
39 | .enable_hangcheck = true, |
40 | .enable_ppgtt = -1, | |
d94d6e87 | 41 | .enable_psr = -1, |
d330a953 | 42 | .preliminary_hw_support = IS_ENABLED(CONFIG_DRM_I915_PRELIMINARY_HW_SUPPORT), |
1b0e3a04 | 43 | .disable_power_well = -1, |
d330a953 | 44 | .enable_ips = 1, |
73831236 | 45 | .fastboot = 0, |
d330a953 | 46 | .prefault_disable = 0, |
5bedeb2d | 47 | .load_detect_test = 0, |
d330a953 JN |
48 | .reset = true, |
49 | .invert_brightness = 0, | |
a0bae57f | 50 | .disable_display = 0, |
5c411bb1 | 51 | .enable_cmd_parser = 1, |
84c33a64 | 52 | .use_mmio_flip = 0, |
5978118c | 53 | .mmio_debug = 0, |
e2c719b7 | 54 | .verbose_state_checks = 1, |
c5b852f3 | 55 | .nuclear_pageflip = 0, |
9e458034 | 56 | .edp_vswing = 0, |
63dc0449 AD |
57 | .enable_guc_submission = false, |
58 | .guc_log_level = -1, | |
7cc96139 | 59 | .enable_dp_mst = true, |
4fec15d1 | 60 | .inject_load_failure = 0, |
d330a953 JN |
61 | }; |
62 | ||
63 | module_param_named(modeset, i915.modeset, int, 0400); | |
64 | MODULE_PARM_DESC(modeset, | |
bf13af56 | 65 | "Use kernel modesetting [KMS] (0=disable, " |
d330a953 JN |
66 | "1=on, -1=force vga console preference [default])"); |
67 | ||
25e1793f | 68 | module_param_named_unsafe(panel_ignore_lid, i915.panel_ignore_lid, int, 0600); |
d330a953 JN |
69 | MODULE_PARM_DESC(panel_ignore_lid, |
70 | "Override lid status (0=autodetect, 1=autodetect disabled [default], " | |
71 | "-1=force lid closed, -2=force lid open)"); | |
72 | ||
fc9740ce | 73 | module_param_named_unsafe(semaphores, i915.semaphores, int, 0400); |
d330a953 JN |
74 | MODULE_PARM_DESC(semaphores, |
75 | "Use semaphores for inter-ring sync " | |
76 | "(default: -1 (use per-chip defaults))"); | |
77 | ||
fc9740ce | 78 | module_param_named_unsafe(enable_rc6, i915.enable_rc6, int, 0400); |
3adee7a7 | 79 | MODULE_PARM_DESC(enable_rc6, |
d330a953 JN |
80 | "Enable power-saving render C-state 6. " |
81 | "Different stages can be selected via bitmask values " | |
82 | "(0 = disable; 1 = enable rc6; 2 = enable deep rc6; 4 = enable deepest rc6). " | |
83 | "For example, 3 would enable rc6 and deep rc6, and 7 would enable everything. " | |
84 | "default: -1 (use per-chip default)"); | |
85 | ||
443646c7 PJ |
86 | module_param_named_unsafe(enable_dc, i915.enable_dc, int, 0400); |
87 | MODULE_PARM_DESC(enable_dc, | |
88 | "Enable power-saving display C-states. " | |
89 | "(-1=auto [default]; 0=disable; 1=up to DC5; 2=up to DC6)"); | |
90 | ||
fc9740ce | 91 | module_param_named_unsafe(enable_fbc, i915.enable_fbc, int, 0600); |
3adee7a7 | 92 | MODULE_PARM_DESC(enable_fbc, |
d330a953 JN |
93 | "Enable frame buffer compression for power savings " |
94 | "(default: -1 (use per-chip default))"); | |
95 | ||
57b63d00 | 96 | module_param_named_unsafe(lvds_channel_mode, i915.lvds_channel_mode, int, 0400); |
d330a953 JN |
97 | MODULE_PARM_DESC(lvds_channel_mode, |
98 | "Specify LVDS channel mode " | |
99 | "(0=probe BIOS [default], 1=single-channel, 2=dual-channel)"); | |
100 | ||
25e1793f | 101 | module_param_named_unsafe(lvds_use_ssc, i915.panel_use_ssc, int, 0600); |
d330a953 JN |
102 | MODULE_PARM_DESC(lvds_use_ssc, |
103 | "Use Spread Spectrum Clock with panels [LVDS/eDP] " | |
104 | "(default: auto from VBT)"); | |
105 | ||
57b63d00 | 106 | module_param_named_unsafe(vbt_sdvo_panel_type, i915.vbt_sdvo_panel_type, int, 0400); |
d330a953 JN |
107 | MODULE_PARM_DESC(vbt_sdvo_panel_type, |
108 | "Override/Ignore selection of SDVO panel mode in the VBT " | |
109 | "(-2=ignore, -1=auto [default], index in VBT BIOS table)"); | |
110 | ||
b1330fbb | 111 | module_param_named_unsafe(reset, i915.reset, bool, 0600); |
d330a953 JN |
112 | MODULE_PARM_DESC(reset, "Attempt GPU resets (default: true)"); |
113 | ||
25e1793f | 114 | module_param_named_unsafe(enable_hangcheck, i915.enable_hangcheck, bool, 0644); |
d330a953 JN |
115 | MODULE_PARM_DESC(enable_hangcheck, |
116 | "Periodically check GPU activity for detecting hangs. " | |
117 | "WARNING: Disabling this can cause system wide hangs. " | |
118 | "(default: true)"); | |
119 | ||
fc9740ce | 120 | module_param_named_unsafe(enable_ppgtt, i915.enable_ppgtt, int, 0400); |
3adee7a7 | 121 | MODULE_PARM_DESC(enable_ppgtt, |
d330a953 | 122 | "Override PPGTT usage. " |
1f9a99e0 | 123 | "(-1=auto [default], 0=disabled, 1=aliasing, 2=full, 3=full with extended address space)"); |
d330a953 | 124 | |
25e1793f | 125 | module_param_named_unsafe(enable_execlists, i915.enable_execlists, int, 0400); |
127f1003 OM |
126 | MODULE_PARM_DESC(enable_execlists, |
127 | "Override execlists usage. " | |
27401d12 | 128 | "(-1=auto [default], 0=disabled, 1=enabled)"); |
127f1003 | 129 | |
25e1793f | 130 | module_param_named_unsafe(enable_psr, i915.enable_psr, int, 0600); |
65f61b42 | 131 | MODULE_PARM_DESC(enable_psr, "Enable PSR " |
d94d6e87 RV |
132 | "(0=disabled, 1=enabled - link mode chosen per-platform, 2=force link-standby mode, 3=force link-off mode) " |
133 | "Default: -1 (use per-chip default)"); | |
d330a953 | 134 | |
57b63d00 | 135 | module_param_named_unsafe(preliminary_hw_support, i915.preliminary_hw_support, int, 0400); |
d330a953 JN |
136 | MODULE_PARM_DESC(preliminary_hw_support, |
137 | "Enable preliminary hardware support."); | |
138 | ||
d314cd43 | 139 | module_param_named_unsafe(disable_power_well, i915.disable_power_well, int, 0400); |
d330a953 | 140 | MODULE_PARM_DESC(disable_power_well, |
1b0e3a04 ID |
141 | "Disable display power wells when possible " |
142 | "(-1=auto [default], 0=power wells always on, 1=power wells disabled when possible)"); | |
d330a953 | 143 | |
25e1793f | 144 | module_param_named_unsafe(enable_ips, i915.enable_ips, int, 0600); |
d330a953 JN |
145 | MODULE_PARM_DESC(enable_ips, "Enable IPS (default: true)"); |
146 | ||
73831236 JN |
147 | module_param_named(fastboot, i915.fastboot, bool, 0600); |
148 | MODULE_PARM_DESC(fastboot, | |
149 | "Try to skip unnecessary mode sets at boot time (default: false)"); | |
150 | ||
5bedeb2d | 151 | module_param_named_unsafe(prefault_disable, i915.prefault_disable, bool, 0600); |
d330a953 JN |
152 | MODULE_PARM_DESC(prefault_disable, |
153 | "Disable page prefaulting for pread/pwrite/reloc (default:false). " | |
154 | "For developers only."); | |
155 | ||
5bedeb2d DV |
156 | module_param_named_unsafe(load_detect_test, i915.load_detect_test, bool, 0600); |
157 | MODULE_PARM_DESC(load_detect_test, | |
158 | "Force-enable the VGA load detect code for testing (default:false). " | |
159 | "For developers only."); | |
160 | ||
25e1793f | 161 | module_param_named_unsafe(invert_brightness, i915.invert_brightness, int, 0600); |
d330a953 JN |
162 | MODULE_PARM_DESC(invert_brightness, |
163 | "Invert backlight brightness " | |
164 | "(-1 force normal, 0 machine defaults, 1 force inversion), please " | |
165 | "report PCI device ID, subsystem vendor and subsystem device ID " | |
166 | "to dri-devel@lists.freedesktop.org, if your machine needs it. " | |
167 | "It will then be included in an upcoming module version."); | |
a0bae57f | 168 | |
57b63d00 | 169 | module_param_named(disable_display, i915.disable_display, bool, 0400); |
a0bae57f | 170 | MODULE_PARM_DESC(disable_display, "Disable display (default: false)"); |
351e3db2 | 171 | |
25e1793f | 172 | module_param_named_unsafe(enable_cmd_parser, i915.enable_cmd_parser, int, 0600); |
351e3db2 | 173 | MODULE_PARM_DESC(enable_cmd_parser, |
5c411bb1 | 174 | "Enable command parsing (1=enabled [default], 0=disabled)"); |
84c33a64 | 175 | |
25e1793f | 176 | module_param_named_unsafe(use_mmio_flip, i915.use_mmio_flip, int, 0600); |
84c33a64 SG |
177 | MODULE_PARM_DESC(use_mmio_flip, |
178 | "use MMIO flips (-1=never, 0=driver discretion [default], 1=always)"); | |
5978118c | 179 | |
48572edd | 180 | module_param_named(mmio_debug, i915.mmio_debug, int, 0600); |
5978118c | 181 | MODULE_PARM_DESC(mmio_debug, |
48572edd CW |
182 | "Enable the MMIO debug code for the first N failures (default: off). " |
183 | "This may negatively affect performance."); | |
e2c719b7 RC |
184 | |
185 | module_param_named(verbose_state_checks, i915.verbose_state_checks, bool, 0600); | |
186 | MODULE_PARM_DESC(verbose_state_checks, | |
187 | "Enable verbose logs (ie. WARN_ON()) in case of unexpected hw state conditions."); | |
b2e7723b | 188 | |
c5b852f3 ML |
189 | module_param_named_unsafe(nuclear_pageflip, i915.nuclear_pageflip, bool, 0600); |
190 | MODULE_PARM_DESC(nuclear_pageflip, | |
191 | "Force atomic modeset functionality; asynchronous mode is not yet supported. (default: false)."); | |
192 | ||
9e458034 SJ |
193 | /* WA to get away with the default setting in VBT for early platforms.Will be removed */ |
194 | module_param_named_unsafe(edp_vswing, i915.edp_vswing, int, 0400); | |
195 | MODULE_PARM_DESC(edp_vswing, | |
196 | "Ignore/Override vswing pre-emph table selection from VBT " | |
197 | "(0=use value from vbt [default], 1=low power swing(200mV)," | |
198 | "2=default swing(400mV))"); | |
63dc0449 AD |
199 | |
200 | module_param_named_unsafe(enable_guc_submission, i915.enable_guc_submission, bool, 0400); | |
201 | MODULE_PARM_DESC(enable_guc_submission, "Enable GuC submission (default:false)"); | |
202 | ||
203 | module_param_named(guc_log_level, i915.guc_log_level, int, 0400); | |
204 | MODULE_PARM_DESC(guc_log_level, | |
205 | "GuC firmware logging level (-1:disabled (default), 0-3:enabled)"); | |
7cc96139 NS |
206 | |
207 | module_param_named_unsafe(enable_dp_mst, i915.enable_dp_mst, bool, 0600); | |
208 | MODULE_PARM_DESC(enable_dp_mst, | |
209 | "Enable multi-stream transport (MST) for new DisplayPort sinks. (default: true)"); | |
4fec15d1 ID |
210 | module_param_named_unsafe(inject_load_failure, i915.inject_load_failure, uint, 0400); |
211 | MODULE_PARM_DESC(inject_load_failure, | |
212 | "Force an error after a number of failure check points (0:disabled (default), N:force failure at the Nth failure check point)"); |