[deliverable/linux.git] / drivers / gpu / drm / i915 / i915_sysfs.c

/*
 * Copyright © 2012 Intel Corporation
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice (including the next
 * paragraph) shall be included in all copies or substantial portions of the
 * Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
 * IN THE SOFTWARE.
 *
 * Authors:
 *    Ben Widawsky <ben@bwidawsk.net>
 *
 */

#include <linux/device.h>
#include <linux/module.h>
#include <linux/stat.h>
#include <linux/sysfs.h>
#include "intel_drv.h"
#include "i915_drv.h"

#ifdef CONFIG_PM
static u32 calc_residency(struct drm_device *dev, const u32 reg)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	u64 raw_time; /* 32b value may overflow during fixed point math */

	if (!intel_enable_rc6(dev))
		return 0;

	raw_time = I915_READ(reg) * 128ULL;
	return DIV_ROUND_UP_ULL(raw_time, 100000);
}

static ssize_t
show_rc6_mask(struct device *kdev, struct device_attribute *attr, char *buf)
{
	struct drm_minor *dminor = container_of(kdev, struct drm_minor, kdev);
	return snprintf(buf, PAGE_SIZE, "%x\n", intel_enable_rc6(dminor->dev));
}

static ssize_t
show_rc6_ms(struct device *kdev, struct device_attribute *attr, char *buf)
{
	struct drm_minor *dminor = container_of(kdev, struct drm_minor, kdev);
	u32 rc6_residency = calc_residency(dminor->dev, GEN6_GT_GFX_RC6);
	return snprintf(buf, PAGE_SIZE, "%u\n", rc6_residency);
}

static ssize_t
show_rc6p_ms(struct device *kdev, struct device_attribute *attr, char *buf)
{
	struct drm_minor *dminor = container_of(kdev, struct drm_minor, kdev);
	u32 rc6p_residency = calc_residency(dminor->dev, GEN6_GT_GFX_RC6p);
	return snprintf(buf, PAGE_SIZE, "%u\n", rc6p_residency);
}

static ssize_t
show_rc6pp_ms(struct device *kdev, struct device_attribute *attr, char *buf)
{
	struct drm_minor *dminor = container_of(kdev, struct drm_minor, kdev);
	u32 rc6pp_residency = calc_residency(dminor->dev, GEN6_GT_GFX_RC6pp);
	return snprintf(buf, PAGE_SIZE, "%u\n", rc6pp_residency);
}

static DEVICE_ATTR(rc6_enable, S_IRUGO, show_rc6_mask, NULL);
static DEVICE_ATTR(rc6_residency_ms, S_IRUGO, show_rc6_ms, NULL);
static DEVICE_ATTR(rc6p_residency_ms, S_IRUGO, show_rc6p_ms, NULL);
static DEVICE_ATTR(rc6pp_residency_ms, S_IRUGO, show_rc6pp_ms, NULL);

static struct attribute *rc6_attrs[] = {
	&dev_attr_rc6_enable.attr,
	&dev_attr_rc6_residency_ms.attr,
	&dev_attr_rc6p_residency_ms.attr,
	&dev_attr_rc6pp_residency_ms.attr,
	NULL
};

static struct attribute_group rc6_attr_group = {
	.name = power_group_name,
	.attrs =  rc6_attrs
};
#endif

static int l3_access_valid(struct drm_device *dev, loff_t offset)
{
	if (!HAS_L3_GPU_CACHE(dev))
		return -EPERM;

	if (offset % 4 != 0)
		return -EINVAL;

	if (offset >= GEN7_L3LOG_SIZE)
		return -ENXIO;

	return 0;
}

static ssize_t
i915_l3_read(struct file *filp, struct kobject *kobj,
	     struct bin_attribute *attr, char *buf,
	     loff_t offset, size_t count)
{
	struct device *dev = container_of(kobj, struct device, kobj);
	struct drm_minor *dminor = container_of(dev, struct drm_minor, kdev);
	struct drm_device *drm_dev = dminor->dev;
	struct drm_i915_private *dev_priv = drm_dev->dev_private;
	uint32_t misccpctl;
	int i, ret;

	ret = l3_access_valid(drm_dev, offset);
	if (ret)
		return ret;

	ret = i915_mutex_lock_interruptible(drm_dev);
	if (ret)
		return ret;

	misccpctl = I915_READ(GEN7_MISCCPCTL);
	I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);

	for (i = offset; count >= 4 && i < GEN7_L3LOG_SIZE; i += 4, count -= 4)
		*((uint32_t *)(&buf[i])) = I915_READ(GEN7_L3LOG_BASE + i);

	I915_WRITE(GEN7_MISCCPCTL, misccpctl);

	mutex_unlock(&drm_dev->struct_mutex);

	return i - offset;
}

static ssize_t
i915_l3_write(struct file *filp, struct kobject *kobj,
	      struct bin_attribute *attr, char *buf,
	      loff_t offset, size_t count)
{
	struct device *dev = container_of(kobj, struct device, kobj);
	struct drm_minor *dminor = container_of(dev, struct drm_minor, kdev);
	struct drm_device *drm_dev = dminor->dev;
	struct drm_i915_private *dev_priv = drm_dev->dev_private;
	u32 *temp = NULL; /* Just here to make handling failures easy */
	int ret;

	ret = l3_access_valid(drm_dev, offset);
	if (ret)
		return ret;

	ret = i915_mutex_lock_interruptible(drm_dev);
	if (ret)
		return ret;

	if (!dev_priv->l3_parity.remap_info) {
		temp = kzalloc(GEN7_L3LOG_SIZE, GFP_KERNEL);
		if (!temp) {
			mutex_unlock(&drm_dev->struct_mutex);
			return -ENOMEM;
		}
	}

	ret = i915_gpu_idle(drm_dev);
	if (ret) {
		kfree(temp);
		mutex_unlock(&drm_dev->struct_mutex);
		return ret;
	}

	/* TODO: Ideally we really want a GPU reset here to make sure errors
	 * aren't propagated. Since I cannot find a stable way to reset the GPU
	 * at this point it is left as a TODO.
	*/
	if (temp)
		dev_priv->l3_parity.remap_info = temp;

	memcpy(dev_priv->l3_parity.remap_info + (offset/4),
	       buf + (offset/4),
	       count);

	i915_gem_l3_remap(drm_dev);

	mutex_unlock(&drm_dev->struct_mutex);

	return count;
}

static struct bin_attribute dpf_attrs = {
	.attr = {.name = "l3_parity", .mode = (S_IRUSR | S_IWUSR)},
	.size = GEN7_L3LOG_SIZE,
	.read = i915_l3_read,
	.write = i915_l3_write,
	.mmap = NULL
};

static ssize_t gt_cur_freq_mhz_show(struct device *kdev,
				    struct device_attribute *attr, char *buf)
{
	struct drm_minor *minor = container_of(kdev, struct drm_minor, kdev);
	struct drm_device *dev = minor->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	int ret;

	mutex_lock(&dev_priv->rps.hw_lock);
	ret = dev_priv->rps.cur_delay * GT_FREQUENCY_MULTIPLIER;
	mutex_unlock(&dev_priv->rps.hw_lock);

	return snprintf(buf, PAGE_SIZE, "%d\n", ret);
}

static ssize_t gt_max_freq_mhz_show(struct device *kdev, struct device_attribute *attr, char *buf)
{
	struct drm_minor *minor = container_of(kdev, struct drm_minor, kdev);
	struct drm_device *dev = minor->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	int ret;

	mutex_lock(&dev_priv->rps.hw_lock);
	ret = dev_priv->rps.max_delay * GT_FREQUENCY_MULTIPLIER;
	mutex_unlock(&dev_priv->rps.hw_lock);

	return snprintf(buf, PAGE_SIZE, "%d\n", ret);
}

static ssize_t gt_max_freq_mhz_store(struct device *kdev,
				     struct device_attribute *attr,
				     const char *buf, size_t count)
{
	struct drm_minor *minor = container_of(kdev, struct drm_minor, kdev);
	struct drm_device *dev = minor->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	u32 val, rp_state_cap, hw_max, hw_min;
	ssize_t ret;

	ret = kstrtou32(buf, 0, &val);
	if (ret)
		return ret;

	val /= GT_FREQUENCY_MULTIPLIER;

	mutex_lock(&dev_priv->rps.hw_lock);

	rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
	hw_max = (rp_state_cap & 0xff);
	hw_min = ((rp_state_cap & 0xff0000) >> 16);

	if (val < hw_min || val > hw_max || val < dev_priv->rps.min_delay) {
		mutex_unlock(&dev_priv->rps.hw_lock);
		return -EINVAL;
	}

	if (dev_priv->rps.cur_delay > val)
		gen6_set_rps(dev_priv->dev, val);

	dev_priv->rps.max_delay = val;

	mutex_unlock(&dev_priv->rps.hw_lock);

	return count;
}

static ssize_t gt_min_freq_mhz_show(struct device *kdev, struct device_attribute *attr, char *buf)
{
	struct drm_minor *minor = container_of(kdev, struct drm_minor, kdev);
	struct drm_device *dev = minor->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	int ret;

	mutex_lock(&dev_priv->rps.hw_lock);
	ret = dev_priv->rps.min_delay * GT_FREQUENCY_MULTIPLIER;
	mutex_unlock(&dev_priv->rps.hw_lock);

	return snprintf(buf, PAGE_SIZE, "%d\n", ret);
}

static ssize_t gt_min_freq_mhz_store(struct device *kdev,
				     struct device_attribute *attr,
				     const char *buf, size_t count)
{
	struct drm_minor *minor = container_of(kdev, struct drm_minor, kdev);
	struct drm_device *dev = minor->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	u32 val, rp_state_cap, hw_max, hw_min;
	ssize_t ret;

	ret = kstrtou32(buf, 0, &val);
	if (ret)
		return ret;

	val /= GT_FREQUENCY_MULTIPLIER;

	mutex_lock(&dev_priv->rps.hw_lock);

	rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
	hw_max = (rp_state_cap & 0xff);
	hw_min = ((rp_state_cap & 0xff0000) >> 16);

	if (val < hw_min || val > hw_max || val > dev_priv->rps.max_delay) {
		mutex_unlock(&dev_priv->rps.hw_lock);
		return -EINVAL;
	}

	if (dev_priv->rps.cur_delay < val)
		gen6_set_rps(dev_priv->dev, val);

	dev_priv->rps.min_delay = val;

	mutex_unlock(&dev_priv->rps.hw_lock);

	return count;

}

static DEVICE_ATTR(gt_cur_freq_mhz, S_IRUGO, gt_cur_freq_mhz_show, NULL);
static DEVICE_ATTR(gt_max_freq_mhz, S_IRUGO | S_IWUSR, gt_max_freq_mhz_show, gt_max_freq_mhz_store);
static DEVICE_ATTR(gt_min_freq_mhz, S_IRUGO | S_IWUSR, gt_min_freq_mhz_show, gt_min_freq_mhz_store);


static ssize_t gt_rp_mhz_show(struct device *kdev, struct device_attribute *attr, char *buf);
static DEVICE_ATTR(gt_RP0_freq_mhz, S_IRUGO, gt_rp_mhz_show, NULL);
static DEVICE_ATTR(gt_RP1_freq_mhz, S_IRUGO, gt_rp_mhz_show, NULL);
static DEVICE_ATTR(gt_RPn_freq_mhz, S_IRUGO, gt_rp_mhz_show, NULL);

/* For now we have a static number of RP states */
static ssize_t gt_rp_mhz_show(struct device *kdev, struct device_attribute *attr, char *buf)
{
	struct drm_minor *minor = container_of(kdev, struct drm_minor, kdev);
	struct drm_device *dev = minor->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	u32 val, rp_state_cap;
	ssize_t ret;

	ret = mutex_lock_interruptible(&dev->struct_mutex);
	if (ret)
		return ret;
	rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
	mutex_unlock(&dev->struct_mutex);

	if (attr == &dev_attr_gt_RP0_freq_mhz) {
		val = ((rp_state_cap & 0x0000ff) >> 0) * GT_FREQUENCY_MULTIPLIER;
	} else if (attr == &dev_attr_gt_RP1_freq_mhz) {
		val = ((rp_state_cap & 0x00ff00) >> 8) * GT_FREQUENCY_MULTIPLIER;
	} else if (attr == &dev_attr_gt_RPn_freq_mhz) {
		val = ((rp_state_cap & 0xff0000) >> 16) * GT_FREQUENCY_MULTIPLIER;
	} else {
		BUG();
	}
	return snprintf(buf, PAGE_SIZE, "%d\n", val);
}

static const struct attribute *gen6_attrs[] = {
	&dev_attr_gt_cur_freq_mhz.attr,
	&dev_attr_gt_max_freq_mhz.attr,
	&dev_attr_gt_min_freq_mhz.attr,
	&dev_attr_gt_RP0_freq_mhz.attr,
	&dev_attr_gt_RP1_freq_mhz.attr,
	&dev_attr_gt_RPn_freq_mhz.attr,
	NULL,
};

void i915_setup_sysfs(struct drm_device *dev)
{
	int ret;

#ifdef CONFIG_PM
	if (INTEL_INFO(dev)->gen >= 6) {
		ret = sysfs_merge_group(&dev->primary->kdev.kobj,
					&rc6_attr_group);
		if (ret)
			DRM_ERROR("RC6 residency sysfs setup failed\n");
	}
#endif
	if (HAS_L3_GPU_CACHE(dev)) {
		ret = device_create_bin_file(&dev->primary->kdev, &dpf_attrs);
		if (ret)
			DRM_ERROR("l3 parity sysfs setup failed\n");
	}

	if (INTEL_INFO(dev)->gen >= 6) {
		ret = sysfs_create_files(&dev->primary->kdev.kobj, gen6_attrs);
		if (ret)
			DRM_ERROR("gen6 sysfs setup failed\n");
	}
}

void i915_teardown_sysfs(struct drm_device *dev)
{
	sysfs_remove_files(&dev->primary->kdev.kobj, gen6_attrs);
	device_remove_bin_file(&dev->primary->kdev,  &dpf_attrs);
#ifdef CONFIG_PM
	sysfs_unmerge_group(&dev->primary->kdev.kobj, &rc6_attr_group);
#endif
}
Commit	Line	Data
0136db58 BW	1	/*
	2	* Copyright © 2012 Intel Corporation
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice (including the next
	12	* paragraph) shall be included in all copies or substantial portions of the
	13	* Software.
	14	*
	15	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	16	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	17	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	18	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	19	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
	20	* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
	21	* IN THE SOFTWARE.
	22	*
	23	* Authors:
	24	* Ben Widawsky <ben@bwidawsk.net>
	25	*
	26	*/
	27
	28	#include <linux/device.h>
	29	#include <linux/module.h>
	30	#include <linux/stat.h>
	31	#include <linux/sysfs.h>
84bc7581	32	#include "intel_drv.h"
0136db58 BW	33	#include "i915_drv.h"
0136db58 BW	34
5ab3633d	35	#ifdef CONFIG_PM
0136db58 BW	36	static u32 calc_residency(struct drm_device *dev, const u32 reg)
	37	{
	38	struct drm_i915_private *dev_priv = dev->dev_private;
	39	u64 raw_time; /* 32b value may overflow during fixed point math */
	40
	41	if (!intel_enable_rc6(dev))
	42	return 0;
	43
a85d4bcb BW	44	raw_time = I915_READ(reg) * 128ULL;
a85d4bcb BW	45	return DIV_ROUND_UP_ULL(raw_time, 100000);
0136db58 BW	46	}
	47
	48	static ssize_t
dbdfd8e9	49	show_rc6_mask(struct device kdev, struct device_attribute attr, char *buf)
0136db58	50	{
dbdfd8e9	51	struct drm_minor *dminor = container_of(kdev, struct drm_minor, kdev);
3e2a1556	52	return snprintf(buf, PAGE_SIZE, "%x\n", intel_enable_rc6(dminor->dev));
0136db58 BW	53	}
	54
	55	static ssize_t
dbdfd8e9	56	show_rc6_ms(struct device kdev, struct device_attribute attr, char *buf)
0136db58	57	{
dbdfd8e9	58	struct drm_minor *dminor = container_of(kdev, struct drm_minor, kdev);
0136db58	59	u32 rc6_residency = calc_residency(dminor->dev, GEN6_GT_GFX_RC6);
3e2a1556	60	return snprintf(buf, PAGE_SIZE, "%u\n", rc6_residency);
0136db58 BW	61	}
	62
	63	static ssize_t
dbdfd8e9	64	show_rc6p_ms(struct device kdev, struct device_attribute attr, char *buf)
0136db58	65	{
dbdfd8e9	66	struct drm_minor *dminor = container_of(kdev, struct drm_minor, kdev);
0136db58	67	u32 rc6p_residency = calc_residency(dminor->dev, GEN6_GT_GFX_RC6p);
3e2a1556	68	return snprintf(buf, PAGE_SIZE, "%u\n", rc6p_residency);
0136db58 BW	69	}
	70
	71	static ssize_t
dbdfd8e9	72	show_rc6pp_ms(struct device kdev, struct device_attribute attr, char *buf)
0136db58	73	{
dbdfd8e9	74	struct drm_minor *dminor = container_of(kdev, struct drm_minor, kdev);
0136db58	75	u32 rc6pp_residency = calc_residency(dminor->dev, GEN6_GT_GFX_RC6pp);
3e2a1556	76	return snprintf(buf, PAGE_SIZE, "%u\n", rc6pp_residency);
0136db58 BW	77	}
	78
	79	static DEVICE_ATTR(rc6_enable, S_IRUGO, show_rc6_mask, NULL);
	80	static DEVICE_ATTR(rc6_residency_ms, S_IRUGO, show_rc6_ms, NULL);
	81	static DEVICE_ATTR(rc6p_residency_ms, S_IRUGO, show_rc6p_ms, NULL);
	82	static DEVICE_ATTR(rc6pp_residency_ms, S_IRUGO, show_rc6pp_ms, NULL);
	83
	84	static struct attribute *rc6_attrs[] = {
	85	&dev_attr_rc6_enable.attr,
	86	&dev_attr_rc6_residency_ms.attr,
	87	&dev_attr_rc6p_residency_ms.attr,
	88	&dev_attr_rc6pp_residency_ms.attr,
	89	NULL
	90	};
	91
	92	static struct attribute_group rc6_attr_group = {
	93	.name = power_group_name,
	94	.attrs = rc6_attrs
	95	};
8c3f929b	96	#endif
0136db58	97
84bc7581 BW	98	static int l3_access_valid(struct drm_device *dev, loff_t offset)
84bc7581 BW	99	{
ebf69cb8	100	if (!HAS_L3_GPU_CACHE(dev))
84bc7581 BW	101	return -EPERM;
	102
	103	if (offset % 4 != 0)
	104	return -EINVAL;
	105
	106	if (offset >= GEN7_L3LOG_SIZE)
	107	return -ENXIO;
	108
	109	return 0;
	110	}
	111
	112	static ssize_t
	113	i915_l3_read(struct file filp, struct kobject kobj,
	114	struct bin_attribute attr, char buf,
	115	loff_t offset, size_t count)
	116	{
	117	struct device *dev = container_of(kobj, struct device, kobj);
	118	struct drm_minor *dminor = container_of(dev, struct drm_minor, kdev);
	119	struct drm_device *drm_dev = dminor->dev;
	120	struct drm_i915_private *dev_priv = drm_dev->dev_private;
	121	uint32_t misccpctl;
	122	int i, ret;
	123
	124	ret = l3_access_valid(drm_dev, offset);
	125	if (ret)
	126	return ret;
	127
	128	ret = i915_mutex_lock_interruptible(drm_dev);
	129	if (ret)
	130	return ret;
	131
	132	misccpctl = I915_READ(GEN7_MISCCPCTL);
	133	I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
	134
	135	for (i = offset; count >= 4 && i < GEN7_L3LOG_SIZE; i += 4, count -= 4)
	136	((uint32_t )(&buf[i])) = I915_READ(GEN7_L3LOG_BASE + i);
	137
	138	I915_WRITE(GEN7_MISCCPCTL, misccpctl);
	139
	140	mutex_unlock(&drm_dev->struct_mutex);
	141
	142	return i - offset;
	143	}
	144
	145	static ssize_t
	146	i915_l3_write(struct file filp, struct kobject kobj,
	147	struct bin_attribute attr, char buf,
	148	loff_t offset, size_t count)
	149	{
	150	struct device *dev = container_of(kobj, struct device, kobj);
	151	struct drm_minor *dminor = container_of(dev, struct drm_minor, kdev);
	152	struct drm_device *drm_dev = dminor->dev;
	153	struct drm_i915_private *dev_priv = drm_dev->dev_private;
	154	u32 temp = NULL; / Just here to make handling failures easy */
	155	int ret;
	156
	157	ret = l3_access_valid(drm_dev, offset);
	158	if (ret)
	159	return ret;
	160
	161	ret = i915_mutex_lock_interruptible(drm_dev);
	162	if (ret)
	163	return ret;
	164
a4da4fa4	165	if (!dev_priv->l3_parity.remap_info) {
84bc7581 BW	166	temp = kzalloc(GEN7_L3LOG_SIZE, GFP_KERNEL);
	167	if (!temp) {
	168	mutex_unlock(&drm_dev->struct_mutex);
	169	return -ENOMEM;
	170	}
	171	}
	172
	173	ret = i915_gpu_idle(drm_dev);
	174	if (ret) {
	175	kfree(temp);
	176	mutex_unlock(&drm_dev->struct_mutex);
	177	return ret;
	178	}
	179
	180	/* TODO: Ideally we really want a GPU reset here to make sure errors
	181	* aren't propagated. Since I cannot find a stable way to reset the GPU
	182	* at this point it is left as a TODO.
	183	*/
	184	if (temp)
a4da4fa4	185	dev_priv->l3_parity.remap_info = temp;
84bc7581	186
a4da4fa4	187	memcpy(dev_priv->l3_parity.remap_info + (offset/4),
84bc7581 BW	188	buf + (offset/4),
	189	count);
	190
	191	i915_gem_l3_remap(drm_dev);
	192
	193	mutex_unlock(&drm_dev->struct_mutex);
	194
	195	return count;
	196	}
	197
	198	static struct bin_attribute dpf_attrs = {
	199	.attr = {.name = "l3_parity", .mode = (S_IRUSR \| S_IWUSR)},
	200	.size = GEN7_L3LOG_SIZE,
	201	.read = i915_l3_read,
	202	.write = i915_l3_write,
	203	.mmap = NULL
	204	};
	205
df6eedc8 BW	206	static ssize_t gt_cur_freq_mhz_show(struct device *kdev,
	207	struct device_attribute attr, char buf)
	208	{
	209	struct drm_minor *minor = container_of(kdev, struct drm_minor, kdev);
	210	struct drm_device *dev = minor->dev;
	211	struct drm_i915_private *dev_priv = dev->dev_private;
	212	int ret;
	213
4fc688ce	214	mutex_lock(&dev_priv->rps.hw_lock);
df6eedc8	215	ret = dev_priv->rps.cur_delay * GT_FREQUENCY_MULTIPLIER;
4fc688ce	216	mutex_unlock(&dev_priv->rps.hw_lock);
df6eedc8	217
3e2a1556	218	return snprintf(buf, PAGE_SIZE, "%d\n", ret);
df6eedc8 BW	219	}
	220
	221	static ssize_t gt_max_freq_mhz_show(struct device kdev, struct device_attribute attr, char *buf)
	222	{
	223	struct drm_minor *minor = container_of(kdev, struct drm_minor, kdev);
	224	struct drm_device *dev = minor->dev;
	225	struct drm_i915_private *dev_priv = dev->dev_private;
	226	int ret;
	227
4fc688ce	228	mutex_lock(&dev_priv->rps.hw_lock);
df6eedc8	229	ret = dev_priv->rps.max_delay * GT_FREQUENCY_MULTIPLIER;
4fc688ce	230	mutex_unlock(&dev_priv->rps.hw_lock);
df6eedc8	231
3e2a1556	232	return snprintf(buf, PAGE_SIZE, "%d\n", ret);
df6eedc8 BW	233	}
df6eedc8 BW	234
46ddf194 BW	235	static ssize_t gt_max_freq_mhz_store(struct device *kdev,
	236	struct device_attribute *attr,
	237	const char *buf, size_t count)
	238	{
	239	struct drm_minor *minor = container_of(kdev, struct drm_minor, kdev);
	240	struct drm_device *dev = minor->dev;
	241	struct drm_i915_private *dev_priv = dev->dev_private;
	242	u32 val, rp_state_cap, hw_max, hw_min;
	243	ssize_t ret;
	244
	245	ret = kstrtou32(buf, 0, &val);
	246	if (ret)
	247	return ret;
	248
	249	val /= GT_FREQUENCY_MULTIPLIER;
	250
4fc688ce	251	mutex_lock(&dev_priv->rps.hw_lock);
46ddf194 BW	252
	253	rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
	254	hw_max = (rp_state_cap & 0xff);
	255	hw_min = ((rp_state_cap & 0xff0000) >> 16);
	256
	257	if (val < hw_min \|\| val > hw_max \|\| val < dev_priv->rps.min_delay) {
4fc688ce	258	mutex_unlock(&dev_priv->rps.hw_lock);
46ddf194 BW	259	return -EINVAL;
	260	}
	261
	262	if (dev_priv->rps.cur_delay > val)
	263	gen6_set_rps(dev_priv->dev, val);
	264
	265	dev_priv->rps.max_delay = val;
	266
4fc688ce	267	mutex_unlock(&dev_priv->rps.hw_lock);
46ddf194 BW	268
	269	return count;
	270	}
	271
df6eedc8 BW	272	static ssize_t gt_min_freq_mhz_show(struct device kdev, struct device_attribute attr, char *buf)
	273	{
	274	struct drm_minor *minor = container_of(kdev, struct drm_minor, kdev);
	275	struct drm_device *dev = minor->dev;
	276	struct drm_i915_private *dev_priv = dev->dev_private;
	277	int ret;
	278
4fc688ce	279	mutex_lock(&dev_priv->rps.hw_lock);
df6eedc8	280	ret = dev_priv->rps.min_delay * GT_FREQUENCY_MULTIPLIER;
4fc688ce	281	mutex_unlock(&dev_priv->rps.hw_lock);
df6eedc8	282
3e2a1556	283	return snprintf(buf, PAGE_SIZE, "%d\n", ret);
df6eedc8 BW	284	}
df6eedc8 BW	285
46ddf194 BW	286	static ssize_t gt_min_freq_mhz_store(struct device *kdev,
	287	struct device_attribute *attr,
	288	const char *buf, size_t count)
	289	{
	290	struct drm_minor *minor = container_of(kdev, struct drm_minor, kdev);
	291	struct drm_device *dev = minor->dev;
	292	struct drm_i915_private *dev_priv = dev->dev_private;
	293	u32 val, rp_state_cap, hw_max, hw_min;
	294	ssize_t ret;
	295
	296	ret = kstrtou32(buf, 0, &val);
	297	if (ret)
	298	return ret;
	299
	300	val /= GT_FREQUENCY_MULTIPLIER;
	301
4fc688ce	302	mutex_lock(&dev_priv->rps.hw_lock);
46ddf194 BW	303
	304	rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
	305	hw_max = (rp_state_cap & 0xff);
	306	hw_min = ((rp_state_cap & 0xff0000) >> 16);
	307
	308	if (val < hw_min \|\| val > hw_max \|\| val > dev_priv->rps.max_delay) {
4fc688ce	309	mutex_unlock(&dev_priv->rps.hw_lock);
46ddf194 BW	310	return -EINVAL;
	311	}
	312
	313	if (dev_priv->rps.cur_delay < val)
	314	gen6_set_rps(dev_priv->dev, val);
	315
	316	dev_priv->rps.min_delay = val;
	317
4fc688ce	318	mutex_unlock(&dev_priv->rps.hw_lock);
46ddf194 BW	319
	320	return count;
	321
	322	}
	323
df6eedc8	324	static DEVICE_ATTR(gt_cur_freq_mhz, S_IRUGO, gt_cur_freq_mhz_show, NULL);
46ddf194 BW	325	static DEVICE_ATTR(gt_max_freq_mhz, S_IRUGO \| S_IWUSR, gt_max_freq_mhz_show, gt_max_freq_mhz_store);
46ddf194 BW	326	static DEVICE_ATTR(gt_min_freq_mhz, S_IRUGO \| S_IWUSR, gt_min_freq_mhz_show, gt_min_freq_mhz_store);
df6eedc8	327
ac6ae347 BW	328
	329	static ssize_t gt_rp_mhz_show(struct device kdev, struct device_attribute attr, char *buf);
	330	static DEVICE_ATTR(gt_RP0_freq_mhz, S_IRUGO, gt_rp_mhz_show, NULL);
	331	static DEVICE_ATTR(gt_RP1_freq_mhz, S_IRUGO, gt_rp_mhz_show, NULL);
	332	static DEVICE_ATTR(gt_RPn_freq_mhz, S_IRUGO, gt_rp_mhz_show, NULL);
	333
	334	/* For now we have a static number of RP states */
	335	static ssize_t gt_rp_mhz_show(struct device kdev, struct device_attribute attr, char *buf)
	336	{
	337	struct drm_minor *minor = container_of(kdev, struct drm_minor, kdev);
	338	struct drm_device *dev = minor->dev;
	339	struct drm_i915_private *dev_priv = dev->dev_private;
	340	u32 val, rp_state_cap;
	341	ssize_t ret;
	342
	343	ret = mutex_lock_interruptible(&dev->struct_mutex);
	344	if (ret)
	345	return ret;
	346	rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
	347	mutex_unlock(&dev->struct_mutex);
	348
	349	if (attr == &dev_attr_gt_RP0_freq_mhz) {
	350	val = ((rp_state_cap & 0x0000ff) >> 0) * GT_FREQUENCY_MULTIPLIER;
	351	} else if (attr == &dev_attr_gt_RP1_freq_mhz) {
	352	val = ((rp_state_cap & 0x00ff00) >> 8) * GT_FREQUENCY_MULTIPLIER;
	353	} else if (attr == &dev_attr_gt_RPn_freq_mhz) {
	354	val = ((rp_state_cap & 0xff0000) >> 16) * GT_FREQUENCY_MULTIPLIER;
	355	} else {
	356	BUG();
	357	}
3e2a1556	358	return snprintf(buf, PAGE_SIZE, "%d\n", val);
ac6ae347 BW	359	}
ac6ae347 BW	360
df6eedc8 BW	361	static const struct attribute *gen6_attrs[] = {
	362	&dev_attr_gt_cur_freq_mhz.attr,
	363	&dev_attr_gt_max_freq_mhz.attr,
	364	&dev_attr_gt_min_freq_mhz.attr,
ac6ae347 BW	365	&dev_attr_gt_RP0_freq_mhz.attr,
	366	&dev_attr_gt_RP1_freq_mhz.attr,
	367	&dev_attr_gt_RPn_freq_mhz.attr,
df6eedc8 BW	368	NULL,
	369	};
	370
0136db58 BW	371	void i915_setup_sysfs(struct drm_device *dev)
	372	{
	373	int ret;
	374
8c3f929b	375	#ifdef CONFIG_PM
112abd29 DV	376	if (INTEL_INFO(dev)->gen >= 6) {
	377	ret = sysfs_merge_group(&dev->primary->kdev.kobj,
	378	&rc6_attr_group);
	379	if (ret)
	380	DRM_ERROR("RC6 residency sysfs setup failed\n");
	381	}
8c3f929b	382	#endif
e1ef7cc2	383	if (HAS_L3_GPU_CACHE(dev)) {
112abd29 DV	384	ret = device_create_bin_file(&dev->primary->kdev, &dpf_attrs);
	385	if (ret)
	386	DRM_ERROR("l3 parity sysfs setup failed\n");
	387	}
df6eedc8 BW	388
	389	if (INTEL_INFO(dev)->gen >= 6) {
	390	ret = sysfs_create_files(&dev->primary->kdev.kobj, gen6_attrs);
	391	if (ret)
	392	DRM_ERROR("gen6 sysfs setup failed\n");
	393	}
0136db58 BW	394	}
	395
	396	void i915_teardown_sysfs(struct drm_device *dev)
	397	{
df6eedc8	398	sysfs_remove_files(&dev->primary->kdev.kobj, gen6_attrs);
84bc7581	399	device_remove_bin_file(&dev->primary->kdev, &dpf_attrs);
853c70e8	400	#ifdef CONFIG_PM
0136db58	401	sysfs_unmerge_group(&dev->primary->kdev.kobj, &rc6_attr_group);
853c70e8	402	#endif
0136db58	403	}