[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_audio.c

/*
 * Copyright © 2014 Intel Corporation
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice (including the next
 * paragraph) shall be included in all copies or substantial portions of the
 * Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
 * DEALINGS IN THE SOFTWARE.
 */

#include <linux/kernel.h>

#include <drm/drmP.h>
#include <drm/drm_edid.h>
#include "intel_drv.h"
#include "i915_drv.h"

static const struct {
	int clock;
	u32 config;
} hdmi_audio_clock[] = {
	{ DIV_ROUND_UP(25200 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_25175 },
	{ 25200, AUD_CONFIG_PIXEL_CLOCK_HDMI_25200 }, /* default per bspec */
	{ 27000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27000 },
	{ 27000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27027 },
	{ 54000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54000 },
	{ 54000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54054 },
	{ DIV_ROUND_UP(74250 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_74176 },
	{ 74250, AUD_CONFIG_PIXEL_CLOCK_HDMI_74250 },
	{ DIV_ROUND_UP(148500 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_148352 },
	{ 148500, AUD_CONFIG_PIXEL_CLOCK_HDMI_148500 },
};

/* get AUD_CONFIG_PIXEL_CLOCK_HDMI_* value for mode */
static u32 audio_config_hdmi_pixel_clock(struct drm_display_mode *mode)
{
	int i;

	for (i = 0; i < ARRAY_SIZE(hdmi_audio_clock); i++) {
		if (mode->clock == hdmi_audio_clock[i].clock)
			break;
	}

	if (i == ARRAY_SIZE(hdmi_audio_clock)) {
		DRM_DEBUG_KMS("HDMI audio pixel clock setting for %d not found, falling back to defaults\n", mode->clock);
		i = 1;
	}

	DRM_DEBUG_KMS("Configuring HDMI audio for pixel clock %d (0x%08x)\n",
		      hdmi_audio_clock[i].clock,
		      hdmi_audio_clock[i].config);

	return hdmi_audio_clock[i].config;
}

static bool intel_eld_uptodate(struct drm_connector *connector,
			       int reg_eldv, uint32_t bits_eldv,
			       int reg_elda, uint32_t bits_elda,
			       int reg_edid)
{
	struct drm_i915_private *dev_priv = connector->dev->dev_private;
	uint8_t *eld = connector->eld;
	uint32_t tmp;
	int i;

	tmp = I915_READ(reg_eldv);
	tmp &= bits_eldv;

	if (!tmp)
		return false;

	tmp = I915_READ(reg_elda);
	tmp &= ~bits_elda;
	I915_WRITE(reg_elda, tmp);

	for (i = 0; i < eld[2]; i++)
		if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
			return false;

	return true;
}

static void g4x_audio_codec_disable(struct intel_encoder *encoder)
{
	struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
	uint32_t eldv, tmp;

	DRM_DEBUG_KMS("Disable audio codec\n");

	tmp = I915_READ(G4X_AUD_VID_DID);
	if (tmp == INTEL_AUDIO_DEVBLC || tmp == INTEL_AUDIO_DEVCL)
		eldv = G4X_ELDV_DEVCL_DEVBLC;
	else
		eldv = G4X_ELDV_DEVCTG;

	/* Invalidate ELD */
	tmp = I915_READ(G4X_AUD_CNTL_ST);
	tmp &= ~eldv;
	I915_WRITE(G4X_AUD_CNTL_ST, tmp);
}

static void g4x_audio_codec_enable(struct drm_connector *connector,
				   struct intel_encoder *encoder,
				   struct drm_display_mode *mode)
{
	struct drm_i915_private *dev_priv = connector->dev->dev_private;
	uint8_t *eld = connector->eld;
	uint32_t eldv;
	uint32_t tmp;
	int len, i;

	DRM_DEBUG_KMS("Enable audio codec, %u bytes ELD\n", eld[2]);

	tmp = I915_READ(G4X_AUD_VID_DID);
	if (tmp == INTEL_AUDIO_DEVBLC || tmp == INTEL_AUDIO_DEVCL)
		eldv = G4X_ELDV_DEVCL_DEVBLC;
	else
		eldv = G4X_ELDV_DEVCTG;

	if (intel_eld_uptodate(connector,
			       G4X_AUD_CNTL_ST, eldv,
			       G4X_AUD_CNTL_ST, G4X_ELD_ADDR_MASK,
			       G4X_HDMIW_HDMIEDID))
		return;

	tmp = I915_READ(G4X_AUD_CNTL_ST);
	tmp &= ~(eldv | G4X_ELD_ADDR_MASK);
	len = (tmp >> 9) & 0x1f;		/* ELD buffer size */
	I915_WRITE(G4X_AUD_CNTL_ST, tmp);

	len = min_t(int, eld[2], len);
	DRM_DEBUG_DRIVER("ELD size %d\n", len);
	for (i = 0; i < len; i++)
		I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));

	tmp = I915_READ(G4X_AUD_CNTL_ST);
	tmp |= eldv;
	I915_WRITE(G4X_AUD_CNTL_ST, tmp);
}

static void hsw_audio_codec_disable(struct intel_encoder *encoder)
{
	struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
	enum pipe pipe = intel_crtc->pipe;
	uint32_t tmp;

	DRM_DEBUG_KMS("Disable audio codec on pipe %c\n", pipe_name(pipe));

	/* Disable timestamps */
	tmp = I915_READ(HSW_AUD_CFG(pipe));
	tmp &= ~AUD_CONFIG_N_VALUE_INDEX;
	tmp |= AUD_CONFIG_N_PROG_ENABLE;
	tmp &= ~AUD_CONFIG_UPPER_N_MASK;
	tmp &= ~AUD_CONFIG_LOWER_N_MASK;
	if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DISPLAYPORT))
		tmp |= AUD_CONFIG_N_VALUE_INDEX;
	I915_WRITE(HSW_AUD_CFG(pipe), tmp);

	/* Invalidate ELD */
	tmp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD);
	tmp &= ~(AUDIO_ELD_VALID_A << (pipe * 4));
	I915_WRITE(HSW_AUD_PIN_ELD_CP_VLD, tmp);
}

static void hsw_audio_codec_enable(struct drm_connector *connector,
				   struct intel_encoder *encoder,
				   struct drm_display_mode *mode)
{
	struct drm_i915_private *dev_priv = connector->dev->dev_private;
	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
	enum pipe pipe = intel_crtc->pipe;
	const uint8_t *eld = connector->eld;
	uint32_t tmp;
	int len, i;

	DRM_DEBUG_KMS("Enable audio codec on pipe %c, %u bytes ELD\n",
		      pipe_name(pipe), eld[2]);

	/* Enable audio presence detect, invalidate ELD */
	tmp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD);
	tmp |= AUDIO_OUTPUT_ENABLE_A << (pipe * 4);
	tmp &= ~(AUDIO_ELD_VALID_A << (pipe * 4));
	I915_WRITE(HSW_AUD_PIN_ELD_CP_VLD, tmp);

	/*
	 * FIXME: We're supposed to wait for vblank here, but we have vblanks
	 * disabled during the mode set. The proper fix would be to push the
	 * rest of the setup into a vblank work item, queued here, but the
	 * infrastructure is not there yet.
	 */

	/* Reset ELD write address */
	tmp = I915_READ(HSW_AUD_DIP_ELD_CTRL(pipe));
	tmp &= ~IBX_ELD_ADDRESS_MASK;
	I915_WRITE(HSW_AUD_DIP_ELD_CTRL(pipe), tmp);

	/* Up to 84 bytes of hw ELD buffer */
	len = min_t(int, eld[2], 21);
	for (i = 0; i < len; i++)
		I915_WRITE(HSW_AUD_EDID_DATA(pipe), *((uint32_t *)eld + i));

	/* ELD valid */
	tmp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD);
	tmp |= AUDIO_ELD_VALID_A << (pipe * 4);
	I915_WRITE(HSW_AUD_PIN_ELD_CP_VLD, tmp);

	/* Enable timestamps */
	tmp = I915_READ(HSW_AUD_CFG(pipe));
	tmp &= ~AUD_CONFIG_N_VALUE_INDEX;
	tmp &= ~AUD_CONFIG_N_PROG_ENABLE;
	tmp &= ~AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK;
	if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DISPLAYPORT))
		tmp |= AUD_CONFIG_N_VALUE_INDEX;
	else
		tmp |= audio_config_hdmi_pixel_clock(mode);
	I915_WRITE(HSW_AUD_CFG(pipe), tmp);
}

static void ilk_audio_codec_disable(struct intel_encoder *encoder)
{
	struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
	struct intel_digital_port *intel_dig_port =
		enc_to_dig_port(&encoder->base);
	enum port port = intel_dig_port->port;
	enum pipe pipe = intel_crtc->pipe;
	uint32_t tmp, eldv;
	int aud_config;
	int aud_cntrl_st2;

	DRM_DEBUG_KMS("Disable audio codec on port %c, pipe %c\n",
		      port_name(port), pipe_name(pipe));

	if (HAS_PCH_IBX(dev_priv->dev)) {
		aud_config = IBX_AUD_CFG(pipe);
		aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
	} else if (IS_VALLEYVIEW(dev_priv)) {
		aud_config = VLV_AUD_CFG(pipe);
		aud_cntrl_st2 = VLV_AUD_CNTL_ST2;
	} else {
		aud_config = CPT_AUD_CFG(pipe);
		aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
	}

	/* Disable timestamps */
	tmp = I915_READ(aud_config);
	tmp &= ~AUD_CONFIG_N_VALUE_INDEX;
	tmp |= AUD_CONFIG_N_PROG_ENABLE;
	tmp &= ~AUD_CONFIG_UPPER_N_MASK;
	tmp &= ~AUD_CONFIG_LOWER_N_MASK;
	if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DISPLAYPORT))
		tmp |= AUD_CONFIG_N_VALUE_INDEX;
	I915_WRITE(aud_config, tmp);

	if (WARN_ON(!port)) {
		eldv = IBX_ELD_VALIDB;
		eldv |= IBX_ELD_VALIDB << 4;
		eldv |= IBX_ELD_VALIDB << 8;
	} else {
		eldv = IBX_ELD_VALIDB << ((port - 1) * 4);
	}

	/* Invalidate ELD */
	tmp = I915_READ(aud_cntrl_st2);
	tmp &= ~eldv;
	I915_WRITE(aud_cntrl_st2, tmp);
}

static void ilk_audio_codec_enable(struct drm_connector *connector,
				   struct intel_encoder *encoder,
				   struct drm_display_mode *mode)
{
	struct drm_i915_private *dev_priv = connector->dev->dev_private;
	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
	struct intel_digital_port *intel_dig_port =
		enc_to_dig_port(&encoder->base);
	enum port port = intel_dig_port->port;
	enum pipe pipe = intel_crtc->pipe;
	uint8_t *eld = connector->eld;
	uint32_t eldv;
	uint32_t tmp;
	int len, i;
	int hdmiw_hdmiedid;
	int aud_config;
	int aud_cntl_st;
	int aud_cntrl_st2;

	DRM_DEBUG_KMS("Enable audio codec on port %c, pipe %c, %u bytes ELD\n",
		      port_name(port), pipe_name(pipe), eld[2]);

	/*
	 * FIXME: We're supposed to wait for vblank here, but we have vblanks
	 * disabled during the mode set. The proper fix would be to push the
	 * rest of the setup into a vblank work item, queued here, but the
	 * infrastructure is not there yet.
	 */

	if (HAS_PCH_IBX(connector->dev)) {
		hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
		aud_config = IBX_AUD_CFG(pipe);
		aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
		aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
	} else if (IS_VALLEYVIEW(connector->dev)) {
		hdmiw_hdmiedid = VLV_HDMIW_HDMIEDID(pipe);
		aud_config = VLV_AUD_CFG(pipe);
		aud_cntl_st = VLV_AUD_CNTL_ST(pipe);
		aud_cntrl_st2 = VLV_AUD_CNTL_ST2;
	} else {
		hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
		aud_config = CPT_AUD_CFG(pipe);
		aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
		aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
	}

	if (WARN_ON(!port)) {
		eldv = IBX_ELD_VALIDB;
		eldv |= IBX_ELD_VALIDB << 4;
		eldv |= IBX_ELD_VALIDB << 8;
	} else {
		eldv = IBX_ELD_VALIDB << ((port - 1) * 4);
	}

	/* Invalidate ELD */
	tmp = I915_READ(aud_cntrl_st2);
	tmp &= ~eldv;
	I915_WRITE(aud_cntrl_st2, tmp);

	/* Reset ELD write address */
	tmp = I915_READ(aud_cntl_st);
	tmp &= ~IBX_ELD_ADDRESS_MASK;
	I915_WRITE(aud_cntl_st, tmp);

	/* Up to 84 bytes of hw ELD buffer */
	len = min_t(int, eld[2], 21);
	for (i = 0; i < len; i++)
		I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));

	/* ELD valid */
	tmp = I915_READ(aud_cntrl_st2);
	tmp |= eldv;
	I915_WRITE(aud_cntrl_st2, tmp);

	/* Enable timestamps */
	tmp = I915_READ(aud_config);
	tmp &= ~AUD_CONFIG_N_VALUE_INDEX;
	tmp &= ~AUD_CONFIG_N_PROG_ENABLE;
	tmp &= ~AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK;
	if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DISPLAYPORT))
		tmp |= AUD_CONFIG_N_VALUE_INDEX;
	else
		tmp |= audio_config_hdmi_pixel_clock(mode);
	I915_WRITE(aud_config, tmp);
}

/**
 * intel_audio_codec_enable - Enable the audio codec for HD audio
 * @intel_encoder: encoder on which to enable audio
 *
 * The enable sequences may only be performed after enabling the transcoder and
 * port, and after completed link training.
 */
void intel_audio_codec_enable(struct intel_encoder *intel_encoder)
{
	struct drm_encoder *encoder = &intel_encoder->base;
	struct intel_crtc *crtc = to_intel_crtc(encoder->crtc);
	struct drm_display_mode *mode = &crtc->config.adjusted_mode;
	struct drm_connector *connector;
	struct drm_device *dev = encoder->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;

	connector = drm_select_eld(encoder, mode);
	if (!connector)
		return;

	DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
			 connector->base.id,
			 connector->name,
			 connector->encoder->base.id,
			 connector->encoder->name);

	/* ELD Conn_Type */
	connector->eld[5] &= ~(3 << 2);
	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
		connector->eld[5] |= (1 << 2);

	connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;

	if (dev_priv->display.audio_codec_enable)
		dev_priv->display.audio_codec_enable(connector, intel_encoder, mode);
}

/**
 * intel_audio_codec_disable - Disable the audio codec for HD audio
 * @encoder: encoder on which to disable audio
 *
 * The disable sequences must be performed before disabling the transcoder or
 * port.
 */
void intel_audio_codec_disable(struct intel_encoder *encoder)
{
	struct drm_device *dev = encoder->base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;

	if (dev_priv->display.audio_codec_disable)
		dev_priv->display.audio_codec_disable(encoder);
}

/**
 * intel_init_audio - Set up chip specific audio functions
 * @dev: drm device
 */
void intel_init_audio(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;

	if (IS_G4X(dev)) {
		dev_priv->display.audio_codec_enable = g4x_audio_codec_enable;
		dev_priv->display.audio_codec_disable = g4x_audio_codec_disable;
	} else if (IS_VALLEYVIEW(dev)) {
		dev_priv->display.audio_codec_enable = ilk_audio_codec_enable;
		dev_priv->display.audio_codec_disable = ilk_audio_codec_disable;
	} else if (IS_HASWELL(dev) || INTEL_INFO(dev)->gen >= 8) {
		dev_priv->display.audio_codec_enable = hsw_audio_codec_enable;
		dev_priv->display.audio_codec_disable = hsw_audio_codec_disable;
	} else if (HAS_PCH_SPLIT(dev)) {
		dev_priv->display.audio_codec_enable = ilk_audio_codec_enable;
		dev_priv->display.audio_codec_disable = ilk_audio_codec_disable;
	}
}
Commit	Line	Data
7c10a2b5 JN	1	/*
	2	* Copyright © 2014 Intel Corporation
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice (including the next
	12	* paragraph) shall be included in all copies or substantial portions of the
	13	* Software.
	14	*
	15	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	16	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	17	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	18	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	19	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
	20	* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
	21	* DEALINGS IN THE SOFTWARE.
	22	*/
	23
	24	#include <linux/kernel.h>
	25
	26	#include <drm/drmP.h>
	27	#include <drm/drm_edid.h>
	28	#include "intel_drv.h"
	29	#include "i915_drv.h"
	30
87fcb2ad	31	static const struct {
7c10a2b5 JN	32	int clock;
	33	u32 config;
	34	} hdmi_audio_clock[] = {
	35	{ DIV_ROUND_UP(25200 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_25175 },
	36	{ 25200, AUD_CONFIG_PIXEL_CLOCK_HDMI_25200 }, /* default per bspec */
	37	{ 27000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27000 },
	38	{ 27000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27027 },
	39	{ 54000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54000 },
	40	{ 54000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54054 },
	41	{ DIV_ROUND_UP(74250 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_74176 },
	42	{ 74250, AUD_CONFIG_PIXEL_CLOCK_HDMI_74250 },
	43	{ DIV_ROUND_UP(148500 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_148352 },
	44	{ 148500, AUD_CONFIG_PIXEL_CLOCK_HDMI_148500 },
	45	};
	46
	47	/* get AUD_CONFIG_PIXEL_CLOCK_HDMI_* value for mode */
	48	static u32 audio_config_hdmi_pixel_clock(struct drm_display_mode *mode)
	49	{
	50	int i;
	51
	52	for (i = 0; i < ARRAY_SIZE(hdmi_audio_clock); i++) {
	53	if (mode->clock == hdmi_audio_clock[i].clock)
	54	break;
	55	}
	56
	57	if (i == ARRAY_SIZE(hdmi_audio_clock)) {
	58	DRM_DEBUG_KMS("HDMI audio pixel clock setting for %d not found, falling back to defaults\n", mode->clock);
	59	i = 1;
	60	}
	61
	62	DRM_DEBUG_KMS("Configuring HDMI audio for pixel clock %d (0x%08x)\n",
	63	hdmi_audio_clock[i].clock,
	64	hdmi_audio_clock[i].config);
	65
	66	return hdmi_audio_clock[i].config;
	67	}
	68
	69	static bool intel_eld_uptodate(struct drm_connector *connector,
	70	int reg_eldv, uint32_t bits_eldv,
	71	int reg_elda, uint32_t bits_elda,
	72	int reg_edid)
	73	{
	74	struct drm_i915_private *dev_priv = connector->dev->dev_private;
	75	uint8_t *eld = connector->eld;
f9f682ae JN	76	uint32_t tmp;
f9f682ae JN	77	int i;
7c10a2b5	78
f9f682ae JN	79	tmp = I915_READ(reg_eldv);
f9f682ae JN	80	tmp &= bits_eldv;
7c10a2b5	81
f9f682ae	82	if (!tmp)
7c10a2b5 JN	83	return false;
7c10a2b5 JN	84
f9f682ae JN	85	tmp = I915_READ(reg_elda);
	86	tmp &= ~bits_elda;
	87	I915_WRITE(reg_elda, tmp);
7c10a2b5 JN	88
	89	for (i = 0; i < eld[2]; i++)
	90	if (I915_READ(reg_edid) != ((uint32_t )eld + i))
	91	return false;
	92
	93	return true;
	94	}
	95
76d8d3e5 JN	96	static void g4x_audio_codec_disable(struct intel_encoder *encoder)
	97	{
	98	struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
	99	uint32_t eldv, tmp;
	100
	101	DRM_DEBUG_KMS("Disable audio codec\n");
	102
	103	tmp = I915_READ(G4X_AUD_VID_DID);
	104	if (tmp == INTEL_AUDIO_DEVBLC \|\| tmp == INTEL_AUDIO_DEVCL)
	105	eldv = G4X_ELDV_DEVCL_DEVBLC;
	106	else
	107	eldv = G4X_ELDV_DEVCTG;
	108
	109	/* Invalidate ELD */
	110	tmp = I915_READ(G4X_AUD_CNTL_ST);
	111	tmp &= ~eldv;
	112	I915_WRITE(G4X_AUD_CNTL_ST, tmp);
	113	}
	114
69bfe1a9 JN	115	static void g4x_audio_codec_enable(struct drm_connector *connector,
	116	struct intel_encoder *encoder,
	117	struct drm_display_mode *mode)
7c10a2b5 JN	118	{
	119	struct drm_i915_private *dev_priv = connector->dev->dev_private;
	120	uint8_t *eld = connector->eld;
	121	uint32_t eldv;
f9f682ae JN	122	uint32_t tmp;
f9f682ae JN	123	int len, i;
7c10a2b5	124
d5ee08de JN	125	DRM_DEBUG_KMS("Enable audio codec, %u bytes ELD\n", eld[2]);
d5ee08de JN	126
f9f682ae JN	127	tmp = I915_READ(G4X_AUD_VID_DID);
f9f682ae JN	128	if (tmp == INTEL_AUDIO_DEVBLC \|\| tmp == INTEL_AUDIO_DEVCL)
7c10a2b5 JN	129	eldv = G4X_ELDV_DEVCL_DEVBLC;
	130	else
	131	eldv = G4X_ELDV_DEVCTG;
	132
	133	if (intel_eld_uptodate(connector,
	134	G4X_AUD_CNTL_ST, eldv,
c46f111f	135	G4X_AUD_CNTL_ST, G4X_ELD_ADDR_MASK,
7c10a2b5 JN	136	G4X_HDMIW_HDMIEDID))
	137	return;
	138
f9f682ae	139	tmp = I915_READ(G4X_AUD_CNTL_ST);
c46f111f	140	tmp &= ~(eldv \| G4X_ELD_ADDR_MASK);
f9f682ae JN	141	len = (tmp >> 9) & 0x1f; /* ELD buffer size */
f9f682ae JN	142	I915_WRITE(G4X_AUD_CNTL_ST, tmp);
7c10a2b5	143
f9f682ae	144	len = min_t(int, eld[2], len);
7c10a2b5 JN	145	DRM_DEBUG_DRIVER("ELD size %d\n", len);
	146	for (i = 0; i < len; i++)
	147	I915_WRITE(G4X_HDMIW_HDMIEDID, ((uint32_t )eld + i));
	148
f9f682ae JN	149	tmp = I915_READ(G4X_AUD_CNTL_ST);
	150	tmp \|= eldv;
	151	I915_WRITE(G4X_AUD_CNTL_ST, tmp);
7c10a2b5 JN	152	}
7c10a2b5 JN	153
69bfe1a9 JN	154	static void hsw_audio_codec_disable(struct intel_encoder *encoder)
69bfe1a9 JN	155	{
5fad84a7 JN	156	struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
	157	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
	158	enum pipe pipe = intel_crtc->pipe;
69bfe1a9 JN	159	uint32_t tmp;
69bfe1a9 JN	160
5fad84a7 JN	161	DRM_DEBUG_KMS("Disable audio codec on pipe %c\n", pipe_name(pipe));
	162
	163	/* Disable timestamps */
	164	tmp = I915_READ(HSW_AUD_CFG(pipe));
	165	tmp &= ~AUD_CONFIG_N_VALUE_INDEX;
	166	tmp \|= AUD_CONFIG_N_PROG_ENABLE;
	167	tmp &= ~AUD_CONFIG_UPPER_N_MASK;
	168	tmp &= ~AUD_CONFIG_LOWER_N_MASK;
	169	if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DISPLAYPORT))
	170	tmp \|= AUD_CONFIG_N_VALUE_INDEX;
	171	I915_WRITE(HSW_AUD_CFG(pipe), tmp);
	172
	173	/* Invalidate ELD */
69bfe1a9	174	tmp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD);
5fad84a7	175	tmp &= ~(AUDIO_ELD_VALID_A << (pipe * 4));
69bfe1a9 JN	176	I915_WRITE(HSW_AUD_PIN_ELD_CP_VLD, tmp);
	177	}
	178
	179	static void hsw_audio_codec_enable(struct drm_connector *connector,
	180	struct intel_encoder *encoder,
	181	struct drm_display_mode *mode)
7c10a2b5 JN	182	{
7c10a2b5 JN	183	struct drm_i915_private *dev_priv = connector->dev->dev_private;
820d2d77	184	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
5fad84a7 JN	185	enum pipe pipe = intel_crtc->pipe;
5fad84a7 JN	186	const uint8_t *eld = connector->eld;
f9f682ae JN	187	uint32_t tmp;
f9f682ae JN	188	int len, i;
7c10a2b5	189
5fad84a7 JN	190	DRM_DEBUG_KMS("Enable audio codec on pipe %c, %u bytes ELD\n",
5fad84a7 JN	191	pipe_name(pipe), eld[2]);
7c10a2b5	192
5fad84a7 JN	193	/* Enable audio presence detect, invalidate ELD */
	194	tmp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD);
	195	tmp \|= AUDIO_OUTPUT_ENABLE_A << (pipe * 4);
	196	tmp &= ~(AUDIO_ELD_VALID_A << (pipe * 4));
	197	I915_WRITE(HSW_AUD_PIN_ELD_CP_VLD, tmp);
7c10a2b5	198
5fad84a7 JN	199	/*
	200	* FIXME: We're supposed to wait for vblank here, but we have vblanks
	201	* disabled during the mode set. The proper fix would be to push the
	202	* rest of the setup into a vblank work item, queued here, but the
	203	* infrastructure is not there yet.
	204	*/
7c10a2b5	205
5fad84a7 JN	206	/* Reset ELD write address */
5fad84a7 JN	207	tmp = I915_READ(HSW_AUD_DIP_ELD_CTRL(pipe));
c46f111f	208	tmp &= ~IBX_ELD_ADDRESS_MASK;
5fad84a7	209	I915_WRITE(HSW_AUD_DIP_ELD_CTRL(pipe), tmp);
7c10a2b5	210
5fad84a7 JN	211	/* Up to 84 bytes of hw ELD buffer */
5fad84a7 JN	212	len = min_t(int, eld[2], 21);
7c10a2b5	213	for (i = 0; i < len; i++)
5fad84a7	214	I915_WRITE(HSW_AUD_EDID_DATA(pipe), ((uint32_t )eld + i));
7c10a2b5	215
5fad84a7	216	/* ELD valid */
69bfe1a9	217	tmp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD);
5fad84a7	218	tmp \|= AUDIO_ELD_VALID_A << (pipe * 4);
69bfe1a9	219	I915_WRITE(HSW_AUD_PIN_ELD_CP_VLD, tmp);
5fad84a7 JN	220
	221	/* Enable timestamps */
	222	tmp = I915_READ(HSW_AUD_CFG(pipe));
	223	tmp &= ~AUD_CONFIG_N_VALUE_INDEX;
	224	tmp &= ~AUD_CONFIG_N_PROG_ENABLE;
	225	tmp &= ~AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK;
	226	if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DISPLAYPORT))
	227	tmp \|= AUD_CONFIG_N_VALUE_INDEX;
	228	else
	229	tmp \|= audio_config_hdmi_pixel_clock(mode);
	230	I915_WRITE(HSW_AUD_CFG(pipe), tmp);
7c10a2b5 JN	231	}
7c10a2b5 JN	232
495a5bb8 JN	233	static void ilk_audio_codec_disable(struct intel_encoder *encoder)
	234	{
	235	struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
	236	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
	237	struct intel_digital_port *intel_dig_port =
	238	enc_to_dig_port(&encoder->base);
	239	enum port port = intel_dig_port->port;
	240	enum pipe pipe = intel_crtc->pipe;
	241	uint32_t tmp, eldv;
	242	int aud_config;
	243	int aud_cntrl_st2;
	244
	245	DRM_DEBUG_KMS("Disable audio codec on port %c, pipe %c\n",
	246	port_name(port), pipe_name(pipe));
	247
	248	if (HAS_PCH_IBX(dev_priv->dev)) {
	249	aud_config = IBX_AUD_CFG(pipe);
	250	aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
	251	} else if (IS_VALLEYVIEW(dev_priv)) {
	252	aud_config = VLV_AUD_CFG(pipe);
	253	aud_cntrl_st2 = VLV_AUD_CNTL_ST2;
	254	} else {
	255	aud_config = CPT_AUD_CFG(pipe);
	256	aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
	257	}
	258
	259	/* Disable timestamps */
	260	tmp = I915_READ(aud_config);
	261	tmp &= ~AUD_CONFIG_N_VALUE_INDEX;
	262	tmp \|= AUD_CONFIG_N_PROG_ENABLE;
	263	tmp &= ~AUD_CONFIG_UPPER_N_MASK;
	264	tmp &= ~AUD_CONFIG_LOWER_N_MASK;
	265	if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DISPLAYPORT))
	266	tmp \|= AUD_CONFIG_N_VALUE_INDEX;
	267	I915_WRITE(aud_config, tmp);
	268
	269	if (WARN_ON(!port)) {
	270	eldv = IBX_ELD_VALIDB;
	271	eldv \|= IBX_ELD_VALIDB << 4;
	272	eldv \|= IBX_ELD_VALIDB << 8;
	273	} else {
	274	eldv = IBX_ELD_VALIDB << ((port - 1) * 4);
	275	}
	276
	277	/* Invalidate ELD */
	278	tmp = I915_READ(aud_cntrl_st2);
	279	tmp &= ~eldv;
	280	I915_WRITE(aud_cntrl_st2, tmp);
	281	}
	282
69bfe1a9 JN	283	static void ilk_audio_codec_enable(struct drm_connector *connector,
	284	struct intel_encoder *encoder,
	285	struct drm_display_mode *mode)
7c10a2b5 JN	286	{
7c10a2b5 JN	287	struct drm_i915_private *dev_priv = connector->dev->dev_private;
820d2d77	288	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
c6bde93b JN	289	struct intel_digital_port *intel_dig_port =
	290	enc_to_dig_port(&encoder->base);
	291	enum port port = intel_dig_port->port;
	292	enum pipe pipe = intel_crtc->pipe;
7c10a2b5 JN	293	uint8_t *eld = connector->eld;
7c10a2b5 JN	294	uint32_t eldv;
f9f682ae JN	295	uint32_t tmp;
f9f682ae JN	296	int len, i;
7c10a2b5 JN	297	int hdmiw_hdmiedid;
	298	int aud_config;
	299	int aud_cntl_st;
	300	int aud_cntrl_st2;
c6bde93b JN	301
	302	DRM_DEBUG_KMS("Enable audio codec on port %c, pipe %c, %u bytes ELD\n",
	303	port_name(port), pipe_name(pipe), eld[2]);
	304
	305	/*
	306	* FIXME: We're supposed to wait for vblank here, but we have vblanks
	307	* disabled during the mode set. The proper fix would be to push the
	308	* rest of the setup into a vblank work item, queued here, but the
	309	* infrastructure is not there yet.
	310	*/
7c10a2b5 JN	311
	312	if (HAS_PCH_IBX(connector->dev)) {
	313	hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
	314	aud_config = IBX_AUD_CFG(pipe);
	315	aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
	316	aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
	317	} else if (IS_VALLEYVIEW(connector->dev)) {
	318	hdmiw_hdmiedid = VLV_HDMIW_HDMIEDID(pipe);
	319	aud_config = VLV_AUD_CFG(pipe);
	320	aud_cntl_st = VLV_AUD_CNTL_ST(pipe);
	321	aud_cntrl_st2 = VLV_AUD_CNTL_ST2;
	322	} else {
	323	hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
	324	aud_config = CPT_AUD_CFG(pipe);
	325	aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
	326	aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
	327	}
	328
c6bde93b	329	if (WARN_ON(!port)) {
7c10a2b5 JN	330	eldv = IBX_ELD_VALIDB;
	331	eldv \|= IBX_ELD_VALIDB << 4;
	332	eldv \|= IBX_ELD_VALIDB << 8;
	333	} else {
f9f682ae	334	eldv = IBX_ELD_VALIDB << ((port - 1) * 4);
7c10a2b5 JN	335	}
7c10a2b5 JN	336
c6bde93b	337	/* Invalidate ELD */
f9f682ae JN	338	tmp = I915_READ(aud_cntrl_st2);
	339	tmp &= ~eldv;
	340	I915_WRITE(aud_cntrl_st2, tmp);
7c10a2b5	341
c6bde93b	342	/* Reset ELD write address */
f9f682ae	343	tmp = I915_READ(aud_cntl_st);
c46f111f	344	tmp &= ~IBX_ELD_ADDRESS_MASK;
f9f682ae	345	I915_WRITE(aud_cntl_st, tmp);
7c10a2b5	346
c6bde93b JN	347	/* Up to 84 bytes of hw ELD buffer */
c6bde93b JN	348	len = min_t(int, eld[2], 21);
7c10a2b5 JN	349	for (i = 0; i < len; i++)
	350	I915_WRITE(hdmiw_hdmiedid, ((uint32_t )eld + i));
	351
c6bde93b	352	/* ELD valid */
f9f682ae JN	353	tmp = I915_READ(aud_cntrl_st2);
	354	tmp \|= eldv;
	355	I915_WRITE(aud_cntrl_st2, tmp);
c6bde93b JN	356
	357	/* Enable timestamps */
	358	tmp = I915_READ(aud_config);
	359	tmp &= ~AUD_CONFIG_N_VALUE_INDEX;
	360	tmp &= ~AUD_CONFIG_N_PROG_ENABLE;
	361	tmp &= ~AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK;
	362	if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DISPLAYPORT))
	363	tmp \|= AUD_CONFIG_N_VALUE_INDEX;
	364	else
	365	tmp \|= audio_config_hdmi_pixel_clock(mode);
	366	I915_WRITE(aud_config, tmp);
7c10a2b5 JN	367	}
7c10a2b5 JN	368
69bfe1a9 JN	369	/**
	370	* intel_audio_codec_enable - Enable the audio codec for HD audio
	371	* @intel_encoder: encoder on which to enable audio
	372	*
	373	* The enable sequences may only be performed after enabling the transcoder and
	374	* port, and after completed link training.
	375	*/
	376	void intel_audio_codec_enable(struct intel_encoder *intel_encoder)
7c10a2b5	377	{
33d1e7c6 JN	378	struct drm_encoder *encoder = &intel_encoder->base;
	379	struct intel_crtc *crtc = to_intel_crtc(encoder->crtc);
	380	struct drm_display_mode *mode = &crtc->config.adjusted_mode;
7c10a2b5 JN	381	struct drm_connector *connector;
	382	struct drm_device *dev = encoder->dev;
	383	struct drm_i915_private *dev_priv = dev->dev_private;
	384
	385	connector = drm_select_eld(encoder, mode);
	386	if (!connector)
	387	return;
	388
	389	DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
	390	connector->base.id,
	391	connector->name,
	392	connector->encoder->base.id,
	393	connector->encoder->name);
	394
6189b036 JN	395	/* ELD Conn_Type */
	396	connector->eld[5] &= ~(3 << 2);
	397	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
	398	connector->eld[5] \|= (1 << 2);
	399
7c10a2b5 JN	400	connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
7c10a2b5 JN	401
69bfe1a9 JN	402	if (dev_priv->display.audio_codec_enable)
	403	dev_priv->display.audio_codec_enable(connector, intel_encoder, mode);
	404	}
	405
	406	/**
	407	* intel_audio_codec_disable - Disable the audio codec for HD audio
	408	* @encoder: encoder on which to disable audio
	409	*
	410	* The disable sequences must be performed before disabling the transcoder or
	411	* port.
	412	*/
	413	void intel_audio_codec_disable(struct intel_encoder *encoder)
	414	{
	415	struct drm_device *dev = encoder->base.dev;
	416	struct drm_i915_private *dev_priv = dev->dev_private;
	417
	418	if (dev_priv->display.audio_codec_disable)
	419	dev_priv->display.audio_codec_disable(encoder);
7c10a2b5 JN	420	}
	421
	422	/**
	423	* intel_init_audio - Set up chip specific audio functions
	424	* @dev: drm device
	425	*/
	426	void intel_init_audio(struct drm_device *dev)
	427	{
	428	struct drm_i915_private *dev_priv = dev->dev_private;
	429
69bfe1a9 JN	430	if (IS_G4X(dev)) {
69bfe1a9 JN	431	dev_priv->display.audio_codec_enable = g4x_audio_codec_enable;
76d8d3e5	432	dev_priv->display.audio_codec_disable = g4x_audio_codec_disable;
69bfe1a9 JN	433	} else if (IS_VALLEYVIEW(dev)) {
69bfe1a9 JN	434	dev_priv->display.audio_codec_enable = ilk_audio_codec_enable;
495a5bb8	435	dev_priv->display.audio_codec_disable = ilk_audio_codec_disable;
69bfe1a9 JN	436	} else if (IS_HASWELL(dev) \|\| INTEL_INFO(dev)->gen >= 8) {
	437	dev_priv->display.audio_codec_enable = hsw_audio_codec_enable;
	438	dev_priv->display.audio_codec_disable = hsw_audio_codec_disable;
	439	} else if (HAS_PCH_SPLIT(dev)) {
	440	dev_priv->display.audio_codec_enable = ilk_audio_codec_enable;
495a5bb8	441	dev_priv->display.audio_codec_disable = ilk_audio_codec_disable;
69bfe1a9	442	}
7c10a2b5	443	}