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ALSA: hda - display audio call sync_audio_rate callback
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_audio.c
CommitLineData
7c10a2b5
JN		 1/*
2 * Copyright © 2014 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 */
23
24#include <linux/kernel.h>
58fddc28
ID		 25#include <linux/component.h>
26#include <drm/i915_component.h>
27#include "intel_drv.h"
7c10a2b5
JN		 28
29#include <drm/drmP.h>
30#include <drm/drm_edid.h>
7c10a2b5
JN		 31#include "i915_drv.h"
32
28855d2a
JN		 33/**
34 * DOC: High Definition Audio over HDMI and Display Port
35 *
36 * The graphics and audio drivers together support High Definition Audio over
37 * HDMI and Display Port. The audio programming sequences are divided into audio
38 * codec and controller enable and disable sequences. The graphics driver
39 * handles the audio codec sequences, while the audio driver handles the audio
40 * controller sequences.
41 *
42 * The disable sequences must be performed before disabling the transcoder or
43 * port. The enable sequences may only be performed after enabling the
3e6da4a9
JN		 44 * transcoder and port, and after completed link training. Therefore the audio
45 * enable/disable sequences are part of the modeset sequence.
28855d2a
JN		 46 *
47 * The codec and controller sequences could be done either parallel or serial,
48 * but generally the ELDV/PD change in the codec sequence indicates to the audio
49 * driver that the controller sequence should start. Indeed, most of the
50 * co-operation between the graphics and audio drivers is handled via audio
51 * related registers. (The notable exception is the power management, not
52 * covered here.)
53 */
54
87fcb2ad 55static const struct {
7c10a2b5
JN		 56 int clock;
57 u32 config;
58} hdmi_audio_clock[] = {
59 { DIV_ROUND_UP(25200 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_25175 },
60 { 25200, AUD_CONFIG_PIXEL_CLOCK_HDMI_25200 }, /* default per bspec */
61 { 27000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27000 },
62 { 27000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27027 },
63 { 54000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54000 },
64 { 54000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54054 },
65 { DIV_ROUND_UP(74250 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_74176 },
66 { 74250, AUD_CONFIG_PIXEL_CLOCK_HDMI_74250 },
67 { DIV_ROUND_UP(148500 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_148352 },
68 { 148500, AUD_CONFIG_PIXEL_CLOCK_HDMI_148500 },
69};
70
4a21ef7d
LY		 71/* HDMI N/CTS table */
72#define TMDS_297M 297000
73#define TMDS_296M DIV_ROUND_UP(297000 * 1000, 1001)
74static const struct {
75 int sample_rate;
76 int clock;
77 int n;
78 int cts;
79} aud_ncts[] = {
80 { 44100, TMDS_296M, 4459, 234375 },
81 { 44100, TMDS_297M, 4704, 247500 },
82 { 48000, TMDS_296M, 5824, 281250 },
83 { 48000, TMDS_297M, 5120, 247500 },
84 { 32000, TMDS_296M, 5824, 421875 },
85 { 32000, TMDS_297M, 3072, 222750 },
86 { 88200, TMDS_296M, 8918, 234375 },
87 { 88200, TMDS_297M, 9408, 247500 },
88 { 96000, TMDS_296M, 11648, 281250 },
89 { 96000, TMDS_297M, 10240, 247500 },
90 { 176400, TMDS_296M, 17836, 234375 },
91 { 176400, TMDS_297M, 18816, 247500 },
92 { 192000, TMDS_296M, 23296, 281250 },
93 { 192000, TMDS_297M, 20480, 247500 },
94};
95
7c10a2b5
JN		 96/* get AUD_CONFIG_PIXEL_CLOCK_HDMI_* value for mode */
97static u32 audio_config_hdmi_pixel_clock(struct drm_display_mode *mode)
98{
99 int i;
100
101 for (i = 0; i < ARRAY_SIZE(hdmi_audio_clock); i++) {
102 if (mode->clock == hdmi_audio_clock[i].clock)
103 break;
104 }
105
106 if (i == ARRAY_SIZE(hdmi_audio_clock)) {
107 DRM_DEBUG_KMS("HDMI audio pixel clock setting for %d not found, falling back to defaults\n", mode->clock);
108 i = 1;
109 }
110
111 DRM_DEBUG_KMS("Configuring HDMI audio for pixel clock %d (0x%08x)\n",
112 hdmi_audio_clock[i].clock,
113 hdmi_audio_clock[i].config);
114
115 return hdmi_audio_clock[i].config;
116}
117
4a21ef7d
LY		 118static int audio_config_get_n(const struct drm_display_mode *mode, int rate)
119{
120 int i;
121
122 for (i = 0; i < ARRAY_SIZE(aud_ncts); i++) {
123 if ((rate == aud_ncts[i].sample_rate) &&
124 (mode->clock == aud_ncts[i].clock)) {
125 return aud_ncts[i].n;
126 }
127 }
128 return 0;
129}
130
131/* check whether N/CTS/M need be set manually */
132static bool audio_rate_need_prog(struct intel_crtc *crtc,
133 struct drm_display_mode *mode)
134{
135 if (((mode->clock == TMDS_297M) ||
136 (mode->clock == TMDS_296M)) &&
137 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
138 return true;
139 else
140 return false;
141}
142
7c10a2b5
JN		 143static bool intel_eld_uptodate(struct drm_connector *connector,
144 int reg_eldv, uint32_t bits_eldv,
145 int reg_elda, uint32_t bits_elda,
146 int reg_edid)
147{
148 struct drm_i915_private *dev_priv = connector->dev->dev_private;
149 uint8_t *eld = connector->eld;
f9f682ae
JN		 150 uint32_t tmp;
151 int i;
7c10a2b5 152
f9f682ae
JN		 153 tmp = I915_READ(reg_eldv);
154 tmp &= bits_eldv;
7c10a2b5 155
f9f682ae 156 if (!tmp)
7c10a2b5
JN		 157 return false;
158
f9f682ae
JN		 159 tmp = I915_READ(reg_elda);
160 tmp &= ~bits_elda;
161 I915_WRITE(reg_elda, tmp);
7c10a2b5 162
938fd8aa 163 for (i = 0; i < drm_eld_size(eld) / 4; i++)
7c10a2b5
JN		 164 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
165 return false;
166
167 return true;
168}
169
76d8d3e5
JN		 170static void g4x_audio_codec_disable(struct intel_encoder *encoder)
171{
172 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
173 uint32_t eldv, tmp;
174
175 DRM_DEBUG_KMS("Disable audio codec\n");
176
177 tmp = I915_READ(G4X_AUD_VID_DID);
178 if (tmp == INTEL_AUDIO_DEVBLC || tmp == INTEL_AUDIO_DEVCL)
179 eldv = G4X_ELDV_DEVCL_DEVBLC;
180 else
181 eldv = G4X_ELDV_DEVCTG;
182
183 /* Invalidate ELD */
184 tmp = I915_READ(G4X_AUD_CNTL_ST);
185 tmp &= ~eldv;
186 I915_WRITE(G4X_AUD_CNTL_ST, tmp);
187}
188
69bfe1a9
JN		 189static void g4x_audio_codec_enable(struct drm_connector *connector,
190 struct intel_encoder *encoder,
191 struct drm_display_mode *mode)
7c10a2b5
JN		 192{
193 struct drm_i915_private *dev_priv = connector->dev->dev_private;
194 uint8_t *eld = connector->eld;
195 uint32_t eldv;
f9f682ae
JN		 196 uint32_t tmp;
197 int len, i;
7c10a2b5 198
d5ee08de
JN		 199 DRM_DEBUG_KMS("Enable audio codec, %u bytes ELD\n", eld[2]);
200
f9f682ae
JN		 201 tmp = I915_READ(G4X_AUD_VID_DID);
202 if (tmp == INTEL_AUDIO_DEVBLC || tmp == INTEL_AUDIO_DEVCL)
7c10a2b5
JN		 203 eldv = G4X_ELDV_DEVCL_DEVBLC;
204 else
205 eldv = G4X_ELDV_DEVCTG;
206
207 if (intel_eld_uptodate(connector,
208 G4X_AUD_CNTL_ST, eldv,
c46f111f 209 G4X_AUD_CNTL_ST, G4X_ELD_ADDR_MASK,
7c10a2b5
JN		 210 G4X_HDMIW_HDMIEDID))
211 return;
212
f9f682ae 213 tmp = I915_READ(G4X_AUD_CNTL_ST);
c46f111f 214 tmp &= ~(eldv | G4X_ELD_ADDR_MASK);
f9f682ae
JN		 215 len = (tmp >> 9) & 0x1f; /* ELD buffer size */
216 I915_WRITE(G4X_AUD_CNTL_ST, tmp);
7c10a2b5 217
938fd8aa 218 len = min(drm_eld_size(eld) / 4, len);
7c10a2b5
JN		 219 DRM_DEBUG_DRIVER("ELD size %d\n", len);
220 for (i = 0; i < len; i++)
221 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
222
f9f682ae
JN		 223 tmp = I915_READ(G4X_AUD_CNTL_ST);
224 tmp |= eldv;
225 I915_WRITE(G4X_AUD_CNTL_ST, tmp);
7c10a2b5
JN		 226}
227
69bfe1a9
JN		 228static void hsw_audio_codec_disable(struct intel_encoder *encoder)
229{
5fad84a7
JN		 230 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
231 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
232 enum pipe pipe = intel_crtc->pipe;
69bfe1a9
JN		 233 uint32_t tmp;
234
5fad84a7
JN		 235 DRM_DEBUG_KMS("Disable audio codec on pipe %c\n", pipe_name(pipe));
236
4a21ef7d
LY		 237 mutex_lock(&dev_priv->av_mutex);
238
5fad84a7
JN		 239 /* Disable timestamps */
240 tmp = I915_READ(HSW_AUD_CFG(pipe));
241 tmp &= ~AUD_CONFIG_N_VALUE_INDEX;
242 tmp |= AUD_CONFIG_N_PROG_ENABLE;
243 tmp &= ~AUD_CONFIG_UPPER_N_MASK;
244 tmp &= ~AUD_CONFIG_LOWER_N_MASK;
245 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DISPLAYPORT))
246 tmp |= AUD_CONFIG_N_VALUE_INDEX;
247 I915_WRITE(HSW_AUD_CFG(pipe), tmp);
248
249 /* Invalidate ELD */
69bfe1a9 250 tmp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD);
82910ac6 251 tmp &= ~AUDIO_ELD_VALID(pipe);
eb45fa0b 252 tmp &= ~AUDIO_OUTPUT_ENABLE(pipe);
69bfe1a9 253 I915_WRITE(HSW_AUD_PIN_ELD_CP_VLD, tmp);
4a21ef7d
LY		 254
255 mutex_unlock(&dev_priv->av_mutex);
69bfe1a9
JN		 256}
257
258static void hsw_audio_codec_enable(struct drm_connector *connector,
259 struct intel_encoder *encoder,
260 struct drm_display_mode *mode)
7c10a2b5
JN		 261{
262 struct drm_i915_private *dev_priv = connector->dev->dev_private;
820d2d77 263 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
5fad84a7
JN		 264 enum pipe pipe = intel_crtc->pipe;
265 const uint8_t *eld = connector->eld;
f9f682ae
JN		 266 uint32_t tmp;
267 int len, i;
7c10a2b5 268
5fad84a7 269 DRM_DEBUG_KMS("Enable audio codec on pipe %c, %u bytes ELD\n",
938fd8aa 270 pipe_name(pipe), drm_eld_size(eld));
7c10a2b5 271
4a21ef7d
LY		 272 mutex_lock(&dev_priv->av_mutex);
273
5fad84a7
JN		 274 /* Enable audio presence detect, invalidate ELD */
275 tmp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD);
82910ac6
JN		 276 tmp |= AUDIO_OUTPUT_ENABLE(pipe);
277 tmp &= ~AUDIO_ELD_VALID(pipe);
5fad84a7 278 I915_WRITE(HSW_AUD_PIN_ELD_CP_VLD, tmp);
7c10a2b5 279
5fad84a7
JN		 280 /*
281 * FIXME: We're supposed to wait for vblank here, but we have vblanks
282 * disabled during the mode set. The proper fix would be to push the
283 * rest of the setup into a vblank work item, queued here, but the
284 * infrastructure is not there yet.
285 */
7c10a2b5 286
5fad84a7
JN		 287 /* Reset ELD write address */
288 tmp = I915_READ(HSW_AUD_DIP_ELD_CTRL(pipe));
c46f111f 289 tmp &= ~IBX_ELD_ADDRESS_MASK;
5fad84a7 290 I915_WRITE(HSW_AUD_DIP_ELD_CTRL(pipe), tmp);
7c10a2b5 291
5fad84a7 292 /* Up to 84 bytes of hw ELD buffer */
938fd8aa
JN		 293 len = min(drm_eld_size(eld), 84);
294 for (i = 0; i < len / 4; i++)
5fad84a7 295 I915_WRITE(HSW_AUD_EDID_DATA(pipe), *((uint32_t *)eld + i));
7c10a2b5 296
5fad84a7 297 /* ELD valid */
69bfe1a9 298 tmp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD);
82910ac6 299 tmp |= AUDIO_ELD_VALID(pipe);
69bfe1a9 300 I915_WRITE(HSW_AUD_PIN_ELD_CP_VLD, tmp);
5fad84a7
JN		 301
302 /* Enable timestamps */
303 tmp = I915_READ(HSW_AUD_CFG(pipe));
304 tmp &= ~AUD_CONFIG_N_VALUE_INDEX;
305 tmp &= ~AUD_CONFIG_N_PROG_ENABLE;
306 tmp &= ~AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK;
307 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DISPLAYPORT))
308 tmp |= AUD_CONFIG_N_VALUE_INDEX;
309 else
310 tmp |= audio_config_hdmi_pixel_clock(mode);
311 I915_WRITE(HSW_AUD_CFG(pipe), tmp);
4a21ef7d
LY		 312
313 mutex_unlock(&dev_priv->av_mutex);
7c10a2b5
JN		 314}
315
495a5bb8
JN		 316static void ilk_audio_codec_disable(struct intel_encoder *encoder)
317{
318 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
319 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
320 struct intel_digital_port *intel_dig_port =
321 enc_to_dig_port(&encoder->base);
322 enum port port = intel_dig_port->port;
323 enum pipe pipe = intel_crtc->pipe;
324 uint32_t tmp, eldv;
325 int aud_config;
326 int aud_cntrl_st2;
327
328 DRM_DEBUG_KMS("Disable audio codec on port %c, pipe %c\n",
329 port_name(port), pipe_name(pipe));
330
d3902c3e
JN		 331 if (WARN_ON(port == PORT_A))
332 return;
333
495a5bb8
JN		 334 if (HAS_PCH_IBX(dev_priv->dev)) {
335 aud_config = IBX_AUD_CFG(pipe);
336 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
337 } else if (IS_VALLEYVIEW(dev_priv)) {
338 aud_config = VLV_AUD_CFG(pipe);
339 aud_cntrl_st2 = VLV_AUD_CNTL_ST2;
340 } else {
341 aud_config = CPT_AUD_CFG(pipe);
342 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
343 }
344
345 /* Disable timestamps */
346 tmp = I915_READ(aud_config);
347 tmp &= ~AUD_CONFIG_N_VALUE_INDEX;
348 tmp |= AUD_CONFIG_N_PROG_ENABLE;
349 tmp &= ~AUD_CONFIG_UPPER_N_MASK;
350 tmp &= ~AUD_CONFIG_LOWER_N_MASK;
351 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DISPLAYPORT))
352 tmp |= AUD_CONFIG_N_VALUE_INDEX;
353 I915_WRITE(aud_config, tmp);
354
d3902c3e 355 eldv = IBX_ELD_VALID(port);
495a5bb8
JN		 356
357 /* Invalidate ELD */
358 tmp = I915_READ(aud_cntrl_st2);
359 tmp &= ~eldv;
360 I915_WRITE(aud_cntrl_st2, tmp);
361}
362
69bfe1a9
JN		 363static void ilk_audio_codec_enable(struct drm_connector *connector,
364 struct intel_encoder *encoder,
365 struct drm_display_mode *mode)
7c10a2b5
JN		 366{
367 struct drm_i915_private *dev_priv = connector->dev->dev_private;
820d2d77 368 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
c6bde93b
JN		 369 struct intel_digital_port *intel_dig_port =
370 enc_to_dig_port(&encoder->base);
371 enum port port = intel_dig_port->port;
372 enum pipe pipe = intel_crtc->pipe;
7c10a2b5
JN		 373 uint8_t *eld = connector->eld;
374 uint32_t eldv;
f9f682ae
JN		 375 uint32_t tmp;
376 int len, i;
7c10a2b5
JN		 377 int hdmiw_hdmiedid;
378 int aud_config;
379 int aud_cntl_st;
380 int aud_cntrl_st2;
c6bde93b
JN		 381
382 DRM_DEBUG_KMS("Enable audio codec on port %c, pipe %c, %u bytes ELD\n",
938fd8aa 383 port_name(port), pipe_name(pipe), drm_eld_size(eld));
c6bde93b 384
d3902c3e
JN		 385 if (WARN_ON(port == PORT_A))
386 return;
387
c6bde93b
JN		 388 /*
389 * FIXME: We're supposed to wait for vblank here, but we have vblanks
390 * disabled during the mode set. The proper fix would be to push the
391 * rest of the setup into a vblank work item, queued here, but the
392 * infrastructure is not there yet.
393 */
7c10a2b5
JN		 394
395 if (HAS_PCH_IBX(connector->dev)) {
396 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
397 aud_config = IBX_AUD_CFG(pipe);
398 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
399 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
400 } else if (IS_VALLEYVIEW(connector->dev)) {
401 hdmiw_hdmiedid = VLV_HDMIW_HDMIEDID(pipe);
402 aud_config = VLV_AUD_CFG(pipe);
403 aud_cntl_st = VLV_AUD_CNTL_ST(pipe);
404 aud_cntrl_st2 = VLV_AUD_CNTL_ST2;
405 } else {
406 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
407 aud_config = CPT_AUD_CFG(pipe);
408 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
409 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
410 }
411
d3902c3e 412 eldv = IBX_ELD_VALID(port);
7c10a2b5 413
c6bde93b 414 /* Invalidate ELD */
f9f682ae
JN		 415 tmp = I915_READ(aud_cntrl_st2);
416 tmp &= ~eldv;
417 I915_WRITE(aud_cntrl_st2, tmp);
7c10a2b5 418
c6bde93b 419 /* Reset ELD write address */
f9f682ae 420 tmp = I915_READ(aud_cntl_st);
c46f111f 421 tmp &= ~IBX_ELD_ADDRESS_MASK;
f9f682ae 422 I915_WRITE(aud_cntl_st, tmp);
7c10a2b5 423
c6bde93b 424 /* Up to 84 bytes of hw ELD buffer */
938fd8aa
JN		 425 len = min(drm_eld_size(eld), 84);
426 for (i = 0; i < len / 4; i++)
7c10a2b5
JN		 427 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
428
c6bde93b 429 /* ELD valid */
f9f682ae
JN		 430 tmp = I915_READ(aud_cntrl_st2);
431 tmp |= eldv;
432 I915_WRITE(aud_cntrl_st2, tmp);
c6bde93b
JN		 433
434 /* Enable timestamps */
435 tmp = I915_READ(aud_config);
436 tmp &= ~AUD_CONFIG_N_VALUE_INDEX;
437 tmp &= ~AUD_CONFIG_N_PROG_ENABLE;
438 tmp &= ~AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK;
439 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DISPLAYPORT))
440 tmp |= AUD_CONFIG_N_VALUE_INDEX;
441 else
442 tmp |= audio_config_hdmi_pixel_clock(mode);
443 I915_WRITE(aud_config, tmp);
7c10a2b5
JN		 444}
445
69bfe1a9
JN		 446/**
447 * intel_audio_codec_enable - Enable the audio codec for HD audio
448 * @intel_encoder: encoder on which to enable audio
449 *
450 * The enable sequences may only be performed after enabling the transcoder and
451 * port, and after completed link training.
452 */
453void intel_audio_codec_enable(struct intel_encoder *intel_encoder)
7c10a2b5 454{
33d1e7c6
JN		 455 struct drm_encoder *encoder = &intel_encoder->base;
456 struct intel_crtc *crtc = to_intel_crtc(encoder->crtc);
6e3c9717 457 struct drm_display_mode *mode = &crtc->config->base.adjusted_mode;
7c10a2b5
JN		 458 struct drm_connector *connector;
459 struct drm_device *dev = encoder->dev;
460 struct drm_i915_private *dev_priv = dev->dev_private;
51e1d83c
DH		 461 struct i915_audio_component *acomp = dev_priv->audio_component;
462 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
463 enum port port = intel_dig_port->port;
7c10a2b5
JN		 464
465 connector = drm_select_eld(encoder, mode);
466 if (!connector)
467 return;
468
469 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
470 connector->base.id,
471 connector->name,
472 connector->encoder->base.id,
473 connector->encoder->name);
474
6189b036
JN		 475 /* ELD Conn_Type */
476 connector->eld[5] &= ~(3 << 2);
477 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
478 connector->eld[5] |= (1 << 2);
479
7c10a2b5
JN		 480 connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
481
69bfe1a9
JN		 482 if (dev_priv->display.audio_codec_enable)
483 dev_priv->display.audio_codec_enable(connector, intel_encoder, mode);
51e1d83c
DH		 484
485 if (acomp && acomp->audio_ops && acomp->audio_ops->pin_eld_notify)
f0675d4a 486 acomp->audio_ops->pin_eld_notify(acomp->audio_ops->audio_ptr, (int) port);
69bfe1a9
JN		 487}
488
489/**
490 * intel_audio_codec_disable - Disable the audio codec for HD audio
491 * @encoder: encoder on which to disable audio
492 *
493 * The disable sequences must be performed before disabling the transcoder or
494 * port.
495 */
51e1d83c 496void intel_audio_codec_disable(struct intel_encoder *intel_encoder)
69bfe1a9 497{
51e1d83c
DH		 498 struct drm_encoder *encoder = &intel_encoder->base;
499 struct drm_device *dev = encoder->dev;
69bfe1a9 500 struct drm_i915_private *dev_priv = dev->dev_private;
51e1d83c
DH		 501 struct i915_audio_component *acomp = dev_priv->audio_component;
502 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
503 enum port port = intel_dig_port->port;
69bfe1a9
JN		 504
505 if (dev_priv->display.audio_codec_disable)
51e1d83c
DH		 506 dev_priv->display.audio_codec_disable(intel_encoder);
507
508 if (acomp && acomp->audio_ops && acomp->audio_ops->pin_eld_notify)
f0675d4a 509 acomp->audio_ops->pin_eld_notify(acomp->audio_ops->audio_ptr, (int) port);
7c10a2b5
JN		 510}
511
512/**
513 * intel_init_audio - Set up chip specific audio functions
514 * @dev: drm device
515 */
516void intel_init_audio(struct drm_device *dev)
517{
518 struct drm_i915_private *dev_priv = dev->dev_private;
519
69bfe1a9
JN		 520 if (IS_G4X(dev)) {
521 dev_priv->display.audio_codec_enable = g4x_audio_codec_enable;
76d8d3e5 522 dev_priv->display.audio_codec_disable = g4x_audio_codec_disable;
69bfe1a9
JN		 523 } else if (IS_VALLEYVIEW(dev)) {
524 dev_priv->display.audio_codec_enable = ilk_audio_codec_enable;
495a5bb8 525 dev_priv->display.audio_codec_disable = ilk_audio_codec_disable;
69bfe1a9
JN		 526 } else if (IS_HASWELL(dev) || INTEL_INFO(dev)->gen >= 8) {
527 dev_priv->display.audio_codec_enable = hsw_audio_codec_enable;
528 dev_priv->display.audio_codec_disable = hsw_audio_codec_disable;
529 } else if (HAS_PCH_SPLIT(dev)) {
530 dev_priv->display.audio_codec_enable = ilk_audio_codec_enable;
495a5bb8 531 dev_priv->display.audio_codec_disable = ilk_audio_codec_disable;
69bfe1a9 532 }
7c10a2b5 533}
58fddc28
ID		 534
535static void i915_audio_component_get_power(struct device *dev)
536{
537 intel_display_power_get(dev_to_i915(dev), POWER_DOMAIN_AUDIO);
538}
539
540static void i915_audio_component_put_power(struct device *dev)
541{
542 intel_display_power_put(dev_to_i915(dev), POWER_DOMAIN_AUDIO);
543}
544
632f3ab9
LH		 545static void i915_audio_component_codec_wake_override(struct device *dev,
546 bool enable)
547{
548 struct drm_i915_private *dev_priv = dev_to_i915(dev);
549 u32 tmp;
550
551 if (!IS_SKYLAKE(dev_priv))
552 return;
553
554 /*
555 * Enable/disable generating the codec wake signal, overriding the
556 * internal logic to generate the codec wake to controller.
557 */
558 tmp = I915_READ(HSW_AUD_CHICKENBIT);
559 tmp &= ~SKL_AUD_CODEC_WAKE_SIGNAL;
560 I915_WRITE(HSW_AUD_CHICKENBIT, tmp);
561 usleep_range(1000, 1500);
562
563 if (enable) {
564 tmp = I915_READ(HSW_AUD_CHICKENBIT);
565 tmp |= SKL_AUD_CODEC_WAKE_SIGNAL;
566 I915_WRITE(HSW_AUD_CHICKENBIT, tmp);
567 usleep_range(1000, 1500);
568 }
569}
570
58fddc28
ID		 571/* Get CDCLK in kHz */
572static int i915_audio_component_get_cdclk_freq(struct device *dev)
573{
574 struct drm_i915_private *dev_priv = dev_to_i915(dev);
575 int ret;
576
577 if (WARN_ON_ONCE(!HAS_DDI(dev_priv)))
578 return -ENODEV;
579
580 intel_display_power_get(dev_priv, POWER_DOMAIN_AUDIO);
1652d19e
VS		 581 ret = dev_priv->display.get_display_clock_speed(dev_priv->dev);
582
58fddc28
ID		 583 intel_display_power_put(dev_priv, POWER_DOMAIN_AUDIO);
584
585 return ret;
586}
587
4a21ef7d
LY		 588static int i915_audio_component_sync_audio_rate(struct device *dev,
589 int port, int rate)
590{
591 struct drm_i915_private *dev_priv = dev_to_i915(dev);
592 struct drm_device *drm_dev = dev_priv->dev;
593 struct intel_encoder *intel_encoder;
594 struct intel_digital_port *intel_dig_port;
595 struct intel_crtc *crtc;
596 struct drm_display_mode *mode;
597 enum pipe pipe = -1;
598 u32 tmp;
599 int n_low, n_up, n;
600
601 /* HSW, BDW SKL need this fix */
602 if (!IS_SKYLAKE(dev_priv) &&
603 !IS_BROADWELL(dev_priv) &&
604 !IS_HASWELL(dev_priv))
605 return 0;
606
607 mutex_lock(&dev_priv->av_mutex);
608 /* 1. get the pipe */
609 for_each_intel_encoder(drm_dev, intel_encoder) {
610 if (intel_encoder->type != INTEL_OUTPUT_HDMI)
611 continue;
612 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
613 if (port == intel_dig_port->port) {
614 crtc = to_intel_crtc(intel_encoder->base.crtc);
615 if (!crtc) {
616 DRM_DEBUG_KMS("%s: crtc is NULL\n", __func__);
617 continue;
618 }
619 pipe = crtc->pipe;
620 break;
621 }
622 }
623
624 if (pipe == INVALID_PIPE) {
625 DRM_DEBUG_KMS("no pipe for the port %c\n", port_name(port));
626 mutex_unlock(&dev_priv->av_mutex);
627 return -ENODEV;
628 }
629 DRM_DEBUG_KMS("pipe %c connects port %c\n",
630 pipe_name(pipe), port_name(port));
631 mode = &crtc->config->base.adjusted_mode;
632
633 /* 2. check whether to set the N/CTS/M manually or not */
634 if (!audio_rate_need_prog(crtc, mode)) {
635 tmp = I915_READ(HSW_AUD_CFG(pipe));
636 tmp &= ~AUD_CONFIG_N_PROG_ENABLE;
637 I915_WRITE(HSW_AUD_CFG(pipe), tmp);
638 mutex_unlock(&dev_priv->av_mutex);
639 return 0;
640 }
641
642 n = audio_config_get_n(mode, rate);
643 if (n == 0) {
644 DRM_DEBUG_KMS("Using automatic mode for N value on port %c\n",
645 port_name(port));
646 tmp = I915_READ(HSW_AUD_CFG(pipe));
647 tmp &= ~AUD_CONFIG_N_PROG_ENABLE;
648 I915_WRITE(HSW_AUD_CFG(pipe), tmp);
649 mutex_unlock(&dev_priv->av_mutex);
650 return 0;
651 }
652 n_low = n & 0xfff;
653 n_up = (n >> 12) & 0xff;
654
655 /* 4. set the N/CTS/M */
656 tmp = I915_READ(HSW_AUD_CFG(pipe));
657 tmp &= ~(AUD_CONFIG_UPPER_N_MASK | AUD_CONFIG_LOWER_N_MASK);
658 tmp |= ((n_up << AUD_CONFIG_UPPER_N_SHIFT) |
659 (n_low << AUD_CONFIG_LOWER_N_SHIFT) |
660 AUD_CONFIG_N_PROG_ENABLE);
661 I915_WRITE(HSW_AUD_CFG(pipe), tmp);
662
663 mutex_unlock(&dev_priv->av_mutex);
664 return 0;
665}
666
58fddc28
ID		 667static const struct i915_audio_component_ops i915_audio_component_ops = {
668 .owner = THIS_MODULE,
669 .get_power = i915_audio_component_get_power,
670 .put_power = i915_audio_component_put_power,
632f3ab9 671 .codec_wake_override = i915_audio_component_codec_wake_override,
58fddc28 672 .get_cdclk_freq = i915_audio_component_get_cdclk_freq,
4a21ef7d 673 .sync_audio_rate = i915_audio_component_sync_audio_rate,
58fddc28
ID		 674};
675
676static int i915_audio_component_bind(struct device *i915_dev,
677 struct device *hda_dev, void *data)
678{
679 struct i915_audio_component *acomp = data;
51e1d83c 680 struct drm_i915_private *dev_priv = dev_to_i915(i915_dev);
58fddc28
ID		 681
682 if (WARN_ON(acomp->ops || acomp->dev))
683 return -EEXIST;
684
d5f362a7 685 drm_modeset_lock_all(dev_priv->dev);
58fddc28
ID		 686 acomp->ops = &i915_audio_component_ops;
687 acomp->dev = i915_dev;
51e1d83c 688 dev_priv->audio_component = acomp;
d5f362a7 689 drm_modeset_unlock_all(dev_priv->dev);
58fddc28
ID		 690
691 return 0;
692}
693
694static void i915_audio_component_unbind(struct device *i915_dev,
695 struct device *hda_dev, void *data)
696{
697 struct i915_audio_component *acomp = data;
51e1d83c 698 struct drm_i915_private *dev_priv = dev_to_i915(i915_dev);
58fddc28 699
d5f362a7 700 drm_modeset_lock_all(dev_priv->dev);
58fddc28
ID		 701 acomp->ops = NULL;
702 acomp->dev = NULL;
51e1d83c 703 dev_priv->audio_component = NULL;
d5f362a7 704 drm_modeset_unlock_all(dev_priv->dev);
58fddc28
ID		 705}
706
707static const struct component_ops i915_audio_component_bind_ops = {
708 .bind = i915_audio_component_bind,
709 .unbind = i915_audio_component_unbind,
710};
711
712/**
713 * i915_audio_component_init - initialize and register the audio component
714 * @dev_priv: i915 device instance
715 *
716 * This will register with the component framework a child component which
717 * will bind dynamically to the snd_hda_intel driver's corresponding master
718 * component when the latter is registered. During binding the child
719 * initializes an instance of struct i915_audio_component which it receives
720 * from the master. The master can then start to use the interface defined by
721 * this struct. Each side can break the binding at any point by deregistering
722 * its own component after which each side's component unbind callback is
723 * called.
724 *
725 * We ignore any error during registration and continue with reduced
726 * functionality (i.e. without HDMI audio).
727 */
728void i915_audio_component_init(struct drm_i915_private *dev_priv)
729{
730 int ret;
731
732 ret = component_add(dev_priv->dev->dev, &i915_audio_component_bind_ops);
733 if (ret < 0) {
734 DRM_ERROR("failed to add audio component (%d)\n", ret);
735 /* continue with reduced functionality */
736 return;
737 }
738
739 dev_priv->audio_component_registered = true;
740}
741
742/**
743 * i915_audio_component_cleanup - deregister the audio component
744 * @dev_priv: i915 device instance
745 *
746 * Deregisters the audio component, breaking any existing binding to the
747 * corresponding snd_hda_intel driver's master component.
748 */
749void i915_audio_component_cleanup(struct drm_i915_private *dev_priv)
750{
751 if (!dev_priv->audio_component_registered)
752 return;
753
754 component_del(dev_priv->dev->dev, &i915_audio_component_bind_ops);
755 dev_priv->audio_component_registered = false;
756}
Linux kernel - Deliverables
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